Fairchild TMC2302A service manual
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TMC2302A
Image Manipulation Sequencer
40 MHz
Features
• Asynchronous loading of control parameters
• Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
• Three-dimensional image addressing capability
• General third-order polynomial transformations in two
dimensions on-chip
• Three-dimensional transformation of up to order 1.5 also
supported
• Flexible, user-configurable pixel datapath timing structure
• Static convolutional filtering of up to 16 x 16 Pixel (onepass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
• User-selectable source image subpixel resolution of
-8
-16
2
to 2
• Pin-compatible upgrade to TMC2302
• 24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
• Low power CMOS process
• A vailable in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
Applications
• High-performance video special-effects generators
• Guidance systems
• Image recognition
• Robotics
• High-precision image registration
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address generator which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipulation is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a twodimensional image, whereas three can second-order warp a
three-dimensional image.
Preliminary Information
Simplified Block Diagram
IDAT
15-0
IADR
ASYNCHRONOUS
HOST INTERFACE
SYNCHRONOUS
HOST INTERFACE
6-0
ICS
IWR
SYNC
NOOP
INIT
CLK
CONTROL
PARAMETER
REGISTERS
CONTROL
SOURCE
ADDRESS
GENERATOR
WALK
COUNTER
TARGET
ADDRESS
GENERATOR
65-2302-01
OES
SADR
SVAL
OEK
KADR
ACC
TWR
OET
TADR
TVAL
END
DONE
SOURCE MEMORY
23-0
7-0
11-0
INTERFACE
CONVOLUTIONAL
TARGET
MEMORY
INTERFACE
SYNC FLAGS
CONTROL
Rev. 0.9.2
TMC2302A PRODUCT SPECIFICATION
Description
(continued)
A system based on two TMC2302As can nearest-neighbor
resample a two-dimensional 512 x 512 pixel image in 6.5
milliseconds, translating, rotating, or warping it, depending
on the user-selected transformation parameters. A complete
bilinear interpolation of the sample image can be completed
in 26 milliseconds (or 6.5ms with a TMC2246A companion
chip), while a nearest-neighbor resampling of a 3D image
128 pixels on a side takes only 53 milliseconds with three
TMC2302As. Image resampling speed is independent of
angle of rotation, degree of warp, or amount of zoom specified.
Block Diagram
ASYNCHRONOUS
HOST INTERFACE
IDAT
15-0
IADR
6-0
ICS
IWR
SYNCHRONOUS
HOST INTERFACE
CONTROL
PARAMETER
AND ADDRESS
BUFFER
SOURCE
ADDRESS
GENERATOR
48-BITS
(47-24)
(23-12)
KERNEL WALK
ACCUMULATOR
The TMC2302A can process image data fields with up to 24
bits of binary resolution (2
24
pixels) per dimension, with 0 to
16-bit subpixel resolution.
Along with the original Plastic Pin Grid Array (PPGA)
package, the TMC2302A is offered in a 120-lead Metric
Quad FlatPack (MQFP) as well. All TMC2302 electrical,
functional, and environmental specifications are improved or
remain unchanged in the TMC2302A.
SOURCE MEMORY
OFFSET
24-BITS
WALK
COUNTER
8-BITS
COMPARATOR
(7-0)
BOUNDARY
36-BITS
CONVOLUTIONAL
TARGET MEMORY
INTERFACE
INTERFACE
SADR
OES
SVAL
CONTROL
KADR
OEK
ACC
TWR
23-0
7-0
NOOP
INT
CLK
SYNC
Preliminary Information
PROGRAMMABLE
DELAY
0 TO 7 CLOCKS
CONTROL
INTERNAL
CLOCK
TARGET
ADDRESS
GENERATOR
3 X 13-BITS
X(11-0)
Y(11-0)
Z(11-0)
3-D BOUNDARY
COMPARATOR
3 x 13 BITS
TADR
OET
TVAL
END
DONE
65-2302-02
11-0
2
PRODUCT SPECIFICATION TMC2302A
Functional Description
General Information
The TMC2302A is a versatile, high-performance address
generator which can control, under user direction, filtering or
remapping of two or three-dimensional images by resampling them from one set of Cartesian coordinates (x, y, z)
into a new, transformed set (u, v, w). Most applications
utilize two identical devices for two-dimensional, or three
devices for three-dimensional, image processing. The host
CPU initializes the system by loading the input image buffer
RAM with the source image pixel data and the TMC2302As
with the image transformation and system configuration control parameters. These parameters are loaded by a separate,
asynchronous input clock. The IMS-based system then executes the entire transformation as programmed, generating a
DONE flag upon completion of the transform. The user can
program the chip to repeat the transform continuously or to
halt at the end.
The IMSs continuously compute the target bit plane (u, v) or
bit space addresses (u, v, w) in typical line-by-line, rasterscan serial sequence. For each output pixel address, they
compute the corresponding remapped source image coordinates, each of whose upper 24 bits become the source bit
plane addresses (x, y). An additional lower twelve bits are
available through the target address port in the optional
extended address mode. Source image addresses may be
generated at up to 40MHz, with the corresponding target
image addresses then appearing at up to (40/k)MHz, where
“k” is the size of the interpolation kernel implemented. In the
two-IMS system, one TMC2302A computes the horizontal
coordinates x and u while the other generates the y and v
(vertical) addresses. In a three-dimensional system, one
additional IMS would provide the z and w (depth or time)
coordinates.
T o support a wide range of image transformations, the “ro w”
or x/u device implements a 16-term polynomial of the form:
x = a + bu + cu
2
+ jv
u + kv
2
u
3
+ du
+ ev + fvu + gvu
2
2
3
+ lv
u
+ mv
3
+ nv
3
u + ov
2
+ hvu
3
2
+ iv
3
2
3
+ pv
3
u
u
2
where "a" through "p" are the user-defined image transformation parameters. The TMC2302A steps sequentially
through the pixels within a user-defined rectangle in the target image space, computing the “old” source image address
(x, y, z) corresponding to each “new” target image pixel (u,
v, w). User-programmable flags are available to indicate
when the source and target image addresses have fallen outside of a defined rectangular area, simplifying the generation
of complex images or image windows. Here, u = U-UMIN
and v = V-VMIN, where (u,v) is the target address output by
the TMC2302A.
In the three-dimensional mode, the x/u transformation equation is:
x = a + bu + ev + kw + fuv + ivw + luw + juvw
See “The Image Transformation Polynomial” section of the
Applications Discussion.
Preliminary Information
(XMIN, YMIN) ORIGINAL (SOURCE) IMAGE NEW (TARGET) IMAGE
y
x
(U0, V0)
NOTE 2
(XMAX, YMAX)
Notes:
1. Coordinate transformation U, V pixel mapped into X, Y coordinates.
2. Bilinear pixel interpolation walk. New U, V pixel intensity calculated from surrounding X, Y pixel neigborhood.
Figure 1. Image resampling geometry showing two-dimensional image rotation and expansion
(UMIN, VMIN)
NOTE 1
U
V
NEW PIXEL
(UMAX, VMAX)
65-2302-03
3
TMC2302A PRODUCT SPECIFICATION
The TMC2302A utilizes an external multiplier-accumulator
or interpolator, connected to the system clock, to calculate
the interpolated pixel value for each color. The products of
the original source image pixel values surrounding the
remapped pixel location (interpolation kernel) and the appropriate weights stored in the coefficient lookup table are
summed. The resulting new interpolated image pixel v alue is
then stored in the corresponding (u, v, w) memory location in
the target image memory buffer. Next, the target image
address is incremented by one in the “u” direction until
UMAX is reached (end of line), when u is reset to UMIN,
and the v counter is incremented to give the first pixel location in the next line. The process is repeated, proceeding
line-by-line through the image, until VMAX is reached. In
the case of three-dimensional images, the IMS system also
steps through each page in the image, incrementing in the
“w” direction with the completion of each image plane until
WMAX is reached, and the transformation is complete.
The Image Manipulation Sequencer can support any nearestneighbor, bilinear interpolation, or cubic convolution resampling. Interpolation kernels of more than one pixel require an
external interpolation coefficient lookup table and multiplier-
accumulator or multiple multiplier array. One, two, and
three-pass algorithms are supported. For each output point in
a typical two-dimensional single-pass static image filter, the
TMC2302A implements a spiralling pixel resampling algorithm, “walking” around the resampling neighborhood in
two dimensions and generating the appropriate coefficient
table addresses to sum up the interpolated pixel value in the
external pixel interpolator. At the end of each walk, the
TMC2302A will advance one pixel along the output scan
line and then execute the walk for that next pixel. When performing multiple-pass interpolation, the TMC2302A system
proceeds along only one dimension per pass, which requires
dimensionally separable, preferably orthogonal, coefficients.
A basic, two-dimensional TMC2302A-based system is
shown in Figure 2 . In this typical arrangement, two Image
Manipulation Sequencers process the image. The only other
components needed beyond the source and target image
buffer memories are a multiplier-accumulator or pixel interpolator such as the TMC2246A Image Mixer or TMC2250A
Matrix Multiplier, and the Interpolation Coefficient Lookup
Table RAM or ROM.
INITIALIZATION
DATA
CONTROL
Preliminary Information
CLOCK
Figure 2. Basic two-dimensional image convolver using TMC2302A IMS with typical 8-bit data path
IMAGE DATA IN
8
16
IDAT
15-0
IDAR
6-0
KADR
INTERPOLATION
DATA
IN
IDAT
15-0
IDAR
6-0
SADR
TMC2302A
ROW (X)
TADR
, SADR
7-0
16
ADDRESS
COEFFICIENT
BUFFER RAM
ADDRESS
8
SADR
7-0
SADR
TMC2302A
ROW (Y)
TADR
23-8
ACC
TWR
7-0
DATA
OUT
23-8
16 2 x 16
11-0
16
11-0
2 x 24
SOURCE
ADDRESS
CLOCK
DESTINATION
ADDRESS
SOURCE
IMAGE
BUFFER
RAM
8
X
ACC
X, Y, P
Y
MULTIPLIER-
ACCUMULATOR
8
WR
DESTINATION
IMAGE
BUFFER
RAM
8
IMAGE DATA OUT
65-2302-04
4
PRODUCT SPECIFICATION TMC2302A
Pin Assignments
120 Pin Plastic Pin Grid Array, PPGA
12345678910111213
A
B
C
D
E
KEY
F
G
Top View
Cavity Up
H
J
K
L
M
N
65-2302-05
Pin Name Pin Name
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
SADR
SADR
IADR
IADR
IDAT
IDAT
GND
GND
IDAT
SADR
SADR
GND
V
DD
IDAT
IDAT
SADR
SADR
GND
GND
IDAT
IDAT
SADR
SADR
V
DD
V
DD
GND
IDAT
SADR
GND
V
DD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
GND
SADR
SADR
V
DD
SADR
OES
IADR
IADR
IADR
IDAT
IDAT
IDAT
V
DD
SADR
SADR
V
DD
SADR
SADR
SADR
IADR
IADR
ICS
IDAT
IDAT
IDAT
IDAT
SADR
V
DD
V
DD
GND
16
17
21
6
3
0
15
12
9
14
15
18
20
23
4
2
13
11
8
7
13
Pin Name Pin Name
GND
G11
19
22
5
1
14
10
6
11
12
5
4
9
10
3
2
7
8
1
6
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
V
DD
IDAT
SADR
SADR
GND
GND
V
DD
SYNC
SADR
SADR
V
DD
V
DD
CLK
IWR
SADR
SADR
GND
V
DD
INIT
GND
SVAL
V
DD
NC
V
DD
GND
KADR
V
DD
TADR
TADR
0
5
4
3
2
1
0
0
4
8
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
DONE
V
DD
GND
NOOP
ACC
OEK
KADR
KADR
KADR
OET
TADR
TADR
TADR
TADR
GND
GND
TVAL
GND
KADR
KADR
KADR
KADR
TWR
TADR
TADR
TADR
TADR
TADR
TADR
ENDD
6
4
2
0
3
6
9
7
5
3
1
1
2
5
7
10
11
Preliminary Information
5
TMC2302A PRODUCT SPECIFICATION
Pin Assignments
(continued)
120 Lead Metric Quad Flat Pack, MQFP
120 91
1
30
31 60
90
61
65-2302-06
Pin Name Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DD
SADR
SADR
GND
V
DD
SADR
SADR
GND
SADR
SADR
SADR
V
DD
SADR
SADR
GND
V
DD
SADR
SADR
SADR
GND
SADR
SADR
SADR
V
DD
SADR
SVAL
ACC
GND
V
DD
GND
31
OEK
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
KADR
V
DD
KADR
KADR
KADR
GND
KADR
KADR
KADR
KADR
OET
TWR
TADR
V
DD
TADR
TADR
TADR
TADR
TADR
TADR
TADR
TADR
TADR
TADR
TADR
DONE
GND
NC
ENDD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Pin Name Pin Name
V
61
DD
GND
62
7
63
TVAL
V
64
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
DD
GND
NOOP
INIT
V
DD
GND
CLK
IWR
GND
V
DD
SYNC
V
DD
GND
IDAT
IDAT
GND
V
DD
IDAT
IDAT
IDAT
GND
IDAT
IDAT
IDAT
V
DD
GND
V
DD
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
0
108
1
109
110
111
2
112
3
113
4
114
115
5
116
6
117
7
118
119
120
GND
IDAT
IDAT
IDAT
IDAT
IDAT
IDAT
IDAT
IDAT
ICS
IADR
IADR
IADR
IADR
IADR
IADR
IADR
OES
SADR
SADR
SADR
SADR
V
DD
SADR
SADR
SADR
SADR
GND
V
DD
GND
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
23
22
21
20
19
18
17
16
Pin Descriptions
Pin Name
Preliminary Information
Power
V
DD
GND D3, E3, G2,
6
Pin Number
C3, C2, F3,
G3, J3, L2,
L4, L7, L11,
K11, J11,
H12, G12,
F11, D11,
A13, A4, B3
H3, K3, N1,
L5, M11,
M12, L12,
K13, H11,
G11, F12,
E11, C12,
C11, C4, A1
1, 5, 12, 16,
24, 29, 33,
45, 61, 64,
68, 73, 75,
80, 88, 90,
113, 119
4, 8, 15, 20,
28, 30, 37,
58, 62, 65,
69, 72, 76,
79, 84, 89,
91, 118, 120
Pin Function DescriptionPPGA MQFP
Supply Voltage. The TMC2302A operates from a single +5V
supply. All pins must be connected.
Ground.
PRODUCT SPECIFICATION TMC2302A
Pin Descriptions
(continued)
Pin Number
Pin Name
Clocks
CLK J12 70
IWR
J13 71
Inputs
IDAT
15-0
A10, C9,
B10, A11,
B11, C10,
A12, B12,
B13, C13,
D12, D13,
E12, E13,
F13, G13
IADR
6-0
A7, C7, B7,
A8, B8, C8,
A9
Outputs
SADR
23-0
B6, C6, A5,
B5, C5, B4,
A3, A2, B2,
B1, C1, D2,
D1, E2, E1,
F2, F1, G1.
H1, H2, J1,
J2, K1, K2
KADR
7-0
N2, M3, N3,
M4, N4, M5,
N5, L6
99, 98, 97,
96, 95, 94,
93, 92, 87,
86, 85, 83,
82, 81, 78,
77
107, 106,
105, 104,
103, 102,
101
109, 110,
111, 112,
114, 115,
116, 117, 2,
3, 6, 7, 9,
10, 11, 13,
14, 17, 18,
19, 21, 22,
23, 25
32, 34, 35,
36, 38, 39,
40, 41
Pin Function DescriptionPPGA MQFP
System Clock . The pixel clock of the TMC2302A strobes all
internal registers except the control parameter preload registers.
All timing specifications except those are referenced to the rising
edge of CLK.
Input Parameter Write Clock. The internal image transformation
and configuration control parameter registers are double buffered
to simplify interfacing with system controllers. Depending on the
state of the chip selects ICS
, control words input to IDAT
the corresponding addresses presented to IADR
are strobed
6-0
15-0
and
into the outer preload registers on the rising edge of the Input
parameter Write clock IWR
. The last parameter must be loaded
twice on two consecutive rising edges of IWR.
Input Parameter Data. Configuration and transformation
parameter Input Data are presented, along with the appropriate
input register address word IADR
, to the parameter Input Data
6-0
port, and are latched into the preload registers on the next rising
edge of IWR
. Preload register updates are disabled by the chip
select control ICS. See Figure 3.
Input Parameter Address. The input parameter preload register
currently indicated by the Input parameter register Address
IADR
rising edge of IWR
is loaded with the data presented to input port IDAT on the
6-0
, as demonstrated in Figure 3.
Source Address. The 24-bit address of one dimension (X, Y, Z) of
the source image pixel value currently being resampled is output
through the Source Address port SADR
forced to the high-impedance state by the enable control OES
. This port can be
23-0
.
Coefficient Address. The integer address steps for each
dimension of the spiral interpolation walk performed by the
TMC2302A, as determined by the transform parameter KERNEL,
are generated by the internal walk counter and output at the
Coefficient Address output port KADR
to the high-impedance state by the enable control OEK
. This port can be forced
7-0
.
Preliminary Information
7
TMC2302A PRODUCT SPECIFICATION
Pin Descriptions
Pin Name
TADR
11-0
Controls
INIT K12 67
SYNC H13 74
ICS B9 100
Preliminary Information
ACC M1 27
N12, N11,
M10, L9,
N10, M9,
N9, L8, M8,
N8, N7, M7
(continued)
Pin Number
56, 55, 54,
53, 52, 51,
50, 49, 48,
47, 46, 44
Pin Function DescriptionPPGA MQFP
Target Address. The 12-bit address of one dimension (U, V, W) of
the target image pixel value just resampled is output through the
Target Address Port TADR
impedance state by the enable control OET
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by utilization of the pipeline delay parameter
PIPTAD. For systems requiring greater spatial resolution in the
source image than that offered by the SADR
Address Port can be reconfigured to output 12 additional LSBs of
the source address by placing the device into the Extended mode,
in which case the pipeline delay parameter must be set to 0 to
maintain alignment with the current source address port output.
See the Device Configuration and Control Parameters section.
Initialize. The TMC2302A control logic is cleared and initialized for
the start of a new image transformation, and the internal working
registers are updated with the contents of the current control
parameter preload registers when the registered control input INIT
is HIGH. The image transformation then commences with the first
source image pixel address nine clocks after INIT is returned low.
Run/Halt. The user can select between continuous or one-frame
operation with the registered input control SYNC. Assuming that
INIT remains LOW and NOOP
HIGH at the end of a transform the TMC2302A will begin the next
image transformation without interruption. This assumes either that
the user is not changing the parameter set, or that a new set of
parameters has already been loaded into the preload registers
midframe, prior to the beginning of the last line in the transform. If
SYNC is LOW during the last clock cycle of a transform, the device
will complete the image, having loaded the new transform
parameter set during the first clock of the final line of the transform,
and halt in the state set on the first clock cycle of the next
transform. These outputs are held until SYNC is again brought
HIGH, and operation resumes on the next clock. See Figure 5.
Input Parameter Chip Select. The input parameter preload
register write clock IWR, and thus the preloading of all
configuration and transformation parameters, is disabled on the
next clock when the registered Input parameter Chip Select input is
HIGH. When ICS returns LOW, they are enabled on the next clock.
See Figure 3
Accumulate. The external pixel interpolator or multiplier-
accumulator is initialized for a new accumulation of products by the
registered Accumulator Control output ACC. On the first cycle of
each interpolation walk, this output goes LOW for one cycle,
effectively clearing the register by loading in only the first new
resampled pixel value. When performing nearest-neighbor
resampling, this control will remain LOW throughout the entire
transform. This output can be delayed up to seven clock cycles
after the nominal sequence shown in Table 4 by the pipeline delay
parameter PIPACC. See the Device Configuration and Control
Parameters section.
.
. This port is forced into the high-
11-0
. TADR
23-0
remains HIGH, if SYNC remains
can be
11-0
alone, the Target
8
PRODUCT SPECIFICATION TMC2302A
Pin Descriptions
Pin Name
TWR
NOOP
OES A6 108
OEK M2 31
OET M6 42
Flags
SVAL L1 26
N6 43
L13 66
(continued)
Pin Number
Pin Function DescriptionPPGA MQFP
Target Memory Write Enable. On the last cycle of each
interpolation walk, the Target Write Enable goes LOW for one clock
cycle, returning HIGH for all but the last cycle of the next walk.
When performing nearest-neighbor resampling, this control will
remain LOW throughout the entire transform. This output can be
forced to the high-impedance state by the enable control OET, and
can be delayed up to seven clock cycles after the nominal
sequence shown in Table 4 by the pipe-line delay parameter
PIPTWR. See the Device Configuration and Control Parameters
section.
No Operation. Assuming that INIT remains LOW, the internal
system clock of the TMC2302A will be disabled on the next clock,
halting the current transform, when the registered control input
NOOP goes LOW. When NOOP returns HIGH, normal operation
resumes on the next clock. This control does not affect the loading
of the configuration and transformation parameter preread
registers.
Source Address Output Enable. The source address port
SADR
is LOW. When OES is HIGH, the port is in the high-impedance
state.
Coefficient Address Output Enable. The interpolation coefficient
address port KADR
enable OEK
impedance state.
Target Address Output Enable. The target address port TADR
and target write enable TWR
0
asynchronous Target Output Enable OET is LOW. When OET is
HIGH, these outputs are in the high-impedance state. This control
functions in both the normal and extended addressing modes.
Source Address Valid. When the current source image address
component output is within the working space defined by the
parameters XMIN and XMAX (or YMIN, YMAX for the column (Y/V)
device or ZMIN, ZMAX for the page (Z/W) device), the Source
Address Valid flag SVAL for that device is LOW. This flag will go
HIGH on the clock in which the corresponding component address
falls outside the defined region. In a typical system, the SVAL
outputs of all IMS devices are OR’ed together to generate a global
boundary violation flag. The user might then insert zeroes into the
pixel interpolator to ignore that portion of the image outside the
defined space, or insert a background color or image. This output
can be delayed up to seven clock cycles after the nominal
sequence shown in Table 4 by the pipeline delay parameter
PIPSVA. See the Device Configuration and Control Parameters
section.
is enabled when the asynchronous output enable OES
23-0
is enabled when the asynchro- nous output
7-0
is LOW. When OEK is HIGH, the port is in the high-
are enabled when the
11-
Preliminary Information
9
TMC2302A PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number
Pin Name
TVAL
ENDD N13 60
DONE L10 57 Done. On the last clock cycle of the current image transform, the
No Connects
NC L3 59 No Connect.
Preliminary Information
M13 63
D4 — Index Pin.
Pin Function DescriptionPPGA MQFP
Target Address Valid. When the current target image addresses
are within the working space defined by the parameters UMINI and
UMAXI, and VMINI and VMAXI (and WMINI and WMAXI for
systems processing three-dimensional images), the Target
Address Valid flag TVAL for that device is LOW. This flag will go
HIGH on the clock in which the current target address outputs fall
outside the defined region, which must fall inside the target area
defined by UMIN, UMAX, etc. Since each TMC2302A device is
programmed with distinct MINI/MAXI parameters and generates a
separate TVAL
dimensional target space windows for each device. TVAL can be
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by the pipeline delay parameter PIPTVA. See the
Device Configuration and Control Parameters section.
End of Dimension. During the last pixel interpolation walk of a row
(X/U device), the last row in a page (Y/V device), or the last page in
a three-dimensional transform (Z/W device), the flag ENDD goes
HIGH for the entire walk, indicating End of the transform in that
dimension. It remains LOW otherwise. This output can be delayed
up to seven clock cycles after the nominal sequence shown in
Table 4 by the pipeline delay parameter PIPEND. See the Device
Configuration and Control Parameters section.
DONE flags on all TMC2302As go HIGH for one clock cycle. On
the next clock cycle, all devices output the first addresses and
control signals for the next image transform. If SYNC is LOW, the
IMS system halts. If SYNC is HIGH, operation continues without
interruption. See “SYNC,” in the Controls section. This flag can be
delayed up to seven clock cycles after the nominal sequence
shown in Table 4 by the pipeline delay parameter PIPDON. Also
see “PFLS,” in the Device Configuration and Control Parameters
section.
flag, the user may define separate two or three-
10
PRODUCT SPECIFICATION TMC2302A
Transformation Coefficient and
Configuration and Control
Parameters
The TMC2302A is intended to act as a co-processor, requiring only that the user program the device to perform the
image transformation desired by loading in the appropriate
device configuration and transformation control parameters
discussed in this section. The user then issues an “Init”
command, allowing his system to run unattended until the
completion of the image when a “Done” flag is generated to
inform the host system.
The capabilities and flexibility of the TMC2302A Image
Manipulation Sequencer are apparent when reviewing the
following tables which define the transformation coefficient
and configuration and control parameters. These tables are
broken up into two separate groups. The first parameters discussed are the control words which select the dimension calculated, the functional configuration of each device, the
working space in which they will operate, the size of the
interpolation kernel desired, and the timing of the various
address and control signals involved in handling the pixel
data pipeline. The second parameters are the polynomial
transform coefficients used in performing image manipulation. The TMC2302A utilizes three levels of internal 48-bit
accumulators to calculate these values by forward difference
accumulation, generating no significant cumulative spatial
error for most applications. The user must be aware that all
internal parameter and coefficient registers must be set by
the user, including resetting after powerup any unused control words or coefficients.
As mentioned above, the TMC2302A also features userprogrammable image data pipeline configuration controls.
All output signals except the source and coefficient address
outputs can be individually delayed by the user up to seven
clocks after the nominal system timing illustrated in Table 4.
This allows the user to software-configure the TMC2302As
in his system to match his pixel interpolator, image buffer,
and interpolation coefficient RAM structure timing.
The user can also program the device to continue into the
next image for a set number of clock cycles after the Done
flag has appeared. First, this “flushes” the final resampled
pixel data word through the interpolation pipeline, all the
way to the target image RAM. Also, valid pixel data will
then appear on the first clock of the next transform independent of the length of the pixel pipeline, incurring no lost
clock cycles.
Device Configuration and Control
Parameters
UMIN,
VMIN,
WMIN
UMAX,
VMAX,
WMAX
Note: The parameter UMAX must exceed UMIN so as to
ensure that a minimum of 5 system clock cycles in twodimensional operation, or 15 clock cycles in three-dimensional operation, pass between the periods in which these
two target address values are generated. Thus in 2D nearest
neighbor operation UMAX must be 5 greater than UMIN. In
2D bilinear interpolation mode (4-pixel two-dimensional
kernel) the distance must be two pixels in the target image
(actually enforcing a spacing of 8 system clocks).
UMINI,
VMINI,
WMINI
UMAXI,
VMAXI,
WMAXI
The memory addresses of the target image
boundaries corresponding to the top, left side,
and front page of the new image being generated are defined in all devices of the user's
system by the parameters UMIN, VMIN, and
WMIN, respectively. At the beginning of the
transformation, the initial source image coordinate (X
coordinate set. The numeric format assumed
is 12-bit unsigned binary integer.
The memory addresses of the target image
boundaries corresponding to the bottom,
right side, and last page of the image being
generated are defined in all devices by the
parameters UMAX, VMAX, and WMAX,
respectively. These values should be greater
than the UMIN/VMIN/WMIN values defined
above. Numeric format assumed is unsigned
12-bit binary integer.
The target image addresses corresponding to
those of the top, left side, and front page of the
2 or 3 dimensional region indicated by the
valid target address flag TVAL are UMINI,
VMINI, and WMINI, respectively. Thus, to
define a valid region beginning at “m,” the
MINI parameter value is “m,” These parameters are assumed to be in 12-bit unsigned
binary integer format. Proper TVAL operation
requires UMIN < UMINI < UMAXI
< UMAX, etc.
The target image addresses one more than
those of the right side, bottom and back page
of the region indicated by the valid target
address flag TVAL are UMAXI, VMAXI, and
WMAXI, respectively. Thus, to define a valid
region ending at “n,” the MAXI parameter
value is “n+1”. These parameters are assumed
to be in 12-bit unsigned integer format.
, Y0, Z0) will be mapped to this
0
Preliminary Information
11
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