Dell XPS 13-9360 Schematics

MODEL NAME :

PCB NO :

BOM P/N :

ZZZ

1 1

MB_PCB

DAA000AW000

LA-C881P

TBD

AAZ80

R1 R3 R3

DAA000AW010 DAA000AW011 DAA000AW012 DAA000AW013

CPN

Dell/Compal Confidential

2 2

Schematic Document

Dino2 (Skylake ULT)

3 3

2015-09-16

Rev: 1.0 (A00)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P01-Cover Page

LA-C881P

1 59Wednesday, October 14, 2015

1.0

www.schematic-x.blogspot.com

eDP Panel Conn.

USB TypeC Conn.

1 1

P.22

P.26

Alpine Ridge Thunderbolt

TI PD Controller

SB 3.0 Conn.

Digital Camera

Touch Screen

2 2

Daughter/B

USB 3.0 Conn.

( Power Share)

P.30

P.22

USB3.0

USB3.0 Re-Driver

CardReader RTS5242

eDP 1.3

DP 1.2 X2

PCIe Gen3 X 2

USB3.0/USB2.0

USB2.0

USB3.0

USB2.0

Intel

Skylake ULT

15W TDP

Memory Bus (LPDDR3)

Dual Channel

1.2V LPDDR3 1866 MHz Non-Interleave

SPI

SATA3 X1 / PCIE X4

USB2.0

PCIEPCIE Gen2

Channel A LPDDR3 8Gb or 16Gb (x32) * 2

P.12, 14

Channel B LPDDR3 8Gb or 16Gb (x32) * 2

P.13, 14

SPI ROM 128Mb

TPM1.2 Nuvoton

M.2 Socket3 M-Key

SSD

M.2 Slot A-SD

WLAN BT4.0

P.08

P.27

P.29

P.28

Precision Touch Pad

3 3

Fan conn.

P.35

P.29

RTC conn.

DC/DC Interface CKT.

Power Circuit DC/DC

4 4

LED+DMIC/FPC

P.32~33

P.38~48

Front Side LED+DMICx2 Board

I2C

PS/2

SMBus

KBC/B

EC MEC 5085

ECE1117B

Page 5 ~ 14

LPC Bus

BCBUS

HDA

Audio Codec ALC3246

P.36

KSIO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

I2C

GPIO Extender MCP 23017

Int.KBDKeyboard Controller

2013/07/04 2013/10/28

P.37

Compal Secret Data

Deciphered Date

DMIC

Headphone Jack

( iPhone & Nokia compatible)

P.24

Int. Speaker

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P02-Block Diagram

LA-C881P

P.25

2 59Tuesday, October 13, 2015

0.6

2+2 CPU Option

UCPU1

QJKM_2+2@

UCPU1

QJKR_2+2@

UCPU1

QJKR_2+2@

SA000092N1L

FJ8066201931104 QJKR

UCPU1

SR2EU_2+2@

UCPU1

1 1

SR2EU_2+2@

SA000092N4L

FJ8066201931104 SR2EU

UCPU1

QJKP_2+2@

UCPU1

QJKP_2+2@

SA000092O1L

FJ8066201930409 QJKP

UCPU1

SR2EY_2+2@

UCPU1

SR2EY_2+2@

SA000092O3L

FJ8066201930409 SR2EY

QJKM_2+2@

SA000092T1L

FJ8066201924931 QJKM

UCPU1

SR2F0_2+2@

UCPU1

SR2F0_2+2@

SA000092T3L

FJ8066201924931 SR2F0

UCPU1

QJKK_2+2@

UCPU1

QJKK_2+2@

SA000092P1L

FJ8066201930408 QJKK

UCPU1

SR2EZ_2+2@

UCPU1

SR2EZ_2+2@

SA000092P3L

FJ8066201930408 SR2EZ

UCPU1

QJKH_2+2@

UCPU1

QJKH_2+2@

SA000092U1L

FJ8066201924950 QJKH

UCPU1

SR2F1_2+2@

UCPU1

SR2F1_2+2@

SA000092U3L

FJ8066201924950 SR2F1

2+3 CPU Option

UCPU1

QK1Q_2+3@

UCPU1

QK1Q_2+3@

SA00009CL0L

FH8066202496511 QK1Q

UCPU1

QK1P_2+3@

UCPU1

QK1P_2+3@

SA00009E80L

FJ8066202496507 QK1P

UCPU1

FJ8066202496507 QK2S

UCPU1

FJ8066202499208 QK20

QK2S_2+3@

SA00009E81L

QK20_2+3@

SA00009E70L

AR Option

UT1

AR_QSJN@

UT1

AR_QSJN@

SA000090N3L

DSL6340 QSJN B1

UT1

AR_SLL42@

UT1

AR_SLL42@

SA000090N5L

DSL6340 SLL42 B1

DRAM Option DRAM Config Option

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2

RH144

SD028100280

10K_0402_5%

RH129

SD028100280

10K_0402_5%

RH129

M4G_1866@

M8G_1866@

H4G_1866@

RH139

SD028100280

10K_0402_5%

RH150

SD028100280

10K_0402_5%

RH139

M4G_1866@

M8G_1866@

H4G_1866@

RH145

SD028100280

10K_0402_5%

RH145

SD028100280

10K_0402_5%

RH149

M4G_1866@

M8G_1866@

H4G_1866@

RH151

SD028100280

10K_0402_5%

RH151

SD028100280

10K_0402_5%

RH151

Micron 4G/1866

Micron 8G/1866

UD19

M4G_1866@

UD19

M4G_1866@

SA00008PF1L

EDF8132A3MA-JD-F-R A31!

UD19

M8G_1866@

UD19

M8G_1866@

SA00008Q11L

EDFA232A2MA-JD-F-R A31!

UD19

H4G_1866@

UD19

H4G_1866@

UD20

M4G_1866@

UD20

M4G_1866@

SA00008PF1L

EDF8132A3MA-JD-F-R A31!

UD20

M8G_1866@

UD20

M8G_1866@

SA00008Q11L

EDFA232A2MA-JD-F-R A31!

UD20

H4G_1866@

UD20

H4G_1866@

UD21

M4G_1866@

UD21

M4G_1866@

SA00008PF1L

EDF8132A3MA-JD-F-R A31!

UD21

M8G_1866@

UD21

M8G_1866@

SA00008Q11L

EDFA232A2MA-JD-F-R A31!

UD21

H4G_1866@

UD21

H4G_1866@

UD22

M4G_1866@

UD22

M4G_1866@

SA00008PF1L

EDF8132A3MA-JD-F-R A31!

UD22

M8G_1866@

UD22

M8G_1866@

SA00008Q11L

EDFA232A2MA-JD-F-R A31!

UD22

H4G_1866@

UD22

H4G_1866@

Hynix 4G/1866

2 2

SA00008G61L

H9CCNNN8GTMLAR-NUD A31!

UD19

H8G_1866@

UD19

H8G_1866@

SA00008G61L

H9CCNNN8GTMLAR-NUD A31!

UD20

H8G_1866@

UD20

H8G_1866@

SA00008G61L

H9CCNNN8GTMLAR-NUD A31!

UD21

H8G_1866@

UD21

H8G_1866@

SA00008G61L

H9CCNNN8GTMLAR-NUD A31!

UD22

H8G_1866@

UD22

H8G_1866@

SD028100280

10K_0402_5%~D

RH144

H8G_1866@

RH144

H8G_1866@

SD028100280

10K_0402_5%~D

RH139

H8G_1866@

RH139

H8G_1866@

SD028100280

10K_0402_5%~D

RH149

H8G_1866@

RH149

H8G_1866@

SD028100280

10K_0402_5%~D

RH151

Hynix 8G/1866

SA00008FJ1L

H9CCNNNBJTMLAR-NUD A31!

UD19

S4G_1866@

UD19

S4G_1866@

SA00008FJ1L

H9CCNNNBJTMLAR-NUD A31!

UD20

S4G_1866@

UD20

S4G_1866@

SA00008FJ1L

H9CCNNNBJTMLAR-NUD A31!

UD21

S4G_1866@

UD21

S4G_1866@

SA00008FJ1L

H9CCNNNBJTMLAR-NUD A31!

UD22

S4G_1866@

UD22

S4G_1866@

SD028100280

10K_0402_5%~D

RH144

S4G_1866@

RH144

S4G_1866@

SD028100280

10K_0402_5%~D

RH150

S4G_1866@

RH150

S4G_1866@

SD028100280

10K_0402_5%~D

RH149

S4G_1866@

RH149

S4G_1866@

SD028100280

10K_0402_5%~D

RH151

Samsung 4G/1866

SD028100280

S8G_1866@

SD028100280

10K_0402_5%~D

RH146

SA00008PQ1L

K4E8E304EE-EGCF A31!

UD19

S8G_1866@

UD19

S8G_1866@

SA00008PQ1L

K4E8E304EE-EGCF A31!

UD20

S8G_1866@

UD20

S8G_1866@

SA00008PQ1L

K4E8E304EE-EGCF A31!

UD21

S8G_1866@

UD21

S8G_1866@

SA00008PQ1L

K4E8E304EE-EGCF A31!

UD22

S8G_1866@

UD22

S8G_1866@

SD028100280

10K_0402_5%~D

RH129

S8G_1866@

RH129

S8G_1866@

SD028100280

10K_0402_5%~D

RH139

S8G_1866@

RH139

S8G_1866@

SD028100280

10K_0402_5%~D

RH145

Samsung 8G/1866

SD028100280

SA00008QV1L

K4E6E304EE-EGCF A31!

UD19

M16G_1866@

UD19

M16G_1866@

SA00008QV1L

K4E6E304EE-EGCF A31!

UD20

M16G_1866@

UD20

M16G_1866@

SA00008QV1L

K4E6E304EE-EGCF A31!

UD21

M16G_1866@

UD21

M16G_1866@

SA00008QV1L

K4E6E304EE-EGCF A31!

UD22

M16G_1866@

UD22

M16G_1866@

SD028100280

10K_0402_5%~D

RH144

M16G_1866@

RH144

M16G_1866@

SD028100280

10K_0402_5%~D

RH150

M16G_1866@

RH150

M16G_1866@

SD028100280

10K_0402_5%~D

RH145

M16G_1866@

RH145

M16G_1866@

SD028100280

10K_0402_5%~D

RH151

Mircon 16G/1866

SD028100280

SA00008QW1L

3 3

SA00008QW1L

EDFB232A1MA-JD-F-R A31!

UD19

S16G_2133@

UD19

S16G_2133@

SA00008QW1L

EDFB232A1MA-JD-F-R A31!

UD20

S16G_2133@

UD20

S16G_2133@

SA00008QW1L

EDFB232A1MA-JD-F-R A31!

UD21

S16G_2133@

UD21

S16G_2133@

SA00008QW1L

EDFB232A1MA-JD-F-R A31!

UD22

S16G_2133@

UD22

S16G_2133@

SD028100280

10K_0402_5%~D

RH129

S16G_2133@

SD028100280

10K_0402_5%~D

RH150

S16G_2133@

RH150

S16G_2133@

SD028100280

10K_0402_5%~D

RH145

S16G_2133@

RH145

S16G_2133@

SD028100280

10K_0402_5%~D

RH151

Samsung 16G/2133

SA00008VV1L

K4EBE304EB-EGCG A31!

UD19

S16G_1866@

UD19

S16G_1866@

SA00008VV1L

K4EBE304EB-EGCG A31!

UD20

S16G_1866@

UD20

S16G_1866@

SA00008VV1L

K4EBE304EB-EGCG A31!

UD21

S16G_1866@

UD21

S16G_1866@

SA00008VV1L

K4EBE304EB-EGCG A31!

UD22

S16G_1866@

UD22

S16G_1866@

SD028100280

10K_0402_5%~D

RH144

S16G_1866@

SD028100280

10K_0402_5%~D

RH139

S16G_1866@

RH139

S16G_1866@

SD028100280

10K_0402_5%~D

RH145

S16G_1866@

RH145

S16G_1866@

SD028100280

10K_0402_5%~D

RH146

SD028100280

Samsung 16G/1866

SD028100280

H16G_1866@

SD028100280

10K_0402_5%~D

RH151

SA00008X11L

K4EBE304EB-EGCF A31!

UD19

H16G_1866@

UD19

H16G_1866@

SA00008X11L

K4EBE304EB-EGCF A31!

UD20

H16G_1866@

UD20

H16G_1866@

SA00008X11L

K4EBE304EB-EGCF A31!

UD21

H16G_1866@

UD21

H16G_1866@

SA00008X11L

K4EBE304EB-EGCF A31!

UD22

H16G_1866@

UD22

H16G_1866@

SD028100280

10K_0402_5%~D

RH129

H16G_1866@

RH129

H16G_1866@

SD028100280

10K_0402_5%~D

RH150

H16G_1866@

RH150

H16G_1866@

SD028100280

10K_0402_5%~D

RH149

Hynix 16G/1866

SD028100280

SA00008YT1L

H9CCNNNCLTMLAR-NUD A31!

SA00008YT1L

H9CCNNNCLTMLAR-NUD A31!

SA00008YT1L

H9CCNNNCLTMLAR-NUD A31!

SA00008YT1L

H9CCNNNCLTMLAR-NUD A31!

SD028100280

10K_0402_5%~D

SD028100280

10K_0402_5%~D

SD028100280

10K_0402_5%~D

SD028100280

10K_0402_5%~D

M4G_1866@

M8G_1866@

H4G_1866@

H8G_1866@

S4G_1866@

S8G_1866@

M16G_1866@

S16G_2133@

S16G_1866@

H16G_1866@

MEM_CONFIG4MEM_CONFIG3

RH147

M4G_1866@

RH147

M4G_1866@

SD028100280

10K_0402_5%

RH147

M8G_1866@

RH147

M8G_1866@

SD028100280

10K_0402_5%

RH147

H4G_1866@

RH147

H4G_1866@

SD028100280

10K_0402_5%~D

RH147

H8G_1866@

RH147

H8G_1866@

SD028100280

10K_0402_5%~D

RH147

S4G_1866@

RH147

S4G_1866@

SD028100280

10K_0402_5%~D

RH152

S8G_1866@

RH152

S8G_1866@

SD028100280

10K_0402_5%~D

RH147

M16G_1866@

RH147

M16G_1866@

SD028100280

10K_0402_5%~D

RH152

S16G_2133@

RH152

S16G_2133@

SD028100280

10K_0402_5%~D

RH152

S16G_1866@

RH152

S16G_1866@

SD028100280

10K_0402_5%~D

RH147

H16G_1866@

RH147

H16G_1866@

SD028100280

10K_0402_5%~D

4 4

LA-C881P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAYNO TBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

ANDTRADE SECRET INFORMATION. THIS SHEET MAYNO TBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D

ANDTRADE SECRET INFORMATION. THIS SHEET MAYNO TBE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONOF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATIONIT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTYWITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P03-BoM Option

Size Document Number Rev

Date: Sheet of

0.6

3 59Tuesday, October 13, 2015

Board ID Table for AD channel

X00240K X01

X03 X04 A00

REV

CE54RE79

4700p

130K

4700p 4700p

62K X02

4700p

33K

4700p

8.2K 4700p

4.3K

4700p

BOARD_ID rise time is measured from 5%~68%.

Dino2

SKU

Vpro+CS

nVpro+CS

PTT TPM2.0

Disable

Enable

Enable None

PCH USB 2.0 Port Mapping

USB PORT# DESTINATION

External USB3(On IOB)

External USB3(On MB)

NGFF CARD WLAN

Touch Panel

Camera

SMBUS Control Table

SOURCE

I2C1A_CLK I2C1A_DATA

I2C1C_CLK I2C1C_DATA

I2C1G_CLK I2C1G_DATA

I2C2A_DATA

PCH_SML0CLK PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

SMBCLK SMBDATA

I2C0_CLK

1 1

I2C0_DATA

I2C1_CLK I2C1_DATA

MEC5085

MEC5085I2C2A_CLK

PCH

BATTERY

5085Charger

XDP

Touch Pad

AudioPD23017

PCH USB 3.0

External USB3(On IOB)

External USB3(On MB)

Port Mapping

PCH DDI

Port Mapping

DDI PORT# DESTINATION

Alpine Ridge

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

FLEX CLK#

CLKOUT_LPC_0

CLKOUT_LPC_1

DESTINATIONDIFFERENTIAL CLK#

Alpine Ridge

NGFF CARD WLAN

M.2 SSD / PCIe

Card Reader

DESTINATION

EC LPC

Debug

PCI EXPRESS PORT#

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Lane 9

Lane 10

Lane 11

Lane 12 / SATA 2

DESTINATION

Alpine Ridge

NGFF CARD WLAN

Card Reader

M.2 SSD

SATA PORT#

DESTINATION

SATA-0

SATA-1A

SATA-1B

SATA-2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

M.2 SSD

Compal Secret Data

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

Symbol Note :

: means Digital Ground

: means Analog Ground

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P04-Notes List

LA-C881P

4 59Tuesday, October 13, 2015

1.0

SY8210A

PU600)

(

ADAPTER

D D

SYX196D (PU700)

TPS62134A (PU1400)

CHARGER BQ24777

(PU300)

TPS62134B (PU1401)

SY8288C (PU501)

B+

BATTERY

C C

TLV62150R (PU800)

SIO_SLP_S4# & SUS_ON_EC

+1.2V_DDR

TPS22961

SIO_SLP_SUS#

880mA 240mA

SIO_SLP_S0# & RUN_ON_P

3100mA

SIO_SLP_SUS#

2570mA

ALWON

530mA

SIO_SLP_SUS#

210mA

+1.0VA

+1.0VS_VCCIO

+1.0V_PRIM_CORE

+5VALW

+1.8VA

LDOIN

(UZ22)

SY8210

PU600)

(

SIO_SLP_S0# & RUN_ON_P

260mA

SM_PG_CTRL

600mA5500mA

AOZ1331

(U719)

AOZ1331 (U719)

TPS2544

(US1)

G547I1P

(US2)

+0.6VS

+VCCPLL_OC

RUN_ON_P

200mA

AUD_PWR_EN

3150mA

USB_PWR_SHR_VB US_EN_R

2430mA

USB2_EN

2000mA

+5VS_AUDIO

+5V_USB_P2

+1.0V_MPHYAON

TPS22961

(UZ25)

TPS22961

(UZ19)

+5VS

+5V_USB_P1

TPS22961

SIO_SLP_SUS# & SUS_ON_P

SIO_SLP_S0# & RUN_ON_P

40mA

(UZ20)

+1.0V_VCCST

+1.0V_VCCSTG

MPHYP_PWR_EN

2100mA

CPU PWR

PCH PWR

GPU PWR

Peripheral Device PWR

+1.0V_MPHYGT

SY8286B (PU500)

ALWON

590mA

TPS62134C (

PU1500)

TPS62134C (PU1501)

B B

IMVP_VR_ON

2500mA

IMVP_VR_ON

2000mA

+VCC_EDRAM

+VCC_EOPIO

+3VALW

TPS22961 (UZ24)

AOZ1331 (U716)

AOZ1331 (U717)

AOZ1331 (U720)

TLV62150R (PU900)

AOZ1331 (U718)

660mA

SUS_ON_P

AOZ1331 (U664)

ISL95857

(PU1000)

A A

5100mA

IMVP_VR_ON

VCC_SA

64000mA

IMVP_VR_ON

+VCC_GT+

29000mA

IMVP_VR_ON

+VCC_CORE

Si3457BDV

(Q70)

590mA

EN_INVPWR

+INV_PWR_SRC

+1.8VU

TPS22961 (UZ23)

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

ENVDD

545mA

TP_PW_EN

35mA

PCH_PWR_EN (SIO_SLP_SUS#)

535mA

AUX_EN_WOWL

620mA

EN_CAM

300mA

AUD_PWR_EN

50mA

SUS_ON_P

600mA

+LCDVDD

+3VS_TP

SD_PWR_EN

1200mA

+3V_PCH

RUN_ON_P

2500mA

+3VS_NGFF

RUN_ON_P

480mA

+3VS_CAM

3.3V_TS_EN

45mA

+3VS_AUDIO

+3V_TBT

DELL CONFIDENTIAL/PROPRIETARY

AOZ1331 (U664)

+3VS_CR

+3.3VDX_SSD

+3VS

+3VS_TS

Title

Size Document Number Rev

Date: Sheet of

AUD_PWR_EN

400mA

+1.8VS_AUDIO

+V1.8S_EDRAM

Compal Electronics, Inc.

P05-Power rails

LA-C881P

5 59Tuesday, October 13, 2015

1.0

D D

SKL-U

MEM_SMBCLK

MEM_SMBDATA

+3V_PCH

2N7002

2.2K

+3VS

XDP

V3W3

SML1_SMBDATA

SML1_SMBCLK

B6A5

USBC_MCP23017_SMBCLK

USBC_MCP23017_SMBDAT

+3V_PCH

2.2K

+3VALW_5085

MCP_23017

C C

PD_Debug

DBC Buffer

2.2K

KBC

A56

1C1CB59

PBAT_SMBCLK

PBAT_SMBDAT

2.2K

B49

B48

A49

B52

UPD_SMBCLK

UPD_SMBDAT

B B

MEC 5085

8.2K

B50

A47

CHARGER_SMBCLK

CHARGER_SMBDAT

A A

8.2K

+3VALW_5085

100 ohm

+3VALW_5085

BATTERY CONN

UPD

Charger

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P06-SMBus block diagram

LA-C881P

6 59Tuesday, October 13, 2015

1.0

D D

+3VS

RC175 2.2K_0402_5%RC175 2.2K_0402_5%

RC178 2.2K_0402_5%RC178 2.2K_0402_5%

RC176 2.2K_0402_5%RC176 2.2K_0402_5%

RC177 2.2K_0402_5%RC177 2.2K_0402_5%

C C

B B

A A

CPU_DP1_CTRL_CLK

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_CLK

CPU_DP2_CTRL_DATA

UCPU1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

KL-U_BGA1356

DDR Memory Configuratino Type Strap pin

+1.8VA

RH144 10K_0402_5%@RH144 10K_0402_5%@

RH150 10K_0402_5%@RH150 10K_0402_5%@

RH149 10K_0402_5%@RH149 10K_0402_5%@

RH151 10K_0402_5%@RH151 10K_0402_5%@

RH152 10K_0402_5%@RH152 10K_0402_5%@

SKL_ULT

Alpine Ridge

+1.0VS_VCCIO

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

CPU_DP1_CTRL_CLK<39>

CPU_DP1_CTRL_DATA<39> CPU_DP1_HPD <39>

CPU_DP2_CTRL_CLK<39>

CPU_DP2_CTRL_DATA<39>

CAD Note:Trace width=20 mils, Isolation Spacing=25mil, Max length=100 mils.

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC_RCOMP

9 OF 20

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG3

MEM_CONFIG4

DDI1_PTX_TBRX_N0<39> DDI1_PTX_TBRX_P0<39> DDI1_PTX_TBRX_N1<39> DDI1_PTX_TBRX_P1<39> DDI1_PTX_TBRX_N2<39> DDI1_PTX_TBRX_P2<39> DDI1_PTX_TBRX_N3<39> DDI1_PTX_TBRX_P3<39>

DDI2_PTX_TBRX_N0<39> DDI2_PTX_TBRX_P0<39> DDI2_PTX_TBRX_N1<39> DDI2_PTX_TBRX_P1<39> DDI2_PTX_TBRX_N2<39> DDI2_PTX_TBRX_P2<39> DDI2_PTX_TBRX_N3<39> DDI2_PTX_TBRX_P3<39>

CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA CPU_DP1_HPD

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

1 2

RC2 24.9_0402_1%RC2 24.9_0402_1%

COMPENSATION PU FOR eDP

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

1 2

CSI2_COMP

RC3 100_0402_1%RC3 100_0402_ 1%

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4

EMMC_RCOMP

RC4 200_0402_1%RC4 200_0402_1%

RH129 10K_0402_5%@RH129 10K_0402_5%@

RH139 10K_0402_5%@RH139 10K_0402_5%@

RH145 10K_0402_5%@RH145 10K_0402_5%@

RH146 10K_0402_5%@RH146 10K_0402_5%@

RH147 10K_0402_5%@RH147 10K_0402_5%@

1 2

EDP_COMP

SKL-U

UCPU1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

KL-U_BGA1356

SKL-U

DDI

DISPLAY SIDEBANDS

1 OF 20

SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0

GPIO Pin

GPP_D5

GPP_D6

GPP_D7

GPP_D8 M EM_CONFIG3

GPP_D9

GPIO Pin

GPP_D5

GPP_D6

GPP_D7

GPP_D8 M EM_CONFIG3

GPP_D9

GPIO Pin

GPP_D5

GPP_D6

GPP_D7

GPP_D9

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG4

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG2

MEM_CONFIG4

Pin Name

MEM_CONFIG0

MEM_CONFIG1

MEM_CONFIG3GPP_D8

MEM_CONFIG4

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

1600 Mbps

1866 Mbps

2133 Mbps

CPU_DP2_HPD

EDP_HPD

Micron 4G

eDP_TXN_P0 <25> eDP_TXP_P0 <25> eDP_TXN_P1 <25> eDP_TXP_P1 <25> eDP_TXN_P2 <25> eDP_TXP_P2 <25> eDP_TXN_P3 <25> eDP_TXP_P3 <25>

eDP_AUXN <25> eDP_AUXP <25>

CPU_DDI1_AUXN <39> CPU_DDI1_AUXP <39> CPU_DDI2_AUXN <39> CPU_DDI2_AUXP <39>

PAD~D

PAD~D PAD~D

PAD~D

CPU_DP2_HPD <39>

EDP_HPD <25>

PANEL_BKLEN < 25> EDP_BIA_PWM <25> ENVDD_PCH <33,37>

Micron 8G

0 1

Support QHD

Mircon 16G

Hynix 4G

0 1

0 11

EDP_HPD

CPU_DP1_HPD

CPU_DP2_HPD

Hynix 16GHynix 8G

RC1100K_0402_5% RC1100K_0402_5%

RC312100K_0402_5% RC312100K_0402_5%

RC242100K_0402_5% RC242100K_0402_5%

Samsung 8GSamsung 4G

0 1

1 1

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0

Micron 4G

Micron 8G

1 1

Mircon 16G

Hynix 4G

1 0

1 11

Hynix 16GHynix 8G

1 1 1 1 1 1 1

0 0 0 0 0 0 0

Micron 4G

Micron 8G

0MEM_CONFIG2

Mircon 16G

Hynix 4G

Hynix 8G Hynix 16G

1 11

0 0 0

Samsung 4G Samsung 8G

Samsung 8GSamsung 4G

0 0

Samsung 16G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document Number R ev

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P07-MCP(1/14)DDI,EDP,CSI2,EMMC

LA-C881P

7 59Tuesday, October 13, 2015

1.0

LPDDR3, Ballout for side by side(Non-Interleave)

SKL-U

UCPU1B

AL71

DDR_A_D0 DDR_A_D1

D D

DDR_A_D[32..47]<21>

DDR_B_D[0..15]<22>

C C

DDR_B_D[32..47]<22>

B B

DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

KL-U_BGA1356

SKL-U

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA [5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA [9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA [6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA [8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA [7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA [12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA [11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA [13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]

DDR0_WE#/DDR0_C AB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA [2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA [10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA [1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA [0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_ODT[1]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

2 OF 20

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE2 DDR_A_CKE3

DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0

DDR_VTT_CNTL

DDR_A_CLK#0 <21,23> DDR_A_CLK0 <21,23> DDR_A_CLK#1 <21,23> DDR_A_CLK1 <21,23>

DDR_A_CKE0 <21,23> DDR_A_CKE1 <21,23> DDR_A_CKE2 <21,23> DDR_A_CKE3 <21,23>

DDR_A_CS#0 <21,23> DDR_A_CS#1 <21,23> DDR_A_ODT0 <21,23>

DDR_A_CA1_0 <21,23> DDR_A_CA1_1 <21,23> DDR_A_CA1_2 <21,23> DDR_A_CA1_3 <21,23> DDR_A_CA1_4 <21,23> DDR_A_CA1_5 <21,23> DDR_A_CA1_6 <21,23> DDR_A_CA1_7 <21,23> DDR_A_CA1_8 <21,23> DDR_A_CA1_9 <21,23>

DDR_A_CA2_0 <21,23> DDR_A_CA2_1 <21,23> DDR_A_CA2_2 <21,23> DDR_A_CA2_3 <21,23> DDR_A_CA2_4 <21,23> DDR_A_CA2_5 <21,23> DDR_A_CA2_6 <21,23> DDR_A_CA2_7 <21,23> DDR_A_CA2_8 <21,23> DDR_A_CA2_9 <21,23>

DDR_A_DQS#0 <21> DDR_A_DQS0 <21> DDR_A_DQS#1 <21> DDR_A_DQS1 <21> DDR_A_DQS#4 <21> DDR_A_DQS4 <21> DDR_A_DQS#5 <21> DDR_A_DQS5 <21> DDR_B_DQS#0 <22> DDR_B_DQS0 <22> DDR_B_DQS#1 <22> DDR_B_DQS1 <22> DDR_B_DQS#4 <22> DDR_B_DQS4 <22> DDR_B_DQS#5 <22> DDR_B_DQS5 <22>

T19

PAD~D

+V_DDR_REF_CA <23> +V_DDR_REFA_R <23> +V_DDR_REFB_R <23>

DDR_A_D[16..31]<21>DDR_A_D[0..15]<21>

DDR_A_D[48..63]<21>

DDR_B_D[16..31]<22>

DDR_B_D[48..63]<22>

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UCPU1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KL-U_BGA1356

SKL-U

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA [5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA [9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA [6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA [8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA [7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA [12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA [11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA [13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]

DDR1_WE#/DDR1_C AB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA [2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA [10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA [1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA [0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DRAM_RESET# DDR_RCOMP[0]

DDR CH - B

DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_CLK#0 DDR_B_CLK#1 DDR_B_CLK0 DDR_B_CLK1

DDR_B_CKE0 DDR_B_CKE1 DDR_B_CKE2 DDR_B_CKE3

DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR_B_CLK#0 <22,23> DDR_B_CLK#1 <22,23> DDR_B_CLK0 <22,23> DDR_B_CLK1 <22,23>

DDR_B_CKE0 <22,23> DDR_B_CKE1 <22,23> DDR_B_CKE2 <22,23> DDR_B_CKE3 <22,23>

DDR_B_CS#0 <22,23> DDR_B_CS#1 <22,23> DDR_B_ODT0 <22,23>

DDR_B_CA1_0 <22,23> DDR_B_CA1_1 <22,23> DDR_B_CA1_2 <22,23> DDR_B_CA1_3 <22,23> DDR_B_CA1_4 <22,23> DDR_B_CA1_5 <22,23> DDR_B_CA1_6 <22,23> DDR_B_CA1_7 <22,23> DDR_B_CA1_8 <22,23> DDR_B_CA1_9 <22,23>

DDR_B_CA2_0 <22,23> DDR_B_CA2_1 <22,23> DDR_B_CA2_2 <22,23> DDR_B_CA2_3 <22,23> DDR_B_CA2_4 <22,23> DDR_B_CA2_5 <22,23> DDR_B_CA2_6 <22,23> DDR_B_CA2_7 <22,23> DDR_B_CA2_8 <22,23> DDR_B_CA2_9 <22,23>

DDR_A_DQS#2 <21> DDR_A_DQS2 <21> DDR_A_DQS#3 <21> DDR_A_DQS3 <21> DDR_A_DQS#6 <21> DDR_A_DQS6 <21> DDR_A_DQS#7 <21> DDR_A_DQS7 <21> DDR_B_DQS#2 <22> DDR_B_DQS2 <22> DDR_B_DQS#3 <22> DDR_B_DQS3 <22> DDR_B_DQS#6 <22> DDR_B_DQS6 <22> DDR_B_DQS#7 <22> DDR_B_DQS7 <22>

T21

PAD~D

T18

PAD~D

+1.2V_DDR

UC2

GND

VCC

UC2

CC240

0.1U_0402_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

+3VS

RE60

RE60 100K_0402_5%

100K_0402_5%

SM_PG_CTRL <49>

Compal Secret Data

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

LPDDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Trace width=12~15 mil, Spacing=20 mils Max trace length= 500 mil

1 2

RC5 200_0402_1%RC5 200_0402_1%

1 2

RC6 80.6_0402_1%RC6 80.6_0402_1%

1 2

RC7 162_0402_1%RC7 162_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P08-MCP(2/14)LPDDR3

LA-C881P

8 59Tuesday, October 13, 2015

1.0

DDR_VTT_CNTL

A A

74AUP1G07GW_TSSOP5

SPI_MOSI= SPI_IO0 SPI_MISO= SPI_IO1 PCH EDS R0.7 p.235~236

PCH_SPI_CLK

TPM_PIRQ#<28>

CL_DAT<29>

CL_CK<29>

CL_RST#<29>

SIO_RCIN#

IRQ_SERIRQ

PCH_SPI_SO PCH_SPI_SI PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0#

1 2

PCH_SPI_DO_XDP<15>

D D

+3V_PCH

RC13 10K_0402_5%RC13 10K_0402_5%

+3VS

RC16 10K_0402_5%RC16 10K_0402_5%

RC21 10K_0402_1%RC21 10K_0402_1%

C C

PCH_SPI_DO2_XDP<15>

1 2

RC10 1K_0402_1%RC10 1K_0402_1% RC11 1K_0402_1%RC11 1K_0402_1%

MEDIACARD_IRQ#

SIO_RCIN#

IRQ_SERIRQ

1 2

PCH_SPI_CS2#<28>

MEDIACARD_IRQ#<24>

SIO_RCIN#<37>

IRQ_SERIRQ<37>

AW3

AW2 AU4 AU3 AU2 AU1

AW13

AY11

AV2

AV3

M2 M3

J4 V1 V2

G3 G2 G1

UCPU1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

KL-U_BGA1356

SKL-U

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

5 OF 20

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

MEM_SMBCLK MEM_SMBDATA PCH_SMB_ALERT#

GPP_C5

SML1_SMBCLK SML1_SMBDAT GPP_B23

PCI_CLK_LPC0 PCI_CLK_LPC1 CLKRUN#

SML1_SMBCLK <37>

SML1_SMBDAT <37>

LPC_AD0 <37 > LPC_AD1 <37 > LPC_AD2 <37 > LPC_AD3 <37 >

LPC_FRAME# < 37>

1 2

RC18 22_0402_5%RC18 22_0402_5%

1 2

RC22 22_0402_5%RC22 22_0402_5%

CLKRUN# <37>

MEM_SMBCLK

MEM_SMBDATA

+3VS

DMN66D0LDW-7_SOT363-6

3 4

QC2B

DMN66D0LDW-7_SOT363-6

CLK_PCI_MEC <37> CLK_LPC_DEBUG <37>

QC2A

DDR_XDP_SMBCLK

DDR_XDP_SMBDAT

DDR_XDP_SMBCLK <15>

DDR_XDP_SMBDAT

DDR_XDP_SMBCLK

CLKRUN#

MEM_SMBCLK

MEM_SMBDATA

SML1_SMBCLK

SML1_SMBDAT

DDR_XDP_SMBDAT <15>

1 2

RC12 1K_0402_5%RC12 1K_0402_5%

1 2

RC14 1K_0402_5%RC14 1K_0402_5%

1 2

RC15 1K_0402_5%RC15 1K_0402_5%

1 2

RC17 1K_0402_5%RC17 1K_0402_5%

+3VS

RN192.2K_0402_5% RN192.2K_0402_5%

RN202.2K_0402_5% RN202.2K_0402_5%

RC278.2K_0402_5% RC278.2K_0402_5%

+3V_PCH

ENABLE DISABLE

ESPI LPC

ENABLE DISABLE

+3V_PCH

RP5

1 2

1 8 2 7 3 6 4 5

33_8P4R_5%

RP6

1 8 2 7 3 6 4 5

33_8P4R_5%

SPI_SI_VROM

+3V_PCH

SPI_CLK_VROM

SPI_SO_VROM SPI_IO2_VROM SPI_IO3_VROM

RH59 1K_0402_5%~D@RH59 1K_0402_5%~D@

RH58 1K_0402_5%~D@RH58 1K_0402_5%~D@

RH56 1K_0402_5%~D@RH56 1K_0402_5%~D@

+3V_PCH

128Mb Flash ROM

UH8

PCH_SPI_CS0#

SPI_SO_VROM

SPI_IO2_VROM

B B

A A

/CS

DO(IO1)

/WP(IO2)

GND

W25Q128FVSIQ_SO8

/HOLD(IO3)

DI(IO0)

VCC

7 6

CLK

SPI_CLK_VROM

33_0402_5%

RC29@

1 2

33P_0402_50V8J

CC8@

1 2

CC9

1 2

0.1U_0402_25V6

SPI_IO3_VROM SPI_CLK_VROM SPI_SI_VROM

PCH_SPI_CLK_TPM<28> PCH_SPI_SI_TPM<28>

PCH_SPI_SO_TPM<28>

9/5 MOW Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the required 1 kOhm pull-up resistor(MOW WW5). In this case, customers must ensure that the SPI flash device on the platform has HOLD functionality disabled by default.

Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms with ES and SKL S/H platforms with pre-ES1/ES1 samples(MOW WW9).

PCH_SPI_SI

PCH_SPI_CLK

PCH_SPI_SO

PCH_SPI_IO2 PCH_SPI_IO3

PCH_SPI_IO2

PCH_SPI_IO3

CLK_PCI_MEC

CLK_LPC_DEBUG

Reserve for RF

@12P_0402_50V8J

CC4

@12P_0402_50V8J

CC5

PCH_SMB_ALERT#

TLS CONFIDENTIALITY

HIGH LOW(DEFAULT)

GPP_C5

1 2

RC23 8.2K_0402_5%RC23 8.2K_0402_5%

1 2

RC25 10K_0402_5%@RC25 10 K_0402_5%@

EC interface

HIGH LOW(DEFAULT)

GPP_B23

1 2

RC26 4.7K_0402_5%@RC 26 4.7K_0402_5%@

EXI BOOT STALL BYPASS

HIGH LOW(DEFAULT)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document Number R ev

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P09-MCP(3/14)SPI,SMB,LPC

LA-C881P

9 59Tuesday, October 13, 2015

1.0

+3VS

1 2

HOST_SD_WP#

SIO_EXT_SCI#

UART1_TXD

UART1_RXD

SIO_EXT_WAKE#

KB_DET#

I2C1_SDA_TP

I2C1_SCK_TP

USB2_PWR_EN

TBT_PWR_EN

D D

C C

RC292 10K_0402_5%RC292 10K_0402_5%

RC237 10K_0402_5%RC237 10K_0402_5%

RH562 49.9K_0402_1%RH562 49.9K_0402_1%

RH563 49.9K_0402_1%RH563 49.9K_0402_1%

+3V_PCH

RC283 10K_0402_5%RC283 10K_0402_5%

RC288 100K_0402_5%~DRC288 100K_0402_5%~D

RC284 4.7K_0402_5%RC284 4.7K_0402_5%

RC285 4.7K_0402_5%RC285 4.7K_0402_5%

RC293 10K_0402_5%RC293 10K_0402_5%

RH556 100K_0402_5%~DRH556 100K_0402_5%~D

UCPU1F

LPSS ISH

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

NRB_BIT

PAD~D

SIO_EXT_SCI#

GPP_B22

HOST_SD_WP#

SIO_EXT_WAKE#

I2C1_SDA_TP I2C1_SCK_TP

SIO_EXT_SCI#<37>

3.3V_TS_EN<33>

UART0_TX<37>

HOST_SD_WP#<24>

SIO_EXT_WAKE#<37>

T125

I2C0_SDA_EDP_PCH<25>

I2C0_SCK_EDP_PCH<25>

I2C1_SDA_TP<36>

I2C1_SCK_TP<36>

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA

GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

KL-U_BGA1356

TPM_DET

SKL-U

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BD ATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK /I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALE RT#

TPM@

1 2

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_R XD

GPP_C13/UART1_TXD/ISH_UART1_TX D GPP_C14/UART1_RTS#/ISH_UART1_R TS# GPP_C15/UART1_CTS#/ISH_UART1_C TS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

+3V_PCH

RH148100K_0402_5%

RH153100K_0402_5%

6 OF 20

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

DDR_CHB_EN DDR_CHA_EN

UART1_RXD UART1_TXD

KB_DET#

USB2_PWR_EN TBT_PWR_EN TPM_DET

T124

PAD~D

T121

PAD~D

KB_DET# <35>

AUD_PWR_EN <33> USB2_PWR_EN <31>

DDR_CHA_EN

DDR_CHB_EN

DDR_CHA_EN

DDR_CHB_EN

1 2

RH440 100K_0402_5%~DRH440 100K_0402_5%~D

1 2

RH441 100K_0402_5%~DRH441 100K_0402_5%~D

1 2

RH442 SHORT PADS@RH442 SHORT PADS@

1 2

RH443 SHORT PADS@RH443 SHORT PADS@

+3VS

+3V_PCH

1 2

RC186 4.7K_0402_5%

NRB_BIT

NO REBOOT STRAP

B B

HIGH LOW(DEFAULT) Weak IPD

+3V_PCH

RC184

8.2K_0402_5%

GPP_B22

No REBOOT REBOOT ENABLE

TPM BOM Optional

TPM_DET

1 = W/TPM

TPM

0 = W/O TPM

+5VS

JUART

UART1_TXD UART1_RXD

GND

ACES_50207-00471-P01

CONN@

BOOT BIOS Destination(Bit 6)

HIGH LOW(DEFAULT)

A A

LPC SPI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P10-MCP(4/14)GSPI,I2C,UART,ISH

LA-C881P

10 59Tuesday, October 13, 2015

1.0

D D

Alpine Ridge PCIe Gen3 x 2

WLAN PCIe Gen2 x 1

Cardreader PCIe Gen2 x 1

C C

M.2 SSD PCIe Gen3 x 4

B B

+3VS

1 2

RC245 10K_0402_5%RC245 10K_0402_5%

SATA SSD

PCIE_PRX_TBTX_N1<39> PCIE_PRX_TBTX_P1< 39> PCIE_PTX_TBRX_N1<39> PCIE_PTX_TBRX_P1< 39>

PCIE_PRX_TBTX_N2<39> PCIE_PRX_TBTX_P2< 39> PCIE_PTX_TBRX_N2<39> PCIE_PTX_TBRX_P2< 39>

PCIE_PRX_WLANTX_ N5<29> PCIE_PRX_WLANTX_ P5<29> PCIE_PTX_WLANRX_ N5<29> PCIE_PTX_WLANRX_ P5<29>

PCIE_PRX_CARDTX_N6<24> PCIE_PRX_CARDTX_P6<24> PCIE_PTX_CARDRX_N6<24> PCIE_PTX_CARDRX_P6<24>

PCIE_PRX_SSDTX_N9<30> PCIE_PRX_SSDTX_P9<30> PCIE_PTX_SSDRX_N9<30> PCIE_PTX_SSDRX_P9<30>

PCIE_PRX_SSDTX_N10<30> PCIE_PRX_SSDTX_P10<30> PCIE_PTX_SSDRX_N10<30> PCIE_PTX_SSDRX_P10<30>

RC45 100_0402_1%R C45 100_0402_1%

PCIE_PRX_SSDTX_N11<30> PCIE_PRX_SSDTX_P11<30> PCIE_PTX_SSDRX_N11<30> PCIE_PTX_SSDRX_P11<30> SATA_PRX_SSDTX_N2<30> SATA_PRX_SSDTX_P2<30> SATA_PTX_SSDRX_N2<30> SATA_PTX_SSDRX_P2<30>

1 2

CPU_XDP_PREQ#<15> CPU_XDP_PRDY#<15>

UCPU1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

PCIE_RCOMPN PCIE_RCOMPP

PCIE_RCOMPN

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KL-U_BGA1356

SKL-U

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

8 OF 20

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

R07_0720: Add GPIO to disable SATA#1

USB3RN1 <24> USB3RP1 <24> USB3TN1 <24>

USB3TP1 <24>

USB3RN2 <31> USB3RP2 <31> USB3TN2 <31>

USB3TP2 <31>

USB20_N1 <24> USB20_P1 <24>

USB20_N2 <31> USB20_P2 <31>

USB20_N3 <29> USB20_P3 <29>

USB20_N4 <25> USB20_P4 <25>

USB20_N5 <25> USB20_P5 <25>

USBCOMP

RC44 113_0402_1%R C44 113_0402_1%

USB2_ID

RC19 0_0402_1%@RC19 0_0402_1%@

VBUSSENSE

RC20 1K_0402_5%RC20 1K_0402_5%

TBT_USB_OC0# USB_OC1# USB_OC2# USB_OC3#

1 2

GPP_E1

RC51 0_0201_5%RC51 0_0201_5%

USB3.0 IO/B Side

USB3.0 M/B Side

USB2.0 IO/B Side

USB2.0 M/B Side

NGFF (WLAN)

Touch Panel

Camera

1 2 1 2 1 2

TBT_USB_OC0# <41> USB_OC1# <24> USB_OC2# <31>

SSD_DEVSLP < 30>

SSD_IFDET <30>

+3V_PCH

TBT_USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P11-MCP(5/14)PCIE,USB,SATA

LA-C881P

1 2

RC189 10K_0402_5%RC189 10K_0402_5%

1 2

RC185 10K_0402_5%RC185 10K_0402_5%

1 2

RC188 10K_0402_5%RC188 10K_0402_5%

1 2

RC191 10K_0402_5%RC191 10K_0402_5%

11 59Tuesday, October 13, 2015

1.0

Alpine Ridge--->

D D

WLAN--->

SDD--->

Card Reader --->

+3V_PCH_DSW

C C

B B

1 2

RC67 1K_0402_5%RC67 1K_0 402_5%

1 2

RC95 10K_0402_5%RC95 10K_0402_5%

+3VS

1 2

RC225@ 8.2K_0402_5%RC225@ 8.2K_0402_5%

+1.0V_VCCST

1 2

RC71 1K_0402_5%RC71 1K_0 402_5%

+3V_PCH

1 2

RC74 10K_0402_5%@RC74 10K_0402_ 5%@

H_VCCST_PWRGD_P<15,36>

100P_0402_50V8J~D

CA35

CLK0_PCIE_TBT#<39> CLK0_PCIE_TBT<39>

CLKREQ_PCIE#0<39>

CLK1_PCIE_WLAN#<29> CLK1_PCIE_WLAN<29>

CLKREQ_PCIE#1<29>

CLK_PCIE_SSD#<30> CLK_PCIE_SSD<30>

CLKREQ_PCIE#3<30>

CLK_PCIE_MMI#<24> CLK_PCIE_MMI<24>

CLKREQ_PCIE#5<24>

PCH_PCIE_WAKE#

LAN_WAKE#

ME_RESET#

H_VCCST_PWRGD_P

ME_SUS_PWR_AC K

PAD~D

H_VCCST_PWRGD_PH_CPUPWRGD

100P_0402_50V8J~D

CA32

1 2

RC63 10K_0402_5%@R C63 10K_0402_5%@

+3VS

1 2

RC47 10K_0402_5%RC47 10K_0402_5%

+3VS

1 2

RC49 10K_0402_5%RC49 10K_0402_5%

+3VS

1 2

RC59 10K_0402_5%RC59 10K_0402_5%

+3VS

1 2

RC50 10K_0402_5%RC50 10K_0402_5%

+3VS

1 2

RC190 10K_0402_5%RC190 10K_0402_5%

+3VS

PCH_PLTRST#_EC<24,28,29,30,37,39>

PCH_RSMRST#<15,37>

1 2

RC75 10K_0402_5%RC75 10K_0402_5%

1 2

RC77 1K_0402_5%@RC77 1K_0402_5%@

1 2

RC78 60.4_0402_1%RC78 60.4_0402_1%

RESET_OUT#<15,37> PCH_PWROK<53>

PCH_DPWROK_R<37>

ME_SUS_PWR_AC K<37>

SUSACK#<37>

PCH_PCIE_WAKE#<37>

LAN_WAKE#<37>

3.3V_CAM_EN#<33>

PCH_RSMRST#

ME_SUS_PWR_AC K

PCH_PCIE_WAKE# LAN_WAKE#

ESD Request:pla ce near CPU si de

RC215

POP

NO Support Deep sleep

DE-POP

Support Deep sleep

RC215 0_0402_5%

0.01U_0402_16V7K

100K_0402_5%~D

CC266

RC220

1 2

PCH_DPWROK_R PCH_RSM RST#

A A

XDP_DBRESET#<15>

if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40

AU8

E40 E38

AU7

100K_0402_5%

PCH_PLTRST# SYS_RESET#

H_CPUPWRGDH_CPUPWRGD_R VCCST_PWRGDH_VCCST_PWRGD_P

UCPU1J

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

KL-U_BGA1356

RC65

UCPU1K

AN10

GPP_B13/PLTRST#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWR OK

AR13

GPP_A13/SUSWARN#/SUS PWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KL-U_BGA1356

XDP_DBRESET#

RC227@ 8.2K_0402_5%RC227@ 8.2K_0402_5%

SKL_ULT

CLOCK SIGNALS

1 2

RC226 0_0402_5%

+3VS

UC7

TC7SH08FU_SSOP5~D

SYSTEM POWER MANAGEMENT

1 2

RC290 0_0402_1%@RC290 0_0402_1%@

+3VS

ME_RESET#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_OUT

XCLK_BIASREF

1 2

SKL-U

GPP_B11/EXT_PWR_GATE#

UC12@

74AHC1G09GW_TSSOP5

1 2

SUSCLK

RC48 1K_0402_5%@RC48 1K_0402_5%@

F43

CLK_ITPXDP_N_R

E43

CLK_ITPXDP_P_R

BA17

SUSCLK

E37 E35

E42

AM18 AM20

AN18 AM16

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

RC52 2.7K_0402_1%RC52 2.7K_0402_1%

PCH_RTCX1 PCH_RTCX2

SRTCRST#

PCH_RTCRST#

XTAL24_IN

RTCX1 RTCX2

SRTCRST#

RTCRST#

10 OF 20

CMOS1 must take care short & touch risk on layout placement

PCH_PLTRST#

RC85

@RC85

10K_0402_5%

PCH_BATLOW#

AC_PRESENT

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B2/VRALERT#

SYS_RESET#_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

AT11 AP15 BA16 AY16

AN15

SLP_SUS#

AW15

SLP_LAN#

BB17 AN16

BA15 AY15 AU13

AU11 AP16

INTRUDER#

AM10 AM11

11 OF 20

1 2

RC224 1K_0402_5%RC224 1K_0402_5%

1 2

RC297 0_0402_1%@RC297 0_0402_1%@

1 2

RC298 0_0402_1%@RC298 0_0402_1%@

SUSCLK < 29,30>

1 2

RC56 20K_0402_5%RC56 20K_0402_5%

1 2

CC24 1U_0402_6.3V6KCC24 1U_0402_6.3V6K

1 2

RC57 20K_0402_5%RC57 20K_0402_5%

1 2

CC25 1U_0402_6.3V6KCC25 1U_0402_6.3V6K

SHORT PADS~D

CMOS1

1 2

RC72 8.2K_0402_5%RC72 8.2K_0402_5%

1 2

RC243 10K_0402_5%RC243 10K_0402_5%

SIO_SLP_S0# SIO_SLP_S3# SIO_SLP_S4# SIO_SLP_S5#

AC_PRESENT PCH_BATLOW#

PME# INTRUDER#

VRALERT#

+3VS

SYS_RESET#

2013/07/04 2013/10/28

SIO_SLP_S0# <28,34,56> SIO_SLP_S3# <36,37,39> SIO_SLP_S4# <36,37> SIO_SLP_S5# <37>

SIO_SLP_SUS# <33,36,37,50,51,56>

PAD~D

SIO_SLP_WLAN# <37> SIO_SLP_A# <37>

SIO_PWRBTN# <15,37>

AC_PRESENT <37>

PAD~D

MPHYP_PWR_EN <34>

RC291

10K_0402_5%

Compal Secret Data

+1.0V_CLK

+3V_PCH_DSW

T116

T115

Deciphered Date

CLK_ITPXDP_N <15> CLK_ITPXDP_P <15>

XTAL24_IN XTAL24_OUT

R04_0609: Remov e RC295 for la yout limitation

PCH_RTCX1 PCH_RTCX2

+RTCVCC

INTRUDER#

VRALERT#

SLP_S0# for support connect stand by mode

8/21 CRB1.0 change to 0603 1/10W

1 2

RC69 330K_0402_5 %RC69 330K_0402_ 5%

1 2

RC73 10K_0402_5%RC73 10K_0402_5%

1M_0402_1%

1 2

+RTCVCC

+3V_PCH

RC46

CC21

1 2

15P_0402_50V8J

YC1

YC1 24MHZ_12PF_X3G024000DC1H

24MHZ_12PF_X3G024000DC1H

CC22

1 2

15P_0402_50V8J

CC23

1 2

6.8P_0402_50V8J

YC2

YC2 9PF 20PPM 9H03280012

9PF 20PPM 9H03280012

ESR MAX=50k ohm

CC26

1 2

6.8P_0402_50V8J

RC54

RC54 10M_0402_5%

10M_0402_5%

1 2

PCH_RTCX2_R

RC296 0_0402_1%

R04_0609: Fine tune cap by ve ndor suggestion

APS CONN

JAPS1

+3V_PCH

PBTN_SW#<24,37>

+3VALW

SIO_SLP_S3#

SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A#

PCH_RTCRST#

SYS_RESET#

SIO_SLP_S0#

GND

CONN@

ACES_50506-01841-P01

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P12-MCP(6/14)CLK,PM,RTC

LA-C881P

12 59Tuesday, October 13, 2015

1.0

+1.0V_VCCST

+1.0V_VCCSTG

D D

C C

1 2

RC79 49.9_0402_1%@RC79 49.9_0402_1%@

1 2

RC80 1K_0402_5%RC80 1K_0402_5%

1 2

RC83 1K_0402_5%RC83 1K_0402_5%

+3VS

1 2

RC272 10K_0402_5%RC272 10K_0402_5%

1 2

RC277 10K_0402_5%RC277 10K_0402_5%

1 2

RC246 10K_0402_5%@ RC246 10K_0402_5%@

+3V_PCH

1 2

RC236 10K_0402_5%RC236 10K_0402_5%

H_CATERR#

H_THERMTRIP#

H_PROCHOT#

TOUCHPAD_INTR#

TOUCH_SCREEN_PD#

EC_SLP_S0IX#

SIO_EXT_SMI#

PTP_INT#_EC<36,37>

H_PROCHOT#<37,46,47,53>

H_THERMTRIP#<37>

DZ3

DZ3 RB751S40T1G_SOD523-2

RB751S40T1G_SOD523-2

1 2

PECI_EC<37>

TOUCHPAD_INTR#

1 2

RC84 499_0402_1%RC84 499_0402_1%

XDP_OBS0_R<15> XDP_OBS1_R<15>

T10

PAD~D

T11

PAD~D

SIO_EXT_SMI#<37>

TOUCH_SCREEN_PD#<25>

EC_SLP_S0IX#<37>

RC89

RC88

49.9_0402_1%

H_CATERR#

H_PROCHOT#_RH_PROCHOT# H_THERMTRIP#

XDP_OBS2_R XDP_OBS3_R

SIO_EXT_SMI# TOUCH_SCREEN_PD# TOUCHPAD_INTR#

CPU_POPIRCOMP PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

EOPIO_RCOMP

RC90

RC91

49.9_0402_1%

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

UCPU1D

KL-U_BGA1356

CPU MISC

SKL-U

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

4 OF 20

B61

TCLK_XDP

D60

TDI_XDP

A61

TDO_XDP

C60

TMS_XDP

B59

TRST#_XDP

B56

PCH_JTAG_TCLK

D59

TDI_XDP

A56

TDO_XDP

C59

TMS_XDP

C61

TRST#_XDP

A59

TCLK_XDP

TCLK_XDP <15> TDI_XDP <15> TDO_XDP <15> TMS_XDP <15> TRST#_XDP <15>

PCH_JTAG_TCLK <15>

1 2

RC87 1K_0402_5%@RC 87 1K_0402_5%@

TDI_XDP

51_0402_5%

TDO_XDP

51_0402_5%

TMS_XDP

51_0402_5%

PCH_JTAG_TCLK

+1.0V_VCCSTG

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT.

HDA_SDOUT

ME_FWP_EC<37>

RH241K_0402_5%~D RH241K_04 02_5%~D

R11910_0402_5%~D R11910_0402 _5%~D

RC86 51_0402_5%

+3VS_AUDIO

RC9 1K_0402_5%

1K_0402_5%

ME_EN

@RC9

SW1

1 2 3

SSAL120100_3P

+1.0V_VCCSTG

RC81

RC82

RC130

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

SKL-U

UCPU1G

AUDIO

1 2

HDA_SYNC_R<26>

HDA_BIT_CLK_R<26>

HDA_SDOUT_R<26>

HDA_BIT_CLK_R

CC27

B B

CC27

22P_0402_50V8J

Close to RC93

RTD3_CIO_PWR_EN<39> TBT_FORCE_PWR<39>

RC92 33_0402_5%RC92 33_0402_5%

1 2

RC93 33_0402_5%RC93 33_0402_5%

1 2

RC94 33_0402_5%RC94 33_0402_5%

RC248 0_0402_1%@RC248 0_0402_1%@ RC247 0_0402_1%@RC247 0_0402_1%@

HDA_SYNC HDA_BIT_CLK HDA_SDOUT

HDA_SDIN0<26>

12 12

SPKR<26>

PCH_RTD3_CIO_PWR_E N PCH_TBT_FORCE_PW R

SPKR

BA22 AY22 BB22 BA21 AY21

AW22

T192PAD~D @T192PAD~D @

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK

GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

KL-U_BGA1356

AUDIO

SKL-U

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

7 OF 20

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

CAM_CBL_DET#

SD_RCOMP

1 2

RC96 200_0402_1%RC96 200_0402_1%

CAM_CBL_DET# <25>

TBT_CIO_PLUG_EVENT# <39>

SSD_PWR_EN <33>

SD_PWR_EN <33>

Disable ME Protect (ME can be updated) ----> Pin1 & Pin2 short Enable ME Protect (ME cannot be updated)-->Pin3 & Pin2 short(Default position)

CAM_CBL_DET#

1 2

RC280 100K_0402_5%~DRC280 100K_0402_5%~D

+3VS

+3V_PCH +3V_PCH

A A

1 2

RC183 8.2K_0402_5%

SPKR HDA_SDOUT

TOP SWAP STRAP

HIGH LOW(DEFAULT)

ENABLE DISABLE

1 2

RC187 4.7K_0402_5%

Flash Descriptor Security override

HIGH LOW(DEFAULT)

DISABLE ENABLE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document Number R ev

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P13-MCP(7/14)MISC,JTAG,HDA,SDIO

LA-C881P

13 59Tuesday, October 13, 2015

1.0

D D

1 2

RC113 10K_0402_1%

CFG0

Stall reset sequence

HIGH(DEFAULT) LOW

C C

RC109 10K_0402_1%RC109 10K_0402_1%

No stall(Normal Operation) stall

1 2

CFG4

eDP enable

HIGH(DEFAULT) LOW

B B

Disabled Enabled

RC112 10K_0402_1%

RC110 10K_0402_1%

+1.0VA_XDP

1 2

CFG16<15> CFG17<15>

CFG18<15> CFG19<15>

@ @

PAD~D

PAD~D PAD~D

PAD~D

CFG_RCOMP

ITP_PMODE

RC114 49.9_0402_1%RC114 49.9_0402_1%

RC115 1.5K_0402_5%RC115 1.5K_0402_5%

ITP_PMODE<15>

T16

T16 T17

T17

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

AL25 AL27

BA70 BA68

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

AY2 AY1

D1 D3

K46 K45

C71 B70

F60

A52

J71 J68

F65 G65

F61 E61

UCPU1S

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

KL-U_BGA1356

CFG[0..15]<15>

RESERVED SIGNALS-1

SKL-U

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

RC120 100K_0402_5%RC120 100K_0402_5%

1 2

PAD~D

PAD~D PAD~D

PAD~D

PAD~D PAD~D

PAD~D

PAD~D PAD~D

PAD~D

PAD~D PAD~D

PAD~D

PAD~D PAD~D

PAD~D

T12

T13

T14

T15

T128

T129

T130

T126

T127

LPM_ZVM_N <57>

T113

T114

MSM_N <57>

ZVM# for SKYLAKE-U 2+3e

MSM# for SKYLAKE-U 2+3e

+1.0V_VCCST

AW69 AW68

AU56

AW48

C7 U12 U11 H11

UCPU1T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

KL-U_BGA1356

SPARE

SKL-U

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

20 OF 20

F6 E3 C11 B11 A11 D12 C12 F52

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P14-MCP(8/14)CFG,RSVD

LA-C881P

14 59Tuesday, October 13, 2015

1.0

+1.0VA

RC216

RC216 0_0603_5%

0_0603_5%

1 2

D D

C C

B B

Place near JXDP1

+1.0VS_VCCIO

+1.0V_VCCST

+1.0VA_XDP

0.1U_0402_10V7K

@CC28

CC28

H_VCCST_PWRGD_P<12,36>

PCH_RSMRST#<12,37>

PCH_SPI_DO_XDP<9>

1 2

RC132 150_0402_5%

1 2

RC218 150_0402_5%

1 2

RC219 10K_0402_5%

1 2

RC138

CC33@ 0.1U_0402_25V 6CC33@ 0.1U_0402_25V6

Place near JXDP1.47

RESET_OUT#<12,37>

0.1U_0402_10V7K

@CC29

CC29

FIVR_EN_R

FIVR_EN

CPU_XDP_PREQ#

51_0402_5%

RESET_OUT#_R

+1.0VA_XDP

XDP_OBS0_R<13> XDP_OBS1_R<13>

PCH_SPI_DO_XDP

RC5 need to close to JCPU1

1 2

RC123 1K_0402_5%@ RC123 1K_0402_5%@

1 2

RC124CXDP@

FIVR_EN CFG0

1K_0402_5%

CPU XDP

CPU_XDP_PREQ#<11> CPU_XDP_PRDY#<11>

RC239 0_0402_5%CXDP@ RC239 0_0402_5%CXDP@ RC240 0_0402_5%CXDP@ RC240 0_0402_5%CXDP@

1 2

RC217 0_0402_5%@ RC217 0_0402_5%@

1 2

RC126 1K_0402_5%

1 2

RC128 0_0402_5%CXDP@ RC128 0_0402_5%CXDP@

1 2

RC129 0_0402_5%@RC129 0_0402_5%@

DDR_XDP_SMBDAT<9>

DDR_XDP_SMBCLK<9>

1 2 1 2

SIO_PWRBTN#<12,37>

PCH_JTAG_TCLK<13>

CFG0<14> CFG1<14>

CFG2<14> CFG3<14>

CFG4<14> CFG5<14>

CFG6<14> CFG7<14>

H_VCCST_PWRGD_XD P

TCLK_XDP<13>

+3V_PCH

CPU_XDP_PREQ#

CFG0

CFG3

XDP_OBS0 XDP_OBS1

SIO_PWRBTN#

FIVR_EN_R

RESET_OUT#_R

TCLK_XDP

RC133

1.5K_0402_5%

PCH_SPI_DO_XDP

+1.0VA_XDP

XDP_PRSNT_PIN1 CFG3

JXDP1

GND0

OBSFN_A0

OBSFN_A1

GND2

OBSDATA_A0

OBSDATA_A1

GND4

OBSDATA_A2

OBSDATA_A3

GND6

OBSFN_B0

OBSFN_B1

GND8

OBSDATA_B0

OBSDATA_B1

GND10

OBSDATA_B2

OBSDATA_B3

GND12 PWRGOOD/HOOK039ITPCLK/HOOK4

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

GND14

SDA

SCL

TCK1

TCK0

GND16

CXDP@

1 2

RC121 1K_0402_5%

1 2

RC122 0_0402_5%@ RC122 0_0402_5%@

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

XDP_DBRESET#

Place near JXDP1.48

GND1 OBSFN_C0 OBSFN_C1

GND3

GND5

GND7 OBSFN_D0 OBSFN_D1

GND9

GND11

GND13

GND15

TD0

TRST#

TMS

GND17

CONN@SAMTE_BSH-030-01-L-D-A

+1.0VA_XDP

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

+3VS

1K_0402_5%

0.1U_0402_25V6

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

XDP_DBRESET#

RC137

CXDP@ CC32

CXDP@

CC32

Place near JXDP1.41

CFG17 <14> CFG16 <14>

CFG8 <14> CFG9 <14>

CFG10 <14> CFG11 <14>

CFG19 <14> CFG18 <14>

CFG12 <14> CFG13 <14>

CFG14 <14> CFG15 <14>

CLK_ITPXDP_P <12> CLK_ITPXDP_N <12>

ITP_PMODE <14>

XDP_DBRESET# <12>

TDO_XDP <13> TRST#_XDP <13> TDI_XDP <13> TMS_XDP<1 3> PCH_SPI_DO2_XDP <9>

+3V_PCH_DSW

SIO_PWRBTN#

+1.0V_VCCSTG

TMS_XDP

51_0402_5%

TDI_XDP

51_0402_5%

TDO_XDP

51_0402_5%

TRST#_XDP

51_0402_5%

TCLK_XDP

51_0402_5%

1.5K_0402_5%

RC241

0.1U_0402_25V6

@CC269

CC269

RC131

RC134

RC135

RC136

RC139

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P15-MCP(9/14)XDP

LA-C881P

15 59Tuesday, October 13, 2015

1.0

PSC(Primary side cap) : Place as close to the package as possible BSC(Backside cap) : Place on secondary side, underneath the package

Component placement order: Package edge > 0402 caps > 0805 caps > Bulk caps >Power source

D D

+VCC_EDRAM: 1V, 2.5A +V1.8S_EDRAM: 1.8V, 50mA

+VCC_CORE: 0.55~1.5V, 29A

+1.8VA

R1334

R1334 0_0603_5%

0_0603_5%

1 2

+V1.8S_EDRAM

+VCC_EOPIO: 0.8~1V, 2A

T122

PAD~D

T123

PAD~D

VCC_EDRAM_SENSE<57> VSS_EDRAM_SENSE<57>

VCC_EOPIO_SENSE<57> VSS_EOPIO_SENSE<57>

CC187

10U_0402_6.3V6M

PAD~D

RC232 @ 0_0603_5%RC232 @ 0_0603 _5%

10U_0402_6.3V6M

+VCC_EDRAM

+V1.8S_EDRAM

+VCC_EOPIO

C C

+VCC_EDRAM Deco upling Requirm ent Back Side (unde rneath the pac kage): 10U_0402*1 pcs + 1U_0201*6 pc s

+VCC_EDRAM +VCC_EOPIO

+VCC_EOPIO Deco upling Requirm ent Back Side (unde rneath the pac kage): 10U_0402*2 pcs

BSC BSC

CC180

B B

10U_0402_6.3V6M

CC183

1U_0201_6.3V6M

CC188

CC189

CC190

CC191

CC192

1U_0201_6.3V6M

CC192

1U_0201_6.3V6M

CC184

+VCC_CORE +VCC_CORE

+VCC_CORE_G0

+VCC_CORE_G1

1 2

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e (w/ on package cache)

AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

AK32

AB62

G61

AC63 AE63

AE62 AG62

AL63

AJ62

A30 A34 A39 A44

K32

P62 V62

H63

UCPU1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

KL-U_BGA1356

CPU POWER 1 OF 4

1.5V@29A

V@2.5A

1V@2A

SKL-U

1V@0.05A

VCC_SENSE VSS_SENSE

VCCSTG_G20

SVID ALERT

VIDALERT_N<53>

SVID DATA

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VIDALERT#

VIDSCK

VIDSOUT

12 OF 20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32

VCCSENSE

E33

VSSSENSE

B63

H_CPU_SVIDALRT#

A63

VIDSCLK_R

D64

VIDSOUT_R

G20

+1.0V_VCCSTG_R

+1.0V_VCCST

RC143 @ 0_0603_5%RC143 @ 0_0603_5%

56_0402_1%

RC152

100_0402_1%

RC157

+VCC_CORE

Close CPU

RC140

100_0402_1%

VCCSENSE <53>

1 2

CAD Note: Place the PU resistors close to CPU

VSSSENSE <53>

RC141

100_0402_1%

+1.0V_VCCSTG

RC204 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

RC153220_0402_5% RC153220_0402_5%

RC208close to CPU 300 - 1500mils

VIDSOUT<53>

SVID CLK

VIDSCLK<53>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

+1.0V_VCCST

Deciphered Date

100_0402_1%

@RC158

RC158

CAD Note: Place the PU resistors close to CPU

VIDSOUT_R

RC1540_0402_1%

RC208close to CPU 300 - 1500mils

VIDSCLK_R

RC1550_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Title

P16-MCP(10/14)PWR-VCC CORE

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LA-C881P

1.0

16 59Tuesday, October 13, 2015

1.0

+VCCGT: 0.55~1.5V, 54A +VCCGTX : 0.55~1.5V, 7A

D D

C C

Close CPU

VCC_GT_SENSE<53>

B B

VSS_GT_SENSE<53>

+VCC_GT +VCC_GT

+VCC_GT

RC161

100_0402_1%

VCC_GT_SENSE VSS_GT_SENSE

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

M62

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58

J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71

N63 N64 N66 N67 N69

J70

J69

UCPU1M

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

KL-U_BGA1356

SKL-U

CPU POWER 2 OF 4

1.5V@54A

1.5V@7A

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

13 OF 20

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50

VCCGTX for SKYLAKE-U 2+3e

AL53 AL56

Merged the GT and GTx rail

AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GT

T195 PAD~D @T195 PAD~D @ T196 PAD~D @T196 PAD~D @

RC163

100_0402_1%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2013/07/04 2013/10/28

Compal Secret Data

Deciphered Date

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Title

ize Document Number R ev

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

P17-MCP(11/14)PWR-VCCGT

LA-C881P

17 59Tuesday, October 13, 2015

1.0

+1.2V_DDR: 1.2V, 3.5A +1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA +1.0V_VCCSTG: 1V, 40mA +VCCPLL_OC: 1.2V, 260mA +1.0VS_VCCIO: 0.85~0.95V, 3.1A

D D

C C

+VCC_SA: 1.15V, 5.1A

+1.2V_MEM_CPUCLK+1.2V_DDR

1 2

RC171 0_0402_1%

+1.0V_VCCST

PSC

close to package

CC195

1U_0402_6.3V6K

+1.0V_VCCSTG

BSC

underneath the package

CC199

@CC199

1U_0402_6.3V6K

+1.2V_MEM_CPUCLK

+VCCPLL_OC +1.0V_VCCST

PSC

CC261

1U_0201_6.3V6M

+1.2V_DDR

1V@0.12A

1V@0.04A

1.2V@0.26A

1V@0.12A

close to packageclose to package

PSC

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

UCPU1N

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

KL-U_BGA1356

CC202

1U_0402_6.3V6K

CPU POWER 3 OF 4

1.2V@3.5A

SKL-U

0.95V@3.1A

1.15V@5.1A

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

+VCC_SA

+1.0VS_VCCIO

AK28

VCCIO

AK30

VCCIO

AL30

VCCIO

AL42

VCCIO

AM28

VCCIO

AM30

VCCIO

AM42

VCCIO

AK23

VCCSA

AK25

VCCSA

G23

VCCSA

G25

VCCSA

G27

VCCSA

G28

VCCSA

J22

VCCSA

J23

VCCSA

J27

VCCSA

K23

VCCSA

K25

VCCSA

K27

VCCSA

K28

VCCSA

K30

VCCSA

AM23

VCCIO_SENSE

AM22

VSSIO_SENSE

H21 H20

14 OF 20

1 2

RC168 100_0402_1%RC168 100_0402_1%

+VCC_SA

+1.0VS_VCCIO

RC166

100_0402_1%

VSA_SEN- <53> VSA_SEN+ <53>

Close CPU

RC165

100_0402_1%

VCCIO_SENSE <56> VSSIO_SENSE <56 >

RC167

100_0402_1%

+1.2_DDR Decoup ling Requirmen t Back Side (unde rneath the pac kage): 10U_0402*2 pcs + 1U_0201*4 pc s (@) Primary Side (c lose to packag e): 10U_0402*4 pcs + 22U_0603*3 p cs

B B

+1.2V_DDR

PSC

CC31

CC34

22U_0603_6.3V6M

CC35

CC177

22U_0603_6.3V6M

10U_0402_6.3V6M

CC176

CC178

10U_0402_6.3V6M

CC176

CC179

10U_0402_6.3V6M

BSC

CC174

@CC174

10U_0402_6.3V6M

A A

CC258

CC175

@CC258

@CC175

1U_0201_6.3V6M

10U_0402_6.3V6M

CC259

@CC259

1U_0201_6.3V6M

CC257

CC256

@CC257

@CC256

1U_0201_6.3V6M

+1.0VS_VCCIO De coupling Requi rment Back Side (unde rneath the pac kage): 10U_0402*2 pcs + 1U_0201*4 pc s (@) Primary Side (c lose to packag e): 1U_0402*4 pcs

+1.0VS_VCCIO

PSC

CC252

1U_0402_6.3V6K

CC253

CC250

CC251

1U_0402_6.3V6K

BSC

CC248

CC249

@CC248

@CC249

10U_0402_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

CC182

@CC182

1U_0201_6.3V6M

CC185

CC186

@CC185

@CC186

1U_0201_6.3V6M

Compal Secret Data

Deciphered Date

CC181

@CC181

1U_0201_6.3V6M

2013/07/04 2013/10/28

+1.2V_MEM_CPUCL K (VDDQC) Plac e on CPU Back Side (unde rneath the pac kage): 1U_0201*1 pcs ( @) Primary Side (c lose to packag e): 10U_0402 * 1 pc s

+1.2V_DDR

BSCPSC

CC194

CC260

@CC260

10U_0402_6.3V6M

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

1U_0201_6.3V6M

Compal Electronics, Inc.

P18-MCP(12/14)PWR-VCCIO,MEM

LA-C881P

18 59Tuesday, October 13, 2015

1.0

+ 41 hidden pages

Dell XPS 13-9360 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual