Dell N4010 Schematics

5

4

3

2

1

Arsenal Discrete Schematics Document

D D

AMD Danube CPU S1G4

VGA ATI PARKS3-LP

RS880M + SB820M

C C

2010-05-07 REV : X01

DY : Nopop Component

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Arsenal DJ1 Discrete

1 89Friday, May 07, 2010

1

of

X01

5

2

28,

3

4

3

2

1

CHARGER

Project code :

Arsenal DJ1 Discrete Block Diagram

PCB P/N : Revision : 09915-1

AMD Champlain

D D

Clock Generator

ICS9LPRS480BKLFT

7

VRAM

64Mx16bx4 (512MB)

84,85

4

CPU S1G4

OUT

8,9,10,11

IN

DDR III 800/1066

HyperTransport 16X16

DDRIII 800/1066/1333

gDDR3 700MHz

ATI PARK-S3

CRT

C C

LCD

55

54

RGB CRT

LVDS

80,81,82,83

PCIe x 16

North Bridge

AMD RS880M

CPU I/F LVDS, CRT I/F

INTEGRATED GRAHPICS

12,13,14,15

PCIE x 1

USB 2.0 x 2

A-LINK 4X4

PCIE x 1 USB 2.0 x 1

CardReader

SD/SDIO/MMC MS/MS Pro/xD

B B

Internal Analog MIC

44

Realtek RTS5138

32

Azalia

USB2.0

AZALIA

CODEC

MIC IN

HP OUT

2CH SPEAKER

A A

5

& OP AMP

92HD79B1

30

4

South Bridge

AMD SB820M

14 USB 2.0 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

4 PCIE GPP

6 SATA ports

ACPI 1.1

LPC I/F

PCI/PCI BRIDGE

HDD

20,21,22,23,24

SATA

ODD

59 59

SATA

USB 2.0

SPI

Flash ROM

2MB

3

LPC Bus

NUVOTON

NPCE781BA0DX

Touch

62 68 25

PAD

DIMM1

18

DIMM2

19

I/O Board

Connector

76

10/100 NIC

ATHEROS AR8152

USB 2.0 x 1

Left Side: USB x 2

Mini-Card

802.11a/b/g

CAMERA (Option)

Bluetooth

Right Side: USB x 1

RJ45 CONN

73

63

KBC

37

ThermalInt.

68

KB

EMC2102

Fan

58

2

39

Title

Block Diagram

Size Document N umber Rev

A3

Date: Sheet of

Block Diagram

Arsenal DJ1 Discrete

BQ24745RHDR

INPUTS

+DC_IN_SS

+CHAGER_SRC

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

TPS51125RGER-GP

INPUTS

+PWR_SRC

OUTPUTS

+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

SYSTEM DC/DC

RT8209EGQW

INPUTS OUTPUTS

+1.1V_ALW+PWR_SRC

CPU CORE

ISL6265AHRTZ-T-GP

INPUTS

+PWR_SRC

OUTPUTS

+VCC_CORE +VDDNB

DDR III SUS&VTT

TPS51116RGER-GP-U

INPUTS

+PWR_SRC

OUTPUTS

+1.5V_SUS

SYSTEM DC/DC

APL5930KAI

INPUTS

+3.3V_ALW

OUTPUTS

+1.8V_RUN

+1.8V_DELAY

SYSTEM DC/DC

Swithes

INPUTS

+5V_ALW +5V_RUN

+1.5V_SUS

OUTPUTS

+3.3V_RUN+3.3V_ALW

+1.5V_RUN

+1.1V_RUN+1.1V_ALW

VGA

RT8208AGQW

INPUTS

OUTPUTS

+VCC_GFX_CORE+PWR_SRC

PCB LAYER

L1: Top L2: GND L3: Signal L4: Signal L5: VCC L6: Signal L7: GND L8: Bottom

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

2 89Friday, May 07, 2010

1

X01

46

48

47

49

52

53

86

A

B

C

D

E

Power Shape

Power Block Diagram

Regulator LDO Switch

4 4

Adapter

AO4407A

Battery

3 3

+3.3V_RTC_LDO

+PWR_SRC

Charger

+PBATT

G547F2P81U

+5V_USB1

TPS51125RGER

+5V_ALW

AO4468

+5V_RUN

ISL6265AHRTZ TPS51116RGERRT9025 RT8208AGQW RT8209EGQW

+VCC_CORE

+VDDNB(CPU)

VDDR(CPU)

+VCC_GFX_CORE

+1.1V_ALW

SI4634DY

G547F2P81U

+5V_USB2

+5V_ALW2

SI2301BDS

+3.3V_DELAY

AO4468

+3.3V_RUN

+3.3V_ALW

PA102FMG

+3.3V_LAN

+1.1V_RUN

AO4468

+1.1V_GFX_RUN

APL5930

+1.8V_RUN

+1.5V_SUS

AO4468

+1.5V_RUN

APL5930

+1.8V_DELAY

2 2

RESISTER

+PVDD

1 1

A

RESISTER

+AVDD

G5285T11U

+LCDVDD

B

RTS5138

+3.3V_RUN_CARD

RT9013-25PB

+2.5V_RUN

C

AR8152

+1.2V_LOM

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Power Block Diagram

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

3 89Friday, May 07, 2010

E

X01

5

4

3

2

1

SB820M SMBus Block Diagram

D D

+3.3V_RUN

SRN2K2J

SB820M

C C

SCL0

S

SCL1

SDA1

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

DA0

SB_SMBCLK

SB_SMBDATA

SMB_CLK

SMB_DATA

CPU_SIC

CPU_SID

+3.3V_ALW

SRN10K2J

SB_SMBCLK

SB_SMBDATA

SB_SMBCLK

SB_SMBDATA

SB_SMBCLK

SB_SMBDATA

DIMM 1

SCL

SDA

SMBus Address:A0

DIMM 2

SCL

SDA

SMBus Address:A4

CLOCK GEN

SCLK

SDATA

SMBus address:D2

NPCE781

KBC SMBus Block Diagram

+5V_RUN

SRN10KJ-5-GP

PSDAT1

KBC

GPIO61/SCL2

GPIO62/SDA2

PSCLK1

SCL1

SDA1

TPDATA

TPCLK

BAT_SCL

B

AT_SDA

KBC_SCL1

KBC_SDA1

+KBC_PWR

SRN4K7J-8-GP

SRN100J-3-GP

2N7002SPT

PBAT_SMBCLK1

PBAT_SMBDAT1

TPDATA

TPCLK

Battery Conn.

CLK_SMB

DAT_SMB

BQ24745RHDR

SCL

SDA

+3.3V_RUN

TouchPad Conn.

TPDATA

TPCLK

(In I/O Board)

SRN4K7J-8-GP

Thermal

THERM_SCL

SCL

THERM_SDA

SDA

SMBus address:16

SMBus address:12

SMBus address:7A

MINI CARD

SB_SMBCLK

B B

+1.5V_SUS

A A

5

4

SMB_CLK

SB_SMBDATA

SMB_DATA

SRN1K2J

SIC

CPU_SIC

SID

CPU_SID

SMBus address:98

CPU S1G4

ATI PARKLP-S3

3

DC1CLK

D

DDC1DATA

DDC2CLK

DDC2DATA

LDDC_CLK

LDDC_DATA

+3.3V_DELAY

M92CRT_DDCCLK

M92CRT_DDCDATA

SRN2K2J-8-GP

+3.3V_DELAY

2K2R2J-2-GP

2N7002SPT

LCD Conn.

+3.3V_DELAY

2

+5V_CRT_RUN

SRN2K2J-8-GP

DDC_CLK_CON

DDC_DATA_CON

CRT CONN

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

SMBUS BLOCK DIAGRAM

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

1

4 89Friday, May 07, 2010

X01

5

4

3

2

1

D D

C C

Thermal Block Diagram

CPU

DP1

DN1

H_THERMDA

SC470P50V3JN-2GP

H_THERMDC

THERMDA

THERMDC

Thermal EMC2102

DP2

DN2

VGA_THERMDA

SC470P50V3JN-2GP

VGA_THERMDC

DPLUS

DMINUS

GPU

Audio Block Diagram

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

HP1_PORT_B_L

HP1_PORT_B_R

Codec 92HD81

VREFOUT_A_OR_F

HP0_PORT_A_L

HP0_PORT_A_R

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

AUD_HP1_JACK_L

UD_HP1_JACK_R

A

AUD_VREFOUT_B

AUD_EXT_MIC_L

AUD_EXT_MIC_R

60D4R2F

4K7R2J-2-GP

Bead

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

SPEAKER

60

HP

OUT

60

MIC

IN

60

B B

EMC2102_DP3

DP3

DN3

SC470P50V3JN-2GP

EMC2102_DN3

PMBS3904

System sensor, put between CPU and NB.

A A

5

4

3

DMIC_CLK/GPIO1

DMIC0/GPIO2

PORT_C_L

PORT_C_R

VREFOUT_C

AUD_DMIC_CLK

AUD_DMIC_IN0

AUD_INT_MIC_R_L

AUD_VREFOUT_C

30

33R2J-2-GP

4K7R2J-2-GP

SC1U10V3KX-3GP

2

33R2J-2-GP

AUD_DMIC_CLK_G

AUD_DMIC_IN0_R

INT_MIC_L_R

Title

THERMAL/AUDIO BLOCK DIAGRAM

Size Document Number Rev

Custom

Date: Sheet of

Digital MIC Array

Internal MIC

Arsenal DJ1 Discrete

54

60

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5 89Friday, May 07, 2010

1

X01

5

4

3

2

1

SB820M Strapping

Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide

Name Strap Name Schematic Note

LPCCLK0

D D

EC_PWM3 EC_PWM2

LPCCLK1

PCICLK1

C C

ECEnableStrap

{ROMTYPE_1, ROMTYPE_0 }

CLKGEN

BIF_GEN2_ COMPLIANCE_Strap

PCICLK2 BootFailTmrEn

PCICLK3 DefaultStrapMode

Embedded Controller (EC)

0 V – Disabled

*

3.3 V - Enabled

ROMTYPE_1 ROMTYPE_0 ROM TYPE

3.3V 0V

3.3V 3.3V

0V 0V

0V 3.3V

*

LPC ROM (supports both LPC and PMC ROM types)

Defines clock generator

External clock mode: Use 100-M Hz PCIeR

*

0V –

clock as reference clock and g enerate i nternal clocks only.

Integrated clock mode: Use 25- MHz crystal

3.3V–

clock and generate both intern al and external clocks

Set PCIe to Gen II mode

Force PCIe interface at Gen I mode

0V–

PCIe interfacce is at Gen II m ode

3.3V-

*

Not Applicable to SB820M but p rovision for pull-down is required.

Watchdog function

Disable the boot fail timer fu nction

0V–

*

Enable the boot fail timer fu nction

3.3V-

Default Debug Straps

Disable Debug Straps.

0V–

*

Select external Debug Straps

3.3V–

SPI ROM

Reserved

Firmware Hub

NB880M Strapping

Capture from 46113_rs880m_ds_nda_1.03

DAC_VSYNC

DAC_HSYNC

SUS_STAT#

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESE

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

If BIOS_ROM_EN (GPIO22) = 0

Size of the primary memory apertures

128MB 256MB

V

64MB 32MB 512MB 1GB 2GB 4GB

STRAP_DEBUG_BUS_GPIO _ENABLE#

SIDE_PORT_EN#

LOAD_EEPROM_STRAPS#

ATI RESERVED CONFIGURATION STRAPS

H2SYNC , V2SYNC

If BIOS_ROM_EN (GPIO22) = 1

GPIO[13,12,11]

x000 x001 x010 x x x x x

Manufacturer Part Number GPIO[13,12,11]

ST Microelectronics

Chingis (formerly PMC)

Enables debug bus access through memory I/O pads and GPIOs. 0: Enable 1: Disable

*

Indicates if memory side-port is available or not 0: Available

*

1: Not available

Selects loading of strap values from EEPROM. 0: I2C master can load strap values from EEPROM if connected, or use default values if EEPROM is not connected. Please refer to RS880M's reference schematics for system level implementation details. 1: Use default values

*

M25P05A M25P10A M25P20 M25P40 M25P80

Pm25LV512A Pm25LV010A

0100 0101 0101 0101 0101

0100 0101

Schematic NoteStrap FunctionName

CPU/NB HT Clock Selection

Reserved.

PCICLK4 CPUClkSel

*

0V–

Required setting for integrate d clock mode.

3.3V–

This strap is not used if the strap CLKGEN is configured for external clock generator mode.

Slow down core clock for low power platform.

AZ_SDOUT CoreSpeedMode

B B

*

0V–

3.3V-

Performance mode

Low Power mode

USB Table

Pair

0 1 2 3 4 5 6 7

A A

8 9 10 11 12 13

USB

Device

USB2 USB3 USB0 (I/O Board) USB1 (I/O Board, 17") WLAN Reserve Reserve Reserve Reserve BLUETOOTH CARD READER CAMERA Reserve Reserve

5

PCIE SB820M

PCI-E Port Device Remark

Device 21

PCI-E Port #0

PCI-E Port #1

Onboard LAN

Mini Card

4

STRAPS PIN DESCRIPTION

TX_PWRS_ENB

(Internal PD)

TX_DEEMPH_EN

(Internal PD)

BIF_GEN2_EN_A

ROMIDCFG[3:0]

(Internal PD)

BIOS_ROM_EN

(Internal PD)

AUD[1] AUD[0]

(Internal PD)

VGA_DIS

(Internal PD)

GPIO_VGA_00

GPIO_VGA_01

GPIO_VGA_02

GPIO[13,12,11]

GPIO_22_ROMCSB

VGA_HSYNC

VGA_VSYNC

GPIO_VGA_09

Tansmitter Power Savings Enable

V

0= 50% Tx output swing 1= Full Tx output swing

Transmitter De-emphasis Enable

V

0= Tx de-emphasis disabled 1= Tx de-emphasis enabled

0 = Advertises the PCI-E device

V

as 2.5GT/s 1 = Advertises the PCI-E device as 5GT/s

if BIOS_ROM_EN=1,then Config[3:0] defines the ROM type if BIOS_ROM_EN=0,then Config[3:0]

V

defines the primary memory apeture size

Enable external BIOS ROM device

V

0= Disable external BIOS ROM device 1= Enable external BIOS ROM device

AUD[1:0]

V

00:No audio function 01:Audio for DisplayPort and HDMI ( if adapter is detected) 10:Audio for DisplayPort only 11:Audio for both DisplayPort and HDMI

0: VGA Controller capacity enabled

V

1: The device will not be recognized as the system's VGA controller

ATHEROS AR8132

WLAN

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Table of Content

Size Document Num ber Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

1

6 89Friday, May 07, 2010

X01

5

4

3

2

1

1'nd 68.00084.A31(MURATA) 2'nd

+3.3V_CLK_VDD+3.3V_RUN

R702

1 2

0R3J-0-U-GP

D D

SC10U6D3V5KX-1GP

C701

12

+3.3V_CLK_VDD (40 mils)

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

C703

C705

C704

12

SCD1U10V2KX-4GP

C706

12

SCD1U10V2KX-4GP

C707

C709

C708

12

+3.3V_RUN +3.3V_CLK_VDDIO

+3.3V_RUN +3.3V_CLK_VDDREF

C C

WLAN(100MHz)

LAN(100MHz)

B B

VGA(27MHz)

TP701TP701 TP702TP702 TP703TP703 TP704TP704 TP705TP705 TP706TP706 TP707TP707 TP708TP708 TP709TP709 TP710TP710

A A

EMI

EC704

SC4D7P50V2CN-1GPDYEC704

SC4D7P50V2CN-1GP

TP_CLK_SRC6

1

TP_CLK_SRC6#

1

TP_CLKREQ0#

1

TP_CLKREQ3#

1

TP_CLKREQ4#

1

TP_CLK_SRC4

1

TP_CLK_SRC4#

1

TP_CLKREQ2#

1

TP_CLK_SRC2

1

TP_CLK_SRC2#

1

12

DY

1 2

EC705

SC4D7P50V2CN-1GPDYEC705

SC4D7P50V2CN-1GP

DY

R703

0R3J-0-U-GP

R701

0R3J-0-U-GP

12

SC10U6D3V5KX-1GP

12

DY

SC2D2U6D3V3KX-GP

12

SB_PWRGD21,41

CLK_PCIE_MINI176 CLK_PCIE_MINI1#76

CLK_PCIE_LAN76 CLK_PCIE_LAN#76

CLK_VGA_27M_SS81 CLK_VGA_27M_NSS81

NB_GPPSB_CLK13 NB_GPPSB_CLK#13

SB_PCIE_CLK20 SB_PCIE_CLK#20

CLK_NBHT_CLK13 CLK_NBHT_CLK#13

CLK_VGA_27M_SS CLK_VGA_27M_NSS

5

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

C710

C711

12

SCD1U10V2KX-4GP

C721

C720

12

R706

1 2

0R2J-2-GP

2 3 1

X01

R713 47R2J-2-GPR713 47R2J-2-GP

1 2

R714 33R2J-2-GPR714 33R2J-2-GP

1 2

2 3 1

0923

SCD1U10V2KX-4GP

C712

DY

SCD1U10V2KX-4GP

C713

12

+3.3V_RUN

10KR2J-3-GP

12

4

SCD1U10V2KX-4GP

C714

12

+3.3V_CLK_VDDREF

R705

EC702

EC702 SC10P50V2JN-4GP

SC10P50V2JN-4GP

12

RN702

RN702 SRN0J-6-GP

SRN0J-6-GP

RN703

RN703 SRN0J-6-GP

SRN0J-6-GP

RN704

RN704 SRN0J-6-GP

SRN0J-6-GP

RN705

RN705 SRN0J-6-GP

SRN0J-6-GP

RN706

RN706 SRN0J-6-GP

SRN0J-6-GP

SCD1U10V2KX-4GP

C715

C716

12

+3.3V_CLK_VDDIO

CLKGEN_PD#

R_VGA_27M_SS_CLK R_VGA_27M_NSS_CLK

NB_GPPSB_CLK_R NB_GPPSB_CLK#_R

CLK_NBHT_CLK_R CLK_NBHT_CLK#_R

SCD1U10V2KX-4GP

C717

12

+3.3V_CLK_VDD

CLK_MINI1_R CLK_MINI1#_R TP_CLK_SRC2 TP_CLK_SRC2# LAN_CLK_R LAN_CLK#_R TP_CLK_SRC4 TP_CLK_SRC4# TP_CLK_SRC6 TP_CLK_SRC6#

SB_PCIE_CLK_R SB_PCIE_CLK#_R

4

0507

U701

26

VDDATIG

25

VDDATIG_IO

48

VDDCPU

47

VDDCPU_ IO

16

VDDSRC

17

VDDSRC_ IO

11

VDDSRC_ IO

35

VDDSB_S RC

34

VDDSB_S RC_IO

40

VDDSATA

4

VDD

55

VDDHTT

56

VDDREF

63

VDD48

51

PD#

22

SRC0T_L PRS

21

SRC0C_L PRS

20

SRC1T_L PRS

19

SRC1C_L PRS

15

SRC2T_L PRS

14

SRC2C_L PRS

13

SRC3T_L PRS

12

SRC3C_L PRS

9

SRC4T_L PRS

8

SRC4C_L PRS SRC6T/SA TAT_LPRS42GNDSATA

41

SRC6C/SA TAC_LPRS SRC7T_L PRS/27MHZ_SS6GND

5

SRC7C_L PRS/27MHZ_NS

37

SB_SRC0 T_LPRS

36

SB_SRC0 C_LPRS

32

SB_SRC1 T_LPRS

31

SB_SRC1 C_LPRS

54

HTT0T_L PRS/66M

53

HTT0C_L PRS/66M

ICS9LPRS480BKLFT-GP

1ST 71.08628.003

71.09480.A03

ATIG0T_LP RS ATIG0C_LP RS ATIG1T_LP RS ATIG1C_LP RS

CPUKG0T _LPRS

CPUKG0C _LPRS

REF0/SEL _HTT66

REF1/SEL _SATA

SMBCLK SMBDAT

CLKREQ0 # CLKREQ1 # CLKREQ2 # CLKREQ3 # CLKREQ4 #

48MHZ_0

REF2/SEL _27

GNDATIG

GNDHTT GNDREF

GNDCPU

GND48

GNDSRC GNDSRC

GNDSB_S RC

GND

XTAL 1'nd 82.30005.901 2'nd 82.30005.A51

X-14D31818M-37GP

C718 SC12P50V2JN-3GPC718 SC12P50V2JN-3GP

12

X701

CLKGEN_X1

61

X1

CLKGEN_X2

62

X2

2 3

30 29 28 27

23 45 44 39 38

50 49

64

59 58 57

43 24 7 52 60 46 1

10 18

33

65

GFX_CLKP GFX_CLKN

NB_GFX_CLK_R NB_GFX_CLK_R#

TP_CLKREQ0#

TP_CLKREQ2# TP_CLKREQ3# TP_CLKREQ4#

CPU_HT_CLK CPU_HT_CLK#

48M_CLK

FS0 FS1 FS2

1

4

2 3

1

4

2 3

1

4

2 3

R709 22R2J-2-GPR709 22R2J-2-GP

1 2

R710 22R2J-2-GPR710 22R2J-2-GP

1 2

SC4D7P50V2CN-1GP

12

DY

R715 158R2F-GPR715 158R2F-GP

RN709

RN709 SRN0J-6-GP

SRN0J-6-GP

RN710

RN710 SRN0J-6-GP

SRN0J-6-GP

RN708

RN708 SRN0J-6-GP

SRN0J-6-GP

SC4D7P50V2CN-1GP

EC703

12

DY

1 2

C719 SC12P50V2JN-3GPC719 SC12P50V2JN-3GP

EC701

For EMI

0423

1 2

SB_SMBCLK 18,19,21,76 SB_SMBDATA 18,19,21,76

CLK_PCIE_VGA 80 CLK_PCIE_VGA# 80

NB_GFX_CLK 13 NB_GFX_CLK# 13

MINI1_CLK_REQ# 76

CPU_CLK 10 CPU_CLK# 10

CLK_48M_CARD 32 USB_48M_CLK 21

90D9R2F-1-GP

12

R718

+3.3V_RUN

8K2R2J-3-GP

12

8K2R2J-3-GP

12

DY

R711

R717

VGA(100MHz)

1002

8K2R2J-3-GP

Place together

3

NB ALINK (100MHz)

SB PCIE (100MHz)

VGA Park (27MHz)

SEL_HTT66 FS0

SEL_SATA FS1

SEL_27MHz FS2

* default

66 MHz 3.3V single ended HTT clock

1

*0

100 MHz differential HTT clock

1*

100 MHz non-spreading differential SRC clock

100 MHz spreading differential SRC clock

0

27MHz non-spreading singled clock on pin 5

1

*

and 27MHz spread clock on pin 6

0

100MHz differential spreading SRC clock

2

CLKREQ# MAP

CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#

CPU_CLK(200MHz)

CardReader(48MHz) SB820M_USB(48MHz)

12

R712

R716 33R2J-2-GPR716 33R2J-2-GP

1 2

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

No use CLKSRC1 MINI1 No use No use No use

+3.3V_RUN

R707

MINI1_CLK_REQ#

0824

NB_14M_CLK 13 SB_14M_CLK 21

Clock Generator ICS9LPRS480

Arsenal DJ1 Discrete

R707

1 2

10KR2J-3-GP

NB OSCIN(14MHz) SB OSCIN(14MHz)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

7 89Friday, May 07, 2010

1

X01

5

4

3

2

1

SSID = CPU

D D

+1.1V_RUN

SC22U6D3V5MX-2GP

12

C C

B B

Place close to socket 1.1V(1.5A) for VLDT

SC4D7U6D3V3KX-GP

C802

C801

12

SCD22U10V3KX-2GP

C803

C804

12

C804

12

SC180P50V2JN-1GP

SCD22U10V3KX-2GP

C805

12

HT_NB_CPU_CAD_H012 HT_NB_CPU_CAD_L012 HT_NB_CPU_CAD_H112 HT_NB_CPU_CAD_L112 HT_NB_CPU_CAD_H212 HT_NB_CPU_CAD_L212 HT_NB_CPU_CAD_H312 HT_NB_CPU_CAD_L312 HT_NB_CPU_CAD_H412 HT_NB_CPU_CAD_L412 HT_NB_CPU_CAD_H512 HT_NB_CPU_CAD_L512 HT_NB_CPU_CAD_H612 HT_NB_CPU_CAD_L612 HT_NB_CPU_CAD_H712 HT_NB_CPU_CAD_L712 HT_NB_CPU_CAD_H812 HT_NB_CPU_CAD_L812 HT_NB_CPU_CAD_H912 HT_NB_CPU_CAD_L912 HT_NB_CPU_CAD_H1012 HT_NB_CPU_CAD_L1012 HT_NB_CPU_CAD_H1112 HT_NB_CPU_CAD_L1112 HT_NB_CPU_CAD_H1212 HT_NB_CPU_CAD_L1212 HT_NB_CPU_CAD_H1312 HT_NB_CPU_CAD_L1312 HT_NB_CPU_CAD_H1412 HT_NB_CPU_CAD_L1412 HT_NB_CPU_CAD_H1512 HT_NB_CPU_CAD_L1512

HT_NB_CPU_CLK_H012 HT_NB_CPU_CLK_L012 HT_NB_CPU_CLK_H112 HT_NB_CPU_CLK_L112

HT_NB_CPU_CTL_H012 HT_NB_CPU_CTL_L012 HT_NB_CPU_CTL_H112 HT_NB_CPU_CTL_L112

SC180P50V2JN-1GP

C806

C807

12

C807

12

CPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_ H0

E2

L0_CADIN_ L0

E1

L0_CADIN_ H1

F1

L0_CADIN_ L1

G3

L0_CADIN_ H2

G2

L0_CADIN_ L2

G1

L0_CADIN_ H3

H1

L0_CADIN_ L3

J1

L0_CADIN_ H4

K1

L0_CADIN_ L4

L3

L0_CADIN_ H5

L2

L0_CADIN_ L5

L1

L0_CADIN_ H6

M1

L0_CADIN_ L6

N3

L0_CADIN_ H7

N2

L0_CADIN_ L7

E5

L0_CADIN_ H8

F5

L0_CADIN_ L8

F3

L0_CADIN_ H9

F4

L0_CADIN_ L9

G5

L0_CADIN_ H10

H5

L0_CADIN_ L10

H3

L0_CADIN_ H11

H4

L0_CADIN_ L11

K3

L0_CADIN_ H12

K4

L0_CADIN_ L12

L5

L0_CADIN_ H13

M5

L0_CADIN_ L13

M3

L0_CADIN_ H14

M4

L0_CADIN_ L14

N5

L0_CADIN_ H15

P5

L0_CADIN_ L15

J3

L0_CLKIN_ H0

J2

L0_CLKIN_ L0

J5

L0_CLKIN_ H1

K5

L0_CLKIN_ L1

N1

L0_CTLIN_ H0

P1

L0_CTLIN_ L0

P3

L0_CTLIN_ H1

P4

L0_CTLIN_ L1

DANUBE

L0_CADO UT_H0 L0_CADO UT_L0 L0_CADO UT_H1 L0_CADO UT_L1 L0_CADO UT_H2 L0_CADO UT_L2 L0_CADO UT_H3 L0_CADO UT_L3 L0_CADO UT_H4 L0_CADO UT_L4 L0_CADO UT_H5 L0_CADO UT_L5 L0_CADO UT_H6 L0_CADO UT_L6 L0_CADO UT_H7 L0_CADO UT_L7 L0_CADO UT_H8 L0_CADO UT_L8 L0_CADO UT_H9 L0_CADO UT_L9

L0_CADO UT_H10

L0_CADO UT_L10

L0_CADO UT_H11

L0_CADO UT_L11

L0_CADO UT_H12

L0_CADO UT_L12

L0_CADO UT_H13

L0_CADO UT_L13

L0_CADO UT_H14

L0_CADO UT_L14

L0_CADO UT_H15

L0_CADO UT_L15

L0_CLKO UT_H0

L0_CLKO UT_L0

L0_CLKO UT_H1

L0_CLKO UT_L1

L0_CTLO UT_H0 L0_CTLO UT_L0 L0_CTLO UT_H1 L0_CTLO UT_L1

1 OF 6

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

HT_CPU_NB_CAD_H0 12 HT_CPU_NB_CAD_L0 12 HT_CPU_NB_CAD_H1 12 HT_CPU_NB_CAD_L1 12 HT_CPU_NB_CAD_H2 12 HT_CPU_NB_CAD_L2 12 HT_CPU_NB_CAD_H3 12 HT_CPU_NB_CAD_L3 12 HT_CPU_NB_CAD_H4 12 HT_CPU_NB_CAD_L4 12 HT_CPU_NB_CAD_H5 12 HT_CPU_NB_CAD_L5 12 HT_CPU_NB_CAD_H6 12 HT_CPU_NB_CAD_L6 12 HT_CPU_NB_CAD_H7 12 HT_CPU_NB_CAD_L7 12 HT_CPU_NB_CAD_H8 12 HT_CPU_NB_CAD_L8 12 HT_CPU_NB_CAD_H9 12 HT_CPU_NB_CAD_L9 12 HT_CPU_NB_CAD_H10 12 HT_CPU_NB_CAD_L10 12 HT_CPU_NB_CAD_H11 12 HT_CPU_NB_CAD_L11 12 HT_CPU_NB_CAD_H12 12 HT_CPU_NB_CAD_L12 12 HT_CPU_NB_CAD_H13 12 HT_CPU_NB_CAD_L13 12 HT_CPU_NB_CAD_H14 12 HT_CPU_NB_CAD_L14 12 HT_CPU_NB_CAD_H15 12 HT_CPU_NB_CAD_L15 12

HT_CPU_NB_CLK_H0 12 HT_CPU_NB_CLK_L0 12 HT_CPU_NB_CLK_H1 12 HT_CPU_NB_CLK_L1 12

HT_CPU_NB_CTL_H0 12 HT_CPU_NB_CTL_L0 12 HT_CPU_NB_CTL_H1 12 HT_CPU_NB_CTL_L1 12

SKT-BGA638H176

1'nd 62.10055.111 2'nd 62.10055.171

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_HT_LINK I/F_(1/4)

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

8 89Friday, May 07, 2010

1

X01

5

4

3

2

1

SSID = CPU

M_A_DQ[63..0]18

D D

+CPU_VDDR

SC4D7U6D3V3KX-GP

12

Place near to CPU

SCD22U10V3KX-2GP

SC4D7U6D3V3KX-GP

C902

C901

12

SC4D7U6D3V3KX-GP

C903

C913

12

C913

12

SCD22U10V3KX-2GP

12

C914

C904

12

SCD22U10V3KX-2GP

12

C906

C905

12

SC1000P50V3JN-GP-U

SC1KP50V2KX-1GP

C907

C915

12

C915

12

SC1000P50V3JN-GP-U

SC1KP50V2KX-1GP

C908

C909

12

C909

12

SC180P50V2JN-1GP

12

C911

C910

12

SC180P50V2JN-1GP

C916

C912

12

C912

12

0.9V(1.25A) for VDDR

+CPU_VDDR

C C

+1.5V_SUS

R901 39D2R2F-L-GPR901 39D2R2F-L-GP

1 2

R903 39D2R2F-L-GPR903 39D2R2F-L-GP

1 2

12

B B

MEM_MA_ADD[0..15]18 MEM_MB_ADD[0..15] 19

DDR3_A_DRAMRST#18

C917

C917 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

MEM_MA0_ODT018 MEM_MA0_ODT118

MEM_MA0_CS#018 MEM_MA0_CS#118

MEM_MA_CKE018 MEM_MA_CKE118

MEM_MA_CLK0_P18 MEM_MA_CLK0_N18

MEM_MA_CLK1_N18

MEM_MA_BANK018 MEM_MA_BANK118 MEM_MA_BANK218

MEM_MA_RAS#18 MEM_MA_CAS#18 MEM_MA_WE#18

MEMZP MEMZN

S1G4

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

0.9V--DDR1066

1.05V---DDR1333 (1.75A)

CPU1B

D10

VDDR

C10

VDDR

B10

VDDR

AD10

VDDR

AF10

MEMZP

AE10

MEMZN

H16

MA_RESE T#

T19

MA0_ODT 0

V22

MA0_ODT 1

U21

MA1_ODT 0

V19

MA1_ODT 1

T20

MA0_CS# 0

U19

MA0_CS# 1

U20

MA1_CS# 0

V20

MA1_CS# 1

J22

MA_CKE0

J20

MA_CKE1

N19

MA_CLK_ H5

N20

MA_CLK_ L5

E16

MA_CLK_ H1

F16

MA_CLK_ L1

Y16

MA_CLK_ H7

AA16

MA_CLK_ L7

P19

MA_CLK_ H4

P20

MA_CLK_ L4

N21

MA_ADD0

M20

MA_ADD1

N22

MA_ADD2

M19

MA_ADD3

M22

MA_ADD4

L20

MA_ADD5

M24

MA_ADD6

L21

MA_ADD7

L19

MA_ADD8

K22

MA_ADD9

R21

MA_ADD1 0

L22

MA_ADD1 1

K20

MA_ADD1 2

V24

MA_ADD1 3

K24

MA_ADD1 4

K19

MA_ADD1 5

R20

MA_BANK 0

R23

MA_BANK 1

J21

MA_BANK 2

R19

MA_RAS#

T22

MA_CAS#

T24

MA_W E#

VDDR VDDR VDDR

DANUBE

VDDR VDDR

VDDR_SE NSE

MEMVREF

MB_RESE T#

MB0_ODT 0 MB0_ODT 1 MB1_ODT 0

MB0_CS# 0 MB0_CS# 1 MB1_CS# 0

MB_CKE0 MB_CKE1

MB_CLK_ H5 MB_CLK_ L5 MB_CLK_ H1 MB_CLK_ L1 MB_CLK_ H7 MB_CLK_ L7 MB_CLK_ H4 MB_CLK_ L4

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD1 0 MB_ADD1 1 MB_ADD1 2 MB_ADD1 3 MB_ADD1 4 MB_ADD1 5

MB_BANK 0 MB_BANK 1 MB_BANK 2

MB_RAS#

MB_CAS#

MB_W E#

2 OF 6

W10 AC10 AB10 AA10 A10

From VDDR SEL

TP_CPU_VDDR_SENSE

Y10

W17

B18

S1G4

W26 W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

MEM_MB_ADD0

P24

MEM_MB_ADD1

N24

MEM_MB_ADD2

P26

MEM_MB_ADD3

N23

MEM_MB_ADD4

N26

MEM_MB_ADD5

L23

MEM_MB_ADD6

N25

MEM_MB_ADD7

L24

MEM_MB_ADD8

M26

MEM_MB_ADD9

K26

MEM_MB_ADD10

T26

MEM_MB_ADD11

L26

MEM_MB_ADD12

L25

MEM_MB_ADD13

W24

MEM_MB_ADD14

J23

MEM_MB_ADD15

J24

R24 U26 J26

U25 U24 U23

+1.5V_SUS

SCD1U10V2KX-4GP

1KR3F-GP

C918

12

+0.75V_SUS_CPU_M_VREF +V_DDR_REF

TP901TP901

1

DDR3_B_DRAMRST# 19

MEM_MB0_ODT0 19 MEM_MB0_ODT1 19

MEM_MB0_CS#0 19 MEM_MB0_CS#1 19

MEM_MB_CKE0 19 MEM_MB_CKE1 19

MEM_MB_CLK0_P 19 MEM_MB_CLK0_N 19

MEM_MB_CLK1_P 19 MEM_MB_CLK1_N 19

MEM_MB_BANK0 19 MEM_MB_BANK1 19 MEM_MB_BANK2 19

MEM_MB_RAS# 19 MEM_MB_CAS# 19 MEM_MB_WE# 19

SCD1U10V2KX-4GP

1KR3F-GP

SC1000P50V3JN-GP-U

C919

12

1KR3F-GP

C920

12

CLOSE TO CPU

12

R902

1 2

12

R905

R904

DY

0R3J-0-U-GP

M_A_DM[7..0]18

M_A_DQS018 M_A_DQS#018 M_A_DQS118 M_A_DQS#118 M_A_DQS218 M_A_DQS#218 M_A_DQS318 M_A_DQS#318 M_A_DQS418 M_A_DQS#418 M_A_DQS518 M_A_DQS#518 M_A_DQS618 M_A_DQS#618 M_A_DQS718 M_A_DQS#718

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24

E21 E22 H20 H22

Y24 AB24 AB22 AA21

W22 W21

Y22 AA22

Y20 AA20 AA18 AB18 AB21 AD21 AD19

Y18 AD17

W16 W14

Y14

Y17 AB17 AB15 AD15 AB13 AD13

Y12

W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24

AC24

Y19

AB16

Y13

G13 H13 G16 G15 C22 C21 G22

G21 AD23 AC23 AB19 AB20

Y15

W15 W12 W13

J19

3 OF 6

MA_DATA 0 MA_DATA 1 MA_DATA 2 MA_DATA 3 MA_DATA 4 MA_DATA 5 MA_DATA 6 MA_DATA 7 MA_DATA 8 MA_DATA 9 MA_DATA 10 MA_DATA 11 MA_DATA 12 MA_DATA 13 MA_DATA 14 MA_DATA 15 MA_DATA 16 MA_DATA 17 MA_DATA 18 MA_DATA 19 MA_DATA 20 MA_DATA 21 MA_DATA 22 MA_DATA 23 MA_DATA 24 MA_DATA 25 MA_DATA 26 MA_DATA 27 MA_DATA 28 MA_DATA 29 MA_DATA 30 MA_DATA 31 MA_DATA 32 MA_DATA 33 MA_DATA 34 MA_DATA 35 MA_DATA 36 MA_DATA 37 MA_DATA 38 MA_DATA 39 MA_DATA 40 MA_DATA 41 MA_DATA 42 MA_DATA 43 MA_DATA 44 MA_DATA 45 MA_DATA 46 MA_DATA 47 MA_DATA 48 MA_DATA 49 MA_DATA 50 MA_DATA 51 MA_DATA 52 MA_DATA 53 MA_DATA 54 MA_DATA 55 MA_DATA 56 MA_DATA 57 MA_DATA 58 MA_DATA 59 MA_DATA 60 MA_DATA 61 MA_DATA 62 MA_DATA 63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_ H0 MA_DQS_ L0 MA_DQS_ H1 MA_DQS_ L1 MA_DQS_ H2 MA_DQS_ L2 MA_DQS_ H3 MA_DQS_ L3 MA_DQS_ H4 MA_DQS_ L4 MA_DQS_ H5 MA_DQS_ L5 MA_DQS_ H6 MA_DQS_ L6 MA_DQS_ H7 MA_DQS_ L7

DANUBE

CPU1C

MB_DATA 0 MB_DATA 1 MB_DATA 2 MB_DATA 3 MB_DATA 4 MB_DATA 5 MB_DATA 6 MB_DATA 7 MB_DATA 8

MB_DATA 9 MB_DATA 10 MB_DATA 11 MB_DATA 12 MB_DATA 13 MB_DATA 14 MB_DATA 15 MB_DATA 16 MB_DATA 17 MB_DATA 18 MB_DATA 19 MB_DATA 20 MB_DATA 21 MB_DATA 22 MB_DATA 23 MB_DATA 24 MB_DATA 25 MB_DATA 26 MB_DATA 27 MB_DATA 28 MB_DATA 29 MB_DATA 30 MB_DATA 31 MB_DATA 32 MB_DATA 33 MB_DATA 34 MB_DATA 35 MB_DATA 36 MB_DATA 37 MB_DATA 38 MB_DATA 39 MB_DATA 40 MB_DATA 41 MB_DATA 42 MB_DATA 43 MB_DATA 44 MB_DATA 45 MB_DATA 46 MB_DATA 47 MB_DATA 48 MB_DATA 49 MB_DATA 50 MB_DATA 51 MB_DATA 52 MB_DATA 53 MB_DATA 54 MB_DATA 55 MB_DATA 56 MB_DATA 57 MB_DATA 58 MB_DATA 59 MB_DATA 60 MB_DATA 61 MB_DATA 62 MB_DATA 63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_ H0

MB_DQS_ L0

MB_DQS_ H1

MB_DQS_ L1

MB_DQS_ H2

MB_DQS_ L2

MB_DQS_ H3

MB_DQS_ L3

MB_DQS_ H4

MB_DQS_ L4

MB_DQS_ H5

MB_DQS_ L5

MB_DQS_ H6

MB_DQS_ L6

MB_DQS_ H7

MB_DQS_ L7

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11

A12 B16 A22 E25 AB26 AE22 AC16 AD12

C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 19 M_B_DQS#0 19 M_B_DQS1 19 M_B_DQS#1 19 M_B_DQS2 19 M_B_DQS#2 19 M_B_DQS3 19 M_B_DQS#3 19 M_B_DQS4 19 M_B_DQS#4 19 M_B_DQS5 19 M_B_DQS#5 19 M_B_DQS6 19 M_B_DQS#6 19 M_B_DQS7 19 M_B_DQS#7 19

M_B_DQ[63..0] 19

M_B_DM[7..0] 19MEM_MA_CLK1_P18

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_DDR_(2/4)

Size Document Number Rev

Custom

Date: Sheet of

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

9 89Friday, May 07, 2010

1

X00

5

4

3

2

1

SSID = CPU

L1001

1 2

SC180P50V2JN-1GP

D D

+1.5V_RUN

4

RN1001

RN1001 SRN300J-3-GP

SRN300J-3-GP

1

CPU_LDT_RST#20

CPU_LDT_PWRGD20,42

CPU_LDT_STOP#13,20

C C

+1.5V_RUN

B B

0423

+1.5V_SUS

2 3

R1001 0R0402-PADR1001 0R0402-PAD

R1002 0R0402-PADR1002 0R0402-PAD

R1003 0R0402-PADR1003 0R0402-PAD

R1012 300R2J-4-GP

1 2

DY

R1013 300R2J-4-GP

1 2

DY

R1014 300R2J-4-GP

1 2

DY

R1016 300R2J-4-GP

1 2

DY

RN1002 SRN1KJ-7-GPRN1002 SRN1KJ-7-GP

1 2 3

RN1004 SRN1KJ-7-GPRN1004 SRN1KJ-7-GP

1 2 3

RN1003

1 2 3 4 5

SRN1KJ-4-GP

1 2

4

8 7 6

X01

CPU_CLK(200MHz)

For HDT DBG

CPU_R_LDT_RST#

CPU_R_LDT_PWRGD

CPU_R_LDT_STOP#

CPU_LDT_REQ#

CPU_DBRDY TP_CPU_TEST14 TP_CPU_TEST15

CPU_TEST18 CPU_TEST19

CPU_TEST24 CPU_TEST22

CPU_TEST23 CPU_TEST12 CPU_TEST20 CPU_TEST21

CPU_R_LDT_RST#

HDT_RST_R#

510R2F-L-GP

R1018

R1020

CPU_CLK7 CPU_CLK#7

R1009

1 2

DY

0R2J-2-GP

+1.5V_SUS

12

DY

12

SC180P50V2JN-1GP

PBY160808T-330Y-N-GP

C1001

12

Cloce To CPU

C1005 SC3900P50V2KX-2GPC1005 SC3900P50V2KX-2GP

1 2

C1006 SC3900P50V2KX-2GPC1006 SC3900P50V2KX-2GP

1 2

Close CPU

+1.1V_RUN

to power IC FB

12

R1019

R1019 510R2F-L-GP

510R2F-L-GP

12

R1022

DY

510R2F-L-GP

CPU_VDD0_RUN_FB_H47 CPU_VDD0_RUN_FB_L47

CPU_VDD1_RUN_FB_H47 CPU_VDD1_RUN_FB_L47

LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

+2.5V_RUN_VDDA+2.5V_RUN

2.5V(250mA) for VDDA

SC3300P50V2KX-1GP

SCD22U6D3V2KX-1GP

SC4D7U6D3V3KX-GP

C1002

12

R1008 169R2F-GPR1008 169R2F-GP

1 2

SCD1U16V2ZY-2GP

DY

R1010 44D2R2F-GPR1010 44D2R2F-GP

1 2

R1011 44D2R2F-GPR1011 44D2R2F-GP

1 2

0R2J-2-GP

12

R1023

C1007

CPU_R_LDT_PWRGD CPU_R_LDT_STOP# CPU_LDT_REQ#

CPU_SIC CPU_SID CPU_ALERT#

CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI

CPU_TEST23

CPU_TEST18 CPU_TEST19

CPU_TEST25_H CPU_TEST25_L

CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27

CPU_TEST9

C1003

CPUCLK_IN CPUCLK_IN#

CPU_HTREF0 CPU_HTREF1

C1004

12

AC9 AD9

AD7

AC8

F10

AF4 AF5 AE6

AB6

G10 AA9

AF9

H10

AB8 AF7 AE7 AE8

AF8

AA6

G9

E9 E8

C2

A3 A5 B3 B5 C1

F8 F9

A9 A8

B7 A7

C6

R6 P6

F6 E6

Y6

CPU1D

VDDA VDDA

CLKIN_H CLKIN_L

RESET# PWRO K LDTSTOP # LDTREQ#

SIC SID ALERT#

HT_REF0 HT_REF1

VDD0_FB _H VDD0_FB _L

VDD1_FB _H VDD1_FB _L

DBRDY TMS TCK TRST# TDI

TEST23

TEST18 TEST19

TEST25_ H TEST25_ L

TEST21 TEST20 TEST24 TEST22 TEST12 TEST27

TEST9 TEST6

RSVD#A3 RSVD#A5 RSVD#B3 RSVD#B5 RSVD#C1

RSVD#W 18

DANUBE

THERMTR IP#

PROCHOT #

VDDIO_FB_ H

VDDIO_FB_ L

VDDNB_F B_H

VDDNB_F B_L

4 OF 6

VSS

SVC SVD

MEMHOT#

THERMDC THERMDA

DBREQ#

TDO

TEST28_ H TEST28_ L

TEST17 TEST16 TEST15 TEST14

TEST7

TEST10

TEST8

TEST29_ H TEST29_ L

RSVD#H1 8 RSVD#H1 9 RSVD#AA 7

RSVD#D5 RSVD#C5

0423

+1.5V_SUS

M11 W18

A6 A4

CPU_THERMTRIP#

AF6

CPU_PROCHOT#

AC7

CPU_MEMHOT#

AA8

W7 W8

TP_CPU_VDDIO_SUS_FB_H

W9

TP_CPU_VDDIO_SUS_FB_L

Y9

H6 G6

CPU_DBREQ#

E10

CPU_TDO

AE9

J7 H8

TP_CPU_TEST17

D7

TP_CPU_TEST16

E7

TP_CPU_TEST15

F7

TP_CPU_TEST14

C7

C3

CPU_TEST10

K8

C4

CPU_TEST29H

C9

CPU_TEST29L

C8

H18 H19 AA7 D5 C5

4

RN1006

RN1006 SRN1KJ-7-GP

SRN1KJ-7-GP

1

2 3

CPU_SVC 47 CPU_SVD 47

1

H_THERMDC 39 H_THERMDA 39

CPU_VDDNB_RUN_FB_H 47 CPU_VDDNB_RUN_FB_L 47

R1015

1 2

300R2J-4-GP

1 2

DY

R1021 300R3-GP

1 2

R1024 80D6R2F-L-GPR1024 80D6R2F-L-GP

+1.5V_SUS

1KR2J-1-GP

300R2J-4-GP

12

R1006

R1007

TP1002TP1002

S1G4 not support MEMHOT

+1.5V_SUS

+1.1V_RUN

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

HDT Connectors

CPU_PROCHOT# 20

R1026

R1026 1KR2J-1-GP

1KR2J-1-GP

1 2

CPU_TEST27

R1029

R1029 300R2J-4-GP

300R2J-4-GP

DY

1 2

TP1001TP1001 TP1003TP1003 TP1006TP1006 TP1007TP1007 TP1008TP1008 TP1009TP1009

0423

A A

CPU_PROCHOT#_EC37

1 1 1 1 1 1

5

TP_CPU_VDDIO_SUS_FB_H TP_CPU_VDDIO_SUS_FB_L TP_CPU_TEST17 TP_CPU_TEST16 TP_CPU_TEST15 TP_CPU_TEST14

+3.3V_RUN

8K2R2J-3-GP

12

R1040

Q1005 PMBS3904-1-GPQ1005 PMBS3904-1-GP

+1.5V_RUN

2K2R2J-2-GP

12

1

2

R1039

CPU_PROCHOT#

3

CPU_SIC21

CPU_SID21

TALERT#21,39

For old HDT tool (3.3V level)

4

+1.5V_SUS

1

4

23

0423

RN1005

RN1005 SRN1KJ-7-GP

SRN1KJ-7-GP

10KR2J-3-GP

DY

2K2R2J-2-GP

12

312

Q1001

PMBS3904-1-GP

12

R1037

Q1004 PMBS3904-1-GP

R1032

+1.8V_RUN+3.3V_RUN

2K2R2J-2-GP

12

DY

312

DY

HDT1

1

2

DY

3

4

5

1KR2J-1-GP

12

R1033

CPU_SIC

CPU_SID

CPU_ALERT#

R1036

HDT_RST_R#HDT_RST#

3

H_THERMTRIP#21,37,39,42

CPU_PWRGD_SVID_REG47

+KBC_PWR

8K2R2J-3-GP

12

DY

10KR2J-3-GP

12

R1034

+1.5V_RUN

R1027

312

PMBS3904-1-GP

+1.8V_RUN+3.3V_RUN

2K2R2J-2-GP

312

Q1003

PMBS3904-1-GP

2K2R2J-2-GP

Q1002

12

R1028

12

R1035

2

X01

CPU_THERMTRIP#

CPU_R_LDT_PWRGD

CPU_DBREQ#

CPU_DBRDY

CPU_TCK CPU_TMS CPU_TDI

CPU_TRST#

CPU_TDOCPU_TDO

1.5V

CPU_R_LDT_RST#

HDT_RST#

3.3V

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.5V_SUS

1 2

DY

R1038 0R2J-2-GP

CPU_Control&Debug_(3/4)

Arsenal DJ1 Discrete

SMC-CONN26A-FP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24 26

X01

10 89Friday, May 07, 2010

X01

5

4

3

2

1

SSID = CPU

D D

6 OF 6

CPU1F

AA4

VSS

AA11

VSS

AA13

VSS

AA15

VSS

AA17

VSS

AA19

VSS

AB2

VSS

AB7

VSS

AB9

VSS

AB23

VSS

AB25

VSS

AC11

VSS

AC13

VSS

AC15

VSS

AC17

VSS

AC19

VSS

AC21

VSS

AD6

C C

B B

AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

B11

B13

B15

B17

B19

B21

B23

B25

D11

D13

D15

D17

D19

D21

D23

D25

H21

H23

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B4

VSS

B6

VSS

B8

VSS

B9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D6

VSS

D8

VSS

D9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

E4

VSS

F2

VSS

F11

VSS

F13

VSS

F15

VSS

F17

VSS

F19

VSS

F21

VSS

F23

VSS

F25

VSS

H7

VSS

H9

VSS VSS VSS

J4

VSS

VSS VSS VSS

DANUBE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

+1.5V_SU S

(36A) for 35W S1G4 VDD

+VCC_CO RE +VCC_CO RE

+VDDNB

SC22U6D3V5MX-2GP

Bottom Side Decoupling Bottom Side Decoupling

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

C1103

C1101

12

22UF *4

0.22UF *1 180PF *1 10nF*1

0.9V(4A) for VDDNB

SC22U6D3V5MX-2GP

C1116

C1115

12

1.5V(3A) for VDDIO

Bottom Side Decoupling

SC22U6D3V5MX-2GP

SCD22U10V3KX-2GP

C1131

C1130

12

22UF *2

0.22UF *2 180PF *1

0.01UF *1

0.1UF *2

C1132

12

SCD22U10V3KX-2GP

SC22U6D3V5MX-2GP

C1104

C1105

12

C1117

22UF *3

SC180P50V2JN-1GP

SCD22U10V3KX-2GP

C1134

C1133

12

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

C1106

C1107

C1102

SCD01U50V2KX-1GP

12

C1107

12

SCD1U10V2KX-4GP

C1121

C1120

12

CPU1E

G4

VDD

H2

VDD

J9

VDD

J11

VDD

J13

VDD

J15

VDD

K6

VDD

K10

VDD

K12

VDD

K14

VDD

L4

VDD

L7

VDD

L9

VDD

L11

VDD

L13

VDD

L15

VDD

M2

VDD

M6

VDD

M8

VDD

M10

VDD

N7

VDD

N9

VDD

N11

VDD

K16

VDDNB

M16

VDDNB

P16

VDDNB

T16

VDDNB

V16

VDDNB

H25

VDDIO

J17

VDDIO

K18

VDDIO

K21

VDDIO

K23

VDDIO

K25

VDDIO

L17

VDDIO

M18

VDDIO

M21

VDDIO

M23

VDDIO

M25

VDDIO

N17

VDDIO

C1135

12

5 OF 6

DANUBE

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

SCD22U10V3KX-2GP

SC180P50V2JN-1GP

12

Place near to CPU

SC180P50V2JN-1GP

SCD22U10V3KX-2GP

SC22U6D3V5MX-2GP

C1109

SCD22U10V3KX-2GP

C1119

12

SC22U6D3V5MX-2GP

C1110

12

22UF *4

0.22UF *1 180PF *1 10nF*1

C1122

12

SCD01U50V2KX-1GP

C1108

12

SC180P50V2JN-1GP

C1118

12

SCD22U10V3KX-2GP

SC22U6D3V5MX-2GP

C1111

12

SCD22U10V3KX-2GP

C1123

12

0.22UF *4

4.7UF *4 180PF *2

SC22U6D3V5MX-2GP

C1141

C1112

12

SC4D7U6D3V3KX-GP

SCD22U10V3KX-2GP

C1124

C1125

12

C1114

+1.5V_SU S

SC4D7U6D3V3KX-GP

C1126

12

SC4D7U6D3V3KX-GP

C1128

C1127

C1129

12

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_Power_(4/4)

Size Document N umber Rev

A3

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

11 89Friday, May 07, 2010

1

of

X01

5

4

3

2

1

SSID = N.B

HT_CPU_NB_CAD_H08

HT_CPU_NB_CAD_L08

RS880M : 71.RS880.M05

D D

C C

Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24

B B

A A

LANE REVERSE

A-LINK

5

ALINK_NBRX_SBTX_P020 ALINK_NBRX_SBTX_N020 ALINK_NBRX_SBTX_P120 ALINK_NBRX_SBTX_N120 ALINK_NBRX_SBTX_P220 ALINK_NBRX_SBTX_N220 ALINK_NBRX_SBTX_P320 ALINK_NBRX_SBTX_N320

HT_CPU_NB_CAD_H18 HT_CPU_NB_CAD_L18 HT_CPU_NB_CAD_H28 HT_CPU_NB_CAD_L28 HT_CPU_NB_CAD_H38 HT_CPU_NB_CAD_L38 HT_CPU_NB_CAD_H48 HT_CPU_NB_CAD_L48 HT_CPU_NB_CAD_H58 HT_CPU_NB_CAD_L58 HT_CPU_NB_CAD_H68 HT_CPU_NB_CAD_L68 HT_CPU_NB_CAD_H78 HT_CPU_NB_CAD_L78

HT_CPU_NB_CAD_H88 HT_CPU_NB_CAD_L88 HT_CPU_NB_CAD_H98 HT_CPU_NB_CAD_L98 HT_CPU_NB_CAD_H108 HT_CPU_NB_CAD_L108 HT_CPU_NB_CAD_H118 HT_CPU_NB_CAD_L118 HT_CPU_NB_CAD_H128 HT_CPU_NB_CAD_L128 HT_CPU_NB_CAD_H138 HT_CPU_NB_CAD_L138 HT_CPU_NB_CAD_H148 HT_CPU_NB_CAD_L148 HT_CPU_NB_CAD_H158 HT_CPU_NB_CAD_L158

HT_CPU_NB_CLK_H08 HT_CPU_NB_CLK_L08 HT_CPU_NB_CLK_H18 HT_CPU_NB_CLK_L18

HT_CPU_NB_CTL_H08 HT_CPU_NB_CTL_L08 HT_CPU_NB_CTL_H18 HT_CPU_NB_CTL_L18

R1201 301R2F-GPR1201 301R2F-GP

1 2

PCIE_NRX_GTX_P0 PCIE_NRX_GTX_N0 PCIE_NRX_GTX_P1 PCIE_NRX_GTX_N1 PCIE_NRX_GTX_P2 PCIE_NRX_GTX_N2 PCIE_NRX_GTX_P3 PCIE_NRX_GTX_N3 PCIE_NRX_GTX_P4 PCIE_NRX_GTX_N4 PCIE_NRX_GTX_P5 PCIE_NRX_GTX_N5 PCIE_NRX_GTX_P6 PCIE_NRX_GTX_N6 PCIE_NRX_GTX_P7 PCIE_NRX_GTX_N7 PCIE_NRX_GTX_P8 PCIE_NRX_GTX_N8 PCIE_NRX_GTX_P9 PCIE_NRX_GTX_N9 PCIE_NRX_GTX_P10 PCIE_NRX_GTX_N10 PCIE_NRX_GTX_P11 PCIE_NRX_GTX_N11 PCIE_NRX_GTX_P12 PCIE_NRX_GTX_N12 PCIE_NRX_GTX_P13 PCIE_NRX_GTX_N13 PCIE_NRX_GTX_P14 PCIE_NRX_GTX_N14 PCIE_NRX_GTX_P15 PCIE_NRX_GTX_N15

HT_RXCALP HT_TXCALP HT_RXCALN

Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25

AC24 AC25

AB25 AB24 AA24 AA25

Y22

Y23 W21 W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23 AA22

M22

M23

R21

R20

C23

A24

U1B

D4 C4

A3 B3

C2 C1

E5 F5

G5 G6 H5 H6

J6 J5 J7 J8 L5 L6

M8

L8 P7

M7

P5

M5 R8

P8

R6 R5

P4 P3 T4 T3

AE3

AD4

AE2 AD3 AD1 AD2

V5

W6

U5 U6 U8 U7

AA8

Y8

AA7

Y7 AA5 AA6

W5

Y5

RS880M-1-GP

4

U1A

HT_RXCA D0P HT_RXCA D0N HT_RXCA D1P HT_RXCA D1N HT_RXCA D2P HT_RXCA D2N HT_RXCA D3P HT_RXCA D3N HT_RXCA D4P HT_RXCA D4N HT_RXCA D5P HT_RXCA D5N HT_RXCA D6P HT_RXCA D6N HT_RXCA D7P HT_RXCA D7N

HT_RXCA D8P HT_RXCA D8N HT_RXCA D9P HT_RXCA D9N HT_RXCA D10P HT_RXCA D10N HT_RXCA D11P HT_RXCA D11N HT_RXCA D12P HT_RXCA D12N HT_RXCA D13P HT_RXCA D13N HT_RXCA D14P HT_RXCA D14N HT_RXCA D15P HT_RXCA D15N

HT_RXCL K0P HT_RXCL K0N HT_RXCL K1P HT_RXCL K1N

HT_RXCT L0P HT_RXCT L0N HT_RXCT L1P HT_RXCT L1N

HT_RXCA LP HT_RXCA LN

RS880M-1-GP

GFX_RX0 P GFX_RX0 N GFX_RX1 P GFX_RX1 N GFX_RX2 P GFX_RX2 N GFX_RX3 P GFX_RX3 N GFX_RX4 P GFX_RX4 N GFX_RX5 P GFX_RX5 N GFX_RX6 P GFX_RX6 N GFX_RX7 P GFX_RX7 N GFX_RX8 P GFX_RX8 N GFX_RX9 P GFX_RX9 N GFX_RX1 0P GFX_RX1 0N GFX_RX1 1P GFX_RX1 1N GFX_RX1 2P GFX_RX1 2N GFX_RX1 3P GFX_RX1 3N GFX_RX1 4P GFX_RX1 4N GFX_RX1 5P GFX_RX1 5N

GPP_RX0 P GPP_RX0 N GPP_RX1 P GPP_RX1 N GPP_RX2 P GPP_RX2 N GPP_RX3 P GPP_RX3 N GPP_RX4 P GPP_RX4 N GPP_RX5 P GPP_RX5 N

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

PART 1 OF 6

HYPER TRANSPORT CPU I/F

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

HT_TXCA D0P HT_TXCA D0N HT_TXCA D1P HT_TXCA D1N HT_TXCA D2P HT_TXCA D2N HT_TXCA D3P HT_TXCA D3N HT_TXCA D4P HT_TXCA D4N HT_TXCA D5P HT_TXCA D5N HT_TXCA D6P HT_TXCA D6N HT_TXCA D7P HT_TXCA D7N

HT_TXCA D8P HT_TXCA D8N

HT_TXCA D9P

HT_TXCA D9N HT_TXCA D10P HT_TXCA D10N HT_TXCA D11P HT_TXCA D11N HT_TXCA D12P HT_TXCA D12N HT_TXCA D13P HT_TXCA D13N HT_TXCA D14P HT_TXCA D14N HT_TXCA D15P HT_TXCA D15N

HT_TXCL K0P HT_TXCL K0N HT_TXCL K1P HT_TXCL K1N

HT_TXCT L0P HT_TXCT L0N HT_TXCT L1P HT_TXCT L1N

HT_TXCA LP

HT_TXCA LN

GFX_TX0 P

GFX_TX0 N

GFX_TX1 P

GFX_TX1 N

GFX_TX2 P

GFX_TX2 N

GFX_TX3 P

GFX_TX3 N

GFX_TX4 P

GFX_TX4 N

GFX_TX5 P

GFX_TX5 N

GFX_TX6 P

GFX_TX6 N

GFX_TX7 P

GFX_TX7 N

GFX_TX8 P

GFX_TX8 N

GFX_TX9 P

GFX_TX9 N GFX_TX1 0P GFX_TX1 0N GFX_TX1 1P GFX_TX1 1N GFX_TX1 2P GFX_TX1 2N GFX_TX1 3P GFX_TX1 3N GFX_TX1 4P GFX_TX1 4N GFX_TX1 5P GFX_TX1 5N

GPP_TX0 P

GPP_TX0 N

GPP_TX1 P

GPP_TX1 N

GPP_TX2 P

GPP_TX2 N

GPP_TX3 P

GPP_TX3 N

GPP_TX4 P

GPP_TX4 N

GPP_TX5 P

GPP_TX5 N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

SB_TX2P

SB_TX2N

SB_TX3P

SB_TX3N

PCE_CAL RP PCE_CAL RN

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

PCIE_NTX_GRX_C_P0

A5

PCIE_NTX_GRX_C_N0

B5

PCIE_NTX_GRX_C_P1

A4

PCIE_NTX_GRX_C_N1

B4

PCIE_NTX_GRX_C_P2

C3

PCIE_NTX_GRX_C_N2

B2

PCIE_NTX_GRX_C_P3

D1

PCIE_NTX_GRX_C_N3

D2

PCIE_NTX_GRX_C_P4

E2

PCIE_NTX_GRX_C_N4

E1

PCIE_NTX_GRX_C_P5

F4

PCIE_NTX_GRX_C_N5

F3

PCIE_NTX_GRX_C_P6

F1

PCIE_NTX_GRX_C_N6

F2

PCIE_NTX_GRX_C_P7

H4

PCIE_NTX_GRX_C_N7

H3

PCIE_NTX_GRX_C_P8

H1

PCIE_NTX_GRX_C_N8

H2

PCIE_NTX_GRX_C_P9

J2

PCIE_NTX_GRX_C_N9

J1

PCIE_NTX_GRX_C_P10

K4

PCIE_NTX_GRX_C_N10

K3

PCIE_NTX_GRX_C_P11

K1

PCIE_NTX_GRX_C_N11

K2

PCIE_NTX_GRX_C_P12

M4

PCIE_NTX_GRX_C_N12

M3

PCIE_NTX_GRX_C_P13

M1

PCIE_NTX_GRX_C_N13

M2

PCIE_NTX_GRX_C_P14

N2

PCIE_NTX_GRX_C_N14

N1

PCIE_NTX_GRX_C_P15

P1

PCIE_NTX_GRX_C_N15

P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

ALINK_NBTX_SBRX_C_P0

AD7

ALINK_NBTX_SBRX_C_N0

AE7

ALINK_NBTX_SBRX_C_P1

AE6

ALINK_NBTX_SBRX_C_N1

AD6

ALINK_NBTX_SBRX_C_P2

AB6

ALINK_NBTX_SBRX_C_N2

AC6

ALINK_NBTX_SBRX_C_P3

AD5

ALINK_NBTX_SBRX_C_N3

AE5

PCE_PCAL

AC8

PCE_NCAL

AB8

HT_NB_CPU_CAD_H0 8 HT_NB_CPU_CAD_L0 8 HT_NB_CPU_CAD_H1 8 HT_NB_CPU_CAD_L1 8 HT_NB_CPU_CAD_H2 8 HT_NB_CPU_CAD_L2 8 HT_NB_CPU_CAD_H3 8 HT_NB_CPU_CAD_L3 8 HT_NB_CPU_CAD_H4 8 HT_NB_CPU_CAD_L4 8 HT_NB_CPU_CAD_H5 8 HT_NB_CPU_CAD_L5 8 HT_NB_CPU_CAD_H6 8 HT_NB_CPU_CAD_L6 8 HT_NB_CPU_CAD_H7 8 HT_NB_CPU_CAD_L7 8

HT_NB_CPU_CAD_H8 8 HT_NB_CPU_CAD_L8 8 HT_NB_CPU_CAD_H9 8 HT_NB_CPU_CAD_L9 8 HT_NB_CPU_CAD_H10 8 HT_NB_CPU_CAD_L10 8 HT_NB_CPU_CAD_H11 8 HT_NB_CPU_CAD_L11 8 HT_NB_CPU_CAD_H12 8 HT_NB_CPU_CAD_L12 8 HT_NB_CPU_CAD_H13 8 HT_NB_CPU_CAD_L13 8 HT_NB_CPU_CAD_H14 8 HT_NB_CPU_CAD_L14 8 HT_NB_CPU_CAD_H15 8 HT_NB_CPU_CAD_L15 8

HT_NB_CPU_CLK_H0 8 HT_NB_CPU_CLK_L0 8 HT_NB_CPU_CLK_H1 8 HT_NB_CPU_CLK_L1 8

HT_NB_CPU_CTL_H0 8 HT_NB_CPU_CTL_L0 8 HT_NB_CPU_CTL_H1 8 HT_NB_CPU_CTL_L1 8

HT_TXCALN

R1203 1K27R2F-L-GPR1203 1K27R2F-L-GP R1204 2KR2F-3-GPR1204 2KR2F-3-GP

R1202 301R2F-GPR1202 301R2F-GP

1 2

C1201 SCD1U16V2KX-3GPC1201 SCD1U16V2KX-3GP

1 2

C1202 SCD1U16V2KX-3GPC1202 SCD1U16V2KX-3GP

1 2

C1203 SCD1U16V2KX-3GPC1203 SCD1U16V2KX-3GP

1 2

C1204 SCD1U16V2KX-3GPC1204 SCD1U16V2KX-3GP

1 2

C1205 SCD1U16V2KX-3GPC1205 SCD1U16V2KX-3GP

1 2

C1206 SCD1U16V2KX-3GPC1206 SCD1U16V2KX-3GP

1 2

C1207 SCD1U16V2KX-3GPC1207 SCD1U16V2KX-3GP

1 2

C1208 SCD1U16V2KX-3GPC1208 SCD1U16V2KX-3GP

1 2

C1209 SCD1U16V2KX-3GPC1209 SCD1U16V2KX-3GP

1 2

C1210 SCD1U16V2KX-3GPC1210 SCD1U16V2KX-3GP

1 2

C1211 SCD1U16V2KX-3GPC1211 SCD1U16V2KX-3GP

1 2

C1212 SCD1U16V2KX-3GPC1212 SCD1U16V2KX-3GP

1 2

C1213 SCD1U16V2KX-3GPC1213 SCD1U16V2KX-3GP

1 2

C1214 SCD1U16V2KX-3GPC1214 SCD1U16V2KX-3GP

1 2

C1215 SCD1U16V2KX-3GPC1215 SCD1U16V2KX-3GP

1 2

C1216 SCD1U16V2KX-3GPC1216 SCD1U16V2KX-3GP

1 2

C1217 SCD1U16V2KX-3GPC1217 SCD1U16V2KX-3GP

1 2

C1218 SCD1U16V2KX-3GPC1218 SCD1U16V2KX-3GP

1 2

C1219 SCD1U16V2KX-3GPC1219 SCD1U16V2KX-3GP

1 2

C1220 SCD1U16V2KX-3GPC1220 SCD1U16V2KX-3GP

1 2

C1221 SCD1U16V2KX-3GPC1221 SCD1U16V2KX-3GP

1 2

C1222 SCD1U16V2KX-3GPC1222 SCD1U16V2KX-3GP

1 2

C1223 SCD1U16V2KX-3GPC1223 SCD1U16V2KX-3GP

1 2

C1224 SCD1U16V2KX-3GPC1224 SCD1U16V2KX-3GP

1 2

C1225 SCD1U16V2KX-3GPC1225 SCD1U16V2KX-3GP

1 2

C1226 SCD1U16V2KX-3GPC1226 SCD1U16V2KX-3GP

1 2

C1227 SCD1U16V2KX-3GPC1227 SCD1U16V2KX-3GP

1 2

C1228 SCD1U16V2KX-3GPC1228 SCD1U16V2KX-3GP

1 2

C1229 SCD1U16V2KX-3GPC1229 SCD1U16V2KX-3GP

1 2

C1230 SCD1U16V2KX-3GPC1230 SCD1U16V2KX-3GP

1 2

C1231 SCD1U16V2KX-3GPC1231 SCD1U16V2KX-3GP

1 2

C1232 SCD1U16V2KX-3GPC1232 SCD1U16V2KX-3GP

1 2

C1237 SCD1U16V2KX-3GPC1237 SCD1U16V2KX-3GP

1 2

C1238 SCD1U16V2KX-3GPC1238 SCD1U16V2KX-3GP

1 2

C1239 SCD1U16V2KX-3GPC1239 SCD1U16V2KX-3GP

1 2

C1240 SCD1U16V2KX-3GPC1240 SCD1U16V2KX-3GP

1 2

C1241 SCD1U16V2KX-3GPC1241 SCD1U16V2KX-3GP

1 2

C1242 SCD1U16V2KX-3GPC1242 SCD1U16V2KX-3GP

1 2

C1243 SCD1U16V2KX-3GPC1243 SCD1U16V2KX-3GP

1 2

C1244 SCD1U16V2KX-3GPC1244 SCD1U16V2KX-3GP

1 2

1 2 1 2

Place < 100mils from pin AC8 and AB8

3

PCIE_NTX_GRX_P0 PCIE_NTX_GRX_N0 PCIE_NTX_GRX_P1 PCIE_NTX_GRX_N1 PCIE_NTX_GRX_P2 PCIE_NTX_GRX_N2 PCIE_NTX_GRX_P3 PCIE_NTX_GRX_N3 PCIE_NTX_GRX_P4 PCIE_NTX_GRX_N4 PCIE_NTX_GRX_P5 PCIE_NTX_GRX_N5 PCIE_NTX_GRX_P6 PCIE_NTX_GRX_N6 PCIE_NTX_GRX_P7 PCIE_NTX_GRX_N7 PCIE_NTX_GRX_P8 PCIE_NTX_GRX_N8 PCIE_NTX_GRX_P9 PCIE_NTX_GRX_N9 PCIE_NTX_GRX_P10 PCIE_NTX_GRX_N10 PCIE_NTX_GRX_P11 PCIE_NTX_GRX_N11 PCIE_NTX_GRX_P12 PCIE_NTX_GRX_N12 PCIE_NTX_GRX_P13 PCIE_NTX_GRX_N13 PCIE_NTX_GRX_P14 PCIE_NTX_GRX_N14 PCIE_NTX_GRX_P15 PCIE_NTX_GRX_N15

ALINK_NBTX_SBRX_P0 20 ALINK_NBTX_SBRX_N0 20 ALINK_NBTX_SBRX_P1 20 ALINK_NBTX_SBRX_N1 20 ALINK_NBTX_SBRX_P2 20 ALINK_NBTX_SBRX_N2 20 ALINK_NBTX_SBRX_P3 20 ALINK_NBTX_SBRX_N3 20

+1.1V_RUN

2

PCIE_NTX_GRX_P[0..15] PCIE_NTX_GRX_N[0..15]

PCIE_NRX_GTX_P[0..15] PCIE_NRX_GTX_N[0..15]

LANE REVERSE

A-LINK

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

PCIE_NTX_GRX_P[0..15] 80 PCIE_NTX_GRX_N[0..15] 80

PCIE_NRX_GTX_P[0..15] 80 PCIE_NRX_GTX_N[0..15] 80

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

RS880M_HT LINK&PCIe(1/4)

Arsenal DJ1 Discrete

12 89Friday, May 07, 2010

1

X01

5

SSID = N.B

RS880M : 71.RS880.M05

D D

+1.8V_RUN

1 2

BLM15AG221SS1D-GP

220 ohm 300mA

1 2

BLM15AG221SS1D-GP

SC22U6D3V5MX-2GP

220 ohm 300mA

C1301

12

C C

B B

CPU_LDT_STOP#10,20

ALLOW_LDTSTOP20

A A

Layout Note Trace at least 15 mil

L1301

+1.8V_VDDA18HTPLL

SC2D2U6D3V3KX-GP

12

L1302

+1.8V_VDDA18PCIEPLL

SC2D2U6D3V3KX-GP

12

R1309

300R2J-4-GP

R1316 0R0402-PADR1316 0R0402-PAD

20mA

SCD1U10V2KX-4GP

C1302

C1303

12

120mA

SCD1U10V2KX-4GP

C1305

C1304

12

R1322 0R2J-2-GP

1 2

U1301

1

1A

2

GND 2A32Y

SN74LVC2G07DCKR-GP

X01

1 2

5

+1.8V_RUN+1.5V_RUN

12

R1311

DY

6

1Y

5

VCC

4

+1.8V_RUN

12

R1315

R1315 1KR2J-1-GP

1KR2J-1-GP

ALLOW_LDTSTOP: 1 = LDTSTOP# can be asserted 0 = LDTSTOP# has to be de-asserted

R1311 2K2R2J-2-GP

2K2R2J-2-GP

NB_LDT_STOP#

12

C1306

SCD1U10V2KX-4GP

NB_ALLOW_LDTSTOP

4

UMA

GREEN/BLUE: Connected to GND through two separate 150-



1% resistors.

RED: Connected to GND through two separate 140resistors.

NB_VGA_HSYNC NB_VGA_VSYNC

Trace at least 10 mil

+1.8V_VDDA18HTPLL

+1.8V_VDDA18PCIEPLL

PLTRST#_NB_GPU20,37

R1312

4K7R2F-GP

R1313

4K7R2F-GP

4

+1.1V_RUN

1 2

NB_PWRGD_IN41

0423

NB_REFCLK_N

12

CLK_NBHT_CLK7 CLK_NBHT_CLK#7

NB_14M_CLK7

NB_GFX_CLK7 NB_GFX_CLK#7

NB_GPPSB_CLK7 NB_GPPSB_CLK#7

R1318

R1318 2KR2J-1-GP

2KR2J-1-GP

NB_LDT_STOP# NB_ALLOW_LDTSTOP

TP1307TP1307

1

TP1308TP1308

1

TP1301TP1301 TP1302TP1302 TP1303TP1303 TP1304TP1304

TP1305TP1305

1 2

R1319 150R2F-1-GPR1319 150R2F-1-GP

3



1%

DIS

TV_OUT

DIS

R1306

1 2

715R2F-GP

NB_GPP_CLK NB_GPP_CLK#

TP_NB_DDC_DATA0

1

TP_NB_DDC_CLK0

1

TP_NB_DDC_CLK1

1

TP_NB_DDC_DATA1

1

TP_NB_RESERVED

1

RS780_AUX_CAL

3

DAC_RSET

+3.3V_RUN

3KR2J-2-GP

12

3KR2J-2-GP

12

DY

U1C

F12

AVDD1

E12

AVDD2

F14

AVDDDI

G15

AVSSDI

H15

AVDDQ

H14

AVSSQ

E17

C_Pr

F17

Y

F15

COMP_Pb

G18

RED

G17

REDb

E18

GREEN

F18

GREENb

E19

BLUE

F19

BLUEb

A11

DAC_HSYNC

B11

DAC_VSYNC

F8

DAC_SCL

E8

DAC_SDA

G14

DAC_RSE T

A12

PLLVDD

D14

PLLVDD1 8

B12

PLLVSS

H17

VDDA18H TPLL

D7

VDDA18P CIEPLL1

E7

VDDA18P CIEPLL2

D8

SYSRESET#

A10

POWE RGOOD

C10

LDTSTOP #

C12

ALLOW _LDTSTOP

C25

HT_REFC LKP

C24

HT_REFC LKN

E11

REFCLK_ P/OSCIN

F11

REFCLK_ N

T2

GFX_REF CLKP

T1

GFX_REF CLKN

U1

GPP_REF CLKP

U2

GPP_REF CLKN

V4

GPPSB_R EFCLKP

V3

GPPSB_R EFCLKN

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DAT A0/AUX0N

A8

DDC_CLK 0/AUX0P

B7

DDC_CLK 1/AUX1P

A7

DDC_DAT A1/AUX1N

B10

STRP_DA TA

G11

RESERVE D

C8

AUX_CAL

RS880M-1-GP

2

1

STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)

Enables debug bus access thro ugh memory I/O pads and GPIOs. 1 : Disable

3KR2J-2-GP

12

R1303

R1302

NB_VGA_VSYNC NB_VGA_HSYNC

3KR2J-2-GP

12

R1305

R1304

DY

*

0 : Enable

SIDE_PORT_EN# ( RS880M use DAC_HSYNC)

1 = Memory Side port Not avai lable

*

0 = Memory Side port availabl e

LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)

Selects Loading of STRAPS Fro m EEPROM 1 : use Default Values

*

0 : I2C Master can load strap values from EEPROM if connect ed, or use default values if not connected

*DEFAULT

TXCLK_L P TXCLK_L N TXCLK_U P

TXCLK_U N

VDDLTP1 8 VSSLTP1 8

VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7

HPD

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

A13 B13

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

TMDS_HPD

D9

HPD

D10

NB_SUS_STAT#

D12

AE8 AD8

TESTMODE_NB

D13

Title

Size Document Number Rev

Custom

Date: Sheet of

1 1

R1317

1 2

DY

0R2J-2-GP

1K8R2F-GP

12

R1320

RS880M_LVDS&CRT_(2/4)

Arsenal DJ1 Discrete

NB_SUS_STAT#

TP1311TP1311 TP1306TP1306

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

+3.3V_RUN

DY

SUS_STAT# 21

13 89Friday, May 07, 2010

R1314

R1314 4K7R2J-2-GP

4K7R2J-2-GP

1 2

12

R1321

R1321 3KR2J-2-GP

3KR2J-2-GP

X01

20mA

120mA

PART 3 OF 6

CRT/TVOUT

PM

CLOCKs PLL PWR

MIS.

LVTM

TXOUT_U 0P TXOUT_U 0N TXOUT_U 1P TXOUT_U 1N TXOUT_U 2P TXOUT_U 2N TXOUT_U 3P TXOUT_U 3N

LVDS_DIGO N

LVDS_BL ON

LVDS_EN A_BL

THERMAL DIODE_P THERMAL DIODE_N

2

TXOUT_L 0P TXOUT_L 0N TXOUT_L 1P TXOUT_L 1N TXOUT_L 2P TXOUT_L 2N TXOUT_L 3P TXOUT_L 3N

VDDLT18 _1

VDDLT18 _2

VDDLT33 _1

VDDLT33 _2

TMDS_HP D

SUS_STA T#

TESTMOD E

5

4

3

2

1

SSID = N.B

RS880M : 71.RS880.M05

D D

U1D

AB12

MEM_A0

AE16

MEM_A1

V11

MEM_A2

AE15

MEM_A3

AA12

MEM_A4

AB16

MEM_A5

AB14

MEM_A6

AD14

MEM_A7

AD13

MEM_A8

AD15

MEM_A9

AC16

MEM_A10

AE13

MEM_A11

AC14

MEM_A12

Y14

MEM_A13

AD16

MEM_BA0

AE17

MEM_BA1

AD17

MEM_BA2

W12

MEM_RAS#

Y12

MEM_CAS#

AD18

C C

AB13 AB18

W14

AE12 AD12

V14

V15

MEM_WE# MEM_CS# MEM_CKE MEM_ODT

MEM_CKP MEM_CKN

MEM_COMPP MEM_COMPN

RS880M-1 -GP

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC

MEM_DQ2/DVO_DE

MEM_DQ3/DVO_D0

MEM_DQ4 MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3 MEM_DQ9/DVO_D5

MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7

MEM_DQ12

MEM_DQ13/DVO_D9 MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11

MEM_DQS0P/DVO_IDCKP

MEM_DQS0N/DVO_IDCKN

MEM_DQS1P MEM_DQS1N

MEM_DM0

MEM_DM1/DVO_D8

SBD_MEM/DVO_I/F

IOPLLVDD18

IOPLLVDD

IOPLLVSS

MEM_VREF

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23

AE18

15mA

+1.8V_RU N

+1.1V_RU N

26mA

SBD MEM disable SBD MEM disable

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RS880M_SidePort_(3/4)

Size Document N umber Rev

A3

Date: Sheet of

RS880M_SidePort_(3/4)

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

14 89Friday, May 07, 2010

1

X01

5

4

3

2

1

SSID = N.B

RS880M : 71.RS880.M05

D D

+1.1V_RU N

C C

+1.1V_RU N

+1.8V_RU N

220 ohm @ 100MHz,2A

B B

+1.8V_RU N

R1501

1 2

0R3J-0-U-G P

R1502

1 2

0R3J-0-U-G P

R1503

1 2

0R3J-0-U-G P

L1505

1 2

PBY160808 T-221Y-N-GP

40 mils

SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

C1501

12

40 mils

SC10U6D3V5KX-1GP

SCD1U10V2KX-4GP

C1511

12

20 mils

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP

C1514

12

40 mils

SC4D7U6D3V3KX-GP

C1528

12

15 mils

SC1U6D3V2KX-GP

C1534

12

Layout Note

1.1V(0.6A) for VDDHT

+1.1V_RU N_VDDHT

SCD1U10V2KX-4GP

C1503

C1502

12

1.1V(0.7A) for VDDHTRX

+1.1V_RU N_VDDHTRX

SCD1U10V2KX-4GP

C1507

12

.2V(0.4A) for VDDHTTX

1

+1.2V_RU N_VDDHTTX

SCD1U10V2KX-4GP

C1515

12

1.8V(0.7A) for VDDA18PCIE

+1.8V_RU N_VDDA18PCIE

SCD1U10V2KX-4GP

C1529

12

C1503

C1506

12

SCD1U10V2KX-4GP

C1512

C1513

12

SCD1U10V2KX-4GP

C1516

C1517

12

SCD1U10V2KX-4GP

C1531

C1530

12

1.8V(0.01A) for VDD18

C1518

SCD1U10V2KX-4GP

C1533

C1532

12

SBD MEM disable

K16

M16 P16 R16 T16

H18 G19 F20 E21 D22 B23 A23

AE25 AD24 AC23 AB22 AA21

Y20

W19

V18 U17 T17 R17 P17 M17

P10 K10 M10

T10 R10

AA9 AB9 AD9 AE9 U10

AE11 AD11

J17

L16

J10

L10 W9

H9

Y9

F9

G9

U1E

VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2

RS880M-1 -GP

PART 5/6

POWER

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1 VDD_MEM2 VDD_MEM3 VDD_MEM4 VDD_MEM5 VDD_MEM6

VDD33_1 VDD33_2

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

1.1V(2.5A) for VDDPCIE

SCD1U10V2KX-4GP

C1508

12

1.1V(10A) for VDDC

SCD1U10V2KX-4GP

C1519

12

SC1U6D3V2KX-GP

C1504

C1509

12

SCD1U10V2KX-4GP

12

C1509

12

SCD1U10V2KX-4GP

C1521

C1520

12

SBD MEM disable

3.3V(0.06A) for VDD33

SCD1U10V2KX-4GP

C1535

C1536

12

C1536

12

SC4D7U6D3V3KX-GP

C1510

SCD1U10V2KX-4GP

C1522

1

30 mils

C1505

12

550 mils

SCD1U10V2KX-4GP

C1523

12

15 mils

Layout Note

U1F

A25

G22 G24 G25 H19

M20 N22 P20 R19 R22 R24 R25 H20 U22

V19 W22 W24 W25

Y21

AD25

M14

N13

P12

P15

R11

R14

U14

U11

U15

V12 W11 W15

AC12 AA14

Y18

AB11 AB15 AB17 AB19 AE20 AB21

K11

D23 E22

J22 L17 L22 L24 L25

L12

T12

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

RS880M-1 -GP

PART 6/6

+1.1V_RU N

0423

+NB_VCORE

+1.1V_RU N

SCD1U10V2KX-4GP

C1525

C1524

12

SC10U6D3V5KX-1GP

C1527

C1526

12

+3.3V_RU N

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

RS880M_PWR&GD_(4/4)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

15 89Friday, May 07, 2010

1

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 89Friday, May 07, 2010

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

17 89Friday, May 07, 2010

X01

5

MEM_MA_ADD[0..15]9

D D

MEM_MA_BANK29

MEM_MA_BANK09 MEM_MA_BANK19

M_A_DQ[63..0]9

C C

M_A_DQS#09 M_A_DQS#19 M_A_DQS#29 M_A_DQS#39

MEM_MA0_ODT09 MEM_MA0_ODT19

DDR3_A_DR AMRST#9

M_A_DQS#49 M_A_DQS#59 M_A_DQS#69 M_A_DQS#79

M_A_DQS09 M_A_DQS19 M_A_DQS29 M_A_DQS39 M_A_DQS49 M_A_DQS59 M_A_DQS69 M_A_DQS79

0423

SCD1U10V2KX- 5GP

12

DY

C1822

+0.75V_DDR_VT T

B B

+V_DDR_RE F

SCD1U10V2KX-4GP

C1810

SCD1U10V2KX-4GP

C1811

12

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

4

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1

30

203 204

DM1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12

2mA

DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

18uA

VREF_DQ

RESET#

VTT1

500mA

VTT2

DDR3-204P- 41-GP-U

62.10017.N41

62.10017.N41 H =5.2mm

RAS#

CAS#

CKE0 CKE1

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

CS0# CS1#

CK0#

CK1#

3

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

M_A_DM0

11

DM0

M_A_DM1

28

DM1

M_A_DM2

46

DM2

M_A_DM3

63

DM3

M_A_DM4

136

DM4

M_A_DM5

153

DM5

M_A_DM6

170

DM6

M_A_DM7

187

DM7

200

SDA

202

SCL

PM_EXTTS#0

198

199

197

SA0

201

SA1

77 122 125

3.5A

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

+1.5V_SUS

MEM_MA_RAS# 9 MEM_MA_WE# 9 MEM_MA_CAS# 9

MEM_MA0_CS#0 9 MEM_MA0_CS#1 9

MEM_MA_CKE0 9 MEM_MA_CKE1 9

MEM_MA_CLK0_P 9 MEM_MA_CLK0_N 9

MEM_MA_CLK1_P 9 MEM_MA_CLK1_N 9

M_A_DM[7..0] 9

SB_SMBDATA 7,19,21,76 SB_SMBCLK 7,19,21,76

Layout Note: Place these Caps near SO-DIMMA.

12

C1802

C1802 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

+3.3V_RUN

SODIMM A DECOUPLING (ONE CAP PER POWER PIN)

+1.5V_SUS

12

C1805

C1806

C1804

SCD1U16V2KX-3GP

C1814

C1813

C1812

SC10U10V5ZY-1GP

DY

12

DY

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

12

C1808

C1807

C1809

SCD1U16V2KX-3GP

C1815

C1817

C1816

SC10U10V5ZY-1GP

12

DY

12

DY

PM_EXTTS#0

0423

12

TC1801

TC1801 SE330U2VDM-L- GP

SE330U2VDM-L- GP

2

1 2

DY

1

+1.5V_SUS

R18064K7R2J-2-GPDYR18064K7R2J-2-GP

Place these caps close to VTT1 and

A A

VTT2.

5

C1819

12

SC4D7U6D3V3KX-GP

C1820

12

C1821

SCD1U16V2KX-3GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM1

Arsenal DJ1 Discrete

1

X01

18 89Friday, May 07, 2010

X01

5

MEM_MB_ADD[0..15]9

D D

C C

B B

+V_DDR_RE F

SCD1U10V2KX-4GP

C1904

C1905

12

Place these caps close to VTT1 and VTT2.

A A

MEM_MB_BANK29

MEM_MB_BANK09 MEM_MB_BANK19

M_B_DQ[63..0]9

M_B_DQS#09 M_B_DQS#19 M_B_DQS#29 M_B_DQS#39 M_B_DQS#49 M_B_DQS#59 M_B_DQS#69 M_B_DQS#79

M_B_DQS09 M_B_DQS19 M_B_DQS29 M_B_DQS39 M_B_DQS49 M_B_DQS59 M_B_DQS69 M_B_DQS79

MEM_MB0_ODT09

SCD1U10V2KX-4GP

MEM_MB0_ODT19

DDR3_B_DR AMRST#9

C1921

SCD1U10V2KX- 5GP

0423

+0.75V_DDR_VT T

12

C1919

C1920

C1918

SC4D7U6D3V3KX-GP

C1920

SCD1U16V2KX-3GP

DY

12

DY

12

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 40-GP-U

62.10017.N11

H = 9.2mm

500mA

NP1

NP2

110

RAS#

113

WE#

115

CAS#

114

CS0#

121

CS1#

73

CKE0

74

CKE1

101

CK0

103

CK0#

102

CK1

104

CK1#

M_B_DM0

11

DM0

M_B_DM1

28

DM1

M_B_DM2

46

DM2

M_B_DM3

63

DM3

M_B_DM4

136

DM4

M_B_DM5

153

DM5

M_B_DM6

170

DM6

M_B_DM7

187

DM7

200

SDA

202

SCL

PM_EXTTS#1

198

EVENT#

199

VDDSPD

2mA

197

SA0

201

SA1

77

NC#1

122

NC#2

125

NC#/TEST

18uA

3.5A

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

SO-DIMMB is placed farther from the Processor than SO-DIMMA

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

+1.5V_SUS

MEM_MB_RAS# 9 MEM_MB_WE# 9 MEM_MB_CAS# 9

MEM_MB0_CS#0 9 MEM_MB0_CS#1 9

MEM_MB_CKE0 9 MEM_MB_CKE1 9

MEM_MB_CLK0_P 9 MEM_MB_CLK0_N 9

MEM_MB_CLK1_P 9 MEM_MB_CLK1_N 9

M_B_DM[7..0] 9

+3.3V_RUN

3

SB_SMBDATA 7,18,21,76 SB_SMBCLK 7,18,21,76

Layout Note: Place these Caps near SO-DIMMB.

12

C1902

C1902 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

+3.3V_RUN

C1906

C1912

+1.5V_SUS

12

SCD1U16V2KX-3GP

SC10U10V5ZY-1GP

12

DY

2

+1.5V_SUS

PM_EXTTS#1

1 2

DY

R19064K7R2J-2-G PDYR19064K7R2J-2-G P

SODIMM B DECOUPLING (ONE CAP PER POWER PIN)

C1907

C1913

12

C1908

SCD1U16V2KX-3GP

C1914

SC10U10V5ZY-1GP

12

DY

12

C1910

C1909

C1911

SCD1U16V2KX-3GP

C1916

C1915

C1917

SC10U10V5ZY-1GP

12

DY

12

DY

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Title

Size Document Num ber Rev

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O.C.

DDR3-SODIMM2

Arsenal DJ1 Discrete

1

X01

19 89Friday, May 07, 2010

X01

5

SSID = S.B

C2001 SC150P5 0V2KX-GPC2001 SC150 P50V2KX-GP

1 2

ALINK_NBR X_SBTX_P012 ALINK_NBR X_SBTX_N012 ALINK_NBR X_SBTX_P112

LAN

WLAN

ALINK_NBR X_SBTX_N112 ALINK_NBR X_SBTX_P212 ALINK_NBR X_SBTX_N212 ALINK_NBR X_SBTX_P312 ALINK_NBR X_SBTX_N312

ALINK_NBT X_SBRX_P012 ALINK_NBT X_SBRX_N012 ALINK_NBT X_SBRX_P112 ALINK_NBT X_SBRX_N112 ALINK_NBT X_SBRX_P212 ALINK_NBT X_SBRX_N212 ALINK_NBT X_SBRX_P312 ALINK_NBT X_SBRX_N312

+1.1V_RU N_PCIE_VDDR

PCIE_TXN176

PCIE_TXN076

PCIE_TXP176

PCIE_TXP076

D D

Place R <100mils form p

ins AD29,AD28

SB820M: 71.SB820.M02

R2024 22R2J-2-GPR2024 22R2J-2-G P

C2002 SCD1U16 V2KX-3GPC2002 SCD1U16 V2KX-3GP

1 2

C2003 SCD1U16 V2KX-3GPC2003 SCD1U16 V2KX-3GP

1 2

C2004 SCD1U16 V2KX-3GPC2004 SCD1U16 V2KX-3GP

1 2

C2005 SCD1U16 V2KX-3GPC2005 SCD1U16 V2KX-3GP

1 2

C2006 SCD1U16 V2KX-3GPC2006 SCD1U16 V2KX-3GP

1 2

C2007 SCD1U16 V2KX-3GPC2007 SCD1U16 V2KX-3GP

1 2

C2008 SCD1U16 V2KX-3GPC2008 SCD1U16 V2KX-3GP

1 2

C2009 SCD1U16 V2KX-3GPC2009 SCD1U16 V2KX-3GP

1 2

R2002 590R2F-GPR2002 590R2F-GP

1 2

R2007 2KR2F-3-GPR200 7 2KR2F-3-G P

1 2

C2018SCD1U16 V2KX-3GP C2018SCD1U16 V2KX-3GP

12

C2019SCD1U16 V2KX-3GP C2019SCD1U16 V2KX-3GP

12

C2020SCD1U16 V2KX-3GP C2020SCD1U16 V2KX-3GP

12

C2021SCD1U16 V2KX-3GP C2021SCD1U16 V2KX-3GP

12

ALINK_NBR X_SBTX_C_P0 ALINK_NBR X_SBTX_C_N0 ALINK_NBR X_SBTX_C_P1 ALINK_NBR X_SBTX_C_N1 ALINK_NBR X_SBTX_C_P2 ALINK_NBR X_SBTX_C_N2 ALINK_NBR X_SBTX_C_P3 ALINK_NBR X_SBTX_C_N3

0423

LAN

C C

NOTE: SB8XX ONLY SUPPORTS 2 GPP PORT 2 AND 3 IS NOT SUPPORTED. (From CRB)

B B

WLAN

PCIE_RXP17 6 PCIE_RXN176 PCIE_RXP07 6 PCIE_RXN076

SB_PCIE_C LK7 SB_PCIE_C LK#7 SB_GPIO_A _RST#21

USE EXTERNAL CLKGEN

0824

1nd 82.30020.851 2nd 82.30020.791

A A

R2017 1MR2J-1-GPR 2017 1MR2J-1-G P

1 2

X2001

1 2

XTAL-25M HZ-102-GP

C2014

C2014 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

1 2

5

1 2

C2015

C2015 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

TP2009TP2009

25M_X1

25M_X2

4

PCIE_RST# _SB

A_RST#_ RA_RST#

SB_PCIE_C ALRP SB_PCIE_C ALRN

PCIE_C_TX P1

PCIE_C_TX N1

PCIE_C_TX P0

PCIE_C_TX N0

OSC_CLK

1

25M_X1

25M_X2

4

U2A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M-1-GP

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

REQ2#/CLK_REQ8#/GPIO41

PCI INTERFACELPC

REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

ALLOW_LDTSTP/DMA_ACTIVE#

CLOCK GENERATOR

CPU

RTC

3

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR STOP# PERR# SERR# REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44 GNT2#/GPO45

CLKRUN#

LOCK#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

PROCHOT#

LDT_PG LDT_STP# LDT_RST#

32K_X1

32K_X2

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

3

W2 W1 W3 W4 Y1

PCI_RST#

V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4

SB_GPIO42

AC12 AD12 AJ5 AH6

SB_GPIO46

AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25

LPC_LAD 0_R

J27

LPC_LAD 1_R

J26

LPC_LAD 2_R

H29

LPC_LAD 3_R

H28 G28

TP_LPC_ LDRQ0#

J25

TP_LPC_ LDRQ1#

AA18 AB19

G21 H21 K19 G22 J24

32K_X1

C1

32K_X2_ R

C2

RTC_CLK

D2

INTRUDER_ ALERT#

B2 B1

1

TP2008TP2008

SB_GPIO_P CIE_RST#2 1

PCIE_RST# _SB

SB_GPIO28

1

SB_GPIO29

1

RN2009 SRN33J-4 -GPRN2009 SRN33J-4 -GP

1

1 2

R2009 22R2J-2-G PR2009 2 2R2J-2-GP

1'nd 73.01G08.DHG 2'nd 73.01G08.L04

PCI_AD23 24 VDDR_SE L 24,51 PCI_AD25 24 PCI_AD26 24 PCI_AD27 24

TP2010TP2010 TP2011TP2011

1'nd 73.01G08.DHG 2'nd 73.01G08.L04

A_RST#

TP2003TP2003

TP2004TP2004

RN2008

RN2008 SRN22-3-G P

SRN22-3-G P

1

4 2 3 1

8 2

7 3

6 4 5

1 1

0423

TP2005TP2005 TP2006TP2006

INT_SERIRQ 37

ALLOW _LDTSTOP 13

CPU_PRO CHOT# 10 CPU_LDT _PWRGD 10,4 2 CPU_LDT _STOP# 10,1 3 CPU_LDT _RST# 10

1 2

R2018 10R 2J-2-GPR20 18 10R2 J-2-GP

TP2007TP2007

SCD1U10V2KX-4GP

12

DY

2

PCI_CLK1 2 4 PCI_CLK2 2 4 PCI_CLK3 2 4,70 PCLK_FW H 24

0423

U2002

SNLVC1G 08DCKRG4-GP

1

A

VCC

2

B

DY

GND3Y

12

R202533R2J-2-G P R202533R2J-2 -GP

U2001

SNLVC1G 08DCKRG4-GP

1

A

VCC

2

B

DY

GND3Y

1 2

R2021 0R0402-PADR202 1 0R0 402-PAD

PCLK_KB C 24,37 LPCCLK1 2 4

LPC_LFR AME# 37 ,70

LPC Bus Routing first connects to MINICARD then connects to KBC

RTCCLK_ KBC 37

RTC_CLK 39

+RTC_CE LL

C2017

2

STRAP PIN

+3.3V_AL W

5

4

+3.3V_AL W

5

4

SCD1U10V2KX-4GP

DY

PLTRST#

12

1 2

C2010

0423

C2013

C2013 SC150P5 0V2KX-GP

SC150P5 0V2KX-GP

R2005

R2008

X01

PM_CLKR UN# 37

LPC_LAD 0 37,70 LPC_LAD 1 37,70 LPC_LAD 2 37,70 LPC_LAD 3 37,70

32K_X1

32K_X2_ R 32K_X2

0R2J-2-GP

Title

SB820M_PCIE&PCI_(1/5)

ize Document Nu mber Rev

Size Document N umber Rev

S

A3

Date: Sheet of

placed CAP closed SB820M

0423

+3.3V_RU N

12

R2026

R2026 10KR2J-3 -GP

10KR2J-3 -GP

0R2J-2-GP

1 2

0R2J-2-GP

1 2

12

R2014

20MR3-GP

R2016

12

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

1

PCI_CLK3

EC2002

PLTRST# _LAN_WLAN 70,76

PLTRST# _NB_GPU 1 3,37

PLTRST# _EC 37

SC12P50 V2JN-3GP

1 2

0423

X2002

X2002 X-32D768 KHZ-40GPU

X-32D768 KHZ-40GPU

4

1

2 3

1 2

C2012

C2012 SC12P50 V2JN-3GP

SC12P50 V2JN-3GP

20 89Friday, May 07, 2010

1

12

DY

SC10P50V2JN-4GP

GPU,NB

KBC

C2011

X01

5

SB820M: 71.SB820.M02

SSID = S.B

+3.3V_RUN

RN2101

1 2 3

SRN2K2J-1-GP

D D

C C

B B

A A

SRN2K2J-1-GP

1 2

R2127 10KR2J-3-GPR2127 10KR2J-3-GP

+3.3V_ALW

RN2103

1 2 3

SRN10KJ-5-GP

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1 2

4K7R2J-2-GP

1 2

DY

R2118 10KR2J-3-GP

1 2

DY

R2119 10KR2J-3-GP

1 2

DY

R2133 10KR2J-3-GP

Close SB

1 2

DY

C2101 SCD1U10V2KX-4GP

+3.3V_ALW

1 2 3 4 5

SRN10KJ-6-GP

R2124 10KR2J-3-GPR2124 10KR2J-3-GP

1 2

1 2 3

TP_SB_GPIO64 TP_SB_GPIO63 TP_SB_GPIO62

USB_OC#2_3 USB_OC#0_1

4

R2108

R2108 2K2R2J-2-GP

2K2R2J-2-GP

R2110

R2110 2K2R2J-2-GP

2K2R2J-2-GP

R2112

R2112 2K2R2J-2-GP

2K2R2J-2-GP

R2113

R2113 10KR2J-3-GP

10KR2J-3-GP

R2114

R2114 10KR2J-3-GP

10KR2J-3-GP

R2115

R2115 10KR2J-3-GP

10KR2J-3-GP

R2116

R2116 10KR2J-3-GP

10KR2J-3-GP

R2117

R2117 10KR2J-3-GP

10KR2J-3-GP R2134

R2134

RN2102

RN2104

SRN10KJ-5-GP

4

1 1 1

1 1

SB_SMBCLK SB_SMBDATA

SUS_STAT#

SMB_DATA

SMB_CLK

SB_TEST2

SB_TEST1

SB_TEST0

PCIE_WAKE#

KBC_RSMRST#

SIO_EXT_WAKE#

SIO_EXT_SCI#

SIO_EXT_SMI#

TALERT#

SB_SDIN_CODEC

ACZ_BIT_CLK

SP_VRAM_SEL

PM_RSMRST#_R

8 7 6

GBE_RXERR

4

TP2121TP2121 TP2122TP2122 TP2127TP2127

TP2134TP2134

J

TP2135TP2135

JTAG_RST#

5

0423

GBE_MDIO GBE_CRS GBE_COL

GBE_PHY_INTR

SCL2 SDA2

TAG_TDI

SB_AZ_CODEC_BITCLK30 SB_AZ_CODEC_SDOUT30

SB_SDIN_CODEC30

SB_AZ_CODEC_SYNC30 SB_AZ_CODEC_RST#30

GbE Controller Not Enabled

EC Not Implemented

SIO_EXT_WAKE#37

PM_SLP_S3#37,41,42,49,52,86 PM_SLP_S5#37,49

PM_PWRBTN#37 SB_PWRGD7,41

SIO_A20GATE37 SIO_RCIN#37 SIO_EXT_SCI#37 SIO_EXT_SMI#37

PCIE_WAKE#76

H_THERMTRIP#10,37,39,42

NB_PWRGD41

KBC_RSMRST#37

SB_GPIO_A_RST#20 SB_GPIO_PCIE_RST#20

ACZ_SPKR30 SB_SMBCLK7,18,19,76 SB_SMBDATA7,18,19,76

SB_14M_CLK7

TALERT#10,39

ACZ_SDATAOUT_R24

1 2 1 2

4

R2111

1 2

0R0402-PAD

R2125

1 2

0R0402-PAD

1 2

R2126 0R0402-PADR2126 0R0402-PAD

X01

R2129 0R2J-2-GPR2129 0R2J-2-GP

1 2

R2130 0R2J-2-GPR2130 0R2J-2-GP

1 2

0423

1 2

USB_OC#2_363 USB_OC#0_163

33R2J-2-GPR2120 33R2J-2-GPR2120 33R2J-2-GPR2121 33R2J-2-GPR2121

33R2J-2-GPR2122 33R2J-2-GPR2122 33R2J-2-GPR2123 33R2J-2-GPR2123

4

TP2101TP2101

X01

1 2

SUS_STAT#13

TP2120TP2120

1 2

DY

R21090R2J-2-GPDYR21090R2J-2-GP

SB_GPIO_A_RST#_R SB_GPIO_PCIE_RST#_R

0423

TP2113TP2113

SBD DDR RESET

DY

R21280R2J-2-GP

TP2138TP2138 TP2139TP2139

TP2137TP2137 TP2132TP2132 TP2133TP2133

TP2128TP2128 TP2131TP2131 TP2116TP2116 TP2117TP2117

1

PM_PWRBTN#_R

R21060R0402-PAD R21060R0402-PAD

SYS_RESET#

1

SB_THERMTRIP#

PM_RSMRST#_R

TP_SB_GPIO64 TP_SB_GPIO63

TP_SB_GPIO62 SP_VRAM_SEL

SB_OSCIN

USB_OC7#

1

USB_OC6#

1

TALERT# USB_OC4#

1

TP_JTAG_TDO

1

TP_JTAG_TCK

1

USB_OC#2_3 USB_OC#0_1

ACZ_BIT_CLK

ACZ_SYNC_R ACZ_RST#_R

GBE_COL GBE_CRS

GBE_MDIO

GBE_RXERR

GBE_PHY_INTR

TP_DEBUG_DAT

1

TP_DEBUG_CLK

1

SPI_CS2#

1

GPO160

1

TP_PCI_PME#

SUS_STAT#

SB_TEST0 SB_TEST1 SB_TEST2

SCL0

SDA0 SMB_CLK SMB_DATA

SB_GPIO51

1

U2D

J2

PCI_PME#/GE VENT4#

K1

RI#/GEVENT 22#

D3

SPI_CS3#/G BE_STAT1/GEVEN T21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_ BTN#

H5

PWR_ GOOD

G6

SUS_STA T#

B3

TEST0

C4

TEST1/TM S

F6

TEST2

AD21

GA20IN/GEVE NT0#

AE21

KBRST#/G EVENT1#

K2

LPC_PME #/GEVENT3#

J29

LPC_SMI#/GE VENT23#

H2

GEVENT5 #

J1

SYS_RESET #/GEVENT19#

H6

WAKE #/GEVENT8#

F3

IR_RX1/GEV ENT20#

J6

THRMTRIP# /SMBALERT#/GEVE NT2#

AC19

NB_PW RGD

G1

RSMRST#

AD19

CLK_REQ 4#/SATA_IS0#/GPIO64

AA16

CLK_REQ 3#/SATA_IS1#/GPIO63

AB21

SMARTVO LT1/SATA_IS2#/GPIO5 0

AC18

CLK_REQ 0#/SATA_IS3#/GPIO60

AF20

SATA_IS4# /FANOUT3/GPIO55

AE19

SATA_IS5# /FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO22 7

F4

SDA1/GPIO22 8

AH21

CLK_REQ 2#/FANIN4/GPIO62

AB18

CLK_REQ 1#/FANOUT4/GPIO61

E1

IR_LED#/LL B#/GPIO184

AJ21

SMARTVO LT2/SHUTDOW N#/GPIO51

H4

DDR3_RS T#/GEVENT7#

D5

GBE_LED 0/GPIO183

D7

GBE_LED 1/GEVENT9#

G5

GBE_LED 2/GEVENT10#

K3

GBE_STA T0/GEVENT11#

AA20

CLK_REQ G#/GPIO65/OSCIN/IDLEEXT #

H3

BLINK/USB_ OC7#/GEVENT18#

D1

USB_OC6 #/IR_TX1/GEVENT6#

E4

USB_OC5 #/IR_TX0/GEVENT17 #

D4

USB_OC4 #/IR_RX0/GEVENT16 #

E8

USB_OC3 #/AC_PRES/TDO/G EVENT15#

F7

USB_OC2 #/TCK/GEVENT14 #

E7

USB_OC1 #/TDI/GEVENT13#

F8

USB_OC0 #/TRST#/GEVENT 12#

M3

AZ_BITCLK

N1

AZ_SDOU T

L2

AZ_SDIN0/G PIO167

M2

AZ_SDIN1/G PIO168

M1

AZ_SDIN2/G PIO169

M4

AZ_SDIN3/G PIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDC K

L5

GBE_MDIO

T9

GBE_RXC LK

U1

GBE_RXD 3

U3

GBE_RXD 2

T2

GBE_RXD 1

U2

GBE_RXD 0

T5

GBE_RXC TL/RXDV

V5

GBE_RXE RR

P5

GBE_TXC LK

M5

GBE_TXD 3

P9

GBE_TXD 2

T7

GBE_TXD 1

P7

GBE_TXD 0

M7

GBE_TXC TL/TXEN

P4

GBE_PHY_P D

M9

GBE_PHY_R ST#

V7

GBE_PHY_INTR

E23

PS2_DAT /SDA4/GPIO187

E24

PS2_CLK /SCL4/GPIO188

F21

SPI_CS2#/G BE_STAT2/GPIO166

G29

FC_RST# /GPO160

D27

PS2KB_D AT/GPIO189

F28

PS2KB_C LK/GPIO190

F29

PS2M_DA T/GPIO191

E27

PS2M_CL K/GPIO192

SB820M-1-GP

3

Part 4 of 5

HD AUDIO

GBE LAN

3

USBCLK/1 4M_25M_48M_O SC

ACPI / WAKE UP EVENTS

GPIO

USB OC

EC_PW M0/EC_TIMER0/GP IO197 EC_PW M1/EC_TIMER1/GP IO198 EC_PW M2/EC_TIMER2/GP IO199 EC_PW M3/EC_TIMER3/GP IO200

EMBEDDED CTRL

USB_RCO MP

USB_FSD 1P/GPIO186

USB_FSD 0P/GPIO185

USB_HSD 13P USB_HSD 13N

USB 1.1USB MISCEMBEDDED CTRL

USB_HSD 12P USB_HSD 12N

USB_HSD 11P USB_HSD 11N

USB_HSD 10P USB_HSD 10N

USB_HSD 9N

USB_HSD 8N

USB_HSD 7N

USB 2.0

USB_HSD 6N

USB_HSD 5N

USB_HSD 4N

USB_HSD 3N

USB_HSD 2N

USB_HSD 1N

USB_HSD 0N

SCL2/GPIO19 3

SDA2/GPIO19 4

SCL3_LV /GPIO195

SDA3_LV /GPIO196

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

KSO_0/GP IO209 KSO_1/GP IO210 KSO_2/GP IO211 KSO_3/GP IO212 KSO_4/GP IO213 KSO_5/GP IO214 KSO_6/GP IO215 KSO_7/GP IO216 KSO_8/GP IO217

KSO_9/GP IO218 KSO_10/G PIO219 KSO_11/G PIO220 KSO_12/G PIO221 KSO_13/G PIO222 KSO_14/G PIO223 KSO_15/G PIO224 KSO_16/G PIO225 KSO_17/G PIO226

USB_FSD 1N

USB_FSD 0N

USB_HSD 9P

USB_HSD 8P

USB_HSD 7P

USB_HSD 6P

USB_HSD 5P

USB_HSD 4P

USB_HSD 3P

USB_HSD 2P

USB_HSD 1P

USB_HSD 0P

A10

G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB_RCOMP

TP_USB_PP8 TP_USB_PN8

TP_USB_PP5 TP_USB_PN5

USB_PP3 USB_PN3

SCL2 SDA2

2

TP2140TP2140 TP2141TP2141

USB_48M_CLK 7

USB_PP11 54 USB_PN11 54

USB_PP10 32 USB_PN10 32

USB_PP9 73 USB_PN9 73

1 2

R2102

R2102 11K8R2F-GP

11K8R2F-GP

1 1

0423

TP2142TP2142

1

TP2143TP2143

1

USB_PP4 76

TP2114TP2114 TP2115TP2115

USB_PN4 76

USB_PP2 76 USB_PN2 76

USB_PP1 63 USB_PN1 63

USB_PP0 63 USB_PN0 63

0423

1 1

Not use

CPU_SIC 10 CPU_SID 10

SB_GPO199 24 SB_GPO200 24

Strap Pin / define to use LPC or SPI ROM

EC Not Implemented

Title

SB820M_USB&GPIO_(2/5)

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

2

Date: Sheet of

1

USB

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

Device

USB2

USB3

USB0 (I/O Board)

USB1 (I/O Board, 17")

WLAN

RESERVED

BLUETOOTH

CARD READER

CAMERA

RESERVED

21 89Friday, May 07, 2010

1

X01

SSID = S.B

SB820M: 71.SB820.M02

0916

XTAL 1'nd 82.30020.851

C2209

1 2

SC12P50V2JN-3GP

C2210

1 2

SC12P50V2JN-3GP

2'nd 82.30020.791

XTAL-25MHZ-102-GP

DY

XTAL-25MHZ-102-GP

12

DY

10MR2J-L-GP

12

X2201

R2204

DY

SATA HDD

SATA ODD

SATA_X1

SATA_X2

SATA_TXP059 SATA_TXN059

SATA_RXN059 SATA_RXP059

SATA_TXP159 SATA_TXN159

SATA_RXN159 SATA_RXP159

C2201 SCD01U50V2KX-1GPC2201 SCD01U50V2KX-1GP

1 2

C2202 SCD01U50V2KX-1GPC2202 SCD01U50V2KX-1GP

1 2

C2203 SCD01U50V2KX-1GPC2203 SCD01U50V2KX-1GP

1 2

C2204 SCD01U50V2KX-1GPC2204 SCD01U50V2KX-1GP

1 2

C2205 SCD01U50V2KX-1GPC2205 SCD01U50V2KX-1GP

1 2

C2206 SCD01U50V2KX-1GPC2206 SCD01U50V2KX-1GP

1 2

C2208 SCD01U50V2KX-1GPC2208 SCD01U50V2KX-1GP

1 2

C2207 SCD01U50V2KX-1GPC2207 SCD01U50V2KX-1GP

1 2

PLACE SATA AC DECOUPLING CAPS CLOSE TO SB820M

+1.1V_RUN_AVDD_SATA

SPI ROM in KBC side

Very Close to SB820

1KR2F-3-GP

R2201

1 2

R2202 931R2F-1-GPR2202 931R2F-1-GP

SATA_ACT#66

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

SATA_TXP1_C SATA_TXN1_C

SATA_RXN1_C SATA_RXP1_C

SATA_CALP

SATA_CALN

SATA_X1

SATA_X2

0423

U2B

AH9

SATA_TX 0P

AJ9

SATA_TX 0N

AJ8

SATA_RX 0N

AH8

SATA_RX 0P

AH10

SATA_TX 1P

AJ10

SATA_TX 1N

AG10

SATA_RX 1N

AF10

SATA_RX 1P

AG12

SATA_TX 2P

AF12

SATA_TX 2N

AJ12

SATA_RX 2N

AH12

SATA_RX 2P

AH14

SATA_TX 3P

AJ14

SATA_TX 3N

AG14

SATA_RX 3N

AF14

SATA_RX 3P

AG17

SATA_TX 4P

AF17

SATA_TX 4N

AJ17

SATA_RX 4N

AH17

SATA_RX 4P

AJ18

SATA_TX 5P

AH18

SATA_TX 5N

AH19

SATA_RX 5N

AJ19

SATA_RX 5P

AB14

SATA_CA LRP

AA14

SATA_CA LRN

AD11

SATA_AC T#/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO16 3

K4

SPI_CLK/GP IO162

K9

SPI_CS1#/G PIO165

G2

ROM_RST #/GPIO161

SB820M-1-GP

Part 2 of 5

SERIAL ATA

TEMPIN3/TA LERT#/GPIO174

HW MONITOR

SPI ROM

FC_CLK

FC_FBCL KOUT

FC_FBCL KIN

FC_OE#/G PIOD145

FC_AVD# /GPIOD146

FC_W E#/GPIOD148 FC_CE1# /GPIOD149 FC_CE2# /GPIOD150

FC_INT1/GP IOD144

FC_INT2/GP IOD147

FC_ADQ0 /GPIOD128 FC_ADQ1 /GPIOD129 FC_ADQ2 /GPIOD130 FC_ADQ3 /GPIOD131 FC_ADQ4 /GPIOD132 FC_ADQ5 /GPIOD133 FC_ADQ6 /GPIOD134 FC_ADQ7 /GPIOD135 FC_ADQ8 /GPIOD136

FC_ADQ9 /GPIOD137 FC_ADQ1 0/GPIOD138 FC_ADQ1 1/GPIOD139 FC_ADQ1 2/GPIOD140 FC_ADQ1 3/GPIOD141 FC_ADQ1 4/GPIOD142 FC_ADQ1 5/GPIOD143

FLASH

FANOUT0 /GPIO52 FANOUT1 /GPIO53 FANOUT2 /GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GP IO171 TEMPIN1/GP IO172 TEMPIN2/GP IO173

TEMP_CO MM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_S TAT3/GPIO181

VIN7/GBE_L ED3/GPIO182

NC#G27

NC2#Y2

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6 Y9

W7 V9 W8

B6 A6 A5 B5 C7

A3 B4 A4 C5 A7 B7 B8 A8

G27 Y2

GPIOD[150:128] are open drain GPIO pins where as GPO160 is an open drain GPO pin. These pins are not programmed to GPIO mode by default.

If use as GPIO, need to pull up to 1.8V_RUN

TEMPIN0 TEMPIN1 TEMPIN2 TEMPIN3

VIN0 VIN1 VIN2 VIN3 MEM_1V5 VIN5 VIN6 VIN7

suggest not use HW monitor

MEM_1V5 51

TEMPIN2 TEMPIN3 TEMPIN1 TEMPIN0

VIN0 VIN1 VIN2

X01

VIN5 VIN3 VIN7 VIN6

1 2 3 4 5

RN2201

8 7 6

SRN10KJ-6-GP

RN2202

8 7 6

SRN10KJ-6-GP

RN2203

8 7 6

SRN10KJ-6-GP

+3.3V_ALW

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Number Rev

Size Document Number Rev

S

Custom

Date: Sheet of

SB820M_SATA-IDE_(3/5)

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

22 89Friday, May 07, 2010

X01

5

4

3

2

1

SSID = S.B

SB820M: 71.SB820.M02

+3.3V_RUN

D D

+1.8V_RUN

Flash Controller func, not supported by the SB 820M

+3.3V_RUN

BLM15AG221SS1D-GP

220 ohm 300mA

C C

+1.1V_RUN +1.1V_RUN_PCIE_VDDR

PBY160808T-330Y-N-GP

+3.3V_RUN

BLM15AG221SS1D-GP

220 ohm 300mA

+1.1V_RUN +1.1V_RUN_AVDD_SATA

1 2

PBY160808T-330Y-N-GP

B B

PBY160808T-330Y-N-GP

+3.3V_ALW +3.3V_AVDD_USB

1 2

PBY160808T-221Y-N-GP

220 ohm @ 100MHz,2A

+1.1V_ALW +1.1V_AVDD_USB

1 2

BLM15AG221SS1D-GP

220 ohm 300mA

R2301

1 2

0R3J-0-U-GP

R2302

1 2

0R3J-0-U-GP

L2301

1 2

L2303

1 2

33R 3A

L2304

1 2

L2305

L2307

L2309

+3.3V_SB_VDDIO

+1.8V_SB_VDDIO_FC

+3.3V_VDDPL_PCIE

+3.3V_VDDPL_SATA

SC22U6D3V5MX-2GP

12

SC4D7U6D3V3KX-GP

12

DY

SC2D2U6D3V3KX-GP

12

SC22U6D3V5MX-2GP

12

SC2D2U6D3V3KX-GP

12

SC22U6D3V5MX-2GP

12

SC1U6D3V2KX-GP

12

SC2D2U6D3V3KX-GP

12

C2301

TC2301

12

SCD1U10V2KX-4GP

C2305

C2306

12

DY

SCD1U10V2KX-4GP

C2313

C2314

12

DY

SC1U6D3V2KX-GP

TC2303

C2319

12

DY

SCD1U10V2KX-4GP

C2325

C2326

12

DY

SC1U6D3V2KX-GP

TC2304

C2337

C2343

SC1U6D3V2KX-GP

C2330

12

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

C2338

12

SCD1U10V2KX-4GP

C2344

12

C2320

C2331

C2339

C2302

12

SCD1U10V2KX-4GP

SC10U6D3V5KX-1GP

SCD1U10V2KX-4GP

71mA

43mA

600mA

SCD1U10V2KX-4GP

C2321

12

93mA

567mA

SCD1U10V2KX-4GP

C2332

12

658mA

C2340

12

TBDmA

C2303

12

U2E

Part 5 of 5

Y14

U2C

AH1

VDDIO_33_ PCIGP

V6

VDDIO_33_ PCIGP

Y19

VDDIO_33_ PCIGP

AE5

VDDIO_33_ PCIGP

AC21

VDDIO_33_ PCIGP

AA2

VDDIO_33_ PCIGP

AB4

VDDIO_33_ PCIGP

AC8

VDDIO_33_ PCIGP

AA7

VDDIO_33_ PCIGP

AA9

VDDIO_33_ PCIGP

AF7

VDDIO_33_ PCIGP

AA19

VDDIO_33_ PCIGP

AF22

VDDIO_18_ FC

AE25

VDDIO_18_ FC

AF24

VDDIO_18_ FC

AC22

VDDIO_18_ FC

POWER

AE28

VDDPL_3 3_PCIE

U26

VDDAN_1 1_PCIE

V22

VDDAN_1 1_PCIE

W22 W26

AD14

AJ20

AF18 AH20 AG19

AE18 AD18

AE16

V26 V27 V28 V29

A18 A19 A20 B18 B19 B20 C18 C20 D18 D19 D20 E19

C11 D11

VDDAN_1 1_PCIE VDDAN_1 1_PCIE VDDAN_1 1_PCIE VDDAN_1 1_PCIE VDDAN_1 1_PCIE VDDAN_1 1_PCIE

VDDPL_3 3_SATA

VDDAN_1 1_SATA VDDAN_1 1_SATA VDDAN_1 1_SATA VDDAN_1 1_SATA VDDAN_1 1_SATA VDDAN_1 1_SATA VDDAN_1 1_SATA

VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S VDDAN_3 3_USB_S

VDDAN_1 1_USB_S VDDAN_1 1_USB_S

SB820M-1-GP

C2322

12

C2333

12

Part 3 of 5

PCI/GPIO I/O

FLASH I/O

GBE LAN

PCI EXPRESSSERIAL ATA

USB I/O

PLL CLKGEN I/O

VDDCR_1 1 VDDCR_1 1 VDDCR_1 1 VDDCR_1 1 VDDCR_1 1 VDDCR_1 1 VDDCR_1 1

CORE S03.3V_S5 I/O

VDDCR_1 1 VDDCR_1 1

VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK VDDAN_1 1_CLK

VDDRF_G BE_S

VDDIO_33_ GBE_S

VDDCR_1 1_GBE_S VDDCR_1 1_GBE_S

VDDIO_GBE _S VDDIO_GBE _S

VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S VDDIO_33_ S

VDDCR_1 1_S VDDCR_1 1_S

VDDIO_AZ_ S

CORE S5

VDDCR_1 1_USB_S VDDCR_1 1_USB_S

VDDPL_3 3_SYS

VDDPL_1 1_SYS_S

VDDPL_3 3_USB_S

VDDAN_3 3_HWM_S

VDDXL_3 3_S

N13 R15 N17 U13 U17 V12 V18 W12 W18

K28 K29 J28 K26 J21 J20 K21 J22

V1

M10

L7 L9

M6 P8

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

M8

A11 B11

M21

L22

F19

D6

L20

510mA

SCD1U10V2KX-4GP

TBD mA

SCD1U10V2KX-4GP

GBE PHY not used

32mA

113mA

TBDmA

R2303 0R2J-2-GPR2303 0R2J-2-GP

+3.3VALW_VDDIO_AZ

197mA

3.3V_RUN_VDDPL

1.1V_ALW_VDDPL

3.3V_ALW_VDDXL

C2304

12

C2315

12

1 2

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

12

SCD1U10V2KX-4GP

12

DY

C2309

C2308

12

SC1U6D3V2KX-GP

C2317

C2316

12

+3.3V_ALW

C2329

SC2D2U6D3V3KX-GP

C2329

SC2D2U6D3V3KX-GP

12

SCD1U10V2KX-4GP

C2334

12

17mA

+1.1V_RUN

SC10U10V5KX-2GP

SC1U6D3V2KX-GP

12

SC1U6D3V2KX-GP

12

DY

SC2D2U6D3V3KX-GP

12

SC1U6D3V2KX-GP

12

SCD1U10V2KX-4GP

12

C2311

C2310

12

+1.1V_RUN+1.1V_RUN_SB_CLKGEN

1 2

SC22U6D3V5MX-2GP

TC2302

C2318

+3.3V_ALW

SC2D2U6D3V3KX-GP

C2323

+1.1V_ALW

C2327

SC1U6D3V2KX-GP

SC10U10V5KX-2GP

C2335

SCD1U10V2KX-4GP

C2347

12

DY

C2324

12

C2328

12

C2336

12

+3.3V_ALW

SC2D2U6D3V3KX-GP

12

1 2

C2348

R2304

0R3J-0-U-GP

+1.1V_ALW+1.1V_ALW_VDDR_USB

L2306

BLM15AG221SS1D-GP

220 ohm 300mA

AB16 AC14 AE12 AE14

AF9 AF11 AF13 AF16

AG8

AH7 AH11 AH13 AH16

AJ7 AJ11 AJ13 AJ16

B10

K11

D10

D12

D14

D17

F12

F14

F16

G11

F18

H12

H14

H16

H18

K12

K18

H19

M19

P21

P20

M22 M24 M26

P22

P24

P26

T20

T22

T24

V20

Y16

A9

B9

E9 F9

C9

D9

J11 J19

K14 K16

Y4

D8

J23

VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A VSSIO_SAT A

VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB VSSIO_USB

EFUSE

VSSAN_H WM

VSSXL

VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K

SB820M-1-GP

Part 5 of 5

GROUND

VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K VSSIO_PCIECL K

VSSPL_S YS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8

M20

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

131mA

SCD1U10V2KX-4GP

SC22U6D3V5MX-2GP

WOL supported: Tied +3.3V_ALW not supported: Tied +3.3V_RUN

A A

TBDmA

3.3V_ALW_VDDXL

SCD1U10V2KX-4GP

DY

1 2

SC2D2U6D3V3KX-GP

C2342

C2341

12

5

+3.3V_ALW +3.3V_ALW

L2308

BLM15AG221SS1D-GP

220 ohm 300mA

WOL supported: Tied +1.1V_ALW not supported: Tied +1.1V_RUN

62mA 47mA

+1.1V_ALW +3.3V_RUN

L2312

1.1V_ALW_VDDPL 3.3V_RUN_VDDPL

SC2D2U6D3V3KX-GP

L2312

1 2

C2349

BLM15AG221SS1D-GP

12

220 ohm 300mA 220 ohm 300mA

4

SC2D2U6D3V3KX-GP

C2350

BLM15AG221SS1D-GP

12

L2313

1 2

5mA

3

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

12

DY

C2346

C2345

12

DY

2

Title

SB820M_POWER&GND_(4/5)

Size Document Number Rev

Custom

Date: Sheet of

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

23 89Friday, May 07, 2010

1

X01

5

SSID = S.B

4

3

2

1

REQUIRED STRAPS

D D

PCI_CLK120 PCI_CLK220 PCI_CLK320,70

PCLK_FW H20

C C

PCLK_KB C20,37 LPCCLK120

SB_GPO2 002 1 SB_GPO1 992 1

ACZ_SDA TAOUT_R2 1

+3.3V_RU N +3.3V_ ALW

R240110KR2J-3-GPDYR240110KR2J-3-GP

R240210KR2J-3-GPDYR240210KR2J-3-GP

DY

R240410KR2J-3-GP R240410KR2J-3-GP12R240310KR2J-3-GPDYR240310KR2J-3-GP

12

DY

R241910KR2J-3-GPDYR241910KR2J-3-GP

R241810KR2J-3-GP R241810KR2J-3-GP

R241710KR2J-3-GP R241710KR2J-3-GP

12

DY

12

R241610KR2J-3-GPDYR241610KR2J-3-GP

12

DY

R240610KR2J-3-GPDYR240610KR2J-3-GP

12

R242110KR2J-3-GP R242110KR2J-3-GP

12

1008

12

DY

12

R24082K2R2F-GP R24082K2R2F-GP

R24072K2R2F-GPDYR24072K2R2F-GP

12

DY

R242410KR2J-3-GP R242410KR2J-3-GP

R24222K2R2F-GP R24222K2R2F-GP

R24232K2R2F-GPDYR24232K2R2F-GP

12

R240510KR2J-3-GPDYR240510KR2J-3-GP

12

DY

R242010KR2J-3-GP R242010KR2J-3-GP

12

R240910KR2J-3-GPDYR240910KR2J-3-GP

DY

DEBUG STRAPS

PCI_AD23 2 0 VDDR_SE L 20,51 PCI_AD25 2 0 PCI_AD26 2 0 PCI_AD27 2 0

DY

R24112K2R2J-2-GPDYR24112K2R2J-2-GP

R24122K2R2J-2-GPDYR24122K2R2J-2-GP

12

DY

R24152K2R2J-2-GPDYR24152K2R2J-2-GP

R24142K2R2J-2-GPDYR24142K2R2J-2-GP

R24132K2R2J-2-GPDYR24132K2R2J-2-GP

12

DY

B B

REQUIRED SYSTEM STRAPS

PCI_CLK2

WatchDOG (NB_PWRGD) ENABLED

WatchDog (NB_PWRGD) DISABLED

DEFAULT

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

(PCI_CLK4)

non_Fusion CLOCK mode

DEFAULT

Fusion CLOCK mode

PULL HIGH

PULL LOW

AZ_SDOUT#

LOW POWER MODE

PERFORMANCE MODE

DEFAULT

PCI_CLK1

Allow PCIE GEN2

DEFAULT

Force PCIE GEN1

USE this pin to determine INT/EXT CLK

PCLK_KBCPCLK_FWH

(LPCCLK0)

ENABLE EC

DISABLE EC

DEFAULT

LPCCLK1

DEFAULT

CLKGEN ENABLED

(Use Internal)

CLKGEN DISABLED

(Use External)

SB_GPO200 , SB_GPO199

ROM TYPE:

H, H = Reserved

H, L = SPI ROM

L, H = LPC ROM

L, L = FWH ROM

DEFAULT

PULL HIGH

PULL LOW

USE PCI PLL

BYPASS PCI PLL

PCI_AD26PCI_AD27

Disable ILA AUTORUN

Enable ILA AUTORUN

PCI_AD25 PCI_AD23

USE FC PLL

PCI_AD24

USE DEFAULT PCIE STRAPS

Disable PCI MEM BOOT

(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)

BYPASS FC PLL

USE EEPROM PCIE STRAPS

Enable PCI MEM BOOT

Note: SB820 has 15K internal PU FOR PCI_AD[27:23]

Not Applicable to SB820M but provision for pull-down is required.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ize Document Nu mber Rev

Size Document N umber Rev

S

Date: Sheet of

SB820M_STRAPPING_(5/5)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Arsenal DJ1 Discrete

24 89Friday, May 07, 2010

1

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)

Size Document N umber Rev

Date: Sheet of

CPU (VCC_CORE)

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

25 89Friday, May 07, 2010

1

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

Size Document N umber Rev

Date: Sheet of

CPU (VCC_GFXCORE)

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

26 89Friday, May 07, 2010

1

X01

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec .1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Arsenal DJ1 Discrete

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

1

27 89Friday, May 07, 2010

X01

Dell N4010 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual