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MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
• TTL Compatible Outputs
• On–Chip Oscillator
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock
• Output Latches
• Master Reset
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PDIP–16
P SUFFIX
CASE 648
SOIC–16
DW SUFFIX
CASE 751G
MARKING
DIAGRAMS
MC14553BCP
AWLYYWW
1
16
14553B
AWLYYWW
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
DD
Vin, V
I
in
I
out
P
T
T
stg
T
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range
out
Input Current
Output Current
Power Dissipation,
D
Ambient Temperature Range –55 to +125 °C
A
Storage Temperature Range –65 to +150 °C
Lead Temperature
L
SS
or VDD). Unused outputs must be left open.
SS
Parameter Value Unit
(DC or Transient)
(DC or Transient) per Pin
(DC or Transient) per Pin
per Package (Note 2.)
(8–Second Soldering)
(Vin or V
) VDD.
out
) (Note 1.)
SS
–0.5 to VDD + 0.5 V
±10 mA
+20 mA
500 mW
260 °C
and V
in
should be constrained
out
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device Package Shipping
MC14553BCP PDIP–16 25/Rail
MC14553BDW SOIC–16 47/Rail
Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 5
1 Publication Order Number:
MC14553B/D
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MC14553B
43
CIA CIB
12
10
13
CLOCK
LE
11
DIS
MR
V
= PIN 16
DD
V
SS
Q0
Q1
Q2
Q3
O.F.
DS
DS
DS
= PIN 8
9
7
6
5
14
1
2
1
2
3
15
Figure 1. Block Diagram
TRUTH TABLE
Inputs
Master
Reset
0 0 0 No Change
0 0 0 Advance
0 X 1 X No Change
0 1 0 Advance
0 1 0 No Change
0 0 X X No Change
0 X X Latched
0 X X 1 Latched
1 X X 0 Q0 = Q1 = Q2 = Q3 = 0
X = Don’t Care
Clock Disable LE
Outputs
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MC14553B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
– 55C 25C 125C
Typ
(Note 3.)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 0.36
– 0.9
– 3.5
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
4.0
8.0
20
0.010
0.020
0.030
Max Min Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
DD
DD
DD
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
–0.14
–0.35
–1.1
– 0.36
– 0.9
– 2.4
0.28
0.65
1.20
1.6
3.5
10
—
—
—
0.05
0.05
0.05
Characteristic Symbol
Output Voltage “0” Level
V
= VDD or 0
in
“1” Level
V
= 0 or V
in
DD
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
O
= 9.0 or 1.0 Vdc)
(V
O
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
(V
= 0.5 or 4.5 Vdc)
O
= 1.0 or 9.0 Vdc)
(V
O
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 4.6 Vdc) Source —
OH
= 9.5 Vdc) Pin 3
(V
OH
(V
= 13.5 Vdc)
OH
(VOH = 4.6 Vdc) Source —
(V
= 9.5 Vdc) Other
OH
(V
= 13.5 Vdc) Outputs
OH
(VOL = 0.4 Vdc) Sink —
(V
= 0.5 Vdc) Pin 3
OL
= 1.5 Vdc)
(V
OL
(VOL = 0.4 Vdc) Sink — Other
(V
= 0.5 Vdc) Outputs
OL
= 1.5 Vdc)
(V
OL
Input Current I
Input Capacitance
(V
= 0)
in
Quiescent Current
(Per Package)
MR = V
DD
Total Supply Current
(Note 4., 5.)
(Dynamic plus Quiescent,
Per Package)
= 50 pF on all outputs, all
(C
L
V
DD
Vdc
V
OL
5.0
10
15
V
OH
5.0
10
15
V
IL
5.0
10
15
V
IH
5.0
10
15
I
OH
5.0
10
15
5.0
10
15
I
OL
5.0
10
15
5.0
10
15
in
C
in
I
DD
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
— — — — 5.0 7.5 — — pF
5.0
10
15
I
T
5.0
10
15
Min Max Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.25
– 0.62
– 1.8
– 0.64
– 1.6
– 4.2
0.5
1.1
1.8
3.0
6.0
18
—
—
—
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
– 0.51
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.2
– 0.5
– 1.5
– 1.3
– 3.4
0.4
0.9
1.5
2.5
5.0
15
—
—
—
IT = (0.35 µA/kHz) f + I
IT = (0.85 µA/kHz) f + I
IT = (1.50 µA/kHz) f + I
buffers switching)
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25C.
5. To calculate total supply current at loads other than 50 pF:
I
) = IT(50 pF) + (CL – 50) Vfk
T(CL
where: I
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
T
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
300
600
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
mAdc
mAdc
µAdc
µAdc
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MC14553B
SWITCHING CHARACTERISTICS (Note 6.) (C
Characteristic Figure Symbol V
Output Rise and Fall Time
t
, t
TLH
t
TLH
t
TLH
Clock to BCD Out 2a t
Clock to Overflow 2a t
Reset to BCD Out 2b t
Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time
Removal Time
Latch Enable to Clock
Clock Pulse Width 2a t
Reset Pulse Width 2b t
Reset Removal Time — t
Input Clock Frequency 2a f
Input Clock Rise Time 2b t
= (1.5 ns/pF) CL + 25 ns
THL
, t
= (0.75 ns/pF) CL + 12.5 ns
THL
, t
= (0.55 ns/pF) CL + 9.5 ns
THL
= 50 pF, TA = 25C)
L
2a t
2b t
2b t
TLH
t
THL
PLH
t
PHL
PHL
PHL
su
rem
WH(cl)
WH(R)
rem
cl
TLH
,
,
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
DD
Min Typ
—
(Note 7.)
100
—
—
—
—
—
—
—
—
—
—
—
600
400
200
– 80
– 10
0
550
200
900
500
200
600
400
200
900
500
300
300
200
100
– 200
– 70
– 50
275
100
150
1200
600
450
– 80
0
20
—
—
—
600
300
225
– 180
– 50
– 30
1.5
5.0
7.0
No
Limit
50
40
75
Max Unit
200
100
80
1800
1000
400
1200
800
400
1800
1000
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.9
2.5
3.5
15
Disable, MR, Latch Enable
Rise and Fall Times
Scan Oscillator Frequency
(C1 measured in µF)
— t
1 f
TLH
t
THL
osc
,
5.0
10
15
5.0
10
15
—
—
—
—
—
—
—
—
—
1.5/C1
4.2/C1
7.0/C1
15
5.0
4.0
—
—
—
6. The formulas given are for the typical characteristics only at 25C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
µs
Hz
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