Dell Latitude E6520 Schematics
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
PCB NO :
DAZ NO :
BOM P/N :
LA-6561P (DA80000JO10)
DAZ0FI00100
43193131L01,46193131L03.
MODEL NAME :
PAL61
www.qdzbwx.com
GPIOMAP:E3MasterGPIOMap10102010.xlsx
E3 MACALLAN 15.6" SG
rPGA Sandy Bridge +
FCBGA PCH Cougar Point-M
2 2
2011-01-12
REV : 1.0(A00)
@ : Nopop Component
CONN@:ConnectorComponent
3 3
MBType
TPMEN/TCMDIS
TPMDIS/TCMEN
TPMDIS/TCMDIS 2@
MB PCB
4 4
MB PCB
Part Number Description
Part Number Description
PCB 0FI LA-6561P REV0 M/B DSC
PCB 0FI LA-6561P REV0 M/B DSC
DA80000I700
DA80000I700
BOMP/N
43193131L01 (R1)
43193131L02 (R1)
43193131L03 (R1)
1@
2@
3@
4@
3@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
1 77Thursday, January 13, 2011
1 77Thursday, January 13, 2011
1 77Thursday, January 13, 2011
E
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B
B
of
of
of
A
B
C
D
E
Block Diagram
LVDS LCD
page24
1 1
2 2
3 3
4 4
HDMI
CONN
DOCKING
PORT
EXPRESS
Stick
page25
page39
USB 8,9
SATA 5
DOCK LAN
Card
page38 page37 page36page37 page37
USB 10
CPU XDP Port
PCH XDP Port
Thermal
EMC4022
WiFi ON/OFF
Compal confidential Model: PAL61
LVDS SW
PI3LVD400ZFEX
page23
DAI
HDMIRepeater
PS121
page25
DP
DP
VGA
CRT CONN Video Switch
page46
IO/B
1394
page36
HDMI
MAX14885EETL
2. IEEE1394+Card reader
OZ600RJ1LN
SDXC
page36
PCIE 5
1/2 Mini Card
Pink Panther
USB 6
Smart Card
page7
page14
PCIE 2
1/2 Mini Card
WLAN
USB 4
page34
RFID
page34
Full Mini Card
TDA8034HN
Fingerprint
CONN
SMSC SIO
ECE5028
page22
IO/B
LVDS
LVDS
page25
PCI Express BUS
PCIE 1PCIE 3
WWAN/UWB
USB 5
page34
page23
page40
GPU
page47~50
VGA
VGA
Option
China TPM1.2
SSX35BCB
USH
FP_USB
BC BUS
PEG
page36
TPM1.2
BCM5882
page35,36
USB 7
SMSC KBC
MEC5055
PCIE 6
LPC BUS
page41
Sandy Bridge
4MB (Socket G1)
rPGA /BGA CPU
988 pins
FDI
Lane x 8
INTEL
COUGAR POINT-M
BGA
page14~21
SPI
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
W25X64ZE
64M 4K sector
W25Q32BV
32M 4K sector
www.qdzbwx.com
page6~11
DMI
Lane x 4
page36
PCIE 4
Memory BUS
(DDR3)
USB
HD Audio I/F
SATA 1
E-Module
page29
USB 13
USB 11
USB 12
SATA 4
USB 1
USB 0
USB 2
USB 1
PCIE 7
SATA 0
HDD
Support Frequence 1066/1333
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
TS
page24
BT
page42
Camera
page24
page12,13
Trough eDP Cable
SATA Repeater
MAX4951BECTP
page45
IO/B
HDA Codec
92HD90B2
page30
MDC
page45page28
RJ11
Trough Cable
Trough eDP Cable
E-SATA
USB Port
USB Port
USB Port
USB Port
page45
page45
DOCK LAN
INT.Speaker
page30
HeadPhone &
MIC Jack
page46
DAI
To Docking side
Dig.
MIC
Intel Lewisville
82579LM
page32
LAN SWITCH
PI3L720
page32
Transformer
page33
IO/B
RJ45
page33
DELL CONFIDENTIAL/PROPRIETARY
DC/DC Interface
page43
Power On/Off
SW & LED
page31
A
page42 page42
B
KB CONNTP CONN
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
2 77Thursday, January 13, 2011
2 77Thursday, January 13, 2011
2 77Thursday, January 13, 2011
E
B
B
B
of
of
of
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1
D D
S4 (Suspend to DISK) / M1 ON ON OFF
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH HIGH ON ON ON OFF
LOW HIGH
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
HIGH
S4
STATE#
HIGH
SLP
M#
HIGH
HIGH
HIGHLOW
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
www.qdzbwx.com
OFF
OFF
OFF
PCH
PM TABLE
+15V_ALW
+5V_ALW
C C
State
S0
S3
S5 S4/AC
power
plane
+3.3V_ALW_PCH
+3.3V_RTC_LDO
ON
ON
+3.3V_SUS
+1.5V_MEM
ON ON
ON
OFF
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+0.75V_DDR_VTT
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN
OFFON
OFF
+3.3V_M
+1.05V_M
ON
ON
ON
+3.3V_M
+1.05V_M
(M-OFF)
ON
OFF
OFF
SATA
SATA 0
SATA 1
SATA 2
SATA 4
SATA 5
DESTINATION
HDD
ODD/ E3 Module Bay
NA
NASATA 3
ESATA
Dock
USH
USB PORT#
0
1
2
3
4
5
6
7
JUSB1 (Ext Right Side)
JESA1 (Ext Right Side)
IO Board- JUSB1 (Ext Left Side)
IO Board- JUSB2 (Ext Left Side)
WLAN
WWAN
JMINI3(Pink Panther)
USH->BIO
DOCKING8
9
DOCKING
10 Express card
11
12
Bluetooth
Camera
13 LCD Touch
0
1
DESTINATION
BIO
NA
S5 S4/AC don't exist
B B
A A
OFF
OFF
OFF
OFFOFF
DSC DP/HDMI Port
Port C
Port D
Port E
Connetion
Dock DP port 2
Dock DP port 1
MB HDMI Conn
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
DESTINATION
MINI CARD-1 WWAN
MINI CARD-2 WLAN
Express card
E3 Module Bay (USB3)
MINI CARD-3 (Pink Panther)
MMI
10/100/1G LOM
Lane 8 None
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
3 77Thursday, January 13, 2011
3 77Thursday, January 13, 2011
3 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
4
3
2
1
EN_INVPWR
FDC654P
Q21
+BL_PWR_SRC
HDDC_EN
MODC_EN
ADAPTER
D D
+PWR_SRC
BATTERY
PGPU_PWR_EN
1.05V_VTTPWRGD
ISL95870A
(PU15)
ISL95870AH
(PU13)
+GPU_CORE
+0.8V_VCC_SA
+5V_HDD
ALWON
SI3456BDVSI3456BDV
(Q30)(Q27)
+5V_MOD
+15V_ALW
CHARGER
C C
www.qdzbwx.com
ISL6236IRZA
(PU2)
+5V_ALW
RUN_ON
SI4164DY
+3.3V_ALW
(Q50)
+5V_RUN
MAX17411
(PU9)
RT8209BGQW
(PU3)
RT9026GFP
(PU5)
TPS51311
(PU4)
SN1003055
(PU7)
SN1003055
(PU6)
AUX_EN_WOWL
SI3456BDV
(Q38)
PCH_ALW_ON
SI3456BDV
(Q49)
SUS_ON
S13456
(Q54)
AUX_ON
SI3456
RUN_ON
NTMS4107
(Q34) (Q55)
M_ON
SI3456
(Q58)
B B
+VCC_GFXCORE
1.05V_0.8V_PWROK
+VCC_CORE
CPU1.5V_S3_GATE
DDR_ON
+1.5V_MEM +0.75V_DDR_VTT
RUN_ON
AO4728
(QC3)
SI3456
(Q59)
0.75V_VR_EN
RUN_ON
+1.8V_RUN
CPU_VTT_ON
+1.05V_RUN_VTT +1.05V_M
M_ON
RUN_ON
SI4164
(Q63)
+3.3V_WLAN
Pop option
+3.3V_ALW_PCH
+1.0V_LAN
+3.3V_M
Pop option
+3.3V_LAN+3.3V_SUS
+3.3V_RUN
+3.3V_M
+0.8V_VCCSA
A A
+1.5V_CPU_VDDQ
5
+1.5V_RUN
+1.05V_RUN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
1
B
B
4 77Thursday, January 13, 2011
4 77Thursday, January 13, 2011
4 77Thursday, January 13, 2011
B
of
of
of
5
SMBUS Address [0x9a]
H14
C9
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
2.2K
B4
A3
B5
A4
LAN_SMBCLK
LAN_SMBDATA
2.2K
+3.3V_ALW_PCH
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
C6
G8
E14M16
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
2.2K
2.2K
2.2K
2.2K
4
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
SMBUS Address [C8]
127
129
DOCKING
3
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
202
200
202
200
2
DIMMA
DIMMB
53
51
53
51
XDP1
XDP2
SMBUS Address [A0h]
A0h --> 1010 0000
SMBUS Address [A4h]
A4h --> 1010 0100
SMBUS Address [TBD]
SMBUS Address [TBD]
1
2.2K
G Sensor
+3.3V_RUN
SMBUS Address [TBD]
2.2K
14
13
30
32
WWAN
SMBUS Address [TBD]
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
10
9
7
6
M9
L9
7
8
Charger
BATTERY
CONN
Express card
SMBUS Address [0x16]
USH
SMBUS Address [0xa4]
SMBUS Address [TBD]
SMBUS Address [0x12]
31
32
8
9
3
E3 Module Bay
A/D,D/A
converter
www.qdzbwx.com
SMBUS Address [TBD]
SMBUS Address [0x30]
SMBUS Address
SMB_ADM1032: 0x98
SMB_DIAG_DUMP: 0x04
SMB_DIAG_DUMP2: 0x05
SMB_BLACKTOP: 0x60
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
5 77Thursday, January 13, 2011
5 77Thursday, January 13, 2011
5 77Thursday, January 13, 2011
1
B
B
B
of
of
of
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5055
2B
2B
2.2K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
2D
A A
2D
2.2K
2.2K
B49
B48
GPU_SMBCLK
GPU_SMBDAT
2A
2A
5
2.2K
5
4
3
2
JCPU1I
JCPU1I
1
www.qdzbwx.com
JCPU1A
JCPU1A
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
D D
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
C C
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
(1)EDP_COMPIOuse4miltracetoRC1
(2)EDP_ICOMPOuse12miltoRC1
B B
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG reverse check CFG2 routing
DP Compensation
12
RC1
RC1
24.9_0402_1%~D
24.9_0402_1%~D
J22
J21
H22
PEG_CRX_GTX_N15
K33
PEG_CRX_GTX_N14
M35
PEG_CRX_GTX_N13
L34
PEG_CRX_GTX_N12
J35
PEG_CRX_GTX_N11
J32
PEG_CRX_GTX_N10
H34
PEG_CRX_GTX_N9
H31
PEG_CRX_GTX_N8
G33
PEG_CRX_GTX_N7
G30
PEG_CRX_GTX_N6
F35
PEG_CRX_GTX_N5
E34
PEG_CRX_GTX_N4
E32
PEG_CRX_GTX_N3
D33
PEG_CRX_GTX_N2
D31
PEG_CRX_GTX_N1
B33
PEG_CRX_GTX_N0
C32
PEG_CRX_GTX_P15
J33
PEG_CRX_GTX_P14
L35
PEG_CRX_GTX_P13
K34
PEG_CRX_GTX_P12
H35
PEG_CRX_GTX_P11
H32
PEG_CRX_GTX_P10
G34
PEG_CRX_GTX_P9
G31
PEG_CRX_GTX_P8
F33
PEG_CRX_GTX_P7
F30
PEG_CRX_GTX_P6
E35
PEG_CRX_GTX_P5
E33
PEG_CRX_GTX_P4
F32
PEG_CRX_GTX_P3
D34
PEG_CRX_GTX_P2
E31
PEG_CRX_GTX_P1
C33
PEG_CRX_GTX_P0
B32
PEG_CTX_GRX_C_N15
M29
PEG_CTX_GRX_C_N14
M32
PEG_CTX_GRX_C_N13
M31
PEG_CTX_GRX_C_N12
L32
PEG_CTX_GRX_C_N11
L29
PEG_CTX_GRX_C_N10
K31
PEG_CTX_GRX_C_N9
K28
PEG_CTX_GRX_C_N8
J30
PEG_CTX_GRX_C_N7
J28
PEG_CTX_GRX_C_N6
H29
PEG_CTX_GRX_C_N5
G27
PEG_CTX_GRX_C_N4
E29
PEG_CTX_GRX_C_N3
F27
PEG_CTX_GRX_C_N2
D28
PEG_CTX_GRX_C_N1
F26
PEG_CTX_GRX_C_N0
E25
PEG_CTX_GRX_C_P15
M28
PEG_CTX_GRX_C_P14
M33
PEG_CTX_GRX_C_P13
M30
PEG_CTX_GRX_C_P12
L31
PEG_CTX_GRX_C_P11
L28
PEG_CTX_GRX_C_P10
K30
PEG_CTX_GRX_C_P9
K27
PEG_CTX_GRX_C_P8
J29
PEG_CTX_GRX_C_P7
J27
PEG_CTX_GRX_C_P6
H28
PEG_CTX_GRX_C_P5
G28
PEG_CTX_GRX_C_P4
E28
PEG_CTX_GRX_C_P3
F28
PEG_CTX_GRX_C_P2
D27
PEG_CTX_GRX_C_P1
E26
PEG_CTX_GRX_C_P0
D25
+1.05V_RUN_VTT+1.05V_RUN_VTT
PEG_COMP
PEG Compensation
12
RC2
RC2
24.9_0402_1%~D
24.9_0402_1%~D
PEG_CRX_GTX_N[0..15] <47>
PEG_CRX_GTX_P[0..15] <47>
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_P[0..15] <47>
PEG_CTX_GRX_N[0..15] <47>
CheckifsupportPCIEGEN2
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_N15
CC49 0.22U_0402_16V7K~DCC49 0.22U_0402_16V7K~D
12
CC33 0.22U_0402_16V7K~DCC33 0.22U_0402_16V7K~D
12
CC50 0.22U_0402_16V7K~DCC50 0.22U_0402_16V7K~D
12
CC34 0.22U_0402_16V7K~DCC34 0.22U_0402_16V7K~D
12
CC51 0.22U_0402_16V7K~DCC51 0.22U_0402_16V7K~D
12
CC35 0.22U_0402_16V7K~DCC35 0.22U_0402_16V7K~D
12
CC52 0.22U_0402_16V7K~DCC52 0.22U_0402_16V7K~D
12
CC36 0.22U_0402_16V7K~DCC36 0.22U_0402_16V7K~D
12
CC53 0.22U_0402_16V7K~DCC53 0.22U_0402_16V7K~D
12
CC37 0.22U_0402_16V7K~DCC37 0.22U_0402_16V7K~D
12
CC54 0.22U_0402_16V7K~DCC54 0.22U_0402_16V7K~D
12
CC38 0.22U_0402_16V7K~DCC38 0.22U_0402_16V7K~D
12
CC55 0.22U_0402_16V7K~DCC55 0.22U_0402_16V7K~D
12
CC39 0.22U_0402_16V7K~DCC39 0.22U_0402_16V7K~D
12
CC56 0.22U_0402_16V7K~DCC56 0.22U_0402_16V7K~D
12
CC40 0.22U_0402_16V7K~DCC40 0.22U_0402_16V7K~D
12
CC57 0.22U_0402_16V7K~DCC57 0.22U_0402_16V7K~D
1 2
CC41 0.22U_0402_16V7K~DCC41 0.22U_0402_16V7K~D
1 2
CC58 0.22U_0402_16V7K~DCC58 0.22U_0402_16V7K~D
1 2
CC42 0.22U_0402_16V7K~DCC42 0.22U_0402_16V7K~D
1 2
CC59 0.22U_0402_16V7K~DCC59 0.22U_0402_16V7K~D
1 2
CC43 0.22U_0402_16V7K~DCC43 0.22U_0402_16V7K~D
1 2
CC60 0.22U_0402_16V7K~DCC60 0.22U_0402_16V7K~D
1 2
CC44 0.22U_0402_16V7K~DCC44 0.22U_0402_16V7K~D
1 2
CC61 0.22U_0402_16V7K~DCC61 0.22U_0402_16V7K~D
1 2
CC45 0.22U_0402_16V7K~DCC45 0.22U_0402_16V7K~D
1 2
CC62 0.22U_0402_16V7K~DCC62 0.22U_0402_16V7K~D
1 2
CC46 0.22U_0402_16V7K~DCC46 0.22U_0402_16V7K~D
1 2
CC63 0.22U_0402_16V7K~DCC63 0.22U_0402_16V7K~D
1 2
CC47 0.22U_0402_16V7K~DCC47 0.22U_0402_16V7K~D
1 2
CC64 0.22U_0402_16V7K~DCC64 0.22U_0402_16V7K~D
1 2
CC48 0.22U_0402_16V7K~DCC48 0.22U_0402_16V7K~D
1 2
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
PEG_CTX_GRX_P8
PEG_CTX_GRX_N8
PEG_CTX_GRX_P9
PEG_CTX_GRX_N9
PEG_CTX_GRX_P10
PEG_CTX_GRX_N10
PEG_CTX_GRX_P11
PEG_CTX_GRX_N11
PEG_CTX_GRX_P12
PEG_CTX_GRX_N12
PEG_CTX_GRX_P13
PEG_CTX_GRX_N13
PEG_CTX_GRX_P14
PEG_CTX_GRX_N14
PEG_CTX_GRX_P15
PEG_CTX_GRX_N15
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
EDP_COMP
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
A A
5
PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
4
PEG_COMP
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
6 77Thursday, January 13, 2011
6 77Thursday, January 13, 2011
6 77Thursday, January 13, 2011
1
of
of
of
B
B
B
5
Follow DG Rev0.71 SM_DRAMPWROK topology
+3.3V_ALW_PCH
UC2
UC2
RUNPWROK<40,41>
+3.3V_ALW_PCH
D D
+1.05V_RUN_VTT
C C
H_PROCHOT#<41,59>
1 2
RC18 200_0402_5%~DRC18 200_0402_5%~D
PM_DRAM_PWRGD<16>
1 2
RC126 56_0402_5%~D@RC126 56_0402_5%~D@
1 2
RC128 49.9_0402_1%~D@ RC128 49.9_0402_1%~D@
1 2
RC44 62_0402_5%~DRC44 62_0402_5%~D
H_THERMTRIP#<22>
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
CPU_DETECT#<40>
@
@
1
2
RUN_ON_CPU1.5VS3#<11,43>
PECI_EC<41>
1 2
RC57 56_0402_5%~DRC57 56_0402_5%~D
1 2
RC129
RC129
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC156
CC156
1 2
5
P
B
A
RUNPWROK_AND PM_DRAM_PWRGD_CPU
4
O
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#_R
0_0402_5%~D
0_0402_5%~D
+1.5V_CPU_VDDQ
RC64
RC64
39_0402_5%~D
39_0402_5%~D
1 2
13
D
D
QC1
QC1
2
G
G
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
S
S
www.qdzbwx.com
JCPU1B
CONN@
JCPU1B
CONN@
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
place RC129 near CPU
H_PM_SYNC<16>
B B
H_CPUPWRGD<18>
1 2
@
@
RC25 0_0402_5%~D
RC25 0_0402_5%~D
Buffered reset to CPU
A A
PCH_PLTRST#<14,17>
5
H_PM_SYNC
VCCPWRGOOD_0_R
PM_DRAM_PWRGD_CPU
PCH_PLTRST#_R
+3.3V_RUN
UC1
UC1
1
2
5
NC
VCC
A
4
GND3Y
SN74LVC1G07DCKR_SC70-5~D
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
AM34
AP33
AR33
+1.05V_RUN_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CC140
CC140
2
PCH_PLTRST#_BUF
PM_SYNC
UNCOREPWRGOOD
V8
SM_DRAMPWROK
RESET#
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
RC4
75_0402_1%~D
RC4
75_0402_1%~D
12
1 2
RC10 43_0402_5%~DRC10 43_0402_5%~D
4
12
RC12
RC12
200_0402_5%~D
200_0402_5%~D
1 2
RC28 130_0402_5%~DRC28 130_0402_5%~D
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
PCH_PLTRST#_R
4
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
JTAG & BPM
JTAG & BPM
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
3
+3.3V_ALW_PCH
12
RC124
@RC124
@
1K_0402_5%~D
1K_0402_5%~D
SYS_PWROK_XDP
The resistor for HOOK2 should beplaced
such that the stub is very small on CFG0 net
H_CPUPWRGD
SIO_PWRBTN#_R<14,16>
CFG0
DDR_XDP_WAN_SMBDAT<12,13,14,15,28,37>
DDR_XDP_WAN_SMBCLK<12,13,14,15,28,37>
CPU_DMI
A28
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
CPU_DMI#
CPU_DPLL
CPU_DPLL#
RC13 0_0402_5%~D@RC13 0_0402_5%~D@
RC15
@ RC15
@
RC100
RC100
@
@
RC101
RC101
DDR3_DRAMRST#_CPU
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
XDP_DBRESET#_R
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
For ESD concern, please put near CPU
VCCPWRGOOD_0_R
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
SYS_PWROK<16,40>
RC125 0_0402_5%~DRC125 0_0402_5%~D
RC127 0_0402_5%~DRC127 0_0402_5%~D
1 2
1 2
0_0402_5%~D
0_0402_5%~D
1 2
0_0402_5%~D@
0_0402_5%~D@
1 2
0_0402_5%~D
0_0402_5%~D
Max 500mils
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
RC130
RC130
10K_0402_5%~D
10K_0402_5%~D
3
12
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
0_0402_5%~D@
RC26
@ RC26
@
RC30 0_0402_5%~D
RC30 0_0402_5%~D
@
@
RC31 0_0402_5%~D@RC31 0_0402_5%~D@
RC33
@RC33
@
RC34
RC34
RC36
RC36
RC37
RC37
RC38 0_0402_5%~D@RC38 0_0402_5%~D@
RC39 0_0402_5%~D@RC39 0_0402_5%~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC5 1K_0402_5%~DRC5 1K_0402_5%~D
RC6 0_0402_5%~D@ RC6 0_0402_5%~D@
RC7 1K_0402_5%~DRC7 1K_0402_5%~D
RC9 0_0402_5%~D@ RC9 0_0402_5%~D@
1 2
1 2
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
CLK_CPU_DPLL <15>
CLK_CPU_DPLL# <15>
RC50
RC50
4.99K_0402_1%~D
4.99K_0402_1%~D
DDR_HVREF_RST_PCH<15>
DDR_HVREF_RST_GATE<41>
XDP_DBRESET#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3XDP_OBS3_R
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
+1.05V_RUN_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
CC65
CC65
2
2
Place near JXDP1
CFG10<9>
CFG11<9>
1 2
1 2
1 2
1 2
12
SM_RCOMP2
SM_RCOMP1
SM_RCOMP0
DDR_XDP_WAN_SMBDAT_R1
DDR_XDP_WAN_SMBCLK_R1
1 2
RC48 0_0402_5%~D@RC48 0_0402_5%~D@
XDP_DBRESET# <14,16>
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC66
CC66
XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
CFG10
CFG11
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP
SYS_PWROK_XDP
XDP_TCLK
D
S
D
S
13
QC2
QC2
G
G
BSS138W-7-F_SOT323-3~D
BSS138W-7-F_SOT323-3~D
2
1
CC177
CC177
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2
@ RC46
@
RC47 0_0402_5%~D@RC47 0_0402_5%~D@
XDP_TDO_R XDP_TDO
RC42
RC42
140_0402_1%~D
140_0402_1%~D
+1.05V_RUN_VTT +1.05V_RUN_VTT
DDR3_DRAMRST# <12>
DDR_HVREF_RST
1 2
RC46
0_0402_5%~D
0_0402_5%~D
1 2
1 2
RC23 0_0402_5%~D@RC23 0_0402_5%~D@
1 2
RC24
RC24
12
RC43
RC43
12
12
RC45
RC45
200_0402_1%~D
200_0402_1%~D
25.5_0402_1%~D
25.5_0402_1%~D
2
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
CONN@
CONN@
CLK_XDP
CLK_XDP#
XDP_TDIXDP_TDI_R
0_0402_5%~D@
0_0402_5%~D@
1
JXDP1
JXDP1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
XDP_RST#_R
1 2
RH107 0_0402_5%~D@RH107 0_0402_5%~D@
1 2
@
@
RH106 0_0402_5%~D
RH106 0_0402_5%~D
CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>
2
GND1
4
OBSFN_C0
6
OBSFN_C1
8
GND3
10
12
14
GND5
16
18
20
GND7
22
OBSFN_D0
24
OBSFN_D1
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
RC8 1K_0402_5%~DRC8 1K_0402_5%~D
12
1 2
RH109 0_0402_5%~D@RH109 0_0402_5%~D@
1 2
RH108 0_0402_5%~D@RH108 0_0402_5%~D@
CFG16
CFG17
CFG0
CFG1
CFG2
CFG3
CFG8
CFG9
CFG4
CFG5
CFG6
CFG7
CLK_XDP
CLK_XDP#
XDP_RST#_RXDP_HOOK2
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
CFG16 <9>
CFG17 <9>
CFG0 <9>
CFG1 <9>
CFG2 <9>
CFG3 <9>
CFG8 <9>
CFG9 <9>
CFG4 <9>
CFG5 <9>
CFG6 <9>
CFG7 <9>
PLTRST_XDP# <17>
CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>
PU/PD for JTAG signals
XDP_DBRESET#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO
XDP_TCLK
XDP_TRST#
RC19 1K_0402_5%~DRC19 1K_0402_5%~D
RC27 51_0402_1%~DRC27 51_0402_1%~D
RC29 51_0402_1%~DRC29 51_0402_1%~D
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
RC35 51_0402_1%~DRC35 51_0402_1%~D
RC40
RC40
RC41
RC41
12
12
12
12
12
12
51_0402_1%~D
51_0402_1%~D
12
51_0402_1%~D
51_0402_1%~D
+1.05V_RUN_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
7 77Thursday, January 13, 2011
7 77Thursday, January 13, 2011
7 77Thursday, January 13, 2011
1
+3.3V_RUN
of
of
B
B
B
5
JCPU1C
JCPU1C
D D
C C
B B
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
F10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AE8
AD9
AF9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
4
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12>
3
DDR_B_D[0..63]<13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
2
JCPU1D
JCPU1D
M_CLK_DDR2
AE2
SB_CLK[0]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
AP3
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_CLK_DDR#2
DDR_CKE2_DIMMB
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
1
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_B_MA[0..15] <13>
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
A A
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
8 77Thursday, January 13, 2011
8 77Thursday, January 13, 2011
8 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
4
3
2
1
CFG Straps for Processor
www.qdzbwx.com
D D
CFG0<7>
CFG1<7>
CFG2<7>
CFG3<7>
CFG4<7>
CFG5<7>
CFG6<7>
CFG7<7>
CFG8<7>
CFG9<7>
CFG10<7>
+VCC_GFXCORE
1 2
RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
+VCC_CORE
1 2
C C
B B
RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
RC96 1K_0402_5%~D@RC96 1K_0402_5%~D@
RC97 1K_0402_5%~D@RC97 1K_0402_5%~D@
1 2
1 2
1 2
1 2
RSVD1
RSVD3
RSVD2
RSVD4
+DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
CFG11<7>
T9 PAD~D@T9 PAD~D@
T10 PAD~D@T10 PAD~D@
T12 PAD~D@T12 PAD~D@
T14 PAD~D@T14 PAD~D@
CFG16<7>
CFG17<7>
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD1
RSVD2
RSVD3
RSVD4
T22PAD~D @T22PAD~D @
+DIMM0_1_CA_CPU
T28PAD~D @T28PAD~D @
T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~D @
T31PAD~D @T31PAD~D @
T33PAD~D @T33PAD~D @
T35PAD~D @T35PAD~D @
T36PAD~D @T36PAD~D @
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T40PAD~D @T40PAD~D @
T41PAD~D @T41PAD~D @
T42PAD~D @T42PAD~D @
T43PAD~D @T43PAD~D @
T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @
T46PAD~D @T46PAD~D @
T47PAD~D @T47PAD~D @
T48PAD~D @T48PAD~D @
T155PAD~D @T155PAD~D @
T52PAD~D @T52PAD~D @
JCPU1E
JCPU1E
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
RESERVED
RESERVED
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
AT2
AT1
AR1
B1
T1 PAD~D@T1 PAD~D@
T2 PAD~D@T2 PAD~D@
T3 PAD~D@T3 PAD~D@
T4 PAD~D@T4 PAD~D@
T5 PAD~D@T5 PAD~D@
T6 PAD~D@T6 PAD~D@
T7 PAD~D@T7 PAD~D@
T8 PAD~D@T8 PAD~D@
T11 PAD~D@T11 PAD~D@
T13 PAD~D@T13 PAD~D@
T15 PAD~D@T15 PAD~D@
T16 PAD~D@T16 PAD~D@
T17 PAD~D@T17 PAD~D@
T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@
T20 PAD~D@T20 PAD~D@
T21 PAD~D@T21 PAD~D@
T23 PAD~D@T23 PAD~D@
T24 PAD~D@T24 PAD~D@
T25 PAD~D@T25 PAD~D@
T26 PAD~D@T26 PAD~D@
T27 PAD~D@T27 PAD~D@
T32 PAD~D@T32 PAD~D@
T34 PAD~D@T34 PAD~D@
T39 PAD~D@T39 PAD~D@
CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>
T49 PAD~D@T49 PAD~D@
T50 PAD~D@T50 PAD~D@
T51 PAD~D@T51 PAD~D@
T53 PAD~D@T53 PAD~D@
PEG Static Lane Reversal - CFG2 is for the 16x
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
CFG2
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1K_0402_5%~D
1K_0402_5%~D
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG4
CFG6
CFG5
@ RC54
@
RC54
12
RC51
RC51
1K_0402_5%~D
1K_0402_5%~D
12
12
RC52
@RC52
@
1K_0402_5%~D
1K_0402_5%~D
12
RC53
1K_0402_5%~D
1K_0402_5%~D
@RC53
@
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
CFG7
12
RC56
1K_0402_5%~D
1K_0402_5%~D
@RC56
@
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
A A
0: PEG Wait for BIOS for training
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
9 77Thursday, January 13, 2011
9 77Thursday, January 13, 2011
9 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
+VCC_CORE
1
CC76
CC76
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC88
CC88
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
2
1
2
1
2
1
2
1
+
+
CC131
CC131
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
CC113
CC113
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC118
CC118
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC123
CC123
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
@
@
CC128
CC128
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
+
+
CC129
CC129
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
1
+
CC133
@+CC133
@
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
1
CC75
CC75
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC71
CC71
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC111
CC111
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC116
CC116
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC121
CC121
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
@
@
CC126
CC126
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC67
+VCC_CORE
CC67
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC87
CC87
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC110
CC110
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC115
CC115
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC120
CC120
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC125
CC125
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
+VCC_CORE
D D
C C
B B
A A
1
2
1
2
1
@
@
+
+
CC130
CC130
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
1
+
+
CC134
CC134
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
CC68
CC68
10U_0805_4VAM~D
10U_0805_4VAM~D
CC72
CC72
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CC112
CC112
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC117
CC117
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC122
CC122
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
@
@
CC127
CC127
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
2
1
CC77
CC77
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
CC73
CC73
10U_0805_4VAM~D
10U_0805_4VAM~D
2
1
2
1
2
1
2
1
+
+
CC132
CC132
470U_D2T_2VM~D
470U_D2T_2VM~D
2 3
4
CC114
CC114
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC119
CC119
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC124
CC124
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
@
@
CC74
CC74
10U_0805_4VAM~D
10U_0805_4VAM~D
2
3
POWER
JCPU1F
JCPU1F
+VCC_CORE
53A 8.5A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VCCIO_SENSE
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VSSIO_SENSE
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCSENSE_R
VSSSENSE_R
VTT_SENSE_R
VSSIO_SENSE_R
2
22uFX12.
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC78
CC78
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC89
CC89
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
2
@
@
1
CC79
CC79
2
1
CC91
CC91
2
+1.05V_RUN_VTT
22U_0805_6.3VAM~D
1
CC80
CC80
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC92
CC92
2
@
@
1 2
RC61 43_0402_5%~DRC61 43_0402_5%~D
12
RC63
RC63
130_0402_1%~D
130_0402_1%~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC69
CC69
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC90
CC90
2
@
@
Note: Place the PU resistors close to CPU
RC61 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
VIDSCLK <59>
Place RC66,RC70 near CPU
1 2
RC67 0_0402_5%~D@RC67 0_0402_5%~D@
1 2
RC68 0_0402_5%~D@RC68 0_0402_5%~D@
RC132 0_0402_5%~D@ RC132 0_0402_5%~D@
RC133 0_0402_5%~D@ RC133 0_0402_5%~D@
1 2
1 2
VTT_SENSE <58>
VTT_GND <58>
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC81
CC81
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC93
CC93
@
@
VIDSOUT <59>
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC82
CC82
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC107
CC107
+
+
2
CAD Note: Place the PU
resistors close to CPU
RC63 close to CPU 300 - 1500mils
+VCC_CORE
12
12
1
CC83
CC83
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC108
CC108
+
+
2
RC66
RC66
100_0402_1%~D
100_0402_1%~D
VCCSENSE <59>
VSSSENSE <59>
RC70
RC70
100_0402_1%~D
100_0402_1%~D
1
2
1
2
1
+1.05V_RUN_VTT
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
CC84
CC84
CC85
CC85
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
CC109
CC109
+
+
@
@
+1.05V_RUN_VTT
12
RC60
RC60
75_0402_1%~D
75_0402_1%~D
Iccmax current changed for PDDG Rev0.7
Voltage Rail
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
2
CC86
CC86
CC70
CC70
2
VIDALERT_N <59>
CPU Power Rail Table
Voltage
0.65-1.3
1.05
0.0-1.1
1.8
1.5
0.65-0.9
+1.5V_MEM 1.5
Description
*
5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT
S0 Iccmax
Current (A)
53
8.5
26
3
5
6
12-16
*
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
10 77Thursday, January 13, 2011
10 77Thursday, January 13, 2011
10 77Thursday, January 13, 2011
1
B
B
B
of
of
of
Sandy Bridge_rPGA_Rev1p0
DELL CONFIDENTIAL/PROPRIETARY
5
4
3
2
1
+1.5V_CPU_VDDQ Source
+15V_ALW+3.3V_ALW2
12
RC74
RC74
100K_0402_5%~D
61
2
+VCC_GFXCORE
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC139
CC139
CC148
CC148
1
2
330U_D2_2.5VM_R6M~D
330U_D2_2.5VM_R6M~D
1
CC176
CC176
+
+
2
100K_0402_5%~D
RUN_ON_CPU1.5VS3#
QC4A
QC4A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
JCPU1G
3A
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
26A
5
POWER
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
4
D D
RUN_ON<38,40,43,56,64>
CPU1.5V_S3_GATE<41> RUN_ON_CPU1.5VS3# <7,43>
+VCC_GFXCORE
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC138
CC138
CC137
CC137
1
1
C C
B B
A A
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
2
1
+
+
2 3
+1.8V_RUN
1
2
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC151
CC151
CC141
CC141
1
1
2
2
470U_D2T_2VM~D
470U_D2T_2VM~D
1
@
@
CC159
CC159
+
+
2 3
1 2
RC77 0_0402_5%~D@RC77 0_0402_5%~D@
1 2
RC79 0_0402_5%~D@RC79 0_0402_5%~D@
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC144
CC144
CC145
CC145
1
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC153
CC153
CC152
CC152
1
2
470U_D2T_2VM~D
470U_D2T_2VM~D
CC158
CC158
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CC173
CC173
2
5
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CC147
CC147
CC146
CC146
1
1
2
1
2
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CC175
CC175
CC174
CC174
2
+1.5V_MEM +1.5V_CPU_VDDQ
12
RC72
RC72
100K_0402_5%~D
100K_0402_5%~D
RUN_ON_CPU1.5VS3
3
QC4B
QC4B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID1
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
FC_C22
QC3
QC3
AO4728L_SO8~D
AO4728L_SO8~D
8
7
6
5
4
1
CC136
CC136
4700P_0402_25V7K~D
4700P_0402_25V7K~D
2
AK35
AK34
AL1
+V_SM_VREF should
have 10 mil trace width
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
1
2
3
1 2
RC138 0_0402_5%~D@ RC138 0_0402_5%~D@
H_FC_C22
20K_0402_5%~D
20K_0402_5%~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
12
@
@
RC73
RC73
CC135
CC135
1
2
+V_DDR_REF
RUN_ON_CPU1.5VS3
VCC_AXG_SENSE <59>
VSS_AXG_SENSE <59>
+V_SM_VREF_CNT
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC161
CC161
CC162
CC162
2
2
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CC168
CC168
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC164
CC164
CC163
CC163
2
2
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC169
CC169
CC170
CC170
2
2
1 2
RC137 0_0402_5%~D@RC137 0_0402_5%~D@
VCCSA_VID_1 <62>
1
CC165
CC165
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
@CC171
@
1
CC171
2
12
QC5
QC5
NTR4503NT1G_SOT23-3~D
NTR4503NT1G_SOT23-3~D
1 2
RC134 0_0402_5%~D@RC134 0_0402_5%~D@
+1.5V_CPU_VDDQ
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
1
CC166
CC166
+
+
2
2
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
1
CC172
CC172
+
+
2
12
RC81
0_0402_5%~D
0_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
RC83
RC83
1
3
2
CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D
12
CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D
12
CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D
12
CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D
12
@PJP1
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
@PJP2
@
1 2
PAD-OPEN 4x4m
+VCC_SA
+GND_VCC_SA <62>
VCCSA_SENSE <62>
@RC81
@
PAD-OPEN 4x4m
CC167
CC167
PJP1
PJP2
+V_SM_VREF_CNT
12
RC78
RC78
100K_0402_5%~D
100K_0402_5%~D
2
+1.5V_MEM
JCPU1H
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0
CONN@
CONN@
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
11 77Thursday, January 13, 2011
11 77Thursday, January 13, 2011
11 77Thursday, January 13, 2011
1
of
of
B
B
B
5
+V_DDR_REF
+DIMM0_1_VREF_CPU
D D
C C
B B
A A
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
Layout Note:
Place near JDIMM1
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
CD4
CD4
CD3
CD3
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD7
CD7
CD8
CD8
CD9
CD9
1
1
2
2
Layout Note:
Place near JDIMM1.203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD17
CD17
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD18
CD18
CD6
CD6
CD5
CD5
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD10
CD10
CD11
CD11
1
2
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD19
CD19
2
2
All VREF traces should
have 10 mil trace width
Populate RD1 for Intel DDR3
VREFDQ multiple methods M1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
330U_SX_2VY~D
@CD13
@
CD51
CD51
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD20
CD20
1
CD13
CD14
CD14
1
+
+
2
2
4
1 2
RD1 0_0402_5%~D@RD1 0_0402_5%~D@
1 2
RD7 0_0402_5%~D@ RD7 0_0402_5%~D@
1
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
1 2
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
+3.3V_RUN
+DIMM0_1_VREF_DQ
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
CD1
CD1
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
CD21
CD21
2
3
JDIMM1
CONN@JDIMM1
CONN@
1
VREF_DQ
3
DDR_A_D0
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_A_D1
1
CD2
CD2
DDR_A_D2
2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
CD22
CD22
+0.75V_DDR_VTT
2
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013289-2~D
TYCO_2-2013289-2~D
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
VDD
VDD
VDD
VDD
CK1
CK1#
VDD
RAS#
VDD
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
2-3A to 1 DIMMs/channel
+1.5V_MEM+1.5V_MEM
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR3_DRAMRST#_R
DDR_A_D14
DDR_A_D15
DDR_A_D20DDR_A_D16
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.75V_DDR_VTT
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
M_ODT0 <8>
M_ODT1 <8>
2
JDIMM1 H=5.2
DDR3_DRAMRST#_R
DDR_CKE1_DIMMA <8>
+DIMM0_1_VREF_CA
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
DDR_XDP_WAN_SMBDAT <7,13,14,15,28,37>
DDR_XDP_WAN_SMBCLK <7,13,14,15,28,37>
CD15
CD15
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CD16
CD16
1
2
1 2
RD29 0_0402_5%~D@ RD29 0_0402_5%~D@
1 2
RD31 0_0402_5%~D@RD31 0_0402_5%~D@
+1.5V_MEM
12
RD27
RD27
1K_0402_1%~D
1K_0402_1%~D
1 2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
+V_DDR_REF
+DIMM0_1_CA_CPU
1
DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
12 77Thursday, January 13, 2011
12 77Thursday, January 13, 2011
12 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
All VREF traces should
have 10 mil trace width
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
D D
C C
B B
A A
DDR_B_MA[0..15]<8>
+1.5V_MEM
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CD25
CD25
CD26
CD26
2
2
+1.5V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD29
CD29
CD30
CD30
CD31
CD31
CD39
CD39
1
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD40
CD40
2
1
1
2
2
Layout Note:
Place near JDIMM2.203,204
+0.75V_DDR_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
2
CD32
CD32
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD27
CD27
CD41
CD41
CD28
CD28
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
CD34
CD34
CD33
CD33
1
1
2
1
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CD42
CD42
2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
Populate RD4 for Intel DDR3
VREFDQ multiple methods M1
330U_SX_2VY~D
330U_SX_2VY~D
@CD35
@
1
CD35
CD36
CD36
+
+
2
4
+DIMM0_1_VREF_DQ
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
+3.3V_RUN
RD5 10K_0402_5%~DRD5 10K_0402_5%~D
+3.3V_RUN
12
CD23
CD23
DDR_CKE2_DIMMB<8>
DDR_CS3_DIMMB#<8>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
12
CD24
CD24
10K_0402_5%~D
10K_0402_5%~D
RD6
RD6
3
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
+0.75V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
CD43
CD43
2
2
+1.5V_MEM
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
CD44
CD44
JDIMM2
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
TYCO_2-2013310-2~D
TYCO_2-2013310-2~D
CONN@JDIMM2
CONN@
2
2-3A to 1 DIMMs/channel
+1.5V_MEM
2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
VDD
VDD
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
A7
A6
A4
A2
A0
NC
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.75V_DDR_VTT
JDIMM2 H=9.2
DDR3_DRAMRST#_R <12>
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <8>
M_ODT3 <8>
+DIMM0_1_VREF_CA
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
1
CD37
CD37
2
DDR_XDP_WAN_SMBDAT <7,12,14,15,28,37>
DDR_XDP_WAN_SMBCLK <7,12,14,15,28,37>
1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CD38
CD38
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
13 77Thursday, January 13, 2011
13 77Thursday, January 13, 2011
13 77Thursday, January 13, 2011
1
B
B
B
of
of
5
CMOS settingCMOS_CLR1
Open
ME_CLR1
Shunt
Open
+RTC_CELL
D D
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
*
Low - Enable External VRs
C C
+3.3V_RUN
B B
A A
Clear CMOSShunt
Keep CMOS
TPM setting
Clear ME RTC Registers
Keep ME RTC Registers
12
RH38
RH38
330K_0402_5%~D
330K_0402_5%~D
PCH_INTVRMEN
12
RH39
@RH39
@
330K_0402_5%~D
330K_0402_5%~D
1
1
@
@
ME1 SHORT PADS~D
ME1 SHORT PADS~D
1 2
CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D
PCH_AZ_CODEC_SDOUT<30>
PCH_AZ_CODEC_SYNC<30>
PCH_AZ_CODEC_RST#<30>
@CH101
@
27P_0402_50V8J~D
27P_0402_50V8J~D
12
RH295
@RH295
@
8.2K_0402_5%~D
8.2K_0402_5%~D
PCH_SPI_DO
SPI_PCH_CS0#
SPI_PCH_DIN SPI_DIN64
SPI_WP#_SEL
SPI_WP#_SEL<40>
2
CH101
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
+3.3V_ALW_PCH
12
RH66
RH66
1K_0402_5%~D
1K_0402_5%~D
PCH_AZ_SYNC
12
RH282
@RH282
@
100K_0402_5%~D
100K_0402_5%~D
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
+RTC_CELL
2
1 2
RH29 33_0402_5%~DRH29 33_0402_5%~D
1 2
RH26 33_0402_5%~DRH26 33_0402_5%~D
1 2
RH27 33_0402_5%~DRH27 33_0402_5%~D
1 2
RH25 33_0402_5%~DRH25 33_0402_5%~D
1
+3.3V_ALW_PCH
2
12
@RH288
@
0_0603_5%~D
0_0603_5%~D
SPI_MOSI (PCH_SPI_DO)
High: Enable Intel Anti-Theft Technology
Left floating: Disable Intel Anti-Theft Technology
1 2
R935 47_0402_5%~DR935 47_0402_5%~D
1 2
R894 33_0402_5%~DR894 33_0402_5%~D
1 2
R898 0_0402_5%~D@R898 0_0402_5%~D@
5
1 2
RH22 20K_0402_5%~DRH22 20K_0402_5%~D
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
1
@
@
CMOS1 SHORT PADS~D
CMOS1 SHORT PADS~D
CH4
CH4
CMOS place near DIMM
PCH_AZ_SDOUT
PCH_AZ_SYNC_Q
PCH_AZ_RST#
PCH_AZ_BITCLK
RH288
+3.3V_ALW_PCH_JTAG
Γ
R890
R890
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_PCH_CS0#_R
1
2
2
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RH59 51_0402_1%~DRH59 51_0402_1%~D
RH44 200_0402_1%~DRH44 200_0402_1%~D
RH45 200_0402_1%~DRH45 200_0402_1%~D
RH43 200_0402_1%~DRH43 200_0402_1%~D
1 2
RH31 1M_0402_5%~DRH31 1M_0402_5%~D
PCH_PLTRST#_EC<17,35,37,38,40,41>
12
200 MIL SO8
64Mb Flash ROM
X76@ U52
X76@
1
/CS
2
DO
3
/WP
GND4DIO
W25Q64BVSSIG_SO8~D
W25Q64BVSSIG_SO8~D
PCH_AZ_MDC_SDOUT<45>PCH_AZ_CODEC_BITCLK<30>
PCH_AZ_SYNC_Q
U52
/HOLD
12
12
12
12
VCC
CLK
USB_OC0#_R<17>
USB_OC1#_R<17>
SIO_EXT_SMI#<17,41>
SLP_ME_CSW_DEV#<18,40>
USB_MCARD1_DET#<18,37>
EN_ESATA_RPTR#<18>
TEMP_ALERT#<18,40>
PCH_GPIO15<18>
SIO_EXT_SCI#_R<18>
PCH_RSMRST#_Q<16,41>
CH2
CH2
15P_0402_50V8J~D
15P_0402_50V8J~D
CH3
CH3
15P_0402_50V8J~D
15P_0402_50V8J~D
PCH_AZ_MDC_BITCLK<45>
PCH_AZ_MDC_SYNC<45>
PCH_AZ_MDC_RST#<45>
PCH_AZ_CODEC_SDIN0<30>
PCH_AZ_MDC_SDIN1<45>
ME_FWP<40>
PCH_PLTRST#_EC
+3.3V_SPI
8
7
SPI_CLK64
6
SPI_DO64
5
SPI_CLK64
4
USB_OC2#<17>
USB_OC3#<17>
USB_OC4#<17>
USB_OC5#<17>
USB_OC6#<17>
GPIO36<18>
GPIO37<18>
12
12
CH100
@CH100
@
27P_0402_50V8J~D
27P_0402_50V8J~D
SPKR<30>
+3.3V_ALW_PCH
12
RH48
RH48
@
@
100_0402_1%~D
100_0402_1%~D
1 2
R933 0_0402_5%~D@R933 0_0402_5%~D@
S
S
G
G
2
C746
C746
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
12
R891
R891
3.3K_0402_5%~D
3.3K_0402_5%~D
1 2
R899 33_0402_5%~DR899 33_0402_5%~D
1 2
R901 33_0402_5%~DR901 33_0402_5%~D
12
@
@
RE1
RE1
33_0402_5%~D
33_0402_5%~D
1
@
@
CE2
CE2
27P_0402_50V8J~D
27P_0402_50V8J~D
2
4
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV#
USB_MCARD1_DET#
HDD_DET#_R
BBS_BIT0_R
GPIO36
GPIO37
EN_ESATA_RPTR#
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R
PCH_RTCX1
1
32.768KHZ_12.5PF_Q13MC1461000~D
32.768KHZ_12.5PF_Q13MC1461000~D
PCH_RTCX2_R
12
12
12
RH49
RH49
@
@
@
@
100_0402_1%~D
100_0402_1%~D
D
D
13
QH7
QH7
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
SPI_PCH_CLK
SPI_PCH_DO
YH1
YH1
2
G
G
34
G
G
1 2
@
@
RH286
RH286
1 2
RH32 33_0402_5%~DRH32 33_0402_5%~D
1 2
RH33 33_0402_5%~DRH33 33_0402_5%~D
1 2
RH34 33_0402_5%~DRH34 33_0402_5%~D
1 2
RH287 1K_0402_5%~D@ RH287 1K_0402_5%~D@
1 2
RH36 33_0402_5%~DRH36 33_0402_5%~D
1 2
RH50 1K_0402_5%~DRH50 1K_0402_5%~D
RH47
RH47
100_0402_1%~D
100_0402_1%~D
PCH_AZ_SYNC
RH1 33_0402_5%~D@ RH1 33_0402_5%~D@
RH3 33_0402_5%~D@ RH3 33_0402_5%~D@
RH4 33_0402_5%~D@ RH4 33_0402_5%~D@
RH5 33_0402_5%~D@ RH5 33_0402_5%~D@
RH6 33_0402_5%~D@ RH6 33_0402_5%~D@
RH7 33_0402_5%~D@ RH7 33_0402_5%~D@
RH8 33_0402_5%~D@ RH8 33_0402_5%~D@
RH9 33_0402_5%~D@ RH9 33_0402_5%~D@
RH10 33_0402_5%~D@RH10 33_0402_5%~D@
RH12 33_0402_5%~D@RH12 33_0402_5%~D@
RH13 33_0402_5%~D@RH13 33_0402_5%~D@
RH14 33_0402_5%~D@RH14 33_0402_5%~D@
RH15 33_0402_5%~D@RH15 33_0402_5%~D@
RH16 33_0402_5%~D@RH16 33_0402_5%~D@
RH17 33_0402_5%~D@RH17 33_0402_5%~D@
RH18 33_0402_5%~D@RH18 33_0402_5%~D@
RH19 33_0402_5%~D@RH19 33_0402_5%~D@
RH20 33_0402_5%~D@RH20 33_0402_5%~D@
RH24 1K_0402_5%~D@RH24 1K_0402_5%~D@
0_0402_5%~D
0_0402_5%~D
USB30_SMI#<29>
3
RSMRST#_XDP
PCH_AZ_SYNCPCH_AZ_SYNC_Q
PCH_AZ_SDOUT
PCH_GPIO33
USB30_SMI#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
DDR_XDP_WAN_SMBDAT<7,12,13,15,28,37>
DDR_XDP_WAN_SMBCLK<7,12,13,15,28,37>
1.05V_0.8V_PWROK<41,59>
SIO_PWRBTN#_R<7,16>
UH4A
UH4A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
+3.3V_ALW_PCH
1
@
@
CH1
CH1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
RH284 0_0402_5%~D@RH284 0_0402_5%~D@
1 2
1 2
RH285 0_0402_5%~D@RH285 0_0402_5%~D@
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
RH283 1K_0402_5%~D@RH283 1K_0402_5%~D@
1.05V_0.8V_PWROK_R
1 2
PCH_PWRBTN#_XDP
1 2
RH21 0_0402_5%~D@ RH21 0_0402_5%~D@
DDR_XDP_WAN_SMBDAT_R2
DDR_XDP_WAN_SMBCLK_R2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA 6G
SATA 6G
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
RH2
RH2
10M_0402_5%~D
10M_0402_5%~D
PCH_RTCX2
PCH_RTCRST#
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_AZ_BITCLK
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_MDC_SDIN1
PCH_JTAG_TCK
12
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
BBS_BIT0 - BIOS BOOT STRAP BIT 0
+3.3V_SPI
12
200 MIL SO8
R888
R888
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_PCH_CS1#
SPI_PCH_DIN
SPI_WP#_SEL SPI_CLK32
SPI_PCH_CS1#_R
1 2
R936 22_0402_5%~DR936 22_0402_5%~D
SPI_DIN32
1 2
R895 33_0402_5%~DR895 33_0402_5%~D
1 2
R896 0_0402_5%~D@R896 0_0402_5%~D@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
16Mb Flash ROM
X76@ U53
X76@
1
/CS
2
DO
3
/WP
GND4DIO
W25Q16BVSSIG_SO8~D
W25Q16BVSSIG_SO8~D
SPI_CLK32
12
@
@
RE2
RE2
33_0402_5%~D
33_0402_5%~D
1
@
@
CE1
CE1
27P_0402_50V8J~D
27P_0402_50V8J~D
2
U53
8
VCC
7
/HOLD
6
CLK
SPI_DO32
5
2
+3.3V_ALW_PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
LPC_LAD0
C38
LPC_LAD1
A38
LPC_LAD2
B37
LPC_LAD3
C37
LPC_LFRAME#
D36
LPC_LDRQ0#
E36
LPC_LDRQ1#
K36
IRQ_SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
SATA_COMP
Y10
AB12
SATA3_COMP
AB13
RBIAS_SATA3
AH1
SATA_ACT#
P3
HDD_DET#_R
V14
BBS_BIT0_R
P1
PCH_PLTRST#<7,17>
C745
C745
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
12
R892
R892
3.3K_0402_5%~D
3.3K_0402_5%~D
SPI_PCH_CLK
1 2
R897 33_0402_5%~DR897 33_0402_5%~D
SPI_PCH_DO
1 2
R900 33_0402_5%~DR900 33_0402_5%~D
2
JXDP2
CONN@JXDP2
CONN@
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-030-01-L-D-A
SAMTE_BSH-030-01-L-D-A
LPC_LAD0 <34,35,40,41>
LPC_LAD1 <34,35,40,41>
LPC_LAD2 <34,35,40,41>
LPC_LAD3 <34,35,40,41>
LPC_LFRAME# <34,35,40,41>
LPC_LDRQ0# <40>
LPC_LDRQ1# <40>
IRQ_SERIRQ <34,35,40,41>
PSATA_PRX_DTX_N0_C <28>
PSATA_PRX_DTX_P0_C <28>
PSATA_PTX_DRX_N0_C <28>
PSATA_PTX_DRX_P0_C <28>
SATA_ODD_PRX_DTX_N1_C <29>
SATA_ODD_PRX_DTX_P1_C <29>
SATA_ODD_PTX_DRX_N1_C <29>
SATA_ODD_PTX_DRX_P1_C <29>
ESATA_PRX_DTX_N4_C <45>
ESATA_PRX_DTX_P4_C <45>
ESATA_PTX_DRX_N4_C <45>
ESATA_PTX_DRX_P4_C <45>
SATA_PRX_DKTX_N5_C <39>
SATA_PRX_DKTX_P5_C <39>
SATA_PTX_DKRX_N5_C <39>
SATA_PTX_DKRX_P5_C <39>
1 2
RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D
1 2
RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D
1 2
RH46 750_0402_1%~DRH46 750_0402_1%~D
SATA_ACT# <44>
RH290 0_0402_5%~D@RH290 0_0402_5%~D@
D
D
1 3
QH1 BSS138W-7-F_SOT323-3~D
QH1 BSS138W-7-F_SOT323-3~D
G
G
2
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
+1.05V_RUN
+1.05V_RUN
1 2
S
S
JSPI1
JSPI1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
G1
18
G2
HRS_FH12-16S-0P5SH(55)~D
HRS_FH12-16S-0P5SH(55)~D
CONN@
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
2
GND1
XDP_FN16
4
XDP_FN17
6
8
GND3
XDP_FN8
10
XDP_FN9
12
14
GND5
XDP_FN10
16
XDP_FN11
18
20
GND7
22
24
26
GND9
XDP_FN12
28
XDP_FN13
30
32
GND11
GND13
GND15
TRST#
GND17
XDP_FN14
34
XDP_FN15
36
38
40
42
44
RSMRST#_XDP
46
XDP_DBRESET#
48
50
PCH_JTAG_TDO
52
TD0
54
PCH_JTAG_TDI
56
TDI
PCH_JTAG_TMSPCH_JTAG_TCK
58
TMS
60
PCH_GPIO33
IRQ_SERIRQ
PCH_AZ_SYNC_Q
BBS_BIT0_R
HDD
ODD/ E Module Bay
E-SATA
DOCK
+3.3V_RUN
12
RH30
RH30
10K_0402_5%~D
10K_0402_5%~D
PCH_SATA_MOD_EN# <41>
SPI_PCH_CS1#
PCH_SPI_CS1#
RH345 0_0402_5%~DRH345 0_0402_5%~D
SPI_PCH_DO
PCH_SPI_DO
RH346 0_0402_5%~DRH346 0_0402_5%~D
SPI_PCH_DIN
PCH_SPI_DIN
RH347 0_0402_5%~DRH347 0_0402_5%~D
SPI_PCH_CLK
PCH_SPI_CLK
RH348 0_0402_5%~DRH348 0_0402_5%~D
SPI_PCH_CS0#
PCH_SPI_CS0#
RH349 0_0402_5%~DRH349 0_0402_5%~D
+3.3V_M
RH350 0_0402_5%~DRH350 0_0402_5%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
1
+3.3V_ALW_PCH
XDP_DBRESET# <7,16>
RH355 100K_0402_5%~DRH355 100K_0402_5%~D
RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D
SPKR
1 2
1 2
1 2
1 2
1 2
1 2
12
12
12
RH41 10K_0402_5%~DRH41 10K_0402_5%~D
1 2
RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D
12
RH35 10K_0402_5%~D@RH35 10K_0402_5%~D@
No Reboot Strap
Low = Default
SPKR
High = No Reboot
HDD_DET# <28>
+3.3V_SPI
14 77Thursday, January 13, 2011
14 77Thursday, January 13, 2011
14 77Thursday, January 13, 2011
1
of
+3.3V_RUN
+3.3V_RUN
B
B
B
www.qdzbwx.com
5
D D
FollowDG0.9Devicedown&Express/Mini
cardtopology
PCIE_PRX_WANTX_N1<37>
MiniWWAN (Mini Card 1)--->
MiniWLAN (Mini Card 2)--->
EXPRESS Card--->
E3 Module Bay--->
1/2vMINI CARD-3 PCIE
(Mini Card 3)--->
C C
MMI --->
10/100/1G LAN --->
MiniWWAN (Mini Card 1)--->
10/100/1G LAN --->
MMI Card--->
B B
MiniWPAN (Mini Card 3)--->
Express card--->
MiniWLAN (Mini Card 2)--->
eModule Bay--->
A A
PCIE_PRX_WANTX_P1<37>
PCIE_PTX_WANRX_N1<37>
PCIE_PTX_WANRX_P1<37>
PCIE_PRX_WLANTX_N2<37>
PCIE_PRX_WLANTX_P2<37>
PCIE_PTX_WLANRX_N2<37>
PCIE_PTX_WLANRX_P2<37>
PCIE_PRX_EXPTX_N3<38>
PCIE_PRX_EXPTX_P3<38>
PCIE_PTX_EXPRX_N3<38>
PCIE_PTX_EXPRX_P3<38>
PCIE_PRX_EMBTX_N4<29>
PCIE_PRX_EMBTX_P4<29>
PCIE_PTX_EMBRX_N4<29>
PCIE_PTX_EMBRX_P4<29>
PCIE_PRX_WPANTX_N5<37>
PCIE_PRX_WPANTX_P5<37>
PCIE_PTX_WPANRX_N5<37>
PCIE_PTX_WPANRX_P5<37>
PCIE_PRX_MMITX_N6<36>
PCIE_PRX_MMITX_P6<36>
PCIE_PTX_MMIRX_N6<36>
PCIE_PTX_MMIRX_P6<36>
PCIE_PRX_GLANTX_N7<32>
PCIE_PRX_GLANTX_P7<32>
PCIE_PTX_GLANRX_N7<32>
PCIE_PTX_GLANRX_P7<32>
CLK_PCIE_MINI1#<37>
CLK_PCIE_MINI1<37>
+3.3V_ALW_PCH
MINI1CLK_REQ#<37>
CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>
LANCLK_REQ#<32>
CLK_PCIE_MMI#<36>
CLK_PCIE_MMI<36>
+3.3V_RUN
MMICLK_REQ#<36>
CLK_PCIE_MINI3#<37>
CLK_PCIE_MINI3<37>
+3.3V_ALW_PCH
MINI3CLK_REQ#<37>
CLK_PCIE_EXP#<38>
CLK_PCIE_EXP<38>
+3.3V_ALW_PCH
EXPCLK_REQ#<38>
CLK_PCIE_MINI2#<37>
CLK_PCIE_MINI2<37>
+3.3V_ALW_PCH
MINI2CLK_REQ#<37>
+3.3V_ALW_PCH
CLK_PCIE_EMB#<29>
CLK_PCIE_EMB<29>
+3.3V_ALW_PCH
EMBCLK_REQ#<29>
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
RH307 0_0402_5%~D@ RH307 0_0402_5%~D@
RH308 0_0402_5%~D@ RH308 0_0402_5%~D@
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
RH82 0_0402_5%~D@RH82 0_0402_5%~D@
RH83 0_0402_5%~D@RH83 0_0402_5%~D@
RH85 0_0402_5%~D@RH85 0_0402_5%~D@
RH86 0_0402_5%~D@RH86 0_0402_5%~D@
RH87 10K_0402_5%~DRH87 10K_0402_5%~D
RH88 0_0402_5%~D@RH88 0_0402_5%~D@
RH90 0_0402_5%~D@RH90 0_0402_5%~D@
RH152 10K_0402_5%~DRH152 10K_0402_5%~D
RH92 0_0402_5%~D@RH92 0_0402_5%~D@
RH93 0_0402_5%~D@RH93 0_0402_5%~D@
RH94 10K_0402_5%~DRH94 10K_0402_5%~D
RH95 0_0402_5%~D@RH95 0_0402_5%~D@
RH96 0_0402_5%~D@RH96 0_0402_5%~D@
RH97 10K_0402_5%~DRH97 10K_0402_5%~D
RH98 10K_0402_5%~DRH98 10K_0402_5%~D
RH310 0_0402_5%~D@ RH310 0_0402_5%~D@
RH312 0_0402_5%~D@ RH312 0_0402_5%~D@
RH104 10K_0402_5%~DRH104 10K_0402_5%~D
RH280 0_0402_5%~D@ RH280 0_0402_5%~D@
RH281 0_0402_5%~D@ RH281 0_0402_5%~D@
PCIEREQpowerrail:
suspend:034567
core:12
5
4
www.qdzbwx.com
UH4B
UH4B
1 2
1 2
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
4
PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3
PCIE_PRX_EMBTX_N4
PCIE_PRX_EMBTX_P4
PCIE_PTX_EMBRX_N4
PCIE_PTX_EMBRX_P4
PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5
PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_MMI#
PCIE_MMI
MMICLK_REQ#
PCIE_MINI3#
PCIE_MINI3
MINI3CLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCIE_MINI2#
PCIE_MINI2
MINI2CLK_REQ#
PEG_B_CLKRQ#
PCIE_EMB#
PCIE_EMB
EMBCLK_REQ#
CLK_BCLK_ITP#
CLK_BCLK_ITP
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
3
PCH_SMB_ALERT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
REFCLK14IN
XTAL25_IN
E12
H14
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
XCLK_RCOMP
PCI_TCM
SIO_14M
PCI_TPM
JETWAY_14M
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH
LAN_SMBCLK
LAN_SMBDATA
GPIO74
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
GFX_CLK_REQ#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_DPLL#
CLK_CPU_DPLL
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
CLK_PCI_LOOPBACK
XTAL25_IN
XTAL25_OUT
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
2
MEM_SMBCLK
MEM_SMBDATA
DDR_HVREF_RST_PCH <7>
LAN_SMBCLK <32>
LAN_SMBDATA <32>
SML1_SMBCLK <41>
SML1_SMBDATA <41>
PCH_CL_CLK1 <37>
PCH_CL_DATA1 <37>
PCH_CL_RST1# <37>
CLK_PCIE_VGA# <47>
CLK_PCIE_VGA <47>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_CPU_DPLL# <7>
CLK_CPU_DPLL <7>
CLK_PCI_LOOPBACK <17>
1 2
RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D
RH311 22_0402_5%~D4@ RH311 22_0402_5%~D4@
RH313 22_0402_5%~DRH313 22_0402_5%~D
RH314 22_0402_5%~DRH314 22_0402_5%~D
RH315 22_0402_5%~D@RH315 22_0402_5%~D@
12
12
12
12
2
+3.3V_RUN
2
6 1
5
3
4
QH5B
QH5B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
1 2
RH296 0_0402_5%~D@ RH296 0_0402_5%~D@
1 2
RH297 0_0402_5%~D@ RH297 0_0402_5%~D@
CLOCK TERMINATION for FCIM and need close to PCH
+1.05V_RUN
CLK_PCI_TPM_CHA <35>
CLK_SIO_14M <40>
CLK_PCI_TPM <34>
JETWAY_CLK14M <35>
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
QH5A
QH5A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
SML1_SMBCLK
SML1_SMBDATA
DDR_HVREF_RST_PCH
GPIO74
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
LAN_SMBCLK
LAN_SMBDATA
+3.3V_ALW_PCH
3.3V_RUN_GFX_ON<40,50>
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
CLK_PCH_14M
RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D
RH300 1K_0402_5%~DRH300 1K_0402_5%~D
RH301 10K_0402_5%~DRH301 10K_0402_5%~D
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
RH304 10K_0402_5%~DRH304 10K_0402_5%~D
RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D
RH80
RH80
10K_0402_5%~D
10K_0402_5%~D
RH309
RH309
@
@
12
RH99
RH99
1M_0402_5%~D
1M_0402_5%~D
25MHZ_12PF_X5H025000DC1H-H
25MHZ_12PF_X5H025000DC1H-H
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
DDR_XDP_WAN_SMBCLK <7,12,13,14,28,37>
DDR_XDP_WAN_SMBDAT <7,12,13,14,28,37>
+3.3V_ALW_PCH
1 2
1 2
+3.3V_ALW_PCH
12
12
12
12
12
+3.3V_LAN
12
12
GFX_CLK_REQ#
12
13
D
D
QH2
QH2
2
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
G
G
S
S
1 2
RH74 10K_0402_5%~DRH74 10K_0402_5%~D
1 2
RH75 10K_0402_5%~DRH75 10K_0402_5%~D
1 2
RH91 10K_0402_5%~DRH91 10K_0402_5%~D
1 2
RH76 10K_0402_5%~DRH76 10K_0402_5%~D
1 2
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
1 2
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
1 2
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
1 2
RH183 10K_0402_5%~DRH183 10K_0402_5%~D
12
0_0402_5%~D
0_0402_5%~D
YH2
YH2
12
2
CH18
CH18
1
10P_0402_50V8J~D
10P_0402_50V8J~D
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
1
2
CH19
CH19
1
10P_0402_50V8J~D
10P_0402_50V8J~D
15 77Thursday, January 13, 2011
15 77Thursday, January 13, 2011
15 77Thursday, January 13, 2011
of
of
of
B
B
B
5
4
3
2
1
+3.3V_ALW_PCH
DMI_COMP_R
RBIAS_CPY
1 2
PCH_RI#
SUS_STAT#/LPCPD#
ME_SUS_PWR_ACK
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_RI#
CLKRUN#
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
SUSACK#_R
XDP_DBRESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PM_DRAM_PWRGD_R
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#_R
SIO_PWRBTN#_R
AC_PRESENT
PCH_BATLOW#
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
PCH_RSMRST#_Q
UH4C
UH4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
1 2
RH113 0_0402_5%~D@ RH113 0_0402_5%~D@
SYS_PWROKRESET_OUT#
1 2
RH321 0_0402_5%~D@ RH321 0_0402_5%~D@
SUSACK#_R
1 2
RH323 0_0402_5%~D@RH323 0_0402_5%~D@
1 2
RH322 10K_0402_5%~DRH322 10K_0402_5%~D
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
DMI
DMI
System Power Management
System Power Management
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
H_PM_SYNC
SIO_SLP_LAN#
1 2
RH318 10K_0402_5%~D@RH318 10K_0402_5%~D@
1 2
RH144 10K_0402_5%~DRH144 10K_0402_5%~D
D D
+3.3V_RUN
C C
+1.05V_RUN
1 2
RH111 49.9_0402_1%~DRH111 49.9_0402_1%~D
1 2
RH112 750_0402_1%~DRH112 750_0402_1%~D
SUSACK#<40> PCH_DPWROK <40>
B B
A A
SYS_PWROK<7,40>
RESET_OUT#<41>
PM_APWROK<41>
PM_DRAM_PWRGD<7>
PCH_RSMRST#_Q<14,41>
ME_SUS_PWR_ACK<41>
AC_PRESENT<41>
+3.3V_ALW_PCH
SIO_PWRBTN#_R<7,14>
SIO_PWRBTN#<41>
1 2
RH142 10K_0402_5%~DRH142 10K_0402_5%~D
1 2
RH319 10K_0402_5%~D@RH319 10K_0402_5%~D@
1 2
RH140 10K_0402_5%~DRH140 10K_0402_5%~D
1 2
RH137 8.2K_0402_5%~DRH137 8.2K_0402_5%~D
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
1 2
RH114 0_0402_5%~D@ RH114 0_0402_5%~D@
XDP_DBRESET#<7,14>
1 2
RH116 0_0402_5%~D@ RH116 0_0402_5%~D@
1 2
RH117 0_0402_5%~D@ RH117 0_0402_5%~D@
1 2
RH118 0_0402_5%~D@ RH118 0_0402_5%~D@
1 2
RH320 0_0402_5%~D@ RH320 0_0402_5%~D@
1 2
RH120 0_0402_5%~D@ RH120 0_0402_5%~D@
1 2
RH121 0_0402_5%~D@ RH121 0_0402_5%~D@
RH122 0_0402_5%~D@ RH122 0_0402_5%~D@
1 2
RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D
RH131 150_0402_1%~DRH131 150_0402_1%~D
RH132 150_0402_1%~DRH132 150_0402_1%~D
RH133 150_0402_1%~DRH133 150_0402_1%~D
RH134 100K_0402_5%~DRH134 100K_0402_5%~D
DSWODVREN - On Die DSW VR Enable
Enabled (DEFAULT)
Disabled
RH127 330K_0402_1%~DRH127 330K_0402_1%~D
1 2
RH129 330K_0402_1%~D@RH129 330K_0402_1%~D@
1 2
PCH_PCIE_WAKE# <40>
CLKRUN# <35,40,41>
T56 PAD~DT56 PAD~D
T57 PAD~DT57 PAD~D
T58 PAD~DT58 PAD~D
SIO_SLP_S5# <41>
T59 PAD~DT59 PAD~D
SIO_SLP_S4# <40>
T60 PAD~DT60 PAD~D
SIO_SLP_S3# <40>
T61 PAD~DT61 PAD~D
SIO_SLP_A# <40,57>
T62 PAD~DT62 PAD~D
SIO_SLP_SUS# <40>
T63 PAD~DT63 PAD~D
SIO_SLP_LAN# <32,40>
PCH_CRT_BLU
1 2
PCH_CRT_GRN
1 2
PCH_CRT_RED
1 2
ENVDD_PCH
1 2
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
LOW: RH129 STUFFED,
RH127 UNSTUFFED
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC0 <6>
FDI_LSYNC1 <6>
H_PM_SYNC <7>
Minimum speacing of 20mils for LVD_IBG
+RTC_CELL
2.2K_0402_5%~D
2.2K_0402_5%~D
G_CLK_DDC2
PCH_CRT_HSYNC<25>
PCH_CRT_VSYNC<25>
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
12
12
RH317
RH316
RH316
RH317
+3.3V_RUN
4
PANEL_BKEN_PCH<24>
ENVDD_PCH<24,40>
BIA_PWM_PCH<24>
LDDC_CLK_PCH<23>
LDDC_DATA_PCH<23>
1 2
RH344 2.37K_0402_1%~DRH344 2.37K_0402_1%~D
LCD_ACLK-_PCH<23>
LCD_ACLK+_PCH<23>
LCD_A0-_PCH<23>
LCD_A1-_PCH<23>
LCD_A2-_PCH<23>
LCD_A0+_PCH<23>
LCD_A1+_PCH<23>
LCD_A2+_PCH<23>
LCD_BCLK-_PCH<23>
LCD_BCLK+_PCH<23>
LCD_B0-_PCH<23>
LCD_B1-_PCH<23>
LCD_B2-_PCH<23>
LCD_B0+_PCH<23>
LCD_B1+_PCH<23>
LCD_B2+_PCH<23>
PCH_CRT_BLU<25>
PCH_CRT_GRN<25>
PCH_CRT_RED<25>
RH123 20_0402_1%~DRH123 20_0402_1%~D
RH124 20_0402_1%~DRH124 20_0402_1%~D
PCH_CRT_DDC_CLK
61
QH6A
QH6A
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
2
5
QH6B
QH6B
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
PCH_CRT_DDC_DATG_DAT_DDC2
3
PANEL_BKEN_PCH
ENVDD_PCH
BIA_PWM_PCH
LDDC_CLK_PCH
LDDC_DATA_PCH
LVD_IBG
LCD_ACLK-_PCH
LCD_ACLK+_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH
LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH
LCD_BCLK-_PCH
LCD_BCLK+_PCH
LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH
LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
G_CLK_DDC2
G_DAT_DDC2
HSYNC
1 2
VSYNC
1 2
12
RH126
RH126
1K_0402_0.5%~D
1K_0402_0.5%~D
CRT_IREF
PCH_CRT_DDC_CLK <25>
PCH_CRT_DDC_DAT <25>
Intel request DDPB can not support eDP
UH4D
UH4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
CRT
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
16 77Thursday, January 13, 2011
16 77Thursday, January 13, 2011
16 77Thursday, January 13, 2011
1
B
B
B
of
of
of
+3.3V_RUN
5
4
3
2
1
PLTRST_USH#<34>
PLTRST_MMI#<36>
PLTRST_XDP#<7>
PLTRST_LAN#<32>
PLTRST_GPU#<47>
PLTRST_EMB#<29>
PCH_PLTRST#
5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LVDS_CBL_DET#
CAM_MIC_CBL_DET#
BT_DET#
PCH_GPIO3
+3.3V_RUN
5
1
P
B
2
A
G
3
HDD_FALL_INT<28>
1 2
RH335 0_0402_5%~D@ RH335 0_0402_5%~D@
1 2
RH336 0_0402_5%~D@ RH336 0_0402_5%~D@
1 2
RH337 0_0402_5%~D@ RH337 0_0402_5%~D@
1 2
RH338 0_0402_5%~D@ RH338 0_0402_5%~D@
1 2
RH343 0_0402_5%~D@ RH343 0_0402_5%~D@
1 2
RH340 0_0402_5%~D@ RH340 0_0402_5%~D@
CLK_PCI_5048<40>
CLK_PCI_MEC<41>
CLK_PCI_DOCK<39>
CLK_PCI_LOOPBACK<15>
CH102
CH102
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
UH3
UH3
PCH_PLTRST#_EC
4
O
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PCIE_MCARD2_DET#_R<37>
BT_DET#<42>
LVDS_CBL_DET#<24>
CAM_MIC_CBL_DET#<24>
1 2
RH334 0_0402_5%~D@RH334 0_0402_5%~D@
1 2
12
12
12
4
RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 33_0402_5%~DRH103 33_0402_5%~D
RH105 22_0402_5%~DRH105 22_0402_5%~D
PCH_PLTRST#_EC <14,35,37,38,40,41>
T72PAD~D @T72PAD~D @
T64PAD~D @T64PAD~D @
T73PAD~D @T73PAD~D @
T65PAD~D @T65PAD~D @
T74PAD~D @T74PAD~D @
T66PAD~D @T66PAD~D @
T67PAD~D @T67PAD~D @
T75PAD~D @T75PAD~D @
T76PAD~D @T76PAD~D @
T77PAD~D @T77PAD~D @
T68PAD~D @T68PAD~D @
T69PAD~D @T69PAD~D @
T78PAD~D @T78PAD~D @
T79PAD~D @T79PAD~D @
T80PAD~D @T80PAD~D @
T70PAD~D @T70PAD~D @
T81PAD~D @T81PAD~D @
T71PAD~D @T71PAD~D @
T82PAD~D @T82PAD~D @
T83PAD~D @T83PAD~D @
T84PAD~D @T84PAD~D @
T85PAD~D @T85PAD~D @
T86PAD~D @T86PAD~D @
T87PAD~D @T87PAD~D @
T88PAD~D @T88PAD~D @
T89PAD~D @T89PAD~D @
T90PAD~D @T90PAD~D @
T91PAD~D @T91PAD~D @
T92PAD~D @T92PAD~D @
T93PAD~D @T93PAD~D @
T94PAD~D @T94PAD~D @
T95PAD~D @T95PAD~D @
T96PAD~D @T96PAD~D @
T97PAD~D @T97PAD~D @
T98PAD~D @T98PAD~D @
T99PAD~D @T99PAD~D @
T100PAD~D @T100PAD~D @
T101PAD~D @T101PAD~D @
T102PAD~D @T102PAD~D @
T103PAD~D @T103PAD~D @
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
BT_DET#
BBS_BIT1
PCI_GNT3#
LVDS_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
FFS_PCH_INT
T104PAD~D @T104PAD~D @
PCH_PLTRST#
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
UH4E
UH4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
RSVD
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
RSVD
PCI
PCI
USB
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
SATA_SLPD
(BBS_BIT0)
0 0
0 1
1 0
1 1
LPC
Reserved (NAND)
PCI
SPI
3
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBP13USBP13+
USBRBIAS
USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USBP0- <45>
USBP0+ <45>
USBP1- <45>
USBP1+ <45>
USBP2- <46>
USBP2+ <46>
USBP3- <46>
USBP3+ <46>
USBP4- <37>
USBP4+ <37>
USBP5- <37>
USBP5+ <37>
USBP6- <37>
USBP6+ <37>
USBP7- <34>
USBP7+ <34>
USBP8- <39>
USBP8+ <39>
USBP9- <39>
USBP9+ <39>
USBP10- <38>
USBP10+ <38>
USBP11- <42>
USBP11+ <42>
USBP12- <24>
USBP12+ <24>
USBP13- <24>
USBP13+ <24>
Within 500 mils
1 2
RH151
RH151
22.6_0402_1%~D
22.6_0402_1%~D
1 2
RH339 0_0402_5%~D@ RH339 0_0402_5%~D@
1 2
RH341 0_0402_5%~D@ RH341 0_0402_5%~D@
SIO_EXT_SMI#
BBS_BIT1
----->Right Side
----->Right Side
----->left Side
----->Left Side
----->WLAN/WIMAX
----->WWAN/UWB
----->Flash
----->USH
----->DOCK
----->DOCK
----->Express Card
----->Blue Tooth
----->Camera
----->LCD Touch
12
RH342
@RH342
@
1K_0402_5%~D
1K_0402_5%~D
2
USB_OC0# <45>
USB_OC1# <46>
USB_OC2# <14>
USB_OC3# <14>
USB_OC4# <14>
USB_OC5# <14>
USB_OC6# <14>
SIO_EXT_SMI# <14,41>
USB_OC0#_R <14>
USB_OC1#_R <14>
+3.3V_ALW_PCH
RPH1
USB_OC0#
USB_OC1#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC2#
SIO_EXT_SMI#
RH51 10K_0402_5%~DRH51 10K_0402_5%~D
RPH1
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
RPH2
RPH2
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%~D
10K_1206_8P4R_5%~D
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
17 77Thursday, January 13, 2011
17 77Thursday, January 13, 2011
17 77Thursday, January 13, 2011
1
of
of
B
B
B
1 2
D D
C C
RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D
1 2
RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D
1 2
RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D
1 2
RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D
1 2
RH327 10K_0402_5%~DRH327 10K_0402_5%~D
1 2
RH330 10K_0402_5%~DRH330 10K_0402_5%~D
1 2
RH331 10K_0402_5%~DRH331 10K_0402_5%~D
1 2
RH328 10K_0402_5%~DRH328 10K_0402_5%~D
1 2
RH332 10K_0402_5%~D@RH332 10K_0402_5%~D@
PCI_GNT3#
12
RH333
@RH333
@
1K_0402_5%~D
1K_0402_5%~D
A16 swap override Strap/Top-Block
Swap Override jumper
PCI_GNT#3
B B
A A
PCH_PLTRST#<7,14>
Low = A16 swap
High = Default
5
+3.3V_ALW_PCH
RH53
RH53
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
SLP_ME_CSW_DEV#
RH353
D D
C C
B B
A A
RH353
1K_0402_5%~D
1K_0402_5%~D
@
@
1 2
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
+3.3V_ALW_PCH
SIO_EXT_WAKE# PCH_GPIO1
1 2
1 2
RH273 1K_0402_5%~D@ RH273 1K_0402_5%~D@
12
KB_DET#
12
GPIO36
12
GPIO37
12
EN_ESATA_RPTR#
12
TEMP_ALERT#
12
MEDIA_DET#
12
GPIO17
IO_LOOP#
IO1_LOOP#
PCH_GPIO15
5
RH177 10K_0402_5%~DRH177 10K_0402_5%~D
RH354 1K_0402_5%~DRH354 1K_0402_5%~D
GPIO17
+3.3V_ALW_PCH
RH170 10K_0402_5%~DRH170 10K_0402_5%~D
+3.3V_RUN
RH171 10K_0402_5%~D@RH171 10K_0402_5%~D@
RH173 1K_0402_1%~D@ RH173 1K_0402_1%~D@
RH265 10K_0402_5%~DRH265 10K_0402_5%~D
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
RH179 10K_0402_5%~DRH179 10K_0402_5%~D
1 2
RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D
1 2
RH163 10K_0402_5%~DRH163 10K_0402_5%~D
1 2
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
SIO_EXT_SCI#_R<14>
SIO_EXT_SCI#<41>
IO_LOOP#<46>
IO1_LOOP#<46>
SIO_EXT_WAKE#<14,40>
PM_LANPHY_ENABLE<32>
PCH_GPIO15<14>
EN_ESATA_RPTR#<14>
MEDIA_DET#<46>
PCIE_MCARD1_DET#<37>
E3_PAID_TS_DET#<24>
SLP_ME_CSW_DEV#<14,40>
DGPU_HOLD_RST#<47>
USB_MCARD1_DET#<14,37>
GPIO36<14>
GPIO37<14>
FFS_INT2<28>
TEMP_ALERT#<14,40>
KB_DET#<42>
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
+3.3V_RUN
TPM_ID0
RH267
1@ RH267
1@
10K_0402_5%~D
10K_0402_5%~D
1 2
RH270
2@ RH270
2@
10K_0402_5%~D
10K_0402_5%~D
1 2
4
SIO_EXT_SCI#
RH259 0_0402_5%~D@ RH259 0_0402_5%~D@
PCH_GPIO1
IO_LOOP#
IO1_LOOP#
PM_LANPHY_ENABLE
PCH_GPIO15
EN_ESATA_RPTR#
GPIO17
MEDIA_DET#
E3_PAID_TS_DET#
SLP_ME_CSW_DEV#
DGPU_HOLD_RST#
USB_MCARD1_DET#
GPIO36
GPIO37
TPM_ID0
TPM_ID1
FFS_INT2
TEMP_ALERT#
KB_DET#
TPM_ID1
4
1 2
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
+3.3V_RUN
12
3@ RH268
3@
12
4@ RH271
4@
T7
A42
H36
E38
C10
C4
G2
U2
D40
T5
E8
E16
P8
K1
K4
V8
M5
N2
M3
V13
V3
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
RH268
20K_0402_5%~D
20K_0402_5%~D
RH271
2.2K_0402_5%~D
2.2K_0402_5%~D
UH4F
UH4F
BMBUSY# / GPIO0
TACH1 / GPIO1
TACH2 / GPIO6
TACH3 / GPIO7
GPIO8
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24 / MEM_LED
GPIO27
GPIO28
STP_PCI# / GPIO34
GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
SATA5GP / GPIO49
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
China TPM
No TPM, No China TPM
USH2.0
GPIO
GPIO
NCTF
NCTF
3
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
DF_TVS
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
0
0
1 1
3
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
CONTACTLESS_DET#
DGPU_PWROK
SIO_A20GATE
SIO_RCIN#
H_CPUPWRGD
PCH_THRMTRIP#_R
INIT3_3V#
DF_TVS
NC_1
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2
CONTACTLESS_DET# <34>
DGPU_PWROK <40,64>
PCIE_MCARD3_DET# <37>
USB_MCARD2_DET# <37>
SIO_A20GATE <41>
SIO_RCIN# <41>
H_CPUPWRGD <7>
T106PAD~D@T106PAD~D
@
T108PAD~D @T108PAD~D @
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
RH262 56_0402_5%~DRH262 56_0402_5%~D
1
CH97
CH97
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
+1.05V_RUN_VTT
12
CONTACTLESS_DET#
PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)
+VCCDFTERM
12
1 2
RH256 10K_0402_1%~DRH256 10K_0402_1%~D
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
RH149
RH149
2.2K_0402_5%~D
2.2K_0402_5%~D
RH150 0_0402_5%~DRH150 0_0402_5%~D
1
+3.3V_RUN
+3.3V_RUN
RH158 10K_0402_5%~DRH158 10K_0402_5%~D
RH203 10K_0402_5%~DRH203 10K_0402_5%~D
RH263 10K_0402_5%~DRH263 10K_0402_5%~D
RH164 10K_0402_5%~DRH164 10K_0402_5%~D
12
12
1 2
1 2
RH149 need to close to CPU
1 2
DF_TVSDF_TVS_R
DMI & FDI Termination Voltage
DF_TVS
TPM_ID1TPM_ID0
Set to Vss when LOW
Set to Vcc when HIGH
0
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
18 77Thursday, January 13, 2011
18 77Thursday, January 13, 2011
18 77Thursday, January 13, 2011
1
of
of
B
B
B
5
4
3
2
1
LH1
POWER
+1.05V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CH30
CH30
D D
+1.05V_RUN
+1.05V_RUN
C C
+3.3V_RUN
B B
@ RH247
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
1 2
RH247
CH51
CH51
2
+1.05V_RUN
1UH_LB2012T1R0M_20%~D
1UH_LB2012T1R0M_20%~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH44
CH44
CH45
CH45
2
2
+1.05V_RUN
+1.05V_RUN_VTT
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH32
CH32
CH33
CH33
2
2
1
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
+1.05V_+1.5V_1.8V_RUN
CH46
CH46
1
1
CH47
CH47
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH31
CH31
2
+VCCAPLLEXP
CH40
CH40
@
@
10U_0805_4VAM~D
10U_0805_4VAM~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH48
CH48
+VCCAPLL_FDI
UH4G
UH4G
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
DMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
DFT / SPI HVCMOS
DFT / SPI HVCMOS
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCCLKDMI
VCCSPI
U48
U47
AK36
AK37
AM37
AM38
AP36
AP37
V33
V34
AT16
AT20
AB36
AG16
AG17
AJ16
AJ17
V1
+VCCADAC
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
1
CH34
CH34
2
2
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CH103
CH103
2
1
CH43
CH43
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCCLKDMI
1
CH50
CH50
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+VCCDFTERM
1
CH52
CH52
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH54
CH54
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1 2
LH1
12
BLM18PG181SN1_0603~D
BLM18PG181SN1_0603~D
10U_0805_4VAM~D
10U_0805_4VAM~D
1
CH36
CH36
CH35
CH35
2
+1.8V_RUN_LVDS
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1
CH104
CH104
2
CH49
CH49
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
@
@
CH106
CH106
10U_0805_4VAM~D
10U_0805_4VAM~D
2
RH276 0_0805_5%~D@ RH276 0_0805_5%~D@
@PJP66
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
1
2
+3.3V_RUN
LH9 HK1608R10J-T_0603~DLH9 HK1608R10J-T_0603~D
1 2
PJP66
+3.3V_M
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CH105
CH105
+1.05V_RUN_VTT
12
+3.3V_RUN
LH8
LH8
HK1608R10J-T_0603~D
HK1608R10J-T_0603~D
0.1uH inductor, 200mA
CPN: SHI0110BJ0L
+3.3V_RUN
+1.8V_RUN
12
+1.05V_RUN
+3.3V_RUN
+1.8V_RUN
PCH Power Rail Table
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC3
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax
Current (A)
0.001
5
5
0.001
0.001
0.266
0.001
0.08
0.08
1.3
0.042
1.05VccIO 2.925
VccASW
VccSPI
VccDSW3_3 0.003
1.05
3.3
3.3
1.01
0.020
1.8 0.19VccpDFTERM
3.3VccRTC 2 (mA)
3.3VccSus3_3
3.3VccSusHDA
0.119
0.01
VccVRM 1.8 / 1.5 0.16
1.05VccClkDMI 0.02
1.05VccSSC
VccDIFFCLKN 0.055
1.05
VccALVDS 3.3
0.095
0.001
1.8VccTX_LVDS 0.06
VccAPLLEXP 1.05 0.05
+1.05V_RUN
+VCCAPLL_FDI
1 2
RH195 0.022_0805_1%@RH195 0.022_0805_1%@
+1.5V_RUN
+1.8V_RUN
+1.05V_RUN
A A
RH197 0_0603_5%~DRH197 0_0603_5%~D
RH198 0_0603_5%~D@ RH198 0_0603_5%~D@
RH199 0_0603_5%~D@ RH199 0_0603_5%~D@
12
12
12
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
1
+
CH41
@+CH41
@
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
2
1
+
CH42
@+CH42
@
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
19 77Thursday, January 13, 2011
19 77Thursday, January 13, 2011
19 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
Note: C225 - STUFFED ONLY FOR CPT INTERPOSER;
UNSTUFF FOR CPT
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW2
D D
+1.05V_RUN
1 2
RH201 0_0402_5%~D@RH201 0_0402_5%~D@
1 2
RH253 0_0402_5%~D@ RH253 0_0402_5%~D@
LH3
@ LH3
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
@CH58
@
CH58
1
2
+1.05V_RUN
RH200 0.022_0805_1%@RH200 0.022_0805_1%@
1
CH55
CH55
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
www.qdzbwx.com
+1.05V_M
C C
+3.3V_RUN
1 2
RH215 0.022_0805_1%@RH215 0.022_0805_1%@
LH4
LH4
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
B B
+1.05V_M
RH248 0.022_0805_1%@RH248 0.022_0805_1%@
A A
+1.05V_RUN
1 2
+1.05V_M_VCCSUS
+1.05V_RUN_VTT
+1.05V_RUN
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
5
LH6
LH6
1 2
1 2
LH7
LH7
+3.3V_RUN_VCC_CLKF33
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
@CH73
@
1
CH73
2
1
CH96
CH96
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CH85
CH85
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
2
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1
+
+
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH74
CH74
2
1
2
1
CH79
CH79
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH86
CH86
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH92
CH92
CH94
CH94
1
+
+
2
2
1 2
@
@
CH57
CH57
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
1
1
CH64
CH64
2
2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
1
CH67
CH67
2
2
CH78
CH78
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
CH81
CH81
1 2
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH84
CH84
2
1
CH87
CH87
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH93
CH93
CH95
CH95
1
2
4
+VCCACLK
+VCCDSW3_3
+PCH_VCCDSW
1
+3.3V_RUN_VCC_CLKF33
2
+VCCAPLL_CPY_PCH
+VCCSUS1
1
@
@
CH61
CH61
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
CH65
CH65
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
CH69
CH69
CH68
CH68
2
+VCCRTCEXT
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VCCA_A_DPL
+1.05V_RUN_VCCA_B_DPL
+VCCSST
+1.05V_M_VCCSUS
1
CH83
@CH83
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
+RTC_CELL
1
1
CH89
CH89
CH88
CH88
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+1.05V_RUN_VCCA_A_DPL +1.05V_RUN_VCCA_B_DPL
4
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
AG33
V16
T17
V19
BJ8
A22
1
CH90
CH90
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1 2
RH279 0_0805_5%~D@ RH279 0_0805_5%~D@
UH4J
UH4J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3[5]
VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]
VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCADPLLA
VCCADPLLB
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCSSC
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO
VCCRTC
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
3
POWER
POWER
N26
VCCIO[29]
P26
VCCIO[30]
P28
VCCIO[31]
T27
VCCIO[32]
T29
VCCIO[33]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
V5REF
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
T21
V21
T19
P32
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
VCCAPLLSATA
SATA USB
SATA USB
VCCASW[22]
VCCASW[23]
HDA
HDA
VCCASW[21]
VCCSUSHDA
3
CPURTC
CPURTC
1
2
1
CH59
CH59
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+PCH_V5REF_SUS
+VCCA_USBSUS
+PCH_V5REF_RUN
1
2
1
CH91
CH91
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
CH56
CH56
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
2
CH70
CH70
1U_0603_10V6K~D
1U_0603_10V6K~D
+3.3V_RUN
1
CH76
CH76
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
+VCCSATAPLL
+1.05V_+1.5V_1.8V_RUN
CH60
CH60
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH66
CH66
2
1
CH72
CH72
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
1
CH82
CH82
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
2
2
+1.05V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN
CH75
CH75
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH77
CH77
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
1
CH80
CH80
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
2
+1.05V_M
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CRB 0.7 RH208,RH213 trace width 20mil.
+3.3V_RUN
+1.05V_RUN
LH5
@LH5
@
10UH_LBR2012T100M_20%~D
10UH_LBR2012T100M_20%~D
1 2
@
@
+1.05V_RUN
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet of
1
PJP68 PAD-OPEN1x1mPJP68 PAD-OPEN1x1m
1 2
D
S
D
S
1 3
QH4
@
QH4
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
ALW_ENABLE<43>
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
10_0402_5%~D
@
G
G
2
+3.3V_ALW_PCH+5V_ALW_PCH
12
21
DH2
+3.3V_RUN+5V_RUN
12
+VCCA_USBSUS
+1.05V_RUN
1
DH2
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_SUS
1
CH63
CH63
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
21
DH3
DH3
RB751S40T1_SOD523-2~D
RB751S40T1_SOD523-2~D
+PCH_V5REF_RUN
1
CH71
CH71
1U_0603_10V6K~D
1U_0603_10V6K~D
2
RH208
RH208
RH213
RH213
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
+5V_ALW_PCH+5V_ALW
1
CH98
CH98
2
@
@
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
CH62
@CH62
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
2
20 77Thursday, January 13, 2011
20 77Thursday, January 13, 2011
20 77Thursday, January 13, 2011
12
RH278
RH278
@
@
20K_0402_5%~D
20K_0402_5%~D
B
B
B
of
of
5
D D
C C
B B
A A
UH4H
UH4H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
4
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
UH4I
UH4I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
CougarPoint_Rev_1p0
CougarPoint_Rev_1p0
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
21 77Thursday, January 13, 2011
21 77Thursday, January 13, 2011
21 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
PlaceunderCPU
PlaceC266closetotheQ12aspossible
C
@
@
D D
100P_0402_50V8J~D
100P_0402_50V8J~D
C266
C266
2
1
C
2
B
B
E
E
Q12
Q12
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
REM_DIODE1_P_4022
REM_DIODE1_N_4022
DP3/DN3forSODIMMonQ14,placeQ14closetoSODIMMandC272closetoQ14
DP5/DN5forSkinonQ13,placeQ13closetoJMINI1forWWANandC277closeQ13.
REM_DIODE3_P_4022
1
C272
@C272
@
100P_0402_50V8J~D
100P_0402_50V8J~D
C C
B B
2
+1.05V_RUN_VTT
H_THERMTRIP#<7>
C
C
E
E
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
R398
R398
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
PMST3904_SOT323-3~D
PMST3904_SOT323-3~D
2.2K_0402_5%~D
2.2K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
12
12
R1111
R1111
2
B
B
Q14
Q14
2
B
B
Q15
Q15
R1112
R1112
100P_0402_50V8J~D
100P_0402_50V8J~D
+3.3V_M
12
R395
R395
8.2K_0402_5%~D
8.2K_0402_5%~D
C
C
E
E
3 1
+3.3V_M+3.3V_RUN_GFX
12
THERMATRIP2#
R405
R405
8.2K_0402_5%~D
8.2K_0402_5%~D
C277
@C277
@
1
C278
C278
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
E
E
31
Q13
Q13
B
B
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
2
C
C
2
REM_DIODE3_N_4022
4
+FAN1_VOUT
D2
+5V_RUN
1
2
10U_0805_10V4Z~D
C276
C276
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C275
C275
1
1
C305
2
C305
2
2
+3.3V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
RB751S40T1_SOD523-2~DD2RB751S40T1_SOD523-2~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C1171
C1171
1 2
C270 2200P_0402_50V7K~DC270 2200P_0402_50V7K~D
C271 2200P_0402_50V7K~DC271 2200P_0402_50V7K~D
MAX8731_IINP<61>
PCH_PWRGD#<41>
3
FAN1_DET#
FAN1_TACH_FB
1
C219
C219
2
2 1
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
+3.3V_M
1 2
R389 10K_0402_5%~DR389 10K_0402_5%~D
12
R387 4.7K_0402_5%~DR387 4.7K_0402_5%~D
+3.3V_M
R1178 10K_0402_5%~DR1178 10K_0402_5%~D
R391 1K_0402_5%~DR391 1K_0402_5%~D
VDD_PWRGD
REM_DIODE1_N_4022
REM_DIODE1_P_4022
VGA_THERMDN
VGA_THERMDP
REM_DIODE3_P_4022
REM_DIODE3_N_4022
VCP2
12
VSET_4022
FAN1_TACH_FB
FAN1_DET#
1 2
+RTC_CELL
JFAN1
1
1
2
2
3
3
4
4
MOLEX_53398-0471~D
MOLEX_53398-0471~D
PWM
12
3V_PWROK#
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1
C274
C274
2
2
CONN@JFAN1
CONN@
5
G1
6
G2
www.qdzbwx.com
U9
U9
2
VDDH
3
VDDH
6
VDDL
13
VDD_PWRGD
23
DN1/THERM
24
DP1/VREF_T
26
DN2/DP4
27
DP2/DN4
30
DP3/DN5
29
DN3/DP5
31
VCP
25
VIN
28
VSET
10
TACH/GPIO1
11
GPIO2
15
GPIO3/PWM/THERMTRIP_SIO
12
3V_PWROK#
16
RTC_PWR3V
EMC4022-1-EZK-TR_QFN32_5X5~D
EMC4022-1-EZK-TR_QFN32_5X5~D
THERMTRIP2#
THERMTRIP3#
SYS_SHDN#
POWER_SW#
ACAVAIL_CLR
ATF_INT#/BC_IRQ#
FAN_OUT
FAN_OUT
SMCLK/BC_CLK
SMDATA/BC_DATA
VDD
ADDR_MODE/XEN
TEST1
TEST2
VSS
17
18
19
20
21
9
5
4
8
7
1
32
14
22
33
THERMATRIP2#
THERMATRIP3#
POWER_SW#
ACAV_IN
BC_INT#_EMC4022
+FAN1_VOUT
+VCC_4022
ADDR_XEN
1 2
R393 4.7K_0402_5%~DR393 4.7K_0402_5%~D
12
R403
R403
10K_0402_5%~D
10K_0402_5%~D
VGA_THERMDP<48>
VGA_THERMDN<48>
BC_INT#_EMC4022
FAN1_TACH_FB
FAN1_DET#
1 2
R390 47K_0402_1%~D@ R390 47K_0402_1%~D@
ACAV_IN <41,61,63>
BC_INT#_EMC4022 <41>
BC_CLK_EMC4022 <41>
BC_DAT_EMC4022 <41>
+VCC_4022
1
DSConly
VGA_THERMDP
1
C1104
C1104
470P_0402_50V7K~D
470P_0402_50V7K~D
2
VGA_THERMDN
THERM_STP# <54>
+RTC_CELL
R388
R388
22_0402_5%~D
22_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C273
C273
2
12
12
12
+3.3V_M
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
C1179
C1179
12
1
2
R385 10K_0402_5%~DR385 10K_0402_5%~D
R426 10K_0402_5%~DR426 10K_0402_5%~D
R402 10K_0402_5%~DR402 10K_0402_5%~D
+3.3V_M
THERMATRIP3#
C
C
THERMB3
2
B
B
E
E
Q115
PMST3904_SOT323-3~D
THERMTRIP_VGA#<47>
PMST3904_SOT323-3~D
Q115
1
C280
C280
0.1U_0402_16V4Z~D
3 1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C282
C282
1
2
12
R406
R406
953_0402_1%~D
953_0402_1%~D
VSET_4022
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
POWER_SW#
U10
U10
4
+RTC_CELL
5
O
3
1
P
B
2
A
G
C281
C281
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2
DOCK_PWR_SW# <41>
POWER_SW_IN# <41>
Rest=953,Tp=88degree
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
22 77Thursday, January 13, 2011
22 77Thursday, January 13, 2011
22 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
4
3
2
1
D D
PORTA
U84
U84
LCD_A0+_GPU<48>
LCD_A0-_GPU<48>
LCD_A1+_GPU<48>
LCD_A1-_GPU<48>
LCD_A2+_GPU<48>
LCD_A2-_GPU<48>
LCD_ACLK+_GPU<48>
LCD_ACLK-_GPU<48>
LDDC_CLK_GPU<47>
LDDC_DATA_GPU<47>
LCD_A0+_PCH<16>
LCD_A0-_PCH<16>
LCD_A1+_PCH<16>
LCD_A1-_PCH<16>
LCD_A2+_PCH<16>
LCD_A2-_PCH<16>
LCD_ACLK+_PCH<16>
C C
B B
LVDSSW
LCD_ACLK-_PCH<16>
LDDC_CLK_PCH<16>
LDDC_DATA_PCH<16>
DGPU_SELECT#
48
0B1
47
1B1
43
2B1
42
3B1
37
4B1
36
5B1
32
6B1
31
7B1
22
8B1
23
9B1
46
0B2
45
1B2
41
2B2
40
3B2
35
4B2
34
5B2
30
6B2
29
7B2
25
8B2
26
9B2
54
SEL2
52
NC
5
NC
51
NC
57
Thermal_GND
PI3LVD400ZFEX_TQFN56_11X5~D
PI3LVD400ZFEX_TQFN56_11X5~D
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V_RUN_GFX
+3.3V_RUN
+3.3V_RUN_LVDS_A
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C1145
C1145
C1146
C1146
C1147
C1147
1
1
4
10
18
27
38
50
56
2
3
7
8
11
12
14
15
19
20
17
1
6
9
13
16
21
24
28
33
39
44
49
53
55
R1122 2.2K_0402_5%~DR1122 2.2K_0402_5%~D
R1121 2.2K_0402_5%~DR1121 2.2K_0402_5%~D
R1124 2.2K_0402_5%~DR1124 2.2K_0402_5%~D
R1123 2.2K_0402_5%~DR1123 2.2K_0402_5%~D
1 2
1 2
1 2
1 2
2
2
SW_LVDS_A0+ <24>
SW_LVDS_A0- <24>
SW_LVDS_A1+ <24>
SW_LVDS_A1- <24>
SW_LVDS_A2+ <24>
SW_LVDS_A2- <24>
SW_LVDS_ACLK+ <24>
SW_LVDS_ACLK- <24>
0
1
LDDC_CLK_SW <24>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PAD-OPEN1x1m
PAD-OPEN1x1m
1
2
LDDC_DATA_SW <24>
DGPU_SELECT# <25,40>
ChanelSEL
COM=B2
LDDC_CLK_GPU
LDDC_DATA_GPU
LDDC_CLK_PCH
LDDC_DATA_PCH
PJP54
PJP54
1 2
+3.3V_RUN
Source
GPUCOM=B1
PCH
LCD_B0+_GPU<48>
LCD_B0-_GPU<48>
LCD_B1+_GPU<48>
LCD_B1-_GPU<48>
LCD_B2+_GPU<48>
LCD_B2-_GPU<48>
LCD_BCLK+_GPU<48>
LCD_BCLK-_GPU<48>
LCD_B0+_PCH<16>
LCD_B0-_PCH<16>
LCD_B1+_PCH<16>
LCD_B1-_PCH<16>
LCD_B2+_PCH<16>
LCD_B2-_PCH<16>
LCD_BCLK+_PCH<16>
LCD_BCLK-_PCH<16>
DGPU_SELECT#
PORTB
U85
U85
48
0B1
47
1B1
43
2B1
42
3B1
37
4B1
36
5B1
32
6B1
31
7B1
22
8B1
23
9B1
46
0B2
45
1B2
41
2B2
40
3B2
35
4B2
34
5B2
30
6B2
29
7B2
25
8B2
26
9B2
54
SEL2
52
NC
5
NC
51
NC
57
Thermal_GND
PI3LVD400ZFEX_TQFN56_11X5~D
PI3LVD400ZFEX_TQFN56_11X5~D
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3.3V_RUN_LVDS_B
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C1148
C1150
C1150
1
1
2
2
SW_LVDS_B0+ <24>
SW_LVDS_B0- <24>
SW_LVDS_B1+ <24>
SW_LVDS_B1- <24>
SW_LVDS_B2+ <24>
SW_LVDS_B2- <24>
SW_LVDS_BCLK+ <24>
SW_LVDS_BCLK- <24>
0
1
C1148
C1149
C1149
4
10
18
27
38
50
56
2
A0
3
A1
7
A2
8
A3
11
A4
12
A5
14
A6
15
A7
19
A8
20
A9
DGPU_SELECT#DGPU_SELECT#
17
1
6
9
13
16
21
24
28
33
39
44
49
53
55
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
ChanelSEL
COM=B2
PJP55
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
Source
GPUCOM=B1
PCH
+3.3V_RUN
PJP55
CONN@
CONN@
JFP1
JFP1
1
1
2
2
3
3
4
4
5
7
5
G1
6
8
6
G2
TYCO_2041084-6~D
A A
TYCO_2041084-6~D
FP_USB_DFP_USB_D+
FP_RESET# <34>
+3.3V_FP
1
C285
C285
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
R1135 0_0402_5%~D@ R1135 0_0402_5%~D@
R1136 0_0402_5%~D@ R1136 0_0402_5%~D@
1 2
1 2
+3.3V_RUN
+3.3V_ALW
U12
U12
1
GND
VCC
2
IO1
IO2
PRTR5V0U2X_SOT143-4~D
PRTR5V0U2X_SOT143-4~D
L8
@L8
@
DLW21SN121SQ2L_4P~D
DLW21SN121SQ2L_4P~D
4
3
+3.3V_FP
FP_USBD+<34>
FP_USBD-<34>
1
1
4
4
1 2
R409 0_0402_5%~DR409 0_0402_5%~D
1 2
R410 0_0402_5%~DR410 0_0402_5%~D
FP_USB_D+
2
2
FP_USB_D-FP_USB_D- FP_USB_D+
3
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
FingerprintCONN.
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
23 77Thursday, January 13, 2011
23 77Thursday, January 13, 2011
23 77Thursday, January 13, 2011
1
B
B
B
of
of
of
5
ACES_59003-0400C-001
ACES_59003-0400C-001
1
GND
BATT_WHITE_LED
BATT_YELLOW_LED
BREATH_WHITE_LED
D D
C C
46
45
44
43
42
41
MGND6
MGND5
MGND4
MGND3
MGND2
MGND1
JLVDS1
JLVDS1
+3.3V_RUN
DISP_ON/OFF#
CONNTST_GND
LCD_B_CLK+
LCD_B_CLK-
LVDS_A_CLK+
LVDS_A_CLK-
CONN@
CONN@
2
3
4
5
VR_SRC
6
VR_SRC
7
VR_SRC
8
NC
9
10
PWM
11
12
VR_GND
13
VR_GND
14
VR_GND
15
16
17
GND
18
LVDS_B2+
19
LVDS_B2-
20
LVDS_B1+
21
LVDS_B1-
22
LVDS_B0+
23
LVDS_B0-
24
GND
25
26
27
GND
28
LVDS_A2+
29
LVDS_A2-
30
LVDS_A1+
31
LVDS_A1-
32
LVDS_A0+
33
LVDS_A0-
EDID_DATA
EDID_CLK
V_EDID
LCD_VDD
LCD_VDD
CONNTST
1 2
R159 2.2K_0402_5%~DR159 2.2K_0402_5%~D
1 2
R160 2.2K_0402_5%~DR160 2.2K_0402_5%~D
BIST
LDDC_DATA_SW
34
LDDC_CLK_SW
35
LCD_TST
36
37
38
39
40
LDDC_CLK_SW
LDDC_DATA_SW
DISP_ON
BIA_PWM_LVDS
LVDS_CBL_DET#
BATT_WHITE_LED <44>
BATT_YELLOW_LED <44>
BREATH_WHITE_LED <44>
1 2
C246
C246
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
SW_LVDS_BCLK+ <23>
SW_LVDS_BCLK- <23>
SW_LVDS_B2+ <23>
SW_LVDS_B2- <23>
SW_LVDS_B1+ <23>
SW_LVDS_B1- <23>
SW_LVDS_B0+ <23>
SW_LVDS_B0- <23>
SW_LVDS_ACLK+ <23>
SW_LVDS_ACLK- <23>
SW_LVDS_A2+ <23>
SW_LVDS_A2- <23>
SW_LVDS_A1+ <23>
SW_LVDS_A1- <23>
SW_LVDS_A0+ <23>
SW_LVDS_A0- <23>
LDDC_DATA_SW <23>
LDDC_CLK_SW <23>
LCD_TST <40>
+3.3V_RUN
+LCDVDD
LVDS_CBL_DET# <17>
Place near to JLVDS1
4
+BL_PWR_SRC
www.qdzbwx.com
BIA_PWM_LVDS_RBIA_PWM_LVDS
1 2
0_0603_5%
0_0603_5%
RE9
@ RE9
@
DISP_ON
10K_0402_5%~D
10K_0402_5%~D
R1137
R1137
12
100K_0402_5%~D
100K_0402_5%~D
12
R1138
R1138
3
LCD Power
ENVDD_PCH<16,40>
LCD_VCC_TEST_EN<40>
ENVDD_GPU<47>
D66 RB751V-40GTE-17_SOD323-2~DD66 RB751V-40GTE-17_SOD323-2~D
D63
D63
D68 RB751V-40GTE-17_SOD323-2~DD68 RB751V-40GTE-17_SOD323-2~D
D67 RB751V-40GTE-17_SOD323-2~DD67 RB751V-40GTE-17_SOD323-2~D
D64 RB751V-40GTE-17_SOD323-2~DD64 RB751V-40GTE-17_SOD323-2~D
D69 RB751V-40GTE-17_SOD323-2~DD69 RB751V-40GTE-17_SOD323-2~D
@ U93
@
4
U93
21
DGPU_SESECT#
+3.3V_RUN
1
OE#
A2Y
21
21
21
21
21
5
P
G
74AHCT1G125GW_SOT353-5
74AHCT1G125GW_SOT353-5
3
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
D53
D53
RB751V-40GTE-17_SOD323-2~D
RB751V-40GTE-17_SOD323-2~D
2 1
D6
D6
2
1
3
BAT54CW_SOT323-3~D
BAT54CW_SOT323-3~D
BIA_PWM_PCH <16>
BIA_PWM_GPU <47>
BIA_PWM_EC <41>
PANEL_BKEN_PCH <16>
PANEL_BKEN_DGPU <47>
PANEL_BKEN_EC <40>
2
EN_LCDPWR
+LCDVDD
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
Q19A
Q19A
+15V_ALW +3.3V_ALW
+LCDVDD
12
R412
R412
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
3
Q19B
Q19B
4
FDC654P-G_SSOT-6~D
FDC654P-G_SSOT-6~D
S
S
4 5
PWR_SRC_ON
EN_INVPWR
470_0402_5%~D
470_0402_5%~D
12
R413
R413
61
2
2
40mil
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
C297
C297
2
EN_INVPWR<41>
+15V_ALW
100K_0402_5%~D
100K_0402_5%~D
12
R414
R414
5
13
Q20
Q20
PDTC124EU_SC70-3~D
PDTC124EU_SC70-3~D
+PWR_SRC
12
R422
R422
100K_0402_5%~D
100K_0402_5%~D
1 2
R423 47K_0402_5%~DR423 47K_0402_5%~D
Panel backlight power control by EC
Q18
Q18
SI3456DDV-T1-GE3_TSOP6~D
SI3456DDV-T1-GE3_TSOP6~D
D
D
S
S
4 5
G
G
3
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
1
C293
C293
2
Q21
Q21
D
D
6
2
1
G
G
3
Q22
Q22
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
D
S
D
S
1 3
G
G
2
1
6
2
1
40mil
1
2
1
2
+BL_PWR_SRC
C296
C296
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
C292
C292
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
FDC654P: P CHANNAL
CONN@
CONN@
JCAM1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B B
1
C298
C298
2
Close to JLVDS1 of 42,43 pins
+CAMERA_VDD
A A
Webcam PWR CTRL
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C299
C299
2
CCD_OFF<40>
For Webcam
10U_0805_10V4Z~D
10U_0805_10V4Z~D
1
C300
C300
2
CCD_OFF
2
G
G
5
Q23
12
R429
R429
100K_0402_5%~D
100K_0402_5%~D
13
D
D
Q24
Q24
S
S
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
Q23
PMV45EN_SOT23-3~D
PMV45EN_SOT23-3~D
+15V_ALW
+3.3V_RUN+LCDVDD
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
Close to JLVDS1.41
D
S
D
S
13
G
G
2
1
2
1
C303
C303
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
2
C243
C243
+3.3V_RUN
C301
C301
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
USBP12+<17>
USBP12-<17>
USBP12_D-
USBP12_D+
4
CAM_MIC_CBL_DET#<17>
DMIC_CLK<30>
DMIC0<30>
USBP12- USBP12_D-
@D75
@
2
3
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
D75
USBP12_D+
USBP12_D-
+CAMERA_VDD
D8
D8
@
@
2 1
2 1
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
@L10
@
DLW21SN121SQ2L_4P~D
DLW21SN121SQ2L_4P~D
1
4
R427 0_0402_5%~DR427 0_0402_5%~D
R428 0_0402_5%~DR428 0_0402_5%~D
1
D7
D7
@
@
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
L10
1
4
1 2
1 2
JCAM1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
G1
10
G2
JST_BM08B-SRSS-TB1-LF-SN~D
JST_BM08B-SRSS-TB1-LF-SN~D
2
2
3
3
USBP12_D+USBP12+
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
12
R431
R431
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
5
61
Q125A
Q125A
TOUCH_SCREEN_PD#<41>
2
Touch Screen Connector
3
+5V_TSP +5V_RUN
+15V_ALW
12
3
4
R430
R430
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
R1001 0_0603_5%~D@ R1001 0_0603_5%~D@
Q125B
Q125B
2
1 2
PMV45EN_SOT23-3~D
PMV45EN_SOT23-3~D
D
S
D
S
13
Q32
Q32
G
G
2
1
C304
C304
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
2
1
2
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
C306
C306
E3_PAID_TS_DET#<18>
USBP13_D-
USBP13_D+
D74
@D74
@
2
3
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
Place close JTCH1
USBP13+<17>
USBP13-<17>
1
4
DLW21SN121SQ2L_4P~D
DLW21SN121SQ2L_4P~D
RE3 0_0402_5%~DRE3 0_0402_5%~D
RE4 0_0402_5%~DRE4 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
SCHEMATICS,MB A6561
401931
401931
401931
LE1
@LE1
@
1
4
1 2
1 2
+5V_TSP
1
C302
C302
2
USBP13_DUSBP13_D+
1
2
3
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
2
3
CONN@
CONN@
JTCH1
JTCH1
1
1
2
2
3
3
4
4
5
5
6
6
7
Shield
8
Shield
MOLEX_48226-0611
MOLEX_48226-0611
USBP13_D+
USBP13_D-
24 77Thursday, January 13, 2011
24 77Thursday, January 13, 2011
24 77Thursday, January 13, 2011
of
of
of
B
B
B
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