Page 1
A
Vinafix.com
COMPAL CONFIDENTIAL
B
C
D
E
1 1
MODEL NAME : ADM60
PCB NO : DAA000AD000
BOM P/N : 4319XY31L01/L02
Park City 12" UMA
Skylake U
2 2
@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
3 3
CONN@ : Connector Component
2015-09-25
REV : 1.0 (A00)
X76@ : SATA REDRIVER OPTION
MB PCB
Part Number
DAA000AD000
4 4
COPYRIGHT 2015
ALL RIGHT RESERVED
REV: A00
PWB: 6N3K7
Description
PCB 1DK LA-C621P REV0 MB
Layout Dell logo
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-C621P
LA-C621P
LA-C621P
1 60Thursday, September 24, 2015
1 60Thursday, September 24, 2015
1 60Thursday, September 24, 2015
E
1.0
1.0
1.0
Page 2
A
Vinafix.com
B
C
D
E
Reverse Type
Block Diagram
Memory BUS (DDR4)
2133MHz
1 1
EDP CONN
VGA CONN
P25
DOCKING
CONN
2 2
P38
P26
VGA Switch
P25
VGA
DP
DP
SYNATICS
VMM3320
DAI
LAN
SATA1
DOCK_USB2.0[5]
DOCK_USB2.0[6]
DOCK_USB3.0[5]
SD4.0
eDP Lane x 2
HDMI 1.4b
CONN
P24
To M2 WiGig card
Card reader
RTS5250
DP DeMUX
PS8338
WIGIG DP
P23
P28P28
P22
DDI[1]
DDI[2]
PCIE[10]
SKYLAKE_U MCP
SPI
PAGE 6~19
SATA[2]/PCIE[11],[12]
USB2.0[1]
USB
HD Audio I/F
SATA[0]/PCIE[7]
PI5USB2544
USB POWER SHARE
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
USB2.0[1]_PS
P36
HDA Codec
ALC3235
USB2.0[9]
USB2.0[2]
USB3.0[1]
USB2.0[4]
USB3.0[4]
USB2.0[3]
USB3.0[3]
P30
LCD Touch
P26
Camera
P26
USB3.0 Conn
PS(RIGHT)
USB3.0 Conn
(REAR LEFT)
USB3.0 Conn
(LEFT)
INT.Speaker
Universal Jack
P30
P30
Trough eDP Cable
P36
P37
P37
Dig. MIC
W25Q128FVSIQ
PCIE[9] PCIE[5]
PCIE[3]
PCIE[6]
LPC
W25Q64CVSSIQ
3 3
Intel Jacksonville
I219LM
Transformer
P27
P27
M.2,3042 Key B
WWAN/LTE/HCA
P29
USB2.0[10]
USB3.0[5]
M.2,3030 Key A
WLAN+BT/WIGIG
USB2.0[8]
WIGIG_DP
SMSC SIO
P29 P31
ECE5048
BC BUS
TPM2.0
NPCT650JAAYX
KB/TP CONN
SMSC KBC
P39
P33
P8
P8
SATA REPEATER
P42
SATA/PCIE REPEATER X1
PS8555
P34
SATA/PCIE REPEATER X1
PS8555
P34
Spindle
HDD Conn
Key M
HDD Conn
P35
P42
reserve PCIE signal for SATA express HDD
MEC5085
RJ45
P27
P32
FAN CONN
P32
Trough eDP Cable
LID SWITCH
LED/B
USH CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
P33
P14
P11
DC/DC Interface
4 4
Smart Card
A
TDA8034HN
RFID/NFC
Fingerprint
CONN
SPI
SPI
USH TPM1.2
BCM58102
B
USB2.0[7]
USH board
P30
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
POWER ON/OFF
SW & LED
Block diagram
Block diagram
Block diagram
LA-C621P
LA-C621P
LA-C621P
E
P41
P40
1.0
1.0
2 60Thursday, September 24, 2015
2 60Thursday, September 24, 2015
2 60Thursday, September 24, 2015
1.0
Page 3
5
Vinafix.com
4
3
2
1
POWER STATES
S
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFL
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
(SOFT OFF) / M-OFF
S5
Signal
P
SLP
L
S3#
S4#
HIGH
HIGH HIGH
LOW HIGH HIGH
LOW
LOW
W HIGHLOW
O
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
SLP
A
#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
O
FF
OFF
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-6
PM TABLE
C C
power
plane
State
S0
+5V_ALW
+3.3V_ALW
+3.3V_ALW_DSW
+3.3V_ALW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
+3.3V_SUS
+1.0V_VCCST
+2.5V_MEM
ON ON
+5V_RUN
+3.3V_RUN
+
0.6V_DDR_VTT
+1.5V_RUN
(M-OFF)
+3.3V_M +3.3V_M
ON
+VCC_CORE
+VCC_GT
+1.0VS_VCCIO
+VCC_SA
ON
SSIC
SSIC-1
SSIC-2
PCIE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
PCIE-7
PCIE-8
PCIE-9
PCIE-10
PCIE-11
PCIE-12
SATA
SATA-0
SATA-1
SATA-1*
SATA-2
JUSB3-->Right
EDOCK PORT1
JUSB1-->LEFT
JUSB2-->Rear LEFT
M2 3042(WWAN)USB3.0-5
NA
M.2 3042(HCA or QCA LTE)
NA
M.2 3030(WLAN)
M.2 3030(WIGIG)
HDD SATA
EDOCK E-SATA
LOM
Card Reader
M.2 Socket 3 (Key M)
(PCIex2 or SATA)
USB PORT#DESTINATION
USH
DESTINATION
1
2
3
4
5
6
7
8
9
10
JUSB1-->Right
Camera
JUSB2-->LEFT
JUSB3-->Rear LEFT
EDOCK PORT1
EDOCK PORT2
USH
M.2 304230(BT)
Touch Screen
M2 3042(WWAN)
0
1
BIO
NA
Check
B B
A A
S3
S5 S4/AC
S5 S4/AC doesn't exist
ON
ON
OFF
OFFOFF
OFFON
OFF
OF
F
ON
ON
OFF
OFF
OFFOFF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-C621P
LA-C621P
LA-C621P
3 60Thursday, September 24, 2015
3 60Thursday, September 24, 2015
3 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 4
5
Vinafix.com
RT8207M
U201)
(P
ADAPTER
D D
CHARGER
BQ24777
(PU801)
+PWR_SRC
BATTERY
C C
ISL95857
(PU602)
SYX198D
(PU301)
T
PS62134A
(PU401)
HUB_LP_EN
PS62134B
T
(PU402)
SYX198C
(PU100)
SYX198B
(PU100)
AO6405
(QV1)
SIO_SLP_S4#
SIO_SLP_SUS#
ALWON
4
1.2V_MEM
+
RUN_ON
TPS22961
(UV28)
SIO_SLP_SUS#
ALWON
+1.0V_PRIM
+1.0VS_VCCIO
+1.0V_RUN_VMM
+1.0V_PRIM_CORE
+5V_ALW
5V_ALW2
+
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
LDOIN
RT8207
U201)
(P
3
0.675_DDR_VTT_ON
TPS22961
(UZ20)
TPS22961
(UZ19)
TPS22961
(UZ21)
TPS22967
(UZ23)
EM5209
(U
Z4)
EM5209
(UZ5)
PI5USB2544
(UI3)
SY6288
(UI1)
SY6288
(UI2)
SY8032A
(PU501)
EM5209
(UZ2)
+0.6V_DDR_VTT
MPHYP_PWR_EN
SIO_SLP_S3#
SIO_SLP_S4#
3.3V_HDD_EN
RUN_ON
AUD_PWR_EN
USB_PWR_EN1#
USB_PWR_EN2#
SIO_SLP_SUS#
SIO_SLP_LAN#
3.3V_WWAN_EN
@SIO_SLP_WLAN#
+5V_HDD
+5V_RUN
+5V_RUN_AUDIO
USB_PWR_SHR_VB US_EN
+1.0V_MPHYGT
+1.0V_VCCSTG
+1.0V_VCCST
+USB_LEFT_PWR
+USB_REAR_PWR
+1.8V_PRIM
+3.3V_LAN
+3.3V_WWAN
2
+5V_USB_CHG_PWR
AP7175SP
(PU1500)
SIO_SLP_S4#
1
CPU PWR
PCH PWR
GPU PWR
Peripheral Device PWR
+2.5V_MEM
IMVP_VR_ON
B B
V
CC_SA
A A
IMVP_VR_ON
IMVP_VR_ON
+BL_PWR_SRC
+VCC_GT+
+VCC_CORE
5
EN_INVPWR
EM5209
(UZ3)
EM5209
(UZ5)
TPS22967
(UZ8)
EM5209
(UZ4)
TPS22967
(UZ18)
AP2821
(U
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
V24)
@SIO_SLP_WLAN#
ENVCC_PCH
3
AUX_EN_WOWL
RUN_ON
AUD_PWR_EN
A_ON
SIO_SLP_SUS#
@PCH_ALW_ON
CV2_ON
+3.3V_WLAN
+3.3V_RUN
+3.3V_RUN_AUDIO
+3.3V_M
+3.3V_ALW_PCH
+3.3V_CV2
+LCDVDD
USH/B
LP2301
(QV8)
AP7175SP
(P
U502)
P2301A
L
(QZ1)
2
3.3V_TS_EN
+3.3V_RUN
3.3V_CAM_EN#
+3V_TSP
+1.5V_RUN
+3.3V_CAM
+3.3V_HDD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-C621P
LA-C621P
LA-C621P
1
1.0
1.0
4 60Thursday, September 24, 2015
4 60Thursday, September 24, 2015
4 60Thursday, September 24, 2015
1.0
Page 5
5
Vinafix.com
B4
A3
B5
A4
EM_SMBCLK
M
MEM_SMBDATA
SML0_SMBCLK
ML0_SMBDATA
S
1K
1K
DOCK_SMB_CLK
D
OCK_SMB_DAT
+3.3V_ALW_PCH
R7
R8
D D
SKL-U
R9
W2
V3W
3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
499
499
4
1K
1K
+3.3V_ALW_PCH
2N7002
N7002
2
+3.3V_ALW_PCH
28
1
3
LOM
3
2
1
2.2K
2.2K
+3.3V_RUN
202
200
202
200
DIMMA
DIMMB
53
5
1
XDP
2.2K
2.2K
+3.3V_ALW
1
129
27
Dock
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
@2.2K
@2.2K
A50
53
B
USH_SMBCLK
USH_SMBDAT
B B
MEC 5085
1E
1E
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
7
6
BATTERY
CONN
2.2K
2.2K
+3.3V_CV2
M9
L9
USH
USH/B
A49
2B
B52
2B
B50
A47
B7
A7
B48
B
49
CHARGER_SMBCLK
HARGER_SMBDAT
C
GPU_SMBDAT
GPU_SMBCLK
1G
1G
A A
2D
2D
2A
2A
5
0K
1
10K
2.2K
2.2K
4
+3.3V_ALW
+3.3V_RUN
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-C621P
LA-C621P
LA-C621P
5 60Thursday, September 24, 2015
5 60Thursday, September 24, 2015
5 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 6
5
Vinafix.com
4
3
2
1
+3.3V_RUN
CPU_DP1_CTRL_CLK
RC175 2.2K_0402_5%
RC178 2.2K_0402_5%
D D
RC176 2.2K_0402_5%
RC177 2.2K_0402_5%
C C
B B
12
CPU_DP1_CTRL_DATA
12
CPU_DP2_CTRL_CLK
12
CPU_DP2_CTRL_DATA
12
+1.0VS_VCCIO
CPU_DP1_N0<22>
CPU_DP1_P0<22>
CPU_DP1_N1<22>
CPU_DP1_P1<22>
CPU_DP1_N2<22>
CPU_DP1_P2<22>
CPU_DP1_N3<22>
CPU_DP1_P3<22>
CPU_DP2_N0<23>
CPU_DP2_P0<23>
CPU_DP2_N1<23>
CPU_DP2_P1<23>
CPU_DP2_N2<23>
CPU_DP2_P2<23>
CPU_DP2_N3<23>
CPU_DP2_P3<23>
CPU_DP1_CTRL_CLK<22>
CPU_DP1_CTRL_DATA<22> CPU_DP1_HPD <22>
CPU_DP2_CTRL_CLK<23>
CPU_DP2_CTRL_DATA<23>
@
T120
PAD~D
1 2
RC2 24.9_0402_1%
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
GPP_E23 CPU_DP1_HPD
EDP_COMP
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL-U_BGA1356
SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0
UC1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL-U_BGA1356
SKL-U
DDI
DISPLAY SIDEBANDS
SKL_ULT
EDP
1 OF 20
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
CSI2_COMP
RC3
EMMC_RCOMP
EDP_TXN0 <26>
EDP_TXP0 <26>
EDP_TXN1 <26>
EDP_TXP1 <26>
CPU_DP1_AUXN
CPU_DP1_AUXP
CPU_DP3_AUXN
CPU_DP3_AUXP
CPU_DP2_HPD <23>
EDP_HPD <26>
PANEL_BKLEN <26>
EDP_BIA_PWM <26>
ENVDD_PCH <26,32>
1 2
100_0402_1%
1 2
RC4 200_0402_1%
Support QHD
EDP_AUXN <26>
EDP_AUXP <26>
CPU_DP2_AUXN <23>
CPU_DP2_AUXP <23>
@
T1
PAD~D
@
T2
PAD~D
CPU_DP1_AUXN
CPU_DP2_AUXN
CPU_DP2_AUXP
CPU_DP1_AUXP
EDP_HPD
CPU_DP2_HPD
+3.3V_RUN
12
RC179100K_0402_5%
12
RC181100K_0402_5%
12
RC182100K_0402_5%
12
RC180100K_0402_5%
12
RC1100K_0402_5%
12
@
RC312100K_0402_5%
12
RC242100K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (1/14)
CPU (1/14)
CPU (1/14)
LA-C621P
LA-C621P
LA-C621P
6 60Thursday, September 24, 2015
6 60Thursday, September 24, 2015
6 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 7
5
Vinafix.com
4
DDR_A_DQS#[0..7]<20>
DDR_A_D[0..63]<20>
DDR_A_DQS[0..7]<20>
DDR_A_MA[0..16]<20>
3
2
1
D D
DDR4, Ballout for side by side(Non-Interleave)
UC1B
DDR_A_D0
AL71
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
C C
B B
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
SKL-U
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]
DDR0_WE#/DDR0_CA B[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
DDR_B_DQS#[0..7]<21>
DDR_B_D[0..63]<21>
DDR_B_DQS[0..7]<21>
DDR_B_MA[0..16]<21>
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2 OF 20
DDR_A_CLK#0
AU53
DDR_A_CLK0
AT53
DDR_A_CLK#1
AU55
DDR_A_CLK1
AT55
DDR_A_CKE0
BA56
DDR_A_CKE1
BB56
DDR_A_CKE2
AW56
DDR_A_CKE3
AY56
DDR_A_CS#0
AU45
DDR_A_CS#1
AU43
DDR_A_ODT0
AT45
DDR_A_ODT1 DDR_B_ODT0
AT43
DDR_A_MA5
BA51
DDR_A_MA9
BB54
DDR_A_MA6
BA52
DDR_A_MA8
AY52
DDR_A_MA7
AW52
DDR_A_BG0
AY55
DDR_A_MA12
AW54
DDR_A_MA11
BA54
DDR_A_ACT#
BA55
DDR_A_BG1
AY54
DDR_A_MA13
AU46
DDR_A_MA15
AU48
DDR_A_MA14 DDR_B_MA15
AT46
DDR_A_MA16
AU50
DDR_A_BA0
AU52
DDR_A_MA2
AY51
DDR_A_BA1
AT48
DDR_A_MA10
AT50
DDR_A_MA1
BB50
DDR_A_MA0
AY50
DDR_A_MA3
BA50
DDR_A_MA4
BB52
DDR_A_DQS#0
AM70
DDR_A_DQS0
AM69
DDR_A_DQS#1
AT69
DDR_A_DQS1
AT70
DDR_A_DQS#4
BA64
DDR_A_DQS4
AY64
DDR_A_DQS#5
AY60
DDR_A_DQS5
BA60
DDR_B_DQS#0
BA38
DDR_B_DQS0
AY38
DDR_B_DQS#1
AY34
DDR_B_DQS1
BA34
DDR_B_DQS#4
BA30
DDR_B_DQS4
AY30
DDR_B_DQS#5
AY26
DDR_B_DQS5
BA26
DDR_A_ALERT#
AW50
DDR_A_PARITY
AT52
AY67
+DDR_VREF_A_DQ
AY68
BA67
AW67
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
DDR_A_CLK#1 <20>
DDR_A_CLK1 <20>
DDR_A_CKE0 <20>
DDR_A_CKE1 <20>
@
PAD~D
@
PAD~D
DDR_A_CS#0 <20>
DDR_A_CS#1 <20>
DDR_A_ODT0 <20>
DDR_A_ODT1 <20>
Check ODT schematic 0918
DDR_A_BG0 <20>
DDR_A_ACT# <20>
DDR_A_BG1 <20>
DDR_A_BA0 <20>
DDR_A_BA1 <20>
DDR0_PAR,DDR0_ALERT# for DDR4
DDR_A_ALERT# <20>
+DDR_VREF_CA
+DDR_VREF_B_DQ
DDR_VTT_CTRL <20>
PAD~D
@
T132
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
T3
T4
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL-U_BGA1356
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]
DDR1_WE#/DDR1_CA B[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DRAM_RESET#
DDR_RCOMP[0]
DDR CH - B
DDR_RCOMP[1]
DDR_RCOMP[2]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
3 OF 20
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CKE2
DDR_B_CKE3
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR_B_CLK#0 <21>
DDR_B_CLK#1 <21>
DDR_B_CLK0 <21>
DDR_B_CLK1 <21>
DDR_B_CKE0 <21>
DDR_B_CKE1 <21>
DDR_B_CS#0 <21>
DDR_B_CS#1 <21>
DDR_B_ODT0 <21>
DDR_B_ODT1 <21>
DDR_B_BG0 <21>
DDR_B_ACT# <21>
DDR_B_BG1 <21>
DDR_B_BA0 <21>
DDR_B_BA1 <21>
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_ALERT# <21>DDR_A_PARITY <20>
DDR_B_PARITY <21>
DDR_DRAMRST# <20>
@
T5
PAD~D
@
T6
PAD~D
C
heck ODT schematic 0918
DDR4 COMPENSATION SIGNALS
A A
5
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
1 2
RC5 121_0402_1%
1 2
RC6 80.6_0402_1%
1 2
RC7 100_0402_1%
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/14)
CPU (2/14)
CPU (2/14)
LA-C621P
LA-C621P
LA-C621P
7 60Thursday, September 24, 2015
7 60Thursday, September 24, 2015
7 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 8
5
Vinafix.com
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
1 2
PCH_SPI_DO_XDP<14>
PCH_SPI_DO2_XDP<14>
D D
+3.3V_RUN
10K_0402_5%
12
RC267@
10K_0402_5%
12
RC268
DIMM Detect
HIGH
LOW
C C
PCH_SPI_CLK_1_R PCH _SPI_CLK_0_R
33_0402_5%
1 2
1 2
B B
A A
RC10 1K_0402_1%
RC11 1K_0402_1%
ONE_DIMM#
1 DIMM
2 DIMM
RC28
@EMC@
33P_0402_50V8J
CC7
@EMC@
1 2
PCH_SPI_CS#2<33>
+3.3V_RUN
12
SIO_RCIN#<32>
+3.3V_RUN
33_0402_5%
RC29
@EMC@
1 2
33P_0402_50V8J
CC8
@EMC@
1 2
9/5 MOW
Option 1: Implement a 1 kOhm pull-down resistor on the signal and de-populate the
required 1 kOhm pull-up resistor. In this case, customers must ensure that the SPI
flash device on the platform has HOLD functionality disabled by default.
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y platforms
with ES and SKL S/H platforms with pre-ES1/ES1 samples.
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
MEDIACARD_IRQ#<28>
PCH_CL_DATA1<29>
RC13
10K_0402_5%
IRQ_SERIRQ<31,32>
RC21 10K_0402_1%
+3.3V_SPI
@
@
@
@
RC37 0_0402_5%
RC39 33_0402_5%
RC42 0_0402_5%
@
RC43 33_0402_5%
@
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
1 2
1 2
1 2
ONE_DIMM#
PCH_SPI_D2_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
TPM_PIRQ#<33>
FFS_INT2<42>
PCH_CL_CLK1<29>
PCH_CL_RST1#<29>
1 2
RC30 1K_0402_5%
RC31 1K_0402_5%
RC316 1K_0402_5%
1 2
1 2
1 2
1 2
4
UC1E
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
SKL-U_BGA1356
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
SPI - FLASH
SPI - TOUCH
C LINK
PCH_SPI_D1_R1<33>
PCH_SPI_D0_R1<33>
PCH_SPI_CLK_R1<33>
128Mb Flash ROM
UC5
1
2
3
4
W25Q128FVSIQ_SO8
64Mb Flash ROM
UC6
1
2
3
4
W25Q64FVSSIQ_SO8
/CS
DO(IO1)
/WP(IO2)
GND
@
/CS
DO(IO1)
/WP(IO2)
GND
SKL-U
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
PCH_SPI_CLK_R1
PCH_SPI_D0_R1
PCH_SPI_D1_R1
VCC
/HOLD(IO3)
CLK
DI(IO0)
VCC
/HOLD(IO3)
CLK
DI(IO0)
SMBUS, SMLINK
LPC
GPP_A14/SUS_STAT#/ESPI_RESET#
SOFTWARE TAA
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
RPC2
@
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
+3.3V_SPI
0.1U_0201_10V6K
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
0.1U_0201_10V6K
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
3
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
5 OF 20
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D3_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D0_1_R
PCH_SPI_D1_1_R
CC9
1 2
@
CC10
1 2
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
+3.3V_SPI
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
GPP_C5
SML1_SMBCLK
SML1_SMBDATA
GPP_B23
SUS_STAT#
PCI_CLK_LPC0
PCI_CLK_LPC1
CLKRUN# <31,32>
RC32 0_0402_5%
@
RC33 0_0402_5%
RC34 0_0402_5%
RC35 0_0402_5%
RC36 0_0402_5%
RC38 0_0402_5%
RC40 0_0402_5%
+3.3V_ALW_PCH
+3.3V_M
@
RC41 0_0402_5%
SML0_SMBCLK <27>
SML0_SMBDATA <27>
SML1_SMBCLK <32>
SML1_SMBDATA <32>
LPC_LAD0 <31,32>
LPC_LAD1 <31,32>
LPC_LAD2 <31,32>
LPC_LAD3 <31,32>
LPC_LFRAME# <31,32>
Reserve
RC16EMC@ 22_0402_5%
RC18EMC@ 22_0402_5%
RC22EMC@ 22_0402_5%
RC24EMC@ 22_0402_5%
CLK_PCI_5048
27P_0402_50V8J
CLK_PCI_MEC
27P_0402_50V8J
CLK_PCI_LPDEBUG
27P_0402_50V8J
CLK_PCI_DOCK
27P_0402_50V8J
Reserve for RF
PCH_SPI_CS#1_R1
12
PCH_SPI_CS#1
PCH_SPI_D0_R1
12
PCH_SPI_D0
PCH_SPI_D1_R1
12
PCH_SPI_D1
PCH_SPI_CLK_R1
12
PCH_SPI_CLK
PCH_SPI_CS#0_R1
12
PCH_SPI_CS#0
PCH_SPI_D2_R1
12
PCH_SPI_D2
PCH_SPI_D3_R1
12
PCH_SPI_D3
@
RC289 0_0402_5%
RC276 0_0402_5%@
+3.3V_SPI_R
12
1 2
1 2
1 2
1 2
12
12
2
12
EMC@
CC3
12
EMC@
CC4
12
EMC@
CC5
12
EMC@
CC6
E-T_6705K-Y20N-00L
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSPI1
CONN@
MEM_SMBCLK
MEM_SMBDATA
DMN65D8LDW-7_SOT363-6
CLK_PCI_5048 <31>
CLK_PCI_MEC <32>
CLK_PCI_LPDEBUG <32>
CLK_PCI_DOCK < 38>
SIO_SLP_A#<11,32>
SIO_SLP_SUS#<11,17,18,32,41,46,47,48>
1
+3.3V_RUN
DDR_XDP_WAN_S MBDAT
DDR_XDP_WAN_S MBCLK
2
1
5
3 4
QC2B
6
DMN65D8LDW-7_SOT363-6
DDR_XDP_WAN_S MBCLK <14,20,21,42>
QC2A
DDR_XDP_WAN_S MBDAT <14,20,21,42>
SML0_SMBCLK
SML0_SMBDATA
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SUS_STAT#
SML0_SMBCLK
SML0_SMBDATA
CLKRUN#
FFS_INT2
PCH_SMB_ALERT#
R
eserve
@
RC19 499_0402_1%
@
RC20 499_0402_1%
1 2
1 2
1 2
RC12 1K_0402_5%
1 2
RC14 1K_0402_5%
1 2
RC15 1K_0402_5%
1 2
RC17 1K_0402_5%
1 2
RC26@ 10K_0402_5%
1 2
RC347 499_0402_1%
1 2
RC348 499_0402_1%
8/5 CKLT0.9
1 2
RC27 8.2K_0402_5%
1 2
RC322 10K_0402_5%
RC23 2.2K_0402_5%
TLS CONFIDENTIALITY
GPP_C5
HIGH
LOW(DEFAULT)
RC25 10K_0402_5%@
ENABLE
DISABLE
1 2
EC interface
HIGH
LOW(DEFAULT)
+3.3V_RUN +3.3V_ALW_PCH
150K_0402_5%
@
RC326
@
RC327 0_0402_5%
12
12
S
G
WEAK INTERNAL PD
1 2
GPP_B23 GPP_B 23_Q
@
RC339 0_0402_5%
RC340@ 0_0402_5%
ESPI
LPC
12
D
13
@
QC3
L2N7002WT1G_SC-70-3
2
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
12
+3.3V_ALW_PCH
150K_0402_5%
1 2
ENABLED
DIABLED
+3.3V_RUN
12
RC3182.2K_0402_5%
12
RC3192.2K_0402_5%
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_RUN
RC317
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/14)
CPU (3/14)
CPU (3/14)
LA-C621P
LA-C621P
LA-C621P
8 60Thursday, September 24, 2015
8 60Thursday, September 24, 2015
8 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 9
5
Vinafix.com
4
3
2
1
+3.3V_ALW_PCH
+3.3V_RUN
UC1F
LPSS ISH
AN8
3.3V_TP_EN
D D
C C
1 2
RC270 10K_0402_5%
1 2
RC282 100K_0402_5%
1 2
RC335 49.9K_0402_1%
@
1 2
RC336 49.9K_0402_1%
@
1 2
RC279 10K_0402_5%
1 2
RC292 10K_0402_5%
RC237 10K_0402_5%
+3.3V_ALW_PCH
1 2
RC283 10K_0402_5%
1 2
RC330 49.9K_0402_1%
1 2
RC331 49.9K_0402_1%
+3.3V_ALW_PCH
12
1 2
RC186 4.7K_0402_5%
@
R
eserve
TS_EN
LPSS_UART2_TXD
LPSS_UART2_RXD
AUD_PWR_EN
HOST_SD_WP#
SIO_EXT_SCI#
SIO_EXT_WAKE#
LPSS_UART2_RXD
LPSS_UART2_TXD
NRB_BIT
SIO_EXT_SCI#<32>
TS_EN<26>
HDD_EN<42>
UART0_TXD<32>
HOST_SD_WP#<28>
SIO_EXT_WAKE#<32>
I2C_1_SDA<39>
Reserve
I2C_1_SCL<39>
NRB_BIT
3.3V_TP_EN
LPSS_UART2_RXD
LPSS_UART2_TXD
Reserve
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKL-U_BGA1356
SKL-U
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA /I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_S CL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALER T#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
6 OF 20
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
DIMM_TYPE
CLKDET#
NON_DOCK
9/24: Reserve for embedded location ,refer Intel PDG 0.9
ISH_I2C2_SDA <29>
ISH_I2C2_SCL <29>
ISH_UART0_RXD <29>
ISH_UART0_TXD <29>
ISH_UART0_RTS# <29>
ISH_UART0_CTS# <29>
LCD_CBL_DET# <26>
@
T121
PAD~D
VMM3320_LPM_DIS <24>
KB_DET# <39>
AUD_PWR_EN <30>
IR_CAM_DET# <26>
WWAN
WLAN
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
Weak IPD
B B
+3.3V_ALW_PCH
12
RC184
@
8.2K_0402_5%
HDD_EN
No REBOOT
REBOOT ENABLE
+5V_ALW
LPSS_UART2_TXD
LPSS_UART2_RXD
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
ACES_50207-00471-P01
8/21
KB_DET#
LCD_CBL_DET#
IR_CAM_DET#
NON_DOCK
+3.3V_ALW_PCH
12
@
12
1 2
RC288 10K_0402_5%
1 2
RC287 100K_0402_5%
1 2
RC346 100K_0402_5%
1 2
RH359 100_0402_1%
@
RC341
10K_0402_5%
DIMM_TYPE
RC342
10K_0402_5%
HIGH
DIMM_TYPE
DDR3L
DR4LOW
D
+3.3V_RUN
BOOT BIOS Destination(Bit 10)
HIGH
LOW(DEFAULT)
LPC
SPI
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (4/14)
CPU (4/14)
CPU (4/14)
LA-C621P
LA-C621P
LA-C621P
9 60Thursday, September 24, 2015
9 60Thursday, September 24, 2015
9 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 10
5
Vinafix.com
4
3
2
1
UC1H
PCIE/USB3/SATA
D D
WWAN
WWAN --->
WLAN --->
WIGIG--->
C C
SATA HDD--->
E DOCK ESATA--->
10/100/1G LAN --->
Card Reader --->
SATA EXPRESS HDD --->
B B
USB3_PRX_DTX_N5<29>
USB3_PRX_DTX_P5<29>
USB3_PTX_DRX_N5<29>
USB3_PTX_DRX_P5<29>
PCIE_PRX_DTX_N3<29>
PCIE_PRX_DTX_P3<29>
PCIE_PTX_DRX_N3<29>
PCIE_PTX_DRX_P3<29>
PCIE_PRX_DTX_N5<29>
PCIE_PRX_DTX_P5<29>
PCIE_PTX_DRX_N5<29>
PCIE_PTX_DRX_P5<29>
PCIE_PRX_DTX_N6<29>
PCIE_PRX_DTX_P6<29>
PCIE_PTX_DRX_N6<29>
PCIE_PTX_DRX_P6<29>
SATA_PRX_DTX_N0<42>
SATA_PRX_DTX_P0<42>
SATA_PTX_DRX_N0<42>
SATA_PTX_DRX_P0<42>
SATA_PRX_DTX_N1<38>
SATA_PRX_DTX_P1<38>
SATA_PTX_DRX_N1<38>
SATA_PTX_DRX_P1<38>
PCIE_PRX_DTX_N9<27>
PCIE_PRX_DTX_P9<27>
PCIE_PTX_DRX_N9<27>
PCIE_PTX_DRX_P9<27>
PCIE_PRX_DTX_N10<28>
PCIE_PRX_DTX_P10<28>
PCIE_PTX_DRX_N10<28>
PCIE_PTX_DRX_P10<28>
1 2
RC45 100_0402_1%
PCIE_PRX_DTX_N11<34>
PCIE_PRX_DTX_P11<34>
PCIE_PTX_DRX_N11<34>
PCIE_PTX_DRX_P11<34>
PCIE_PRX_DTX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PTX_DRX_P12<34>
PCIE_RCOMPN
PCIE_RCOMPP
CPU_XDP_PRDY#<14>
CPU_XDP_PREQ#<14>
HDD_FALL_INT<42>
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL-U_BGA1356
SKL-U
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USBCOMP
USB_OC3#
SATAGP1
USB3_PRX_DTX_N1 <36>
USB3_PRX_DTX_P1 <36>
USB3_PTX_DRX_N1 <36>
USB3_PTX_DRX_P1 <36>
USB3_PRX_DTX_N2 <38>
USB3_PRX_DTX_P2 <38>
USB3_PTX_DRX_N2 <38>
USB3_PTX_DRX_P2 <38>
USB3_PRX_DTX_N3 <37>
USB3_PRX_DTX_P3 <37>
USB3_PTX_DRX_N3 <37>
USB3_PTX_DRX_P3 <37>
USB3_PRX_DTX_N4 <37>
USB3_PRX_DTX_P4 <37>
USB3_PTX_DRX_N4 <37>
USB3_PTX_DRX_P4 <37>
USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <26>
USB20_P2 <26>
USB20_N3 <37>
USB20_P3 <37>
USB20_N4 <37>
USB20_P4 <37>
USB20_N5 <38>
USB20_P5 <38>
USB20_N6 <38>
USB20_P6 <38>
USB20_N7 <33>
USB20_P7 <33>
USB20_N8 <29>
USB20_P8 <29>
USB20_N9 <26>
USB20_P9 <26>
USB20_N10 <29>
USB20_P10 <29>
1 2
RC44 113_0402_1%
@
1 2
RC337 0_0402_5%
1 2
RC338 1K_0402_5%
USB_OC0# <36>
USB_OC1# <37>
USB_OC2# <37>
R
eserve
HDD_DEVSLP <42>
M2_DEVSLP <35>
HDD_DET# <42>
Reserve
IFDET_SATA#_PCIE <34,35>
PCH_SATA_LED# <35,40>
-----> Ext USB3 Port 3 Charge(RIGHT)
-----> EDOCK
-----> Ext USB3 Port 1(LEFT)
-----> Ext USB3 Port 2(REAR LEFT)
-----> Ext USB Port 3 Charge(RIGHT)
-----> Camera
-----> Ext USB Port 1(LEFT)
-----> Ext USB Port 2(REAR LEFT)
-----> EDOCK PORT1
-----> EDOCK PORT2
-----> USH
-----> BT
-----> LCD Touch
-----> M2 3042(WWAN)
8/19 for layout routing change
USB_OC0#
USB_OC3#
USB_OC1#
USB_OC2#
HDD_FALL_INT
IFDET_SATA#_PCIE
PCH_SATA_LED#
HDD_DET#
SATAGP1
RPC3
4 5
3
6
2
7
1
8
10K_8P4R_5%
RPC4
4 5
3
6
2
7
1
8
10K_8P4R_5%
1 2
RC246 10K_0402_5%
CKLT0.9
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_ALW_PCH
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (5/14)
CPU (5/14)
CPU (5/14)
LA-C621P
LA-C621P
LA-C621P
10 60Thursday, September 24, 2015
10 60Thursday, September 24, 2015
10 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 11
5
Vinafix.com
CLK_PCIE_N0<29>
WWAN
D D
WLAN--->
WIGIG--->
SATA EXPRESS HDD--->
LAN--->
MMI --->
H_CPUPWRGD VCCST_PW RGD
100P_0402_50V8J
12
CC300EMC@
C C
+1.0V_VCCST
RC71 1K_0402_5%
+3.3V_ALW_PCH
RC74 10K_0402_5%@
10/6 depop, prevent singal step.
B B
100P_0402_50V8J
12
SD Request:place near CPU side
E
1 2
1 2
@
T9
PAD~D
VCCST_PWRGD<14,32>
RC215
POP
DE-POP
PCH_DPWROK PCH_RSMRST#_Q
0.01UF_0402_25V7K
12
1
CC266
A A
2
CLK_PCIE_P0<29>
CLKREQ_PCIE#0<29>
CLK_PCIE_N1<29>
CLK_PCIE_P1<29>
CLKREQ_PCIE#1<29>
CLK_PCIE_N2<29>
CLK_PCIE_P2<29>
CLKREQ_PCIE#2<29>
CLK_PCIE_N3<35>
CLK_PCIE_P3<35>
CLKREQ_PCIE#3<35>
CLK_PCIE_N4<27>
CLK_PCIE_P4<27>
CLKREQ_PCIE#4<27>
CLK_PCIE_N5<28>
CLK_PCIE_P5<28>
CLKREQ_PCIE#5<28>
CC301@EMC@
VCCST_PWRGD
ME_SUS_PWR_AC K
RC75 10K_0402_5 %
NO Support Deep sleep
Support Deep sleep
1 2
RC215 0_0402_5%
@
100K_0402_1%
RC220
1 2
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_DSW
+3.3V_RUN
RC189 10K_0402_5%
1 2
RC47 10K_0402_5 %
1 2
RC50 10K_0402_5 %
1 2
RC59 10K_0402_5 %
1 2
RC51 10K_0402_5 %
1 2
RC190 10K_0402_5%
PCH_PLTRST#
1 2
RC67 1K_0402_5%
1 2
RC323 10K_0402_5%
1 2
RC225@ 8.2K_0402_5%
PCH_RSMRST#_Q<14,39>
1 2
1 2
RC77 1K_0402_5%@
1 2
RC78 60.4_0402_1%
PCH_DPWROK<32> POWER_SW#_M B<32,40>
ME_SUS_PWR_AC K<32>
PCH_PCIE_WAKE#<31,32>
PM_LANPHY_ENABLE<27>
XDP_DBRESET#<14>
+3.3V_ALW_PCH
1
2
UC7
TC7SH08FU_SSOP5~D
PCH_PCIE_WAKE# SIO_SLP_LAN#
LAN_WAKE#
ME_RESET#
PCH_PLTRST#
SYS_RESET#
PCH_RSMRST#_Q
H_CPUPWRGDH_CPUPWRGD_R
VCCST_PWRGD_CPU
RESET_OUT#<14,32>
PCH_PWROK<49>
SUSACK#<32>
LAN_WAKE#<27,32>
3.3V_CAM_EN#<26>
1 2
RC311 10K_0402_5%
8/28 schematic review
XDP_DBRESET#
RC227@ 8.2K_0402_5%
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
5
4
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL-U_BGA1356
12
12
12
12
RC244 @0_0402_5%
12
RC600_0402_5%
12
RC325 @0_0402_5%
5
P
B
O
A
G
3
AN10
B5
AY17
A68
B65
B6
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
@
RC290 0_0402_5%
ME_RESET#
12
4
UC1J
RC610_0402_5%
@
RC62 @0_0402_5%
RC64 @0_0402_5%
@
PCH_PLTRST#_AND
4
12
RC65
@
100K_0402_5%
UC1K
GPP_B13/PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPW RDNACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD
SKL-U_BGA1356
1 2
+3.3V_RUN
5
1
B
2
A
3
CLOCK SIGNALS
PLTRST_VMM2320# <24>
PLTRST_LAN# <27>
PLTRST_5048# <31>
PCH_PLTRST#_EC <32>
PLTRST_TPM# <33>
PCH_PLTRST#_AND <28,29,33,35>
SYSTEM POWER MANAGEMENT
P
4
O
G
UC12@
74AHC1G09GW_TSSOP5
SKL_ULT
SKL-U
SYS_RESET#_R
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
GPP_B11/EXT_PWR_GATE#
1 2
RC224 1K_0402_5%
INTRUDER#
GPP_B2/VRALERT#
+3.3V_RUN
SYS_RESET#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SUSCLK
CLK_ITPXDP_N
F43
CLK_ITPXDP_P
E43
BA17
XTAL24_IN
E37
XTAL24_OUT
E35
XCLK_BIASREF
E42
PCH_RTCX1
AM18
PCH_RTCX2
AM20
AN18
SRTCRST#
AM16
PCH_RTCRST#
CMOS1 must take care short & touch risk on layout placement
8/21 can change to 10K for merge to RP
PCH_BATLOW#
AC_PRESENT
AT11
AP15
BA16
AY16
AN15
SLP_SUS#
AW15
SLP_LAN#
BB17
AN16
BA15
AY15
PCH_BATLOW#
AU13
AU11
PME#
AP16
INTRUDER#
AM10
AM11
VRALERT#
11 OF 20
12
RC291
@
10K_0402_5%
3
2
1 2
RC48 1K_0402_5%@
1 2
RC297 0_0402_5%@
1 2
RC298 0_0402_5%@
SUSCLK <29,35>
For Skylake pop RC52 and depop RC324
For Cannonlake depop RC52 and pop RC324
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
1 2
RC52 2.7K_0402_1%
1 2
@
RC324 59_0402_1%
@
@
SIO_SLP_S0# <17,33,47>
SIO_SLP_S3# <17,32,48>
SIO_SLP_S4# <17,32,45,54>
SIO_SLP_S5# <32>
1 2
RC56 20K_0402_5 %
1 2
CC24 1U_0402_6.3V6K
1 2
RC57 20K_0402_5 %
1 2
CC25 1U_0402_6.3V6K
1
1
2
SHORT PADS~D
@
CMOS1
1 2
RC344 10K_0402_5%
1 2
RC68 10K_0402_5%
1 2
RC72 8.2K_0402_5%
1 2
RC243 10K_0402_5%
SIO_SLP_SUS# <8,17,18,32,41,46,47,48>
SIO_SLP_LAN# <32,41>
SIO_SLP_WLAN# <31,41>
SIO_SLP_A# <8,32>
SIO_PWRBTN# <14,32>
AC_PRESENT <32>
PAD~D
MPHYP_PWR_EN <18>
co
nnect to VCCMPHYGTAON_1P0 enable pin
@
+3.3V_ALW
+3.3V_ALW_DSW
T115
CLK_ITPXDP_N_R <14>
CLK_ITPXDP_P_R <14>
+1.0V_CLK5
+RTC_CELL
2
+3.3V_ALW_PCH
INTRUDER#
VRALERT#
SLP_S0# for support connect stand by mode
8/21 CRB1.0 change to 0603 1/10W
2
1M_0402_1%
RC46
XTAL24_IN
XTAL24_OUT XTAL24_OUT_R
PCH_RTCX1
PCH_RTCX2
1 2
RC69 1M_0402_5%
1 2
@
RC73 10K_0402_5%
1 2
RC343 10K_0402_5%
1 2
1 2
@
RC295 0_0402_5%
For Skylake YC1 24MHz(50 Ohm ESR)
For Cannonlake YC1 38.4MHz(30 Ohm ESR)
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
RC54
10M_0402_5%
1 2
@
RC296 0_0402_5%
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW_DSW
+3.3V_ALW_DSW
SYS_RESET#
0.1U_0402_25V6
@EMC@
12
CC302
ESD Request:place near CPU side
1 2
+3.3V_ALW_PCH+3.3V_ALW
PCH_RTCX2_R
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
1
3
4
YC1
24MHZ_12PF_X3G024000DC1H
1
2
12
YC2
32.768KHZ 9PF10PPM 9H03200055
ESR MAX=50k ohm
CPU (6/14)
CPU (6/14)
CPU (6/14)
LA-C621P
LA-C621P
LA-C621P
1
CC21
1 2
15P_0402_50V8J
CC22
1 2
15P_0402_50V8J
CC23
12
5P_0402_50V8C
CC26
12
5P_0402_50V8C
JAPS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CONN@
ACES_50506-01841-P01
11 60Thursday, September 24, 2015
11 60Thursday, September 24, 2015
11 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 12
5
Vinafix.com
+1.0V_VCCST
8/21 DG0.9
@
RC79 49.9_0402_1%
RC80 1K_0402_5%
+1.0V_VCCSTG
/19 DG0.9
8
RC83 1K_0402_5%
+3.3V_RUN
D D
RC272 10K_0402_5%
10K_8P4R_5%
+3.3V_ALW_PCH
RC236 10K_0402_5%
C C
B B
1 2
1 2
1 2
1 2
RPC5
4 5
3
2
1
1 2
H_CATERR#
H_THERMTRIP#
H_PROCHOT#
TOUCH_SCREEN_PD#
6
CAM_MIC_CBL_DET#
7
CONTACTLESS_DET#
8
SIO_EXT_SMI#
HDA_SYNC_R<30>
HDA_BIT_CLK_R<30>
HDA_SDOUT_R<30>
22P_0402_50V8J
Close to RC93
CC27
HDA_RST#_R<30>
H_PROCHOT#<32,49,51>
H_THERMTRIP#<20,21,32>
1 2
RC92 33_0402_5%
1 2
RC93 33_0402_5%EMC@
1 2
RC94 33_0402_5%
ME_FWP
HDA_BIT_CLK_R
1
2
1 2
RC223 1K_0402_5%
RC95 33_0402_5%
8/19 DG0.9
1 2
RC84 499_0402_1%
TOUCH_SCREEN_PD#<26>
TOUCHPAD_INTR#<39>
TOUCH_SCREEN_DET#<26>
12
1 2
PECI_EC<32>
SIO_EXT_SMI#<32>
RC88
SPKR<30>
XDP_OBS0_R<14>
XDP_OBS1_R<14>
T10
T11
12
49.9_0402_1%
4
@
PAD~D
@
PAD~D
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
12
RC90
RC89
49.9_0402_1%
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0<30>
HDA_RST#
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#TOUCHPAD_INT R#
XDP_OBS2_R
XDP_OBS3_R
EOPIO_RCOMP
12
RC91
49.9_0402_1%
49.9_0402_1%
AW22
AW20
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
AT16
AU16
H66
H65
UC1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
SKL-U_BGA1356
UC1D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
SKL-U_BGA1356
AUDIO
CPU MISC
SKL-U
SKL-U
3
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
4 OF 20
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
CPU_XDP_TCLK
B61
CPU_XDP_TDI
D60
CPU_XDP_TDO
A61
CPU_XDP_TMS
C60
CPU_XDP_TRST#
B59
PCH_JTAG_TCK
B56
PCH_JTAG_TDI
D59
PCH_JTAG_TDO
A56
PCH_JTAG_TMS
C59
CPU_XDP_TRST#
C61
XDP_JTAGX
A59
RC87 1K_0402_5%@
@
RC328 0_0402_5%
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
1 2
7 OF 20
CPU_XDP_TCLK <1 4>
CPU_XDP_TDI <14>
CPU_XDP_TDO < 14>
CPU_XDP_TMS <14>
CPU_XDP_TRST# <14>
PCH_JTAG_TCK <14>
PCH_JTAG_TDI <14>
PCH_JTAG_TDO <14>
PCH_JTAG_TMS <14>
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
CPU_XDP_TCLK
12
CONTACTLESS_DET#
SD_RCOMP
+1.0V_VCCSTG
2
RC86 51_0402_5%@
CAM_MIC_CBL_DET# <26>
RC96 200_0402_1%
12
CONTACTLESS_DET# <33>
1 2
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.3V_ALW_PCH
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
PCH_JTAG_TDI
51_0402_5%
PCH_JTAG_TDO
100_0402_1%
PCH_JTAG_TMS
51_0402_5%
12
@
RC222
1K_0402_5%
+1.0V_VCCSTG
12
RC81
12
RC82
12
RC130
ME_FWPME_FWP_EC
ME_FWP
12
@
1
2
3
4
5
@
RC221 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
ME_FWP_EC<31>
SW1
A
B
C
G1
G2
SS3-CMFTQR9_3P
1
+3.3V_ALW_PCH +3.3V_ALW_PCH
1 2
RC183 8.2K_0402_5%@
TOP SWAP STRAP
A A
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
SPKR
RC187 4.7K_0402_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
1 2
HDA_SDOUT
DISABLE
ENABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (7/14)
CPU (7/14)
CPU (7/14)
LA-C621P
LA-C621P
LA-C621P
12 60Thursday, September 24, 2015
12 60Thursday, September 24, 2015
12 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 13
5
Vinafix.com
D D
4
3
2
1
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
CFG[0..19]<14>
C C
1 2
RC113 10K_0402_1%@
CFG0
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
+1.0V_PRIM_XDP
1 2
RC112 10K_0402_1%@
1 2
RC110 10K_0402_1%@
RC114 49.9_0402_1%
RC115 1.5K_0402_5%
ITP_PMODE<14>
CFG_RCOMP
12
ITP_PMODE
12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
Stall reset sequence
HIGH(DEFAULT)
LOW
B B
No stall(Normal Operation)
stall
1 2
RC109 1K_0402_5%
CFG4
@
T16
PAD~D
@
T17
PAD~D
eDP enable For Skylake RC120 depop
HIGH(DEFAULT)
LOW
Disabled
Enabled
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
UC1S
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL-U_BGA1356
RESERVED SIGNALS-1
SKL-U
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
AR56
AW71
AW70
AP56
C64
@
For Cannonlake RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
@
T12
PAD~D
@
T13
PAD~D
@
T14
PAD~D
@
T15
PAD~D
@
T128
PAD~D
@
T129
PAD~D
@
T130
PAD~D
@
T126
PAD~D
@
T127
PAD~D
@
T113
PAD~D
@
T114
PAD~D
1 2
RC120 100K_0402_5%
ZVM# for SKYLAKE-U 2+3e
1/5 2014WW52 MOW reserve to support
C
annonlake-U PCH compatibility
close UC1.U11/U12 and <400mil
1 2
RC313 0_0402_5%@
+1.0V_VCCST
+VCC_1P8+1.8V_PRIM
1
2
MSM# for SKYLAKE-U 2+3e
SPARE
SKL-U
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
F6
E3
C11
B11
A11
D12
C12
F52
UC1T
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
SKL-U_BGA1356
CC222
@
1U_0402_6.3V6K
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (8/14)
CPU (8/14)
CPU (8/14)
LA-C621P
LA-C621P
LA-C621P
13 60Thursday, September 24, 2015
13 60Thursday, September 24, 2015
13 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 14
CC29
Vinafix.com
5
+1.0V_PRIM_XDP
XDP_OBS0_R<12>
XDP_OBS1_R<12>
RC123 1K_0402_5%@
RC124
CXDP@ 1K_0402_5%
PCH_SPI_DO_XDP<8>
RESET_OUT#<11,32>
RC239 0_0402_5%
CXDP@
RC240 0_0402_5%
CXDP@
RC5 need to close to JCPU1
1 2
1 2
FIVR_EN
CFG0
RC217 0_0402_5%
@
RC126 1K_0402 _5%
@
RC128 0_0402_5%
CXDP@
RC129 0_0402_5%
@
DDR_XDP_WAN_S MBDAT<8,20,21,42>
DDR_XDP_WAN_S MBCLK<8,20,21,42>
CPU_XDP_PREQ#<10>
CPU_XDP_PRDY#<10>
1 2
1 2
1 2
1 2
1 2
1 2
PCH_JTAG_TCK<12>
CPU_XDP_TCLK<12>
CPU XDP
H_VCCST_PWRGD_XD P
SIO_PWRBTN#<11,32>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RESET_OUT#_R
CPU_XDP_TCLK
+1.0V_PRIM
1 2
RC216 0_0603_1%
@
+1.0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
@
CC28
1
1
2
2
D D
Place near
JXDP1
VCCST_PWRGD<11,32>
PCH_RSMRST#_Q<11,39>
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0
XDP_OBS1
CFG4
CFG5
CFG6
CFG7
FIVR_EN_R
4
XDP_PRSNT_PIN1
1 2
RC121 1K_0402_5%
1 2
RC122 0_0402_5%@
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
CXDP@
CFG3
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
TD0
TDI
+1.0V_PRIM_XDP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
ITP_PMODE
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
XDP_TMS
3
CLK_ITPXDP_P_R <11>
CLK_ITPXDP_N_R <11>
ITP_PMODE <13>
XDP_DBRESET# <11>
PCH_SPI_DO2_XDP <8>
2
CFG[0..19]<13>
+3.3V_RUN
CC30
1 2
0.1U_0201_10V6K
TDO_XDP
TDI_XDP
XDP_TMS
TRST#_XDP
RUNPWROK<31,32>
UC8
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
GND
GND PAD
1
3
1B
6
2B
8
3B
11
4B
7
15
CPU_XDP_TDO < 12>
CPU_XDP_TDI <12>
CPU_XDP_TMS <12>
CPU_XDP_TRST# <12>
+1.0VS_VCCIO
C C
B B
+1.0V_VCCST
+3.3V_RUN
+1.0V_PRIM_XDP
1 2
RC132 150_0402_5%
1 2
RC218 150_0402_5%
@
1 2
RC219 10K_0402_5%
@
1 2
RC137
1 2
RC138
@
FIVR_EN_R
FIVR_EN
FIVR_EN
XDP_DBRESET#
1K_0402_5%
CPU_XDP_PREQ#
51_0402_5%
CKLT0.9
+3.3V_ALW_PCH
0.1U_0402_25V6
CC33@
Place near JXDP1.47
12
RC133
1.5K_0402_5%
CXDP@
PCH_SPI_DO_XDP
RESET_OUT#_R
12
9/1 follow SPI PWR rail
Place near JXDP1.48
XDP_DBRESET#
CPU_XDP_TMS
51_0402_5%
+3.3V_ALW_DSW
0.1U_0402_25V6
CC32
CXDP@
12
SIO_PWRBTN#
12
12
E
DS0.7
1.5K_0402_5%
RC241
@
0.1U_0402_25V6
CC269
@
Place near JXDP1.41
CPU_XDP_TDI
51_0402_5%
CPU_XDP_TDO
100_0402_1%
CPU_XDP_TRST#
51_0402_5%
CPU_XDP_TCLK
51_0402_5%
XDP_TMS
1 2
@
RC228 0_0402_5%
TDI_XDP
1 2
@
RC229 0_0402_5%
TDO_XDP
1 2
@
RC230 0_0402_5%
12
12
12
12
12
RC131
RC134
RC135
RC136 CXDP@
RC139
+1.0V_VCCSTG
PCH_JTAG_TMS <12>
PCH_JTAG_TDI <12>
PCH_JTAG_TDO <12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (9/14)
CPU (9/14)
CPU (9/14)
LA-C621P
LA-C621P
LA-C621P
14 60Thursday, September 24, 2015
14 60Thursday, September 24, 2015
14 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 15
5
Vinafix.com
4
3
2
1
+VCC_CORE: 0.3~1.35V
D D
@
T122
PAD~D
@
T123
PAD~D
C C
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
+VCC_CORE +VCC_CORE
+VCC_CORE_G0
+VCC_CORE_G1
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
SKL-U_BGA1356
UC1L
SKL-U
CPU POWER 1 OF 4
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
12 OF 20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
VCCSENSE
VSSSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
+1.0V_VCCSTG_R
VIDSCLK <49>
+VCC_CORE
12
RC140
100_0402_1%
12
RC141
100_0402_1%
1 2
@
RC143 0_0603_5%
VCCSENSE <49>
VSSSENSE < 49>
+1.0V_VCCSTG
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
ESD Request
+VCC_CORE +1.2V_MEM
+1.0V_PRIM +VCC_CORE
CC282
CC283
CC284
CC285
CC286
CC287
1 2
1 2
1 2
1 2
1 2
1 2
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
22U_0603_6.3V6M@EMC@
+3.3V_RUN+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+1.2V_MEM+1.0V_PRIM
22U_0603_6.3V6M@EMC@
+3.3V_RUN+VCC_CORE
22U_0603_6.3V6M@EMC@
B B
8/21 CRB1.0 , DG0.9
SVID ALERT
VIDALERT_N<49>
SVID DATA
A A
VIDSOUT<49>
5
4
+1.0V_VCCST
12
+1.0V_VCCST
12
56_0402_1%
RC152
100_0402_1%
RC157
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
H_CPU_SVIDALRT#
12
RC153220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/14)
CPU (10/14)
CPU (10/14)
LA-C621P
LA-C621P
LA-C621P
15 60Thursday, September 24, 2015
15 60Thursday, September 24, 2015
15 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 16
5
Vinafix.com
4
3
2
1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
+VCC_GT +VCC_GT
D D
C C
+VCC_GT
12
RC161
100_0402_1%
VCC_GT_SENSE<49>
VSS_GT_SENSE<49>
B B
VCC_GT_SENSE
VSS_GT_SENSE
12
RC163
100_0402_1%
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKL-U_BGA1356
CPU POWER 2 OF 4
SKL-U
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GTUS
VCCGTX for SKYLAKE-U 2+3e
Reserve for soldering
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (11/14)
CPU (11/14)
CPU (11/14)
LA-C621P
LA-C621P
LA-C621P
16 60Thursday, September 24, 2015
16 60Thursday, September 24, 2015
16 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 17
5
Vinafix.com
4
3
2
1
+1.2V_MEM+1.2V_MEM_CPUCLK
1 2
@
RC231 0_0402_5%
D D
C C
BSC PSC
1
2
BSC
1
2
CC256
@
1U_0402_6.3V6K
1
1
1
CC174
CC175
2
2
@
@
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
2
1
2
2
CC254
CC257
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
CC176
2
10U_0402_6.3V6M
1
2
CC255
@
1U_0402_6.3V6K
+1.0V_VCCST
1
CC177
2
10U_0402_6.3V6M
CC294
22U_0603_6.3V6M
PSC
1
2
CC195
1U_0402_6.3V6K
1
CC178
2
10U_0402_6.3V6M
1
2
CC295
22U_0603_6.3V6M
+1.0V_VCCSTG
CC179
1
2
VDDQ: 8.45A
10U_0402_6.3V6M
CC296
22U_0603_6.3V6M
BSC
1
CC199
2
@
1
2
DG0.9
CC297
1U_0402_6.3V6K
10U_0402_6.3V6M
+VCC_SFR_OC
+1.2V_MEM_CPUCLK
BSC
1
CC194
2
@
1U_0402_6.3V6K
1
2
CC288
1U_0402_6.3V6K
+1.2V_MEM
1.35V in DDR3L,
1.2V in LPDDR3 and DDR4
UC1N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
SKL-U_BGA1356
+1.0V_VCCST
1
2
CC202
1U_0402_6.3V6K
SKL-U
PSC
D
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
+VCC_SA
G0.9
+1.0VS_VCCIO
AK28
VCCIO
AK30
VCCIO
AL30
VCCIO
AL42
VCCIO
AM28
VCCIO
AM30
VCCIO
AM42
VCCIO
AK23
VCCSA
AK25
VCCSA
G23
VCCSA
G25
VCCSA
G27
VCCSA
G28
VCCSA
J22
VCCSA
J23
VCCSA
J27
VCCSA
K23
VCCSA
K25
VCCSA
K27
VCCSA
K28
VCCSA
K30
VCCSA
14 OF 20
RC168 100_0402_1%
AM23
AM22
H21
H20
1 2
VCCIO_SENSE
VSSIO_SENSE
+VCC_SA
+1.0VS_VCCIO
12
RC166
100_0402_1%
VSA_SEN- <49>
VSA_SEN+ <49>
12
RC165
12
RC167
8/14 PWR request
100_0402_1%
VCCIO_SENSE <47>
VSSIO_SENSE <47>
100_0402_1%
12
CZ95 1U_0402_6.3V6K
SIO_SLP_S4#<11,17,32,45,54>
+5V_ALW
+1.0V_VCCST source
+1.0V_PRIM
UZ21
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
+1.0VS_VCCIO
SIO_SLP_S0#
SIO_SLP_S3#
PSC
AND
VOUT
1
1
2
2
CC182
CC181
@
@
1U_0402_6.3V6K
1
1
2
2
CC252
CC253
1U_0402_6.3V6K
+1.0V_VCCST_C
6
5
GND
INTEL PDG 1.0
1
1
2
2
CC185
CC186
@
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
CC250
CC251
1U_0402_6.3V6K
1U_0402_6.3V6K
S0 S0Ix S3
HIGH
HIGH
HIGH LOW LOW
LOW
HIGH
LOW
LOW
PJP27
12
PAD-OPEN1x1m
1 2
@
CZ78 0.1U_0201_10V6K
+1.0V_VCCST
BSCBSC
1
1
CC248
CC249
2
2
@
@
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0402_6.3V6M
B B
A A
+VCCPLL_OC source
SIO_SLP_S3#<11,17,32,48>
SIO_SLP_SUS#<8,11,18,32,41,46,47,48>
SIO_SLP_S4#<11,17,32,45,54>
5
UC14
TC7SH08FU_SSOP5~D
12
CZ113 1U_0402_6.3V6K
+5V_ALW
1 2
@
RZ120 0_0402_5%
+3.3V_ALW
1 2
@
CZ115 0.1U_0201_10V6K
5
1
P
B
4
O
2
A
G
3
+1.2V_MEM
1 2
RZ119 0_0603_5%@
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4
VOUT
GND
+VCC_SFR_OC
6
5
1 2
@
CZ114 0.1U_0201_10V6K
CZ87 1U_0402_6.3V6K
SIO_SLP_S0#<11,33,47>
SIO_SLP_S3#<11,17,32,48>
TC7SH08FU_SSOP5~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+1.0V_VCCSTG source
UC13
RC320 0_0402_5%@
12
+5V_ALW
+3.3V_ALW
5
1
P
B
2
A
G
3
1 2
O
+1.0V_PRIM
4
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
2
+1.0V_VCCST+1.0V_VCCSTG
1 2
RC238 0_0603_5%@
pop option with UZ19
1 2
@
CZ82 0.1U_0201_10V6K
VOUT
GND
6
5
12
PJP32
PAD-OPEN1x1m
+1.0V_VCCSTG_C
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/14)
CPU (12/14)
CPU (12/14)
LA-C621P
LA-C621P
LA-C621P
17 60Thursday, September 24, 2015
17 60Thursday, September 24, 2015
17 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 18
5
Vinafix.com
+1.0V_PRIM
LC1
+1.0V_PRIM_CORE
+1.0V_MPHYAON
+1.0V_CLK6
+1.0V_DTS
+1.0V_CLK1
+1.0V_CLK3
+3.3V_1.8V_PGPPG
0/30: layout limit, change from 0603 to 0402
1
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+3.3V_PGPPE
1
CC310
2
0.1U_0402_25V6
22U_0603_6.3V6M
@
22U_0603_6.3V6M
@
CC279
CC280
1
1
2
2
8/26 vender suggest depop
5
+1.0V_MPHYGT
close UC1.AF20 and <400mil
8/26 vender suggest depop
1 2
RC194 0_0805_5%
@
Imax : 2.57A
D D
+1.8V_PRIM
C C
+3.3V_ALW_PCH
+1.8V_PRIM
+3.3V_ALW_PCH
B B
+3.3V_ALW_PCH +3.3V_VCCHDA
A A
1 2
@
RC299 0_0603_5%
1 2
@
RC300 0_0402_5%
1 2
@
RC301 0_0402_5%
1 2
@
RC302 0_0402_5%
1 2
@
RC303 0_0402_5%
1 2
@
RC234 0_0402_5%
1 2
@
RC235 0_0402_5%
1 2
@
RC211 0_0402_5%
1 2
@
RC212 0_0402_5%
1 2
@
RC307 0_0402_5%
1 2
@
RC308 0_0402_5%
1 2
BLM15HG601SN1D
1
CC215
2
@
1U_0402_6.3V6K
+3.3V_ALW +3.3V_ALW_DSW
1 2
@
RC214 0_0402_5%
+1.0V_MPHYAON
1
2
CC203
1U_0402_6.3V6K
close UC1.N15 and CC210 <400mil, CC211 <120mil
1
1
CC210
2
2
CC211
@
1U_0402_6.3V6K
47U_0805_6.3V6M
+1.0V_SRAM
1
2
close UC1.K15, UC1.L15 and <100mil
1 2
@
RC169 0_0603_5%
1
2
CC281
@
0.1U_0201_10V6K
+1.0V_PRIM
LC2
1 2
BLM15HG601SN1D
1
CC225
2
@
47U_0805_6.3V6M
+3.3V_ALW +1.8V_PRIM +1.0V_PRIM
1
CC271
2
47U_0805_6.3V6M
4
close UC1.AL1 and <120mil
1
2
CC204
1U_0402_6.3V6K
CC217
+1.0V_APLLEBB
@
1U_0402_6.3V6K
close UC1.N18 and <120mil
1
2
CC218
1U_0402_6.3V6K
+1.0V_AMPHYPLL+1.0V_MPHYGT
1
CC219
2
@
47U_0805_6.3V6M
+1.0V_VCCAPLL
+1.0V_PRIM_CORE
1
1
CC272
2
CC273
2
47U_0805_6.3V6M
47U_0805_6.3V6M
4
+1.0V_PRIM_CORE+1.0VO_DSW
+1.0V_PRIM
close UC1.K15 and <120mil
1
2
CC264
@
1
CC311
2
+1.0V_AMPHYPLL
+1.0V_VCCAPLL
+1.0V_PRIM
+3.3V_ALW_DSW
+3.3V_VCCHDA
+3.3V_SPI
+3.3V_ALW_PCH
1U_0402_6.3V6K
0.1U_0402_25V6
1
CC274
2
47U_0805_6.3V6M
close UC1.AB19 and <400milclose UC1.K17 and <120mil
+1.0V_PRIM
1
CC206
2
@
AB19
1U_0402_6.3V6K
AB20
AF18
AF19
AB17
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
@
RC170 0_0402_5%
close UC1.K19 and <100mil
8/26 vender suggestion
UC1O
VCCPRIM_1P0
VCCPRIM_1P0
P18
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKL-U_BGA1356
1 2
close UC1.N20 and <100mil
3
PCH PWR
CPU POWER 4 OF 4
+1.0V_CLK2+1.0V_PRIM
1
CC220
2
@
47U_0805_6.3V6M
SKL-U
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
close UC1.L19 and <100mil
close UC1.AG15 and <120mil
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+3.3V_1.8V_PGPPA
+3.3V_PGPPD
+1.8V_PRIM
+3.3V_1.8V_PGPPG
+1.0V_DTS
+3.3V_ALW_PCH
close UC1.AK19 and <120mil
+DCPRTC
close UC1.BB10 and <120mil
+1.0V_CLK1
+1.0V_CLK2
+1.0V_CLK3
+1.0V_CLK4
+1.0V_CLK5
CORE_VID0 <47>
CORE_VID1 <47>
Take care!!! Note1 on Page 19
1 2
@
RC171 0_0402_5%
2
close UC1.Y16 and <400mil
+3.3V_ALW_PCH
close UC1.AA1 and <400mil
1
2
+1.0V_CLK6
1
CC221
2
@
47U_0805_6.3V6M
+3.3V_ALW_PCH
+RTC_CELL
1
2
CC214
D
G0.9
0.1U_0201_10V6K
close UC1.A10 and <120mil
1
CC216
2
@
1U_0402_6.3V6K
+1.0V_MPHYGT source
+1.0V_CLK4+1.0V_PRIM
1 2
@
RC173 0_0402_5%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
CC226
2
@
47U_0805_6.3V6M
SIO_SLP_SUS#<8,11,17,32,41,46,47,48>
MPHYP_PWR_EN<11>
11
/0 change power source
CZ84 1U_0402_6.3V6K@
+1.0V_PRIM
12
+5V_ALW
12
RZ82 0_0402_5%@
12
RZ83 0_0402_5%@
2
1
+1.0V_MPHYGT
1 2
@
+3.3V_ALW_PCH
1
2
CC212
1U_0402_6.3V6K
CC224
1U_0402_6.3V6K
VOUT
GND
RC309 0_0603_5%
1 2
@
RC310 0_0603_5%
close UC1.V19 and <120mil
CC209
@
1U_0402_6.3V6K
Pop PJP35 & Depop UZ20/RZ83/CZ84
1 2
PAD-OPEN1x3m
+1.0V_MPHYGT
6
5
1
2
@
CC270
0.1U_0201_10V6K
DG0.9
+3.3V_PGPPE
1
2
close UC1.T16 and <400mil
1
CC208
2
@
1U_0402_6.3V6K
+1.8V_PRIM
CC213
1U_0402_6.3V6K
+3.3V_ALW_PCH+1.0V_CLK5+1.0V_PRIM
1
CC223
2
0.1U_0201_10V6K
@
UZ20
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
4.4mohm/6A
TR=12.5us@Vin=1.05V
1
2
close UC1.AK17 and <120mil
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (13/14)
CPU (13/14)
CPU (13/14)
LA-C621P
LA-C621P
LA-C621P
1
+1.0V_SRAM
+1.0V_APLLEBB
PJP35
CZ85
0.1U_0201_10V6K
18 60Thursday, September 24, 2015
18 60Thursday, September 24, 2015
18 60Thursday, September 24, 2015
+1.0V_MPHYGT+1.0V_PRIM
1.0
1.0
1.0
Page 19
5
Vinafix.com
4
3
2
1
Note1: VCCPRIM_CORE Implementation with PCH CORE_VID Recommendation
SKL-U
UC1P
GND 1 OF 3
A5
VSS
A67
VSS
A70
VSS
AA2
VSS
AA4
D D
C C
B B
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
UC1Q
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U_BGA1356
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17 OF 20
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
SKL-U_BGA1356
UC1R
GND 3 OF 3
SKL-U
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
18 OF 20
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CPU (14/14)
CPU (14/14)
CPU (14/14)
LA-C621P
LA-C621P
LA-C621P
19 60Thursday, September 24, 2015
19 60Thursday, September 24, 2015
19 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 20
5
Vinafix.com
4
3
2
1
JDIMM1 REV Type H=4
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..16]<7>
Layout Note:
+1.2V_MEM
12
+1.2V_MEM
12
Place near JDIMM1
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD2
CD7
10U_0603_10V6M
10U_0603_10V6M
CD13
CD12
12
12
+0.6V_DDR_VTT
DIMM Select
DIMM1
DIMM2
DIMM3
DIMM4
1U_0402_6.3V6K
CD3
10U_0603_10V6M
CD14
1
2
SA01SA1
12
12
1U_0402_6.3V6K
0
1
0
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD8
CD9
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
CD15
CD16
12
12
Layout Note:
Place near
JDIMM1.203,204
1U_0402_6.3V6K
CD25
CD24
1
1
2
2
SA2
0
0
0
0
0
0
1
5
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
CD10
CD4
CD11
10U_0603_10V6M
10U_0603_10V6M
CD19
CD17
CD18
12
12
12
1
2
12
12
1U_0402_6.3V6K
CD27
@
0_0402_5%
@
RD66
0_0402_5%
10U_0603_10V6M
12
RD62
1U_0402_6.3V6K
CD26
1U_0402_6.3V6K
CD78
10U_0603_10V6M
CD86
CD28
12
12
12
12
12
RD63
@
0_0402_5%
@
RD67
0_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
CD80
CD79
CD81
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
CD89
CD87
CD88
12
12
12
+2.5V_MEM
10U_0603_10V6M
1U_0402_6.3V6K
1
12
@
0_0402_5%
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
12
@
0_0402_5%
RD68
RD64
1
CD70
2
2
@
CD29
+3.3V_RUN+3.3V_RUN+3.3V_RUN
1U_0402_6.3V6K
CD82
10U_0603_10V6M
CD90
1U_0402_6.3V6K
CD71
+3.3V_RUN
12
12
1
2
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
12
@
0_0603_5%
1
2
12
CD83
CD91
12
CD72
RD65
2.2U_0402_6.3V6M
CD31
4
1U_0402_6.3V6K
12
CD84
10U_0603_10V6M
CD92
12
10U_0603_10V6M
1
CD73
2
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
1
2
1U_0402_6.3V6K
CD85
330U_D3_2.5VY_R6M
10U_0603_10V6M
@
12
CD20
CD93
+
DDR_A_CKE0<7>
DDR_A_BG1<7>
DDR_A_BG0<7>
DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_PARITY<7>
DDR_A_CS#0<7>
DDR_A_ODT0<7>
DDR_A_CS#1<7>
DDR_A_ODT1<7>
CD32
D D
C C
B B
A A
DDR_A_BA1<7>
DDR_A_MA14<7>
+2.5V_MEM
DDR_A_D1
DDR_A_D0
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D2
DDR_A_D13
DDR_A_D12
DDR_A_D15
DDR_A_D14
DDR_A_D35
DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D38
DDR_A_D34
DDR_A_D44
DDR_A_D45
DDR_A_D42
DDR_A_D46
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PARITY
DDR_A_BA1
DDR_A_CS#0
DDR_A_MA14
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
T51PAD~D @
DDR_A_D30
DDR_A_D26
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D27
DDR_A_D29
DDR_A_D21
DDR_A_D17
DDR_A_D19
DDR_A_D22
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D63
DDR_A_D62
+3.3V_RUN_DIMM1
JDIMM1
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
75
DM3_n/DBI3_n
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LOTES_ADDR0107-P005A
CONN@
3
RESET_n
ALERT_n
EVENT_n/NF
CK1_t/NF
CK1_c/NF
RAS_n/A16
CAS_n/A15
C0/CS2_n/NC
DM4_n/DBI4_n
DM6_n/DBI6_n
+1.2V_MEM+1.2V_MEM
2
VSS2
VSS4
VSS6
VSS7
VSS9
VSS11
DQ12
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
CKE1
VDD2
ACT_n
VDD4
VDD6
VDD8
VDD10
VDD12
A10/AP
VDD14
VDD16
VDD18
VREFCA
VSS54
DQ36
VSS56
DQ32
VSS58
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
GND2
DQ4
DQ0
DQ6
DQ2
DQ8
A11
A7
A5
A4
A2
A0
BA0
A13
SA2
SDA
SA0
VTT
SA1
DDR_A_D4
4
6
DDR_A_D5
8
10
12
14
DDR_A_D3
16
18
DDR_A_D7
20
22
DDR_A_D9
24
26
DDR_A_D8
28
30
DDR_A_DQS#1
32
DDR_A_DQS1
34
36
DDR_A_D10
38
40
DDR_A_D11
42
44
DDR_A_D32
46
48
DDR_A_D36
50
52
54
56
DDR_A_D39
58
60
DDR_A_D33
62
64
DDR_A_D40
66
68
DDR_A_D41
70
72
DDR_A_DQS#5
74
DDR_A_DQS5
76
78
DDR_A_D47
80
82
DDR_A_D43
84
86
88
90
92
94
96
98
100
102
104
106
DDR_DRAMRST#_R
108
DDR_A_CKE1
110
112
DDR_A_ACT#
114
DDR_A_ALERT#
116
118
DDR_A_MA11
120
DDR_A_MA7
122
124
DDR_A_MA5
126
DDR_A_MA4
128
130
DDR_A_MA2
132
JDIMM1_EVENT#
134
136
DDR_A_CLK1
138
DDR_A_CLK#1
140
142
DDR_A_MA0
144
DDR_A_MA10
146
148
DDR_A_BA0
150
DDR_A_MA16
152
154
DDR_A_MA15
156
DDR_A_MA13
158
160
162
164
DIMM1_SA2
166
168
DDR_A_D31
170
172
DDR_A_D25
174
176
178
180
DDR_A_D28
182
184
DDR_A_D24
186
188
DDR_A_D20
190
192
DDR_A_D16
194
196
DDR_A_DQS#2
198
DDR_A_DQS2
200
202
DDR_A_D18
204
206
DDR_A_D23
208
210
DDR_A_D53
212
214
DDR_A_D52
216
218
220
222
DDR_A_D54
224
226
DDR_A_D55
228
230
DDR_A_D61
232
234
DDR_A_D60
236
238
DDR_A_DQS#7
240
DDR_A_DQS7
242
244
DDR_A_D58
246
248
DDR_A_D59
250
252
254
DIMM1_SA0
256
258
DIMM1_SA1
260
262
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_A_CKE1 <7>
DDR_A_ACT# <7>
DDR_A_ALERT# <7>
DDR_A_CLK1 < 7>
DDR_A_CLK#1 <7>
DDR_A_BA0 <7>
T50 PAD~D@
+DDR_VREF_A_CA
DDR_XDP_WAN_SMBDAT <8,14,21,42>DDR_XDP_WAN_SMBCLK<8,14,21,42>
+0.6V_DDR_VTT
+DDR_VREF_A_CA
DDR_VTT_CTRL<7>
2
1
@
CD6
0.1U_0402_25V6
2
JDIMM1_EVENT#
1
NC
2
A
3
GND
SN74AUP1G07DCKR SC70 5P
+1.2V_MEM
470_0402_1%
12
RD2
DG0.9 470ohm+/-1%
1 2
@
RD29 0_0402_5%
+1.2V_MEM
1K_0402_1%
12
RD18
1K_0402_1%
12
RD20
DDR_DRAMRST#
1 2
RD19 2_0402_1%
24.9_0402_1%
12
12
RD21
follow INTEL PDG1.0 page167
RD61 1K_0402_5%@
UD1
1 2
VCC
Y
+1.2V_MEM
5
1 2
[email protected]_0201_10V6K
4
RD30 100K_0402_5%
1 2
H_THERMTRIP# <12,21,32>
0.6V_DDR_VTT_ON <45>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR4
DDR4
ze Document Number Rev
DDR4
LA-C621P
LA-C621P
LA-C621P
1
0.022U_0402_16V7K
CD36
+3.3V_ALW
DDR_DRAMRST# <7>DDR_DRAMRST#_R<21>
+DDR_VREF_CA+DDR_VREF_A_CA
20 60Thursday, September 24, 2015
20 60Thursday, September 24, 2015
20 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 21
5
Vinafix.com
4
3
2
1
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..16]<7>
1U_0402_6.3V6K
12
CD37
10U_0603_10V6M
CD45
12
+0.6V_DDR_VTT
SA01SA1
0
1
0
1
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K
12
12
CD39
CD38
10U_0603_10V6M
CD47
CD46
12
12
1U_0402_6.3V6K
CD57
1
1
2
2
SA2
0
0
0
0
0
0
1
5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD40
CD41
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
CD49
CD48
12
12
Layout Note:
Place near
JDIMM2.203,204
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD59
CD58
1
1
2
2
12
@
RD69
0_0402_5%
12
@
RD72
0_0402_5%
12
CD43
CD51
12
CD61
12
@
RD70
0_0402_5%
@
RD73
0_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
CD102
CD44
CD103
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
CD95
CD52
CD94
12
12
12
12
@
0_0402_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
12
@
0_0402_5%
+2.5V_MEM
RD71
RD74
10U_0603_10V6M
@
CD62
+3.3V_RUN+3.3V_RUN+3.3V_RUN
1U_0402_6.3V6K
12
CD42
10U_0603_10V6M
CD50
12
10U_0603_10V6M
CD60
12
12
12
1U_0402_6.3V6K
10U_0603_10V6M
CD104
CD96
1
2
1U_0402_6.3V6K
12
10U_0603_10V6M
12
1U_0402_6.3V6K
CD74
+3.3V_RUN
CD105
CD97
1
2
12
@
0_0603_5%
12
1U_0402_6.3V6K
12
CD106
10U_0603_10V6M
CD98
12
1U_0402_6.3V6K
1
CD75
2
RD60
+3.3V_RUN_DIMM2
2.2U_0402_6.3V6M
1
CD63
2
4
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
10U_0603_10V6M
0.1U_0201_10V6K
12
CD108
CD107
CD109
330U_D3_2.5VY_R6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
@
12
CD53
CD100
CD101
CD99
12
12
+
DDR_B_CKE0<7>
DDR_B_BG1<7>
DDR_B_BG0<7>
DDR_B_CLK0<7>
DDR_B_CLK#0<7>
DDR_B_PARITY<7>
DDR_B_BA1<7>
DDR_B_CS#0<7>
DDR_B_MA14<7>
DDR_B_ODT0<7>
DDR_B_CS#1<7>
DDR_B_ODT1<7>
T55PAD~D @
10U_0603_10V6M
1
CD77
CD76
2
CD64
+3.3V_RUN_DIMM2
+2.5V_MEM
D D
+1.2V_MEM
1U_0402_6.3V6K
12
+1.2V_MEM
10U_0603_10V6M
12
C C
B B
DIMM Select
DIMM1
DIMM2
DIMM3
*
A A
DIMM4
JDIMM2 REV Type H=4
JDIMM2
1
DDR_B_D1
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D7
DDR_B_D6
DDR_B_D13
DDR_B_D12
DDR_B_D14
DDR_B_D15
DDR_B_D33
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D39
DDR_B_D38
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_CKE0
DDR_B_BG1
DDR_B_BG0
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_PARITY
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D23
DDR_B_D22
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D52
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D54
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
75
DM3_n/DBI3_n
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
LOTES_ADDR0107-P005A
CONN@
3
+1.2V_MEM+1.2V_MEM
2
VSS2
DQ4
VSS4
DQ0
VSS6
VSS7
DQ6
VSS9
DQ2
VSS11
DQ12
VSS13
DQ8
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
A11
A7
VDD6
A5
A4
VDD8
A2
EVENT_n/NF
VDD10
CK1_t/NF
CK1_c/NF
VDD12
A0
A10/AP
VDD14
BA0
RAS_n/A16
VDD16
CAS_n/A15
A13
VDD18
C0/CS2_n/NC
VREFCA
SA2
VSS54
DQ36
VSS56
DQ32
VSS58
DM4_n/DBI4_n
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
DM6_n/DBI6_n
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
SDA
SA0
VTT
SA1
GND2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_B_D5
4
6
DDR_B_D0
8
10
12
14
DDR_B_D2
16
18
DDR_B_D3
20
22
DDR_B_D9
24
26
DDR_B_D8
28
30
DDR_B_DQS#1
32
DDR_B_DQS1
34
36
DDR_B_D11
38
40
DDR_B_D10
42
44
DDR_B_D37
46
48
DDR_B_D32
50
52
54
56
DDR_B_D34
58
60
DDR_B_D35
62
64
DDR_B_D40
66
68
DDR_B_D41
70
72
DDR_B_DQS#5
74
DDR_B_DQS5
76
78
DDR_B_D46
80
82
DDR_B_D47
84
86
88
90
92
94
96
98
100
102
104
106
DDR_DRAMRST#_R
108
DDR_B_CKE1
110
112
DDR_B_ACT#
114
DDR_B_ALERT#
116
118
DDR_B_MA11
120
DDR_B_MA7
122
124
DDR_B_MA5
126
DDR_B_MA4
128
130
DDR_B_MA2
132
JDIMM2_EVENT#
134
136
DDR_B_CLK1
138
DDR_B_CLK#1
140
142
DDR_B_MA0
144
DDR_B_MA10
146
148
DDR_B_BA0
150
DDR_B_MA16
152
154
DDR_B_MA15
156
DDR_B_MA13
158
160
162
164
DIMM2_SA2
166
168
170
172
174
176
178
180
DDR_B_D18
182
184
DDR_B_D19
186
188
190
192
DDR_B_D29
194
196
DDR_B_DQS#3
198
DDR_B_DQS3
200
202
DDR_B_D31
204
206
DDR_B_D30
208
210
DDR_B_D53
212
214
DDR_B_D48
216
218
220
222
DDR_B_D50
224
226
228
230
DDR_B_D61
232
234
DDR_B_D60
236
238
DDR_B_DQS#7
240
DDR_B_DQS7
242
244
DDR_B_D62
246
248
250
252
254
DIMM2_SA0
256
258
DIMM2_SA1
260
262
DDR_B_D16
DDR_B_D17
DDR_B_D28
DDR_B_D51
DDR_B_D63
DDR_B_CKE1 <7>
DDR_B_ACT# <7>
DDR_B_ALERT# <7>
DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>
DDR_B_BA0 <7>
T54 PAD~D@
+DDR_VREF_B_CA
DDR_XDP_WAN_SMBDAT <8,14,20, 42>DDR_XDP_WAN_SMBCLK<8,14,20,42>
+0.6V_DDR_VTT
+DDR_VREF_B_CA
2
JDIMM2_EVENT#
RD4 1K_0402_5%@
1
@
CD35
0.1U_0402_25V6
2
+DDR_VREF_B_CA
1 2
DDR_DRAMRST#_R <20>
+1.2V_MEM
1K_0402_1%
12
RD22
RD75 2_0402_1%
1K_0402_1%
12
RD24
H_THERMTRIP# <12,20,32>
1 2
follow INTEL PDG1.0 page167
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR4
DDR4
ze Document Number Rev
DDR4
LA-C621P
LA-C621P
LA-C621P
1
+DDR_VREF_B_DQ
0.022U_0402_16V7K
CD54
12
24.9_0402_1%
12
RD25
21 60Thursday, September 24, 2015
21 60Thursday, September 24, 2015
21 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 22
5
Vinafix.com
4
3
2
1
CPU_DP1_P0<6>
D D
C C
CPU_DP1_N0<6>
CPU_DP1_P1<6>
CPU_DP1_N1<6>
CPU_DP1_P2<6>
CPU_DP1_N2<6>
CPU_DP1_P3<6>
CPU_DP1_N3<6>
CV17
CV18
CV21
CV22
CV28
CV29
CV13
CV14
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
12
0.1U_0402_25V6
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
EMC@
RV647 8.2_0402_1%EMC@
RV649 8.2_0402_1%EMC@
RV650
RV652 8.2_0402_1%EMC@
RV653 8.2_0402_1%EMC@
RV655
RV656
RV658 8.2_0402_1%EMC@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
8.2_0402_1%
8.2_0402_1%EMC@
8.2_0402_1%EMC@
1 2
1 2
1 2
1 2
HDMI_L_TX_P2
EMC@
RV648
150_0402_5%
HDMI_L_TX_N2
HDMI_L_TX_P1
EMC@
RV651
150_0402_5%
HDMI_L_TX_N1
HDMI_L_TX_P0
EMC@
RV654
150_0402_5%
HDMI_L_TX_N0
HDMI_L_CLKP
EMC@
RV657
150_0402_5%
HDMI_L_CLKN
+5V_RUN
0.1U_0201_10V6K
1
@
CV23
1
2
IN
GND2OUT
AP2330W-7_SC59-3
UV2
3
+VHDMI_VCC
1
2
10U_0603_10V6M
0.1U_0201_10V6K
CV27
12
@
CV26
HDMI connector
+3.3V_RUN
HDMI_HPD
HDMI_OB
2
G
+3.3V_RUN
1
D
QV4
L2N7002WT1G_SC-70-3
S
3
12
RV8@10K_0402_5%
QV3A
2
DMN65D8LDW-7_SOT363-6
CPU_DP1_CTRL_CLK<6>
CPU_DP1_CTRL_DATA<6>
1
5
QV3B
DMN65D8LDW-7_SOT363-6
HDMI_CTRL_CLK
6
HDMI_CTRL_DATA
34
1 2
RV21 2.2K_0402_5%
1 2
RV18 2.2K_0402_5%
B B
+3.3V_RUN
1M_0402_5 %
RV22
CPU_DP1_HPD<6>
1 2
G
123
D
S
QV5
L2N7002WT1G_SC-70-3
HDMI_HPD
1 2
RV20 20K_0402_5%
+VHDMI_VCC
HDMI_TX_P2
HDMI_TX_N2
HDMI_TX_P1
HDMI_TX_N1
HDMI_TX_P0
HDMI_TX_N0
HDMI_CLKP
HDMI_CLKN
+3.3V_RUN
1 2
RV10 470_0402_1%
1 2
RV11 470_0402_1%
RV12 470_0402_1%
1 2
1 2
RV13 470_0402_1%
RV14 470_0402_1%
1 2
1 2
RV15 470_0402_1%
1 2
RV16 470_0402_1%
RV17 470_0402_1%
1 2
1 2
RV19 10K_0402_5%
HDMI_CTRL_DATA
HDMI_CTRL_CLK
HDMI_CEC
HDMI_L_CLKN
HDMI_L_CLKP
HDMI_L_TX_N0
HDMI_L_TX_P0
HDMI_L_TX_N1
HDMI_L_TX_P1
HDMI_L_TX_N2
HDMI_L_TX_P2
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
10
GND
CK_shield
GND
CK+
GND
9
D0-
GND
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
CONCR_099BKAC19YBLCNF
CONN@
20
21
22
23
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-C621P
LA-C621P
LA-C621P
22 60Thursday, September 24, 2015
22 60Thursday, September 24, 2015
22 60Thursday, September 24, 2015
1.0
1.0
1.0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 23
5
Vinafix.com
+3.3V_RUN
SW1_PS8338_CFG0
1 2
RV601 4.7K_0402_5%
SW1_DP0_AUXN
1 2
RV604 100K_0402_5%
D D
C C
RV605 100K_0402_5%
RV606 1M_0402_5%
RV607 1M_0402_5%
RV608 100K_0402_5%
RV609 100K_0402_5%
+3.3V_RUN
12
RV611
RV610
@
@
4.7K_0402_5%
4.7K_0402_5%
12
RV617
RV616
@
@
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
1 2
1 2
1 2
12
RV612
@
4.7K_0402_5%
12
RV618
@
4.7K_0402_5%
SW1_DP1_AUXN
SW1_DP0_CADET
SW1_DP1_CADET
SW1_DP0_AUXP
SW1_DP1_AUXP
12
RV613
@
4.7K_0402_5%
12
RV619
@
4.7K_0402_5%
12
12
RV614
@
4.7K_0402_5%
12
12
RV620
@
4.7K_0402_5%
12
12
RV615
RV603
@
@
4.7K_0402_5%
4.7K_0402_5%
RV621
@
4.7K_0402_5%
12
SW1_PS8338_P0
SW1_PS8338_P1
SW1_PS8338_PC10
SW1_PS8338_PC11
SW1_PS8338_PC20
SW1_PS8338_PC21
SW1_PS8338_PEQ
4
0.01UF_0402_25V7K
12
CPU_DP2_P0<6>
CPU_DP2_N0<6>
CPU_DP2_P1<6>
CPU_DP2_N1<6>
CPU_DP2_P2<6>
CPU_DP2_N2<6>
CPU_DP2_P3<6>
CPU_DP2_N3<6>
for support TMDS signal need contact SCL/SDA to P22,23
CPU_DP2_CTRL_CLK<6>
CPU_DP2_CTRL_DATA<6>
CPU_DP2_AUXP<6>
CPU_DP2_AUXN<6>
CV606 0.1U_0402_25V6
CV607 0.1U_0402_25V6
CV608 0.1U_0402_25V6
CV609 0.1U_0402_25V6
CV610 0.1U_0402_25V6
CV611 0.1U_0402_25V6
CV612 0.1U_0402_25V6
CV613 0.1U_0402_25V6
CV79 0.1U_0402_25V6
CV80 0.1U_0402_25V6
CV604
0.01UF_0402_25V7K
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_DP2_HPD<6>
1 2
1 2
3
+3.3V_RUN
0.1U_0201_10V6K
CV601
1
1
2
2
CPU_DP2_P0_C
CPU_DP2_N0_C
CPU_DP2_P1_C
CPU_DP2_N1_C
CPU_DP2_P2_C
CPU_DP2_N2_C
CPU_DP2_P3_C
CPU_DP2_N3_C
SW1_PS8338_P1
SW1_PS8338_P0
CPU_DP2_AUXP_C
CPU_DP2_AUXN_C
SW1_PS8338_CFG0
SW1_PS8338_PC10
SW1_PS8338_PC11
SW1_PS8338_PC20
SW1_PS8338_PC21
0.1U_0201_10V6K
Dock has high priority when both ports plugged
CV600
UV26
5
VDD33
21
VDD33
30
VDD33
51
VDD33
57
VDD33
6
IN_D0p
7
IN_D0n
9
IN_D1p
10
IN_D1n
12
IN_D2p
13
IN_D2n
15
IN_D3p
16
IN_D3n
4
IN_CA_DET
3
IN_HPD
2
I2C_CTL_EN
1
Pl1/SCL_CTL
60
Pl0/SDA_CTL
22
IN_DDC_SCL
23
IN_DDC_SDA
24
IN_AUXp
25
IN_AUXn
59
CFG0
58
CFG1
56
PC10
55
PC11
54
PC20
53
PC21
11
GND
19
GND
52
GND
61
PAD(GND)
PS8338BQFN60GTR-A0_QFN60_5X9
OUT1_D0p
OUT1_D0n
OUT1_D1p
OUT1_D1n
OUT1_D2p
OUT1_D2n
OUT1_D3p
OUT1_D3n
OUT2_D0p
OUT2_D0n
OUT2_D1p
OUT2_D1n
OUT2_D2p
OUT2_D2n
OUT2_D3p
OUT2_D3n
OUT1_AUXp_SCL
OUT1_AUXn_SDA
OUT2_AUXp_SCL
OUT2_AUXn_SDA
OUT1_CA_DET
OUT1_HPD
OUT2_CA_DET
OUT2_HPD
PEQ
CEXT
REXT
SW
PD
50
49
47
46
45
44
42
41
40
39
37
36
35
34
32
31
26
27
28
29
SW1_DP0_CADET
43
48
SW1_DP1_CADET
33
38
SW1_PS8338_SW
18
SW1_PS8338_PEQ
8
14
17
20
12
RV600
4.99K_0402_1%
0.1U_0201_10V6K
CV602
1
CV603
2
2
SW1_DP0_P0 <24>
SW1_DP0_N0 <24>
SW1_DP0_P1 <24>
SW1_DP0_N1 <24>
SW1_DP0_P2 <24>
SW1_DP0_N2 <24>
SW1_DP0_P3 <24>
SW1_DP0_N3 <24>
SW1_DP1_P0 <29>
SW1_DP1_N0 <29>
SW1_DP1_P1 <29>
SW1_DP1_N1 <29>
SW1_DP1_P2 <29>
SW1_DP1_N2 <29>
SW1_DP1_P3 <29>
SW1_DP1_N3 <29>
SW1_DP0_AUXP <24>
SW1_DP0_AUXN <24>
SW1_DP1_AUXP <29>
SW1_DP1_AUXN <29>
SW1_DP0_HPD <24>
SW1_DP1_HPD <29>
2.2U_0402_6.3V6M
12
CV605
1
-----> VMM3320
-----> WIGIG
+3.3V_RUN
12
RV602
4.7K_0402_5%
SW1_PS8338_SW
1
D
2
DOCKED<25,27,31>
B B
A A
G
3
QV11
L2N7002WT1G_SC-70-3
S
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DP SW
DP SW
DP SW
LA-C621P
LA-C621P
LA-C621P
23 60Thursday, September 24, 2015
23 60Thursday, September 24, 2015
23 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 24
2
Vinafix.com
1
+1.0V_RUN_VMM
LV22
1 2
BLM15PX181SN1D_2P
+1.0V_RUN_VMM
1 2
+3.3V_RUN_VMM
BLM15PX181SN1D_2P
PJP24
1 2
PAD-OPEN1x1m
PJP25
1 2
PAD-OPEN1x1m
BLM15PX181SN1D_2P
LV24
1 2
B B
+1.0VS_VCCIO + 1.0V_RUN_VMM
+3.3V_RUN +3.3V_RUN_VMM
A A
+1.0V_VMM_VDD
10U_0603_10V6M
0.1U_0201_10V6K
CV83
1
1
12
CV82
2
2
1U_0603_10V6K
0.1U_0201_10V6K
CV88
1
12
12
CV87
2
LV23
+1.0V_VMM_VDDTX
10U_0603_10V6M
0.1U_0201_10V6K
CV90
CV91
1
12
12
2
+3.3V_RUN_VDDIO
10U_0603_10V6M
0.1U_0201_10V6K
CV95
1
12
12
CV94
2
+3.3V_RUN_VDDA
0.1U_0201_10V6K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.01UF_0402_25V7K
CV84
12
CV89
CV92
12
12
CV96
0.01UF_0402_25V7K
12
CV85
+1.0VS_VCCIO
0.01UF_0402_25V7K
CV93
0.01UF_0402_25V7K
CV97
0.01UF_0402_25V7K
0.786A
74mA
+1.0V_RUN_VMM
12
RV659
27.4K_0402_1%
12
RV660
88.7K_0402_1%
+1.8V_PRIM
Low Power Mode by external Load switch
12
@
CV616 1U_0402_6.3V6K
+5V_ALW
UV8B
E6
VDD
E7
VDD
E8
VDD
E9
VDD
H6
CV86
VDD
H7
VDD
H8
VDD
H9
VDD
E3
VDDRX
G3
VDDRX
C8
VDDTX0
C9
VDDTX0
F12
VDDTX1
G12
VDDTX1
J3
VDDLP
E5
VDDLP
H3
NC
F3
VDDRXA1
D3
VDDRX
E10
NC
C7
VDDTX0A1
C6
VDDTX0A2
H11
NC
E12
VDDTX1A1
D12
VDDTX1A2
J10
VGA_AVDD
K8
VGA_AVDD
K9
VGA_AVDD
K10
VGA_AVDD
J2
VDDSA
C3
VDDHRX_33
C4
VDDHRX_33
C11
VDDHTX0_33
C12
VDDIO
K3
VDDIO
K4
VDDIO
K11
VDDIO
K12
VDDIO
J4
VDDXT3V
VMM3320BJGR_BGA168
12
CV619 1U_0402_6.3V6K
HUB_LP_EN
12
CV618
10U_0603_10V6M
+1.0VS_VCCIO
HUB_LP_EN
3.3V Analog
1V Digital 1 V Analog 3.3V IO
+5V_ALW
VO=0.8*(R1+R2)/R2 Volt
RV662
@
0_0402_5%
1 2
10
VCNTL
9
EN
8
VIN
7
VIN
6
VIN
11
APL5930QBI-TRG_TDFN10_3X3
@
UV28
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
VOUT
GND
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
UV29
1
POK
2
ADJADJ
FB
3
VOUT
4
VOUT
5
VOUT
GND
Pop UV28 &PJP33, depop PJP24
+1.0V_RUN_VMM_P
6
5
+3.3V_RUN_VDDA +3.3V_RUN_VMM
H5
C10
H12
K6
K7
C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7
F8
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
D4
J5
J11
J12
K5
H10
J6
J7
J8
J9
+1.0V_RUN_VMM
0.01UF_0402_25V7K
12
CV98
12
RV661100K_0402_5%
12
CV617
10U_0603_10V6M
12
PJP33
PAD-OPEN1x1m
1 2
@
CV615 0.1U_0201_10V6K
0.01UF_0402_25V7K
1
12
CV99
2
18P_0402_50V8J
12
CV115
+1.0V_RUN_VMM
0.1U_0201_10V6K
CV100
27MHZ_12PF_X1E000021042600
1 2
BLM15PX181SN1D_2P
10U_0603_10V6M
12
CV101
+3.3V_RUN_VMM
YV2
1
IN
2
GND
LV25
1 2
CV114
UV8A
G1
RxP0
G2
RxN0
F1
RxP1
F2
RxN1
E1
RxP2
E2
RxN2
D1
RxP3
D2
RxN3
H1
RxAUXP
H2
RXAUXN
C2
RxSRCDET
J1
RxHPD
A13
RSTN_IN
B5
VDDIO
B6
VDDIO
B1
NC
A4
SPICS
B3
SPICLK
B4
SPIDI
A3
SPIDO
D14
GPIO0
D13
GPIO1
C14
GPIO2
C13
GPIO3
B14
GPIO4
B13
GPIO5
C1
GPIO6
M12
GPIO7
M13
NC
L3
NC
B2
LP_CTL
A5
LP_EN
K2
RX_STS
L2
TX0_STS
M1
TX1_STS
M2
TX2_STS
K1
XIN
L1
XOUT
VMM3320BJGR_BGA168
Tx0P0
Tx0N0
Tx0P1
Tx0N1
Tx0P2
Tx0N2
Tx0P3
Tx0N3
CAD0
Tx0AUXP
Tx0AUXN
Tx0DDCSCL
Tx0DDCSDA
Tx0HPD
Tx1P0
Tx1N0
Tx1P1
Tx1N1
Tx1P2
Tx1N2
Tx1P3
Tx1N3
CAD1
Tx1AUXP
Tx1AUXN
Tx1DDCSCL
Tx1DDCSDA
Tx1HPD
VGA_VSYNC
VGA_HSYNC
VGA_RP
VGA_RN
VGA_GP
VGA_GN
VGA_BP
VGA_BN
VGA_SCL
VGA_SDA
VGA_DET
VGA_IREF
NC
SSDA
SSCL
NC
RxDDCSDA
NC
NC
NC
RxDDCSCL
8/21 for layout routing
B7
A7
B8
A8
B9
A9
B10
A10
A14
B11
A11
B12
A12
A6
E13
E14
F13
F14
G13
G14
H13
H14
M14
J13
J14
K13
L14
K14
L9
M9
M6
L6
M7
L7
M8
L8
L4
M4
M3
M5
L5
A1
A2
M11
M10
L12
L13
L11
L10
HUB_DP0_AUXP
HUB_DP0_AUXN
HUB_DP0_SCL
HUB_DP0_SDA
HUB_DP1_AUXP
HUB_DP1_AUXN
HUB_DP1_SCL
HUB_DP1_SDA
HUB_VGA_DET
HUB_VGA_IREF
HUB_VGA_NC
I2C_HUB_SDA
I2C_HUB_SCL
HUB_DP1_AUXN
HUB_GPIO6
HUB_SRCDET
HUB_SPI_WP#
HUB_GPIO4
HUB_GPIO5
HUB_DP1_SCL
HUB_DP1_SDA
HUB_GPIO8
HUB_GPIO7
I2C_HUB_SDA
I2C_HUB_SCL
HUB_DP0_SDA
HUB_DP0_SCL
HUB_DP0_AUXN
HUB_SPI_CS#
HUB_SPI_HOLD
HUB_VGA_DET
HUB_VGA_IREF
HUB_DP0_P0 <38>
HUB_DP0_N0 <38>
HUB_DP0_P1 <38>
HUB_DP0_N1 <38>
HUB_DP0_P2 <38>
HUB_DP0_N2 <38>
HUB_DP0_P3 <38>
HUB_DP0_N3 <38>
HUB_DP0_CADET <25,38>
HUB_DP0_AUXP <25>
HUB_DP0_AUXN <25>
HUB_DP0_SCL <25>
HUB_DP0_SDA <25>
HUB_DP0_HPD <38>
HUB_DP1_P0 <38>
HUB_DP1_N0 <38>
HUB_DP1_P1 <38>
HUB_DP1_N1 <38>
HUB_DP1_P2 <38>
HUB_DP1_N2 <38>
HUB_DP1_P3 <38>
HUB_DP1_N3 <38>
HUB_DP1_CADET <25,38>
HUB_DP1_AUXP <25>
HUB_DP1_AUXN <25>
HUB_DP1_SCL <25>
HUB_DP1_SDA <25>
HUB_DP1_HPD <38>
HUB_VGA_VSYNC <25>
HUB_VGA_HSYNC <25>
HUB_VGA_RED <25>
HUB_VGA_GREEN <25>
HUB_VGA_BLUE <25>
HUB_VGA_SCL <25>
HUB_VGA_SDA <25>
T108@ PAD~D
1 2
1 2
1 2
12
12
12
RPV1
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
RPV2
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
1 2
12
12
12
1 2
+3.3V_RUN_VMM
RV821M_0402_5%
RV832.2K_0402_5%
RV841M_0402_5%
RV517@2. 2K_0402_5%
RV518@2. 2K_0402_5%
RV519@2. 2K_0402_5%
RV851M_0402_5%
RV8610K_0402_5%
RV872.2K_0402_5%
RV8810K_0402_5%
RV893.74K_0402_1%
VCC
CLK
CV1020.1U_0402_25V6
CV1030.1U_0402_25V6
CV1040.1U_0402_25V6
CV1050.1U_0402_25V6
CV1060.1U_0402_25V6
CV1070.1U_0402_25V6
CV1080.1U_0402_25V6
CV1090.1U_0402_25V6
CV1100.1U_0402_25V6
CV1110.1U_0402_25V6
+3.3V_RUN_VMM
8
HUB_SPI_HOLD
7
HUB_SPI_CLK
6
HUB_SPI_DO
5
SW1_DP0_P0_C
SW1_DP0_N0_C
SW1_DP0_P1_C
SW1_DP0_N1_C
SW1_DP0_P2_C
SW1_DP0_N2_C
SW1_DP0_P3_C
SW1_DP0_N3_C
SW1_DP0_AUXP_C
SW1_DP0_AUXN_C
HUB_SRCDET
HUB_SPI_WP#
HUB_SPI_CS#
HUB_SPI_CLK
HUB_SPI_DIN
HUB_SPI_DO
HUB_GPIO4
HUB_GPIO5
HUB_GPIO6
HUB_GPIO7
HUB_GPIO8
HUB_GPIO9
VMM3320_LPM_DIS
HUB_LP_EN
CLK_27M_IN
CLK_27M_OUT
0.1U_0201_10V6K
SW1_DP0_P0<23>
SW1_DP0_N0<23>
SW1_DP0_P1<23>
SW1_DP0_N1<23>
SW1_DP0_P2<23>
SW1_DP0_N2<23>
SW1_DP0_P3<23>
SW1_DP0_N3<23>
SW1_DP0_AUXP<23>
SW1_DP0_AUXN<23>
HUB_GPIO9
12
RV731M_0402_5% @
HUB_DP0_AUXP
12
RV741M_0402_5%
HUB_DP1_AUXP
12
RV751M_0402_5%
HUB_VGA_RED
12
RV76150_0402_1%
HUB_VGA_GREEN
12
RV77150_0402_1%
HUB_VGA_BLUE
12
RV78150_0402_1%
VMM3320_LPM_DIS
12
RV79@100K_0402_5%
VMM3320_LPM_DIS
12
RV5162.2K_0402_5% @
CLK_27M_OUT_R
3
OUT
GND
18P_0402_50V8J
4
RV81 2.2K_0402_5%
CV113
12
+3.3V_RUN_VDDIO
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SW1_DP0_HPD<23>
PLTRST_VMM2320#<11>
VMM3320_LPM_DIS<9>
1M_0402_5%
12
RV80
EEPROM
HUB_SPI_CS#
HUB_SPI_DIN
HUB_SPI_WP#
UV9
1
CS#
2
DO(IO1)
3
WP#(IO2)
GND4DI(IO0)
W25X10CVSNIG_SO8
HOLD#(IO3)
VMM2320 Operation power consumption for 1.0V=1.464A (Max)
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP 1.2 MST HUB
DP 1.2 MST HUB
DP 1.2 MST HUB
LA-C621P
LA-C621P
LA-C621P
24 60Thursday, September 24, 2015
24 60Thursday, September 24, 2015
24 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 25
5
Vinafix.com
4
3
2
1
14
13
12
11
10
9
8
+3.3V_RUN_VMM
+3.3V_RUN
RV250 2.2K_0402_5%
RV251 2.2K_0402_5%
D D
0
1
C C
1 2
+3.3V_RUN
+3.3V_RUN
HUB_VGA_SCL
HUB_VGA_RED<24>
HUB_VGA_GREEN<24>
HUB_VGA_BLUE<24>
HUB_VGA_HSYNC<24>
HUB_VGA_VSYNC<24>
HUB_VGA_SDA<24>
HUB_VGA_SCL<24>
DOCKED<23,27,31>
RV121 4.7K_0402_5%
Source
ChanelSEL
MBA=B1
APR/SPR
A=B2
DOCKED
1 2
HUB_VGA_SDA
1 2
VGA SW for MB/DOCK
Use SA00004RS00 as main source
UV16
1
R
2
G
5
B
6
H_SOURCE
7
V_HOURCE
9
SDA_SOURCE
10
SCL_SOURCE
30
SEL
29
TEST
8
Reserved
3
GND
11
GND
28
GND
31
GND
33
GPAD
TS3V713ELRTGR_WQFN32_6X 3~D
5V VDD
VDD
VDD
VDD
H1_OUT
V1_OUT
SDA1
SCL1
H2_OUT
V2_OUT
SDA2
SCL2
16
4
23
32
SW2_VGA1_RED
27
R1
G1
B1
R2
G2
B2
25
22
20
18
12
14
26
24
21
19
17
13
15
SW2_VGA1_GREEN
SW2_VGA1_BLUE
SW2_VGA1_HSYNC
SW2_VGA1_VSYNC
SW2_VGA1_SDA
SW2_VGA1_SCL
0.01UF_0402_25V7K
0.01UF_0402_25V7K
@
@
1
1
CV128
+3.3V_RUN+5V_RUN
CV127
2
2
SW2_VGA2_RED <38>
SW2_VGA2_GREEN <38>
SW2_VGA2_BLUE <38>
SW2_VGA2_HSYNC <38>
SW2_VGA2_VSYNC <38>
SW2_VGA2_SDA <38>
SW2_VGA2_SCL <38>
+3.3V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
CV125
CV126
2
2
+5V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
2
CV144
CV124
2
AUX/DDC SW for DPC to E-DOCK
UV12
1
HUB_DP0_AUXP_C
HUB_DP0_AUXP<24>
HUB_SW1_AUXP<38>
HUB_DP0_AUXN<24>
HUB_SW1_AUXN<38>
HUB_DP0_CADET<24,38>
12
CV122 0.1U_0402_25V6
HUB_DP0_AUXN_C
12
CV123 0.1U_0402_25V6
HUB_DP0_CADET
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
100K_0402_5%
12
13
D
2
G
S
RV91
HUB_DP0_CADETN
L2N7002WT1G_SC-70-3
QV10
VCC
BE3
A3
B3
BE2
A2
B2
AUX/DDC SW for DPB to E-DOCK
PJDLC05C_SOT23-3
2
3
@EMC@
DV5
1
SW2_VGA1_RED
SW2_VGA1_GREEN
SW2_VGA1_BLUE
12
12
B B
RV32
150_0402_1%
A A
12
RV33
RV34
150_0402_1%
150_0402_1%
1
1
2
2
CV52
CV51
2.2P_0402_50V8C
SW2_VGA1_SDA
SW2_VGA1_SCL
SW2_VGA1_HSYNC
EMC@
SW2_VGA1_VSYNC
EMC@
1 2
LV16 BLM15B B470SN1D_2P
EMC@
1 2
LV17 BLM15B B470SN1D_2P
EMC@
1 2
LV18 BLM15B B470SN1D_2P
EMC@
1
2
CV53
2.2P_0402_50V8C
2.2P_0402_50V8C
+CRT_VCC
12
12
RV36
RV35
2.2K_0402_5%
2.2K_0402_5%
1 2
LV19 BLM15A G121SN1D_L0402_2P
1 2
LV20 BLM15A G121SN1D_L0402_2P
1
CV54
@
2
3.3P_0402_50V8C
12
12
RV37
RV38
@
@
1K_0402_5%
1K_0402_5%
1
@
CV58
1
@
CV59
2
2
22P_0402_50V8J
22P_0402_50V8J
1
CV55
@
2
3.3P_0402_50V8C
PJDLC05C_SOT23-3
2
3
1
1
CV56
@
2
3.3P_0402_50V8C
+5V_RUN
@EMC@
DV6
1
IN
GND2OUT
40mils
UV4
AP2330W-7_SC59-3
3
+CRT_VCC
@
T87 PAD~D
VGA1_RED_L
VGA1_GREEN_L
VGA1_HSYNC_L
VGA1_BLUE_L
VGA1_VSYNC_L
M_ID2#
0.1U_0402_25V6
CV57
1
2
1
CV50
1U_0402_6.3V6K
2
JCRT-11
JCRT1
6
11
1
7
12
2
8
13
3
9
14
G
4
G
10
15
5
FUTUR_061-D531-0207
CONN@
HUB_DP1_AUXP<24>
HUB_SW2_AUXP<38>
HUB_DP1_AUXN<24>
HUB_SW2_AUXN<38>
16
17
HUB_DP1_CADET<24,38>
HUB_DP1_AUXP_C
12
CV119 0.1U_0402_25V6
HUB_DP1_AUXN_C
12
CV120 0.1U_0402_25V6
HUB_DP1_CADET
1 2
RV508 1M_0402_5%
1 2
RV509 1M_0402_5%
HUB_DP1_CADET
HUB_DP0_CADET
UV11
1
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
100K_0402_5%
12
RV90
L2N7002WT1G_SC-70-3
13
D
QV9
2
G
S
DPB_CA_DET
DPC_CA_DET
14
VCC
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
HUB_DP1_CADETN
DP
0
0
HDMI
1
1
1 2
0.1U_0201_10V6K
HUB_DP0_SCL <24>
HUB_DP0_SDA <24>
+3.3V_RUN_VMM
HUB_DP1_SCL <24>
HUB_DP1_SDA <24>
CV121
CV118
1 2
0.1U_0201_10V6K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DP SW
DP SW
DP SW
LA-C621P
LA-C621P
LA-C621P
25 60Thursday, September 24, 2015
25 60Thursday, September 24, 2015
25 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 26
5
Vinafix.com
LINK 50398-04041-001 DONE
JEDP1
1
2
3
4
5
6
7
8
9
10
11
D D
C C
+BL_PWR_SRC +3.3V_RUN+3.3V_RUN +3.3V_TSP
0.1U_0603_50V7K
12
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
ACES_50398-04041-001
CONN@
@
CV7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+LCDVDD
+3.3V_TSP
USB20_N2_R
USB20_P2_R
LV1
EMC@
DISP_ON
TOUCH_SCREEN_DET#
EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
EDP_TXP1_C
EDP_TXN1_C
0.1U_0201_10V6K
1
@
CV8
2
TOUCH_SCREEN_PD# <12>
+3.3V_RUN
+3.3V_CAM
CAM_MIC_CBL_DET# <12>
Pin15: LOOP_BACK
+BL_PWR_SRC
1 2
EDP_HPD <6>
LCD_TST <31>
+LCDVDD
LCD_CBL_DET# <9>
BIA_PWM
BLM15BB221SN1D_2P
CV1 0.1U_0402_25V6
CV2 0.1U_0402_25V6
CV3 0.1U_0402_25V6
CV4 0.1U_0402_25V6
CV5 0.1U_0402_25V6
CV6 0.1U_0402_25V6
+3.3V_CAM +3.3V_TSP
0.1U_0201_10V6K
1
@
CZ1
2
4
100P_0402_50V8J
12
12
CA5@EMC@
TOUCH_SCREEN_DET# <12>
12
12
12
12
12
12
0.1U_0201_10V6K
1
@
CZ2
2
DMIC0 <30>
DMIC_CLK0 <30>
100P_0402_50V8J
CA6@EMC@
EDP_AUXN <6>
EDP_AUXP <6>
EDP_TXP0 <6>
EDP_TXN0 <6>
EDP_TXP1 <6>
EDP_TXN1 <6>
+3.3V_RUN
3
OUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events
223
1
3
1

T
USB20_N9_R
USB20_P9_R
PESD5V0U2BT_SOT23-3
@EMC@
DV4
ESD depop location
TOUCH_SCREEN_DET#
+3.3V_RUN
10K_0402_5%
12
RV623
EMC@
LV27
1
1
4
4
MCM1012B900F06BP_4P
2
2
3
3
2
USB20_N9 <10>
USB20_P9 <10>
+PWR_SRC
IR CAM Conn
IR_CAM_DET#<9>
1
JIR1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50450-0067N-P01
CONN@
For Touchscreen
0.1U_0201_10V6K
1
@
CA7
2
10K_0402_5%
12
RV6
QV8
LP2301ALT1G_SOT23-3
123
D
S
G
Close to JEDP1.17~19
BIA_PWM DISP_ON
4.7K_0402_5%
12
RV1
B B
WebCAM
3.3V_CAM_EN#<11>
USB20_P2<10>
A A
Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
DV1
3
1
2
BAT54CW_SOT323-3
EDP_BIA_PWM <6>
BIA_PWM_EC <32>
4.7K_0402_5%
12
RV2
Backlight POWER
+3.3V_CAM +3.3V_RUN
MCM1012B900F06BP_4P
4
4
1
1
LZ1
EMC@
QZ1
LP2301ALT1G_SOT23-3
123
D
S
G
USB20_P2_R
3
3
USB20_N2_R
2
2
+PWR_SRC
1000P_0402_50V7K
12
CV11
0.01U_0402_50V7K
1
CV374
2
DV2
1
BAT54CW_SOT323-3
S
4 5
270K_0402_5%
12
RV4
BL_PWR_SRC_ON
1 2
RV5 47K_0402_5%
EN_INVPWR<32>USB20_N2<10>
3
2
QV1
D
6
2
1
G
AO6405_TSOP6
3
QV2
L2N7002WT1G_SC-70-3
123
D
S
G
PANEL_BKLEN <6>
PANEL_BKEN_EC <31>
+BL_PWR_SRC
0.1U_0603_50V7K
12
CV12
LCDVDD POWER
10U_0603_10V6M
TS_EN<9>
@
CV9
LCD_VCC_TEST_EN<31>
ENVDD_PCH<6,32>
2
G
+LCDVDD +EDP_VDD
12
L2N7002WT1G_SC-70-3
13
D
QV7
S
PJP29
1 2
PAD-OPEN1x1m
BAT54CW_SOT323-3
+3.3V_ALW
5
4
0.01UF_0402_25V7K
@
CV10
12
100K_0402_5%
RV3
1 2
VOUT
GND
/OC
EN_LCDPWR
UV24
VIN
EN
1
2
DV3
2
3
3
G524B1T11U_SOT23-5
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
LA-C621P
LA-C621P
LA-C621P
26 60Thursday, September 24, 2015
26 60Thursday, September 24, 2015
26 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 27
+3.3V_LAN
Vinafix.com
1 2
RL1@ 10K_0402_5%
1 2
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@
1 2
RL70@ 10K_0402_5%
D D
PM_LANPHY_ENABLE<11>
+0.9V_LAN
0.1U_0201_10V6K
22U_0603_6.3V6M
12
C C
B B
+3.3V_LAN
+3.3V_LAN
A A
0.1U_0201_10V6K
CL9
1
1
CL12
2
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
SW_LAN0_ACTLED_YEL#
12
RL29
1M_0402_5%
SW_LAN0_100_ORG#
12
RL30
1M_0402_5%
SW_LAN0_10_GRN#
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
CLKREQ_PCIE#4
12
LAN_WAKE#
@
RL7 0_0402_5%
0.1U_0201_10V6K
CL11
CL10
1
1
2
2
DMN65D8LDW-7_SOT363-6
1
DMN65D8LDW-7_SOT363-6
DMN65D8LDW-7_SOT363-6
1
DMN65D8LDW-7_SOT363-6
5
1 2
LAN CKLT0.7
0.1U_0201_10V6K
CL8
+3.3V_LAN
1
B
2
A
QL1A
2
SYS_LED_MASK#
QL1B
5
SYS_LED_MASK#
QL2A
2
SYS_LED_MASK#
QL2B
5
5
27P_0402_50V8J
1 2
@
CL15
1 2
0.1U_0201_10V6K
5
P
4
O
G
UL2
TC7SH08FU_SSOP5~D
3
LAN_ACTLED_YEL#
6
LED_100_ORG#
34
LED_10_GRN#
6
34
+3.3V_LAN
10K_0402_5%
12
RL5@
10K_0402_5%
12
RL9@
XTALO_R
1 2
@
RL34 0_0402_5%
3
OUT
4
GND
CL13
25MHZ_18PF_7V25000034
WLAN_DISBL# <31>
SYS_LED_MASK# <31,40>
CLKREQ_PCIE#4<11>
PLTRST_LAN#<11>
CLK_PCIE_P4<11>
CLK_PCIE_N4<11>
PCIE_PRX_DTX_P9<10>
PCIE_PRX_DTX_N9<10>
PCIE_PTX_DRX_P9<10>
PCIE_PTX_DRX_N9<10>
SML0_SMBCLK<8>
SML0_SMBDATA<8>
LAN_WAKE#<11,32>
SMBus Device Address 0xC8
YL1
IN
GND
LAN_DISABLE#_R<31>
T88@ PAD~D
T89@ PAD~D
12
RL11
1
2
1M_0402_5%
1 2
0.1U_0201_10V6K
12
CL16
0.1U_0201_10V6K
12
CL20
12
CL1 0.1U_0402_25V6
12
CL2 0.1U_0402_25V6
1 2
CL5 0.1U_0402_25V6
1 2
CL6 0.1U_0402_25V6
27P_0402_50V8J
CL14
SW_LAN0_MDIN3
SW_LAN0_MDIP3
SW_LAN0_MDIN2
SW_LAN0_MDIP2
0.1U_0201_10V6K
SW_LAN0_MDIN1
12
CL17
SW_LAN0_MDIP1
SW_LAN0_MDIN0
0.1U_0201_10V6K
12
CL21
SW_LAN0_MDIP0
4
CLKREQ_PCIE#4
PCIE_PRX_C_DTX_P9
PCIE_PRX_C_DTX_N9
PCIE_PTX_C_DRX_P9
PCIE_PTX_C_DRX_N9
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
LAN_TEST_EN
1K_0402_5%
3.01K_0402_1%
12
12
RL12
4
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTALO
XTAL_OUT
10
XTALI
XTAL_IN
30
TEST_EN
12
RBIAS
RL13
1
2
3
4
5
6
7
8
9
10
11
12
WGI219LM-QREF- A0_QFN48_6X6~D
change to SA000081G0L, S IC A32 WGI219LM QREF A0 QFN 48P PHY
TL1
TD1+
TD1-
TDCT1
TDCT2
TD2+
TD2-
TD3+
TD3-
TDCT3
TDCT4
TD4+
TD4-
MHPC_NS692417
PCIE
SMBUS
JTAG LED
GND
GND
ASSIS
CHASSIS
CH
MDI
RSVD_VCC3P3_1
1:1
1:1
1:1
1:1
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SVR_EN_N
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
LAN_MDIN0
14
LAN_MDIP1
17
LAN_MDIN1
18
LAN_MDIP2
20
LAN_MDIN2
21
LAN_MDIP3
23
LAN_MDIN3
24
6
+RSVD_VCC3P3_1
1
5
4
15
19
29
47
46
37
43
11
40
22
16
8
+REGCTL_PNP10RES_BIAS
7
49
LAN_MDIP0
13
Place CL3, CL4 and LL1 close to UL1
TX1+
TX1-
TXCT1
TXCT2
TX2+
TX2-
TX3+
TX3-
TXCT3
TXCT4
TX4+
TX4-
1 2
CL22 1500P_1808_2KV7K
EMC@
3
Layout Notice : Place bead as
close UL1 as possible
VCT_LAN_R1
8/28 schematic review
24
23
22
21
20
19
18
17
16
15
14
13
3
1 2
RL71 2.2_0603_5%EMC@
1 2
RL72 2.2_0603_5%EMC@
1 2
RL73 2.2_0603_5%EMC@
1 2
RL74 2.2_0603_5%EMC@
1 2
RL75 2.2_0603_5%EMC@
1 2
RL76 2.2_0603_5%EMC@
1 2
RL77 2.2_0603_5%EMC@
1 2
RL78 2.2_0603_5%EMC@
12
RL3 0_0402_5%@
RL6 4.7K_0402_5%
+3.3V_LAN_OUT
+0.9V_LAN
1 2
Idc_min=500mA
DC
R=100mohm
RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIN1
RJ45_MDIP1
RJ45_MDIN0
RJ45_MDIP0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
0.1U_0201_10V6K
RL8@ 0_0603_5%
CL7
1
2
LL14.7UH_BRC2012T4R7MD_20%
1
2
Z2805
Z2807
Z2806
Z2808
+GND_CHASSIS
use 40mil trace if necessary
+0.9V_LAN
0.1U_0201_10V6K
CL3
12
10U_0603_10V6M
12
RL15 75_0402_1%
12
@
CL4
12
RL16 75_0402_1%
LAN_MDIP0_L
LAN_MDIN0_L
LAN_MDIP1_L
LAN_MDIN1_L
LAN_MDIP2_L
LAN_MDIN2_L
LAN_MDIP3_L
LAN_MDIN3_L
+3.3V_LAN
12
12
RL18 75_0402_1%
RL17 75_0402_1%
+3.3V_LAN
+3.3V_LAN_OUT
22U_0805_6.3V6M
1
2
LAN CKLT0.7
CL28
2
+3.3V_LAN
1
2
LAN_MDIN3_L
LAN_MDIP3_L
LAN_MDIN2_L
LAN_MDIP2_L
LAN_MDIN1_L
LAN_MDIP1_L
LAN_MDIN0_L
LAN_MDIP0_L
DOCKED<23,25,31>
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
LAN ANALOG SWITCH
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CL26
CL25
1
2
CL27
1
2
UL4
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5
8
14
21
30
39
VDD
VDD
VDD
VDD
For Layout routing , change port mapping
Place CL28 close to UL1.5
470P_0402_50V7K
1
12
CL18
2
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
LED_10_GRN# LED_10_GRN_R#
LED_100_ORG# LED_100_ORG_R#
1 2
RL14 150_0402_5%
RJ45_MDIN3
RJ45_MDIP3
RJ45_MDIN1
RJ45_MDIN2
RJ45_MDIP2
RJ45_MDIP1
RJ45_MDIN0
RJ45_MDIP0
1 2
RL19 150_0402_5%
1 2
RL20 150_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
4
VDD
0.1U_0201_10V6K
38
VDD
VDD
B0+
37
B0-
34
B1+
33
B1-
29
B2+
28
B2-
25
B3+
24
B3-
17
LEDB0
18
LEDB1
41
LEDB2
36
C0+
35
C0-
32
C1+
31
C1-
27
C2+
26
C2-
23
C3+
22
C3-
19
LEDC0
20
LEDC1
40
LEDC2
+3.3V_LAN
CL19
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
1: TO DOCK
DOCKED
0: TO RJ45
SW_LAN0_MDIN3
SW_LAN0_MDIP3
SW_LAN0_MDIN2
SW_LAN0_MDIP2
SW_LAN0_MDIN1
SW_LAN0_MDIP1
SW_LAN0_MDIN0
SW_LAN0_MDIP0
SW_LAN0_ACTLED_YEL#
SW_LAN0_100_ORG#
SW_LAN0_10_GRN#
SW_LAN1_MDIN3 <38>
SW_LAN1_MDIP3 <38>
SW_LAN1_MDIN2 <38>
SW_LAN1_MDIP2 <38>
SW_LAN1_MDIN1 <38>
SW_LAN1_MDIP1 <38>
SW_LAN1_MDIN0 <38>
SW_LAN1_MDIP0 <38>
SW_LAN1_ACTLED_YEL# <38>
SW_LAN1_100_ORG# <38>
SW_LAN1_10_GRN# <38>
RJ45 LOM circuit
+3.3V_LAN:20mils
JLOM1
CONN@
10
Yellow LED-
9
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
SANTA_130456-511
Link 130456-511 DONE
LAN
LAN
LAN
LA-C621P
LA-C621P
LA-C621P
1
GND
GND
GND
GND
27 60Thursday, September 24, 2015
27 60Thursday, September 24, 2015
27 60Thursday, September 24, 2015
17
16
15
14
1.0
1.0
1.0
Page 28
A
Vinafix.com
+3.3V_MMI_IN+3.3V_RUN
PJP26
1 2
1 1
2 2
+3.3V_MMI_AUX +3.3V_MMI_IN
+3.3V_MMI_AUX
PAD-OPEN1x2m
1 2
@
R274 0_0603_5%
MEDIACARD_IRQ#
1 2
RR19 10K_0402_5%
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
7/18 Vender suggest.
B
PCH_PLTRST#_AND<11,29,33,35>
CLKREQ_PCIE#5<11>
CLK_PCIE_P5<11>
PCIE_PTX_DRX_P10<10>
PCIE_PTX_DRX_N10<10>
PCIE_PRX_DTX_P10<10>
PCIE_PRX_DTX_N10<10>
CR24 0.1U_0402_25V6
CR25 0.1U_0402_25V6
CR26 0.1U_0402_25V6
CR27 0.1U_0402_25V6
+1.2V_LDO
CR13 close to UR2.10
CR9 CR10 close to UR2.14
4.7U_0603_6.3V6K
CR9
12
CLK_PCIE_N5<11>
1 2
1 2
1 2
1 2
MEDIACARD_IRQ#<8>
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
CR13
CR10
2
2
PCIE_PTX_C_DRX_P10
PCIE_PTX_C_DRX_N10
PCIE_PRX_C_DTX_P10
PCIE_PRX_C_DTX_N10
+1.8V_RUN_CARD
SD/MMCCD#
+RREF
12
RR20
6.2K_0402_1%
C
+3.3V_MMI_AUX
0.1U_0201_10V6K
1
CR8
2
UR2
1
PERST#
2
CLK_REQ#
5
REFCLKP
6
REFCLKN
3
HSIP
4
HSIN
7
HSOP
8
HSON
32
WAKE#
31
MS_INS#
30
SD_CD#
10
AV12
14
DV12S
13
SD_VDD2
9
RREF
D
+3.3V_MMI_IN
10U_0402_6.3V6M
1
2
27
11
CARD_3V3
3V3_IN
3V3aux
DV33_18
RTS5242
SD_LN1_P
SD_LN1_M
SD_LN0_P
SD_LN0_M
E-PAD
RTS5242-GR_QFN32_4X4
33
0.1U_0201_10V6K
CR36
SDREG2
GPIO
1
2
SP1
SP2
SP3
SP4
SP5
SP6
SP7
CR43
12
+DV33_18
18
15
SD/MMCDAT1/RCLK-
16
SD/MMCDAT0/RCLK+
17
SD/MMCCLK
19
SD/MMCCMD
20
SD/MMCDAT3
21
SD/MMCDAT2
29
SDWP
SD_UHS2_D1P
22
SD_UHS2_D1N
23
SD_UHS2_D0P
26
SD_UHS2_D0N
25
24
+SDREG2
28
SD_GPIO
+3.3V_RUN_CARD
@
RR21 0_0402_5%
@
RR22 0_0402_5%
RR1EMC@ 10_0402_5%
@
RR23 0_0402_5%
@
RR17 0_0402_5%
@
RR18 0_0402_5%
7/18 Vender suggest
1 2
CR35 1U_0402_6.3V6K
12
RR1610K_0402_5%
1 2
CR37 1U_0402_6.3V6K
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_MMI_AUX
SD/MMCDAT1/RCLK-_R
SD/MMCDAT0/RCLK+_R
SD/MMCCLK_R
SD/MMCCMD_R
SD/MMCDAT3_R
SD/MMCDAT2_R
@EMC@
5P_0402_50V8C
12
CR23
EMI depop location
10U_0402_6.3V6M
1
CR42
2
E
HOST_SD_WP#
3 3
4 4
H
igh
Low
SDWP_Q SDWP
High
High
Low
Low
High
High
Low
High
STATUS
Write Protect(SD LOCK)
Write Enable
Write Protect(SD& FW LOCK)
Write Protect(FW LOCK)
L2N7002WT1G_SC-70-3
SDWP
HOST_SD_WP#<9>
1 3
QR1
SDWP_Q
D
S
G
2
+3.3V_RUN_CARD +1.8V_RUN_CARD
2
CR39
1 2
CR38
1
0.1U_0201_10V6K
4.7U_0603_6.3V6K
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
JSD1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
2
CR40
CR41
1 2
1
0.1U_0201_10V6K
4.7U_0603 _6.3V6K
SD/MMCCMD_R
SD/MMCCLK_R
SD/MMCCD#
SDWP_Q
SD/MMCDAT0/RCLK+_R
SD/MMCDAT1/RCLK-_R
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P
SD_UHS2_D0N
SD_UHS2_D1P
SD_UHS2_D1N
4
VDD/VDD1
14
VDD2
2
CMD
5
CLK
18
CARD DETECT
19
WRITE PROTEC
7
DAT0/RCLK+
8
DAT1/RCLK-
9
DAT2
1
CD/DAT3
11
D0+
12
DO-
16
D1+
15
D1-
3
VSS1
6
VSS2
10
VSS3
13
VSS4
VSS517GND7
T-SOL_156-2000302608_NR
CONN@
GND1
GND2
GND3
GND4
GND5
GND6
20
21
22
23
24
25
26
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Card Reader
Card Reader
Card Reader
LA-C621P
LA-C621P
LA-C621P
E
28 60Thursday, September 24, 2015
28 60Thursday, September 24, 2015
28 60Thursday, September 24, 2015
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 29
5
Vinafix.com
+3.3V_WW AN
NGFF slot B Key B
WWAN_PW R_EN
1 2
RZ43@ 0_0402_5%
JNGFF2
SLOT2_CONFIG_3<31>
USB20_P10<10>
USB20_N10<10>
D D
PCIE_PTX_DRX_N3<10 >
PCIE_PTX_DRX_P3<10>
C C
+3.3V_WW AN
12
CZ58 0.1U_0402_25V6
CZ59 0.1U_0402_25V6
.047U_0402_16V7K
.047U_0402_16V7K
12
CZ51
CZ52
SLOT2_CONFIG_0<31>
WWAN_W AKE#<31>
1 2
1 2
SLOT2_CONFIG_1<31>
SLOT2_CONFIG_2<31>
33P_0402_50V8J
12
CZ53
USB3_PRX_L_DTX_N5
USB3_PRX_L_DTX_P5
USB3_PTX_L_DRX_N5
USB3_PTX_L_DRX_P5
PCIE_PRX_DTX_N3<10 >
PCIE_PRX_DTX_P3<10>
CLK_PCIE_N0<11>
CLK_PCIE_P0<11>
22U_0603_6.3V6M
12
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
33P_0402_50V8J
12
CZ54
47P_0402_50V8J
150U_B2_6.3VM_R35M
1
1
@
+
CZ55
CZ57
2
2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
GND
BELLW_80149-4221
80149-4221 LINK DONE
@
CZ105
WWAN_RADIO_DIS#<31>
HW_GPS_DISABLE#<31>
CONN@
4
3
2
1
NGFF slot A Key A
80148-3221&80148-4221 Footprint the same
80148-3221&80148-4221 Footprint the same
80148-3221&80148-4221 Footprint the same80148-3221&80148-4221 Footprint the same
JNGFF1
CONN@
+3.3V_WW AN
2
2
4
4
WWAN_PW R_EN
6
6
WWAN_RADIO_DIS#_R
8
8
10
10
12
12
14
14
16
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
GND
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
HW_GPS_DISABLE#_R
UIM_RESET
UIM_CLK
UIM_DATA
ISH_I2C2_SCL_R
ISH_I2C2_SDA_R
RZ76 0_0402_5%
@
RZ77 0_0402_5%
@
PCH_PLTRST#_AND
PCIE_WAKE#
SIM_DET
+SIM_PWR
12
12
9/24: Reserve for embedded location ,refer Intel PDG 0.9
CLKREQ_PCIE#0 <11>
ISH_I2C2_SCL <9>
ISH_I2C2_SDA <9>
WLAN
WIGI
SW1_DP1_N3<23>
SW1_DP1_P3<23>
SW1_DP1_N2<23>
SW1_DP1_P2<23>
PCIE_PTX_DRX_P5< 10>
PCIE_PTX_DRX_N5<10>
PCIE_PTX_DRX_P6< 10>
PCIE_PTX_DRX_N6<10>
USB20_P8<10>
USB20_N8<10>
1 2
1 2
CV145 0.1U_0402_25V 6
CV146 0.1U_0402_25V 6
1 2
1 2
CV148 0.1U_0402_25V 6
CV147 0.1U_0402_25V 6
SW1_DP1_HPD<23>
1 2
CZ13 0.1U_0402_25V6
1 2
CZ14 0.1U_0402_25V6
PCIE_PRX_DTX_P5< 10>
PCIE_PRX_DTX_N5<10>
CLK_PCIE_P1<11>
CLK_PCIE_N1<11>
CLKREQ_PCIE#1<11>
PCIE_WAKE#<31,35>
1 2
CZ21 0.1U_0402_25V6
1 2
CZ22 0.1U_0402_25V6
PCIE_PRX_DTX_P6< 10>
PCIE_PRX_DTX_N6<10>
CLK_PCIE_P2<11>
CLK_PCIE_N2<11>
SW1_DP1_N3_C
SW1_DP1_P3_C
SW1_DP1_N2_C
SW1_DP1_P2_C
PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5
PCIE_WAKE#
PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
GND
BELLW_80148-4221
BELLW_80148-4221 LINK DONE
1 2
DZ5
RB751S40T1G_SOD523-2
1 2
DZ6
RB751S40T1G_SOD523-2
WWAN_RADIO_DIS#_R
HW_GPS_DISABLE#_R
DZ1
WLAN_WIGIG60GHZ_DIS#_R
WLAN_WIGIG60GHZ_DIS#<31>
1 2
RB751S40T1G_SOD523-2
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
GND
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
+3.3V_WLAN
+3.3V_WLAN
1
2
0.1U_0201_10V6K
@
SW1_DP1_AUXN_C
SW1_DP1_AUXP_C
SW1_DP1_N1_C
SW1_DP1_P1_C
SW1_DP1_N0_C
SW1_DP1_P0_C
WIGIG_32KHZ
PCH_PLTRST#_AND
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
ISH_UART0_RXD_R
ISH_UART0_TXD_R
ISH_UART0_CTS#_R
ISH_UART0_RTS#_R
PCH_PLTRST#_AND
PCIE_WAKE#
@
@
@
@
12
12
CV1500.1U_0402_25V6
CV1490.1U_0402_25V6
12
12
CV1520.1U_0402_25V6
CV1530.1U_0402_25V6
12
12
CV1560.1U_0402_25V6
CV1570.1U_0402_25V6
PCH_CL_RST1# < 8>
PCH_CL_DATA1 <8>
PCH_CL_CLK1 <8>
@
RZ78 0_0402_5%
RZ79 0_0402_5%
RZ80 0_0402_5%
RZ81 0_0402_5%
12
RZ56 0_0402_5%
PCH_PLTRST#_AND <11,28,33,35>
12
12
12
12
CLKREQ_PCIE#2 <11>
9/24: Reserve for embedded location ,refer Intel PDG 0.9
.047U_0402_16V7K
12
CZ20
CZ15
0.1U_0201_10V6K
.047U_0402_16V7K
12
CZ16
0.1U_0201_10V6K
1
1
CZ17
CZ18
2
2
SW1_DP1_AUXN <23>
SW1_DP1_AUXP <23>
SW1_DP1_N1 < 23>
SW1_DP1_P1 <23>
SW1_DP1_N0 < 23>
SW1_DP1_P0 <23>
SUSCLK <11,35>
ISH_UART0_RXD <9>
ISH_UART0_TXD <9>
ISH_UART0_CTS# <9>
ISH_UART0_RTS# <9>
4.7U_0603_6.3V6K
47P_0402_50V8J
1
12
CZ19
2
@
CZ106
BT_RADIO_DIS#_R
Power Rating TBD
PWR
Rail
+3.3V
Voltage
Tolerance
Primary Power Aux Power
Peak Normal Normal
1 2
1 2
USB3_PRX_L_DTX_P5
USB3_PRX_L_DTX_N5
USB3_PTX_L_DRX_N5
SIM Card Push-Push
+SIM_PWR
1U_0402_6.3V6K
C263
UIM_RESET
12
JSIM1
1
VCC
2
RST
3
CLK
4
RFU1
10
GND
11
GND
12
GND
13
GND
T-SOL_5-991503004000-6
CONN@
DTSW
RFU2
5
GND
6
VPP
7
I/O
8
9
14
GND
15
GND
16
GND
UIM_DATAUIM_CLK
SIM_DET_R SIM_DET
T-SOL_5-991503004000-6 LINK DONE
BT_RADIO_DIS#<31>
1 2
@
RI31 0_0 402_5%
1 2
DZ2
RB751S40T1G_SOD523-2
33P_0402_50V8J
@EMC@
12
CZ67
1 2
@
RI27 0_0402_5%
1 2
@
RI28 0_0402_5%
@
@
RI30 0_0 402_5%
USB3_PRX_DTX_P5< 10>
USB3_PRX_DTX_N5<10>
USB3_PTX_DRX_P5<10>
B B
A A
USB3_PTX_DRX_N5<10>
UIM_RESET
UIM_CLK
UIM_DATA
USB3_PTX_C_DRX_P5 USB3_PTX_L_DRX_P5
CI30 0.1 U_0402_25V612RI29 0_0 402_5%
USB3_PTX_C_DRX_N5
12
CI29 0.1 U_0402_25V6
33P_0402_50V8J
@EMC@
33P_0402_50V8J
@EMC@
12
12
CZ65
CZ66
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
NGFF Card
NGFF Card
NGFF Card
LA-C621P
LA-C621P
LA-C621P
29 60Thursday, September 24, 2015
29 60Thursday, September 24, 2015
29 60Thursday, September 24, 2015
1
Title
Title
For RF team request
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1.0
1.0
1.0
Page 30
2
Vinafix.com
1
1W x 1ch, 4ohm (Transducer spec is 8O hm/0.5Watt per unit, there are two transducer units in one speaker box.)
Internal Speakers Header
INT_SPK_L+
INT_SPK_LÂINT_SPK_R+
INT_SPK_R-
B B
40 mils trace keep 20 mil spacing
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
12
12
CA22@EMC@
CA23@EMC@
Close to UA1
1 2
LA6 BLM15PX330SN1D_2PEMC@
1 2
LA7 BLM15PX330SN1D_2PEMC@
1 2
LA8 BLM15PX330SN1D_2PEMC@
1 2
LA9 BLM15PX330SN1D_2PEMC@
1000P_0402_50V7K
12
CA24@EMC@
CA19@EMC@
INT_SPKR_L+
INT_SPKR_LÂINT_SPKR_R+
INT_SPKR_R-
L03ESDL5V0CC3-2_SOT23-3
2
2
3
3
@EMC@
DA6
1
1
L03ESDL5V0CC3-2_SOT23-3
@EMC@
DA7
JSPK1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
ACES_50271-0040N-001
CONN@
Close to UA1 pin6
HDA_BIT_CLK_R
33_0402_5%
12
RA17@EMC@
10P_0402_50V8J
12
CA33@EMC@
+3.3V_RUN_AUDIO
Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.
13
D
2
QA1
G
S
L2N7002WT1G_SC-70-3
100K_0402_5%
12
RA28
6
1
12
1 2
RA38 100K_0402_5%
200K_0402_5%
12
RA27
100K_0402_5%
12
34
5
QA3B
DMN65D8LDW-7_SOT363-6
0.1U_0402_25V6
CA41
@
RA26
12
QA3A
AUD_SENSE_A
100K_0402_5%
RA29
AUD_SENSE_B
2
Place closely to Pin 13.
Place closely to Pin 14 for DOCK only
A A
DMN65D8LDW-7_SOT363-6
BCLK: Audio serial data bus bi t clock input/output
LRCK: Audio serial data bus wo rd clock input/output
AUD_NB_MUTE#<31>
RA18 10K_0402_5%
AUD_HP_NB_SENSE <31>
Add for solve
pop noise and
detect issue
+3.3V_RUN_AUDIO
DOCK_MIC_DET <31>DOCK_HP_DET<31>
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
+5V_RUN_AUDIO
Reserve for support D3 cold
AUD_PWR_EN<9>
+5V_RUN
+5V_ALW
+3.3V_RUN
UZ5
@
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
EM5209VF_SON14_2X3
VOUT1
VOUT1
VOUT2
GPAD
CT1
GND
CT2
+5V_RUN_AUDIO_UZ5
14
13
12
11
10
9
+3.3V_RUN_AUDIO_UZ5
8
15
PJP31
@
+3.3V_RUN +3.3V_RUN_AUDIO
PAD-OPEN1x3m
1 2
1 2
@
CZ89 0.1U_0201_10V6K
1 2
220P_0402_50V7K
CZ90
@
1 2
1000P_0402_50V7K
CZ91
@
PJP30
@
1 2
PAD-OPEN1x1m
1 2
@
CZ92 0.1U_0201_10V6K
2
1 2
+5V_RUN
+3.3V_RUN_AUDIO
HDA_BIT_CLK_R<12>
HDA_SDOUT_R<12>
HDA_SYNC_R<12>
HDA_SDIN0<12>
HDA_RST#_R<12>
DAI_12MHZ#<38>
DAI_BCLK#<38>
DAI_DO#<38>
DAI_LRCK#<38>
DAI_DI<38>
PJP9
1 2
PAD-OPEN1x3m
PJP10
1 2
PAD-OPEN1x1m
+3.3V_RUN_AUDIO
CA11 close to pin9
CA10 close to pin3
0.1U_0201_10V6K
CA10
CA11
1
1
2
2
Place RA9 close to codec
1 2
RA9 33_0402_5%
1 2
RA30EMC@ 22_0402_5%
1 2
RA31EMC@ 22_0402_5%
1 2
RA32 33_0402_5%
1U_0603_10V6K
12
CA31
1 2
1 2
1 2
+5V_RUN_AUDIO
0.1U_0201_10V6K
CA50
4.7U_0603_6.3V6K
12
AUD_NB_MUTE#
place at AGND and DGND plane
@
RA35 0_0402_5%
@
RA36 0_0402_5%
@
RA37 0_0402_5%
2.5A
0.5A
EN_I2S_NB_CODEC#<31>
HDA_BIT_CLK_R
HDA_SDOUT_R
HDA_SDIN0_R
HDA_RST#_R
I2S_MCLK
I2S_BCLK
I2S_DO
Place RA32 close to codec
100K_0402_5%
12
8/4
4.7U_0603_6.3V6K
CA51
4.7U_0603_6.3V6K
RA44
12
12
1 2
PAD-OPEN1x1m
SLEEVE
34
5
QA2B
DMN65D8LDW-7_SOT363-6
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
MIC1_L
MIC1_R
CA52
12
PJP6
+RTC_CELL
QA2A
DMN65D8LDW-7_SOT363-6
UA1
1
I2S I/F Float
3
DVDD_IO
9
DVDD
6
BCLK
5
SDATA-OUT
10
SYNC
8
SDATA-IN
11
RESET#
15
I2S_MCLK
16
I2S_SCLK
17
I2S_DOUT
18
I2S_LRCK
24
I2S_DIN
19
MIC1-L(PORT-B-L)
20
MIC1-R(PORT-B-R)
48
EAPD+PD
21
LDO1-CAP
39
LDO2-CAP
7
LDO3-CAP
CA53
4.7U_0603_6.3V6K
49
GND
ALC3235-CG_MQFN48_6X6
RING2
AUD_HP_OUT_L
AUD_HP_OUT_R
SLEEVE
100K_0402_5%
12
RA21
6
AUD_NB_MUTE#
2
1
LINE1-L(PORT-C-L)/RING2
LINE1-R(PORT-C-R)/SLEEVE
SPDIF-OUT/DMIC-DATA34/GPIO2
1 2
LA10 BLM15PX330SN1D_2PEMC@
1 2
LA2 BLM15BD601SN1D_2PEMC@
1 2
LA3 BLM15BD601SN1D_2PEMC@
1 2
LA11 BLM15PX330SN1D_2PEMC@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
AVDD1
AVDD2
CPVDD
PVDD1
PVDD2
HP/MIC1 JD(JD1)
I2S_IN/I2S_OUT JD(JD2)
TV Mode/LINE1-JD (JD3)
LINE1-VREFO
MIC-CAP
HPOUT-L(PORT-A-L)
HPOUT-R(PORT-A-R)
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R+
SPK-OUT-R-
PCBEEP
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA12
CPVEE
VREF
MIC1-VREFO
AVSS1
AVSS2
CA43
MIC1_L
CA44
MIC1_R
CBN
CBP
1 2
4.7U_0603_6.3V6K
1 2
4.7U_0603_6.3V6K
place close to pin27
+VDDA_AVDD1
0.1U_0201_10V6K
CA8
1
2
27
40
+VDDA_PVDD
38
41
+5V_RUN_PVDD
46
AUD_SENSE_A
13
AUD_SENSE_B
14
1 2
22
RA45 0_0402_5%@
28
RING2
29
SLEEVE
23
31
33
32
42
43
45
44
12
2
4
47
35
36
34
25
30
26
37
1 2
CA25 10U_0603_10V6M
AUD_OUT_L
AUD_OUT_R
RA7 24.9_0402_1%
RA8 24.9_0402_1%
INT_SPK_L+
INT_SPK_L-
INT_SPK_R+
INT_SPK_R-
AUD_PC_BEEP
Place CA29 close to Codec
12
CA29 1U_0603_10V6K
12
12
CA49 1U_0603_10V6K
CA35 2.2U_0402_6.3V6M
+MIC1_VREF_OUT
RING2_R
AUD_HP_OUT_L1
AUD_HP_OUT_R1
SLEEVE_R
EMC@
680P_0402_50V7K
1
CA1
2
10U_0603_10V6M
BLM15PX600SN1D_2P
12
CA9
place close to pin40
+3.3V_RUN_AUDIO
SLEEVE/RING2 please keep 40 mils trace width
1 2
1 2
12
CA27 0.1U_0402_25V6
12
CA28 0.1U_0402_25V6
1 2
RA14EMC@ 33_0402_5%
RB751S40T1G_SOD523-2
21
21
DA4
4.7K_0402_5%
4.7K_0402_5%
RA25
RA24
1 2
1 2
AUD_HP_OUT_L
AUD_HP_OUT_R
@EMC@
@EMC@
220P_0402_50V7K
220P_0402_50V7K
1
1
2
1
CA3
CA2
2
2
1 2
DMIC_CLK0DMIC_CLK_CODEC
RB751S40T1G_SOD523-2
DA5
EMC@
680P_0402_50V7K
CA4
+5V_RUN_AUDIO +1.5V_RUN
LA5
+1.5V_RUN_AUDIO
4.7U_0603_6.3V6K
place close to pin38
1
CA16
2
+VREFOUT
AUD_HP_OUT_L
AUD_HP_OUT_R
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
DMIC0 <26>
+3.3V_RUN_AUDIO+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
3
1
0.1U_0201_10V6K
1
2
1 2
RA12 1K_0402_5%
1 2
RA13 1K_0402_5%
DMIC_CLK0 <26>
12
RA1
10K_0402_5%
EMC@
2
EMC@
2
3
DA1
DA2
L03ESDL5V0CC3-2_SOT23-3
1
4.7U_0603_6.3V6K
CA17
1
2
@EMC@
680P_0402_50V7K
1
CA13
2
AUD_HP_NB_SENSE
3
L03ESDL5V0CC3-2_SOT23-3
CA18
1
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
2
SPKR <12>
BEEP <32>
HP-Out-Left
EMC@
DA3
AZ5123-02S.R7G_SOT23-3
12
+3.3V_RUN_AUDIO
1
2
DMIC_CLK0
12
0_0603_5%
RA4@
0.1U_0201_10V6K
CA45
0.1U_0201_10V6K
10U_0603_10V6M
CA47
1
1
CA46
2
2
1 2
RING2
1 2
SLEEVE
+VREFOUT
22P_0402_50V8J
12
@EMC@
CA54
0_0603_5%
RA3@
place close to pin41 place close to pin46
place close to UA1 pin2
HP-Out-Right Nokia-MIC
Global Headset
Universal Jack
JHP1
7
GND
4
#4 G/M
1
#1 L/R
5
#5
6
#6 AGND
2
#2 R/L
3
#3 M/G
SINGA_2SJ3095-022111F
RA2 100K_0402_5%
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
CONN@
@EMC@
680P_0402_50V7K
1
CA12
2
Codec ALC3235
Codec ALC3235
Codec ALC3235
LA-C621P
LA-C621P
LA-C621P
+5V_RUN_AUDIO
0_0805_5%
12
RA39@
10U_0603_10V6M
1
CA48
2
1U_0603_10V6K
12
iPhone-MIC
30 60Thursday, September 24, 2015
30 60Thursday, September 24, 2015
30 60Thursday, September 24, 2015
+VREFOUT
RA52.2K_0402_5%
RA62.2K_0402_5%
@
CA26
Normal
Open
1.0
1.0
1.0
Page 31
5
Vinafix.com
+3.3V_ALW
RPE9
USB_PWR_SHR_VBUS_EN
1
8
USB_PWR_EN1#
2
7
USB_PWR_EN2#
3
6
45
100K_0804_8P4R_5%
D D
+3.3V_RUN
C C
B B
RPE12
SLICE_BAT_PRES#
1
8
7
6
100K_0804_8P4R_5%
8
7
6
100K_0804_8P4R_5%
1 2
RE11 100K_0402_5%
1 2
RE12 100K_0402_5%
1 2
RE83 100K_0402_5%@
RE309 10K_0402_5%
RC281 10K_0402_5%
1 2
RE21 10K_0402_5%
1 2
RE20 100K_0402_5%
RPE11
1 2
1 2
VGA_ID
VGA_ID
@
WLAN_WIGIG60GHZ_DIS#
2
DOCK_SMB_ALERT#
3
WWAN_RADIO_DIS#
45
SLOT2_CONFIG_3
1
SLOT2_CONFIG_0
2
SLOT2_CONFIG_2
3
SLOT2_CONFIG_1
45
BT_RADIO_DIS#
HW_GPS_DISABLE#
AC_DIS
AR_SMBUS_ALERT#
USH_DET#
SYS_LED_MASK#
LCD_TST
1 2
1 2
Reserve
+3.3V_ALW
RE84100K_0402_5%
RE85100K_0402_5%
USB_PWR_SHR_EN# <31,36>
DOCK_SMB_ALERT#<38,43>
EN_I2S_NB_CODEC#<30>
USH_PWR_STATE#<33>
EN_DOCK_PWR_BAR<52>
HW_GPS_DISABLE#<29>
LCD_VCC_TEST_EN<26>
AUD_HP_NB_SENSE<30>
SLICE_BAT_PRES#<38,43,52>
Reserve
Reserve
WLAN_WIGIG60GHZ_DIS#<29>
Reserve
USB_PWR_SHR_VBUS_EN<36>
LAN_DISABLE#_R<27>
USB_PWR_EN2#<37>
PANEL_BKEN_EC<26>
PSID_DISABLE#<43>
AUD_NB_MUTE#<30>
3.3V_WWAN_EN<41>
WWAN_WAKE#<29>
USB_PWR_EN1#<37>
SLICE_BAT_ON<52>
T97@ PAD~D
T99@ PAD~D
T98@ PAD~D
BCM5882_ALERT#<33>
SYS_LED_MASK#<27,40>
AC_DIS<43,51,52>
LCD_TST<26>
DOCKED<23,25,27>
DOCK_DET#<38,52>
USH_DET#<33>
EC5048_TX<32>
VGA_ID0
Discrete
CPU_ID
CPU_ID
0
1UMA
1 2
1 2
+3.3V_ALW
RE298100K_0402_5%@
RE299100K_0402_5%
BT_RADIO_DIS#<29>
WWAN_RADIO_DIS#<29>
SIO_SLP_WLAN#<11,41>
CPU_ID0
U CPU
0
1H_CPU
4
LID_CL_SIO#
DOCK_SMB_ALERT#
USB_PWR_EN2#
HW_GPS_DISABLE#
LCD_TST
WWAN_WAKE#
USB_PWR_EN1#
SLICE_BAT_ON
SLICE_BAT_PRES#
GPIOD4
GPIOD5
WLAN_WIGIG60GHZ_DIS#
GPIOE2
AR_SMBUS_ALERT#
VGA_ID
SYS_LED_MASK#
USB_PWR_SHR_VBUS_EN
BT_RADIO_DIS#
WWAN_RADIO_DIS#
+3.3V_ALW +3.3V_ALW_UE1
12
B52
A49
B53
A50
B54
A51
B55
A52
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
B32
A31
B33
B15
A15
B16
A16
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
1 2
10U_0603_10V6M
PAD-OPEN1x1m
CE1
UE1
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
PJP14
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
ECE5048-LZY_DQFN132_11X11~D
3
0.1U_0201_10V6K
CE2
1
1
2
2
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
DB Version 0.4
2
PCIE_WAKE#_R
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CE3
CE4
1
2
A23
B63
PD_ACE_DET#
A60
PROCHOT_GATE
A61
B65
A62
B66
A63
B67
A64
A5
B6
A6
B7
A7
B8
A8
B9
PCIE_WAKE#_R
B10
A10
B11
A11
B12
A12
B60
A57
B64
B68
A9
B1
A18
A44
B34
B39
B51
A27
A26
B26
B25
A21
B22
CLK_PCI_5048
A28
B20
CLKRUN#
LPC_LDRQ1#
A22
B21
A32
B35
B29
B28
A25
A24
B23
D_CLKRUN#
A19
D_DLDRQ1#
B24
D_SERIRQ
A20
A29
B31
A30
A4
RUNPWROK
B56
B19
RE24 10K_0402_5%
+CAP_LDO
B46
B27
VSS
C1
EP
CE5
1
1
2
2
SLOT2_CONFIG_0
CPU_ID
SLOT2_CONFIG_1
SLOT2_CONFIG_2
SLOT2_CONFIG_3
1 2
4.7U_0603_6.3V6K
12
0.1U_0201_10V6K
CE6
USH_RST# <33>
DOCK_AC_OFF_EC <52>
AUX_EN_WOWL <41>
GPIO_PSID_SELECT <43>
DOCK_HP_DET <30>
DOCK_MIC_DET <30>
USB_PWR_SHR_EN# <31,36>
MASK_SATA_LED# <40>
LED_SATA_DIAG_OUT# <40>
SLOT2_CONFIG_0 <29>
WLAN_DISBL# <27>
SLOT2_CONFIG_1 <29>
SLOT2_CONFIG_2 <29>
SLOT2_CONFIG_3 <29>
DIS_BAT_PROCHOT# <52>
LPC_LAD0 <8,32>
LPC_LAD1 <8,32>
LPC_LAD2 <8,32>
LPC_LAD3 <8,32>
LPC_LFRAME# <8,32>
PLTRST_5048# <11>
CLK_PCI_5048 <8>
CLKRUN# <8,32>
IRQ_SERIRQ <8,32>
EC_32KHZ_ECE5048 <32>
D_LAD0 <38>
D_LAD1 <38>
D_LAD2 <38>
D_LAD3 <38>
D_LFRAME# <38>
D_CLKRUN# <38>
D_DLDRQ1# <38>
D_SERIRQ <38>
BC_INT#_ECE5048 <32>
BC_DAT_ECE5048 <32>
BC_CLK_ECE5048 <32>
RUNPWROK <14,32>
CE7
ME_FWP_EC <12>
+CAP_LDO trace width 20 mils
CLK_PCI_5048
33_0402_5%
12
RE27@EMC@
33P_0402_50V8J
12
PCIE_WAKE#_R
RE275 0_0402_5%@
Stuff RE275 and no stuff RE274 keep E5 design
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
LID_CL_SIO#
CE9@EMC@
WWAN_WAKE#
PD_ACE_DET#
PROCHOT_GATE
LPC_LDRQ1#
D_DLDRQ1#
D_SERIRQ
D_CLKRUN#
12
SLICE_BAT_ON
RE17 100K_0402_5%
+3.3V_ALW
100K_0402_5%
12
RE25
.047U_0402_16V7K
12
CE8
RPE8
1
2
3
4 5
100K_0804_8P4R_5%
1 2
12
RE26 10_0402_5%
1
+3.3V_ALW
12
RE3510K_0402_5%
12
RE3810K_0402_5%
12
RE310100K_0402_5%
12
@
RE311100K_0402_5%
+3.3V_RUN
8
7
6
PCIE_WAKE# <29,35>
PCH_PCIE_WAKE# <11,32>
RE2740_0402_5% @
12
LID_CL# <40>
A A
EMI depop location
EMI depop location
EMI depop locationEMI depop location
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ECE5048
ECE5048
ECE5048
LA-C621P
LA-C621P
LA-C621P
1
31 60Thursday, September 24, 2015
31 60Thursday, September 24, 2015
31 60Thursday, September 24, 2015
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 32
BC_DAT_ECE5048
Vinafix.com
PBAT_SMBCLK
8
PBAT_SMBDAT
7
GPU_SMBCLK
6
GPU_SMBDAT
EN_INVPWR
RESET_OUT#
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
MSDATA
DOCK_POR_RST#
CV2_ON
RUN_ON
A_ON
PCH_ALW_ON
1U_0402_6.3V6K
12
CE30
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
+3.3V_ALW
12
12
+3.3V_ALW
+3.3V_RUN
100K_0402_5%
RE63
JTAG_RST#
100_0402_1%
RE65@
49.9_0402_1%
12
RE71
MSCLK
MSDATA
HOST_DEBUG_TX
LPC_LFRAME#
PCH_PLTRST#_EC
5
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
Reserve
Reserve
123
10K_8P4R_5%
678
RPE7
4 5
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
CLK_PCI_LPDEBUG <8>
MEC_XTAL1
33P_0402_50V8J
12
+3.3V_ALW
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
RE73
RE72
Pin8 5085_TXD f or EC Debug
pin9 5048_TXD f or SBIOS
debug
MEC_XTAL2_R
32 KHz Clock
MEC_XTAL2
1 2
YE1
32.768KHZ_12 .5PF_Q13FC1 35000040
CE28
100K_0402_5%
12
RE74
RE75@
12
@
RE305 0_0402_5%
12
@
RE306 0_0402_5%
*
+3.3V_ALW +3.3V_ALW_UE2
1 2
10U_0603_10V6M
PAD-OPEN1x1m
12
CE21
12
@
RE290
0_0402_5%
8/28 schematic review
33P_0402_50V8J
12
CE29
RE79 CE40
240K 4700p
130K 4700p
4700p
33K
8.2K
4700p
4.3K 4700p X05
1K
4700p
+3.3V_ALW
1 2
RE36 100K_040 2_5%
+3.3V_RUN
D D
C C
B B
A A
RPE13
1
2
3
4 5
2.2K_0804_ 8P4R_5%
FAN1_PWM
1 2
RE48 10K_0402_ 5%
RE51 10K_0402_ 5%
+5V_RUN
FAN1_TACH
1 2
1 2
RE55 100K_0402_5 %
1 2
RE56 10K_0402_5%
RPE2
1
8
2
7
3
6
4 5
4.7K_8P4R_ 5%
1 2
RE86 10K _0402_5%
1 2
RE277 10 0K_0402_5 %
RPE10
1
8
2
7
3456
100K_0804 _8P4R_5%
1
JTAG1 CONN@
@SHORT PADS~D
1
2
2
JDEG1
11
G1
12
G2
HB_A531015-SCHR21
JLPDE1
11
G1
12
G2
HB_A531015-SCHR21
CONN@
CONN@
BOARD_ID rise time is measured from 5%~68%.
5
+RTC_CELL
+3.3V_ALW_UE2
+3.3V_ALW_UE2
PJP15
for no-dock : A43 use BC_CLK_ECE1099
for no-dock : B45 use BC_DAT_ECE1099
for no-dock : A42 use BC_INT#_ECE1099
EC5048_TX <31>
UART0_TXD <9>
REV
X00
X01
X02
X03/X04
A00
4
1 2
RE32@ 0_0402_ 5%
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@
CE17
CE16
CE22
1
1
1
2
2
2
for no-dock : A38 use LCD_TST
for no-dock : B41 use Free
for no-dock : A39 use SLP_ME_CSW_DEV#
for no-dock :B42 use Free
for no-dock : A21 use LID_CL_SIO#
trace width 20 mils
trace width 20 mils
CLK_PCI_MEC
@EMC@
10_0402_5%
12
RE66
@EMC@
4.7P_0402_50V8C
12
CE34
EMI depop locat ion
Place close pin A29
BOARD_ID
4
0.1U_0201_10V6K
1
2
+3.3V_ALW
3
+RTC_CELL_VBAT
0.1U_0201_10V6K
CE11
1
2
0.1U_0201_10V6K
1U_0402_6.3V6K
CE13
1
12
CE14
2
0.1U_0201_10V6K
1U_0402_6.3V6K
CE20
1
12
CE15
2
0.1U_0201_10V6K
0.1U_0201_10V6K
CE18
CE19
CE23
1
1
2
2
SML1_SMBDATA<8>
SML1_SMBCLK<8>
CLK_TP_SIO<39>
DAT_TP_SIO<39>
PBAT_SMBDAT<43>
PBAT_SMBCLK<43>
DOCK_POR_RST#<38>
BIA_PWM_EC<26>
BC_CLK_ECE5048<31>
BC_DAT_ECE5048<31>
BC_INT#_ECE5048<31>
ACAV_IN_NB<51,52>
SIO_SLP_S5#<11>
BC_CLK_ECE1117<39>
BC_DAT_ECE1117<39>
BC_INT#_ECE1117<39>
SIO_EXT_SMI#<12>
IRQ_SERIRQ<8,3 1>
PCH_PLTRST#_EC<11>
CLK_PCI_MEC<8>
LPC_LFRAME#<8,31>
SIO_EXT_SCI#<9>
CLK_KBD
CLK_KBD<38>
DAT_KBD
DAT_KBD<38>
CLK_MSE
CLK_MSE<38>
DAT_MSE
DAT_MSE<38>
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
FAN1_TACH
DOCK_POR_RST#
PS_ID<43>
FAN1_PWM
BEEP<30>
SIO_RCIN#<8>
CLK_PCI_MEC
LPC_LAD0<8,31>
LPC_LAD1<8,31>
LPC_LAD2<8,31>
LPC_LAD3<8,31>
CLKRUN#<8,31>
MEC_XTAL1
MEC_XTAL2_R
UE2
B64
VBAT
A22
H_VTR
A58
VTR_ADC
B3
VTR
A11
VTR
A26
VTR
B35
VTR
A41
VTR
A52
VTR
A5
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
B6
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
A37
GPIO110/PS2_CLK2/GPTP-IN6
B40
GPIO111/PS2_DAT2/GPTP-OUT6
A38
GPIO112/PS2_CLK1A
B41
GPIO113/PS2_DAT1A
A39
GPIO114/PS2_CLK0A
B42
GPIO115/PS2_DAT0A
B59
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
A56
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
A51
GPIO145/I2C1K_DATA/JTAG_TDI
B55
GPIO146/I2C1K_CLK/JTAG_TDO
B56
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
A53
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
B47
JTAG_RST#
B22
GPIO050/FAN_TACH1/GTACH0/GANG_START
A21
GPIO051/FAN_TACH2/GANG _MODE
B23
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
B24
GPIO053/PWM0
A23
GPIO054/PWM1/GPWM1
B25
GPIO055/PWM2
A24
GPIO056/PWM3/GPWM0
A43
GPIO123/BCM_A_CLK
B45
GPIO122/BCM_A_DAT
A42
GPIO121/BCM_A_INT#
B20
GPIO032/BCM_E_CLK
A18
GPIO031/GPTP-OUT2/BCM_E_DAT
B19
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
A20
GPIO047/LSBCM_D_CLK
B21
GPIO046/LSBCM_D_DAT/GANG_STROBE
A19
GPIO045/LSBCM_D_INT#
A6
GPIO011/nSMI
A27
GPIO061/LPCPD#
A28
SER_IRQ
B30
LRESET#
A29
PCI_CLK
B31
LFRAME#
A30
LAD0
B32
LAD1
A31
LAD2
B33
LAD3
A32
CLKRUN#
A33
GPIO100/NEC_SCI
A61
XTAL1
A62
XTAL2
POWER_SW_IN#
15mil
AGND
B66
+RTC_CELL
100K_0402_5%
12
RE31
RE33 10K_04 02_5%
1U_0402_6.3V6K
12
CE12
VSS
VSS_ADC
B11
B60
+VR_CAP
CE10@
1 2
1U_0402_6.3 V6K
1 2
GPIO120/UART_TX/V2P_COUT_HI1
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1
GPIO060/KBRST/BCM_B_INT#
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO117/MSCLK/V2P_COUT_HI
GPIO001/ECSPI_CS1/32KHZ_OUT
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY
GPIO151/GPTP-IN4/GANG_DATA2
GPIO005/I2C1B_DATA/BCM_B_DAT
GPIO006/I2C1B_CLK/BCM_B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
VSS_RO
H_VSS
B18
PROCHOT_IN#/PROCHOT_IO#
EP
MEC5085-LZY_DQFN132_11X11
C1
VR_CAP
B12
B54
4.7U_0603_6.3V6K
12
CE31
POWER_SW#_MB <11,40>
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
GPIO025/UART_CLK
VCC_PWRGD
GPIO101/ECGP_SCLK
GPIO103/ECGP_MISO
GPIO105/ECGP_MOSI
GPIO102/BCM_C_INT#
GPIO104/SLP_S0#
GPIO106
GPIO127/A20M
GPIO156/LED1/GANG_DATA1
GPIO157/LED0
GPIO153/LED2/GANG_DATA4
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO152/GPTP-OUT4
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
SYSPWR_PRES
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
VREF_PECI
PECI_DAT
DN1_DP1A/THERM
DP1_DN1A/VREF_T
DN2_DP2A
DP2_DN2A
DN3_DP3A
DP3_DN3A
DN4_DP4A
DP4_DN4A
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
V_ISYS0
V_ISYS1
nFWP
BGP0
VIN
VSET
VCP
A10
B10
B8
B27
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
B65
B57
B1
A55
A1
B28
B2
A8
B9
A9
B39
VCCST_PWRGD_EC
A44
A54
B58
A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50
A59
B62
A64
A60
B67
A63
B63
B68
B51
A48
REM_DIODE1_N
B13
REM_DIODE1_P
A13
REM_DIODE2_N
B14
REM_DIODE2_P
A14
A15
B16
REM_DIODE4_N
A16
REM_DIODE4_P
B17
B15
A17
A12
B34
A2
B29
H_PROCHOT#_R1
A46
B61
A57
RE64 4.7K_0402_ 5%
RE312 0_0402_5%
12
@
RE313
10K_0402_ 5%
ESR <2ohms
+3.3V_RUN
10K_0402_5%
12
RUNPWROK
PANEL SIZE
12"
14"
15"
17"
RE67
DMN65D8LDW-7_SOT363-6
34
QE2B
5
+3.3V_ALW
100K_0402_5%
12
RE68
RUN_ON#
DMN65D8LDW-7_SOT363-6
6
QE2A
RUN_ON<32,41,4 7>
+3.3V_ALW
1K_0402_5%
12
RE79
4700P_0402_25V7K
12
CE40
10K_0402_5%
12
RE81
FWP#
10K_0402_5%
RE82@
1 2
PANEL_ID
+3.3V_ALW
12
12
240K_0402_5%
RE300
4700P_0402_25V7K
CE47
2
1
RE300 CE47
4700p240K
*
4700p130K
4700p
33K
4700p4.3K
PANEL_ID rise time is measured from 5%~68%.
3
+RTC_CELL
12
DOCK_PWR_SW#
12
PANEL_ID
BOARD_ID
mCARD_PCIE#_SATA
HOST_DEBUG_TX
RUNPWROK
EN_INVPWR
PCH_ALW_ON
MSDATA
MSCLK
PCH_RSMRST#
FWP#
IMVP_VR_ON_EC
RUN_ON_EC
RESET_OUT#
SIO_PWRBTN#
DOCK_SMB_DAT CHARGER_SMBCLK
DOCK_SMB_CLK CHARGER_SMBDAT
A_ON
GPU_SMBDAT
GPU_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
SIO_SLP_SUS#_R
POWER_SW_IN#
DOCK_PWR_SW#
VCI_IN2#
POA_WAKE#
+PECI_VREF
PECI_EC_R
VSET_5085
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
1 2
1 2
12
@
RE3080_0402_ 5%
Reserve
Reserve
Reserve
1 2
RE60 4 3_0402_5 %
1 2
CE24 220 0P_0402_ 50V7K
1 2
CE26 220 0P_0402_ 50V7K
1 2
CE27 220 0P_0402_ 50V7K
CE24, CE26, CE27 Place near UE2
1 2
RE288 100_0402_ 5%
Setting for Thermal Design
Setting for Thermal Design
Setting for Thermal DesignSetting for Thermal Design
Thermal diode mapping
5085 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a
DP3/DN3
DP4/DN4
Place under CPU
Place CE35 close to the QE3 as possible
100P_0402_50V8J
CE35@
1 2
DN2/DP2 for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7
DN2/DP2 for Wigig on QE5, place QE5 close to Wigig and
CE37 close to QE5
100P_0402_50V8J
12
CE46@
DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
100P_0402_50V8J
@
CE39
1 2
2
100K_0402_5%
RE62
1 2
RE42 10K_04 02_5%
1U_0402_6.3V6K
CE45
LAN_WAKE# <11,27>
PCH_PCIE_WAKE# <11,31 >
RUNPWROK <14,31>
EN_INVPWR <26>
SIO_SLP_S4# <11,17,45,54>
SIO_SLP_LAN# <11,41>
PCH_ALW_ON <41>
SIO_SLP_S3# <11,17,48>
PCH_DPWROK <11>
PCH_RSMRST# <39>
BREATH_LED# <38,40>
BAT1_LED# <40>
BAT2_LED# <40>
SIO_SLP_A# <8,11>
EC_32KHZ_ECE5048 <31>
ME_SUS_PWR_ACK <11>
CV2_ON <33>
RESET_OUT# <11,14>
AC_PRESENT <11>
SIO_PWRBTN# <11,14>
DOCK_SMB_DAT <38>
DOCK_SMB_CLK <38>
A_ON <41>
SIO_EXT_WAKE# <9>
SUSACK# <11>
ENVDD_PCH <6,26>
CHARGER_SMBDAT <51>
CHARGER_SMBCLK <51>
PBAT_PRES# <43,51,52>
USH_SMBDAT <33>
USH_SMBCLK <33>
EC_FPM_EN <33>
ACAV_IN <51,52>
ALWON <44>
POA_WAKE# <33>
I_ADP <51>
I_BATT <51>
T131 @PAD~D
8/11
VCCST_PWRGD <11,14>
I_SYS <49,51>
CE44@
1 2
1U_0402_6.3 V6K
for no-dock : B2 use Free
Reserve
1 2
RC76 43K_0402_1 %
1 2
RE57 1K_040 2_5%
100K_0402_5%
12
RE58
PECI_EC <12>
H_PROCHOT# <12,49,51>
DOCK_PWR_BTN# <38>
IMVP_VR_ON_EC
SIO_SLP_S3#
8/21 CRB1.0 change to 0603 1/10W
10/30 move to EC side
RE59 close to UE2 at least 250mils
RE59 0_04 02_5%@
0.1U_0201_10V6K
CE25
12
+3.3V_ALW
1
2
UE3
TC7SH08FU_SSOP5~D
SIO_SLP_S3#
RUN_ON_EC
UE5
TC7SH08FU_SSOP5~D
SIO_SLP_SUS# <8,11,17,18,41,46,47,4 8>
+3.3V_ALW2
1 2
+1.0VS_VCCIO
B
A
Location
CPU
WiGig
DDR
NA
V.R
2
B
QE3
METR3904W-G NPN SOT323-3
100P_0402_50V8J
B
2
2
B
QE6
METR3904W-G NPN SOT323-3
2
REM_DIODE1_P
REM_DIODE1_N
12
CE37@
REM_DIODE4_P
REM_DIODE4_N
C
2
B
E
QE5
3 1
METR3904W-G NPN SOT323-3
C
E
3 1
METR3904W-G NPN SOT323-3
E
31
C
QE7
C
E
3 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.0VS_VCCIO
REM_DIODE2_P
REM_DIODE2_N
SIO_SLP_S3#
2
G
1 3
D
QE11
L2N7002WT1G_SC-70-3
1 2
RE90 0_0402_5%@
Rest=1.58K , Tp=96 degree
S
0.1U_0402_25V6
12
CE38
12
@
RE3040_0402_ 5%
@
CE53
1 2
5
0.1U_0402_2 5V6
P
4
O
G
3
1 2
@
RE2800_0402_5%
12
@
RE2920_0402_ 5%
+3.3V_ALW
@
CE52
1 2
0.1U_0402_2 5V6
5
1
P
B
4
O
2
A
G
3
DOCK_SMB_DAT
DOCK_SMB_CLK
THERMATRIP3#
BC_DAT_ECE1117
POA_WAKE#
VCI_IN2#
Reserve
PCH_RSMRST#
Link 50271-0040N-001 DONE
JFAN1
1
2
3
4
GND1
GND2
ACES_50271-00 40N-001
CONN@
1 2
RE70 2.2 K_0402_5%
H_THERMTRIP#<12,20,21>
VSET_5085
1.58K_0402_1%
12
RE77
1
+3.3V_ALW
UE4
1
5
NC
IMVP_VR_ON
IMVP_VR_ON <49>
RUN_ON <32,41,47>
1
2
3
4 5
2.2K_0804_ 8P4R_5%
RE301 1 0K_0402_5 %
1
2
3
4 5
100K_0804 _8P4R_5%
1 2
RE88 10K_ 0402_5%
1
FAN1_PWM
2
FAN1_TACH
3
4
10U_0603_10V6M
5
6
12
CE32
reserve for DC fan
+3.3V_ALW
12
C
2
B
E
3 1
THSEL_STRAP
1 2
RE78 1 K_0402_5%
Channel 1
Thermal Monitoring Interface Strap Option
Thermistor Readings
HIGH
Diode Readings
LOW
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
VCC
2
A
Y
3
GND
SN74AUP1G07DCKR SC70 5P
+3.3V_ALW
RPE3
8
7
6
1 2
+3.3V_ALW
RPE5
8
7
6
+5V_RUN
RB751S40T1G_SOD523-2
@
DE1
2 1
8.2K_0402_5%
RE69
THERMATRIP2#
METR3904W-G NPN SOT323-3
0.1U_0402_25V6
QE4
CE36
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
MEC5085
MEC5085
MEC5085
LA-C621P
LA-C621P
LA-C621P
1
4
+RTC_CELL
VCCST_PWRGD
32 60Thursday, September 24, 2015
32 60Thursday, September 24, 2015
32 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 33
5
Vinafix.com
4
3
2
1
power rail option: TPM power rail must same as +3.3V_SPI (SPI ROM)
D D
RZ72 0_0603_5%@
1 2
+3.3V_M_TPM+3.3V_M
1 2
1 2
+5V_ALW2
USH_DET#<31>
+3.3V_ALW
1 2
RZ8 2.2K_0402_5%
@
1 2
RZ9 2.2K_0402_5%
@
1 2
RZ10 1M_0402_5%
CV2_ON<32>
POA_WAKE#<32>
EC_FPM_EN<32>
USB20_N7<10>
USB20_P7<10>
USH_SMBCLK<32>
USH_SMBDAT<32>
BCM5882_ALERT#<31>
+3.3V_ALW
@
1 2
RZ86 0_0402_5%
+5V_ALW
+3.3V_RUN
+5V_RUN
USH_PWR_STATE#<31>
CONTACTLESS_DET#<12>
1 2
RZ87 0_0402_5%@
DZ7
RB751S40T1G_SOD523-2
+5V_ALW2
0.1U_0201_10V6K
1
@
CZ94
2
USH_SMBCLK
USH_SMBDAT
USH_PWR_STATE#
+PWR_SRC_R
+3.3V_ALW2_R
+5V_ALW2_R
PCH_PLTRST#_AND_R
12
+3.3V_ALW2
0.1U_0201_10V6K
1
@
CZ24
2
USH CONN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
USH_DET#_R
1
E-T_6705K-Y26N-00L
0.1U_0201_10V6K
1
@
CZ10
2
Close to JUSH1
JUSH1
GND
GND
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
2
CONN@
+3.3V_ALW+3.3V_RUN+5V_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
@
@
CZ11
CZ12
2
PJP11
1 2
PAD-OPEN1x1m
+3.3V_M_TPM
1 2
RZ69 10K_0402_5%
C C
PCH_SPI_D1_R1<8>
PCH_SPI_D0_R1<8>
PCH_SPI_CLK_R1<8>
PCH_SPI_CS#2<8>
PCH_SPI_CLK_2_R
33_0402_5%
B B
@EMC@
RZ63
0.1U_0402_25V6
1 2
@EMC@
12
CZ77
+3.3V_RUN
SIO_SLP_S0#<11,17,47>
RZ58
RZ59
RZ60
RZ61 0_0402_5%@
@
+3.3V_M_TPM+3.3V_ALW_PCH
TPM_PIRQ#
1 2
@
RZ90 10K_0402_5%
1 2
RZ112 0_0402_5%
1 2
1 2
1 2
1 2
10K_0402_5%
12
RZ62
7/18 vender suggest.
33_0402_5%
33_0402_5%
TPM_PIRQ#<8>
33_0402_5%
1 2
RZ110 0_0402_5%
@
TPM_LPM#
PCH_SPI_D1_2_R
PCH_SPI_D0_2_R
PCH_SPI_CLK_2_R
PCH_SPI_CS#2_R
PLTRST_TPM#<11>
PCH_SPI_CS#2_R
29
30
24
21
18
15
19
20
17
27
TPM_GPIO4
13
28
RZ113 100_0402_5%
RZ113 RZ111
1K
1
UZ12
GPIO0/SDA/XOR_OUT
GPIO1/SCL
3
GPIO2/GPX
6
GPIO3/BADD
LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
LCKL/SCLK
LFRAME#/SCS#
LRESET#/SPI_RST#/SRESET#
SERIRQ
CLKRUN#/GPIO4/SINT#
LPCPD#
4
PP
5
TEST
NPCT650JAAYX_QFN32_5X5
1 2
1K MMBT3906
00
10K
+3.3V_M_TPM
+3.3V_RUN
+3.3V_M_TPM
3
G
2
1
POP
LP2301A
@
RZ88 0_0402_5%
@
RZ89 0_0402_5%
1
VSB
8
VDD
14
VDD
22
VDD
2
NC
7
NC
10
NC
11
NC
25
NC
26
NC
31
NC
9
GND
16
GND
23
GND
32
GND
33
PGND
12
Reserved
S
LP2301ALT1G_SOT23-3
QZ9
D
TPM_LPM#
1 2
1 2
+UZ12_TPM
12
RZ111
10K_0402_5%
+UZ12_TPM
+3.3V_M_TPM +3.3V_ALW
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
1
1
CZ75
CZ74
2
2
place CZ73 as close as UZ12.8
CZ74,CZ76 as close as UZ12.14
CZ75 as close as UZ12.22
0.1U_0201_10V6K
1
1
CZ76
2
2
place CZ71,CZ72 as close as UZ12.1
@
+PWR_SRC
+3.3V_ALW2
0.1U_0201_10V6K
10U_0603_10V6M
1
1
CZ71
CZ73
CZ72
2
2
PCH_PLTRST#_AND<11,28,29,35>
USH_RST#<31>
PCH_PLTRST#_AND
.047U_0402_16V7K
12
CZ68
EMC@
For ESD solution
RZ85 0_0402_5%
RZ84 0_0402_5%@
1 2
RZ114 0_0402_5%@
1 2
RZ115 0_0402_5%@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-C621P
LA-C621P
LA-C621P
33 60Thursday, September 24, 2015
33 60Thursday, September 24, 2015
33 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 34
5
Vinafix.com
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2
4
3
2
1
10K_0402_5%
@
12
RN25
D D
10K_0402_5%
12
RN38
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
@
12
12
12
RN28
RN26
RN27
RD1_A_DE0
RD1_A_DE1
RD1_B_DE0
RD1_B_DE1 RD 1_A_EQ2
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
12
12
12
RN40
RN39
RN41
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
@
12
12
12
RN42
RN44
RN43
RD1_A_EQ0
RD1_A_EQ1
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
@
@
@
12
12
RN47
RN46
RN45
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
12
10K_0402_5%
12
@
12
12
RN49
RN51
RN50
RD1_B_EQ0
RD1_B_EQ1
RD1_B_EQ2
10K_0402_5%
10K_0402_5%
@
@
@
12
12
RN54
RN52
RN53
+3.3V_HDD_M2
0.1U_0201_10V6K
1
2
I
FDET_SATA#_PCIE
(SATAXPCIE0)
0.01UF_0402_25V7K
CN19
1
CN20
2
0
1
FLEX IO 11
PCIE
SATA
PCIE/SATA Repeater
UN4
12
VDD_3.3
24
VDD_3.3
1
A_INP
A_OUTP
2
A_INN
A_OUTN
5
B_OUTP
B_INP
4
B_OUTN
23
22
19
11
21
16
25
B_INN
A_DE0
A_EQ0
A_DE1
A_EQ1
A_EQ2
B_EQ0
B_DE0
B_DE1
B_EQ1
B_EQ2
PWD
7
GND
REXT
EPAD
MODE
PS8558BTQFN24GTR2-A_TQFN24_4X4
PCIE/SATA Repeater
UN5
12
VDD_3.3
24
VDD_3.3
1
A_INP
A_OUTP
2
A_INN
A_OUTN
5
B_OUTP
4
B_OUTN
23
A_EQ0
22
A_EQ1
19
A_EQ2
11
B_EQ0
21
B_EQ1
16
B_EQ2
7
GND
25
EPAD
PS8558BTQFN24GTR2-A_TQFN24_4X4
1 2
1 2
1 2
1 2
CN210.22U_0402_10V6K
CN220.22U_0402_10V6K
CN230.22U_0402_10V6K
CN240.22U_0402_10V6K
PCIE_PTX_C_RD_DRX_P12
PCIE_PTX_C_RD_DRX_N12
PCIE_PRX_C_RD_DTX_P12
PCIE_PRX_C_RD_DTX_N12
+3.3V_HDD_M2
0.1U_0201_10V6K
CN29
1
1
2
2
PCIE_PTX_C_RD_DRX_P11
CN320.22U_0402_10V6K
PCIE_PTX_C_RD_DRX_N11
CN310.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_P11
CN330.22U_0402_10V6K
PCIE_PRX_C_RD_DTX_N11
CN340.22U_0402_10V6K
0.01UF_0402_25V7K
CN30
RD1_A_EQ0
RD1_A_EQ1
RD1_A_EQ2
RD1_B_EQ0
RD1_B_EQ1
RD1_B_EQ2
RD2_A_EQ0
RD2_A_EQ1
RD2_A_EQ2
RD2_B_EQ0
RD2_B_EQ1
RD2_B_EQ2
Programmable output de-emphasis level
setting for channel A .
A_DE0: internally pulled up at ~150K;
A_DE1 internally pulled down at ~150K
[A_DE1,A_DE0] ==
C C
LL: -7.5dB
HL: -2dB
LH: -3.5dB (default)
HH: -6dB
Programmable output de-emphasis level
setting for channel B.
B_DE0: internally pulled up at ~150K;
B_DE1 internally pulled down at ~150K
[B_DE1,B_DE0] ==
LL: -7.5dB
HL: -2dB
LH: -3.5dB (default)
HH: -6dB
+3.3V_HDD_M2 +3.3V_HDD_M2 +3.3V_HDD_M2
B B
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
12
RN55
10K_0402_5%
@
12
RN59
10K_0402_5%
@
@
12
10K_0402_5%
12
@
12
12
RN56
RN57
RN58
RD2_A_DE0
RD2_A_DE1
RD2_B_DE0
RD2_B_DE1 RD 2_A_EQ2
10K_0402_5%
10K_0402_5%
@
@
@
12
12
RN60
RN61
RN62
Equalizer control and program for channel A.
A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K
[A_EQ2,A_EQ1,A_EQ0] ==
LLL: EQ Level1(default)
LHL: EQ Level2
HLL: EQ Level3
HHL: EQ Level4
LLH: EQ Level5
LHH: EQ Level6
HLH: EQ Level7
HHH: EQ Level8
Equalizer control and program for channel B.
B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K
[B_EQ2,B_EQ1,B_EQ0] ==
LLL: EQ Level1(default)
LHL: EQ Level2
HLL: EQ Level3
HHL: EQ Level4
LLH: EQ Level5
LHH: EQ Level6
HLH: EQ Level7
HHH: EQ Level8
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
@
12
12
12
RN63
RN65
RN64
RD2_A_EQ0
RD2_A_EQ1
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
@
12
12
12
RN68
RN66
RN67
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
12
12
12
RN70
RN69
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
@
12
12
12
RN72
RN73
@
RN71
@
RN74
RD2_B_EQ0
RD2_B_EQ1
RD2_B_EQ2
PCIE_PTX_DRX_P12<10>
PCIE_PTX_DRX_N12<10>
PCIE_PRX_DTX_P12<10>
PCIE_PRX_DTX_N12<10>
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
PCIE_PTX_DRX_P11<10>
PCIE_PTX_DRX_N11<10>
PCIE_PRX_DTX_P11<10>
PCIE_PRX_DTX_N11<10>
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
1 2
1 2
1 2
1 2
B_INP
B_INN
A_DE0
A_DE1
B_DE0
B_DE1
PWD
REXT
MODE
18
17
14
15
6
8
13
9
3
10
20
8/25
PCIE_PTX_RD_DRX_P12
PCIE_PTX_RD_DRX_N12
PCIE_PRX_RD_DTX_P12
PCIE_PRX_RD_DTX_N12
RD1_A_DE0
RD1_A_DE1
RD1_B_DE0
RD1_B_DE1
RD1_REXT
PCIE_PTX_RD_DRX_P11
18
PCIE_PTX_RD_DRX_N11
17
PCIE_PRX_RD_DTX_P11
14
PCIE_PRX_RD_DTX_N11
15
RD2_A_DE0
6
RD2_A_DE1
8
RD2_B_DE0
13
RD2_B_DE1
9
3
RD2_REXT
10
IFDET_SATA#_PCIE
20
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
12
CN25 0.22U_0402_10V6K
12
CN26 0.22U_0402_10V6K
RN77 0_0402_5%
RN78 0_0402_5%
12
12
PCIE_PTX_C_DRX_P12 <35>
PCIE_PTX_C_DRX_N12 <35>
PCIE_PRX_C_DTX_P12 <35>
PCIE_PRX_C_DTX_N12 <35>
PWD Funtion
1 2
RN30 4.99K_0402_1%
IFDET_SATA#_PCIE <10,35>
12
CN35 0.22U_0402_10V6K
12
CN36 0.22U_0402_10V6K
RN81 0_0402_5%
RN82 0_0402_5%
1 2
RN31 4.99K_0402_1%
12
12
Normal mode(default)
0
1
PCIE_PTX_C_DRX_P11 <35>
PCIE_PTX_C_DRX_N11 <35>
PCIE_PRX_C_DTX_P11 <35>
PCIE_PRX_C_DTX_N11 <35>
power down mode
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Mini Card-2/2
Mini Card-2/2
Mini Card-2/2
LA-C621P
LA-C621P
LA-C621P
34 60Thursday, September 24, 2015
34 60Thursday, September 24, 2015
34 60Thursday, September 24, 2015
1
1.0
1.0
1.0
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 35
5
Vinafix.com
4
3
2
1
D D
+3.3V_HDD_M2
0.1U_0201_10V6K
@
CN41
1
2
0.1U_0201_10V6K
22U_0603_6.3V6M
CN42
1
2
22U_0603_6.3V6M
12
12
CZ60
CZ61
2280 SSD
Place near HDD CONN
+3.3V_HDD_M2
C C
B B
1 2
RN37@ 10K_0402_5%
8/5 CKLT0.9
M2_DEVSLP
Double check P/N
PCIE_PRX_C_DTX_N11<34>
PCIE_PRX_C_DTX_P11<34>
PCIE_PTX_C_DRX_N11<34>
PCIE_PTX_C_DRX_P11<34>
PCIE_PRX_C_DTX_P12<34>
PCIE_PRX_C_DTX_N12<34>
PCIE_PTX_C_DRX_N12<34>
PCIE_PTX_C_DRX_P12<34>
CLK_PCIE_N3<11>
CLK_PCIE_P3<11>
IFDET_SATA#_PCIE<10,34>
NGFF slot C Key M
JNGFF3
1
GND
3
GND
5
PERn3
7
PERp3
9
GND
11
PETn3
13
PETp3
15
GND
17
PERn2
19
PERp2
21
GND
23
PETn2
25
PETp2
27
GND
29
PERn1
31
PERp1
33
GND
35
PETn1
37
PETp1
39
GND
41
PERn0/SATA-B+
43
PERp0/SATA-B-
45
GND
47
PETn0/SATA-A-
49
PETp0/SATA-A+
51
GND
53
REFCLKN
55
REFCLKP
57
GND
59
NC
61
PEDET(NC-PCIE/GND-SATA)
63
GND
65
GND
67
GND
BELLW_SD-80159-4221
CONN@
3P3VAUX
3P3VAUX
DAS/DSS#
3P3VAUX
3P3VAUX
3P3VAUX
3P3VAUX
DEVSLP
PERST#
CLKREQ#
PEWake#
SUSCLK(32kHz)
3P3VAUX
3P3VAUX
3P3VAUX
GND1
GND2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
+3.3V_HDD_M2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
69
NVME_LED#
@
RZ118 0_0402_5%
PCIE_WAKE#
SUSCLK_R
PCH_PLTRST#_AND <11,28,29,33>
CLKREQ_PCIE#3 <11>
PCIE_WAKE# <29,31>
1 2
@
RN99 0_0402_5%
2A
PJP34
1 2
PAD-OPEN1x2m
12
M2_DEVSLP <10>
+3.3V_RUN
PCH_SATA_LED# <10,40>
SUSCLK <11,29>
Link BELLW_80159-4221 DONE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HDD CONN
HDD CONN
HDD CONN
LA-C621P
LA-C621P
LA-C621P
35 60Thursday, September 24, 2015
35 60Thursday, September 24, 2015
35 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 36
5
Vinafix.com
4
3
2
1
LI7
+5V_USB_CHG_PWR
150U_B2_6.3VM_R35M
@
1
CI32
+
2
2
2
3
3
JUSB3
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
GND
7
GND
GND
8
SSTX-
GND
9
SSTX+
GND
SINGA_2UB4008-900101F
CONN@
10
11
12
13
PESD5V0U2BT_SOT23-3
EMC@
223
DI5
USB20_N1_R
USB20_P1_R
USB3_PRX_L_DTX_N1
USB3_PRX_L_DTX_P1
USB3_PTX_L_DRX_N1
USB3_PTX_L_DRX_P1
0.1U_0201_10V6K
100U_1206_6.3V6M
1
1
CI14
CI17
2
2
3
1
1
LINK SUB4008-90010F DONE
USB20_N1_R
USB20_P1_R
USB3_PRX_DTX_P1<10>
USB3_PTX_DRX_P1<10 >
USB3_PTX_DRX_N1<10>
USB3_PRX_DTX_N1<10>
ILIM_SEL
12
10K_0402_5%
CI16 0.1U_0402_ 25V6
CI13 0.1U_0402_ 25V6
USB3_PTX_C_DRX_N1
12
USB_OC0#<10>
USB_PWR_SHR_VB US_EN<31>
USB_PWR_SHR_EN #<31>
USB20_N1<10>
USB20_P1<10>
USB3_PTX_C_DRX_P1
12
D D
C C
+5V_ALW
RI13
1 2
@
RI15 0_0402_5%
1 2
@
RI16 0_0402_5%
1 2
@
RI17 0_0402_ 5%
1 2
@
RI18 0_0402_ 5%
+5V_ALW
ILIM_SEL
0.1U_0402_25V6
CI33
@EMC@
1
2
USB3_PRX_L_DTX_P1
USB3_PRX_L_DTX_N1
USB3_PTX_L_DRX_P1
USB3_PTX_L_DRX_N1
UI3
1
IN
2
DM_OUT
3
DP_OUT
13
FAULT#
4
ILIM_SEL
5
EN
6
CTL1
7
CTL2
8
CTL3
PI5USB2544ZHEX_TQFN16_3X3
OUT
DP_IN
DM_IN
ILIM_LO
ILIM_HI
GND
GNDP
12
10
11
15
16
9
NC
14
17
+5V_USB_CHG_PWR
SW_USB20_P1
SW_USB20_N1
RI14
DI4
USB3_PRX_L_DTX_N1 USB3_PRX_L_DTX_N1
USB3_PRX_L_DTX_P1
USB3_PTX_L_DRX_N1
USB3_PTX_L_DRX_P1
12
22.1K_0402_1%
EMC@
1
1
2
2
4
4
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
9
10
8
9
7
7
6
65
SW_USB20_N1
SW_USB20_P1
USB3_PRX_L_DTX_P1
USB3_PTX_L_DRX_N1
USB3_PTX_L_DRX_P1
MCM1012B900F06BP_4P
1
4
1
4
EMC@
Link Pericom PI5USB2544 Done
+5V_ALW
10U_0402_6.3V6M
0.1U_0201_10V6K
@
1
2
CI19
1
CI31
2
Place near UI3.1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
USB SW
USB SW
USB SW
LA-C621P
LA-C621P
LA-C621P
36 60Thursday, September 24, 2015
36 60Thursday, September 24, 2015
36 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 37
5
Vinafix.com
USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
USB3_PTX_C_DRX_P3
12
CI4 0.1U_0402_25V6
USB3_PTX_C_DRX_N3
12
CI5 0.1U_0402_25V6
USB3_PRX_DTX_P3<10>
USB3_PRX_DTX_N3<10>
D D
USB3_PTX_DRX_P3<10>
USB3_PTX_DRX_N3<10>
C C
1 2
@
RI19 0_0402_5%
1 2
@
RI20 0_0402_5%
1 2
@
RI21 0_0402_5%
1 2
@
RI22 0_0402_5%
4
USB3_PRX_L_DTX_P3
USB3_PRX_L_DTX_N3
USB3_PTX_L_DRX_P3
USB3_PTX_L_DRX_N3
3
DI1
USB3_PRX_L_DTX_N3 USB3_PRX_L_DTX_N3
USB3_PRX_L_DTX_P3 USB3_PRX_L_DTX_P3
USB3_PTX_L_DRX_N3 USB3_PTX_L_DRX_N3
USB3_PTX_L_DRX_P3 USB3_PTX_L_DRX_P3
USB20_P3<10>
USB20_N3<10>
USB20_P3
USB20_N3
EMC@
1
1
2
2
4
4
5
3
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
4
4
1
1
MCM1012B900F06BP_4P
8/19 for layout routing change
EMC@
9
10
8
9
7
7
6
65
LI3
3
3
2
2
USB20_P3_R
USB20_N3_R
+USB_LEFT_PWR
100U_1206_6.3V6M
12
CI1
1
2
+5V_ALW
12
2
JUSB1
USB3_PTX_L_DRX_P3
3
1
PESD5V0U2BT_SOT23-3
223
1
USB3_PTX_L_DRX_N3
USB20_P3_R
USB20_N3_R
USB3_PRX_L_DTX_P3
EMC@
USB3_PRX_L_DTX_N3
DI2
0.1U_0201_10V6K
CI3
CONN@
9
SSTX+
1
VBUS
8
SSTX-
3
D+
7
GND
2
D-
6
SSRX+
4
GND
5
SSRX-
LOTES_AUSB0014-P003A
GND
GND
GND
GND
1
10
11
12
13
Link LOTES_AUSB0014-P003A DONE
+USB_LEFT_PWR
UI1
1
OUT
5
IN
10U_0603_10V6M
0.1U_0201_10V6K
@
1
CI6
2
USB_PWR_EN1#<31>
CI7
4
9/3 change to SOT23 package
2
GND
EN
3
OCB
SY6288D20AAC_SOT23-5
0.1U_0402_25V6
CI34
@EMC@
1
2
USB_OC1# <10>
+USB_REAR_PWR
B B
A A
USB3_PRX_DTX_P4<10>
USB3_PRX_DTX_N4<10>
USB3_PTX_C_DRX_P4
USB3_PTX_DRX_P4<10>
USB3_PTX_DRX_N4<10>
12
CI28 0.1U_0402_25V6
CI27 0.1U_0402_25V6
USB3_PTX_C_DRX_N4
12
1 2
@
RI23 0_0402_5%
1 2
@
RI24 0_0402_5%
1 2
@
RI25 0_0402_5%
1 2
@
RI26 0_0402_5%
USB3_PRX_L_DTX_P4
USB3_PRX_L_DTX_N4
USB3_PTX_L_DRX_P4
USB3_PTX_L_DRX_N4
DI6
USB3_PRX_L_DTX_N4 USB3_PRX_L_DTX_N4
USB3_PRX_L_DTX_P4 USB3_PRX_L_DTX_P4
USB3_PTX_L_DRX_N4 USB3_PTX_L_DRX_N4
USB3_PTX_L_DRX_P4 USB3_PTX_L_DRX_P4
USB20_P4<10>
USB20_N4<10>
USB20_P4
USB20_N4
EMC@
1
1
2
4
5
3
8/19 for layout routing change
10
2
9
7
4
65
3
8
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
LI4
4
4
1
1
MCM1012B900F06BP_4P
100U_1206_6.3V6M
9
8
7
6
+5V_ALW
USB20_P4_R
3
3
USB20_N4_R
2
2
12
0.1U_0201_10V6K
CI10
1
12
CI8
2
0.1U_0201_10V6K
10U_0603_10V6M
@
CI12
CI11
1
2
223
1
3
1
USB_PWR_EN2#<31>
USB20_N4_R
USB20_P4_R
USB3_PRX_L_DTX_N4
USB3_PRX_L_DTX_P4
PESD5V0U2BT_SOT23-3
USB3_PTX_L_DRX_N4
USB3_PTX_L_DRX_P4
EMC@
DI3
JUSB2
CONN@
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
GND
7
GND
GND
8
SSTX-
GND
9
SSTX+
GND
ACON_TARAV-9R1U91
Link TARAV-9R1U91 DONE
+USB_REAR_PWR
UI2
1
OUT
5
IN
2
GND
4
EN
3
OCB
SY6288D20AAC_SOT23-5
9/3 change to SOT23 package
10
11
12
13
1
2
0.1U_0402_25V6
CI35
@EMC@
USB_OC2# <10>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB3.0
USB3.0
USB3.0
LA-C621P
LA-C621P
LA-C621P
1
37 60Thursday, September 24, 2015
37 60Thursday, September 24, 2015
37 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 38
5
Vinafix.com
12
HUB_DP0_P0<24>
HUB_DP0_N0<24>
D D
C C
B B
HUB_DP0_P1<24>
HUB_DP0_N1<24>
HUB_DP0_P2<24>
HUB_DP0_N2<24>
HUB_DP0_P3<24>
HUB_DP0_N3<24>
HUB_DP0_HPD
C302 0.1U_0402_25V 6
12
C295 0.1U_0402_25V 6
12
C297 0.1U_0402_25V 6
12
C299 0.1U_0402_25V 6
12
C304 0.1U_0402_25V 6
12
C306 0.1U_0402_25V 6
12
C300 0.1U_0402_25V 6
12
C301 0.1U_0402_25V 6
HUB_DP0_HPD<24> HUB_DP1_HPD <24>
Close to DOCK
I
ts for Enhance ESD on
dock issue.
100K_0402_5%
12
R268
HUB_DP0_P0_C
HUB_DP0_N0_C
HUB_DP0_P1_C
HUB_DP0_N1_C
HUB_DP0_P2_C
HUB_DP0_N2_C
HUB_DP0_P3_C
HUB_DP0_N3_C
0.033U_0402_16V7K
12
C310
+DOCK_PWR_BAR +DOCK_PWR_BAR
4
JDOCK1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
148
PWR1
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
Shield_G
JAE_WD2F144WB 5R400
SLICE_BAT_PRES#
4.7U_0805_25V6-K
0.1U_0603_50V7K
@
12
C33
DOCK_DET_1
HUB_DP0_P0_R
HUB_DP0_N0_R
HUB_DP0_P1_R
HUB_DP0_N1_R
HUB_DP0_P2_R
HUB_DP0_N2_R
HUB_DP0_P3_R
HUB_DP0_N3_R
2
3
C317
1
L30ESD24VC3-2_SOT23-3
D20 @EMC@
SW_LAN1_10_GRN#<27>
1 2
R259 33_0402_5%EMC@
1 2
R252 33_0402_5%EMC@
1 2
R253 33_0402_5%EMC@
1 2
R255 33_0402_5%EMC@
1 2
R257 33_0402_5%EMC@
1 2
R263 33_0402_5%EMC@
1 2
R265 33_0402_5%EMC@
1 2
R266 33_0402_5%EMC@
HUB_SW1_AUXP<25>
HUB_SW1_AUXN<25>
HUB_DP0_HPD
+NBDOCK_DC_IN_SS
@EMC@
SW2_VGA2_BLUE<25>
SW2_VGA2_RED<25>
SW2_VGA2_GREEN<25>
SW2_VGA2_HSYNC<25>
SW2_VGA2_VSYNC<25>
CLK_MSE<32>
DAT_MSE<32>
DAI_BCLK#<30>
DAI_LRCK#<30>
DAI_DI<30>
DAI_DO#<30>
DAI_12MHZ#< 30>
D_LAD0<31>
D_LAD1<31>
D_LAD2<31>
D_LAD3<31>
D_LFRAME#<31>
D_CLKRUN#<31>
D_SERIRQ<31>
D_DLDRQ1#<31>
CLK_PCI_DOCK<8>
DOCK_SMB_CLK<32>
DOCK_SMB_DAT<32>
DOCK_SMB_ALERT#<31,43>
DOCK_PSID<43>
DOCK_PWR_BTN#<32>
SLICE_BAT_PRES#<31,43,52> DOCK_DET# <31,52>
12
CONN@
3
PWR2
PWR2
PWR2
GND2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
2
DOCK_AC_OFF
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
149
150
151
152
159
160
161
162
163
164
HUB_DP1_P0_R
HUB_DP1_N0_R
HUB_DP1_P1_R
HUB_DP1_N1_R
HUB_DP1_P2_R
HUB_DP1_N2_R
HUB_DP1_P3_R
HUB_DP1_N3_R
HUB_DP1_HPD
SATA_PRX_C_DTX_P1
SATA_PRX_C_DTX_N1
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
DOCK_DET_R#
0.1U_0603_50V7K
C318
12
DOCK_AC_OFF <52>
SW_LAN1_100_ORG# <27>
HUB_DP1_CADET <24,25>HUB_DP0_CADET<24,25>
1 2
R260 33_0402_5%EMC@
1 2
R261 33_0402_5%EMC@
1 2
R254 33_0402_5%EMC@
1 2
R256 33_0402_5%EMC@
1 2
R262 33_0402_5%EMC@
1 2
R264 33_0402_5%EMC@
1 2
R258 33_0402_5%EMC@
1 2
R267 33_0402_5%EMC@
HUB_SW2_AUXP <25>
HUB_SW2_AUXN <25>
ACAV_DOCK_SRC# <52>
SW2_VGA2_SDA <25>
SW2_VGA2_SCL <25>
12
12
C312 0.01UF_0402_25V7K
C313 0.01UF_0402_25V7K
1 2
1 2
C314 0.01UF_0402_25V7K
C315 0.01UF_0402_25V7K
USB20_P6 <10>
USB20_N6 <10>
USB20_P5 <10>
USB20_N5 <10>
CLK_KBD <32>
DAT_KBD <32>
USB3_PRX_DTX_N2 <10>
USB3_PRX_DTX_P2 <10>
USB3_PTX_DRX_N2 <10>
USB3_PTX_DRX_P2 <10>
BREATH_LED# <32,40>
SW_LAN1_ACTLED_YEL# <2 7>
SW_LAN1_MDIP0 <27>
SW_LAN1_MDIN0 <27>
SW_LAN1_MDIP1 <27>
SW_LAN1_MDIN1 <27>
+LOM_VCT
SW_LAN1_MDIP2 <27>
SW_LAN1_MDIN2 <27>
SW_LAN1_MDIP3 <27>
SW_LAN1_MDIN3 <27>
DOCK_DCIN_IS+ <51>
DOCK_DCIN_IS- <51>
DOCK_POR_RST# <32>
10_0402_5%
12
EMC@
R41
HUB_DP1_P0_C
HUB_DP1_N0_C
HUB_DP1_P1_C
HUB_DP1_N1_C
HUB_DP1_P2_C
HUB_DP1_N2_C
HUB_DP1_P3_C
HUB_DP1_N3_C
EMI solution for E-Docking USB
D19
1 2
RB751S40T1G_SOD523-2
10_0402_5%
12
EMC@
R6
C294 0.1U_0402_25V6
C296 0.1U_0402_25V6
C298 0.1U_0402_25V6
C303 0.1U_0402_25V6
C305 0.1U_0402_25V6
C307 0.1U_0402_25V6
C308 0.1U_0402_25V6
C309 0.1U_0402_25V6
SATA_PRX_DTX_P1 <10>
SATA_PRX_DTX_N1 <10>
SATA_PTX_DRX_P1 <10>
SATA_PTX_DRX_N1 <10>
+LOM_VCT
1U_0402_6.3V6K
@
12
C316
CLK_PCI_DOCKDAI_12MHZ# DAI_BCLK#
10_0402_5%
12
R273
EMC@
12
12
12
12
12
12
12
12
DOCK_DET#
HUB_DP1_P0 <24>
HUB_DP1_N0 <24>
HUB_DP1_P1 <24>
HUB_DP1_N1 <24>
HUB_DP1_P2 <24>
HUB_DP1_N2 <24>
HUB_DP1_P3 <24>
HUB_DP1_N3 <24>
0.033U_0402_16V7K
@EMC@
12
C311
Close to DOCK
Its for Enhance ESD on dock
issue.
1 2
1
HUB_DP1_HPD
+3.3V_ALW2
R272100K_0402_5%
100K_0402_5%
12
R271
LINK JAE_WD2F144WB5R400 DONE
A A
4.7P_0402_50V8C
12
C43
EMC@
4.7P_0402_50V8C
12
C42
EMC@
4.7P_0402_50V8C
12
C319
EMC@
EMI depop location
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
E-Dock
E-Dock
E-Dock
LA-C621P
LA-C621P
LA-C621P
38 60Thursday, September 24, 2015
38 60Thursday, September 24, 2015
38 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 39
5
Vinafix.com
4
3
2
1
Touch Pad
+3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
12
D D
DAT_TP_SIO<32>
CLK_TP_SIO<32>
+3.3V_TP +3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
12
12
C C
I2C_1_SDA<9>
I2C_1_SCL<9>
B B
RSMRST circuit
PCH_RSMRST#<32>
ALW_PWRGD_3V_ 5V< 44>
RZ21
RZ20
@
RZ26 0_0402_5%
@
RZ29 0_0402_5%
Reserve for future use
+3.3V_ALW
5
1
P
B
2
A
G
3
TC7SH08FU_SSOP5~D
12
RZ18
330P_0402_50V8J
12
12
CZ30
EMC@
EMI depop location
12
12
@
CZ34
1 2
0.1U_0201_10V6K
4
O
UZ6
RZ19
@
RZ22 0_0402_5%
@
RZ23 0_0402_5%
330P_0402_50V8J
CZ31
EMC@
I2C_1_SDA_R
I2C_1_SCL_R
DAT_TP_SIO_R
12
CLK_TP_SIO_R
12
10K_0402_5%
12
12
RZ116
PCH_RSMRST#_Q <11,14>
10K_0402_5%
RZ117
+3.3V_RUN +3.3V_TP
PJP16
1 2
PAD-OPEN1x1m
Keyboard
KB_DET#<9>
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117<32>
BC_DAT_ECE1117<32>
BC_CLK_ECE1117<32>
+3.3V_TP
TOUCHPAD_INTR#<12>
Reserve for future use
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C_1_SDA_R
I2C_1_SCL_R
Link 50506-02041-P0 DONE
eDP Cable W CAM@
Part Number
DC02C007600 H-CONN SET 13D MB-EDP-CAMERA
eDP TS Cable W CAM@
Part Number
DC02C007C00 H-CONN SET 13D MB-EDP-CAMERA-TS
eDP Cable W/O CAM@
Part Number
DC02C007D00 H-CONN SET 13D MB-EDP
SATA SPINDLE Cable@
Part Number
DC02C007500 H-CONN SET 13D MB-SPINDLE HDD
SATA Cable@
Part Number
DC02C007400 H-CONN SET 13D MB-MSATA HDD
DC-IN Cable@
Part Number
DC30100Q100 CONN SET 13F DCJACK-MB 2DW1003-041110F
BATT Cable@
Part Number
DC02001X800 H-CONN SET 13D MB-BATT CABLE
Description
Description
Description
Description
Description
Description
Description
CONN@
JKBTP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
ACES_50506-02041-P01
LED FFC@
Part Number
NBX0001JG00 FFC 10P F P0.5 PAD0.3 172MM MB-LED/B 13D
FP FFC@
Part Number
NBX0001JK00 FFC 8P F P0.5 PAD.3 123MM MB-FP VALIDITY
TP FFC@
Part Number
NBX0001JI00 FFC 16P F P0.5 PAD=0.3 119MM MB-TP 13D
USH Board FFC@
Part Number
NBX0001JJ00 FFC 26P G P0.5 PAD.3 88MM MB-USH/B 13D
RTC BATT@
Part Number
GC02001DS00 BATT CR2032 3V 225MAH PA 5 W/C 30MM
@FAN
Part Number Description
DC28A000800
@Speak
Part Number Description
PK230003Q0L
0.1U_0201_10V6K
1
@
CZ27
2
Place close to JKBTP1
Description
Description
Description
Description
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
SPK PACK ZJX 2.0W 4 OHM FG
+5V_RUN+3.3V_ALW+3.3V_TP
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
@
@
CZ28
CZ29
2
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-C621P
LA-C621P
LA-C621P
39 60Thursday, September 24, 2015
39 60Thursday, September 24, 2015
39 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 40
5
Vinafix.com
4
3
2
1
HDD LED solution for White LED
+3.3V_ALW
10K_0402_5%
12
RZ24
QZ3B
D D
PCH_SATA_LED#<10,35>
MASK_SATA_LED#<31>
LED_SATA_DIAG_OUT#<31>
DMN65D8LDW-7_SOT363-6
5
DZ3
1 2
34
RB751S40T1G_SOD523-2
DZ4
1 2
RB751S40T1G_SOD523-2
SYS_LED_MASK#
QZ3A
DMN65D8LDW-7_SOT363-6
1
2
SATA_LED#
6
2
SATA_LED
DDTA114EUA-7-F_SOT323-3
1 3
1 2
RZ27 220_0402_5%
QZ4
Battery LED
BAT2_LED#<32>
BAT1_LED#<32>
1 2
RZ25 220_0402_5%
1 2
RZ28 330_0402_5%
BATT_WHITE#
BATT_YELLOW#
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
C C
BREATH_LED#<32,38>
+3.3V_ALW
@
CZ48
1 2
0.1U_0201_10V6K
5
1
SYS_LED_MASK#<27,31>
LID_CL#<31,40>
B B
B
2
A
3
P
MASK_BASE_LEDS#
4
O
G
UZ10
TC7SH08FU_SSOP5~D
POWER & INSTANT ON SWITCH
SW3
1
POWER_SW#_MB<11,32>
2
4
SKRBAAE010_4P
3
QZ7B
DMN65D8LDW-7_SOT363-6
34
5
MASK_BASE_LEDS#
BREATH_LED#_Q BREATH_WHITE_LED_SNIFF #
1 2
RZ32 150_0402_5%
1 2
RZ34 220_0402_5%
BREATH_WHITE_LED#
LTW-C193DC-C_WHITE
Place LED3 close to SW3
LED board CONN
BREATH_WHITE_LED#
SATA_LED
BATT_YELLOW#
BATT_WHITE#
LID_CL#<31,40>
+3.3V_ALW
LED3
21
+5V_ALW
+5V_ALW
CONN@
JLED1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
GND1
10
GND2
ACES_50506-00841-P01
Fiducial Mark
FD1@
1
FIDUCIAL MARK~D
FD2@
A A
1
FIDUCIAL MARK~D
FD3@
1
FIDUCIAL MARK~D
FD4@
1
FIDUCIAL MARK~D
5
Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
CPU NGFF
H1@
H3P8
1
H4@
H3@
H2@
H3P8
1
H5@
H3P8
H3P8
H_2P6N
1
1
LED Circuit Control Table
H6@
H_3P0X2P0N
1
1
SYS_LED_MASK# LID_CL#
0
1 0
H7@
H9@
H_3P2
H8@
H_0P9N
H_3P2
1
1
H11@
H10@
H12@
H_2P4
H_0P8N
H_2P4
1
1
1
4
X
H14@
H13@
H_2P4
H_2P4
1
1
1
H_2P4
H17@
H16@
H15@
H_2P4
H_2P4
1
1
1
H_2P4
H21@
H18@
H19@
H_2P4
1
H23@
H20@
H_2P4
H_3P3
H_2P4
1
1
1
H25@
H22@
H24@
H_3P8
H_2P4
H_2P4
1
1
1
1
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAD, LED
PAD, LED
PAD, LED
LA-C621P
LA-C621P
LA-C621P
1
40 60Thursday, September 24, 2015
40 60Thursday, September 24, 2015
40 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 41
5
Vinafix.com
4
3
2
1
PJP23
+3.3V_ALW
D D
3.3V_WWAN_EN<31>
3.3V_WWAN_EN
1 2
+5V_ALW
3.3V_WWAN_EN
SIO_SLP_LAN#<11,32>
RZ40 100K_0 402_5%
UZ2
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
VBIAS
GND
ON2
VIN2
VOUT2
VIN27VOUT2
GPAD
CT1
CT2
4
5
6
EM5209VF_SON14_2X3
14
13
12
11
10
9
8
15
+3.3V_WWAN_UZ2
+3.3V_LAN_UZ2
1 2
PAD-OPEN1x3m
1 2
@
CZ39 0.1U_020 1_10V6K
1 2
CZ38 470P_0402_50V7K
1 2
CZ23 470P_0402_50V7K
1 2
@
CZ50 0.1 U_0201_10V6K
PJP13
1 2
PAD-OPEN1x1m
2.5A
+3.3V_WWAN
+3.3V_LAN
1A
+3.3V_WLAN/+3.3V_RUN source
AUX_EN_WOWL
1 2
C C
SIO_SLP_WLAN#<11,31>
AUX_EN_WOWL<31>
RZ38 100K_0 402_5%
RUN_ON
+5V_ALW
1 2
RZ71 0_0402_5%@
1 2
@
RZ70 0_0402_5%
+3.3V_ALW
UZ3
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
4
5
6
SWAP for BC12 layout routing
CT1
VBIAS
GND
ON2
CT2
VIN2
VOUT2
VIN27VOUT2
GPAD
EM5209VF_SON14_2X3
14
13
12
11
10
9
8
15
+3.3V_RUN_UZ3
+3.3V_WLAN_UZ3
PJP22
1 2
PAD-OPEN1x3m
1 2
@
CZ47 0.1 U_0201_10V6K
1 2
CZ46 470P_0402_50V7K
1 2
CZ37 470P_0402_50V7K
1 2
@
CZ36 0.1 U_0201_10V6K
PJP12
1 2
PAD-OPEN1x2m
3.435A
+3.3V_RUN
+3.3V_WLAN
2A
+3.3V_M source+3.3V_WWAN/+3.3V_LAN source
@
+3.3V_ALW
A_ON<32>
+5V_ALW
UZ8
1
VOUT
VIN
2
VOUT
VIN
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
GND
GND
7
+3.3V_M_UZ8
8
6
CT
5
9
1 2
PAD-OPEN1x1m
1 2
@
CZ43 0.1 U_0201_10V6K
1 2
CZ42 470P_0402_50V7K
@
+3.3V_M
0.013A
PJP20
+5V_RUN/+3.3V_ALW_PCH source
PJP21
+5V_ALW
RUN_ON<32,47>
PCH_ALW_ON<32>
SIO_SLP_SUS#<8,11,17,18,32,46,47,48>
RZ65 0_0402_ 5%@ 1 2
1 2
@
RZ64 0_0402_ 5%
+3.3V_ALW
UZ4
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VOUT2
VIN27VOUT2
EM5209VF_SON14_2X3
CT1
GND
CT2
GPAD
14
+5V_RUN_UZ4
13
12
11
10
9
+3.3V_ALW_PCH_UZ24
8
15
1 2
PAD-OPEN1x2m
1 2
@
CZ44 0.1 U_0201_10V6K
1 2
CZ45 470P_0402_50V7K
CZ69 47 0P_0402_50V7K
@
CZ64 0.1 U_0201_10V6K
1 2
PAD-OPEN1x1m
1 2
1 2
PJP19
2A
+5V_RUN
0.63A
+3.3V_ALW_PCH
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Power control
Power control
Power control
LA-C621P
LA-C621P
LA-C621P
1
41 60Thursday, September 24, 2015
41 60Thursday, September 24, 2015
41 60Thursday, September 24, 2015
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 42
5
Vinafix.com
4
3
2
1
DMN65D8LDW-7_SOT363-6
QN1A
5
RES
12
INT 1
11
INT 2
6
7
GND
8
GND
HDD CONN
HDD CONN
HDD CONN
LA-C621P
LA-C621P
LA-C621P
+5V_HDD
100K_0402_5%
12
RN1@
FFS_INT2_Q
DMN65D8LDW-7_SOT363-6
34
QN1B
5
JSATA1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3
G4
1
HDD_FALL_INT <10>
CONN@
42 60Thursday, September 24, 2015
42 60Thursday, September 24, 2015
42 60Thursday, September 24, 2015
FFS_INT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
STARC_115B20-100020-G2-R
1.0
1.0
1.0
pin 3
pin 3
pin 3pin 3
Pericom
Pericom
PericomPericom
TDet_B#
GND
TI
GND
Parade
D D
SATA_PTX_DRX_P0<10 >
SATA_PTX_DRX_N0<10>
SATA_PRX_DTX_N0<10>
SATA_PRX_DTX_P0<10 >
Pericom PI3EQX6741ST
TI SN75LVCP601
C C
Main
Pericom
2nd
pin 13
pin 13
pin 13pin 13
pin 6
pin 6
pin 6pin 6
NC
TDet_A#
GND
DEW2
REXT
B_EQ2
1 2
CN47 0.01UF_0402_25V7K
1 2
CN50 0.01UF_0402_25V7K
1 2
CN45 0.01UF_0402_25V7K
1 2
CN48 0.01UF_0402_25V7K
0
NC
1 1.5dB
0
TI
NC
1
pin 16
pin 16 pin 18
pin 18
pin 16pin 16
pin 18pin 18
NC
TDeT_EN
DEW1
GND
DEW
A_EQ2
SATA_PTX_C_RD_DRX_P0
SATA_PTX_C_RD_DRX_N0
SATA_PRX_C_RD_DTX_N0
SATA_PRX_C_RD_DTX_P0
HDD_A_EQ
(RN13)
A_EQ
14dB 14dB
SATA Repeater
UN7
X76@
DEW2
DEW1
HDD_A_EQ HDD_B_EQ
PIN17
NC
PD
(RN13)
PD
3dB
6dB
9dB
7dB
0dB
6
NC
16
NC
3
TDet_B#
17
21
PI3EQX6741STZDEX_TQFN20_4X4
HDD_B_EQ
HDD_A_EQ2
PIN19
PD
(RN16)
NC
PD
(RN16)
TDet_A#
A_EQ
9
A_EM
7
TDeT_EN
EN
1
AI+
2
AI-
4
BO-
5
BO+
GND
HDD_B_EQ2 DEW2 HDD_A _PRE HDD_B_PRE
PIN18
PD
(RN23)
(RN83)
PD
(RN23)
(RN83)
PD
(RN23)
(RN83)
B_EQ B_EM
3dB
NC
6dB
9dB
7dB
0dB
1
0
NC
1.5dB
1
+3.3V_HDD
0.01UF_0402_25V7K
1
1
CN46
2
2
10
VDD
20
VDD
HDD_B_EQ2
13
19
B_EQ
HDD_B_PREHDD_A_PRE
8
B_EM
HDD_A_EQ2
18
SATA_PTX_RD_DRX_P0
15
AO+
SATA_PTX_RD_DRX_N0
14
AO-
SATA_PRX_RD_DTX_N0
12
BI-
SATA_PRX_RD_DTX_P0
11
BI+
DEW1
NC
NC
PIN6
NCNC
NC
(IPU)
PD
(RN19)
PIN16PIN13 PIN9 PIN8
PD
PD
(IPU)
PDParade PS8527C
(1/2 VDD)
A_EM
0dB0
0dB
-4dB
-2dB
0dB
0dB
-4dB
-2dB
0.1U_0201_10V6K
CN49
(1/2 VDD)
NC
(IPU)
PH
(RN8)
NC
PD
(RN11)
PH
(RN10)
NC
(1/2 VDD)
HDD_A_PRE
HDD_B_PRE
HDD_A_EQ
HDD_B_EQ
DEW2
DEW1
HDD_B_EQ2
HDD_A_EQ2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
X76@
X76@
12
@
RN12
RN10
RN8
1 2
4.7K_0402_5%
4.7K_0402_5%
@
RN9
4.7K_0402_5%
X76@
X76@
RN11
RN13
1 2
1 2
EQ1EQ2 A_EMB_EQ B_EMA_EQ
B B
3rd
Parade
+3.3V_ALW
12
RN6
@
10K_0402_5%
12
10K_0402_5%
HDD_EN
RN7@
A A
(M = VDD/2)
M
0
0 0
0
M
M 0
M 1
1 M
1 0
1 1
5
2.4dB
7.4dB
14.4dB
1
12.2dB
M
9.4dB
13.3dB
6.2dB
11.2dB
5dB
HDD_EN<9>
2.4dB
7.4dB
14.4dB
12.2dB
9.4dB
13.3dB
6.2dB
11.2dB
0
M
1
5dB
+5V_HDD source
+5V_ALW
UZ23
1
VIN
2
VIN
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
VOUT
VOUT
GND
GND
CT
0dB
-3.5dB
-1.5dB
7
+5V_HDD_UZ2
8
6
5
9
4
0dB
-3.5dB
-1.5dB
* red color is current setting
PJP805
1 2
1 2
1.5A
+5V_HDD
1 2
PAD-OPEN1x1m
@
CZ99 0.1U_0201_10V6K
CZ100 470P_0402_50V7K
PJP1603
@
PAD-OPEN1x1m
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+5V_HDD+5V_RUN
12
3
+3.3V_HDD
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
12
12
@
@
RN18
7.87K_0402_1%
X76@
RN19
1 2
DDR_XDP_WAN_S MBDAT<8,14,20,21>
DDR_XDP_WAN_S MBCLK<8,14,20,21>
SATA_PTX_RD_DRX_P0
SATA_PTX_RD_DRX_N0
SATA_PRX_RD_DTX_N0
SATA_PRX_RD_DTX_P0
+3.3V_RUN
1000P_0402_50V7K
CN13
12
@
RN20
4.7K_0402_5%
@
RN21
0.1U_0201_10V6K
CN14
RN14
1 2
4.7K_0402_5%
X76@
RN16
1 2
1 2
+5V_HDD +3.3V_HDD
12
Place near HDD CONN
12
1 2
12
4.7K_0402_5%
12
@
RN22
4.7K_0402_5%
12
RN23
1 2
PAD-OPEN1x2m
0.1U_0201_10V6K
@
CN15
4.7K_0402_5%
12
@
RN84
4.7K_0402_5%
12
RN83
12
+3.3V_HDD
CN43 0.01UF_0402_25V7K
CN44 0.01UF_0402_25V7K
CN18 0.01UF_0402_25V7K
CN17 0.01UF_0402_25V7K
PJP36
+5V_HDD
0.1U_0201_10V6K
CN16
12
2
+3.3V_RUN
100K_0402_5%
12
RN2
6
FFS_INT2
FFS_INT2<8>
+3.3V_RUN
0.1U_0201_10V6K
10U_0603_10V6M
12
CN2
CN1
1 2
RN5@ 10K_0402_5%
12
12
12
12
+3.3V_HDD
HDD_DEVSLP<10>
HDD_DET#<10>
2
1
Free Fall Sensor
UN1
LNG2DM
10
VDD_IO
9
VDD
3
SDO/SA0
4
SDA/SDI/SDO
SCL/SPC1GND
2
CS
LNG2DMTR_LGA12_2X2
HDD_DEVSLP
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
FFS_INT2_Q
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Page 43
5
Vinafix.com
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR2
PD1
PQ2
1 3
1
2
12
3
PBAT_PRES# <32,51,52>PBAT_SMBCLK <32>
3
2
PC4
1500P_0402_50V7K
1
2
1K_0402_5%
+Z4012
2
+RTC_CELL
1
1
PC2
1U_0603_25V6K
2
DOCK_SMB_ALERT# <31,38>
PU1
NO
GND
NC3COM
TS5A63157DCKR_SC70-6~D
6
IN
5
V+
4
+COINCELL
+3.3V_RTC_LDO
D D
1
PD2
EMC@
TVNST52302AB0_SOT523-3
2
Primary Battery Connector
PBATT1
@
1
1
2
2
3
3
4
4
5
5
12
PC3
EMC@
2200P_0402_50V7K
C C
B B
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
DEREN_40-42251-01001RHF
NB_PSID
PBAT_SMBCLK_C
PBAT_SMBDAT_C
PBAT_PRES#_C
GND
2
3
PD6
PESD5V0U2BT_SOT23-3
1
EMC@
BLM15AG102SN1D_2P
EMC@
PL4
PRP1
100_0804_8P4R_5%
12
3
18
27
36
45
100K_0402_1%
15K_0402_1%
PR8
PR10
1
EMC@
TVNST52302AB0_SOT523-3
2
3
1 2
1 2
PD3
PBATT+_C
PBAT_SMBDAT <32>
PR5
@
1 2
0_0402_5%
1 3
D
S
PQ3
FDV301N-G_SOT23-3
G
2
C
2
PQ4
B
MMST3904-7-F_SOT323~D
E
3 1
PR7
33_0402_5%
1 2
PL2
EMC@
FBMJ4516HS720NT_2P
1 2
PL3
EMC@
FBMJ4516HS720NT_2P
1 2
+5V_ALW
12
PR9
10K_0402_1%
1 2
10K_0402_5%
@
+PBATT
PR11
SLICE_BAT_PRES#<31,38,52>
+3.3V_ALW
PR6
2.2K_0402_5%
1 2
+3.3V_ALW
12
PR3
100K_0402_5%
PD4
1 2
SDMK0340L-7-F_SOD323-2~D
DOCK_PSID<38>
NB_PSID_TS5A63157
PSID_DISABLE# <31>
PR4
1 2
0_0402_5%~D
2
3
1
BAS40CW SOT-323
DMG2301U-7 1P SOT23-3
EMC@
PD7
PESD5V0U2BT_SOT23-3
12
PC8
2200P_0402_50V7K
@EMC@
ACES_50271-0020N-001
GPIO_PSID_SELECT <31>
+5V_ALW
PS_ID <32>
JRTC1
@
1
3
1
G
4
22G
DC_IN+ Source
+DC_IN
PL1
EMC@
FBMJ4516HS720NT_2P
1 2
PQ1B
@
PJPDC1
@
-DCIN_JACK-DCIN _JACK
1
1
2
2
+DCIN_JACK
3
3
A A
4
4
5
5
ACES_50290-0050N-001
12
PC1
EMC@
1000P_0603_50V7K
12
PC6
0.1U_0603_25V7K
@EMC@
2
12
16
PR13
4.7K_0805_5%
@
DCX124EK-7-F PNP/NPN_SC74-6~D
@
PQ1A
4 3
5
DCX124EK-7-F PNP/NPN_SC74-6~D
AC_DIS <31,51,52>
12
PR1
PC5
1 2
1M_0402_5%
0.022U_0805_50V7K
PQ5
S TR AON7401 1P DFN
1
2
3 5
PR14
1 2
10K_0402_5%
12
PR15
1M_0402_5%
4
SOFT_START_GC <52>
12
PR12
+DC_IN_SS
12
PC7
100K_0402_5%
10U_0805_25V6K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
1
43 60Thursday, September 24, 2015
43 60Thursday, September 24, 2015
43 60Thursday, September 24, 2015
Title
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1.0
1.0
1.0
Page 44
A
Vinafix.com
1 1
+PWR_SRC
PJP100
21
PAD-OPEN 1x2m~D
PC100
0.1U_0402_25V6
@EMC@
2 2
+3.3V_ALW
12
PC103
2200P_0402_50V7K
@EMC@
PR107
100K_0402_5%
1 2
PGOOD_3V
3V_VIN
12
PC105
10U_0805_25V6K
+PWR_SRC
PJP101
21
PAD-OPEN 1x2m~D
3 3
PR114
ALWON<32>
4 4
1 2
0_0402_5%~D
12
5V_VIN
12
12
PC116
2200P_0402_50V7K
@EMC@
3V5V_EN
PC128
4.7U_0402_6.3V6M
PC117
10U_0805_25V6K
12
PC118
10U_0805_25V6K
PR113
100K_0402_5%
1 2
PC115
0.1U_0402_25V6
@EMC@
PR116
1M_0402_1%
+3.3V_ALW
12
EN1 and EN2 dont't floating
12
PC104
@
12
PGOOD_5V
B
2
5
12
10U_0805_25V6K
LX_3V
3V5V_EN
LX_5V
PU102
6
7
8
9
10
PU100
6
LX
7
GND
8
SY8288BRAC QFN 20P PWM
GND
9
PG
10
NC
11
ENLDO_3V5V
5
LX
GND
SY8286CRAC_QFN20_3X3
GND
PG
NC
11
3V5V_EN
ENLDO_3V5V
EN112EN2
EN112EN2
IN3IN4IN
FF13OUT14LDO
1
IN
IN3IN4IN
BS
LX
LX
GND
LDO
NC
GND
FF13OUT14NC
15
PC113
1000P_0402_50V7K
3V_FB
1 2
BST_5V
2
1
IN
BS
LX
LX
GND
VCC
NC
GND
15
+5V_ALW2
5V LDO 150mA~300mA
12
PC126
4.7U_0603_6.3V6K
PC127
1000P_0402_50V7K
5V_FB
20
19
18
17
16
21
20
19
18
17
16
21
PC119
1 2
1 2
4.7U_0603_6.3V6K
C
PC101
@
0.1U_0402_10V7K
1 2
PGOOD_3V
PGOOD_5V
PR100
BST_3V
1 2
0_0603_5%~D
LX_3V
PR104
0_0402_5%~D
1 2
1 2
PR105
0_0402_5%~D
3.3V LDO 150mA~300mA
12
PC111
4.7U_0603_6.3V6K
PR108
1K_0402_5%
1 2
PR111
1 2
0_0603_5%~D
LX_5V
PR117
1K_0402_5%
1 2
+3.3V_ALW
5
1
P
B
O
2
A
G
3
TC7SH08FU_SSOP5~D
+3.3V_RTC_LDO
PC114
1 2
0.1U_0603_25V7K
4
PU101
@
PC102
1 2
0.1U_0603_25V7K
+3.3V_ALW2
@EMC@
@EMC@
0_0402_5%~D
PR119
1 2
PR101
@
0_0402_5%
1 2
PR120
1 2
0_0402_5%~D
1.5UH_PCMC063T-1R5MN_9A_20%
1 2
PR106
12
Update PH401 change
to Common Part
SH000016800 20141202
4.7_1206_5%
@EMC@
3V_SN
12
PC112
@EMC@
680P_0603_50V7K
PR109
@
PR110
@
2.2UH +-20% 7.8A 7X7X3 MOLDING
1 2
12
PR112
Update PH401 change
to Common Part
SH000016800 20141202
4.7_1206_5%
5V_SN
12
PC125
680P_0603_50V7K
150K_0402_1%
150K_0402_1%
PL101
PL100
12
12
PR115
@
PR118
@
D
ALW_PWRGD_3V_ 5V <39>
PR102
ENLDO_3V5V
PR103
499K_0402_1%
1 2
12
499K_0402_1%
12
12
PC106
22U_0805_6.3V6M
Vout is 3.234V~3.366V
12
12
150K_0402_1%
12
150K_0402_1%
E
+PWR_SRC
+3.3V_ALWP
12
12
PC107
22U_0805_6.3V6M
12
PC120
22U_0805_6.3V6M
12
PC109
PC108
22U_0805_6.3V6M
PC110
@
22U_0805_6.3V6M
+3.3V_ALWP +3.3V_ALW
3VALWP
TDC 7.087 A
Peak Current 8.504 A
22U_0805_6.3V6M
OCP Current 9 A fix by IC
PJP102
112
JUMP_43X118
PJP103
112
JUMP_43X118
2
2
+5V_ALWP
12
PC121
22U_0805_6.3V6M
5VALWP
TDC 4.5 A
Peak Current 6.3 A
OCP Current 9 A fix by IC
12
12
PC122
22U_0805_6.3V6M
PC124
PC123
@
22U_0805_6.3V6M
22U_0805_6.3V6M
+5V_ALW+5V_ALWP
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
44 60Thursday, September 24, 2015
44 60Thursday, September 24, 2015
44 60Thursday, September 24, 2015
E
1.0
1.0
1.0
Page 45
5
Vinafix.com
4
3
2
1
0.6Volt +/- 5%
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A fix by IC
D D
+PWR_SRC
+1.2V_MEN_P
For RT8207P
C C
12
PC220
B B
12
12
PC218
22U_0603_6.3V6M
22U_0603_6.3V6M
PJP202
PAD-OPEN 1x2m~D
12
PC216
PC217
22U_0603_6.3V6M
22U_0603_6.3V6M
1.2V_B+
21
12
PC201
10U_0805_25V6K
12
22U_0603_6.3V6M
PL201
1 2
PC219
22U_0603_6.3V6M
1UH_PCMB063T-1R0MS_ 12A_20%
12
PC215
12
PC202
@
10U_0805_25V6K
12
12
PC203
2200P_0402_50V 7K
@EMC@
Footprint use AON6932A
AON6994 2N DFN5X6D
12
PR204
4.7_1206_5%
@EMC@
SNUB_1.2V
12
PC211
680P_0603_50V7 K
@EMC@
SIO_SLP_S4#<1 1,17,32,54>
PC204
@EMC@
PQ201
0.1U_0402_25V6
S2
3
PR208
1 2
0_0402_5%~D
PR202
1 2
2.2_0603_5%
12
PC205
0.22U_0603_16V7K
1
2
7
D1
G1
S1/D2
S2
G26S2
4
5
PR205
1 2
5.1_0603_5%
+5V_ALW
BOOT_1.2V
PR203
5.1K_0402_1%
1 2
1U_0603_10V6K
PC209
1U_0603_10V6K
DH_1.2V
SW_ 1.2V
DL_1.2V
PC207
VDD_1.2V
CS_1.2V
12
PR201
2.2_0603_5%
PU201
15
LGATE
14
PGND
13
CS
12
VDDP
11
VDD
+VLDOIN_1.2V
17
16
10
18
19
PHASE
RT8207PGQW _WQFN20_3X3
PGOOD
BOOT
UGATE
TON
9
VLDOIN
S5
S3
8
7
20
VTT
PAD
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
6
1.2V_FB
+5V_ALW
For RT8207P
PR207
1 2
453K_0402_1%
PR210
1 2
0_0402_5%~D
12
PC214
@
.1U_0402 _16V7K
1.2V_B+
S5_1.2V
0.6V_DDR_VTT_ON<20>
PJP203
1 2
PAD-OPEN1x1m
21
1
2
3
+V_DDR_ REF
4
5
+1.2V_MEN_P
12
+1.2V_MEN_P
FB sense trace
w
hen FB pull down to GND
PR206
12K_0402_1%
1 2
PC212
100P_0402_50V8 J
1 2
12
PR209
20K_0402_1%
12
PC213
@
.1U_0402 _16V7K
+0.6V_P
PC206
22U_0603_6.3V6M
+V_DDR_REF
PC210
0.033U_0402_16V7 K
Mode S3 S5 +1.2V_MEN +V_DDR_REF +0.6V_P
+1.2V_MEN_P
S5 L L off off off
S3 L H on on off
S0 H H on on on
FB sense trace
+1.2V_MEM
TDC 8.75 A
Peak Current 12.25 A
OCP Current 14.7 A
TYP MAX
H/S Rds(on) 6.7mohm , 8.5mohm
L/S Rds(on) 2.4mohm , 3.2mohm
A A
Choke DCR 3.0mohm , 3.5mohm
CAP ESR 11mohm
5
+1.2V_MEN_P
4
PJP204
112
JUMP_1x3m
PJP201
112
JUMP_1x3m
2
PJP205
2
+1.2V_MEM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+0.6V_P
3
1 2
PAD-OPEN1x1m
+0.6V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
+1.2V_MEN/+0.6V_DDR_VTT
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
45 60Thursday, September 24, 2015
45 60Thursday, September 24, 2015
45 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 46
5
Vinafix.com
D D
+PWR_SRC
C C
PJP301
PAD-OPEN 1x2m~D
21
12
12
PC301
PC303
0.1U_0402_25V6
2200P_0402_50V 7K
@EMC@
@EMC@
+3.3V_ALW
12
PR307
@
0_0402_5%
ILMT_+1VALWP
12
PR310
@
0_0402_5%
+1.0V_PRIM
10U_0805_25V6K
12
PC305
@
4
+1VALW P_B+
12
PC306
10U_0805_25V6K
ILMT_+1VALWP
PU301
8
IN
EN
GND
ILMT
PG
BS
LX
FB
BYP
LDO
9
3
2
SYX196DQNC_QFN10_3X3
1
BST_+1VALW P
6
10
4
7
5
12
3
EN_+1VALW P
0.1U_0603_25V7K
SW_+1VAL WP
12
PC313
4.7U_0603_6.3V6K
PC304
1 2
PC312
4.7U_0603_6.3V6K
BST_+1VALW P_C
+3.3V_ALW
12
1M_0402_1%
PR302
PR304
1 2
0_0603_5%~D
PR312
1 2
0_0402_5%~D
PR303
@EMC@
4.7_1206_5%
1 2
0.68UH_MMD-05CZ-R68M-X2L_ 8.5A_20%
FB_+1VALW P
PL301
1 2
SNB_+1VALW P
12
PR306
6.65K_0402_1%
12
PR311
10K_040 2_1%
2
SIO_SLP_SUS# <8,11,17 ,18,32,41,47,48>
+1VALWP
PC302
@EMC@
680P_0603_50V7 K
1 2
12
12
12
PC307
12
PR308
1K_0402_5%
PC308
47U_0805_6.3V6M
330P_0402_50V7 K
1
PJP302
2
112
JUMP_43X118
+1.0V_PRIM
+1VALWP
12
12
PC310
PC309
@
47U_0805_6.3V6M
PC311
22U_0805_6.3VAM
22U_0805_6.3VAM
TDC 5 A
Peak Current 7 A
B B
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
The current limit is set to 6A, 9A or 12A when this pin
s pull low, floating or pull high
i
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+1VALWP
+1VALWP
+1VALWP
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
46 60Thursday, September 24, 2015
46 60Thursday, September 24, 2015
46 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
2
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 47
5
Vinafix.com
4
3
2
1
+3.3V_ALW
PR425
@
PR403
1M_0402_1%
VIN_1VS_VCCIO
VID0_VCCIO
VID1_VCCIO
1 2
0_0402_5%
12
12
PC402
@
0.1U_0402_25V6
12
11
10
9
SIO_SLP_S0#<11,17,33,47>
PR402
RUN_ON<32,41>
D D
Vin=3~17V
+5V_ALW
+3.3V_ALW
12
@
10K_0402_1%
12
C C
10K_0402_1%
PR413
PR415
12
PR414
10K_0402_1%
12
PR416
@
10K_0402_1%
VID0_VCCIO
VID1_VCCIO
@
PJP403
1 2
PAD-OPEN1x1m
12
PC408
0.1U_0402_25V6
@EMC@
12
PC409
2200P_0402_50V7K
@EMC@
1 2
0_0402_5%~D
12
12
PC403
PC404
10U_0603_10V6M
10U_0603_10V6M
"R" for SILERGY
PR426
@
SIO_SLP_S0#<11,17,33,47>
1 2
0_0402_5%
12
EN_1VS_VCCIO
14
13
PU401
EN
PVIN
PVIN
S IC SY8057QDC QFN 16P PWM
AVIN
VID0
VID1
8
PR427
0_0402_5%~D
1 2
+3.3V_ALW
12
PR404
0_0402_5%
LPM
7
SS_1VS_VCCIO
12
PR410
0_0402_5%
PJP401
@
JUMP_43X79
2
17
15
TP
PGND16PGND
1
VOS
2
SW
3
SW
4
PG
FBS5AGND6SS
PC410
@
470P_0402_50V7K
LX_1VS_VCCIO
+1VS_VCCIOP
PL402
1UH_1277AS-H-1R0N-P2_3.3A_30%
1 2
12
PR405
@EMC@
4.7_0603_5%
SNUB_1VS_VCCIO
12
PC401
@EMC@
470P_0402_50V7K
PR412
0_0402_5%~D
+1VS_VCCIOP
12
PR421
100_0402_1%
12
PR422
12
0_0402_5%~D
12
12
PC406
PC407
22U_0603_6.3V6M
VCCIO_SENSE < 17>
VSSIO_SENSE <17>
+1VS_VCCIOP
12
PC422
@
22U_0603_6.3V6M
22U_0603_6.3V6M
+1VS_VCCIOP +1.0VS_VCCIO
+1.0VS_VCCIO
TDC 2.5 A
Peak Current 3.5 A
OCP Current 4.2 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
112
PR406
SIO_SLP_SUS#<8,11,17,18,32,41,46,48>
VID0_PRIM_CORE
VID1_PRIM_CORE
Vin=3~17V
+5V_ALW
@
PJP404
1 2
PAD-OPEN1x1m
12
PC417
0.1U_0402_25V6
@EMC@
CORE_VID0<18>
CORE_VID1<18>
12
PC418
2200P_0402_50V7K
@EMC@
B B
+3.3V_ALW
12
10K_0402_1%
12
@
10K_0402_1%
A A
PR417
PR419
12
PR418
10K_0402_1%
12
PR420
@
10K_0402_1%
5
1 2
12
12
PC413
PC412
10U_0603_10V6M
10U_0603_10V6M
4
0_0402_5%~D
PR407
1M_0402_1%
PR408
@
0_0402_5%
1 2
PR411
@
0_0402_5%
1 2
"R" for SILERGY
12
VIN_1V_PRIM
12
PC411
EN_1.0V_PRIM_COREP
@
0.1U_0402_25V6
12
11
10
9
VID0_PRIM_CORE
14
13
PU402
EN
PVIN
PVIN
S IC SY8057QDC QFN 16P PWM
AVIN
VID0
VID1
8
VID1_PRIM_CORE
17
15
LPM
7
SS_1V_PRIM
12
@
TP
PGND16PGND
1
VOS
SW
SW
PG
FBS5AGND6SS
12
PR428
PC420
@
1M_0402_1%
470P_0402_50V7K
+1.0V_PRIM_COREP
PL404
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1V_PRIM
2
3
4
3
1 2
12
12
PC415
PC424
22U_0603_6.3V6M
22U_0603_6.3V6M
PR409
PC419
PR423
1 2
0_0402_5%~D
Rup
12
@EMC@
4.7_0603_5%
SNUB_1V_PRIM
12
@EMC@
470P_0402_50V7K
12
PR424
@
100K_0402_1%
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
+1.0V_PRIM_COREP
12
PC416
@
22U_0603_6.3V6M
2
+1.0V_PRIM_COREP +1.0V_PRIM_CORE
+1.0V_PRIM_CORE
TDC 1.8 A
Peak Current 2.5 A
OCP Current 4.2 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
+1VS_VCCIOP/+1.0V_PRIM_COREP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PJP402
@
JUMP_43X79
2
112
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
1
47 60Thursday, September 24, 2015
47 60Thursday, September 24, 2015
47 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 48
5
Vinafix.com
D D
4
3
2
PJP502
@
JUMP_43X79
+1.8VALWP
112
1
2
+1.8V_PRIM
PC502
22U_0603_6.3V6M
1 2
PJP501
@
JUMP_43X79
PR505
1M_0402_1%
112
12
+3.3V_ALW
PR504
SIO_SLP_SUS#<8,11,17,18,32,41,46,47>
C C
1 2
0_0402_5%~D
Note:
When design Vin =5V, please stu ff snubber
to prevent Vin damage
2
12
@
0.1U_0402_16V7K
VIN_1.8VALW
EN_1.8VALW
PC505
PU501
SY8032ABC_SOT23-6
4
IN
LX
5
PG
GND
FB6EN
3
2
1
LX_1.8VALW
Imax= 2A, Ipeak = 3A
FB=0.6V
PL501
1UH_1277AS-H-1R0N-P2_3.3A_30%
1 2
12
@EMC@
4.7_0603_5%
SNUB_1.8VALW
12
@EMC@
680P_0402_50V7K
PR502
PC506
20K_0402_1%
FB_1.8VALW
10K_0402_1%
PR501
PR506
12
12
Vout=0.6V* (1+R up/Rdown)
Rup
Rdown
+1.8VALWP
12
PC503
68P_0402_50V8J
12
12
PC504
PC501
22U_0603_6.3V6M
22U_0603_6.3V6M
+1.8V_PRIM
TDC 0.665 A
Peak Current 0.931 A
OCP Current 3.5A fix by IC
+3.3V_RUN
+5V_ALW
PAD-OPEN1x1m
12
PC507
6
5
VIN
4
VOUT
VCNTL
3
VOUT
2
FB
9
VIN
GND
1
AP7175SP-13_SO-8EP-8
1U_0402_6.3V6K
Footprint use APL5930
B B
SIO_SLP_S3#<11,17,32>
+3.3V_RUN
47K_0402_5%
1 2
@
PR507
1 2
100K_0402_5%
47K_0402_5%
PR511
PR509
12
12
PC510
.1U_0402_16V7K
PU502
7
8
@EMC@
POK
EN
PJP503
12
+1.5V_VIN
12
PC508
4.7U_0805_6.3V6K
PR508
8.87K_0402_1%
12
12
PR510
10.2K_0402_1%
1.5VSP
12
PC509
0.01UF_0402_25V7K
PAD-OPEN1x1m
12
PC511
22U_0805_6.3V6M
PJP504
1 2
+1.5V_RUN
+1.5V_RUN
TDC 0.021 A
Peak Current 0.6 A
OCP Current 5.7 A fix by IC
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+1.8VALWP/+1.5VSP
+1.8VALWP/+1.5VSP
+1.8VALWP/+1.5VSP
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
1
48 60Thursday, September 24, 2015
48 60Thursday, September 24, 2015
48 60Thursday, September 24, 2015
Title
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1.0
1.0
1.0
Page 49
5
Vinafix.com
4
3
2
1
+1.0V_VCCST
0_0402_5%~D
12
PR604
PR601
@
75_0402_ 1%
45.3_040 2_1%
+3.3V_RUN
PCH_PWROK<11>
IMVP_VR_ON<32>
0_0402_5%~D
I_SYS<32,51>
470K_0402_5%
VCCSENSE<15>
VSSSENSE<15>
12
12
PR605
100_0402 _1%
VIDSCLK_A
VIDALERT_N_A
VIDSOUT_A
PR620
1 2
FCCM_GT<50>
PWM1_GT<50>
PH603
1 2
27.4K_0402_1%
PR647
1 2
PC629
2200P_0402_50V7K
1 2
PC639
2200P_0402_50V7K
1 2
PR648
1 2
1.37K_0402_1%
PC651
@
1 2
330P_0402_50V7K
PC654
1 2
0.01UF_0402_25V7K
PC602
0.1U_0402_25V6
1 2
1 2
1 2
1 2
1 2
1 2
PR616
0_0402_5%~D
PU602
1
2
3
4
5
6
7
8
9
10
41
PC625
330P_0402_50V7K
1 2
PR629
88.7K_0402_1%
1 2
1 2
10K_0402_1%
PR639
3.6K_0402_1%
1 2
PC636
68P_0402_50V8J
1 2
PR645
1 2
PR62610_0402_1%
PR6121.91K_0402_1%
PR6140_0402_5%~D
PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B
AGND
PR635
316_0402_1%
PR61849.9_0402_1%
PR6250_0402_5%~D
39
40
VR_ENABLE
FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A
12
1 2
12
PC653
@
12
1 2
VIDSOUT_B
VIDSCLK_B
VIDALERT_N_B
35
38
36
37
SCLK
ALERT#
VR_HOT#
VR_READY
16
IMON_IA
NTC_IA
COMP_IA
2K_0402_1%
PR650
PC647
680P_0402_50V7K
0.082U_0402_16V7K
PR608
78.7K_0402_1%
1 2
PR611
48.7K_0402_1%
32
33
34
VIN
SDA
VCC
PROG231PROG1
PWM_C
FCCM_C
ISUMN_C
ISUMP_C
RTN_C
FB_C
COMP_C
IMON_C
PWM_A
FCCM_A
FB_A
RTN_A18ISUMP_A19ISUMN_A
17
20
S IC ISL95857HRTZ-TS2778 TQFN 40P PWM
FB_IA
PR657
4.42K_0402_1%
1 2
ISUMP_IA <50>
12
Local sense put on HW site
PR613
86.6K_0402_1%
1 2
PC613
330P_0402_50V8J
1 2
PR621
316_0402_1%
1 2
PR623
2K_0402_1%
1 2
PR638
374_0402_1%
1 2
1 2
PR606 0_0402_5%~D
1 2
PR607 0_0402_5%~D
1 2
PR609 0_0402_5%~D
PC627
2200P_0402_50V7K
1 2
+5V_ALW
@
PC624
12
PC620
0.033U_0402_16V7K
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
PR678
100_0402_1%
1 2
1200P_0402_50V7K
1 2
1.96K_0402_1%
PC621
680P_0402_50V7K
1 2
0.082U_0402_16V7K
12
PC626
0.047U_0402_25V7K
PC617
PR622
1 2
PR632
1K_0402_1%
1 2
D D
H_PROCHOT#<12,32,51>
470K_0402_5%
VCC_GT_SENSE<16>
C C
VSS_GT_SENSE<16>
ISUMP_GT<50>
ISUMN_GT<50>
B B
A A
PH601
1 2
1 2
PR631
27.4K_0402_1%
2200P_0402_50V7K
@
1 2
330P_0402_50V7K
PC619
1 2
0.01UF_0402_25V7K
12
10K_0402_5%
12
PH602
PC614
1 2
PC618
PR628
PC641
PC616
68P_0402_50V8J
1 2
4.42K_0402_1%
12
PR633
12
.1U_0402_16V7K
1 2
PC605 47P_0402_50V8J~D
PR610
10K_0402_1%
1 2
PR617
3.92K_0402_1%
1 2
12
11K_0402_1%
PR602
1 2
1 2
12
0_0402_5%~D
PR603
PC603
PC604
1U_0603_10V6K
0.22U_0603_25V7K
PWM_VSA
30
FCCM_VSA
29
28
27
26
FB_VSA
25
COMP_VSA
24
IMON_VSA PWM_VSA
23
22
PWM_IA <50>
21
FCCM_IA <50>
12
PC630
2200P_0402_50V7K
12
PR644
1K_0402_1%
PC642
0.033U_0402_16V7K
1 2
PC646
0.047U_0402_25V7K
1 2
PR656
11K_0402_1%
1 2
PH605
10KB_0402_5%
1 2
12
CPU_B+
PR640
340_0402_1%
PC645
.1U_0402_16V7K
12
+5V_ALW
ISUMN_IA <50>
PR619
1 2
2.2_0603_5%
PC611
1 2
0.22U_0603_16V7K
12
PC628
10P_0402_50V8J
PC631
12
330P_0402_50V7K
PC643
PR651
1
2
3
12
PR630
12
1200P_0402_50V7K
12
124K_0402_1%
Local sense put on HW site
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VCC_SA
TDC 3.7A
Peak Current 4.5A
OCP current 5.4A
Choke DCR 13 m ohm
SA_UGATE
PU606
ISL95808HRZ-TS2378_DFN8_2X2
UGATE
BOOT
PWM
GND4LGATE
8
PHASE
7
FCCM
6
VCC
5
TP
9
+5V_RUN
PC632
2200P_0402_25V7K
PR646
1 2
316_0402_1%
1.62K_0402_1%
PR652
2K_0402_1%
PC601
680P_0402_50V7K
2
1 2
PR636 1.24K_0402_1%
1 2
2200P_0402_50V7K
PR649
1 2
7.32K_0402_1%
12
12
PC685
1U_0402_10V6K
1 2
SA_LGATE
12
12
1 2
1K_0402_1%
PC640
PJP603
VCCSA_B+ CPU_B+
1 2
PAD-OPEN1x1m
VCCSA_B+
12
12
PC612
PC608
@
10U_0805_25V6K
10U_0805_25V6K
AON7934_DFN3X3A-8-10
1
4
3
2
PR679
0_0402_5%~D
FCCM_VSA
PR641
D1
D1
D1
D110D2/S1
S2
S2
S2
6
7
5
PQ501
G1
9
G2
8
.1U_0402_16V7K
SA_SW
12
PC637
PC644
1 2
12
@EMC@
PR627
4.7_1206_5%
SA_SNUBSA_SNUB
12
0.033U_0402_16V7K
PC650
@
0.082U_0402_16V7K
PL601
1UH_MMD-05CZ-1R0M-M7L_7A_20%
1 2
12
PR624
3.65K_0603_1%
ISUMP_VSA
PC622
680P_0603_50V7K
@EMC@
12
PC633
6800P_0402_25V7K
PC649
0.01UF_0402_25V7K
1 2
1 2
@
330P_0402_50V7K
1 2
1 2
PC652
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_VCORE_ISL95812 for QC
PWR_VCORE_ISL95812 for QC
PWR_VCORE_ISL95812 for QC
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
1
PR643
11K_0402_1%
ISUMN_VSA
ISUMP_VSA
12
PR642
2.61K_0402_1%
12
10KB_0402_5%
VSA_SEN- <17>
VSA_SEN+ <17>
49 60Thursday, September 24, 2015
49 60Thursday, September 24, 2015
49 60Thursday, September 24, 2015
+VCC_SA
PH604
ISUMN_VSAISUMN_VSA
1.0
1.0
1.0
Page 50
5
Vinafix.com
D D
+PWR_SRC
PJP601
12
2200P_0402_50V7K
PGND2
PWM
BOOT
BOOT_R
VIN
@
0_0402_5%~D
1 2
PAD-OPEN 4x4m
@EMC@
SUPPRE_9A Z80 10M 1812
1
+
PC606
2
100U_D_20VM_R55M
PU603
4
VSW
3
PGND1
2
VDD
1
SKIP#
PR659
<49>
FCCM_IA
PL602
1 2
12
12
PC661
1U_0402_10V6K
CPU_B+
@EMC@
12
12
PC656
PC657
PR662
5.11K_040 2_1%
PC658
10U_0805_25V6K
0.22U_0603_16V7K
2.2_0603_5%
12
10U_0805_25V6K
PWM_IA<49>
C C
12
PC686
10P_0402_50V8K
12
PC659
10U_0805_25V6K
0.1U_0402_25V6K~D
PC655
1 2
1 2
PR660
12
PC680
1000P_0402_50V7K
12
@EMC@
PC660
9
8
7
6
5
CSD97374CQ4M_SON8_3P5X4P5
CORE_SW
+5V_RUN
4
VCC_core
TDC 21A
Peak Current 28A
OCP current 34A
Choke DCR 0.9 +-7%m ohm
PL603
0.15UH_MMD06CZER15MG_37A_20%
1
4
3
12
@EMC@
12
PR661
PR663
3.65K_0603_1%
4.7_1206_5%
ISUMP_IA
CORE_SNUB
12
PC662
680P_0603_50V7K
@EMC@
2
<49>
ISUMN_IA
+VCC_CORE
<49>
3
2
VCC_GT
TDC 18A
Peak Current 31A
OCP current 37A
Choke DCR 0.9 +-7%m ohm
PJP602
21
GPU_B+
PAD-OPEN 1x2m~D
CPU_B+
1
GPU_B+
12
12
PC673
PC672
@
10U_0805_25V6K
10U_0805_25V6K
B B
PWM1_GT<49>
12
PC688
10P_0402_50V8K
A A
PR680
5.11K_040 2_1%
1 2
0.22U_0603_16V7K
1 2
2.2_0603_5%
12
12
PC671
PR672
PC679
1000P_0402_50V7K
PU605
9
PGND2
8
PWM
7
BOOT
6
BOOT_R
5
VIN
CSD97374CQ4M_SON8_3P5X4P5
VSW
PGND1
VDD
SKIP#
PR671
0_0402_5%~D
<49>
4
3
2
1
12
FCCM_GT
GT_SW1
12
@EMC@
PR676
12
PC677
1U_0402_10V6K
4.7_1206_5%
+5V_RUN
GT_SNUB1
12
PC678
680P_0603_50V7K
@EMC@
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
PWR_VCORE_ISL95812 for QC
PWR_VCORE_ISL95812 for QC
PWR_VCORE_ISL95812 for QC
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet of
Date: Sheet of
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
PL604
0.15UH_MMD06CZER15MG_37A_20%
1
4
3
GT1P
PR674
3.65K_0603_1%
1 2
<49>
ISUMP_GT
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
+VCC_GT
2
ISUMN_GT
50 60Thursday, September 24, 2015
50 60Thursday, September 24, 2015
50 60Thursday, September 24, 2015
1
<49>
1.0
1.0
1.0
Page 51
A
Vinafix.com
PQ802
SI4835DDY-T1-GE3_SO8
8
13
D
S
PR801
100K_0402_1%
PR817
154K_0402_1%
7
5
BQ24770_REGN
12
12
+DC_IN_SS
1 1
CHARGER_SMBCLK
C
HARGER_SMBDAT
pull up 10K in HW side (R827 R 828)
2 2
ACAV_IN<32,52>
AC_DIS<31,43,52>
DMN65D8LW-7_SOT323-3
3 3
PQ809
12
1M_0402_1%
PR827
1K_0402_5%
PR829
@
154K_0402_1%
2
G
PR837
BQ24770_REGN
12
12
1
2
36
4
PR803
1 2
0_0402_5%
I_ADP<32>
I_BATT<32>
I_SYS<32,49>
H_PROCHOT#<12,32,49>
PBAT_PRES#<32,43,52>
DC_BLOCK_GC <52>
AC Det
Max:16.82V
Typ :16.54V
Min :16.26V
PR813
6.49K_0402_1%
PC815
0.1U_0402_25V6
CHARGER_SMBDAT<32>
CHARGER_SMBCLK<32>
PR816 0_0402_5%~D
1 2
PR819 0_0402_5%~D
1 2
PR820 0_0402_5%~D
1 2
12
12
PC823
1 2
100P_0402_50V8J
PR828
1 2
0_0402_5%~D
+DOCK_PWR_BAR
+DC_IN_SS
+PBATT
+PBATT
+PBATT+PBATT
+SDC_IN
PR812
34K_0402_1%
1 2
PC824
PR822
1 2
100P_0402_50V8J
30.1K_0402_1%
CSS_GC<52>
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
1 2
B
PR804
1 2
0_0402_5%~D
PD802
12
PD801
12
PD803
12
PR811
10_1206_5%
PC814
10U_0805_25V6K
12
PR836 0_0402_5%~D
1 2
PR835 0_0402_5%~D
1 2
PR815 0_0402_5%~D
1 2
PR818 100_0402_1%
1 2
/BATPRES<52>
@
12
PC802
0.1U_0603_25V7K
PQ801
DMP3056L-7 1P SOT23-3
PC808
12
1U_0603_25V6K
1 2
28
+DCIN
3
6
11
12
5
7
8
9
10
13
CMPIN
14
CMPOUT
15
16
29
PR802
0.01_1206_1%
4
3
2
G
13
D
2
G
S
CSSP_1
PR805
100_0402_1%
12
PR806
0_0402_5%~D
PC809
0.1U_0402_25V6
1 2
2
4
PU801
VCC
CMSRC
ACDET
SDA
SCL
ACOK
IADP
IDCHG
ISYS
/PROCHOT
CMPIN
CMPOUT
/BATPRES
CELL
PWPD
BQ24777RUYR_WQFN28_4x4
1
ACP
ACDRV
/BATDRV
1
2
13
D
S
CSSN_1
12
12
PC810
0.1U_0402_25V6
ACN
REGN
BTST
HIDRV
PHASE
LODRV
GND
NC
SRP
SRN
BAT
PQ803
DMP3056L-7 1P SOT23-3
PQ804
DMP3056L-7 1P SOT23-3
S
12
PR807
0_0402_5%~D
PR808
100K_0402_1%
1 2
BQ24770_REGN
24
PR814
2.2_0603_5%
1 2
25
26
27
23
22
PR821
21
1 2
10K_0402_1%
20
19
4.02K_0402_1%
18
1 2
17
1 2
PR826
10_0603_1%
1 2
PC828
1U_0603_25V6K
D
13
G
2
DMP3056L-7 1P SOT23-3
PR809
100K_0402_1%
PC821
0.047U_0603_16V7K
BQ24770_REGN
PR825
+PBATT
+PBATT
+PBATT+PBATT
EMC@
1UH +-20% 6.6A
PQ805
S
G
12
12
CHG_LGATE
C
PL802
@
PJP801
1 2
PAD-OPEN 4x4m
D
13
2
PR810
0_0402_5%~D
PC813
1 2
1U_0603_10V6K
CHG_UGATE
CHG_SW
12
12
DOCK_DCIN_IS+ <38>
DOCK_DCIN_IS- <38>
DK_CSS_GC <52>
1
7
G1
S1/D2
PQ808
G26S2
5
CHAGER_SRC+PWR_SRC_AC+SDC_IN
2
D1
3.3UH_PCMB063T-3R3MS_6.5A_20%
S2
S2
4
3
AON6992 2N DFN5X6D
1 2
CHG_SNUB
12
PC832
1000P_0603_50V7K
@EMC@
TYP MAX
H/S Rds(on) 7.4mohm , 8.8mohm
L/S Rds(on) 2.6mohm , 3.1mohm
Choke DCR 5.8mohm , 7.0mohm
12
12
PC817
0.1U_0402_25V6
@EMC@
12
PC816
@EMC@
PC819
PC818
22U_0805_25V6M
22U_0805_25V6M
2200P_0402_50V7K
+PWR_SRC
12
PC829
1 2
0.01_1206_1%
4
3
0.1U_0402_25V6
PL801
PR824
4.7_1206_5%
@EMC@
0.1U_0402_25V6
D
Near PL701
+PWR_SRC
12
12
PC803
PC804
10U_0805_25V6K
10U_0805_25V6K
+PWR_SRC+PWR_SRC
12
PC811
10U_0805_25V6K
12
PR823
PC822
22U_0805_25V6M
PC830
1 2
12
12
PC820
22U_0805_25V6M
1
2
0.1U_0402_25V6
@
PC831
1 2
+VCHGR
12
12
PC825
PC826
10U_0805_25V6K
0.1U_0603_25V7K
@EMC@
12
12
PC805
10U_0805_25V6K
12
PC812
22U_0805_25V6M
@EMC@
12
PC801
10U_0805_25V6K
12
PC806
PC807
10U_0805_25V6K
10U_0805_25V6K
12
PC827
10U_0805_25V6K
@
+DC_IN
12
PR830
649K_0402_1%
PR831
100K_0402_1%
1 2
ACAV_IN_NB<32,52>
PR833
1 2
0_0402_5%~D
PR832
3M_0402_5%
12
PR834
10K_0402_1%
12
100P_0402_50V8J
PC833
12
CMPIN
CMPOUT
PC834
100P_0402_50V8J
1 2
BATDRV# <52>
+3.3V_ALW
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Charger
Charger
Charger
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
D
51 60Thursday, September 24, 2015
51 60Thursday, September 24, 2015
51 60Thursday, September 24, 2015
1.0
1.0
1.0
Title
Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
Title
Size Document N umber R ev
Size Document N umber R ev
Size Document N umber R ev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 52
5
Vinafix.com
PD902
@
D D
C C
ACAVIN
P33ALW2
1
2
3
4
5
6
7
8
9
37
DK_CSS_GC<51>
PR935
100_0603_1%
1 2
PU901
DC_IN
SS_GC
ERC1
ACAVDK_SRC
GND
SDC_IN
DC_BLK_GC
ACAV_IN
P33ALW2
TP
CSS_GC<51>
PC907
0.047U_0603_25V7M
ERC3
12
B B
PR921
ACAV_IN<32,51,52>
PR920
SOFT_START_GC<43>
1 2
100K_0402_5%
DC_BLOCK_GC<51>
1 2
47_0805_5%~D
0.1U_0603_25V7K
PR928
100_0603_1%
1 2
PR918
1 2
0_0402_5%~D
PR932
1 2
0_0402_5%~D
+DC_IN
+3.3V_ALW2
ACAV_DOCK_SRC#<38>
+SDC_IN
+3.3V_ALW2
A A
PC906
PR923
1 2
0_0402_5%~D
5
12
PC908
0.1U_0603_25V7K
+DC_IN_SS
CD3301_DCIN
ACAVDK_SRC
ERC1
12
+VCHGR
+3.3V_ALW
DK_PWRBAR
DC_IN_SS
35
33
36
34
NC
DC_IN_SS
CHARGERVR_DCIN
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
ERC2
12
PC901
@
0.1U_0402_25V6
PDS5100H-13_POWERDI5-3
1
PQ903
SI4835DDY-T1-GE3_SO8
1
2
3 6
BATDRV#<51>
32
DK_PWRBAR
4
PR913
1 2
0_0402_5%~D
AC_DIS<31,43,51>
PR924
100_0603_1%
1 2 PR919
PR933
100_0603_1%
1 2
30
28
31
29
NC
GND
PBatt+
27
P50ALW
26
PBATT_OFF
DK_AC_OFF_EN
ACAV_IN_NB
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
SL_BAT_PRES#
NBDK_DCINSS
EN_DK_PWRBAR17P33ALW
18
P33ALW
EN_DK_PWRBAR
25
24
23
GND
22
21
20
19
CD3301BRHHR_QFN36_6X6~D
PR931
1 2
0_0402_5%~D
PR939
100_0603_1%
1 2
BLK_MOSFET_GC
BLKNG_MOSFET_GC
SS_DCBLK_GC
16
15
STSTART_DCBLOCK_GC
3301_PWRSRC
+PBATT
3
2
8
7
5
100K_0402_5%
PR916
1 2
10K_0402_5%
+DOCK_PWR_BAR
+PBATT
PR937
0_0402_5%~D
1 2
P50ALW
PR930 0_0402_5%~D
1 2
CD_PBATT_OFF
DK_AC_OFF
DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#
+3.3V_ALW
PR934
1 2
1M_0402_5%
4
DMG2301U-7 1P SOT23-3
12
PR915
13
PQ906
D
2
G
S
3301_ACAV_IN_NB
PR926 0_0402_5%~D
1 2
@
0_0402_5%
1 2
+PWR_SRC_AC
4
PQ909
1
3
13
2
2
DMN65D8LW-7_SOT323-3
+5V_ALW
SLICE_BAT_ON <31>
PR922
1 2
1 2
PR938 0_0402_5%~D
PR927
+DOCK_PWR_BAR
PD901
2
1
3
BAT54CW_SOT323-3
0_0402_5%~D
PR929
1 2
1M_0402_5%
SLICE_BAT_PRES# <31,38,43>
+NBDOCK_DC_IN_SS
PR901
1 2
0_0402_5%~D
PDS5100H-13_POWERDI5-3
DMN65D8LDW-7_SOT363-6
PQ911B
DMN65D8LDW-7_SOT363-6
4
DOCK_DET#<31,38,52>
DOCK_AC_OFF <38>
12
PR925
10K_0402_5%
ACAV_IN_NB <32,51>
DOCK_AC_OFF_EC <31>
EN_DOCK_PWR_BAR <31>
5
1 2
PQ911A
3
0_0402_5%~D
1
PD903
2
3
S TR AO4423L 1P SO8
SDMK0340L-7-F_SOD323-2~D
61
100K_0402_5%
2
PR917
100K_0402_5%
3
+PWR_SRC_AC
PC902
1 2
0.47U_0805_25V6K
36
241
5
123
36
241
PQ901
PR936
12
12
+3.3V_ALW2
1 2
100K_0402_5%
3
PQ904
S TR AO4423L 1P SO8
578
PR908
330K_0402_5%
PQ905
S TR AON7401 1P DFN
4
1500P_0402_50V7K
578
PD904
2
2
PR911
1 2
12
@
PC904
12
13
1
3
PR906
0_0402_5%~D
12
PQ908
PQ910
DMP3099L-7_SOT23-3
Purpose: Trigger PROCHOT# when
a
tive battery is removed from
c
system.
Allows EC to re-establish
system performance for battery
next in line.
STSTART_DCBLOCK_GC
PR910
100K_0402_5%
1 2
12
PR912
10K_0402_5%
13
D
2
G
S
Vth=0.5-1.5V
DMN65D8LW-7_SOT323-3
PD905
1
BAT54CW_SOT323-3
3
2
DIS_BAT_PROCHOT#<31>
+DC_IN_SS
+NBDOCK_DC_IN_SS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_ALW
12
PR905
100K_0402_5%
TC7SH08FU_SSOP5~D
+3.3V_ALW2
PU903
4
O
PBAT_PRES#<32,43,51>
PC905
0.1U_0402_10V7K
5
1
P
B
2
A
G
3
2
1
+3.3V_ALW
12
PR903
100K_0402_5%
PQ902B
5
61
DMN65D8LDW-7_SOT363-6
+3.3V_ALW2
DOCK_DET# <31,38,52>
12
PR902
100K_0402_5%
PR904
@
0_0402_5%
1 2
3
4
DMN65D8LDW-7_SOT363-6
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
/BATPRES <51>
1 2
12
0.1U_0402_10V7K
PR907
0_0402_5%~D
ACAV_IN#
PC903
1 2
+3.3V_ALW
5
1
P
B
O
2
A
G
PU902
3
TC7SH08FU_SSOP5~D
1 2
61
DMN65D8LDW-7_SOT363-6
4
PR909
100K_0402_5%
PQ907A
2
+3.3V_ALW
PQ902A
2
+3.3V_ALW2
12
PR914
100K_0402_5%
ACAV_IN#
3
PQ907B
ACAV_IN<32,51,52>
5
4
DMN65D8LDW-7_SOT363-6
DELL CONFIDENTI AL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: She et of
Date: She et of
2
Date: She et of
Selector
Selector
Selector
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
1
52 60Thursday, September 24, 2015
52 60Thursday, September 24, 2015
52 60Thursday, September 24, 2015
1.0
1.0
1.0
Page 53
A
Vinafix.com
B
C
D
E
VCC_CORE Place on CPU
Back Side.
22U_0603 * 7 pcs +1U_0201*35 pcs
Primary Side.
22U_0603 * 13 pcs+330u_D2*1 pcs
1 1
+VCC_CORE
1
1
1
1
PC1078
PC1076
2
2
2 2
12
12
2
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1081
2
2
@
22U_0603_6.3V6M
12
12
PC1083
PC1030
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1099
PC1095
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1077
PC1079
PC1001
2
2
2
22U_0603_6.3V6M
1
PC1080
PC1082
2
@
22U_0603_6.3V6M
12
PC1032
PC1031
1U_0201_6.3V6M
12
PC1094
PC1096
1U_0201_6.3V6M
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1067
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1033
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1090
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1002
2
@
22U_0603_6.3V6M
1
PC1072
2
22U_0603_6.3V6M
12
PC1034
1U_0201_6.3V6M
12
PC1093
1U_0201_6.3V6M
1
PC1004
PC1003
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1074
PC1069
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1036
PC1035
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1097
PC1091
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1005
2
@
22U_0603_6.3V6M
1
PC1070
2
22U_0603_6.3V6M
12
PC1037
1U_0201_6.3V6M
12
PC1092
1U_0201_6.3V6M
1
1
PC1007
PC1006
22U_0603_6.3V6M
PC1061
22U_0603_6.3V6M
PC1038
1U_0201_6.3V6M
PC1098
1U_0201_6.3V6M
PC1008
2
2
@
1
2
12
12
2
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1071
PC1066
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1084
PC1039
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1051
PC1050
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1009
PC1010
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1068
PC1073
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1086
PC1085
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1053
PC1052
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1011
22U_0603_6.3V6M
PC1075
22U_0603_6.3V6M
PC1088
1U_0201_6.3V6M
PC1054
1U_0201_6.3V6M
PC1013
PC1012
2
2
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1065
PC1064
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1089
PC1087
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
12
PC1126
PC1164
1U_0201_6.3V6M
PC1125
1U_0201_6.3V6M
1U_0201_6.3V6M
+VCC_GT
VCC_GT Place on CPU
Back Side.
22U_0603 * 11 pcs +1U_0201*12 pcs
Primary Side.
22U_0603 * 7 pcs +330u_D2*2 pcs
1
1
1
PC1014
2
2
@
22U_0603_6.3V6M
1
1
PC1133
2
2
22U_0603_6.3V6M
12
12
PC1040
1U_0201_6.3V6M
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
1
1
PC1128
+
+
2
2
1
1
PC1015
22U_0603_6.3V6M
PC1137
22U_0603_6.3V6M
PC1041
1U_0201_6.3V6M
PC1063
PC1017
PC1016
2
2
2
@
1
PC1129
2
12
PC1042
12
PC1181
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1132
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1043
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1180
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1018
22U_0603_6.3V6M
PC1136
22U_0603_6.3V6M
PC1044
1U_0201_6.3V6M
PC1177
@
22U_0603_6.3V6M
PC1020
PC1019
2
2
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1134
PC1135
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1045
PC1046
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
PC1176
PC1179
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1
PC1021
2
2
@
@
22U_0603_6.3V6M
1
1
PC1138
2
2
22U_0603_6.3V6M
12
12
PC1047
1U_0201_6.3V6M
12
12
PC1178
@
22U_0603_6.3V6M
1
PC1022
PC1023
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1027
PC1028
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
PC1048
PC1049
1U_0201_6.3V6M
1U_0201_6.3V6M
PC1175
@
22U_0603_6.3V6M
1
1
PC1024
22U_0603_6.3V6M
PC1130
22U_0603_6.3V6M
PC1055
1U_0201_6.3V6M
PC1026
PC1025
2
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1029
PC1131
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
PC1056
1U_0201_6.3V6M
330U_D2_2.5VM_R9M
330U_D2_2.5VM_R9M
3 3
4 4
@
1
1
PC1062
PC1127
+
+
2
2
12
12
PC1170
@
22U_0603_6.3V6M
12
12
PC1171
@
22U_0603_6.3V6M
12
PC1173
PC1172
@
22U_0603_6.3V6M
PC1174
@
@
22U_0603_6.3V6M
22U_0603_6.3V6M
VCC_SA Place on CPU
Back Side.
22U_0603 * 4 pcs + 1U_0201*7 pcs
Primary Side.
22U_0603 * 8 pcs
+VCC_SA
1
1
PC1057
2
2
22U_0603_6.3V6M
12
12
PC1153
1U_0201_6.3V6M
1
1
PC1058
2
22U_0603_6.3V6M
12
PC1147
1U_0201_6.3V6M
1
1
1
PC1060
PC1059
22U_0603_6.3V6M
PC1148
1U_0201_6.3V6M
PC1139
2
22U_0603_6.3V6M
12
PC1149
1U_0201_6.3V6M
PC1140
2
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
PC1151
PC1150
1U_0201_6.3V6M
1U_0201_6.3V6M
1
1
PC1142
PC1141
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
PC1152
1U_0201_6.3V6M
1
1
PC1143
2
22U_0603_6.3V6M
1
PC1145
PC1144
22U_0603_6.3V6M
PC1146
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
53 60Thursday, September 24, 2015
53 60Thursday, September 24, 2015
53 60Thursday, September 24, 2015
E
1.0
1.0
1.0
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 54
A
Vinafix.com
1 1
B
C
D
+3.3V_ALW
+5V_ALW
PAD-OPEN1x1m
12
2 2
PU1500
7
POK
PR1500
SIO_SLP_S4#<1 1,17,32,45>
3 3
1 2
47K_0402_5%
47K_0402_5%
12
PR1502
12
PC1504
.1U_0402_16V7K
8
EN
@EMC@
PC1500
1U_0402_6.3V6K
6
5
VIN
4
VOUT
VCNTL
3
VOUT
2
FB
9
VIN
GND
1
AP7175SP-13_SO-8EP-8
PJP1501
12
+2.5V_VIN
12
21.5K_0402_1%
PC1501
4.7U_0805_6.3V6K
12
PR1501
12
2.5VSP
PR1503
10.2K_0402_1%
12
PC1502
0.01UF_0402_25V7 K
1 2
PAD-OPEN1x1m
12
PC1503
22U_0805_6.3V6M
+2.5V_MEM
TDC 0.45 A
Peak Current 0.6 A
OCP Current 5.7 A fix by IC
PJP1500
+2.5V_MEM
4 4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+2.5V_MEM
+2.5V_MEM
+2.5V_MEM
LA-C451P
LA-C451P
LA-C451P
D
54 60Thursday, September 24, 2015
54 60Thursday, September 24, 2015
54 60Thursday, September 24, 2015
1.0
1.0
1.0
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 55
5
Vinafix.com
Timing Diagram for S5 to S0 mode
D D
5
C C
VCCST_PWRGD
12
H_CPUPWRGD
15
PCH_PLTRST#
17
0.675V_DDR_VTT_ON
12
+1.0V_PRIM_CORE
+1.8V_PRIM
5
CPU
VCCST_PWRGD
PROCPWRGD
PLTRST#
D
DR_VTT_CNTL
+PWR_SRC
TLV62130
+3.3V_ALW
TLV62130
VCCIO
VCCGT
VDDQ
VDDQC
VCCPLL_OC
VCCST
V
CCSTG
VCCPLL
VCCSA
SIO_SLP_SUS#
4
+1.0V_PRIM SYX198
+VCC_CORE
VCC
+1.0VS_VCCIO
+VCC_GT
+1.35V_MEM
+1.0V_VCCST
+VCC_SA
3
+1.0V_PRIM
TPS22961
6
3
+3.3V_ALW
+3.3V_SPI
+1.0V_MPHYGT
+3.3V_ALW_DSW
+3.3V_ALW_PCH
5
5
+1.8V_PRIM
+PWR_SRC
6
+RTC_CELL
+1.0V_PRIM_CORE
10
+1.0V_PRIM
TPS22961
SIO_SLP_S4#
5
17
4
+3.3V_ALW
11
+5
+LCDVDD
V_TSP
AP2821K
+3.3V_ALW
EM5209VF+3.3V_LAN
+5V_RUN
LP2301ALT1G
+3.3V_RUN
LP2301ALT1G+3.3V_CAM
EXT_PWR_GATE#
PCH_PLTRST#
PCH_DPWROK
ENVDD_PCH
SIO_SLP_LAN#
3.3V_TS_EN
3.3V_CAM_EN#
VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
EXT_PWR_GATE#
VCCDSW_3P3
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
VCCPGPPG
VCCATS
VCCRTC
VCCPRIM_CORE
PLTRST#
DSW_PWROK
EDP_VDDEN
S
LP_LAN#
GPP_B21
GPD7
PCH
PWRBTN#
RSMRST#
SLP_SUS#
SLP_S5#
SLP_S4#
SLP_S3#
SLP_LAN#
SLP_WLAN#/GPD9
SYS_PWROK
PCH_PWROK
VCCST_PWRGD
PROCPWRGD
SLP_A#
2
SIO_PWRBTN#
PCH_RSMRST#
SIO_SLP_SUS#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_WLAN#
RESET_OUT#
PCH_PWROK
VCCST_PWRGD
H_CPUPWRGD
16
15
1
11
14
12
1
8
7
5
9
0
Power Button
SIO_SLP_WLAN#
SIO 5048
11
11
RUN_ON
+5V_ALW
EM5209VF
+3
.3V_ALW
E
M5209VF
+5V_RUN
+3.3V_RUN
+5V_HDD
+3.3V_HDD
+3.3V_RUN
B B
@SIO_SLP_WLAN#
+3.3V_ALW
.3V_WLAN EM5209VF
+3
11
A A
AUX_EN_WOWL
+PWR_SRC
TLV62130
APL5930 +1.5V_RUN
+1.0VS_VCCIO
+VCC_CORE
13
BC BUS
+VCC_SA
+VCC_GT
11
10
+PWR_SRC
ISL95857
PCH_PWROK
14
ADAPTER
BATTERY
7
4
16
5
9
11
PCH_RSMRST#
PCH_DPWROK
RESET_OUT#
SIO_SLP_SUS#
IO_SLP_S4#
S
SIO_SLP_S5#
SIO_SLP_LAN#
SIO_SLP_S3#
SIO_SLP_A#
12
IMVP_VR_ON
2AC1BAT
ALWON
SIO_SLP_SUS#
@PCH_ALW_ON
11
A_ON
10
SUS_ON
EN_INVPWR
10
SUS_ON
0.675V_DDR_VTT_ON
5
+PWR_SRC
SYX198EC 5085
+PWR_SRC
SYX198
+3.3V_ALW
EM5209VF
+3.3V_ALW
+3.3V_ALW
EM5209VF
+PWR_SRC
AO6405
+PWR_SRC
RT8207MZ
+5V_ALW2
+5
V_ALW
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_MEM5209VF
+3.3V_SUS
+BL_PWR_SRC
+1.35V_MEM
+0.675V_DDR_VTT
12
1BAT
2AC
5
Pop option
+3.3V_SPI
18
VDDQ
VTT
DDR
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Compal Electronics, Inc.
Title
Title
Title
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Power Sequence
Power Sequence
Power Sequence
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
55 60Thursday, September 24, 2015
55 60Thursday, September 24, 2015
55 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 56
5
Vinafix.com
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Request
Request
Item
Item Issue Description
ItemItem
D D
Page# Title
Page#Page#
1
47
Title
TitleTitle
VCCIOP
PRIM_COREP
Date
DateDate
1/27 Compal For +1.0VS_VCCIO, +1.0V_PRIM_CORE IC 2nd source Add PR403, PR406, PR427, PR428
RequestRequest
Owner
Owner
OwnerOwner
4
Issue DescriptionDate
Issue DescriptionIssue Description
3
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Rev.Page#
Rev.Rev.
+VCC_CORE
2
3
4
C C
5
6
B B
7
49
49
44
45
49
45
+VCC_SA
+VCC_GT
+VCC_CORE
+VCC_SA
+VCC_GT
+5V_ALW
+3.3V_ALW
+1.35V_MEN
+2.5V_MEM
GPU_VRAM
+VCC_CORE
+VCC_SA
+VCC_GT
+1.2V_MEN
+2.5V_MEM
GPU_VRAM
1/27 Compal Fine tune IMON
1/27 Compal Fine tune VR current loop
For 3V5V PgoodCompal1/27
3/3
4/10 Compal For DDR change to DDR4 Add +2.5V_MEM, GPU_VRAM power rail circuit
Compal
Compal3/27
For DDR change to DDR3L
Fine tune VR control loop
change PR613 to 86.6k
change PR651 to 124k
change PR629 to 88.7k
change PR638 to 374
change PC624 to 0.033uF
change PC642 to 0.1uF
depop PC646
Remove PU101, PR101, PC101
Add PR119, PR120
Remove +2.5V_MEM, GPU_VRAM power rail circuit
change power setting from +1.2 to +1.35
change PR640 to 340
change PC642 to 0.033uF
change PC646 to 0.047uF
change PR657 to 4.42k
change PR628 to 4.42k
change power setting from +1.35 to +1.2
+2.5V_MEM
8
9
10
A A
1
54 change PR1500, PR1502, PR509, PR511 to 47k
51 Charger 4/20 Compal fine tune monitor Psys change PR822 to 40.2k
1
+1.8VALWP
+1.5VSP
+1VS_VCCIOP
+1.0V_PRIM_COREP
CPU MLCC cap
cost down
5
Disable LDO pull up when floating enable pinCompal4/20
CPU MLCC cap
cost down
4
change to SY80657
depop
+VCC_CORE, 22U*15,330U*1
+VCC_GT, 22U*8
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR P.I.R (1/1)
PWR P.I.R (1/1)
PWR P.I.R (1/1)
LA-C631P, C641P
LA-C631P, C641P
LA-C631P, C641P
56 60Thursday, September 24, 2015
56 60Thursday, September 24, 2015
56 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Page 57
5
Vinafix.com
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Title
TitlePage#
TitleTitle
Date Issue Description
DateDate
OwnerDate
OwnerOwner
Material 2015/01/051COMPAL
MEC5085
2
Page#
Page#Page#
8/22/27/
30/40/42
32
Item
ItemItem
D D
4
Issue DescriptionItem
Issue DescriptionIssue Description
Material EOL
For Next Gen EC debug
3
QA2, QA3, QC2, QE2, QL1, QL2, QN1, QV3, QZ3 and QZ7 from SB00000DH00
change to SB00000ZU00
Add Re305 and RE306 reserve UART0_TXD path2015/01/05 DELL
2
Solution Description
Solution DescriptionOwner
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.Rev.
0.2(X01)
0.2(X01)
3
4
5
6
7
8
C C
9
10
11
27 Transformer 2015/01/12 COMPAL ME height limit TL1 changed from SP050006F00 to SP050006Y00
MEC5085 2015/01/12 For Power down sequence. add UE3, UE4, RE304,RE308.COMPAL32
CPU (6/14) 2015/01/12 COMPAL11 For PLTRST glitch issue. 1.UC7.5 change from +3.3V_RUN to +3.3V_ALW_PCH
DDR4 2015/01/1221 COMPAL DIMM select error cause can't recognize
2015/01/12 system will shut down when insert FP. change USH conn pin define, and add RZ85, RZ86, DZ7, reserve RZ84, RZ87COMPALUSH & TPM33
2015/01/12 change BID to X01. change RE79 to 130K ohm.COMPALMEC508532
2015/01/12 add UART port 2 for USB debug.
2015/01/12 Follow 546765_546765_2014WW52_Skylake_
COMPALCPU (4/14)9
MOW_Rev_1_0
2015/01/12 support DCI. add RC327 and reserve RC326, QC3CPU (3/14)8 INTEL
DIMM2.
add net name "LPSS_UART2_TXD", "LPSS_UART2_RXD", and add RC330, RC331
and JUART1 CON
reserve CC222 and RC313.CPU (8/14) INTEL13
2.Pop RC325,depop RC60.
Stuff RD70, RD72 and no stuff RD69, RD73.
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
11 Crystal 2015/01/12 TXC Material EOS YC2 changed from SJ10000LD00 to SJ10000LV0012 0.2(X01)
HDMI CONN 2015/01/202213 COMPAL For HDMI EMI solution. add RV647 ~ RV658 path and depop commom-chock 0.2(X01)
14 26 LCD 2015/01/20 COMPAL BOM changed UV24 from SA00006EE00 to SA00006Y800 0.2(X01)
15 32 EC 2015/01/20 COMPAL BOM changed QE3/QE4/QE5/QE6/QE7 from SB000008P00 to SB000013V00 0.2(X01)
B B
16 32 EC 2015/01/20 COMPAL BOM changed UD1 and UE4 from SA00005U600 to SA00007UR00 0.2(X01)
17 33 TPM 2015/01/20 COMPAL TPM issue
18 9 CPU (4/14) 2015/01/20 COMPAL Non-Dock config Reserve RH359 pull-down for non-dock config
19 32 EC 2015/01/20 COMPAL Power sequence fail
20 18 CPU (13/14) 2015/02/04 COMPAL KB boss and stand off interference
21 10 CPU (5/14) 2015/02/04 INTEL MOW update
22 12 CPU (7/14) 2015/02/04 MOW update
23 8 CPU (3/14) 2015/02/04 MOW update
A A
20,21 DDR4 Follow 546765_546765_2015WW02_Skylake
5
INTEL
INTEL
INTEL
_MOW_Rev_1_0
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1. Reserve10K ohm (RZ90) and Pull-up to +3.3V_RUN on UZ12 pin 29.
2. change VSB power (UZ12.1) to +3.3V_ALW_PCH.
3. added QZ8 and RZ109 between pin3/pin20 to control LPM
4. reserve RZ110 and de-pop.
5. Reserve +3.3V_RUN on UZ12 pin 8 (add RZ88, RZ89)
6. change RZ109 pin 1to +3.3V_M_TPM add QZ9, RZ111
Depop RE280 and RE304 then pop RE292 and UE3
Removed RC304/RC305/RC306/CC205/CC207/CC265
Add RC337 connect to GND and RC338 1K pull down
Add RC328 XDP_JTAGX need connect to CPU_XDP_TCLK for DCI
Changed RC317 from 4.7k to 150k and reserved SIO_SLP_SUS# on RC340
No stuff CD6, CD35.2015/02/0424
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
0.2(X01)
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EE P.I.R (1/3)
EE P.I.R (1/3)
EE P.I.R (1/3)
LA-C621P
LA-C621P
LA-C621P
57 60Thursday, September 24, 2015
57 60Thursday, September 24, 2015
57 60Thursday, September 24, 2015
1
0.2(X01)
0.2(X01)
0.3(X02)
0.3(X02)
0.3(X02)
0.3(X02)
0.3(X02)
1.0
1.0
1.0
Page 58
5
Vinafix.com
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Title
Item
ItemItem
D D
25
Page#
Page#Page#
33 USH & TPM 2015/03/02 Nuvoton
TitlePage#
TitleTitle
Date Issue Description
DateDate
OwnerDate
OwnerOwner
4
Issue DescriptionItem
1.for allow further reducing power in TPM 2.0
F/W,when system is in S3/4/5 and main power
is off.
2.for support modern standby.
Issue DescriptionIssue Description
3
2
Solution Description
Solution DescriptionOwner
Solution DescriptionSolution Description
1.reserve RZ90
2.reserve RZ112.
3.Depop RZ88 and pop RZ89, pop RZ112
1
Rev.
Rev.
Rev.Rev.
0.3(X02)
26 11,27 CPU (6/14) COMPAL Solve auto power on issue. De-pop RL70 and pop RC323. 0.3(X02)2015/03/02
27 32 COMPAL Solve power down sequence fail. De-pop RE308. 0.3(X02)MEC5085 2015/03/02
28 32 change BID to X02. change RE79 to 33K ohm.MEC5085 COMPAL 0.3(X02)2015/03/02
29 26
eDP CONN
& TS
DELL Customer request. add 6 pin IR Conn. 0.3(X02)2015/03/02
30 40 COMPAL ME design change. change H6 from 4mm to 3mm. 0.3(X02)PAD, LED 2015/03/02
31 11/32 COMPALCrystal 2015/03/02 X'tal EA measurement. change CC23 and CC26 from 18pf to 12pf 0.3(X02)
32 8 Intel MOW_2015WW06:Pull-up Resistors on
C C
CPU (3/14) Intel de-pop RC30, RC316 0.3(X02)2015/03/02
SPI_IO2 and SPI_IO3 Requirement Update
33 8 CPU (3/14) COMPAL Follow CRB setting RC23 changed from 8.2K to 2.2K 0.3(X02)2015/03/02
34 33 TPM COMPAL2015/03/02 support modern standby Add RZ112 connect to SIO_SLP_S0# with TPM 0.3(X02)
35 32 EC 2015/03/02 COMPAL Option DDR3L and DDR4 Add GPP_D9(DIMM_TYPE), RC342 and RC341 that selected DDR3L and DDR4. 0.3(X02)
36 32 EC 2015/03/02 COMPAL Follow Intel power sequence Pop RE292 and depop RE280 0.3(X02)
37 8 CPU (3/14) 2015/03/02 COMPAL RF request Pop CC3/CC4/CC5/CC6 from 22p to 27p 0.3(X02)
38 33 TPM 2015/03/02 Nunoton TPM detected sequence Add RZ113 100 ohm 0.3(X02)
39 11 CPU (6/14) 2015/03/02 COMPAL Deep S3 leakage VRALERT# changed power rail from +3.3V_ALW to +3.3V_ALW_PCH 0.3(X02)
40 0.3(X02)27 LAN COMPAL IEEE EA measurement.2015/03/02 change LL2 ~ LL9 to 2.2 ohm Res (RL71~RL78).
B B
41 0.4(X03)9 CPU (4/14) 2015/04/02 COMPAL IR Function
42 31/33 EC/USH 0.4(X03)2015/04/02 Broadcom Vender recommend
1.add IR_CAM_DET# on JIR1 pin 1.
2.add IR_CAM_DET# on UC1.AW7, and PU 100K(RC346) to +3.3V_RUN
1.Reserve RZ114/RZ115 on JUSH1 pin 21
2.add USH_RST# on UE1.A62
43 12 0.4(X03)2015/04/02 COMPAL SIO_EXT_SMI# to wake up system when non-deep S3 Add RC236 SIO_EXT_SMI# change power to +3.3V_ALWS_PCHCPU (7/14)
44 29 2015/04/02 COMPAL 0.4(X03)NGFF Card ME request Change JSIM1 conn to T-SOL_5-991503004000-6
45 32 MEC5085 COMPAL change BID to X03 change RE79 to 1K ohm. 0.4(X03)2015/04/02
46 9 CPU (4/14) 2015/04/02 COMPAL for DIMM type option Pop RC342 and de-pop RC341 0.4(X03)
47 40 PAD, LED 2015/04/02 COMPAL ME request Add H9 and H10 for different SIM CON 0.4(X03)
48 29 NGFF 2015/04/02 COMPAL SIM detect Add RI31 connecting with JSIM1.9 and NGFF2.58 0.4(X03)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EE P.I.R (2/3)
EE P.I.R (2/3)
EE P.I.R (2/3)
LA-C621P
LA-C621P
LA-C621P
58 60Thursday, September 24, 2015
58 60Thursday, September 24, 2015
58 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 59
5
Vinafix.com
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Title
Item
ItemItem
D D
Page#
Page#Page#
TitlePage#
TitleTitle
Date Issue Description
DateDate
OwnerDate
OwnerOwner
4
Issue DescriptionItem
Issue DescriptionIssue Description
3
2
Solution Description
Solution DescriptionOwner
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.Rev.
39 KB 2015/04/20 ALPS For new U1 TP module Add RZ116 and RZ117 PU on I2C._1_SDA_R/I2C_1_SCL_R49 0.4(X03)
50 31 5048 2015/04/20 COMPAL PC common EC code issue need reserved PU Add AR_SMBUS_ALERT# 10K(RE309) PU on ECE5048 pin58 GPIOF2 0.4(X03)
R274,RA35,RA36,RA37,RC143,RC169,RC170,RC171,RC172,RC173,RC211,RC214,
RC228,RC229,RC230,RC231,RC235,RC290,RC295,RC296,RC299,RC300,RC301,RC302,
Changed 0 ohm short-padCOMPAL2015/04/2051 31 All
RC303,RC307,RC308,RC309,RC310,RC325,RC327,RC328,RC337,RC37,RD29,RD60,
RD65,RD66,RD67,RD68,RD70,RD72,RD74,RE290,RE305,RI15,RI16,RI17
RI18,RI19,RI20,RI21,RI22,RI23,RI24,RI25,RI26,RI27,RI28,RI29,RI30,RI31
RL34,RL7,RN99,RR17,RR18,RR21,RR22,RR23,RZ22,RZ23,RZ56,RZ70,RZ85,
RZ86
0.4(X03)
52 8 CPU(3/14) 2015/04/20 COMPAL SMBUS LAN backdrive Add RC347 and RC348 PU to +3.3V_ALW_PCH 0.4(X03)
53 11 CPU(6/14) 2015/05/20 COMPAL Crystal EA -R issue Changed YC2-CL 9pf from 12pf and cc23/cc26 changed to 6pf from 12pf 0.5(X04)
54 35 M2280 2015/05/20 COMPAL Insert NVME SATA LED no function JNGFF3.10 connected to PCH_SATA_LED# 0.5(X04)
C C
55 36 USB 2015/05/20 COMPAL Insert Storage Bus shutdown Add CI32 150U prevent charger current over spec 0.5(X04)
56 39 TP 2015/05/20 COMPAL TP function sometimes lag or crazy CZ30 and CZ31 change from 10p to 330p improve signal quality 0.5(X04)
57 31 5048 2015/05/20 COMPAL For Type-C function
1. Add 5048 GPIO(PROCHOT_GATE) and reserve RE311 pull high
2. Add 5048(PD_ACE_DET#) for AR config and pull high on RE310
0.5(X04)
58 32 MEC5085 2015/05/20 COMPAL change BID to X04 change RE79 to 8.2K ohm. 0.5(X04)
59 18 2015/05/27 COMPAL 5.76GHz noise observed on thie Wi-Fi antenna
60 36/37 2015/05/27 COMPAL ESD request
1.Add RC349 and CC303 on VCCHDA
2.Add RC350 and CC304 on VCCAPLL_1P0
1.Add CI33 0.1U cap to GND on USB_OC0#
2.Add CI34 0.1U cap to GND on USB_OC1#
3.Add CI35 0.1U cap to GND on USB_OC2#
0.5(X04)CPU(13/14)
0.5(X04)USB3.0
2015/06/272661 0.6(X05)Changed DV1, DV2 and DV3 from SCS00003800 to SCS00006400Material shortageCOMPALeDP
B B
33 2015/06/2762 COMPAL 0.6(X05)
TPM Change TPM FW to 1.2 version Changed UZ12 from SA000082D00 to SA00008EL20
32 2015/06/2763 KBC COMPAL WinPE Global reset shutdown issue Add QE11 prevent +1.0V_VCCST timing down before +1.0V_VCCIO 0.6(X05)
3264 KBC 2015/06/27 COMPAL Follow intel power sequence Add UE5 AND Gate control Run_on timing and depop RE292 0.6(X05)
65 11 CPU(6/14) 2015/06/27 COMPAL Cystal EA Changed CC21 and CC22 from 22p to 15p 0.6(X05)
66 33 USH 2015/06/27 COMPAL TPM1.2 deep S3 resume issue UZ12.1 changed power rail from +3.3V_ALW_PCH to +3.3V_ALW 0.6(X05)
1.Add UV29,CV617,CV618,CV619,RV659,RV650,RV661
2.Depop UV28,PJP33,CV615,CV616
0.6(X05)For DP hub display flicker issue2467 COMPAL2015/07/20DP HUB
3668 COMPAL For Sourcer request CI32 change from SGA00002N80 to SGA00004E10 0.6(X05)HW 2015/07/20
69 32 MEC5085 2015/07/20 COMPAL change BID to X05 change RE79 to 4.3K ohm. 0.6(X05)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EE P.I.R (3/3)
EE P.I.R (3/3)
EE P.I.R (3/3)
LA-C621P
LA-C621P
LA-C621P
59 60Thursday, September 24, 2015
59 60Thursday, September 24, 2015
59 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Page 60
5
Vinafix.com
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Title
Item
ItemItem
D D
Page#
Page#Page#
TitlePage#
TitleTitle
Date Issue Description
DateDate
OwnerDate
OwnerOwner
4
Issue DescriptionItem
Issue DescriptionIssue Description
3
2
Solution Description
Solution DescriptionOwner
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.Rev.
41 CPU(12/14) 2015/07/31 COMPAL Follow Intel DG1.5 Add load switch (UZ26) control to +VCCPLL_OC power rail70 0.6(X05)
18 CPU(13/14) 2015/07/31 COMPAL 5.76GHz noise observed on thie Wi-Fi antenna71 Change RC349 and RC350 to LC1 and LC2 0.6(X05)
2015/08/12USB3672 Depop CI32 and then pop CI14Low battery shut down issueCOMPAL 0.6(X05)
73 32 5085 2015/08/12 COMPAL DC mode CPU trubo issue Reserved RE313 pull down path on I_SYS 0.6(X05)
74 34 PCIE 2015/08/12 COMPAL M.2 SATA iEMT Pop RN50 change to level2 0.6(X05)
75 11 CPU(6/14) 2015/08/12 COMPAL RTC delay YC2 changed to 10ppm(SJ10000Q800) and CC23/CC26 changed to 5pf 0.6(X05)
76 24 HUB 2015/09/12 COMPAL Display no function RV662 chnanged to 0 ohm from 1 ohm. 1.0(A00)
C C
78 12 CPU(7/14) 2015/09/12 COMPAL Service mode switch Depop RC222 and SW1 and then short RC221 1.0(A00)
COMPAL Changed 0 ohm short-pad RC41,RC289,RZ89,RZ112,RZ64,RC221,RZ118,RV66277 ALL All 2015/09/12 1.0(A00)
79 32 5085 2015/09/12 COMPAL syn-up with power material issue 1.Change SC600001600 to SCA00000T00(DI2,DI3,DI5,DV4)
2.Change SB000013V00 to SB00000Z500(QE3,QE4,QE5,QE6,QE7)
1.0(A00)
80 32 MEC5085 2015/09/12 COMPAL change BID to A00 change RE79 to 1K ohm. 1.0(A00)
81 22 HDMI 2015/09/18 COMPAL DFX request Delete LV3/LV6/LV9/LV12 co-lay footprint 1.0(A00)
82 12/14 XDP 2015/09/20 COMPAL Follow PDG2.0 Changed RC82 and RC135 to 100 from 51. 1.0(A00)
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EE P.I.R (4/4)
EE P.I.R (4/4)
EE P.I.R (4/4)
LA-C621P
LA-C621P
LA-C621P
60 60Thursday, September 24, 2015
60 60Thursday, September 24, 2015
60 60Thursday, September 24, 2015
1
1.0
1.0
1.0
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Loading...