Dell Latitude E6440 Schematics
A
B
C
D
E
COMPAL CONFIDENTIAL
MODEL NAME : VAL91
PCB NO : DAA0006L000
1 1
GPIO P/N: 2012.8.1 Rev 2.7
BOM P/N :
X76 of SPI:
X7650731L03
SA000039A30 (64M W25Q64FVSSIQ)
SA00003K820 (32M W25Q32FVSSIQ)
X7650731L04
SA00006N000 (32M MX25L3273EM2I-10G)
SA00006N100 (64M MX25L6473EM2I-10G)
SALADO 14 HSW DSC
HASWELL + LYNX POINT
2013-07-04
REV : 1.0 (A00)
2 2
X76 of VRAM:
X7650731L53 - SAMSUNG
SA00006EU1L (128M32 K4G41325FC-HC04)
CONN@ : Connector Component
SD034453180 (4.53K +-1% 0402)
@ : Nopop Component
SPI@ : For X76 SPI
X7650731L54 - HYNIX
SA00006O41L (128M32/2.5G H5GC4H24MFR-T2C)
VRAM@ : For X76 VRAM
SD000000680 (8.45K +-1% 0402)
14DSC
EMC@: EMI/RF/ESD ask to add V
CXDP@ : CPU XDP
3 3
PXDP@ : PCH XDP
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-9932P
LA-9932P
LA-9932P
1 71Thursday, July 04, 2013
1 71Thursday, July 04, 2013
1 71Thursday, July 04, 2013
E
1.0
1.0
1.0
MB PCB
Part Number Description
PCB 0YH LA-9932P REV0 M/B DSC 6
DAA0006L000
A
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
A
B
C
D
E
Block Diagram
AMD
VRAM GDD5 X4
P54-55
1 1
LVDS CONN
HDMI CONN
P26
P28
Dual-Channel LVDS
HDMI level shifter
PS8401A
DOCKING
P44
DAI
USB2.0 [3,6]
SATA2
DOCK LAN
(PERN1/USBRN3)
2 2
PCIE7
EXPRESS
Card
CRT CONN
on IO board
PCIE6
1/2 Mini Card
Pink Pather
P39 P37
USB2.0[8]USB2.0[10]
SUN XT S3
P26
DPC
DPD
Dock VGA
VGA
1/2 Mini Card
WLAN/BT,WiGig
Video Switch
TS3V713ELRTGR
SD4.0/MMC
PCIE3
P37
USB2.0[4]
PEG Gen3 x8Lane
P49-53
eDP to LVDS
RTD2136R
DPB
P25
P36
Full Mini Card
WWAN/mSATA
P27
iVGA
Card Reader
OZ777FJ2LN
PCIE
P38
USB2.0[5]
iEDP 2Lane
P36
SATA_TXN4/PETN1
PCIE2
Intel
HasWell
rPGA CPU
947 Pins
FDI
LANEX2
Intel
Lynx Point
BGA
695 Pins
SPI
S-ATA 0/1/2/3/4/5 6GB/s
W25Q64FV
64M 4K sector
P6-12
DMI
LANEX4
P15-23
Memory BUS (DDR3L)
1333/1600 MHz
USB
(PERN2/USBRN4)
HD Audio I/F
SATA1
P18
USB2.0[12]
USB2.0[0]
USB3.0[6]
SATA0
SATA3
DDR3L-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Camera
SLG55584AVTR USB
Power Share
P28
P40
Through LVDS Cable
USB3.0 Repeater
PS8713
P13-14
USB3.0[1]
USB2.0[0]
USB3.0[2]
USB2.0[1]
USB3.0[5]
USB2.0[2]
USB3.0[6]
USB2.0[9]
JUSB1
P40
JUSB2
P41
JUSB3
P42
JUSB4
DOCK LAN
To Docking side
IO/B
Intel Clarkville
I217LM
LAN SWITCH
PI3L720
P33
P33
3 3
TDA8034HNSmart Card
RFID
Fingerprint
CONN
CPU XDP Port
P7
SMSC SIO
PCH XDP Port
WiFi ON/OFF
DC/DC Interface
4 4
LED
PWM FAN
A
P15
on SNIFFER board
P48
P24
P46
MEC5048
P45
B
USH
BCM5882
BC BUS
USB2.0[7]FP_USB
USH Module
SMSC KBC
MEC5075
KB CONNTP CONN
P46
LPC BUS
33MHz
P47P47
W25Q32FV
PCIE4
P18
E-Module
P32
HDD
FFS
LNG3DM
P31
P31
32M 4K sector
Discrete TPM
AT97SC3204
P35
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
HDA Codec
ALC3226
P30
INT.Speaker
Combo Jack
DAI
To Docking side
Dig. MIC
Through LVDS Cable
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-9932P
LA-9932P
LA-9932P
RJ45
P34
P30
P30
1.0
1.0
2 71Thursday, July 04, 2013
2 71Thursday, July 04, 2013
E
2 71Thursday, July 04, 2013
1.0
5
4
3
2
1
USB 2.0
POWER STATES
Signal
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCH
PORT#
0
1
2
3
4
5
6
7
8
9
PM TABLE
C C
power
plane
State
+PWR_SRC
+PWR_SRC_S
+5V_ALW
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
+3.3V_SUS
+1.35V_MEM
+5V_RUN
+1.5V_RUN
+0.675V_DDR_VTT
+VCC_CORE
+1.05V_RUN
+GPU_CORE
+1.35V_MEM_GFX
+1.8V_RUN_GFX
+VGA_PCIE
+3.3V_RUN_GFX
+VDDCI
+3.3V_M +3.3V_M
+1.05V_M+1.05V_M+3.3V_RUN
(M-OFF)
10 Express card (JEXP1)
11
12
13
PCI EXPRESS DESTINATION
Lane 1 (SATA_TXN4/PETN1) WWAN (JMINI1)
Lane 2 (SATA_RXN5/PERN2)
ON
ON
ON
ON
OFF
OFF
OFFOFF
Lane 2 (PERN2/USBRN4)
Lane 3
Lane 4 E3 Module Bay (JSATA2)
Lane 5
S0
S3
B B
S5 S4/AC
S5 S4/AC don't exist
ON
ON
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
Lane 6
Lane 7
Lane 8
USB 3.0
PORT#
1
2
5
3 (PERN1/USBRN3)
6
None
10/100/1G LOM
WLAN (JMINI2)
None
Pink Pather (JMINI3)
Express card (JEXP1)
MMI
DESTINATION
Rear Side (JUSB1)
Right Side TOP (JUSB2)
Right Side bottom (JUSB3)
DOCKING (JDOCK1)
WLAN (JMINI2)
WWAN (JMINI1)
DOCKING (JDOCK1)
USH (JUSH1)
Pink Pather (JMINI3)
Left Side (JUSB4)
None
CAMERA (JCAM1)
LCD Touch
SATA by default
SATA DESTINATION
SATA 0
SATA 1
SATA 2
SATA 3
SATA 4 (SATA_TXN4/PETN1)
HDD (JSATA1)
ODD (JSATA2)
Dock (JDOCK1)
NA
WWAN (JMINI1)
SATA by default
DISPLAY Ports
On CPU
DDIB
A A
DDIC
DDID
Connetion
MB HDMI (JHDMI1)
Dock DP port 1
Dock DP port 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Configuration
Index and Configuration
Index and Configuration
LA-9932P
LA-9932P
LA-9932P
1
3 71Thursday, July 04, 2013
3 71Thursday, July 04, 2013
3 71Thursday, July 04, 2013
1.0
1.0
1.0
5
4
3
2
1
D D
BATTERY
EN_INVPWR
DGPU_PWR_EN#
+PWR_SRC
ADAPTER
FDC654P
Q21
ISL62883CHRTZ-T
(PU600)
+BL_PWR_SRC
+GPU_CORE
MODC_EN
RUN_ON
TPS22966
(U37)
CHARGER
BQ24717
C C
(PU700)
ALWON
TPS51225
(PU100)
+5V_ALW
+5V_RUN
+5V_HDD
+5V_MOD
Pop option
+5V_RUN
PCH_ALW_ON
(U146)
SYN470DBC
PU400
MCARD_MISC_PWREN
TPS22966
(U145)
+1.5V_RUN
MCARD_WWAN_PWREN
DGPU_PWR_EN#_Q
TPS22965
(UV60)
RUN_ON
IMVP_VR_ON
ISL95812
(PU500)
B B
SUS_ON
RT8207MZQW
(PU200)
0.75V_DDR_VTT_ON
+VCC_CORE +1.35V_MEM +0.675V_DDR_VTT
A_ON
TPS51212DSCR
(PU300)
+1.05V_M
DGPU_PWR_EN#
SY8036L
(PU602)
DGPU_PWR_EN#
G971
(PU603)
EN_LCDPWR
APL3512
(U148)
AUX_EN_WOWL
TPS22966
(U57)
+3.3V_ALW
SUS_ON
SIO_SLP_LAN#
A_ON
TPS22966
RUN_ON
TPS22966
(U36)
RUN_ON
DGPU_PWR_EN#
SI4164
SI4164
(Q63)
+VGA_PCIE
+1.8V_RUN_GFX
+LCDVDD
+3.3V_WLAN
+3.3V_LAN +3.3V_SUS
+3.3V_M
+3.3V_RUN
+3.3V_ALW
_PCH
+3.3V_PCIE
_FLASH
+3.3V_PCIE
_WWAN
+3.3V_RUN_GFX
(QV1)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-9932P
LA-9932P
LA-9932P
1
4 71Thursday, July 04, 2013
4 71Thursday, July 04, 2013
4 71Thursday, July 04, 2013
1.0
1.0
1.0
+1.35V_MEM_GFX
5
+1.05V_RUN
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
5
4
3
2
1
@
@
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_LAN
28
31
LOM
+3.3V_ALW
+LCD_VDD
+3.3V_ALW
100 ohm
100 ohm
2N7002
2N7002
SMBUS Address [ C8]
127
129
DOCKING
7
BATTERY
6
CONN
SMBUS Address
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
SMBUS Address [ 0x16]
202
200
202
200
4
6
XDP1
XDP2
SMBUS Address [ A0]
SMBUS Address [ A4]
SMBUS Address [ TBD]
SMBUS Address [ TBD]
DIMMA
DIMMB
53
51
53
51
10K
10K
13
14
+3.3V_RUN
G Sensor
SMBUS Address [ 0x3B]
eDP to LVDS CONVERTER
SMBUS Address T BD
SMBUS Address [ 0x9a]
B4
A3
B5
A4
MEM_SMBCLK
MEM_SMBDATA
LAN_SMBCLK
LAN_SMBDATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
R10
U11
D D
PCH
U8
R7
K6N11
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
USH_SMBCLK
A50
1E
B53
A49
B52
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
MEC 5075
2B
2B
2.2K
2.2K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
2.2K
2.2K
BAY_SMBDAT
B7
2D
BAY_SMBCLK
A7
2D
A A
GPU_SMBCLK
B49
2A
B48
2A
5
GPU_SMBDAT
2.2K
2.2K
2.2K
4
+3.3V_SUS
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
9
8
M9
L9
USH
SMBUS Address [ 0xa4]
7
8
Express card
Charger
SMBUS Address [ 0x12]
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SMBUS Address [ TBD]
29
E3 Module Bay
30
100
2
3
100
MBATT
8
GPU
9
SMBUS Address [ 0xd2]
SMBUS Address [ 0xXX]
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SMBus block diagram
SMBus block diagram
SMBus block diagram
LA-9932P
LA-9932P
LA-9932P
5 71Thursday, July 04, 2013
5 71Thursday, July 04, 2013
5 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
D D
4
PEG_COMP
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
3
+VCOMP_OUT
12
RC124.9_0402_1%
2
1
JCPU1A
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
C C
B B
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CSYNC<16>
FDI_INT<16>
D21
DMI_RXN_0
C21
DMI_RXN_1
B21
DMI_RXN_2
A21
DMI_RXN_3
D20
DMI_RXP_0
C20
DMI_RXP_1
B20
DMI_RXP_2
A20
DMI_RXP_3
D18
DMI_TXN_0
C17
DMI_TXN_1
B17
DMI_TXN_2
A17
DMI_TXN_3
D17
DMI_TXP_0
C18
DMI_TXP_1
B18
DMI_TXP_2
A18
DMI_TXP_3
H29
FDI_CSYNC
J29
DISP_INT
LOTES_AZIF0012-P002B_HASWELL
CONN@
Haswell rPGA EDS
FDIDMI
1 OF 9
PEG
PEG_RCOMP
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
E23
PEG_COMP
M29
PEG_CRX_GTX_N0
K28
PEG_CRX_GTX_N1
M31
PEG_CRX_GTX_N2
L30
PEG_CRX_GTX_N3
M33
PEG_CRX_GTX_N4
L32
PEG_CRX_GTX_N5
M35
PEG_CRX_GTX_N6
L34
PEG_CRX_GTX_N7
E29
D28
E31
D30
E35
D34
E33
E32
L29
PEG_CRX_GTX_P0
L28
PEG_CRX_GTX_P1
L31
PEG_CRX_GTX_P2
K30
PEG_CRX_GTX_P3
L33
PEG_CRX_GTX_P4
K32
PEG_CRX_GTX_P5
L35
PEG_CRX_GTX_P6
K34
PEG_CRX_GTX_P7
F29
E28
F31
E30
F35
E34
F33
D32
H35
PEG_CTX_GRX_C_N0
H34
PEG_CTX_GRX_C_N1
J33
PEG_CTX_GRX_C_N2
H32
PEG_CTX_GRX_C_N3
J31
PEG_CTX_GRX_C_N4
G30
PEG_CTX_GRX_C_N5
C33
PEG_CTX_GRX_C_N6
B32
PEG_CTX_GRX_C_N7
B31
A30
B29
A28
B27
A26
B25
A24
J35
PEG_CTX_GRX_C_P0
G34
PEG_CTX_GRX_C_P1
H33
PEG_CTX_GRX_C_P2
G32
PEG_CTX_GRX_C_P3
H31
PEG_CTX_GRX_C_P4
H30
PEG_CTX_GRX_C_P5
B33
PEG_CTX_GRX_C_P6
A32
PEG_CTX_GRX_C_P7
C31
B30
C29
B28
C27
B26
C25
B24
PEG_CRX_GTX_N[0..7] <49>
PEG_CRX_GTX_P[0..7] <49>
PEG_CTX_GRX_P[0..7]
PEG_CTX_GRX_N[0..7]
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_P[0..7] <49>
PEG_CTX_GRX_N[0..7] <49>
12
CC1 0.22U_0402_16V7K
12
CC2 0.22U_0402_16V7K
12
CC3 0.22U_0402_16V7K
12
CC4 0.22U_0402_16V7K
12
CC5 0.22U_0402_16V7K
12
CC6 0.22U_0402_16V7K
12
CC7 0.22U_0402_16V7K
12
CC8 0.22U_0402_16V7K
12
CC9 0.22U_0402_16V7K
12
CC10 0.22U_0402_16V7K
12
CC11 0.22U_0402_16V7K
12
CC12 0.22U_0402_16V7K
12
CC13 0.22U_0402_16V7K
12
CC14 0.22U_0402_16V7K
12
CC15 0.22U_0402_16V7K
12
CC16 0.22U_0402_16V7K
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_N1
PEG_CTX_GRX_P2
PEG_CTX_GRX_N2
PEG_CTX_GRX_P3
PEG_CTX_GRX_N3
PEG_CTX_GRX_P4
PEG_CTX_GRX_N4
PEG_CTX_GRX_P5
PEG_CTX_GRX_N5
PEG_CTX_GRX_P6
PEG_CTX_GRX_N6
PEG_CTX_GRX_P7
PEG_CTX_GRX_N7
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/7)
CPU (1/7)
CPU (1/7)
LA-9932P
LA-9932P
LA-9932P
6 71Thursday, July 04, 2013
6 71Thursday, July 04, 2013
6 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
SM_DRAMPWROK with DDR Power Gating Topology
+PCH_VCCDS W3_3
D D
C C
B B
PM_DRAM_P WRGD<16>
DDR_HVREF_ RST_PCH<13,14,1 8>
+1.05V_RU N
RC27 100_0402_1%@
+VCCIO_OUT
+1.05V_RU N +VCCST
1 2
RC12 100K_0402_5%
1 2
RC5 100K_04 02_5%@
RUNPWRO K<46 >
1.35V_S US_PWRGD<46,58>
Refer CRB 1.5
1 2
1 2
RC28 49.9_0402_1%@
1 2
RC29 62_0402_5%
RC7 0_ 0402_5%@
RC13 0_0402_ 5%@
RC104 0_0402_5 %@
RC103 0_0402_5 %@
H_THERMTRIP#
H_CATERR#
H_PROCHOT#
Refer CRB 1.0
12
RC99 0_0603_5%@
PM_DRAM_P WRGD_A
RUNPWRO K_R
12
RUNPWRO K_R
12
PM_DRAM_P WRGD_A
RUNPWRO K_AND
12
12
22U_0805_6.3V6M
1
2
Buffered reset to CPU
A A
PCH_PLTRST#<15,16>
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
5
+PCH_VCCDS W3_3
5
1
P
B
2
A
G
3
@
QC5
L2N7002 WT1G_SC-70 -3
D
S
1 3
G
2
1
0.01U_04 02_16V7K
2
22U_0805_6.3V6M
@
@
1
CC47
CC48
2
+3.3V_RUN
@
UC2
1
5
NC
VCC
2
A
4
PCH_PLTRST#_ BUF
GND3Y
SN74LVC1 G07DCKR_SC7 0-5~D
CC19
@
1 2
0.1U_040 2_25V6
4
RUNPWRO K_AND
O
UC1
74AHC1G0 9GW_TSSOP 5
PM_DRAM_P WRGD_CPU
RUNPWRO K_R
CC138
+1.05V_RU N
0.1U_0402_25V6
1
CC21
2
@
RUN_ON_ENA BLE#<46 ,48>
H_PROCHOT#<46,50,6 1,64,65>
H_THERMTRIP#<46>
1K_0402_1%
12
@
RC60
20K_0402_5%
@
12
RC67
CLK_CPU_ SSC_DPLL#<17>
CLK_CPU_ SSC_DPLL<17>
CPU_PLTRST#<20>
4
2
G
Refer CRB 1.5
H_THERMTRIP#
H_PM_SYNC<16>
H_CPUPW RGD<20>
CLK_CPU_ DPLL#<17>
CLK_CPU_ DPLL<1 7>
CLK_CPU_ DMI#<17>
CLK_CPU_ DMI<17>
4
+1.35V_ME M
1.8K_0402_1%
12
3.3K_0402_1%
39_0402_5%
@
12
RC15
L2N7002WT1G_SC-70-3
@
1 2
13
D
QC1
S
Refer CRB 1.5
+VCCST
RC30 56_0402_ 5%
RC31 0_0402_5 %@
place RC31 near CPU
RC33 0_0402_5%@
RC38 0_0402_5%@
RC40 0_0402_5%@
RC42 0_0402_5%@
RC44 0_0402_5%@
RC48 0_0402_5%@
1 2
RC64 43_0402_5%@
RC66 0_0402_5%@
RC6
RC16
1 2
1 2
1 2
12
1 2
RC9 6.8K_0402 _5%@
RC10 0_0402_ 5%@
CPU_DETECT#<45>
PECI_EC<46>
12
12
12
12
12
12
CPU_PLTRST#_ R
1.35V_S US_PWRGD
12
PM_DRAM_P WRGD_CPU
CPU_DETECT#
H_CATERR#
PECI_EC
H_PROCHOT#_ R
H_THERMTRIP#_ R
H_PM_SYNC
VCCPWRG OOD_0_R
PM_DRAM_P WRGD_CPU
CPU_PLTRST#_ R
CPU_DPLL #
CPU_DPLL
CPU_SSC_ DPLL#
CPU_SSC_ DPLL
CPU_DMI#
CPU_DMI
3
JCPU1B
AP32
SKTOCC
AN32
CATERR
AR27
PECI
AK31
FC_AK31
AM30
PROCHOT
AM35
THERMTRIP
AT28
PM_SYNC
AL34
PWRGOOD
AC10
SM_DRAMPWROK
AT26
PLTRSTIN
G28
DPLL_REF_CLKN
H28
DPLL_REF_CLKP
F27
SSC_DPLL_REF_CLKN
E27
SSC_DPLL_REF_CLKP
D26
BCLKN
E26
BCLKP
LOTES_AZIF0012-P002B_HASW ELL
CONN@
VCCPWRG OOD_0_R
Haswell rPGA EDS
MISC
THERMAL CLOCK
DDR3L
PWR
JTAG
2 OF 9
10K_0402_5%
12
RC56
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC33 & RC56
3
2
+VCCIO_OUT
1
2
Place near JXDP1
H_CPUPW RGD H_CPUPW RGD_XDP
SIO_PW RBTN#_R<15,16>
CPU_PW R_DEBUG<11>
SYS_PW ROK<16,45>
AP3
PRDY
PREQ
TRST
TCK
TMS
TDO
DBR
TDI
SM_RCOMP0
AR3
SM_RCOMP1
AP2
SM_RCOMP2
AN3
DDR3_DRAMRS T#_CPU
AR29
XDP_PRDY#
AT29
XDP_PREQ #
AM34
XDP_TCLK
AN33
XDP_TMS
AM33
XDP_TRST#
AM31
XDP_TDI_R
AL33
XDP_TDO_R
AP33
AR30
XDP_OBS 0
AN31
XDP_OBS 1
AN29
XDP_OBS 2
AP31
XDP_OBS 3
AP30
XDP_OBS 4
AN28
XDP_OBS 5
AP29
XDP_OBS 6
AP28
XDP_OBS 7
DDR3_DRAMRS T#_CPU <13>
1 2
RC32 0_0402_5%CXDP@
1 2
RC34 0_0402_5%CXDP@
RC35 0_0402_5%@
12
PAD~D
T173
@
PAD~D
T174
@
PAD~D
T88
@
PAD~D
T89
@
PAD~D
T90
@
PAD~D
T116
@RC46 0_0402_5%@
PAD~D
T117
@ C1553
PAD~D
T118
@
XDP_DBRE SET#XDP_DBRE SET#_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
SM_DRAMRST
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
different with 15
DDR3 COMPENSATION SIGNALS
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1 2
RC58 100_0402_1%
1 2
RC61 75_0402_1%
1 2
RC63 100_0402_1%
2
0.1U_0402_25V6
0.1U_0402_25V6
CXDP@
1
CC17
2
RC20 need to close to JCPU1
CPU_PLTRST#_ R
XDP_TDI
XDP_TDO
CXDP@
CC18
1 2
RC20 1K_0402_1%CXDP@
1 2
RC21 0_0402_5%CXDP@
1 2
RC22 0_0402_5%CXDP@
1 2
RC24 0_0402_5%@
1 2
RC23 1K_0402_1%CXDP@
XDP_DBRE SET# <15,16>
1
+VCCIO_OUT
JXDP1
1 2
RC11 1K_0402 _1%@
1
EMC@
0.047U_0 402_25V7 K
2
close CPU
12
12
12
12
12
12
12
1
OBSFN_A0
2
OBSFN_A1
3
GND
4
OBSDATA_A[0]
5
OBSDATA_A[1]
6
GND
7
OBSDATA_A[2]
8
OBSDATA_A[3]
9
GND
10
HOOK0
11
HOOK1
12
HOOK2
13
HOOK3
14
HOOK4
15
HOOK5
16
VCCOBS_AB
17
HOOK6
18
HOOK7
19
GND
20
TDO
21
TRSTn
22
TDI
23
TMS
TCK124GND
25
GND
26
TCK0
MOLEX_5 2435-2671
CONN@
+3.3V_RUN
+1.05V_RU N
GND
SYS_PW ROK_XDP
CFG3
XDP_PREQ #
XDP_PRDY#
CFG3
CFG3<10>
CFD_PWR BTN#_XDP
CPU_PW R_DEBUG_R
SYS_PW ROK_XDP
XDP_RST#_ R
XDP_DBRE SET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCLK
XDP_DBRE SET#
ESD Request
PU/PD for JTAG signals
XDP_DBRE SET#
XDP_TMS
XDP_TDI
XDP_PREQ #
XDP_TDO
XDP_TCLK
XDP_TRST#
RC52 1K_0402_1%
EMC@
RC53 51_0402_1%@
RC54 51_0402_1%@
RC55 51_0402_1%@
RC57 51_0402_1%CXDP@
RC59 51_0402_1%
RC62 51_0402_1%
+3.3V_AL W_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/7)
CPU (2/7)
CPU (2/7)
LA-9932P
LA-9932P
LA-9932P
1
12
RC100
1K_0402 _1%
7 71Thursday, July 04, 2013
7 71Thursday, July 04, 2013
7 71Thursday, July 04, 2013
27
28
@
Refer CRB 1.0
1.0
1.0
1.0
5
4
3
2
1
D D
DDR_A_D[0..63]<13>
C C
B B
+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
JCPU1C
AR15
SA_DQ_0
AT14
SA_DQ_1
AM14
SA_DQ_2
AN14
SA_DQ_3
AT15
SA_DQ_4
AR14
SA_DQ_5
AN15
SA_DQ_6
AM15
SA_DQ_7
AM9
SA_DQ_8
AN9
SA_DQ_9
AM8
SA_DQ_10
AN8
SA_DQ_11
AR9
SA_DQ_12
AT9
SA_DQ_13
AR8
SA_DQ_14
AT8
SA_DQ_15
AJ9
SA_DQ_16
AK9
SA_DQ_17
AJ6
SA_DQ_18
AK6
SA_DQ_19
AJ10
SA_DQ_20
AK10
SA_DQ_21
AJ7
SA_DQ_22
AK7
SA_DQ_23
AF4
SA_DQ_24
AF5
SA_DQ_25
AF1
SA_DQ_26
AF2
SA_DQ_27
AG4
SA_DQ_28
AG5
SA_DQ_29
AG1
SA_DQ_30
AG2
SA_DQ_31
J1
SA_DQ_32
J2
SA_DQ_33
J5
SA_DQ_34
H5
SA_DQ_35
H2
SA_DQ_36
H1
SA_DQ_37
J4
SA_DQ_38
H4
SA_DQ_39
F2
SA_DQ_40
F1
SA_DQ_41
D2
SA_DQ_42
D3
SA_DQ_43
D1
SA_DQ_44
F3
SA_DQ_45
C3
SA_DQ_46
B3
SA_DQ_47
B5
SA_DQ_48
E6
SA_DQ_49
A5
SA_DQ_50
D6
SA_DQ_51
D5
SA_DQ_52
E5
SA_DQ_53
B6
SA_DQ_54
A6
SA_DQ_55
E12
SA_DQ_56
D12
SA_DQ_57
B11
SA_DQ_58
A11
SA_DQ_59
E11
SA_DQ_60
D11
SA_DQ_61
B12
SA_DQ_62
A12
SA_DQ_63
AM3
SM_VREF
F16
SA_DIMM_VREFDQ
F13
SB_DIMM_VREFDQ
LOTES_AZIF0012-P002B_HASWELL
CONN@
Haswell rPGA EDS
3 OF 9
RSVD
SA_CKN0
SA_CKP0
SA_CKE_0
SA_CKN1
SA_CKP1
SA_CKE_1
SA_CKN2
SA_CKP2
SA_CKE_2
SA_CKN3
SA_CKP3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
VSS
SA_RAS
SA_WE
SA_CAS
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
AC7
U4
M_CLK_DDR#0
V4
M_CLK_DDR0
AD9
DDR_CKE0_DIMMA
U3
M_CLK_DDR#1
V3
M_CLK_DDR1
AC9
DDR_CKE1_DIMMA
U2
V2
AD8
U1
V1
AC8
M7
DDR_CS0_DIMMA#
L9
DDR_CS1_DIMMA#
M9
M10
M8
M_ODT0
L7
M_ODT1
L8
L10
V5
DDR_A_BS0
U5
DDR_A_BS1
AD1
DDR_A_BS2
V10
U6
DDR_A_RAS#
U7
DDR_A_WE#
U8
DDR_A_CAS#
V8
DDR_A_MA0
AC6
DDR_A_MA1
V9
DDR_A_MA2
U9
DDR_A_MA3
AC5
DDR_A_MA4
AC4
DDR_A_MA5
AD6
DDR_A_MA6
AC3
DDR_A_MA7
AD5
DDR_A_MA8
AC2
DDR_A_MA9
V6
DDR_A_MA10
AC1
DDR_A_MA11
AD4
DDR_A_MA12
V7
DDR_A_MA13
AD3
DDR_A_MA14
AD2
DDR_A_MA15
AP15
DDR_A_DQS#0
AP8
DDR_A_DQS#1
AJ8
DDR_A_DQS#2
AF3
DDR_A_DQS#3
J3
DDR_A_DQS#4
E2
DDR_A_DQS#5
C5
DDR_A_DQS#6
C11
DDR_A_DQS#7
AP14
DDR_A_DQS0
AP9
DDR_A_DQS1
AK8
DDR_A_DQS2
AG3
DDR_A_DQS3
H3
DDR_A_DQS4
E3
DDR_A_DQS5
C6
DDR_A_DQS6
C12
DDR_A_DQS7
T2 PAD~D@
M_CLK_DDR#0 <13>
M_CLK_DDR0 <13>
DDR_CKE0_DIMMA <13>
M_CLK_DDR#1 <13>
M_CLK_DDR1 <13>
DDR_CKE1_DIMMA <13>
DDR_CS0_DIMMA# <13>
DDR_CS1_DIMMA# <13>
M_ODT0 <13>
M_ODT1 <13>
DDR_A_BS0 <13>
DDR_A_BS1 <13>
DDR_A_BS2 <13>
DDR_A_RAS# <13>
DDR_A_WE# <13>
DDR_A_CAS# <13>
DDR_A_MA[0..15] <13>
DDR_A_DQS#[0..7] <13>
DDR_A_DQS[0..7] <13>
DDR_B_D[0..63]<14>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
JCPU1D
AR18
SB_DQ_0
AT18
SB_DQ_1
AM17
SB_DQ_2
AM18
SB_DQ_3
AR17
SB_DQ_4
AT17
SB_DQ_5
AN17
SB_DQ_6
AN18
SB_DQ_7
AT12
SB_DQ_8
AR12
SB_DQ_9
AN12
SB_DQ_10
AM11
SB_DQ_11
AT11
SB_DQ_12
AR11
SB_DQ_13
AM12
SB_DQ_14
AN11
SB_DQ_15
AR5
SB_DQ_16
AR6
SB_DQ_17
AM5
SB_DQ_18
AM6
SB_DQ_19
AT5
SB_DQ_20
AT6
SB_DQ_21
AN5
SB_DQ_22
AN6
SB_DQ_23
AJ4
SB_DQ_24
AK4
SB_DQ_25
AJ1
SB_DQ_26
AJ2
SB_DQ_27
AM1
SB_DQ_28
AN1
SB_DQ_29
AK2
SB_DQ_30
AK1
SB_DQ_31
L2
SB_DQ_32
M2
SB_DQ_33
L4
SB_DQ_34
M4
SB_DQ_35
L1
SB_DQ_36
M1
SB_DQ_37
L5
SB_DQ_38
M5
SB_DQ_39
G7
SB_DQ_40
J8
SB_DQ_41
G8
SB_DQ_42
G9
SB_DQ_43
J7
SB_DQ_44
J9
SB_DQ_45
G10
SB_DQ_46
J10
SB_DQ_47
A8
SB_DQ_48
B8
SB_DQ_49
A9
SB_DQ_50
B9
SB_DQ_51
D8
SB_DQ_52
E8
SB_DQ_53
D9
SB_DQ_54
E9
SB_DQ_55
E15
SB_DQ_56
D15
SB_DQ_57
A15
SB_DQ_58
B15
SB_DQ_59
E14
SB_DQ_60
D14
SB_DQ_61
A14
SB_DQ_62
B14
SB_DQ_63
LOTES_AZIF0012-P002B_HASWELL
CONN@
Haswell rPGA EDS
4 OF 9
RSVD
SB_CKN0
SB_CKP0
SB_CKE_0
SB_CKN1
SB_CKP1
SB_CKE_1
SB_CKN2
SB_CKP2
SB_CKE_2
SB_CKN3
SB_CKP3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
VSS
SB_RAS
SB_WE
SB_CAS
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
AG8
Y4
M_CLK_DDR#2
AA4
M_CLK_DDR2
AF10
DDR_CKE2_DIMMB
Y3
M_CLK_DDR#3
AA3
M_CLK_DDR3
AG10
DDR_CKE3_DIMMB
Y2
AA2
AG9
Y1
AA1
AF9
P4
DDR_CS2_DIMMB#
R2
DDR_CS3_DIMMB#
P3
P1
R4
M_ODT2
R3
M_ODT3
R1
P2
R7
DDR_B_BS0
P8
DDR_B_BS1
AA9
DDR_B_BS2
R10
R6
DDR_B_RAS#
P6
DDR_B_WE#
P7
DDR_B_CAS#
R8
DDR_B_MA0
Y5
DDR_B_MA1
Y10
DDR_B_MA2
AA5
DDR_B_MA3
Y7
DDR_B_MA4
AA6
DDR_B_MA5
Y6
DDR_B_MA6
AA7
DDR_B_MA7
Y8
DDR_B_MA8
AA10
DDR_B_MA9
R9
DDR_B_MA10
Y9
DDR_B_MA11
AF7
DDR_B_MA12
P9
DDR_B_MA13
AA8
DDR_B_MA14
AG7
DDR_B_MA15
AP18
DDR_B_DQS#0
AP11
DDR_B_DQS#1
AP5
DDR_B_DQS#2
AJ3
DDR_B_DQS#3
L3
DDR_B_DQS#4
H9
DDR_B_DQS#5
C8
DDR_B_DQS#6
C14
DDR_B_DQS#7
AP17
DDR_B_DQS0
AP12
DDR_B_DQS1
AP6
DDR_B_DQS2
AK3
DDR_B_DQS3
M3
DDR_B_DQS4
H8
DDR_B_DQS5
C9
DDR_B_DQS6
C15
DDR_B_DQS7
T3 PAD~D@
M_CLK_DDR#2 <14>
M_CLK_DDR2 <14>
DDR_CKE2_DIMMB <14>
M_CLK_DDR#3 <14>
M_CLK_DDR3 <14>
DDR_CKE3_DIMMB <14>
DDR_CS2_DIMMB# <14>
DDR_CS3_DIMMB# <14>
M_ODT2 <14>
M_ODT3 <14>
DDR_B_BS0 <14>
DDR_B_BS1 <14>
DDR_B_BS2 <14>
DDR_B_RAS# <14>
DDR_B_WE# <14>
DDR_B_CAS# <14>
DDR_B_MA[0..15] <14>
DDR_B_DQS#[0..7] <14>
DDR_B_DQS[0..7] <14>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Compal Electronics, Inc.
CPU (3/7)
CPU (3/7)
CPU (3/7)
LA-9932P
LA-9932P
LA-9932P
8 71Thursday, July 04, 2013
8 71Thursday, July 04, 2013
8 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
D D
4
3
2
1
COMPENSATION PU FOR eDP
+VCOMP_OUT
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
JCPU1H
T28
TMDSB_CPU_N2<26>
TMDSB_CPU_P2<26>
C C
TMDSB_CPU_N1<26>
TMDSB_CPU_P1<26>
TMDSB_CPU_N0<26>
TMDSB_CPU_P0<26>
TMDSB_CPU_CLK#<26>
TMDSB_CPU_CLK<26>
DPC_CPU_LANE_N0<44>
DPC_CPU_LANE_P0<44>
DPC_CPU_LANE_N1<44>
DPC_CPU_LANE_P1<44>
DPC_CPU_LANE_N2<44>
DPC_CPU_LANE_P2<44>
DPC_CPU_LANE_N3<44>
DPC_CPU_LANE_P3<44>
DPD_CPU_LANE_N0<44>
DPD_CPU_LANE_P0<44>
DPD_CPU_LANE_N1<44>
DPD_CPU_LANE_P1<44>
DPD_CPU_LANE_N2<44>
DPD_CPU_LANE_P2<44>
DPD_CPU_LANE_N3<44>
DPD_CPU_LANE_P3<44>
DDIB_TXN0
U28
DDIB_TXP0
T30
DDIB_TXN1
U30
DDIB_TXP1
U29
DDIB_TXN2
V29
DDIB_TXP2
U31
DDIB_TXN3
V31
DDIB_TXP3
T34
DDIC_TXN0
U34
DDIC_TXP0
U35
DDIC_TXN1
V35
DDIC_TXP1
U32
DDIC_TXN2
T32
DDIC_TXP2
U33
DDIC_TXN3
V33
DDIC_TXP3
P29
DDID_TXN0
R29
DDID_TXP0
N28
DDID_TXN1
P28
DDID_TXP1
P31
DDID_TXN2
R31
DDID_TXP2
N30
DDID_TXN3
P30
DDID_TXP3
LOTES_AZIF0012-P002B_HASWELL
CONN@
Haswell rPGA EDS
DDI
EDP_DISP_UTIL
eDP
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
8 OF 9
M27
N27
P27
EDP_HPD#
E24
EDP_COMP
R27
P35
R35
N34
P34
P33
R33
N32
P32
Question:
JCPU1H.P27 pinout is EDP_HPD. is it high active when Plug in eDP device?
EDP_CPU_AUX# <27>
EDP_CPU_AUX <27>
T4PAD~D @
EDP_CPU_LANE_N0 <27>
EDP_CPU_LANE_P0 <27>
EDP_CPU_LANE_N1 <27>
EDP_CPU_LANE_P1 <27>
FDI_CTX_PRX_N0 <16>
FDI_CTX_PRX_P0 <16>
FDI_CTX_PRX_N1 <16>
FDI_CTX_PRX_P1 <16>
Max length=100 mils.
+VCCIO_OUT
12
RC7324.9_0402_1%
10K_0402_5%
RC74
HPD INVERSION FOR EDP
B B
CPU_EDP_HPD<27>
100K_0402_5%
12
1 2
EDP_HPD#
13
D
2
QC3
G
L2N7002WT1G_SC-70-3
RC75
S
QC3 change PN to SB50138003L S TR BSS138-7-F 1N SOT23-3
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/7)
CPU (4/7)
CPU (4/7)
LA-9932P
LA-9932P
LA-9932P
9 71Thursday, July 04, 2013
9 71Thursday, July 04, 2013
9 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
4
3
2
1
CFG STRAPS for CPU
CFG2
D D
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
JCPU1I
T11 PAD~D@
T5 PAD~D@
T6 PAD~D@
T8 PAD~D@
T9 PAD~D@
T10 PAD~D@
T15 PAD~D@
T16 PAD~D@
T157PAD~D@
T158PAD~D@
T159PAD~D@
T160PAD~D@
T161PAD~D@
T162PAD~D@
T163PAD~D@
T164PAD~D@
T165PAD~D@
T166PAD~D@
T17 PAD~D@
+VCC_CORE
T18 PAD~D@
T20 PAD~D@
T23 PAD~D@
T26 PAD~D@
T28 PAD~D@
CFG3<7>
C C
12
B B
RC80 49.9_0402_1%
RC81 49.9_0402_1%
RC82 49.9_0402_1%
H_CPU_TESTLO
12
CFG_RCOMP
12
H_CPU_RSVD
H_CPU_RSVD
H_CPU_TESTLO
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
AT1
RSVD_TP
AT2
RSVD_TP
AD10
RSVD
A34
RSVD_TP
A35
RSVD_TP
W29
RSVD_TP
W28
RSVD_TP
G26
TESTLO_G26
W33
VSS
AL30
RSVD
AL29
RSVD
F25
VCC
C35
RSVD_TP
B35
RSVD_TP
AL25
RSVD_TP
W30
RSVD_TP
W31
RSVD_TP
W34
TESTLO_W34
AT20
CFG_0
AR20
CFG_1
AP20
CFG_2
AP22
CFG_3
AT22
CFG_4
AN22
CFG_5
AT25
CFG_6
AN23
CFG_7
AR24
CFG_8
AT23
CFG_9
AN20
CFG_10
AP24
CFG_11
AP26
CFG_12
AN25
CFG_13
AN26
CFG_14
AP25
CFG_15
LOTES_AZIF0012-P002B_HASWELL
CONN@
Haswell rPGA EDS
9 OF 9
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD
FC_G6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
C23
B23
D24
D23
AT31
CFG_RCOMP
AR21
CFG16
AR23
CFG18
AP21
CFG17
AP23
CFG19
AR33
G6
FC_G6
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
Refer 1.2 CRB
T12PAD~D @
T7PAD~D @
T13PAD~D @
T14PAD~D @
T167PAD~D @
T168PAD~D @
T169PAD~D @
T170PAD~D @
T19PAD~D @
T22PAD~D @
T24PAD~D @
T25PAD~D @
T27PAD~D @
T29PAD~D @
T30PAD~D @
T31PAD~D @
T32PAD~D @
T33PAD~D @
T34PAD~D @
T35PAD~D @
T36PAD~D @
CFG4
CFG[6:5]
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
CFG4
Display Port Presence Strap
CFG6
CFG5
PCIE Port Bifurcation Straps
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
1K_0402_1%
12
@
RC76
1K_0402_1%
12
RC77
1K_0402_1%
1K_0402_1%
12
12
@
RC78
@
RC79
1K_0402_1%
12
@
RC83
Note: Reserve this circuit
for future compatibility
12
6.04K_0402_1%
A A
5
FC_G6
4
12
@
2.67K_0402_1%
RC69@
RC68
RESET_OUT# <15,16,46>
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following xxRESETB de assertion
0: PEG Wait for BIOS for training
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/7)
CPU (5/7)
CPU (5/7)
LA-9932P
LA-9932P
LA-9932P
10 71Thursday, July 04, 2013
10 71Thursday, July 04, 2013
10 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
4
3
2
1
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
+VCC_CORE
JCPU1E
Haswell rPGA EDS
+VCC_CORE
K27
RSVD
L27
RSVD
T27
RSVD
V27
RSVD
AB11
VDDQ
AB2
VDDQ
AB5
VDDQ
AB8
VDDQ
AE11
VDDQ
AE2
VDDQ
AE5
VDDQ
AE8
VDDQ
AH11
VDDQ
K11
VDDQ
N11
VDDQ
N8
VDDQ
T11
VDDQ
T2
VDDQ
T5
VDDQ
T8
VDDQ
W11
VDDQ
W2
VDDQ
W5
VDDQ
W8
VDDQ
N26
RSVD
K26
VCC
AL27
RSVD
AK27
RSVD
AL35
VCC_SENSE
E17
RSVD
AN35
VCCIO_OUT
A23
FC_A23
F22
VCOMP_OUT
W32
RSVD
AL16
RSVD
J27
RSVD
AL13
RSVD
AM28
VIDALERT
AM29
VIDSCLK
AL28
VIDSOUT
AP35
VSS
H27
PWR_DEBUG
AP34
VSS
AT35
RSVD_TP
AR35
RSVD_TP
AR32
RSVD_TP
AL26
RSVD_TP
AT34
VSS
AL22
VSS
AT33
VSS
AM21
VSS
AM25
VSS
AM22
VSS
AM20
VSS
AM24
VSS
AL19
VSS
AM23
VSS
AT32
VSS
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y31
VCC
Y32
VCC
Y33
VCC
Y34
VCC
Y35
VCC
LOTES_AZIF0012-P002B_HASWELL
CONN@
5 OF 9
T39 PAD~D@
T40 PAD~D@
T41 PAD~D@
D D
+1.05V_RUN
150_0402_1%
+VCCIO_OUT max. current
12
is 300mA, 20mil
C C
SVID ALERT
VIDALERT_N<61>
SVID DATA
B B
VIDSOUT<61>
VCC_SENSE
+VCCIO_OUT
12
+VCCIO_OUT
12
+VCC_CORE
75_0402_1%
RC87
RC88 43_0402_5%
130_0402_1%
RC90
VIDSOUT
100_0402_1%
12
RC91
CAD Note: Place the PU resistors close to CPU
RC87 close to CPU 300 - 1500mils
12
H_CPU_SVIDALRT#
CAD Note: Place the PU resistors close to CPU
RC90 close to CPU 300 - 1500mils
+1.05V_RUN
RC86 0_0603_5%@
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
+1.05V_RUN +VCCIO2PCH
RC105 0_0603_5%@
+1.35V_MEM
10U_0805_10V6K
1
2
12
12
VDDQ DECOUPLING
10U_0805_10V6K
@
@
1
CC25
CC24
2
+VCCIO_OUT
10U_0805_10V6K
@
1
CC26
2
4.7U_0603_6.3V6K
CC137
1
2
@
10U_0805_10V6K
@
1
1
CC27
2
2
RC85
CPU_PWR_DEBUG
10K_0402_5%
12
@
RC89
+VCCIO2PCH_R
RC106 0_0603_5%@
10U_0805_10V6K
@
CC28
12
Place T72 close to
T55 for iFDIM t est
10U_0805_10V6K
1
2
10U_0805_10V6K
10U_0805_10V6K
@
1
CC29
2
10U_0805_10V6K
@
@
1
1
CC31
CC30
CC32
2
2
T42 PAD~D@
T43 PAD~D@
+VCC_CORE
T44 PAD~D@
T45 PAD~D@
T46 PAD~D@
+VCCIO_OUT
+VCCIO2PCH_R
+VCOMP_OUT
T48 PAD~D@
T49 PAD~D@
T50 PAD~D@
T51 PAD~D@
VIDSCLK<61>
CPU_PWR_DEBUG<7>
T52 PAD~D@
T53 PAD~D@
T54 PAD~D@
T55 PAD~D@
T72
@
PAD~D
330U_D2_2VM_R6M~D
10U_0805_10V6K
@
1
1
CC34
1
+
+
CC33
2
2
2
330U_D2_2VM_R6M
CC35
+1.35V_MEM
VCCSENSE_R
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
CAD Note: RC92 SHOULD BE PLACED CLOSE TO CPU
VCCSENSE<61>
VSSSENSE<61> VSSSENSE_R <12>
A A
VCCSENSE VCCSENSE_R
VSSSENSE VSSSENSE_R
100_0402_1%
12
RC94
12
RC92 0_0402_5%@
CAD Note: RC93 SHOULD BE PLACED CLOSE TO CPU
12
RC93 0_0402_5%@
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CC40
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CC36
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
CC41
@
1
1
1
CC37
CC42
2
2
2
22U_0805_6.3V6M
@
@
1
1
CC43
CC38
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
@
1
CC44
2
22U_0805_6.3V6M
@
@
CC39
@
1
1
CC45
CC46
2
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/7)
CPU (6/7)
CPU (6/7)
LA-9932P
LA-9932P
LA-9932P
1
11 71Thursday, July 04, 2013
11 71Thursday, July 04, 2013
11 71Thursday, July 04, 2013
1.0
1.0
1.0
5
4
3
2
1
JCPU1F
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CONN@
Haswell rPGA EDS
6 OF 9
A10
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AK11
AK25
AK26
AK28
AK29
AK30
AK32
A13
A16
A19
A22
A25
A27
A29
A3
A31
A33
A4
A7
AJ5
E19
D D
C C
B B
LOTES_AZIF0012-P002B_HASWELL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22
JCPU1G
B34
B4
B7
C1
C10
C13
C16
C19
C2
C22
C24
C26
C28
C30
C32
C34
C4
C7
D10
D13
D16
D19
D22
D25
D27
D29
D31
D33
D35
D4
D7
E1
E10
E13
E16
E4
E7
F10
F11
F12
F14
F15
F17
F18
F20
F21
F23
F24
F26
F28
F30
F32
F34
F4
F6
F7
F8
F9
G1
G11
G2
G27
G29
G3
G31
G33
G35
G4
G5
H10
H26
H6
H7
J11
J26
J28
J30
J32
J34
J6
K1
Haswell rPGA EDS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
LOTES_AZIF0012-P002B_HASWELL
CONN@
VSS_SENSE
7 OF 9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
VSSSENSE_R <11>
T56PAD~D @
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/7)
CPU (7/7)
CPU (7/7)
LA-9932P
LA-9932P
LA-9932P
12 71Thursday, July 04, 2013
12 71Thursday, July 04, 2013
12 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
4
3
2
1
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q
1 2
RD26 0_0402_5%@
QD6A
@
DMN66D0LDW-7_SOT363-6
1K_0402_1%
12
DDR_HVREF_RST_PCH
DDR_HVREF_RST_PCH
1U_0402_6.3V6K
1
CD3
2
10U_0603_6.3V6M
CD7
1
2
@
4.99K_0402_1%
5
RD27
@
+SM_VREF
RD29 0_0402_5%@
L2N7002WT1G_SC-70-3
1K_0402_1%
12
RD28
@
Layout Note:
Place near JDIMM1
1U_0402_6.3V6K
1
CD4
2
10U_0603_6.3V6M
CD8
1
1
2
2
12
RD24
D D
DDR_HVREF_RST_PCH<7,14,18>
C C
+1.35V_MEM
B B
A A
DDR3_DRAMRST#_CPU<7> DDR3_DRAMRST#_R <14>
+1.35V_MEM
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
2
1 2
QD7
@
S
G
2
1U_0402_6.3V6K
1
CD5
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD10
CD9
1
2
DDR_HVREF_RST_PCH
61
D
13
1U_0402_6.3V6K
1
2
1
2
+SM_VREF_Q
CD6
10U_0603_6.3V6M
10U_0603_6.3V6M
CD11
1
2
RD4 0_0402_5%@
L2N7002WT1G_SC-70-3
12
12
1 2
RD17 2_0402_1%
1
CD47
0.022U_0402_16V7K
2
RC109
24.9_0402_1%
+V_DDR_REF, +SA_DIMM1_VREFDQ, +SA_DIMM_VREFDQ, +DIMM1_VREF_DQ
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
1 2
RD20 2_0402_1%
1
CD48
0.022U_0402_16V7K
2
RC110
24.9_0402_1%
10U_0603_6.3V6M
@
1
CD12
CD13
1
+
2
2
All VREF traces should
have 10 mil trace width
12
QD9
@
D
S
13
G
2
1
CD45
@
0.047U_0402_16V4Z
2
+1.35V_MEM
1K_0402_1%
12
RD19
+SA_DIMM1_VREFDQ
1K_0402_1%
12
RD18
+1.35V_MEM
1K_0402_1%
12
RD22
+SM_VREF_DIMM
1K_0402_1%
12
RD21
Layout Note:
Place near JDIMM1.203,204
+0.675V_DDR_VTT
330U_2.5V_M
CD14
+1.35V_MEM
12
RD2
@
1K_0402_5%
1 2
RD25 0_0402_5%@
1U_0402_6.3V6K
1
CD17
2
4
Populate RD1, De-Populate RD3 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
1 2
+SA_DIMM1_VREFDQ
+V_DDR_REF
1U_0402_6.3V6K
1
CD18
2
RD1 0_0402_5%@
1 2
RD3 0_0402_5%@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD19
CD20
2
2
1 2
RD6 0_0402_5%@
1 2
RD7 0_0402_5%@
DIMM1_SA0
DIMM1_SA1
+3.3V_RUN
+DIMM1_VREF_DQ
0.1U_0402_25V6
1
CD21
2
JDIMM1 H=5.2mm
JDIMM1
VREF_DQ1VSS1
0.1U_0402_25V6
2.2U_0402_6.3V6M
1
CD1
2
@
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
2.2U_0402_6.3V6M
1
CD22
2
3
DDR_A_D0
DDR_A_D1
1
CD2
2
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9 DDR_A_D13
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DIMM1_SA0
DIMM1_SA1
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
VDD175VDD2
77
NC1
79
BA2
VDD381VDD4
A12/BC#83A11
85
A9
VDD587VDD6
89
A8
91
A5
VDD793VDD8
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013290-1
CONN@
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
4
DQ4
6
DQ5
8
10
12
14
16
DQ6
18
DQ7
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
CK1
104
106
108
BA1
110
112
114
S0#
116
118
120
122
NC2
124
126
128
130
132
134
136
DM4
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
DM6
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SDA
202
SCL
204
206
G2
2
+1.35V_MEM+1.35V_MEM
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR3_DRAMRST#_R
DDR_A_D14
DDR_A_D15
DDR_A_D20DDR_A_D16
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.675V_DDR_VTT+0.675V_DDR_VTT
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
M_ODT0 <8>
M_ODT1 <8>
+V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
+DIMM1_VREF_CA
RD5 0_0402_5%@
RD13 0_0402_5%@
0.1U_0402_25V6
2.2U_0402_6.3V6M
@
CD16
CD15
1
1
2
2
DDR_XDP_WAN_SMBDAT <14,15,18,27,31>
DDR_XDP_WAN_SMBCLK <14,15,18,27,31>
12
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-9932P
LA-9932P
LA-9932P
1
+V_DDR_REF
+SM_VREF_DIMM
13 71Thursday, July 04, 2013
13 71Thursday, July 04, 2013
13 71Thursday, July 04, 2013
1.0
1.0
1.0
5
4
Populate RD4, De-Populate RD9 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M3
3
2
1
JDIMM2 H=9.2mm
1 2
+3.3V_RUN
RD8 0_0402_5%@
1 2
RD9 0_0402_5%@
12
12
DIMM2_SA0
DIMM2_SA1
RD11 0_0402_5%@
RD12 0_0402_5%@
1K_0402_1%
12
1K_0402_1%
12
RD15
RD16
+SB_DIMM2_VREFDQ
+V_DDR_REF
+SB_DIMM2_VREFDQ
4
+SB_DIMM_VREFDQ_Q+SB_DIMM_VREFDQ
D D
DDR_HVREF_RST_PCH<7,13,18>
C C
B B
+1.35V_MEM
A A
RD31 0_0402_5%@
DMN66D0LDW-7_SOT363-6
1K_0402_1%
12
RD30
@
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
+1.35V_MEM
1U_0402_6.3V6K
1
CD25
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD29
1
1
2
2
Layout Note:
Place near JDIMM2.203,204
+0.675V_DDR_VTT
1U_0402_6.3V6K
1
CD39
2
5
QD6B
@
4
5
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K
1
CD26
2
10U_0603_6.3V6M
CD31
CD30
1
1
2
2
1U_0402_6.3V6K
1
CD40
2
12
3
1U_0402_6.3V6K
1
CD27
2
10U_0603_6.3V6M
CD32
1
2
1U_0402_6.3V6K
1
CD41
2
RD14 2_0402_1%
0.022U_0402_16V7K
1
CD46
2
24.9_0402_1%
12
RC108
1U_0402_6.3V6K
1
CD28
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD34
CD33
1
1
2
2
1U_0402_6.3V6K
1
CD42
2
1 2
+V_DDR_REF, +SB_DIMM2_VREFDQ, +SB_DIMM_VREFDQ, +DIMM2_VREF_DQ
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
10U_0603_6.3V6M
@
CD35
+1.35V_MEM
330U_2.5V_M
1
CD36
+
2
+DIMM2_VREF_DQ
2.2U_0402_6.3V6M
1
2
DDR_CKE2_DIMMB<8>
DDR_CS3_DIMMB#<8>
+3.3V_RUN
0.1U_0402_25V6
1
2
0.1U_0402_25V6
DDR_B_D0
1
2
1
2
CD23
2.2U_0402_6.3V6M
CD44
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DIMM2_SA0
DIMM2_SA1
+0.675V_DDR_VTT
3
CD24
@
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
CD43
+1.35V_MEM +1.35V_MEM
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013311-1
CONN@
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR3_DRAMRST#_R
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.675V_DDR_VTT
2
DDR3_DRAMRST#_R <13>
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <8>
M_ODT3 <8>
+V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
+DIMM2_VREF_CA
RD10 0_0402_5%@
2.2U_0402_6.3V6M
1
2
DDR_XDP_WAN_SMBDAT <13,15,18,27,31>
DDR_XDP_WAN_SMBCLK <13,15,18,27,31>
RD23 0_0402_5%@
0.1U_0402_25V6
@
CD37
CD38
1
2
12
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-9932P
LA-9932P
LA-9932P
1
+V_DDR_REF
+SM_VREF_DIMM
1.0
1.0
14 71Thursday, July 04, 2013
14 71Thursday, July 04, 2013
14 71Thursday, July 04, 2013
1.0
5
4
3
2
1
+RTC_CELL
330K_0402_1%
12
RH5
D D
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
+3.3V_RUN
RH34 10K_0402_5%@
NO REBOOT STRAP
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
C C
+3.3V_RUN
RH40 10K_0402_5%@
Follow Check list 1.0
B B
HDA for Codec
PCH_AZ_CO DEC_BITCLK<30>
A A
PCH_AZ_CO DEC_SDOUT<30>
PCH_INTVRMEN
1 2
1 2
PCH_AZ_CO DEC_RST#<30>
PCH_AZ_CO DEC_SYNC<30>
SPKR
PCH_GPIO 33
CMOS_CLR1
Shunt Clear CMOS
Open
ME_CLR1
Shunt Clear ME RTC Registers
Open
+3.3V_AL W_PCH
1 2
RH35 1K_0402_1%@
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
CMOS setting
Keep CMOS
TPM setting
Keep ME RTC Registers
RPH10
1 8
PCH_AZ_B ITCLK
2 7
PCH_AZ_S DOUT
3 6
PCH_AZ_RS T#
4 5
PCH_AZ_S YNC
33_8P4R _5%
PCH_AZ_S DOUT
1
1
@
ME1 SHORT PADS ~D
1 2
CH6 1U_04 02_6.3V6K
MCARD_PCIE _SATA#<20,45>
SIO_EXT_W AKE#<17 ,20,45>
PCH_RSMRST# _Q<16,47>
+RTC_CELL
2
USB_OC0#<19,40,41,42>
USB_OC1#<17, 19,42>
USB_OC2#<17,19>
USB_OC3#<1 9>
USB_OC4#<19,43>
USB_OC5#<1 9>
USB_OC6#<1 9>
SIO_EXT_S MI#<19,46 >
HDD_DET#<15,17 ,31>
PCH_GPIO 36<2 0>
PCH_GPIO 37<2 0>
PCH_GPIO 49<2 0>
LANCLK_R EQ#<17,33>
MMICLK_RE Q#<17,36>
PCH_GPIO 35<2 0>
RESET_OUT#<10,16 ,46>
1 2
RH42 20K_0402_1%
1 2
RH43 1M_0402_5%
1 2
RH44 20K_0402_1%
2
+3.3V_AL W_PCH
0_0603_5%
12
RH46
PXDP@
+3.3V_AL W_PCH_JTAG
HDD_DET#
BBS_BIT0_ R
PCH_GPIO 36
PCH_GPIO 37
MCARD_PCIE _SATA#
PCH_GPIO 49
LANCLK_R EQ#
MMICLK_RE Q#
SIO_EXT_W AKE#
PCH_GPIO 35
PCH_RSMRST# _Q RSMRST#_XDP
RESET_OUT# RESET_OUT#_ R
PCH_RTCRST#<35 >
1
1
@
CMOS1 SHORT PADS~D
1 2
CH7
CMOS place near DIMM
RH47 51_0402_1%
RH48 210_0402_1%
RH50 210_0402_1%
RH3 0 _0402_5%PXDP@
RH4 0 _0402_5%PXDP@
RH6 0 _0402_5%PXDP@
RH7 0 _0402_5%PXDP@
RH8 0 _0402_5%PXDP@
RH9 0 _0402_5%PXDP@
RH17 0_0402_5%PXDP@
RH10 0_0402_5%PXDP@
RH11 0_0402_5%PXDP@
RH13 0_0402_5%PXDP@
RH12 0_0402_5%PXDP@
RH14 0_0402_5%PXDP@
RH16 0_0402_5%PXDP@
RH19 0_0402_5%PXDP@
RH20 0_0402_5%PXDP@
RH22 0_0402_5%PXDP@
RH24 0_0402_5%PXDP@
RH25 0_0402_5%PXDP@
RH26 1K_0402_1%PXDP @
RH27 1K_0402_1%PXDP @
18P_040 2_50V8J
18P_040 2_50V8J
2
2
1U_0402 _6.3V6K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CH4
1 2
CH5
1 2
12
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17
1 2
PCH_RTCX1_R
RH38 0_0402_ 5%@
12
YH1
32.768K HZ_12.5PF_Q 13FC135000 0
PCH_AZ_CO DEC_SDIN0<30>
ME_FWP<45>
PXDP@
PXDP@
100_0402_1%
100_0402_1%
12
12
RH54
RH55
SIO_PW RBTN#_R<7,16>
DDR_XDP_W AN_SMBDAT<13,14,18,27 ,31>
DDR_XDP_W AN_SMBCLK<13,14,1 8,27,31>
PCH_RTCX1
12
RH39
10M_040 2_5%
PCH_RTCX2
SRTCRST#
INTRUDER#
PCH_INTVRMEN
PCH_RTCRST#
PCH_AZ_B ITCLK
PCH_AZ_S YNC
SPKR
SPKR<30>
PCH_AZ_RS T#
PCH_AZ_CO DEC_SDIN0
1 2
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
1 2
RH53 0_0402_ 5%@
T59 PAD~D@
PCH_AZ_S DOUT
PCH_GPIO 33
USB30_S MI#
RH45 1K_04 02_1%
USB30_S MI#<32,45>
PCH_TP25
PCH_JTAG_RS T
+3.3V_AL W_PCH
0.1U_0402_25V6
PXDP@
1
CH2
2
1 2
RH28 0_040 2_5%PXDP@
RH30 0_0402_ 5%PXDP@
1 2
1 2
RH31 0_0402_ 5%PXDP@
UH1A
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
DH82LPMS-QCG1-B0_FCBGA695~D
PCH_PW RBTN#_XDP
DDR_XDP_W AN_SMBDAT_ R2
DDR_XDP_W AN_SMBCLK _R2
DH82LPMS-QCG1-B0_FCBGA695~D
JTAGRTC AZALIA
1 OF 11
UH1 change PN to SA00005NE2L IC A31 DH82LPMS QCG1 B0 FCBGA 695P PCH
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
RSMRST#_XDP
SATA
+3.3V_AL W_PCH
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATA0GP/GPIO21
SATA1GP/GPIO19
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
SAMTE_BSH-0 30-01-L-D-A
SATALED#
SATA_IREF
TP9
TP8
PCH XDP
JXDP2
BC8
PSATA_PRX _DTX_N0_C
BE8
PSATA_PRX _DTX_P0_C
AW8
PSATA_PTX_ DRX_N0_C
AY8
PSATA_PTX_ DRX_P0_C
BC10
SATA_ODD_P RX_DTX_N1_C
BE10
SATA_ODD_P RX_DTX_P1_C
AV10
SATA_ODD_P TX_DRX_N1_C
AW10
SATA_ODD_P TX_DRX_P1_C
BB9
SATA_PRX_ DKTX_N2_C
BD9
SATA_PRX_ DKTX_P2_C
AY13
SATA_PTX_DK RX_N2_C
AW13
SATA_PTX_DK RX_P2_C
BC12
BE12
AR13
AT13
BD13
PCIE_SATA _PRX_WANTX _N4
BB13
PCIE_SATA _PRX_WANTX _P4
AV15
PCIE_SATA _PTX_WANRX _N4
AW15
PCIE_SATA _PTX_WANRX _P4
BC14
BE14
AP15
AR15
AY5
SATA_COMP
AP3
SATA_ACT#
AT1
HDD_DET#
AU2
BBS_BIT0_ R
BD4
SATA_IREF
BA2
BB2
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TRST#
GND17
CONN@
RH51 0_0402_ 5%@
T57PAD~D @
T58PAD~D @
TD0
TMS
SATA_ACT# <24>
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
2
4
XDP_FN16
6
XDP_FN17
8
10
XDP_FN8
12
XDP_FN9
14
16
XDP_FN10
18
XDP_FN11
20
22
24
26
28
XDP_FN12
30
XDP_FN13
32
34
XDP_FN14
36
XDP_FN15
38
40
42
44
46
RESET_OUT#_ R
48
XDP_DBRE SET#
50
52
PCH_JTAG_TDO
54
PCH_JTAG_RS T_R
56
PCH_JTAG_TDI
TDI
58
PCH_JTAG_TMSPCH_JTAG_TCK
60
BBS_BIT0_ R
PSATA_PRX _DTX_N0_C <31>
PSATA_PRX _DTX_P0_C <31>
PSATA_PTX_ DRX_N0_C <31>
PSATA_PTX_ DRX_P0_C <31>
SATA_ODD_P RX_DTX_N1_C <32>
SATA_ODD_P RX_DTX_P1_C <32>
SATA_ODD_P TX_DRX_N1_C <32>
SATA_ODD_P TX_DRX_P1_C <32>
SATA_PRX_ DKTX_N2_C <44>
SATA_PRX_ DKTX_P2_C <44>
SATA_PTX_DK RX_N2_C <44>
SATA_PTX_DK RX_P2_C <44>
PCIE_SATA _PRX_WANTX _N4 <38>
PCIE_SATA _PRX_WANTX _P4 <38>
PCIE_SATA _PTX_WANRX _N4 <38>
PCIE_SATA _PTX_WANRX _P4 <38>
HDD_DET# <15 ,17,31>
12
+1.5V_RUN
PCH_PLTRST#<7,1 6>
1 2
+1.05V_RU N
+3.3V_AL W_PCH
XDP_DBRE SET# <7,16>
1 2
RH32 0_0402_ 5%@
12
D
S
1 3
G
2
BSS138W -7-F_SOT323 -3~D
+1.5V_RUN
RH577.5K_04 02_1%
PCH_JTAG_RS T
+3.3V_RUN
RH374.7K_0 402_5%
HDD
ODD/ E Module B ay
DOCK
WWAN (JMINI1)
SATA by default
PCH_SATA_M OD_EN# <46>
QH2
+3.3V_AL W_PCH_JTAG
12
RH52
210_040 2_1%
12
PXDP@
RH56
100_040 2_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/9)
PCH (1/9)
PCH (1/9)
LA-9932P
LA-9932P
LA-9932P
1
15 71Thursday, July 04 , 2013
15 71Thursday, July 04 , 2013
15 71Thursday, July 04 , 2013
1.0
1.0
1.0
5
+PCH_VCCDS W3_3
1 2
RH92 10K_0402 _5%
RH80 10K_0402 _5%@
+3.3V_AL W_PCH
D D
C C
B B
A A
RH78 10K_0402 _5%@
RH73 10K_0402 _5%@
RH75 10K_0402 _5%
+3.3V_RUN
RH90 8.2K_0402 _5%
RH93 8.2K_0402 _5%@
RH120 100K_0402 _5%
+1.5V_RUN
+1.5V_RUN
SUSACK#<45>
SYS_PW ROK<7,45 >
RESET_OUT#<10,15,4 6>
PM_DRAM_P WRGD<7>
PCH_RSMRST# _Q<15,47>
ME_SUS_P WR_ACK<46>
SIO_PW RBTN#_R<7,15>
SIO_PW RBTN#<4 6>
AC_PRESE NT<46>
+PCH_VCCDS W3_3
DMI_CTX_PRX _N0<6>
DMI_CTX_PRX _N1<6>
DMI_CTX_PRX _N2<6>
DMI_CTX_PRX _N3<6>
DMI_CTX_PRX _P1<6>
DMI_CTX_PRX _P2<6>
DMI_CRX_P TX_N0<6 >
DMI_CRX_P TX_N1<6 >
DMI_CRX_P TX_N2<6 >
DMI_CRX_P TX_N3<6 >
DMI_CRX_P TX_P0<6>
DMI_CRX_P TX_P1<6>
DMI_CRX_P TX_P2<6>
DMI_CRX_P TX_P3<6>
PCH_PCIE_ WAKE#
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DMI_CTX_PRX _P0<6>
DMI_CTX_PRX _P3<6>
SIO_SLP _LAN#
PCH_PCIE_ WAKE#
SUS_STAT#/L PCPD#
ME_SUS_P WR_ACK
PCH_DPW ROK
RH98 0_0402_ 5%@
T65 PAD~D@
T67 PAD~D@
1 2
RH100 7.5K_04 02_1%
1 2
RH101 0_0402_5 %@
1 2
RH102 0_0402_5 %@
1 2
RH103 0_0402_5 %@
1 2
RH104 0_0402_5 %@
1 2
RH105 0_0402_5 %@
1 2
RH107 0_0402_5 %@
1 2
RH108 0_0402_5 %@
1 2
RH112 8.2K_04 02_5%
PCH_RI#<19>
T75 PAD~D@
SIO_SLP _WLAN#<45>
5
CLKRUN#
ME_RESET#
12
DMI_IREF
DMI_RCOMP
SUSACK#_ R
SYS_RESE T#
SYS_PW ROK_R
PCH_PW ROK
PM_APW ROK_R
PM_DRAM_P WRGD_R
PCH_RSMRST# _R
ME_SUS_P WR_ACK_R
SIO_PW RBTN#_R
PCH_BATLOW #
PCH_RI#
XDP_DBRE SET#<7,15>
UH1B
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
AY17
DMI_RCOMP
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPWRNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
12
RH70 8.2K_04 02_5%@
ME_SUS_P WR_ACK_R SUS ACK#_R
LPT_PCH_M_EDS
DMI
DH82LPMS-QCG1-B0_FCBGA695~D
ME_RESET#
PCH_DPW ROK PCH_RSMRST# _R
System Power
Management
4 OF 11
4
1 2
RH66 0_040 2_5%@
+3.3V_RUN
CH10
@
1 2
5
0.1U_040 2_25V6
1
P
B
4
O
2
A
G
UC3
@
74AHC1G0 9GW_TSSOP 5
3
1 2
RH79 0_0402_5 %@
1 2
1 2
FDI
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
BBS_BIT1
1K_0402_1%
12
@
RH119
4
SYS_PW ROKRESET_OUT#
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
TP16
TP15
TP10
FDI_CSYNC
FDI_INT
FDI_IREF
TP17
TP13
FDI_RCOMP
DSWVRMEN
DPWROK
WAKE#
CLKRUN#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
*
TP5
RH85 0_0402_5 %@
RH91 0_0402_5 %@
GPIO51 has internal pull up.
AJ35
AL35
AJ36
AL36
AV43
AY45
AV45
AW44
AL39
AL40
AT45
AU42
AU44
AR44
C8
L13
K3
AN7
U7
Y6
Y7
C6
H1
F3
F1
AY3
G5
SYS_RESE T#
FDI_RCOMP
PM_APW ROK<46>
FDI_CSYNC
FDI_INT
FDI_IREF
RH96 0_0402_ 5%@
DSWODV REN
PCH_DPW ROK
PCH_PCIE_ WAKE#
CLKRUN#
SUS_STAT#/L PCPD#
SUSCLK
SIO_SLP _S4#
SIO_SLP _S3#
SIO_SLP _A#
H_PM_SYNC
SIO_SLP _LAN#
SYS_RESE T# <35>
SIO_SLP _A#
PM_APW ROK
FDI_CTX_PRX _N0 <9>
FDI_CTX_PRX _N1 <9>
FDI_CTX_PRX _P0 <9>
FDI_CTX_PRX _P1 <9>
T62PAD ~D @
T63PAD ~D @
T60PAD ~D @
T61PAD ~D @
FDI_CSYNC <6>
FDI_INT <6>
12
+1.5V_RUN
T64PAD ~D @
T66PAD ~D @
12
+1.5V_RUN
RH997.5 K_0402_1%
PCH_DPW ROK <45>
PCH_PCIE_ WAKE# <46 >
CLKRUN# <35, 45,46>
SUS_STAT#/L PCPD# <35>
SIO_SLP _S5# <35,46>
SIO_SLP _S4# <35,45,5 8>
SIO_SLP _S3# <35,39,4 0,45,60,62 >
SIO_SLP _A# <35,45,59 >
SIO_SLP _SUS# <45>
H_PM_SYNC <7>
SIO_SLP _LAN# <39, 45>
T68PAD~D @
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
SATA_SLPD
(BBS_BIT0)
00 LPC
0 1 Reserved (NAND)
1 0
PCI
11 SPI
ESD Request
+3.3V_AL W2
5
1
IN B
VCC
OUT Y
2
IN A
GND
3
1 2
RH87 0_0402_5%@
3
SYS_RESE T#
CH11
@
1 2
0.1U_040 2_25V6
4
UH2
NL17SZ08 DFT2G_SC70-5
PCH_CRT_DDC_ CLK<25>
PCH_CRT_DDC_ DAT<25>
PCH_CRT_HSYNC<2 5>
PCH_CRT_VSYN C<25>
3
1
EMC@
C1554
0.047U_0 402_25V7 K
2
close PCH
PM_APW ROK_R
PCH_CRT_BLU<2 5>
PCH_CRT_GRN<25 >
PCH_CRT_RED<25>
1 2
RH94 20_0402_1%
1 2
RH95 20_0402_1%
1 2
RH97 649_0402_1%
BIA_PW M_PCH<27>
PANEL_B KEN_PCH<28>
ENVDD_PCH<45>
DGPU_HOL D_RST#<49>
CPPE#<3 7>
DGPU_PW R_EN#<5 3>
USB_MCARD1 _DET#<37>
RPH17
1 8
2 7
3 6
4 5
150_080 4_8P4R_1%
1 2
RH118 100K_0402 _5%
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+RTC_CELL
330K_0402_1%
RH67
1 2
DSWODV REN
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
330K_0402_1%
@
RH81
1 2
UH1E
ENVDD_PCH
PCI_PIRQA #
PCI_PIRQB #
PCI_PIRQC #
PCI_PIRQD #
BBS_BIT1
PCH_GPIO 55
T45
U44
V45
M43
M45
N42
N44
U40
U39
N36
K36
G36
H20
L20
K17
M20
A12
B13
C12
C10
A10
AL6
VGA_BLUE
VGA_GREEN
VGA_RED
VGA_DDC_CLK
VGA_DDC_DATA
VGA_HSYNC
VGA_VSYNC
DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO50
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_ CLK
PCH_CRT_DDC_ DAT
HSYNC
VSYNC
CRT_IREF
BIA_PW M_PCH
PANEL_B KEN_PCH
DGPU_PW R_EN#
DH82LPMS-QCG1-B0_FCBGA695~D
PCH_CRT_RED
PCH_CRT_GRN
PCH_CRT_BLU
ENVDD_PCH
2
A16 SWAP OVERRIDE STRAP
STP_A16OVR
LPT_PCH_M_EDS
LVDSCRT
PCI
5 OF 11
PCH_PLTRST#<7,1 5>
2
PCH_GPIO 55
1K_0402_1%
12
@
RH76
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DISPLAY
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPC_HPD
DDPD_HPD
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
PCH_PLTRST#
R40
R39
R35
R36
N40
N38
H45
K43
J42
H43
K45
J44
K40
K38
H39
G17
F17
L15
M15
AD10
Y11
1
2
FFS_PCH_I NT
PCH_PLTRST#
IN B
IN A
1
RPH4
1 8
2 7
3 6
4 5
8.2K_8P 4R_5%
RPH6
4 5
3 6
2 7
1 8
10K_8P4 R_5%
PCH_DDPB_ CTRLCLK <26>
PCH_DDPB_ CTRLDATA <26>
HDD_FALL_ INT <31>
12
12
12
12
12
PCH_PLTRST#_ EC <3 5,37,38,39 ,45,46>
PCH_GPIO 07<2 0>
PCH_DDPB_ CTRLCLK
PCH_DDPB_ CTRLDATA
PCH_DDPC_C TRLCLK <29>
PCH_DDPD_C TRLCLK <29>
DPC_PCH_DO CK_AUX# <29>
DPD_PCH_DO CK_AUX# <29>
DPC_PCH_DO CK_AUX <29>
DPD_PCH_DO CK_AUX <29>
HDMIB_PCH_ HPD <2 6>
DPC_PCH_DO CK_HPD <44>
DPD_PCH_DO CK_HPD <44>
LCD_CBL_ DET#
XFR_ID#
CAM_MIC_CB L_DET#
T71 PAD~D@
+3.3V_RUN
CH12
@
1 2
0.1U_040 2_25V6
UH3
5
NL17SZ08 DFT2G_SC70-5
VCC
4
OUT Y
GND
3
PCI_PIRQA #
PCI_PIRQB #
PCI_PIRQC #
PCI_PIRQD #
XFR_ID#
CAM_MIC_CB L_DET#
LCD_CBL_ DET#
PCH_CRT_DDC_ CLK
PCH_CRT_DDC_ DAT
DGPU_PW R_EN#
PCH_DDPB_ CTRLCLK
PCH_DDPB_ CTRLDATA
PCH_DDPC_C TRLDATA <29>
PCH_DDPD_C TRLDATA <29>
LCD_CBL_ DET# <2 8>
XFR_ID# < 43>
CAM_MIC_CB L_DET# <28>
12
RH1060 _0402_5% @
RH109 0_0402_5%@
RH110 0_0402_5%@
RH111 0_0402_5%@
RH113 0_0402_5%@
RH114 0_0402_5%@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (2/9)
PCH (2/9)
PCH (2/9)
LA-9932P
LA-9932P
LA-9932P
1
+3.3V_RUN
12
RH882 .2K_0402_ 5%
12
RH892 .2K_0402_ 5%
12
RH3288.2 K_0402_5%
12
RH2552.2 K_0402_5%
12
RH2562.2 K_0402_5%
PLTRST_USH# <35>
PLTRST_MMI# <36 >
PLTRST_LAN# <33>
PLTRST_EMB# <32 >
PLTRST_GPU# <49>
16 71Thursday, July 0 4, 2013
16 71Thursday, July 0 4, 2013
16 71Thursday, July 0 4, 2013
1.0
1.0
1.0
5
4
3
2
1
RPH20
+3.3V_RUN
D D
+3.3V_ALW_PCH
+PCH_VCCDSW3 _3
4 5
3 6
2 7
1 8
10K_8P4R_5%
4 5
3 6
2 7
1 8
10K_8P4R_5%
WWAN (Mini Card 1)--->
10/100/1G LAN --->
C C
PP (Mini Card 3)--->
Express card--->
WLAN (Mini Card 2)--->
eModule Bay--->
B B
PCIECLK REQ Pull UP Power Rail:
RPH21
MMI--->
MMICLK_REQ#
HDD_DET#
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD
MINI1CLK_REQ#
PCH_SMB_ALERT#
TEMP_ALERT#
PM_LANPHY_ENABLE
CLK_PCIE_MINI1#<38>
CLK_PCIE_MINI1<38>
MINI1CLK_REQ#<38>
CLK_PCIE_LAN#<33>
CLK_PCIE_LAN<33>
LANCLK_REQ#<15,33>
CLK_PCIE_MMI#<36>
CLK_PCIE_MMI<36>
MMICLK_REQ#<15,36>
CLK_PCIE_MINI3#<37>
CLK_PCIE_MINI3< 37>
MINI3CLK_REQ#<19,37>
CLK_PCIE_EXP#<39>
CLK_PCIE_EXP<39>
EXPCLK_REQ#<39>
CLK_PCIE_MINI2#<37>
CLK_PCIE_MINI2<37>
MINI2CLK_REQ#<37>
CLK_PCIE_EMB#<32>
CLK_PCIE_EMB<32>
EMBCLK_REQ#<32>
CLK_PCI_5048<45>
CLK_PCI_MEC<46>
CLK_PCI_DOCK<44>
CLK_PCI_LOOPBACK
HDD_DET# <15,31>
PCH_SMB_ALERT# <18>
TEMP_ALERT# <18,45>
PM_LANPHY_ENABLE <20,33>
RH158 22_0402_5%EMC@
RH160 22_0402_5%EMC@
RH162 22_0402_5%EMC@
RH164 22_0402_5%EMC@
USB_OC2#<15,19>
SIO_EXT_WAKE#<15,20,45>
USB_OC1#<15,19,42>
UH1C
Y43
CLKOUT_PCIE_N_0
Y45
CLKOUT_PCIE_P_0
AB1
PCIECLKRQ0#/GPIO73
AA44
CLKOUT_PCIE_N_1
AA42
CLKOUT_PCIE_P_1
LANCLK_REQ#
MMICLK_REQ#
MINI3CLK_REQ#
EXPCLK_REQ#
MINI2CLK_REQ#
PCIECLKRQ6#
EMBCLK_REQ#
12
12
12
12
PCI_5048
PCI_MEC
PCI_DOCK
PCI_LOOPBACKOUT
AF1
PCIECLKRQ1#/GPIO18
AB43
CLKOUT_PCIE_N_2
AB45
CLKOUT_PCIE_P_2
AF3
PCIECLKRQ2#/GPIO20/SMI#
AD43
CLKOUT_PCIE_N_3
AD45
CLKOUT_PCIE_P_3
T3
PCIECLKRQ3#/GPIO25
AF43
CLKOUT_PCIE_N_4
AF45
CLKOUT_PCIE_P_4
V3
PCIECLKRQ4#/GPIO26
AE44
CLKOUT_PCIE_N5
AE42
CLKOUT_PCIE_P_5
AA2
PCIECLKRQ5#/GPIO44
AB40
CLKOUT_PCIE_N_6
AB39
CLKOUT_PCIE_P_6
AE4
PCIECLKRQ6#/GPIO45
AJ44
CLKOUT_PCIE_N_7
AJ42
CLKOUT_PCIE_P_7
Y3
PCIECLKRQ7#/GPIO46
AH43
CLKOUT_ITPXDP
AH45
CLKOUT_ITPXDP_P
D44
CLKOUT_33MHZ0
E44
CLKOUT_33MHZ1
B42
CLKOUT_33MHZ2
F41
CLKOUT_33MHZ3
A40
CLKOUT_33MHZ4
LPT_PCH_M_EDS
CLOCK SIGNAL
2 OF 11
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI_P
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA_P
CLKIN_33MHZLOOPBACK
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
DIFFCLK_BIASREF
DH82LPMS-QCG1-B0_FCBGA695~D
CLKOUT_DMI
CLKOUT_DP
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_SATA
REFCLK14IN
XTAL25_IN
XTAL25_OUT
ICLK_IREF
TP19
TP18
USB_OC2#
PEG_B_CLKRQ#
MINI2CLK_REQ#
PCIECLKRQ6#
EMBCLK_REQ#
EXPCLK_REQ#
SIO_EXT_WAKE#
AB35
CLK_PCIE_VGA#
AB36
CLK_PCIE_VGA
AF6
GFX_CLK_REQ#MINI1CLK_REQ#
Y39
Y38
U4
PEG_B_CLKRQ#
AF39
CLK_CPU_DMI#
AF40
CLK_CPU_DMI
AJ40
CLK_CPU_SSC_DPLL#
AJ39
CLK_CPU_SSC_DPLL
AF35
CLK_CPU_DPLL#
AF36
CLK_CPU_DPLL
AY24
CLK_BUF_DMI#
AW24
CLK_BUF_DMI
AR24
CLK_BUF_BCLK#
AT24
CLK_BUF_BCLK
H33
CLK_BUF_DOT96#
G33
CLK_BUF_DOT96
BE6
CLK_BUF_CKSSCD#
BC6
CLK_BUF_CKSSCD
F45
CLK_PCH_14M
D17
CLK_PCI_LOOPBACK
AM43
XTAL25_IN
AL44
XTAL25_OUT
C40
PCI_TPM_TCM
F38
SIO_14M
F36
CLK_80H
F39
AM45
ICLK_IREF
AD39
AD38
AN44
PCH_CLK_BIASREF
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
CLK_PCI_DOCK
12
RH330
@
33_0402_5%
100P_0402_50V8J
1
@
CH76
2
+3.3V_ALW_PCH
RPH8
4 5
3 6
2 7
1 8
10K_8P4R_5%
+3.3V_ALW_PCH
RPH9
4 5
3 6
2 7
1 8
10K_8P4R_5%
CLK_PCIE_VGA# <49>
CLK_PCIE_VGA <49>
GFX_CLK_REQ# <50>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_CPU_SSC_DPLL# <7>
CLK_CPU_SSC_DPLL <7>
CLK_CPU_DPLL# <7>
CLK_CPU_DPLL <7>
EMC@
1 2
T76PAD~D @
T77PAD~D @
1 2
12
12
12
RH1657.5K_0402_1%
RH155 22_0402_5%
RH157 22_0402_5%
RH159 22_0402_5%
RH163 0_0402_5%@
+1.5V_RUN
+1.5V_RUN
RPH18
4 5
3 6
2 7
1 8
13
2
G
RPH5
4 5
3 6
2 7
1 8
10K_8P4R_5%
1 2
10K_8P4R_5%
GFX_CLK_REQ#
L2N7002WT1G_SC-70-3
D
QH3
S
IRQ_SERIRQ<18,35,45,46>
3.3V_RUN_GFX_ON<45>
CLK_BUF_BCLK#
CLK_BUF_BCLK
CLK_BUF_DMI#
CLK_BUF_DMI
CLK_PCH_14M
GFX_CLK_REQ#
LANCLK_REQ#
IRQ_SERIRQ
RH146 10K_0402_5%
CLOCK TERMINATION for FCIM and need close to PCH
12
1 2
RH152 0_0402_5%@
CLK_PCI_TPM <35>
CLK_SIO_14M <45>
PCLK_80H <37>
PCH_GPIO06<20>
CONTACTLESS_DET#<20,35>
CH13
RH153 1M_0402_5%
25MHZ 10PF +-20PPM 7V25000014
12P_0402_50V8J
2
1
CLK_BUF_DOT96#
CLK_BUF_DOT96
PCH_GPIO06
CONTACTLESS_DET#
3
4
YH2
OUT
GND
1
IN
2
GND
RPH19
4 5
3 6
2 7
1 8
10K_8P4R_5%
+3.3V_ALW_PCH
+3.3V_RUN
XTAL25_IN_R
12P_0402_50V8J
CH14
2
1
+3.3V_RUN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (3/9)
PCH (3/9)
PCH (3/9)
LA-9932P
LA-9932P
LA-9932P
17 71Thursday, July 04, 2013
17 71Thursday, July 04, 2013
17 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
Vinafix
D D
LPC_LAD0<35,37,45,46>
LPC_LAD1<35,37,45,46>
LPC_LAD2<35,37,45,46>
LPC_LAD3<35,37,45,46>
LPC_LFRAME#< 35,37,45,46>
PAD~D
T87
@
LPC_LDRQ1#<45>
IRQ_SERIRQ<17,35,45,46>
C C
+3.3V_SPI
1 2
1 2
1 2
1 2
SPI_PCH_DO2_64
SPI_PCH_DO3_64
SPI_PCH_DO2_32
SPI_PCH_DO3_32
SPI_PCH_CS0# SPI_PCH_CS0#_R
SPI_WP#_SEL<45>
SPI_WP#_SEL
RH180 0_0402_5%@
RPH11
SPI_PCH_DIN SPI_DIN64
SPI_PCH_DO2
SPI_PCH_DIN
SPI_PCH_DO2
SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_WP#_SEL
1 8
2 7
3 6
4 5
33_8P4R_5%
R3664 1K_0402_5%
B B
A A
R3668 1K_0402_5%
R3665 1K_0402_5%
R3666 1K_0402_5%
4
UH1D
A20
LAD_0
C20
LAD_1
A18
LAD_2
C18
LAD_3
B21
LFRAME#
1 2
12
SPI_PCH_DO2_64
SPI_DIN32
SPI_PCH_DO2_32
1 2
12
D21
G20
AL11
AJ11
AJ7
AL7
AJ10
AH1
AH3
AJ4
AJ2
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
LPC_LDRQ0#
IRQ_SERIRQ
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
R7 47_0402_5%
R936 47_0402_5%
RH186 0_0402_5%@
+3.3V_RUN
MEM_SMBCLK
MEM_SMBDATA
DMN66D0LDW-7_SOT363-6
LPT_PCH_M_EDS
SMBus
LPC
C-Link
SPI
Thermal
3 OF 11
6 1
5
DMN66D0LDW-7_SOT363-6
3
4
QH4B
SML1ALERT#/PCHHOT#/GPIO74
DH82LPMS-QCG1-B0_FCBGA695~D
200 MIL SO8
64Mb Flash ROM
U52
SPI_DIN64
SPI_PCH_DO2_64
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
SPI@
VCC
/HOLD(IO3)
CLK
DI(IO0)
200 MIL SO8
32Mb Flash ROM
U53
SPI_DIN32
SPI_PCH_DO2_32
1
/CS
2
DO/IO1
3
/WP/IO2
4
GND
W25Q32FVSSIQ_SO8
SPI@
VCC
/HOLD/IO3
CLK
DI/IO0
3
2
QH4A
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK
CL_DATA
CL_RST#
TD_IREF
+3.3V_SPI
0.1U_0402_25V6
8
7
6
SPI_CLK64
5
SPI_DO64
+3.3V_SPI
8
7
SPI_PCH_DO3_32
6
SPI_CLK32
5
SPI_DO32
DDR_XDP_WAN_ SMBCLK <13,14,15,27,31>
DDR_XDP_WAN_ SMBDAT <13,14,15,27,31>
N7
PCH_SMB_ALERT#
R10
MEM_SMBCLK
U11
MEM_SMBDATA
N8
DDR_HVREF_RST_PCH
U8
LAN_SMBCLK
R7
LAN_SMBDATA
H6
TEMP_ALERT#
K6
SML1_SMBCLK
N11
SML1_SMBDATA
AF11
PCH_CL_CLK1
AF10
PCH_CL_DATA1
AF7
PCH_CL_RST1#
BA45
TP1
BC45
TP2
BE43
TP4
BE44
TP3
AY43
PCH_TD_IREF
RH176 8.2K_0402_1%
C746
1 2
1 2
R3669 33_0402_5%
RPH7
1 8
SPI_DO64
SPI_CLK32
SPI_PCH_DO3_32
C1216
1 2
0.1U_0402_25V6
1 2
R901 33_0402_5%
2 7
3 6
4 5
33_8P4R_5%
SPI_PCH_DO
PCH_SMB_ALERT# <17>
T78PAD~D @
T79PAD~D @
T80PAD~D @
T81PAD~D @
1 2
2
DDR_HVREF_RST_PCH <7,13,14>
LAN_SMBCLK <33>
LAN_SMBDATA <33>
TEMP_ALERT# <17,45>
SML1_SMBCLK <46>
SML1_SMBDATA <46>
PCH_CL_CLK1 <37>
PCH_CL_DATA1 <37>
PCH_CL_RST1# <37>
SPI_PCH_DO3SPI_PCH_DO3_64
SPI_PCH_CLKSPI_CLK64
SPI_PCH_DO
SPI_PCH_CLK
SPI_PCH_DO3
+3.3V_SPI
DDR_HVREF_RST_PCH
SML1_SMBDATA
SML1_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
LAN_SMBCLK
LAN_SMBDATA
12
RH1770_0402_5% @
12
RH1780_0402_5% @
12
RH1790_0402_5% @
12
RH1810_0402_5% @
12
RH1820_0402_5% @
12
RH1830_0402_5% @
12
RH1840_0402_5% @
+3.3V_M
12
RH1850_0402_5% @
RPH12
1 8
2 7
3 6
4 5
2.2K_8P4R_5%
SPI_PCH_CS1#
PCH_SPI_CS1#
SPI_PCH_DO
PCH_SPI_DO
SPI_PCH_DIN
SPI_PCH_CS0#
PCH_SPI_CS0#
SPI_PCH_DO2
PCH_SPI_DO2
SPI_PCH_DO3
PCH_SPI_DO3
+3.3V_ALW_PCH
12
RH1701K_0402_1%
12
RH1742.2K_0402_5%
12
RH1752.2K_0402_5%
PCH_SPI_DIN
SPI_PCH_CLK
PCH_SPI_CLK
+3.3V_LAN
1
JSPI1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND1
22
GND2
TYCO_2-2041070-0
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (4/9)
PCH (4/9)
PCH (4/9)
LA-9932P
LA-9932P
LA-9932P
18 71Thursday, July 04, 2013
18 71Thursday, July 04, 2013
18 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
D D
4
3
2
1
UH1I
USB3RN3<44>
MLK DOCK ----->
10/100/1G LAN --->
WLAN (JMINI2)--->
C C
B B
E3 Module Bay--->
Pink Pather (JMINI3)--->
EXPRESS Card--->
MMI --->
USB3RP3<44>
USB3TN3<44>
USB3TP3<44>
PCIE_PRX_GLANTX_N2<33>
PCIE_PRX_GLANTX_P2<33>
PCIE_PTX_GLANRX_N2<33>
PCIE_PTX_GLANRX_P2<33>
PCIE_PRX_WLANTX_ N3<37>
PCIE_PRX_WLANTX_ P3<37>
PCIE_PTX_WLANRX_ N3<37>
PCIE_PTX_WLANRX_ P3<37>
PCIE_PRX_EMBTX_N4<32>
PCIE_PRX_EMBTX_P4< 32>
PCIE_PTX_EMBRX_N4<32>
PCIE_PTX_EMBRX_P4< 32>
PCIE_PRX_WPANTX _N6<37>
PCIE_PRX_WPANTX _P6<37>
PCIE_PTX_WPANRX _N6<37>
PCIE_PTX_WPANRX _P6< 37>
PCIE_PRX_EXPTX_N7<39>
PCIE_PRX_EXPTX_P7<39>
PCIE_PTX_EXPRX_N7<39>
PCIE_PTX_EXPRX_P7<39>
PCIE_PRX_MMITX_N8<36>
PCIE_PRX_MMITX_P8<36>
PCIE_PTX_MMIRX_N8<36>
PCIE_PTX_MMIRX_P8<36>
1 2
+1.5V_RUN
+1.5V_RUN
RH188 0_0402_5%@
1 2
RH192 7.5K_0402_1%
PCH_PCIE_IREF
T84 PAD~D@
T85 PAD~D@
PCH_PCIE_RCOMP
AW31
AY31
BE32
BC32
AT31
AR31
BD33
BB33
AW33
AY33
BE34
BC34
AT33
AR33
BE36
BC36
AW36
AV36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
BC30
BB29
BD29
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
PCIE_IREF
TP11
TP6
PCIE_RCOMP
LPT_PCH_M_EDS
PCIe
9 OF 11
B37
USB2N0
D37
USB2P0
A38
USB2N1
C38
USB2P1
A36
USB2N2
C36
USB2P2
A34
USB2N3
C34
USB2P3
B33
USB2N4
D33
USB2P4
F31
USB2N5
G31
USB2P5
K31
USB2N6
L31
USB2P6
G29
USB2N7
H29
USB2P7
A32
USB2N8
C32
USB2P8
A30
USB2N9
C30
USB2P9
B29
USB2N10
D29
USB2P10
A28
USB2N11
C28
USB2P11
G26
USB2N12
F26
USB
USB2P12
USB2N13
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
TP24
TP23
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
F24
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USBP0- <40>
USBP0+ <40>
USBP1- <41>
USBP1+ <41>
USBP2- <42>
USBP2+ <42>
USBP3- <44>
USBP3+ <44>
USBP4- <37>
USBP4+ <37>
USBP5- <38>
USBP5+ <38>
USBP6- <44>
USBP6+ <44>
USBP7- <35>
USBP7+ <35>
USBP8- <37>
USBP8+ <37>
USBP9- <43>
USBP9+ <43>
USBP10- <39>
USBP10+ <39>
USBP12- <28>
USBP12+ <28>
USBP13- <28>
USBP13+ <28>
USB3RN1 <40>
USB3RP1 <40>
USB3TN1 <40>
USB3TP1 <40>
USB3RN2 <41>
USB3RP2 <41>
USB3TN2 <41>
USB3TP2 <41>
USB3RN5 <42>
USB3RP5 <42>
USB3TN5 <42>
USB3TP5 <42>
USB3RN6 <43>
USB3RP6 <43>
USB3TN6 <43>
USB3TP6 <43>
T82PAD~D @
T83PAD~D @
USB_OC0# < 15,40,41,42>
USB_OC1# < 15,17,42>
USB_OC2# < 15,17>
USB_OC3# < 15>
USB_OC4# < 15,43>
USB_OC5# < 15>
USB_OC6# < 15>
SIO_EXT_SMI# <15,46>
----->Rear Side
----->Right Side Top
----->Right Side bottom
----->DOCK
----->WLAN/WIMAX
----->WWAN/UWB
----->DOCK
----->USH
----->WPAN
----->Left Side
----->Express Card
----->Camera
----->Touch
----->Rear Side
----->Right Side Top
----->Right Side bottom
----->Left Side
USBRBIAS
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
22.6_0402_1%
12
RH187
DH82LPMS-QCG1-B0_FCBGA695~D
RPH3
USB_OC5#
USB_OC3#
USB_OC0#
MINI3CLK_REQ#<17,37>
A A
MINI3CLK_REQ#
USB_OC4#
SIO_EXT_SMI#
USB_OC6#
PCH_RI#<16>
4 5
3 6
2 7
1 8
10K_8P4R_5%
RPH1
4 5
3 6
2 7
1 8
10K_8P4R_5%
+3.3V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (5/9)
PCH (5/9)
PCH (5/9)
LA-9932P
LA-9932P
LA-9932P
19 71Thursday, July 04, 2013
19 71Thursday, July 04, 2013
19 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
+PCH_VCCDSW3_3
RH216 10K_0402_5%
Support Deep S3 mode
12
EC_WAKE#
RH196 0_0402_5%@
1 2
4
LANWAKE# <33,46>
3
2
1
+3.3V_RUN
SIO_EXT_SCI#<46>
12
RPH16
10K_8P4R_5%
RPH13
10K_8P4R_5%
1 2
RPH15
10K_8P4R_5%
18
27
36
45
18
27
36
45
18
27
36
45
USH_DET#
PCH_GPIO22
PCH_GPIO35
TPM_ID0
SIO_EXT_SCI#
PCH_GPIO71
PCH_GPIO70
PCH_GPIO69
PCH_GPIO22
PCH_GPIO15
PCH_GPIO24
KB_DET#
DGPU_PWROK
RH202 100K_0402_5%
D D
C C
+3.3V_ALW_PCH
1 2
RH331 10K_0402_5%
RH332 100K_0402_5%@
USH_DET#<35>
PCH_GPIO06<17>
PCH_GPIO07<16>
SIO_EXT_WAKE#<15,17,45>
PM_LANPHY_ENABLE<17,33>
MCARD_PCIE_SATA#<15,45>
DGPU_PWROK<45,62>
PCH_GPIO22<35>
EC_WAKE#<46>
SLP_ME_CSW_DEV#<45>
PCH_GPIO35<15>
PCH_GPIO36<15>
PCH_GPIO37<15>
FFS_INT2<31>
PCH_GPIO49<15>
KB_DET#<47>
CONTACTLESS_DET#<17,35>
12
RH195 0_0402_5%@
USH_DET#
PCH_GPIO06
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
PCH_GPIO15
MCARD_PCIE_SATA#
DGPU_PWROK
PCH_GPIO22
PCH_GPIO24
EC_WAKE#
SLP_ME_CSW_DEV#
PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37
TPM_ID0
TPM_ID1
PCH_GPIO49
KB_DET#
CONTACTLESS_DET#
PCH_GPIO69
PCH_GPIO70
PCH_GPIO71
UH1F
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS
BE5
VSS
C45
VSS
A5
VSS
DH82LPMS-QCG1-B0_FCBGA695~D
+3.3V_ALW_PCH
4.7K_0402_5%
RH222
1 2
B B
SLP_ME_CSW_DEV#
1K_0402_1%
12
@
RH223
+3.3V_RUN
1 2
RH224 10K_0402_5%
RH225 10K_0402_5%
RH226 10K_0402_5%@
RH227 10K_0402_5%@
MCARD_PCIE_SATA#
12
PCH_GPIO49
12
MCARD_PCIE_SATA#
12
PCH_GPIO49
LPT_PCH_M_EDS
GPIO
NCTF
6 OF 11
CPU/Misc
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
TP14
PECI
+3.3V_RUN
RPH14
10K_8P4R_5%
+1.05V_RUN
1 8
2 7
3 6
4 5
TPM_ID1
PCH_GPIO34
SIO_A20GATE
SIO_RCIN#
AN10
SIO_A20GATE
AY1
AT6
SIO_RCIN#
AV3
H_CPUPWRGD
AV1
PCH_THRMTRIP#_R
AU4
CPU_PLTRST#
N10
VSS
A2
VSS
A41
VSS
A43
VSS
A44
VSS
B1
VSS
B2
VSS
B44
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CRB1.2 already change to GND d irectly at UH1 .A44, B45, BD1 pins
B45
BA1
BC1
BD1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
SIO_A20GATE <46>
T86PAD~D @
SIO_RCIN# <46>
H_CPUPWRGD <7>
CPU_PLTRST# <7>
RH206 56_0402_5%
0.1U_0402_25V6
1
CH17
2
12
PLL ON DIE VR ENABLE
ENABLED - HIGH(DEFAULT)
DISABLED - LOW
A A
USB X4,PCIEX8,SATAX6
*
Config
GPIO16,49
11
01USB X6,PCIEX8,SATAX4
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
+3.3V_RUN
RH228 1K_0402_1%@
1 2
RH229 1K_0402_1%
RH230 10K_0402_5%
RH231 10K_0402_5%@
12
12
12
PCH_GPIO36
PCH_GPIO37
PCH_GPIO36
PCH_GPIO37
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9)
PCH (6/9)
PCH (6/9)
LA-9932P
LA-9932P
LA-9932P
1
20 71Thursday, July 04, 2013
20 71Thursday, July 04, 2013
20 71Thursday, July 04, 2013
1.0
1.0
1.0
5
D D
4
3
LH1
12
1
2
0.01U_0402_16V7K
CH18
+VCCADAC
0.1U_0402_25V6
1
CH19
2
BLM18PG181SN1D_2P
10U_0603_6.3V6M
1
CH20
2
+1.5V_RUN
2
1
UH1G
+1.05V_RUN
1U_0402_6.3V6K
10U_0603_6.3V6M
1
CH21
2
C C
+1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
22U_0805_6.3V6M
1
2
1
1
CH24
CH23
CH22
2
2
+PCH_VCCDSW
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CH28
CH29
CH30
2
2
AA24
AA26
AD20
AD22
AD24
AD26
AD28
AE18
AE20
AE22
AE24
AE26
AG18
AG20
AG22
AG24
AA18
Y26
U14
U18
U20
U22
U24
V18
V20
V22
V24
Y18
Y20
Y22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DCPSUSBYP
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
VCCASW
DH82LPMS-QCG1-B0_FCBGA695~D
1 2
RH232 5.11_0402_1%
B B
1U_0402_6.3V6K
+PCH_VCCDSW_R
1
CH40
2
+PCH_VCCDSW
LPT_PCH_M_EDS
CRT DAC
HVCMOS
Core
PCIe/DMI
SATA
VCCMPHY
7 OF 11
USB3
PCH Power Rail Table
Voltage S0 Iccmax Current (A)
VCC 1.138 A
VCCIO 1.05V 3.629 A
VCCCLK 0.306 A1.05V
VCCVRM 0.183 A1.5V
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
VCCSPI 3.3V 0.022 A
1.05V
3.3V
VSS
VCCVRM
VCCIO
VCCIO
DCPSUS1
VCCSUS3_3
VCCSUS3_3
DCPSUS3
DCPSUS3
VCCIO
VCCVRM
VCCVRM
VCCVRM
VCCIO
VCCVRM
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
+3.3V_RUN
+1.05V_RUN
+1.5V_RUN
+1.5V_RUN
+1.05V_RUN
+1.5V_RUN
1U_0402_6.3V6K
1
CH34
2
+1.5V_RUN
+3.3V_ALW_PCH
1U_0402_6.3V6K
1
1
CH35
2
2
1U_0402_6.3V6K
CH36
+3.3V_RUN
1
2
+1.05V_RUN
1U_0402_6.3V6K
1
CH37
2
+1.05V_RUN
0.1U_0402_25V6
CH27
10U_0603_6.3V6M
1
2
Voltage Rail
1U_0402_6.3V6K
1
CH25
2
VCCADAC1_5 1.5V 0.070 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK3_3 0.055 A
VCCSUSHDA 3.3V 0.01 A
VCCSUS3_3 3.3V 0.261 A
CH38
VCCDSW3_3 3.3V 0.015 A
V_PROC_IO 1.05V 0.004 A
VCCADAC1_5
VCCADACBG3_3
FDI
VCC3_3_R30
VCC3_3_R32
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (7/9)
PCH (7/9)
PCH (7/9)
LA-9932P
LA-9932P
LA-9932P
21 71Thursday, July 04, 2013
21 71Thursday, July 04, 2013
21 71Thursday, July 04, 2013
1
1.0
1.0
1.0
5
4
3
2
1
Support DEEP SX: populated RH238, de-populated RH237
+3.3V_ALW_PCH
+3.3V_ALW_PCH
D D
C C
1
2
+1.05V_RUN
0.1U_0402_25V6
CH45
+1.05V_RUN
RH246 0_0603_5%@
0.1U_0402_25V6
+3.3V_RUN
1
CH47
2
1 2
0.1U_0402_25V6
+1.05V_RUN
CH48
1
2
1U_0402_6.3V6K
1
2
+PCH_VCC
+1.5V_RUN
CH50
10U_0603_6.3V6M
1
CH52
2
1U_0402_6.3V6K
10U_0603_6.3V6M
@
CH63
1
1
2
2
+PCH_VCC
+PCH_VCCCLK
+PCH_VCCCLK3_3
+PCH_VCCCLK
CH64
R24
VCCSUS3_3
R26
VCCSUS3_3
R28
VCCSUS3_3
U26
VCCSUS3_3
M24
VSS
U35
VCCUSBPLL
L24
VCC3_3
U30
VCCIO
V28
VCCIO
V30
VCCIO
Y30
VCCIO
Y35
DCPSUS2
AF34
VCCVRM
AP45
VCC
Y32
VCCCLK
M29
VCCCLK3_3
L29
VCCCLK3_3
L26
VCCCLK3_3
M26
VCCCLK3_3
U32
VCCCLK3_3
V32
VCCCLK3_3
AD34
VCCCLK
AA30
VCCCLK
AA32
VCCCLK
AD35
VCCCLK
AG30
VCCCLK
AG32
VCCCLK
AD36
VCCCLK
AE30
VCCCLK
AE32
VCCCLK
DH82LPMS-QCG1-B0_FCBGA695~D
UH1H
LPT_PCH_M_EDS
USB
ICC
8 OF 11
GPIO/LPC
RTC
Thermal
1
R20
VCCSUS3_3
R22
VCCSUS3_3
A16
VCC
VCC
AA14
AE14
AF12
AG14
U36
A26
K8
A6
P14
P16
AJ12
AJ14
AD12
P18
+PCH_VCCCFUSE
P20
L17
R18
AW40
AK30
AK32
+PCH_VCCDSW3_3
+PCH_VCCSST
CH46 0.1U_0402_25V6
+1.05V_RUN
+3.3V_VCCPRTCSUS
+PCH_DCPRTC
0.1U_0402_25V6
+VCCIO2PCH
+1.05V_M
+1.5V_RUN
VCCDSW3_3
DCPSST
VCC3_3
VCC3_3
VCC3_3
VCCIO
Azalia
CPU
SPI
VCCSUSHDA
VCCSUS3_3
VCCRTC
DCPRTC
DCPRTC
V_PROC_IO
V_PROC_IO
VCCSPI
VCCASW
VCCASW
VCCVRM
VCC3_3
VCC3_3
1 2
CH54
1 2
2
+3.3V_M
1
2
+3.3V_RUN
+PCH_VCCDSW3_3
0.1U_0402_25V6
CH43
0.1U_0402_25V6
1
CH55
2
1U_0402_6.3V6K
CH59
+RTC_CELL
0.1U_0402_25V6
1
2
0.1U_0402_25V6
CH44
1
2
1U_0402_6.3V6K
1
CH56
CH57
2
+3.3V_ALW_PCH
0.1U_0402_25V6
1
2
+3.3V_RUN
CH51
12
+3.3V_ALW_PCH
RH2370_0603_5% @
12
+3.3V_ALW
RH2380_0603_5% @
PCH Power Rail Table
0.1U_0402_25V6
1
CH49
2
Voltage Rail
VCC 1.138 A
VCCIO 1.05V 3.629 A
VCCADAC1_5 1.5V 0.070 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK 0.306 A1.05V
VCCCLK3_3 0.055 A
VCCVRM 0.183 A1.5V
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
Voltage S0 Iccmax Current (A)
1.05V
3.3V
VCCSUSHDA 3.3V 0.01 A
+VCCIO2PCH
0.1U_0402_25V6
0.1U_0402_25V6
1
0.1U_0402_25V6
1
CH65
2
CH60
2
1U_0402_6.3V6K
1
1
CH61
CH62
2
2
VCCSPI 3.3V 0.022 A
VCCSUS3_3 3.3V 0.261 A
VCCDSW3_3 3.3V 0.015 A
V_PROC_IO 1.05V 0.004 A
Place near pin AP45
+1.05V_RUN
1 2
RH244 0_0805_5%@
B B
+PCH_VCCCLK
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CH67
1U_0402_6.3V6K
@
CH68
1
2
1U_0402_6.3V6K
CH69
1
2
1U_0402_6.3V6K
CH71
CH70
1
1
2
2
+PCH_VCCCFUSE
1U_0402_6.3V6K
1
2
RH242 0_0805_5%@
CH66
12
+3.3V_RUN
+3.3V_RUN
RH245 0_0805_5%@
1 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
+PCH_VCCCLK3_3
1U_0402_6.3V6K
CH72
1
2
1U_0402_6.3V6K
CH73
1
2
1U_0402_6.3V6K
CH74
1
2
Place near pin AG30,AG32,AE30,AE32
1U_0402_6.3V6K
CH75
1
2
+3.3V_VCCPRTCSUS
1U_0402_6.3V6K
1
CH53
2
12
RH240 0_0603_5%@
12
RH241 0_0603_5%@
+3.3V_ALW_PCH
+3.3V_ALW
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (8/9)
PCH (8/9)
PCH (8/9)
LA-9932P
LA-9932P
LA-9932P
1
22 71Thursday, July 04, 2013
22 71Thursday, July 04, 2013
22 71Thursday, July 04, 2013
1.0
1.0
1.0
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