Dell Latitude E5520 Schematics

5

4

3

2

1

KRUG 15" UMA Block Diagram

XDP Debug

D D

DDR3 SODIMM (A)

DDR3 SODIMM (B)

MINI-CARD 3

Flash

PG 6

Dual Channel DDR3
1333MHz 1.5V

PG 14, 15

PCIE (#5)

PG 30

MINI-CARD 2

WLAN

C C

B B

Smart Card CONN

PG 33

PC MCIA

PG 31

MINI-CARD 1

WWAN

5 in 1 Conn

MS/MMC/SD

1394a

PG 32

PG 44

OZ600TJ0TN
OZ2522LN

Express CardTPS2231MRGPR

Smart Card
OZ77CR6LN

OZ600RJ1LN-B

PG 44PG 44

PCIE (#3)

PCIE (#3)
USB2.0 (#12)

USB2.0 (#12)

PCIE (#2)

USB2.0 (#4)

PCIE (#1)

USB2.0 (#13)

PCIE (#6)

PCIE (#3)

USB2.0 (#12)

(Option)

2.5" HDD Conn

PG 28

ODD

PG 28

DE351DLTR8

uBT

PG 28

PG 31

BIO Sensor

PG 38

TPM
AT97SC3204-X2A121-2

A A

(BTO)

5

SATA (#0)

SMBus

SATA (#1)

USB2.0 (#5)

USB2.0 (#10)

LPC

4

Sandy Bridge
(35W)

( rPGA 988 )

PG 2,3,4,5

FDI

Cougar Point

HM65

PG 7 ~ 13

LPC

SIO
MEC5055

PG 33

DMI

LVDS
PCH_VGA

PCH_DPB

PCH_DPC

PCH_DPD

PCIE (#7)

IHDA

USB2.0 (#1)

USB2.0 (#0)

USB2.0 (#3)

USB2.0 (#2)

SATA (#4)

USB2.0 (#11)

LPC

BC bus

BC bus

BC bus

PS/2

KBC Module & TP Module

SPI

Expander I/O
ECE5048

PG 34

Thermal
EMC4021

PG 39

KBC
ECE1177

PG 35

LAN

BCM5761

PG 40~42

MDC RJ11

HD Audio

92HD90B

PG 24

SPI ROM

4MBytes
2MBytes

PG 45

FAN

PG 39

Keyboard

Touch Pad

3

CRT MUX

MAX4885EETG+TCK2

LAN Switch

PI3L720ZHE

PG 43

Locate at I/O R

Locate at I/O L board

Speaker
MIC/HP Combo Jack

USB 2.0 x 1 CONN

USB 2.0 x 1 CONN

USB 2.0 x 1 CONN

eSATA /
USB 2.0 CONN

Camera

DMIC

PG 35

RJ-MAC

Locate at Audio/B

Locate at I/O R

PG 29

PG 29

PG 27

PG 26

Locate at I/O R

Locate at LED/BLocate at Media/B

2

DOCK_VGA

DOCK_DP1

DOCK_DP2

DOCK_LAN

Dock-I2S

USB2.0 (#8, #9)

SATA (#5)

D_LPC

Hall IC

LCD

PG 27

CRT

PG 27

Locate at I/O R

HDMI Conn

PG25

DC Jack BAT CONN

BATT CHARGER

REGULATOR (DC/DC)

+3.3V_ALW/+5V_ALW/+15V_ALW

Docking Power

RUN POWER SW

REGULATOR/LDO (DDR)

+1.5V_MEM/+0.75V_DDR_VTT

REGULATOR (PCH /CPU)

+1.05V_RUN/+1.8V_RUN

REGULATOR (CPU VR, 0.85V)

+VCC_CORE, +VCC_GFXCORE, +0.85V_RUN

PG 48

RTCLED

PG 36 PG 49

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

01 -- BLOCK DIAGRAM

01 -- BLOCK DIAGRAM

01 -- BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

Date: Sheet of

1

PG 57, 54

PG 53,56

of

169Wednesday, February 16, 2011

169Wednesday, February 16, 2011

169Wednesday, February 16, 2011

PG 50

PG 51

PG 59

PG 52

PG 60

PG 55

1A

1A

1A

5

PEG_RCOMPO (H22)

DMI_CRX_PTX_N0[7]
DMI_CRX_PTX_N1[7]
DMI_CRX_PTX_N2[7]
DMI_CRX_PTX_N3[7]

DMI_CRX_PTX_P0[7]
DMI_CRX_PTX_P1[7]
DMI_CRX_PTX_P2[7]
DMI_CRX_PTX_P3[7]

DMI_CTX_PRX_N0[7]
DMI_CTX_PRX_N1[7]
DMI_CTX_PRX_N2[7]
DMI_CTX_PRX_N3[7]

DMI_CTX_PRX_P0[7]
DMI_CTX_PRX_P1[7]
DMI_CTX_PRX_P2[7]
DMI_CTX_PRX_P3[7]

FDI_CTX_PRX_N0[7]
FDI_CTX_PRX_N1[7]
FDI_CTX_PRX_N2[7]
FDI_CTX_PRX_N3[7]
FDI_CTX_PRX_N4[7]
FDI_CTX_PRX_N5[7]
FDI_CTX_PRX_N6[7]
FDI_CTX_PRX_N7[7]

FDI_CTX_PRX_P0[7]
FDI_CTX_PRX_P1[7]
FDI_CTX_PRX_P2[7]
FDI_CTX_PRX_P3[7]
FDI_CTX_PRX_P4[7]
FDI_CTX_PRX_P5[7]
FDI_CTX_PRX_P6[7]
FDI_CTX_PRX_P7[7]

FDI_FSYNC0[7]
FDI_FSYNC1[7]

FDI_INT[7]

FDI_LSYNC0[7]
FDI_LSYNC1[7]

EDP_COMP

+/-1%

+/-1%

R_COMP place close to CPU

PEG_ICOMPI (J22)

PEG_ICOMPO (J21)

width 4 mils

width 12 mils

5

Trace length Max is 500 mils

D D

C C

+1.05V_RUN

R692 24.9

R692 24.9

Trace length Max is 500 mils

B B

eDP_COMPIO (A18)

A A

B27
B25
A25
B24

B28
B26
A24
B23

G21
E22
F21
D21

G22
D22
F20
C21

A21
H19
E19
F18
B21
C20
D18
E17

A22
G19
E20
G18
B20
C19
D19
F17

J18
J17

H20

J19
H17

A18
A17
B16

C15
D15

C17
F16
C16
G15

C18
E16
D16
F15

JCPU1A

JCPU1A

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

eDP_AUX
eDP_AUX#

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

CPU socket

CPU socket

R_COMPeDP_ICOMPO (A17)

R_COMP place close to CPU

width 4 mils

width 12 mils

VCC_IO

VCC_IO

R_COMP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]

DMI

DMI

PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]

Intel(R) FDI

Intel(R) FDI

PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

eDP

eDP

PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

Each FDI pipeline can be configured according to required display bandwidth
requirements. 1, 2, 3 or 4 Lanes may be used to transport frame data over the link.
Each Lane transports at a rate of 2.7 Gbps and uses ANSI 8b10b encoding.

DG(V0.7) P49: FDI Disable

FDI_TX[7:0] FDI_TX#[7:0] Can float on the processor.

FDI_FSYNC[0..1],FDI_LSYNC[0..1],FDI_INT

Can be tied to GND (through 1K ±5% resistors); In addition,‧

FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0],
FDI_LSYNC[1] can be ganged together with one resistor.

If left as no connect, there is no functional impact, but power‧

(~15 mW) may be wasted.

4

3

2

1

SANDY BRIDGE PROCESSOR HOST, PEG, Others

J22

PEG_COMP

J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

+1.05V_RUN

R323 24.9 +/-1%R323 24.9 +/-1%

1028: Add for ESdD solution

H_THERMTRIP#[39]

H_CPUPWRGD[6,11]

R278

R278

10K

10K

+/-5%

+/-5%

Avoid stub in the PWRGD path
while placing resistors R277 & R278

PCH_PLTRST#[8,9,11,30,31,32,33,34,46]

Should be kept minimal
(can be shorter than 0.125").

+3.3V_ALW_PCH

need to confirm component of AND gate and MOS

Follow DG SM_DRAMPWROK topology

4

RUNPWROK[33,34]

PM_DRAM_PWRGD[7]

RUN_ON_CPU1.5VS3#[60]

CPU_DETECT#[34]

H_PECI[11,33]

H_PROCHOT#[33,51,56]

R291 *0_NC_SHORT +/-5%R291 *0_NC_SHORT +/-5%

H_PM_SYNC[7]

R277 *0_NC_SHORT +/-5%R277 *0_NC_SHORT +/-5%

VCCPWRGOOD_0_R

+3.3V_RUN

53

2 4

1

C190 0.1uF 10V,X5RC190 0.1uF 10V,X5R

U17

U17

2

1

74AHC1G09GW

74AHC1G09GW

3 5

R364 *0_NC_SHORT +/-5%R364 *0_NC_SHORT +/-5%

C546

C546

*470pF_NC

*470pF_NC

50V,X7R

50V,X7R

R293 56+/-5%R293 56+/-5%

place R6,R7 near CPU

C450

C450

0.1uF

0.1uF

10V,X5R

10V,X5R

U36

U36

PCH_PLTRST#_BUF

NC

NC

74LVC1G07GW

74LVC1G07GW

4

3

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#_R

VCCPWRGOOD_0_R

PM_DRAM_PWRGD_CPU

PCH_PLTRST#_R

+1.05V_RUN

R670

R670
75

75

+/-1%

+/-1%

R672 43

R672 43

+1.5V_RUN+3.3V_ALW_PCH

D

G

S

R363

R363
200

200

+/-5%

+/-5%

R376 130 +/-5%R376 130 +/-5%R225 200 +/-5%R225 200 +/-5%

R372

R372
39

39

+/-5%

+/-5%

+/-1%

+/-1%

Q23

Q23
2N7002W-7-F

2N7002W-7-F

JCPU1B

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

CPU socket

CPU socket

PCH_PLTRST#_R

PM_DRAM_PWRGD_CPURUNPWROK_AND

R673

R673
*0_NC

*0_NC

+/-5%

+/-5%

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

+1.05V_RUN

R279 *56_NC

R279 *56_NC

+/-5%

+/-5%

R292 *49.9_NC

R292 *49.9_NC

+/-1%

+/-1%

R281 62

R281 62

+/-5%

+/-5%

For CPU S3 Power Reduce

DDR3_DRAMRST#[14,15]

2

BCLK#

PRDY#
PREQ#

TRST#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

DDR_HVREF_RST_PCH[5,10]

DDR_HVREF_RST_GATE[33]

BCLK

TCK
TMS

TDI

TDO

DBR#

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

A28

CPU_DMI

A27

CPU_DMI#

A16

DPLL_REF_SSCLK

A15

DPLL_REF_SSCLK#

R8

DDR3_DRAMRST#_CPU

AK1

SM_RCOMP0

A5

SM_RCOMP1

A4

SM_RCOMP2

AP29

XDP_PRDY#

AP27

XDP_PREQ#

AR26

XDP_TCLK

AR27

XDP_TMS

AP30

XDP_TRST#

AR28

XDP_TDI_R

AP26

XDP_TDO_R

AL35

XDP_DBRESET#_R

AT28

XDP_OBS0_R

AR29

XDP_OBS1_R

AR30

XDP_OBS2_R

AT30

XDP_OBS3_R

AP32

XDP_OBS4_R

AR31

XDP_OBS5_R

AT31

XDP_OBS6_R

AR32

XDP_OBS7_R

R713 1K +/-5%R713 1K +/-5%

R679 *0_NC_SHORT +/-5%R679 *0_NC_SHORT +/-5%
R681 *0_NC_SHORT +/-5%R681 *0_NC_SHORT +/-5%

CLK_CPU_DMI [10]
CLK_CPU_DMI# [10]

Max 500mils

XDP_PRDY# [6]
XDP_PREQ# [6]

XDP_TCLK [6]
XDP_TMS [6]
XDP_TRST# [6]

R682 *0_NC +/-5%R682 *0_NC +/-5%
R314 *0_NC +/-5%R314 *0_NC +/-5%

R662 *0_NC_SHORT +/-5%R662 *0_NC_SHORT +/-5%

R684 *0_NC +/-5%R684 *0_NC +/-5%
R678 *0_NC +/-5%R678 *0_NC +/-5%
R676 *0_NC +/-5%R676 *0_NC +/-5%
R677 *0_NC +/-5%R677 *0_NC +/-5%
R304 *0_NC +/-5%R304 *0_NC +/-5%
R674 *0_NC +/-5%R674 *0_NC +/-5%
R675 *0_NC +/-5%R675 *0_NC +/-5%
R273 *0_NC +/-5%R273 *0_NC +/-5%

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

XDP_TDI [6]
XDP_TDO [6]

XDP_DBRESET# [6,7]
XDP_OBS[0..7] [6]

Close to CPU

XDP_TMS
XDP_TDI_R
XDP_PREQ#
DPLL_REF_SSCLK#

XDP_TCLK
XDP_TRST#

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

DPLL_REF_SSCLK

+1.5V_MEM

R710 *0_NC +/-5%R710 *0_NC +/-5%

R711

R711
1K

1K

+/-5%

+/-5%

D S

R705 *0_NC_SHORT +/-5%R705 *0_NC_SHORT +/-5%

R706 *0_NC +/-5%R706 *0_NC +/-5%

Title

Title

Title

02 -- SNB (rPGA) 1/4 HOST, PEG

02 -- SNB (rPGA) 1/4 HOST, PEG

02 -- SNB (rPGA) 1/4 HOST, PEG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

Date: Sheet of

+1.05V_RUN

R686 51 +/-5%R686 51 +/-5%
R680 51 +/-5%R680 51 +/-5%
R308 *51_NC +/-1%R308 *51_NC +/-1%
R694 1K +/-5%R694 1K +/-5%

R688 51 +/-5%R688 51 +/-5%
R305 51 +/-5%R305 51 +/-5%

R392 140 +/-1%R392 140 +/-1%

R695 25.5+/-1%R695 25.5+/-1%

R696 200 +/-1%R696 200 +/-1%

R693 1K +/-5%R693 1K +/-5%

Q49

Q49
BSS138

BSS138

DDR3_DRAMRST#_CPU

G

R707

R707

4.99K

C495

C495

47nF

47nF

16V,X7R

16V,X7R

4.99K

+/-1%

+/-1%

Ever Light

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Ever Light
Technology Limited

Technology Limited

Technology Limited

269Wednesday, February 16, 2011

269Wednesday, February 16, 2011

269Wednesday, February 16, 2011

1

of

1A

1A

1A

5

4

3

2

1

D D

JCPU1C

JCPU1C

DDR_A_D[0..63][14]

C C

B B

DDR_A_BS0[14]
DDR_A_BS1[14]
DDR_A_BS2[14]

DDR_A_CAS#[14]
DDR_A_RAS#[14]
DDR_A_WE#[14]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

CPU socket

CPU socket

SA_CLK#[0]

SA_CLK#[1]

SA_CLK#[2]

SA_CLK#[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SANDY BRIDGE PROCESSOR (DDR3)

SA_CLK[0]

SA_CKE[0]

SA_CLK[1]

SA_CKE[1]

SA_CLK[2]

SA_CKE[2]

SA_CLK[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_CLK0 [14]
DDR_A_CLK#0 [14]
DDR_A_CKE0 [14]

DDR_A_CLK1 [14]
DDR_A_CLK#1 [14]
DDR_A_CKE1 [14]

DDR_A_CS#0 [14]
DDR_A_CS#1 [14]

DDR_A_ODT0 [14]
DDR_A_ODT1 [14]

DDR_A_DQS#[0..7] [14]

DDR_A_DQS[0..7] [14]

DDR_A_MA[0..15] [14]

JCPU1D

JCPU1D

AE2

SB_CLK[0]

DDR_B_D[0..63][15]

DDR_B_BS0[15]
DDR_B_BS1[15]
DDR_B_BS2[15]

DDR_B_CAS#[15]
DDR_B_RAS#[15]
DDR_B_WE#[15]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

CPU socket

CPU socket

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CLK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CLK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_CLK0 [15]
DDR_B_CLK#0 [15]
DDR_B_CKE0 [15]

DDR_B_CLK1 [15]
DDR_B_CLK#1 [15]
DDR_B_CKE1 [15]

DDR_B_CS#0 [15]
DDR_B_CS#1 [15]

DDR_B_ODT0 [15]
DDR_B_ODT1 [15]

DDR_B_DQS#[0..7] [15]

DDR_B_DQS[0..7] [15]

DDR_B_MA[0..15] [15]

A A

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

03 -- SNB (rPGA) 2/4 DDR

03 -- SNB (rPGA) 2/4 DDR

03 -- SNB (rPGA) 2/4 DDR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

369Wednesday, February 16, 2011

369Wednesday, February 16, 2011

369Wednesday, February 16, 2011

1A

1A

1A

5

SANDY BRIDGE PROCESSOR (POWER)

POWER

POWER

JCPU1F

VCCCORE = (SV) xxA max

D D

C C

B B

A A

JCPU1F

+VCC_CORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CPU socket

CPU socket

Power page :
470uF x 4
100nF x 2
EE page :
22uF x 14
10uF x 9

Intel DG :
470uF x 4 Bottom Socket Edge
22uF x 8 Top Socket Cavity
22uF x 8 Top Socket Edge
10uF x 10 Bottom Socket Cavity

CORE SUPPLY

CORE SUPPLY

+VCC_CORE

C213

C213

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C453

C453

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C212

C212

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C458

C458

10uF

10uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C199

C199

10uF

10uF

4V,X6S

4V,X6S

c0805h14

c0805h14

5

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30

PEG AND DDR

PEG AND DDR

VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE
VSSIO_SENSE

SENSE LINES SVID

SENSE LINES SVID

C455

C455

C197

C197

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C200

C200

C465

C465

*22uF_NC

*22uF_NC

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C227

C227

C201

C201

22uF

22uF

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C457

C457

C456

C456

10uF

10uF

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C228

C228

C466

C466

10uF

10uF

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

+1.05V_RUN

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

VIDALERT#
Connect one end of series-resistor 43±5% close to
processor and pull-up to VCCIO through 75±5% on
the other end of the series-resistor towards Intel MVP 7.

VIDSOUT

AJ29

H_CPU_SVIDALRT#

AJ30
AJ28

VIDSOUT

VIDSOUT:
Requires a pull-up to VCCIO through a pull-up resistor of
130 ±5% close to the processor, and a pull-up to VCCIO
through a pull-up resistor of 130 ±5% close to Intel MVP 7.
VIDSCLK:
Required pull-up to VCCIO through 55 ±5% close to Intel
IMVP 7.

18-mil witdh,and shoulde use differential
routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.

AJ35

VCCSENSE_R

R664 *0_NC_SHORT +/-5%R664 *0_NC_SHORT +/-5%

AJ34

VSSSENSE_R

R665 *0_NC_SHORT +/-5%R665 *0_NC_SHORT +/-5%

B10
A10

C454

C454

C452

C452

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C467

C467

C198

C198

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C217

C217

C211

C211

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C196

C196

C215

C215

10uF

10uF

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C195

C195

C214

C214

*10uF_NC

*10uF_NC

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

R280 130 +/-5%R280 130 +/-5%

Close to CPU

R294 43 +/-5%R294 43 +/-5%

C535

C535

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

c0805h14

c0805h14

C216

C216

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C536

C536

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

c0805h14

c0805h14

4

+1.05V_RUN

VIDALERT# [56]
VIDCLK [56]
VIDSOUT [56]

+VCC_CORE

VCC_SENSE & VSS_SENSE:

R663

R663

xxxxxx

100

100

100- ±1% pull-down to GND near processor

+/-1%

+/-1%

VCCSENSE [56]

VSSSENSE

VSSSENSE [56]

VCCIO_SENSE [57]
VSSIO_SENSE [57]

Voltage Rail Voltage

VCC

VCCIO

VAXG

VCCPLL

VDDQ

VCCSA

+1.5V_MEM

4

CPU Power Rail Table

0.65-1.3

1.05

0.0-1.1

1.8

1.5

0.65-0.9

1.5

* Description
5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT

3

SANDY BRIDGE PROCESSOR (GRAPHICS POWER)

+VCC_GFXCORE

26A

C237

C237

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C463

C463

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

VSSSENSE

S0 Iccmax
Current (A)

53

8.5

33

3

5

6

12-16 *

C234

C234

C472

C472

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C246

C246

C461

C461

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

Power page :
330uF x 2

0.1uF x 2
EE page :
22uF x 12

Intel DG :
470uF x 2 Bottom Socket Edge
22uF x 2 Top Socket Cavity
22uF x 4 Top Socket Edge
22uF x 2 Bottom Socket Cavity
22uF x 4 Bottom Socket Edge

+1.8V_RUN

3A

C249

C249
330uF

330uF

2.5V,<9mOhm

2.5V,<9mOhm

R666

R666
100

100

+/-1%

+/-1%

C245

C245

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C235

C235

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C470

C470

C459

C459

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C240

C240

C241

C241

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C487

C487

C486

C486

10uF

10uF

1uF

1uF

4V,X6S

4V,X6S

6.3V,X5R

6.3V,X5R

c0805h14

c0805h14

c0402h6

c0402h6

Power page :
22uF x 1

0.1uF x 1
EE page :
330uF x 1
10uF x 1
1uF x 2

Intel DG :
330uF x 1 Bottom Socket Edge
10uF x 1 Bottom Socket Edge
1uF x2 Bottom Socket Edge

C242

C242

C474

C474

22uF

22uF

22uF

22uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

C256

C256

C258

C258

*22uF_NC

*22uF_NC

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

4V,X6S

4V,X6S

Power page :
330uF x 2
10uF x 1
EE page :
330uF x 1, NC x 1
22uF x 12, NC x 7

Intel DG :
330uF x 2 near CPU
22uF x 5, NC x 5 Bottom Socket Cavity
22uF x 7, NC x 2 Top Socket Cavity
for 2012 capable designs
330 μF x3

3

C480

C480

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C483

C483

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

C471

C471

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C243

C243

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C485

C485

1uF

1uF

6.3V,X5R

6.3V,X5R

c0402h6

c0402h6

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

C479

C479

22uF

22uF

4V,X6S

4V,X6S

C257

C257

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

B6
A6
A2

C478

C478

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C482

C482

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

JCPU1G

JCPU1G

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCCPLL1
VCCPLL2
VCCPLL3

CPU socket

CPU socket

C477

C477

22uF

22uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C255

C255

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

POWER

POWER

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

VREFMISC

VREFMISC

GRAPHICS

GRAPHICS

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

1.8V RAIL

1.8V RAIL

+1.05V_RUN

C250

C250

C481

C481

C476

C476

22uF

22uF

22uF

22uF

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C226

C226

C484

C484

*330uF_NC

*330uF_NC

22uF

22uF

2V,<=9mOhm

2V,<=9mOhm

4V,X6S

4V,X6S

c0805h14

c0805h14

2

18-mil witdh,and shoulde use differential routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.

AK35
AK34

SM_VREF_RES

AL1

SM_VREF

AF7

VDDQ1

AF4

VDDQ2

AF1

VDDQ3

AC7

VDDQ4

AC4

VDDQ5

AC1

VDDQ6

Y7

VDDQ7

Y4

VDDQ8

Y1

VDDQ9

U7

VDDQ10

U4

VDDQ11

U1

VDDQ12

P7

VDDQ13

P4

VDDQ14

P1

VDDQ15

M27

VCCSA1

M26

VCCSA2

L26

VCCSA3

J26

VCCSA4

J25

VCCSA5

J24

VCCSA6

H26

VCCSA7

H25

VCCSA8

10mil .Spacing is 10mil

H23

C22

H_FC_C22

FC_C22

C24

VCCSA_VID1

VCCSA_VID1

C475

C475

*22uF_NC

*22uF_NC

4V,X6S

4V,X6S

C248

C248
330uF

330uF

2V,+/-20%

2V,+/-20%

2

VAXG_SENSE [56]
VSSAXG_SENSE [56]

+V_SM_VREF should
have 10 mil trace width

C497

C497

C254

C254

10uF

10uF

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

C498

C498
330uF

330uF

2V,+/-20%

2V,+/-20%

C236

C236

C229

C229

*10uF_NC

*10uF_NC

10uF

10uF

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

R687 *0_NC_SHORT +/-5%R687 *0_NC_SHORT +/-5%

VCCSA_SENSE [53]

R683 *0_NC_SHORT +/-5%R683 *0_NC_SHORT +/-5%

R689

R689
1K

1K

+/-5%

+/-5%

C252

C252

10uF

10uF

4V,X6S

4V,X6S

c0805h14

c0805h14

C449

C449

10uF

10uF

4V,X6S

4V,X6S

c0805h14

c0805h14

1

+0.75V_DDR_VTT

R703 *0_NC_SHORT +/-5%R703 *0_NC_SHORT +/-5%

+1.5V_RUN

5A

C251

C251

10uF

10uF

4V,X6S

4V,X6S

c0805h14

c0805h14

6A

C232

C232

*10uF_NC

*10uF_NC

4V,X6S

4V,X6S

R685

R685
1K

1K

+/-5%

+/-5%

Power page :

C253

C253

C496

C496

330uF x 2

*10uF_NC

*10uF_NC

10uF

10uF

10uF x 1

4V,X6S

4V,X6S

4V,X6S

4V,X6S

c0805h14

c0805h14

c0805h14

c0805h14

EE page :
330uF x 1
10uF x 5

Intel DG :
330uF x 1 Bottom Socket Edge
10uF x 6 Bottom Socket Edge

Power page :
330uF x 1

+0.85V_RUN

10uF x1
EE page :
10uF x 2, NC x 2

Intel DG :
330uF x 1 near CPU
10uF x 2 Bottom Socket Cavity
10uF x 1 Bottom Socket Edge

VCCSA_GND [53]

VCCSA_CNTRL1 [53]

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

04 -- SNB (rPGA) 3/4 POWER

04 -- SNB (rPGA) 3/4 POWER

04 -- SNB (rPGA) 3/4 POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet of

Date: Sheet of

Date: Sheet

1

SM_VREF_RES

C492

C492

*0.1uF_NC

*0.1uF_NC

10V,X5R

10V,X5R

C501 100nF 10V,Y5VC501 100nF 10V,Y5V

C499 100nF 10V,Y5VC499 100nF 10V,Y5V

C500 100nF 10V,Y5VC500 100nF 10V,Y5V

C502 100nF 10V,Y5VC502 100nF 10V,Y5V

+1.5V_RUN

469Wednesday, February 16, 2011

469Wednesday, February 16, 2011

469Wednesday, February 16, 2011

R702

R702
*1K_NC

*1K_NC

+/-1%

+/-1%

R704

R704
*1K_NC

*1K_NC

+/-1%

+/-1%

of

1A

1A

1A

5

4

3

2

1

D D

C C

B B

A A

SANDY BRIDGE PROCESSOR (GND)

JCPU1H

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7

AM4

AM3

AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7

AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

CPU socket

CPU socket

5

VSS

VSS

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH26

VSS97

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

AE27

VSS119

AE26

VSS120

AE9

VSS121

AD7

VSS122

AC9

VSS123

AC8

VSS124

AC6

VSS125

AC5

VSS126

AC3

VSS127

AC2

VSS128

AB35

VSS129

AB34

VSS130

AB33

VSS131

AB32

VSS132

AB31

VSS133

AB30

VSS134

AB29

VSS135

AB28

VSS136

AB27

VSS137

AB26

VSS138

Y9

VSS139

Y8

VSS140

Y6

VSS141

Y5

VSS142

Y3

VSS143

Y2

VSS144

W35

VSS145

W34

VSS146

W33

VSS147

W32

VSS148

W31

VSS149

W30

VSS150

W29

VSS151

W28

VSS152

W27

VSS153

W26

VSS154

U9

VSS155

U8

VSS156

U6

VSS157

U5

VSS158

U3

VSS159

U2

VSS160

M_VREF_DQ_A[14,16]

DDR_HVREF_RST_PCH[2,10]

M_VREF_DQ_B[15,16]

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

CPU socket

CPU socket

Q28

Q28
*2N7002W-7-F_NC

*2N7002W-7-F_NC

D S

D S

*2N7002W-7-F_NC

*2N7002W-7-F_NC
Q34

Q34

G

G

VSS

VSS

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

4

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24

+VCC_GFXCORE

E21
E18
E15
E13
E10
E9

+VCC_CORE

E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

CFG2
(PEG Static
Lane Reversal)

CFG4
(Display Port
Presence strap)

CFG7
(PEG Defer Training)

CFG[6:5]
(PCIe Port
Bifurcation Straps)

R317 *49.9_NC +/-1%R317 *49.9_NC+/-1%

R282 *49.9_NC +/-1%R282 *49.9_NC+/-1%

R295 *49.9_NC +/-1%R295 *49.9_NC+/-1%

R296 *49.9_NC +/-1%R296 *49.9_NC+/-1%

R697 *1K_NC +/-1%R697 *1K_NC +/-1%

R701 *1K_NC +/-1%R701 *1K_NC +/-1%

VCCIO_SEL(RSVD26):
For Huron River platforms,
this pin must be pulled high
on the motherboard.

Lan# definition matches
socket pin map definition

Disabled; No Physical Display Port
attached to Embedded Diplay Port

PEG Train immediately following
xxRESETB de assertion

11

x16 - Device 1 functions 1 and 2 disable

10

x8, x8 - Device 1 function 1 enable; function 2 disable

01

Reserved - (Device 1 function 1 disable; function 2 enable)

00

x8, x8, x4 - Device 1 function 1 and 2 enable

RSVD1

RSVD3

RSVD2

RSVD4

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

10mil .Spacing is 10mil

+3.3V_ALW

R690

R690
10K

10K

+/-5%

+/-5%

SANDY BRIDGE PROCESSOR( RESERVED, CFG)

CFG0

CFG0[6]

CFG1

CFG1[6]

CFG2

CFG2[6]

CFG3

CFG3[6]

CFG4

CFG4[6]

CFG5

CFG5[6]

CFG6

CFG6[6]

CFG7

CFG7[6]

CFG8

CFG8[6]

CFG9

CFG9[6]

CFG10

CFG10[6]

CFG11

CFG11[6]

CFG12

T72T72

CFG13

T69T69

CFG14

T81T81

CFG15

T75T75

CFG16

CFG16[6]

CFG17

CFG17[6]

RSVD1
RSVD2
RSVD3
RSVD4

T87T87

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

T71T71
T74T74
T90T90
T85T85
T73T73
T77T77
T86T86
T83T83
T79T79
T155T155
T157T157
T156T156
T80T80
T152T152
T158T158
T78T78

T89T89
T159T159

H_VCCP_SEL

T93T93

JCPU1E

JCPU1E

AK28
AK29
AL26
AL27
AK26
AL29

AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

AJ31
AH31

AJ33
AH33

AJ26

B4
D1

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

J20
B18
A19

J15

CPU socket

CPU socket

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

RSVD5

RSVD6
RSVD7

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD24
RSVD25
VCCIO_SEL

RSVD27

10

(Default Value)

(Default Value)

(Default Value)

Lan Reversed

Enabled; An external Display port
device is connected to the Embedded
Display port

PEG Wait for BIOS for training

(Default Value)

3

2

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RESERVED

RESERVED

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

KEY

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AH27

AN35
AM35

AT2
AT1
AR1

B1

T96T96
T98T98
T100T100
T101T101
T99T99

T84T84
T67T67
T82T82

T97T97
T88T88
T91T91
T92T92

T63T63
T62T62
T70T70
T65T65
T64T64

T149T149
T151T151
T150T150
T153T153
T154T154

T68T68
T66T66

T76T76

CLK_XDP_ITP [6]
CLK_XDP_ITP# [6]

T160T160
T161T161
T163T163

T162T162

CFG2

R315 *1K_NC +/-5%R315 *1K_NC +/-5%

CFG4

R318 *1K_NC +/-5%R318 *1K_NC +/-5%

CFG5

R309 *1K_NC +/-5%R309 *1K_NC +/-5%

CFG6

R275 *1K_NC +/-5%R275 *1K_NC +/-5%

CFG7

R276 *1K_NC +/-5%R276 *1K_NC +/-5%

Ever Light

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Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

05 -- SNB (rPGA) 4/4(GND)

05 -- SNB (rPGA) 4/4(GND)

05 -- SNB (rPGA) 4/4(GND)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

Date: Sheet of

1

of

569Wednesday, February 16, 2011

569Wednesday, February 16, 2011

569Wednesday, February 16, 2011

1A

1A

1A

5

4

3

2

1

R321 *0_NC+/-5%R321 *0_NC +/-5%

XDP_DBRESET#

XDP_DBRESET#

R320 *0_NC+/-5%R320 *0_NC +/-5%

PLTRST_XDP# [9]

PCH_RSMRST# [7,33]

XDP_DBRESET# [2,7]

PCH_JTAG_TDO [8]

PCH_JTAG_TDI [8]
PCH_JTAG_TMS [8]

CLK_XDP

R312 *0_NC +/-5%R312 *0_NC +/-5%

CLK_XDP#

CLK_XDP
CLK_XDP#

XDP_RST#_R

XDP_TDI
XDP_TMS

XDP_FN16
XDP_FN17

XDP_FN8
XDP_FN9

XDP_FN10
XDP_FN11

XDP_FN12
XDP_FN13

XDP_FN14
XDP_FN15

RSMRST#_XDP

PCH_JTAG_TDO

PCH_JTAG_TDI
PCH_JTAG_TMS

R311 *0_NC +/-5%R311 *0_NC +/-5%

1206: Change to NC

CFG16 [5]
CFG17 [5]

CFG0 [5]
CFG1 [5]

CFG2 [5]
CFG3 [5]

CFG8 [5]
CFG9 [5]

CFG4 [5]
CFG5 [5]

CFG6 [5]
CFG7 [5]

1206: Change to NC

R303 *1K_NC +/-5%R303 *1K_NC +/-5%

XDP_TRST# [2]
XDP_TDI [2]
XDP_TMS [2]

1206: Change to NC

R237 *1K_NC +/-5%R237 *1K_NC +/-5%

+1.05V_RUN

D D

C C

B B

C224

C224

C222

C222

0.1uF

0.1uF

0.1uF

0.1uF

10V,X5R

10V,X5R

10V,X5R

10V,X5R

+1.05V_RUN

C185

C185

0.1uF

0.1uF

10V,X5R

10V,X5R

MEM_XDP_HDD_SMBDAT[10,14,15,28,32]
MEM_XDP_HDD_SMBCLK[10,14,15,28,32]

XDP_TCLK[2]

1.05V_0.8V_PWROK[33,56]
SIO_PWRBTN#_R[7]

MEM_XDP_HDD_SMBDAT[10,14,15,28,32]
MEM_XDP_HDD_SMBCLK[10,14,15,28,32]

PCH_JTAG_TCK[8]

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

+3.3V_ALW_PCH +3.3V_ALW_PCH

H_CPUPWRGD[2,11]
SIO_PWRBTN#_R[7]

CFG0[5]
RESET_OUT#[7,33]

+3.3V_ALW

R287 *1K_NC +/-5%R287 *1K_NC +/-5%

XDP_PREQ#[2]
XDP_PRDY#[2]

XDP_OBS[0..7][2]

1206: Change to NC

R313 *1K_NC +/-5%R313 *1K_NC +/-5%
R307 *0_NC +/-5%R307 *0_NC +/-5%

R302 *1K_NC +/-5%R302 *1K_NC +/-5%
R286 *0_NC +/-5%R286 *0_NC +/-5%

R284 *0_NC +/-5%R284 *0_NC +/-5%
R285 *0_NC +/-5%R285 *0_NC +/-5%

1206: Change to NC

R106 *1K_NC +/-5%R106 *1K_NC +/-5%
R114 *0_NC +/-5%R114 *0_NC +/-5%

R113 *0_NC +/-5%R113 *0_NC +/-5%
R105 *0_NC +/-5%R105 *0_NC +/-5%

PCH_JTAG_TCK

RESET_OUT#_XDP

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

CFG10[5]
CFG11[5]

XDP_OBS4
XDP_OBS5

XDP_OBS6
XDP_OBS7

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

XDP_HOOK2
RESET_OUT#_XDP

XDP_HDD_SMBDAT_R1
XDP_HDD_SMBCLK_R1

1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP

XDP_HDD_SMBDAT_R2
XDP_HDD_SMBCLK_R2

XDP_FN0
XDP_FN1

XDP_FN2
XDP_FN3

XDP_FN4
XDP_FN5

XDP_FN6
XDP_FN7

CPU XDP

JXDP2

JXDP2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12
PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1
VCC_OBS_AB43VCC_OBS_CD

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

*Header_2X30_NC

*Header_2X30_NC

PCH XDP

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1

13

GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1

31

GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3

37

GND12
PWRGOOD/HOOK039ITPCLK/HOOK4

41

HOOK1
VCC_OBS_AB43VCC_OBS_CD

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

*Header_2X30_NC

*Header_2X30_NC

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK#/HOOK5

RESET#/HOOK6

DBR#/HOOK7

OBSFN_C0
OBSFN_C1

OBSFN_D0
OBSFN_D1

GND11

GND13

ITPCLK#/HOOK5

RESET#/HOOK6

DBR#/HOOK7

GND15

TRSTN

GND17

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TDO

54

TRSTN

56

TDI

58

TMS

60

GND17

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32
34
36
38
40
42
44
46
48
50
52

TDO

54
56

TDI

58

TMS

60

+1.05V_RUN

CLK_XDP_ITP [5]
CLK_XDP_ITP# [5]

CLK_CPU_ITP [10]
CLK_CPU_ITP# [10]

+3.3V_RUN

R300

R300
51

51

+/-5%

+/-5%

XDP_TDO

R301

R301
1K

1K

+/-1%

+/-1%

XDP_DBRESET# [2,7]

XDP_TDO [2]

USB_OC0#_R[9]
USB_OC1#_R[9]
USB_OC2#[9]
USB_OC3#[9]
USB_OC4#[9]
USB_OC5#[9]
USB_OC6#[9]
SIO_EXT_SMI_R#[9]
SLP_ME_CSW_DEV#[11,34]
USB_MCARD1_DET#[11,32]

HDD_DET#_R[8]
BBS_BIT0[8,9]
PCH_GPIO36[11]
FDI_OVRVLTG[11]
EN_ESATA_RPTR[11]

A A

5

4

TEMP_ALERT#[11,34]
PCH_GPIO15[11]
SIO_EXT_SCI#_R[11]

R112 *33_NC +/-5%R112 *33_NC +/-5%
R111 *33_NC +/-5%R111 *33_NC +/-5%
R110 *33_NC +/-5%R110 *33_NC +/-5%
R109 *33_NC +/-5%R109 *33_NC +/-5%
R108 *33_NC +/-5%R108 *33_NC +/-5%
R107 *33_NC +/-5%R107 *33_NC +/-5%
R116 *33_NC +/-5%R116 *33_NC +/-5%
R115 *33_NC +/-5%R115 *33_NC +/-5%
R235 *33_NC +/-5%R235 *33_NC +/-5%
R234 *33_NC +/-5%R234 *33_NC +/-5%

R239 *33_NC +/-5%R239 *33_NC +/-5%
R238 *33_NC +/-5%R238 *33_NC +/-5%
R233 *33_NC +/-5%R233 *33_NC +/-5%
R232 *33_NC +/-5%R232 *33_NC +/-5%
R231 *33_NC +/-5%R231 *33_NC +/-5%
R230 *33_NC +/-5%R230 *33_NC +/-5%
R240 *33_NC +/-5%R240 *33_NC +/-5%
R236 *33_NC +/-5%R236 *33_NC +/-5%

1206: Change to NC

XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9

XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

06 -- XDP Connector

06 -- XDP Connector

06 -- XDP Connector

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thunder 1A

Thunder 1A

Thunder 1A

Date: Sheet

Date: Sheet of

3

2

Date: Sheet of

1

of

669Wednesday, February 16, 2011

669Wednesday, February 16, 2011

669Wednesday, February 16, 2011

5

COUGAR POINT (DMI,FDI,GPIO)

D D

Width = 4 mil, Spacing = 20 mil
Close PCH within 500 mil

From EC

SYS_PWROK
This signal should be used on the platform to indicate

C C

that the processor VR power is good and therefore
it can be connected to the same source as PWROK on PCH.

Follow DG 0.9

B B

+3.3V_RUN

+3.3V_ALW_PCH

A A

SUSACK#[34]

SYS_PWROK[34]

RESET_OUT#[6,33]

PM_APWROK[33]

PM_DRAM_PWRGD[2] SIO_SLP_S5# [33]

PCH_RSMRST#[6,33]

ME_SUS_PWR_ACK[33]
SIO_PWRBTN#_R[6]

SIO_PWRBTN#[33]

AC_PRESENT[33]

R199 8.2K +/-1%R199 8.2K +/-1%

R180 *10K_NC +/-5%R180 *10K_NC +/-5%

R155 *10K_NC +/-5%R155 *10K_NC +/-5%

R147 10K +/-5%R147 10K +/-5%

R162 10K +/-5%R162 10K +/-5%

R211 10K +/-5%R211 10K +/-5%

R645 10K +/-5%R645 10K +/-5%

5

DMI_CTX_PRX_N0[2]
DMI_CTX_PRX_N1[2]
DMI_CTX_PRX_N2[2]
DMI_CTX_PRX_N3[2]

DMI_CTX_PRX_P0[2]
DMI_CTX_PRX_P1[2]
DMI_CTX_PRX_P2[2]
DMI_CTX_PRX_P3[2]

DMI_CRX_PTX_N0[2]
DMI_CRX_PTX_N1[2]
DMI_CRX_PTX_N2[2]
DMI_CRX_PTX_N3[2]

DMI_CRX_PTX_P0[2]
DMI_CRX_PTX_P1[2]
DMI_CRX_PTX_P2[2]
DMI_CRX_PTX_P3[2]

+1.05V_RUN

R652 *0_NC +/-5%R652 *0_NC +/-5%

XDP_DBRESET#[2,6]

R213 *0_NC+/-5%R213 *0_NC +/-5%

R197 *0_NC_SHORT +/-5%R197 *0_NC_SHORT +/-5%
R214 *0_NC_SHORT +/-5%R214 *0_NC_SHORT +/-5%
R198 *0_NC_SHORT +/-5%R198 *0_NC_SHORT +/-5%

R205 *0_NC+/-5%R205 *0_NC +/-5%

R646 *0_NC_SHORT +/-5%R646 *0_NC_SHORT +/-5%

R642 *0_NC_SHORT +/-5%R642 *0_NC_SHORT +/-5%

R650 *0_NC_SHORT +/-5%R650 *0_NC_SHORT +/-5%

R160 *0_NC_SHORT +/-5%R160 *0_NC_SHORT +/-5%

R181 8.2K +/-5%R181 8.2K+/-5%

+3.3V_ALW_PCH

R651 *0_NC_SHORT +/-5%R651 *0_NC_SHORT +/-5%

SUSACK# and SUSWARN# can be tied together
if EC does not want to involve in the
handshake mechanism for the Deep Sleep state entry and exit.

CLKRUN#

SUS_STAT#/LPCPD#

SIO_SLP_LAN#

PCH_PCIE_WAKE#

ME_SUS_PWR_ACK

PCH_RSMRST#

R639 49.9 +/-1%R639 49.9 +/-1%

R124 750 +/-1%R124 750 +/-1%

Deep Sleep not implemented
SUSACK# unconnected

PCH_RI#

DMI_COMP_R

RBIAS_CPY

SUSACK#_R

SYS_PWROK_R

PCH_PWROK

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

SIO_PWRBTN#_R

PCH_BATLOW#

PCH_RI#

SUSACK#_RME_SUS_PWR_ACK_R

4

U3C

U3C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

APWROK
This is a input signal to the PCH from power monitoring circuit to indicate that all Active
Sleep Well (ASW) rails, i.e. Intel ME sub-system and LAN power rails are stable on the
platform. Connect to ASW power rail monitoring circuit on motherboard. For platform
not supporting Intel AMT it can be connected to PWROK. The ASW power must be
stable for at least 1ms before platform logic asserts APWROK.

DPWROK
This is an input signal to the PCH from platform power monitoring logic to indicate that
all power rails associated with the PCH Deep Sx well (DSW) are valid and stable.
Connect to VccDSW3_3 power rail monitoring circuit on mother board for platforms
that support Deep Sx state. This signal can be tied to RSMRST# for platforms that do
not support the Deep Sx state. The DSW rails must be stable for at least 10ms before
DPWROK is asserted to PCH.

DMI

DMI

System Power Management

System Power Management

DSWODVREN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

R644 330K +/-5%R644 330K +/-5%

R643 *330K_NC +/-5%R643 *330K_NC +/-5%

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

CLKRUN#

G8

SUS_STAT#/LPCPD#

N14

SUSCLK

D10

SIO_SLP_S5#

H4

SIO_SLP_S4#

F4

SIO_SLP_S3#

G10

SIO_SLP_A#

G16

SIO_SLP_SUS#

AP14

K14

SIO_SLP_LAN#

DSWODVREN - On Die DSW VR Enable

Enabled (DEFAULT)
HIGH: R142 STUFFED,
R145 UNSTUFFED
Disabled
LOW: R142 STUFFED,
R145 UNSTUFFED

4

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT [2]

FDI_FSYNC0 [2]

FDI_FSYNC1 [2]

FDI_LSYNC0 [2]

FDI_LSYNC1 [2]

DSWODVREN

PCH_DPWROK

R641 *0_NC_SHORT +/-5%R641 *0_NC_SHORT +/-5%

PCH_PCIE_WAKE#

+RTC_CELL

3

FDI_CTX_PRX_N0 [2]
FDI_CTX_PRX_N1 [2]
FDI_CTX_PRX_N2 [2]
FDI_CTX_PRX_N3 [2]
FDI_CTX_PRX_N4 [2]
FDI_CTX_PRX_N5 [2]
FDI_CTX_PRX_N6 [2]
FDI_CTX_PRX_N7 [2]

FDI_CTX_PRX_P0 [2]
FDI_CTX_PRX_P1 [2]
FDI_CTX_PRX_P2 [2]
FDI_CTX_PRX_P3 [2]
FDI_CTX_PRX_P4 [2]
FDI_CTX_PRX_P5 [2]
FDI_CTX_PRX_P6 [2]
FDI_CTX_PRX_P7 [2]

Deep Sleep not implemented
DPWROK connect to RSMRST#

PCH_DPWROK [34]

PCH_RSMRST#_R

PCH_PCIE_WAKE# [34]

CLKRUN# [33,34,37,46]

T50T50

T36T36

T44T44

T47T47

SIO_SLP_S4# [34]

T56T56

SIO_SLP_S3# [34]

T39T39

SIO_SLP_A# [34]

T35T35

SIO_SLP_SUS# [34]

T54T54

H_PM_SYNC [2]

SIO_SLP_LAN# [34,40]

3

If the LVDS interface is not implemented,
all signals associated with the interface can
be left as No Connects

LCD_ACLK-_PCH[27]
LCD_ACLK+_PCH[27]

LCD_A0-_PCH[27]
LCD_A1-_PCH[27]
LCD_A2-_PCH[27]

LCD_A0+_PCH[27]
LCD_A1+_PCH[27]
LCD_A2+_PCH[27]

LCD_BCLK-_PCH[27]
LCD_BCLK+_PCH[27]

LCD_B0-_PCH[27]
LCD_B1-_PCH[27]
LCD_B2-_PCH[27]

LCD_B0+_PCH[27]
LCD_B1+_PCH[27]
LCD_B2+_PCH[27]

PCH_CRT_BLU[26]
PCH_CRT_GRN[26]
PCH_CRT_RED[26]

PCH_CRT_DDC_CLK[26]
PCH_CRT_DDC_DAT[26]

PCH_CRT_HSYNC[26]
PCH_CRT_VSYNC[26]

CRT_HSYNC and CRT_VSYNC resistor
33 ohm for Direct Connect
20 ohm for Dock Support
20 ohm for Switchable Graphics Device Down Topology
10 ohm for Switchable Graphics Dock Support

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

Put close PCH 500 mil

PANEL_BKEN_PCH[27]
ENVDD_PCH[27,34]

BIA_PWM_PCH[27]

LDDC_CLK_PCH[27]
LDDC_DATA_PCH[27]

R32 *2.2K_NC +/-5%R32 *2.2K_NC +/-5%

+3.3V_RUN

R47 *2.2K_NC +/-5%R47 *2.2K_NC +/-5%

R64 2.37K +/-1%R64 2.37K +/-1%

R66 1K +/-0.5%R66 1K +/-0.5%

R613 150 +/ -1%R613 150 +/ -1%
R612 150 +/ -1%R612 150 +/ -1%
R611 150 +/ -1%R611 150 +/ -1%

PANEL_BKEN_PCH

ENVDD_PCH

T5T5

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT

R615 20+/-1%R615 20+/-1%
R614 20+/-1%R614 20+/-1%

2

COUGAR POINT (LVDS,DDI)

U3D

U3D

J47

LVD_IBG
LVD_VBG

HSYNC
VSYNC

CRT_IREF

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
DOCK_DP1_PCH_CTRLDATA
DOCK_DP1_PCH_CTRLCLK
DOCK_DP2_PCH_CTRLDATA
DOCK_DP2_PCH_CTRLCLK

1

ENVDD_PCH

R53 100K +/-5%R53 100K +/-5%

PANEL_BKEN_PCH

R34 *100K_NC +/-5%R34 *100K_NC +/-5%

1231: Added for HDMI hot plug issue

HDM_HPD

C559 10nF 25V,X7RC559 10nF 25V,X7R

DOCK_DP1_HPD

R20 110K +/-5%R20 110K +/-5%

DOCK_DP2_HPD

AP43
AP45

AM42

SDVO_STALLN

AM40

SDVO_STALLP

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46

DOCK_DP1_PCH_CTRLCLK

P42

DOCK_DP1_PCH_CTRLDATA

AP47

DDPC_AUXN

AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

M43

DOCK_DP2_PCH_CTRLCLK

M36

DOCK_DP2_PCH_CTRLDATA

AT45

DDPD_AUXN

AT43

DDPD_AUXP

BH41

DDPD_HPD

BB43

DDPD_0N

BB45

DDPD_0P

BF44

DDPD_1N

BE44

DDPD_1P

BF42

DDPD_2N

BE42

DDPD_2P

BJ42

DDPD_3N

BG42

DDPD_3P

R33 2.2K+/-5%R33 2.2K +/-5%
R28 2.2K+/-5%R28 2.2K +/-5%
R31 2.2K+/-5%R31 2.2K +/-5%
R44 2.2K+/-5%R44 2.2K +/-5%
R18 2.2K+/-5%R18 2.2K +/-5%
R17 2.2K+/-5%R17 2.2K +/-5%

Title

Title

Title

07 -- CBT 1/6 (DMI&VIDEO)

07 -- CBT 1/6 (DMI&VIDEO)

07 -- CBT 1/6 (DMI&VIDEO)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

Date: Sheet of

R55 110K +/-5%R55 110K +/-5%

HDM_HPD

DOCK_DP1_HPD

DOCK_DP2_HPD

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

+3.3V_RUN

HDMI_TX2-_PCH [25]
HDMI_TX2+_PCH [25]
HDMI_TX1-_PCH [25]
HDMI_TX1+_PCH [25]
HDMI_TX0-_PCH [25]
HDMI_TX0+_PCH [25]
HDMI_CLK-_PCH [25]
HDMI_CLK+_PCH [25]

DOCK_DP1_PCH_CTRLCLK [48]
DOCK_DP1_PCH_CTRLDATA [48]

DOCK_DP1_PCH_AUX- [48]
DOCK_DP1_PCH_AUX+ [48]
DOCK_DP1_HPD [48]

DOCK_DP1_TX0- [48]
DOCK_DP1_TX0+ [48]
DOCK_DP1_TX1- [48]
DOCK_DP1_TX1+ [48]
DOCK_DP1_TX2- [48]
DOCK_DP1_TX2+ [48]
DOCK_DP1_TX3- [48]
DOCK_DP1_TX3+ [48]

DOCK_DP2_PCH_CTRLCLK [48]
DOCK_DP2_PCH_CTRLDATA [48]

DOCK_DP2_PCH_AUX- [48]
DOCK_DP2_PCH_AUX+ [48]

DOCK_DP2_TX0- [48]
DOCK_DP2_TX0+ [48]
DOCK_DP2_TX1- [48]
DOCK_DP2_TX1+ [48]
DOCK_DP2_TX2- [48]
DOCK_DP2_TX2+ [48]
DOCK_DP2_TX3- [48]
DOCK_DP2_TX3+ [48]

1

HDMI_CLK_PCH [25]
HDMI_DAT_PCH [25]

HDM_HPD [25]

DOCK_DP2_HPD [48]

of

769Wednesday, February 16, 2011

769Wednesday, February 16, 2011

769Wednesday, February 16, 2011

1A

1A

1A

5

D D

+3.3V_ALW_PCH

R636

R636
*1K_NC

*1K_NC

+/-5%

+/-5%

PCH_AZ_SDOUT

INTVRMEN :
Integrated 1.05 V VRM Enable / Disable.
Integrated 1.05 V VRMs is enabled when high
NOTE: This signal should always be pulled high

+RTC_CELL +3.3V_ALW_PCH

R648

R648
330K

330K

+/-5%

+/-5%

PCH_INTVRMEN PCH_AZ_SYNC

R647

R647
*330K_NC

*330K_NC

+/-5%

+/-5%

PLL ODVR VOLTAGE (HDA_SYNC have Internal PD 20k)

C C

B B

HIGH - SET VCCVRM TO 1.5 V

+3.3V_RUN

R89

R89

10K

10K

+/-5%

+/-5%

R768

R768
1M

1M

+/-5%

+/-5%

R633 33+/-5%R633 33+/-5%

R79 33+/-5%R79 33+/-5%

R78 33+/-5%R78 33+/-5%

R70 33+/-5%R70 33+/-5%

FDV301NQ7FDV301N

G

PCH_AZ_CODEC_SDOUT[24]

PCH_AZ_CODEC_SYNC[24]

PCH_AZ_CODEC_RST#[24]

PCH_AZ_CODEC_BITCLK[24]

C89

C89

*27pF_NC

*27pF_NC

50V,NPO

50V,NPO

Q7

PCH_AZ_SDOUT

PCH_AZ_SYNC_G

PCH_AZ_RST#

PCH_AZ_BITCLK

DS

PCH_AZ_SYNCPCH_AZ_SYNC_G

+5V_RUN

LOW - SET VCCVRM TO 1.8 V (DEFAULT)

HDA_SYNC

1214:Refer to Intel guide rev 1.5

PCH_AZ_SDOUT

5

R634 33+/-5%R634 33+/-5%

R73 33+/-5%R73 33+/-5%

R88 33+/-5%R88 33+/-5%

R69 33+/-5%R69 33+/-5%

C78

C78

*27pF_NC

*27pF_NC

50V,NPO

50V,NPO

PCH_AZ_SYNC_G

PCH_AZ_RST#

PCH_AZ_BITCLK

PCH_AZ_MDC_SDOUT[37]

PCH_AZ_MDC_SYNC[37]

A A

PCH_AZ_MDC_RST#[37]

PCH_AZ_MDC_BITCLK[37]

R87

R87
1K

1K

+/-5%

+/-5%

R77

R77
*100K_NC

*100K_NC

+/-5%

+/-5%

ME_FWP[34]

+3.3V_ALW_PCH

4

R358 1K +/-5%R358 1K +/-5%

R195 200 +/-5%R195 200 +/-5%

R183 200 +/-5%R183 200 +/-5%

R175 200 +/-5%R175 200 +/-5%

R178 51 +/-5%R178 51 +/-5%

R185 100 +/-5%R185 100 +/-5%

R184 100 +/-5%R184 100 +/-5%

R189 100 +/-5%R189 100 +/-5%

4

+RTC_CELL

R640 20K +/-5%R640 20K +/-5%

R95 20K +/-5%R95 20K +/-5%

Direct Connection to SPI ROM
Due to DELL E3 information

PCH_AZ_SDOUT

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

C446

C446

1uF

1uF

6.3V,X5R

6.3V,X5R

C131

C131

1uF

1uF

6.3V,X5R

6.3V,X5R

PCH_SPI_CLK[45]

PCH_SPI_CS0#[45]

PCH_SPI_CS1#[45]

PCH_SPI_DO[45]

PCH_SPI_DIN[45]

3

R129 *0_NC_SHORT +/-5%R129 *0_NC_SHORT +/-5%

C146 18pF 50V,NPOC146 18pF50V,NPO

2

Y2

Y2

112

+/-20ppm

+/-20ppm

32.768KHz

32.768KHz

334

4

C140 18pF50V,NPOC140 18pF50V,NPO

R637 1M +/-5%R637 1M +/-5%

SPKR[24]

PCH_AZ_CODEC_SDIN0[24]

PCH_AZ_MDC_SDIN1[37]

RTC_DET#[49]

USB_MCARD3_DET#[30]

PCH_JTAG_TCK[6]

PCH_JTAG_TMS[6]

PCH_JTAG_TDI[6]

PCH_JTAG_TDO[6]

T51T51

T58T58

T49T49

T48T48

R656 *0_NC_SHORT +/-5%R656 *0_NC_SHORT +/-5%

R208 *0_NC_SHORT +/-5%R208 *0_NC_SHORT +/-5%

R655 *0_NC_SHORT +/-5%R655 *0_NC_SHORT +/-5%

R209 *0_NC_SHORT +/-5%R209 *0_NC_SHORT +/-5%

R654 *0_NC_SHORT +/-5%R654 *0_NC_SHORT +/-5%

No series resistor required
if routing length is 1.5”-6.5” if using 1 SPI device

3

Cougar Point (HDA,JTAG,SATA)

R122

R122
10M

10M

+/-5%

+/-5%

PCH_RTCRST#

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_AZ_BITCLK

PCH_AZ_SYNC

SPKR

PCH_AZ_RST#

PCH_AZ_SDOUT

RTC_DET#

USB_MCARD3_DET#

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

PCH_SPI_CS1#_R

PCH_SPI_SI_R

PCH_SPI_SO_R

SPKR

Note1, Sampled at rising edge of PWROK
The signal has a weak internal pull-down.
(the internal pull-down is disabled after PLTRST# deasserts.)
If the signal is sampled high, this indicate that
the system is strapped to the "No Reboot" mode

PCH_RTCX1

PCH_RTCX2

No Reboot strap.

Low = Default.
High = No Reboot.

U3A

U3A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

IRQ_SERIRQ

SPKR

JTAG

JTAG

2

RTCIHDA

RTCIHDA

SPI

SPI

2

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

+3.3V_RUN

R251

R251
10K

10K

+/-5%

+/-5%

USB_MCARD3_DET#

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

R256

R256
*10K_NC

*10K_NC

+/-5%

+/-5%

IRQ_SERIRQ

SATA_ACT#

HDD_DET#_R

LPC_LAD0 [30,33,34,46]
LPC_LAD1 [30,33,34,46]
LPC_LAD2 [30,33,34,46]
LPC_LAD3 [30,33,34,46]

LPC_LFRAME# [30,33,34,46]

LPC_LDRQ0# [34]
LPC_LDRQ1# [34]

IRQ_SERIRQ [33,34,37,46]

PSATA_PRX_DTX_N0_C [28]
PSATA_PRX_DTX_P0_C [28]
PSATA_PTX_DRX_N0_C [28]
PSATA_PTX_DRX_P0_C [28]

SATA_ODD_PRX_DTX_N1_C [28]
SATA_ODD_PRX_DTX_P1_C [28]
SATA_ODD_PTX_DRX_N1_C [28]
SATA_ODD_PTX_DRX_P1_C [28]

ESATA_PRX_DTX_N4_C [29]
ESATA_PRX_DTX_P4_C [29]
ESATA_PTX_DRX_N4_C [29]
ESATA_PTX_DRX_P4_C [29]

SATA_PRX_DKTX_N5_C [48]
SATA_PRX_DKTX_P5_C [48]
SATA_PTX_DKRX_N5_C [48]
SATA_PTX_DKRX_P5_C [48]

SATA_COMP

R146 37.4 +/-1%R146 37.4 +/-1%

Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil

SATA3_COMP

R123 49.9 +/-1%R123 49.9 +/-1%

RBIAS_SATA3

R173 750 +/-1%R173 750 +/-1%

SATA_ACT# [36]

R171 *0_NC_SHORT +/-5%R171 *0_NC_SHORT +/-5%

R171
Maximum distance between resistor and PCH is 25.4mm.

BBS_BIT0 [6,9]

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

R90 100K +/-5%R90 100K +/-5%

HDD_DET#_R

R170 10K +/-5%R170 10K +/-5%

BBS_BIT0

R245 4.7K+/-5%R245 4.7K+/-5%

RTC_DET#

R72 10K +/-5%R72 10K +/-5%

SATA_ACT#

R243 10K +/-5%R243 10K +/-5%

ODD_DET#

R423 10K +/-5%R423 10K +/-5%

+1.05V_RUN

+1.05V_RUN

G

D S

Q15

Q15

2N7002W-7-F

2N7002W-7-F

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

08 -- CBT 2/6 (SATA, HDA, SPI)

08 -- CBT 2/6 (SATA, HDA, SPI)

08 -- CBT 2/6 (SATA, HDA, SPI)

KRUG 15" UMA

1

+3.3V_ALW_PCH

+3.3V_RUN

HDD

ODD

E-SATA

Docking

HDD_DET# [28]

HDD_DET#_R [6]

PCH_PLTRST# [2,9,11,30,31,32,33,34,46]

ODD_DET#

ODD_DET# [28]

of

869Wednesday, February 16, 2011

869Wednesday, February 16, 2011

869Wednesday, February 16, 2011

1

1A

1A

1A

5

4

3

2

1

Cougar Point (PCI,USB,NVRAM)

R244 *1K_NC +/-5%R244 *1K_NC +/-5%

R54 *1K_NC +/-5%R54 *1K_NC +/-5%

D D

Boot BIOS Strap

BBS_BIT[0]BBS_BIT[1]

00

0

1

0

1

11

C C

B B

C532

10pF

10pF

50V,NPO

50V,NPO

0823: EMI suggestion.Close to PCH.

+3.3V_RUN

R625 10K +/-5%R625 10K +/-5%
R622 10K +/-5%R622 10K +/-5%
R626 10K +/-5%R626 10K +/-5%
R50 10K +/-5%R50 10K +/-5%
R755 10K +/-5%R755 10K +/-5%

R62 8.2K +/-5%R62 8.2K +/-5%
R631 8.2K +/-5%R631 8.2K+/-5%
R627 8.2K +/-5%R627 8.2K+/-5%

A A

R63 8.2K +/-5%R63 8.2K +/-5%

R527 100K+/-5%R527 100K+/-5%

BBS_BIT0 [6,8]

BBS_BIT1

Boot BIOS Location

LPC

Reserved (NAND)

PCI

SPI

REQ# functionality is not available on Mobile

GNT# functionality is not available on Mobile

CLK_PCI0
CLK_PCI3
CLK_PCI4

C533

C533

C534

C534

10pF

10pF

10pF

10pF

50V,NPO

50V,NPO

50V,NPO

50V,NPO

LVDS_CBL_DET#

PCI_REQ1#

CAM_MIC_CBL_DET#

BT_DET#

PCH_GPIO3

1018: Add PU res R755 for PCH_GPIO3

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCIE_MCARD2_DET#

5

LVDS_CBL_DET#[27]

CAM_MIC_CBL_DET#[27]
HDD_FALL_INT[28]

PIRQ[H:E]# functionality is not available on Mobile

CLK_DEBUG[30]
CLK_PCI_5048[34]
CLK_PCI_MEC[33]
CLK_PCI_DOCK[48]
CLK_PCI_OZ[37]
CLK_PCI_LOOPBACK[10]

PLTRST_OZ600#[44]
PLTRST_XDP#[6]
PLTRST_LAN#[40]
PLTRST#_EXP[37]

R49 *1K_NC +/-1%R49 *1K_NC +/-1%

A16 swap override Strap/Top-Block
Swap Override jumper

Low = A16 swap
override/Top-Block

GNT3#

Swap Override enabled
High = Default

PCIE_MCARD2_DET#[31]
BT_DET#[31]

PCI_GNT3#

4

T23T23
T27T27
T25T25
T130T130
T129T129
T6T6
T7T7
T4T4
T1T1
T128T128
T20T20
T55T55
T45T45
T53T53
T52T52
T38T38
T29T29
T24T24
T3T3
T2T2

T127T127
T33T33
T43T43
T112T112

T12T12
T14T14
T10T10
T125T125
T22T22
T11T11
T9T9
T126T126
T31T31
T18T18
T15T15
T19T19
T30T30
T28T28
T21T21
T13T13

T164T164

R57 *0_NC_SHORT +/-5%R57 *0_NC_SHORT +/-5%

T59T59

PCH_PLTRST#[2,8,11,30,31,32,33,34,46]

R46 22+/-5%R46 22+/-5%
R43 22+/-5%R43 22+/-5%
R623 22+/-5%R623 22+/-5%
R607 22+/-5%R607 22+/-5%
R624 22+/-5%R624 22+/-5%
R45 22+/-5%R45 22+/-5%

R265 *0_NC_SHORT +/-5%R265 *0_NC_SHORT +/-5%
R266 *0_NC_SHORT +/-5%R266 *0_NC_SHORT +/-5%
R264 *0_NC_SHORT +/-5%R264 *0_NC_SHORT +/-5%
R263 *0_NC_SHORT +/-5%R263 *0_NC_SHORT +/-5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ1#
PCIE_MCARD2_DET#
BT_DET#

BBS_BIT1

PCI_GNT3#

LVDS_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#

FFS_PCH_INT

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

PCH_PLTRST#_1

AW30

C186 47nF

C186 47nF

4

74AHC1G08GW

74AHC1G08GW

U3E

U3E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39
TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

+3.3V_RUN

Add Buffers as needed for
Loading and fanout concerns.

16V,X7R

16V,X7R

U16

U16

2

1

3 5

RSVD

RSVD

PCI

PCI

PCH_PLTRST#

3

USB

USB

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

C33

USBRBIAS

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

R635 22.6+/-1%R635 22.6+/-1%

Net USB_BIAS route impedacnes should be 50-ohm

B33

and length less than 500-mil spacing is 15-mil.

A14
K20
B17
C16
L16
A16
D14
C14

R137 *0_NC_SHORT +/-5%R137 *0_NC_SHORT +/-5%

USB_OC1#_R

R132 *0_NC_SHORT +/-5%R132 *0_NC_SHORT +/-5%

R224 *0_NC_SHORT +/-5%R224 *0_NC_SHORT +/-5%C532

R132,R137,R224

Maximum distance between resistor and PCH is 25.4mm.

USBP0- [37]
USBP0+ [37]
USBP1- [37]
USBP1+ [37]
USBP2- [29]
USBP2+ [29]
USBP3- [29]
USBP3+ [29]
USBP4- [31]
USBP4+ [31]
USBP5- [31]
USBP5+ [31]

USBP8- [48]
USBP8+ [48]
USBP9- [48]
USBP9+ [48]
USBP10- [38]
USBP10+ [38]
USBP11- [27]
USBP11+ [27]
USBP12- [37]
USBP12+ [37]
USBP13- [32]
USBP13+ [32]

USB_OC0#USB_OC0#_R
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#

USB_OC0#_R [6]
USB_OC1#_R [6]

SIO_EXT_SMI_R# [6]

2

Right Side pair top

Right Side pair bottom(Debug)

Left Side Top

Left Side Bottom

WLAN

Blue Tooth

DOCK

DOCK

BIO

Camera

BTO

Express Card or Smart Card

WWAN

USB_OC0# [29,37]
USB_OC1# [29]
USB_OC2# [6]
USB_OC3# [6]
USB_OC4# [6]
USB_OC5# [6]
USB_OC6# [6]
SIO_EXT_SMI# [33]

+3.3V_ALW_PCH

RN2

RN2

USB_OC0#

1

USB_OC1#
USB_OC3#
USB_OC4#

USB_OC5#
USB_OC6#
SIO_EXT_SMI#
USB_OC2#

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

2

3

4

5

6

7 8

10K

10K

+/-5%

+/-5%

RN1

RN1

1

2

3

4

5

6

7 8

10K

10K

+/-5%

+/-5%

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

09 -- CBT 3/6 (USB, PCI, NVRAM)

09 -- CBT 3/6 (USB, PCI, NVRAM)

09 -- CBT 3/6 (USB, PCI, NVRAM)

KRUG 15" UMA

1

of

969Wednesday, February 16, 2011

969Wednesday, February 16, 2011

969Wednesday, February 16, 2011

1A

1A

1A

5

PCIE_PRX_WANTX_N1[32]

2nd Mini Card WWAN

D D

1st Mini Card WLAN

Option(Express Card/PCMCIA)

3rd Mini-Card

Card Reader

LAN

1st Mini Card WWAN

C C

LAN

Card Reader

3rd Mini-Card

Option(Express Card/PCMCIA)

2nd Mini Card WLAN

B B

PCIE_PRX_WANTX_P1[32]
PCIE_PTX_WANRX_N1_C[32]
PCIE_PTX_WANRX_P1_C[32]

PCIE_PRX_WLANTX_N2[31]
PCIE_PRX_WLANTX_P2[31]
PCIE_PTX_WLANRX_N2_C[31]
PCIE_PTX_WLANRX_P2_C[31]

PCIE_PRX_EXPTX_N3[37]
PCIE_PRX_EXPTX_P3[37]
PCIE_PTX_EXPRX_N3_C[37]
PCIE_PTX_EXPRX_P3_C[37]

PCIE_PRX_CARDTX_N5[30]
PCIE_PRX_CARDTX_P5[30]
PCIE_PTX_CARDRX_N5_C[30]
PCIE_PTX_CARDRX_P5_C[30]

PCIE_PRX_CARDTX_N6[44]
PCIE_PRX_CARDTX_P6[44]
PCIE_PTX_CARDRX_N6_C[44]
PCIE_PTX_CARDRX_P6_C[44]

PCIE_PRX_GLANTX_N7[40]
PCIE_PRX_GLANTX_P7[40]
PCIE_PTX_GLANRX_N7_C[40]
PCIE_PTX_GLANRX_P7_C[40]

CLK_PCIE_MINI1#[32]
CLK_PCIE_MINI1[32]

+3.3V_ALW_PCH

MINI1CLK_REQ#[32]

CLK_PCIE_LAN#[40]
CLK_PCIE_LAN[40]

+3.3V_RUN

LANCLK_REQ#[40]

CLK_PCIE_CARD#[44]
CLK_PCIE_CARD[44]

+3.3V_RUN

MMICLK_REQ#[44]

CLK_PCIE_MINI3#[30]
CLK_PCIE_MINI3[30]

+3.3V_ALW_PCH

MINI3CLK_REQ#[30]

CLK_PCIE_EXP#[37]
CLK_PCIE_EXP[37]

+3.3V_ALW_PCH

EXPCLK_REQ#[37]

CLK_PCIE_MINI2#[31]
CLK_PCIE_MINI2[31]

+3.3V_ALW_PCH

MINI2CLK_REQ#[31]

CLK_CPU_ITP#[6]
CLK_CPU_ITP[6]

4

Place TX DC blocking caps close PCH.

C102 0.1uF 16V,X7RC102 0.1uF 16V,X7R
C110 0.1uF 16V,X7RC110 0.1uF 16V,X7R

C99 0.1uF 16V,X7RC99 0.1uF 16V,X7R
C94 0.1uF 16V,X7RC94 0.1uF 16V,X7R

C95 0.1uF 16V,X7RC95 0.1uF 16V,X7R
C87 0.1uF 16V,X7RC87 0.1uF 16V,X7R

C79 0.1uF 16V,X7RC79 0.1uF 16V,X7R
C84 0.1uF 16V,X7RC84 0.1uF 16V,X7R

C72 0.1uF 16V,X7RC72 0.1uF 16V,X7R
C77 0.1uF 16V,X7RC77 0.1uF 16V,X7R

C64 0.1uF 16V,X7RC64 0.1uF 16V,X7R
C63 0.1uF 16V,X7RC63 0.1uF 16V,X7R

R41 *0_NC_SHORT +/-5%R41 *0_NC_SHORT +/-5%
R42 *0_NC_SHORT +/-5%R42 *0_NC_SHORT +/-5%
R179 10K +/-5%R179 10K +/-5%

R618 *0_NC_SHORT +/-5%R618 *0_NC_SHORT +/-5%
R617 *0_NC_SHORT +/-5%R617 *0_NC_SHORT +/-5%
R201 10K +/-5%R201 10K +/-5%

R610 *0_NC_SHORT +/-5%R610 *0_NC_SHORT +/-5%
R609 *0_NC_SHORT +/-5%R609 *0_NC_SHORT +/-5%
R250 10K +/-5%R250 10K +/-5%

R40 *0_NC_SHORT +/-5%R40 *0_NC_SHORT +/-5%
R39 *0_NC_SHORT +/-5%R39 *0_NC_SHORT +/-5%
R149 10K +/-5%R149 10K +/-5%

R35 *0_NC_SHORT +/-5%R35 *0_NC_SHORT +/-5%
R36 *0_NC_SHORT +/-5%R36 *0_NC_SHORT +/-5%
R165 10K +/-5%R165 10K +/-5%

R37 *0_NC_SHORT +/-5%R37 *0_NC_SHORT +/-5%
R38 *0_NC_SHORT +/-5%R38 *0_NC_SHORT +/-5%
R247 10K +/-5%R247 10K +/-5%

R193 *0_NC_SHORT +/-5%R193 *0_NC_SHORT +/-5%
R194 *0_NC_SHORT +/-5%R194 *0_NC_SHORT +/-5%

PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1

PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

PCIE_PTX_CARDRX_N5
PCIE_PTX_CARDRX_P5

PCIE_PTX_CARDRX_N6
PCIE_PTX_CARDRX_P6

PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7

CLK_PCIE_MINI1#_C
CLK_PCIE_MINI1_C

CLK_PCIE_LAN#_C
CLK_PCIE_LAN_C

CLK_PCIE_CARD#_C
CLK_PCIE_CARD_C

CLK_PCIE_MINI3#_C
CLK_PCIE_MINI3_C

CLK_PCIE_EXP#_C
CLK_PCIE_EXP_C

CLK_PCIE_MINI2#_C
CLK_PCIE_MINI2_C

PEG_B_CLKRQ#

PCIECLKRQ6#

PCIECLKRQ7#

CLK_BCLK_ITP#
CLK_BCLK_ITP

3

Cougar Point (PCI-E,SMBUS,CLK)

U3B

U3B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

PCI-E*

PCI-E*

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLOCKS

CLOCKS

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

E12

PCH_SMB_ALERT#

H14

PCH_SMBCLK

C9

PCH_SMBDAT

A12

DDR_HVREF_RST_PCH

C8

SML0_SMBCLK

G12

SML0_SMBDATA

C13

GPIO74

E14

SML1_SMBCLK

M16

SML1_SMBDAT

M7

T11

P10

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLKOUTFLEX0

F47

H47

CLKOUTFLEX2

K49

CLKOUTFLEX3

PEG_A_CLKRQ#

CLK_BUF_EXP#
CLK_BUF_EXP

CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

R619 90.9+/-1%R619 90.9+/-1%

Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil

DDR_HVREF_RST_PCH [2,5]

T42T42

SML1_SMBCLK [33]

SML1_SMBDAT [33]

CLK_CPU_DMI# [2]
CLK_CPU_DMI [2]

CLK_PCI_LOOPBACK [9]

+1.05V_RUN

R52 22+/-5%R52 22+/-5%

R48 33+/-5%R48 33+/-5%

R608 22+/-5%R608 22+/-5%

R616 *22_NC +/-5%R616 *22_NC +/-5%

2

PCH_SMB_ALERT#
PCH_SMBCLK
PCH_SMBDAT
GPIO74
DDR_HVREF_RST_PCH
SML1_SMBCLK
SML1_SMBDAT

PEG_B_CLKRQ#
PEG_A_CLKRQ#

PCIECLKRQ6#

SML0_SMBCLK
SML0_SMBDATA

PCIECLKRQ7#

CLK_BUF_EXP#
CLK_BUF_EXP

CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

XTAL25_IN

R756 *0_NC_SHORT +/-5%R756 *0_NC_SHORT +/-5%

R620

R620
1M

1M

+/-5%

+/-5%

XTAL25_OUT

CLK_SMART_48M [37]

CLK_PCI_TPM [46]

CLK_SIO_14M [34]

T165T165

48Mhz Smart Card clock

33Mhz TPM LPC clock

14.318Mhz EC main clock

1

R212 10K +/-5%R212 10K +/-5%
R156 2.2K+/-5%R156 2.2K+/-5%
R151 2.2K+/-5%R151 2.2K+/-5%
R138 10K +/-5%R138 10K +/-5%
R139 1K +/-5%R139 1K +/-5%
R140 2.2K+/-5%R140 2.2K+/-5%
R141 2.2K+/-5%R141 2.2K+/-5%

R248 10K +/-5%R248 10K +/-5%
R228 10K +/-5%R228 10K +/-5%

R154 10K +/-5%R154 10K +/-5%

R169 2.2K+/-5%R169 2.2K+/-5%
R229 2.2K+/-5%R229 2.2K+/-5%

R167 10K +/-5%R167 10K +/-5%

R135 10K +/-5%R135 10K +/-5%
R136 10K +/-5%R136 10K +/-5%

R638 10K +/-5%R638 10K +/-5%

R92 10K +/-5%R92 10K +/-5%
R94 10K +/-5%R94 10K +/-5%

R241 10K +/-5%R241 10K +/-5%
R242 10K +/-5%R242 10K +/-5%

R59 10K +/-5%R59 10K +/-5%

XTA25L_IN_R

X2
XTAL 25MHzX2XTAL 25MHz

1 2

+3.3V_ALW_PCH

C442

C442

30pF

30pF

50V,NPO

50V,NPO

C441

C441

30pF

30pF

50V,NPO

50V,NPO

R157 *0_NC+/-5%R157 *0_NC +/-5%

3 4

LAN_SMBCLK[33,40] MEM_XDP_HDD_SMBCLK [6,14,15,28,32]

A A

5

4

2N7002DW-7-F

2N7002DW-7-F

2N7002DW-7-F

2N7002DW-7-F

Q14A

Q14A

Q14B

Q14B

R188 *0_NC +/-5%R188 *0_NC +/-5%

PCH_SMBCLK PCH_SMBCLK

5

2

6 1

PCH_SMBDATPCH_SMBDAT

3

R158 *0_NC+/-5%R158 *0_NC +/-5%

Q12A

Q12A

2N7002DW-7-F

2N7002DW-7-F

Q12B

Q12B

2N7002DW-7-F

2N7002DW-7-F

3 4

5

R159 2.2K+/-5%R159 2.2K +/-5%

R153 2.2K+/-5%R153 2.2K +/-5%

2

6 1

R152 *0_NC +/-5%R152 *0_NC +/-5%

+3.3V_RUN+3.3V_ALW_PCH

MEM_XDP_HDD_SMBDAT [6,14,15,28,32]LAN_SMBDAT[33,40]

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

10 -- CBT 4/7 (PCIE, CLK)

10 -- CBT 4/7 (PCIE, CLK)

10 -- CBT 4/7 (PCIE, CLK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

2

Date: Sheet of

1

of

10 69Wednesday, February 16, 2011

10 69Wednesday, February 16, 2011

10 69Wednesday, February 16, 2011

1A

1A

1A

5

D D

GPIO15 TLS Confidentiality

Low = Intel ME Crypto Transport Layer
Security (TLS) cipher suite with no
confidentiality
High = Intel ME Crypto TLS cipher suite
with confidentiality

R630 *1K_NC +/-1%R630 *1K_NC +/-1%

PLL ON DIE VR ENABLE

ENABLED - HIGH (R270 UNSTUFFED) DEFAULT
DISABLED - LOW (R270 STUFFED)

+3.3V_ALW_PCH

C C

B B

R182 10K +/-5%R182 10K +/-5%

GPIO8 (SIO_EXT_WAKE#)

Low - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with no confidentiality
High - Intel ME Crypto Transport Layer Security (TLS)
cipher suite with confidentiality

R223 *100K_NC +/-5%R223 *100K_NC +/-5%

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37
(FDI_OVRVLTG)

AUDIO verb table selection

GPIO37
(FDI_OVRVLTG)

PCH_GPIO1

SIO_EXT_WAKE#

FDI_OVRVLTG

LOW - Tx, Rx terminated
to same voltage
(DC Coupling Mode)
DEFAULT

LOW - Internal pull down 20K.
Default MIC detection.
High - Pop R297
External MIC detection

SIO_EXT_SCI#[33]

4

COUGAR POINT (GPIO,VSS_NCTF,RSVD)

R252
Maximum distance between resistor and PCH is 25.4mm.

U3F

G

U3F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

DS

PCH_GPIO28

SIO_EXT_SCI#_R[6]

SIO_EXT_SCI#

R252 *0_NC_SHORT +/-5%R252 *0_NC_SHORT +/-5%

PCH_GPIO1

IOR_B_DET#[37]

LED_B_DET#[37]

SIO_EXT_WAKE#[34]

TPM_B_DET#[46]

PCH_GPIO15[6]

EN_ESATA_RPTR[6]

SPEAKER_DET#[24]

MEDIA_DET#[37]

PCIE_MCARD1_DET#[32]

USB_MCARD1_DET#[6,32]

PCH_GPIO36[6]

FDI_OVRVLTG[6]

TPM_ID0[46]

TPM_ID1[46]

FFS_INT2[28]

TEMP_ALERT#[6,34]

KB_DET#[35]

SLP_ME_CSW_DEV#[6,34]

IOR_B_DET#

LED_B_DET#

SIO_EXT_WAKE#

TPM_B_DET#

PCH_GPIO15

EN_ESATA_RPTR

SPEAKER_DET#

MEDIA_DET#

PCIE_MCARD1_DET#

PCH_GPIO27

PCH_GPIO28

PCH_GPIO34

USB_MCARD1_DET#

PCH_GPIO36

FDI_OVRVLTG

TEMP_ALERT#

KB_DET#

T133T133

T123T123

T124T124

T122T122

T132T132

T131T131

T135T135

T117T117

T144T144

T109T109

T146T146

T110T110

T147T147

T115T115

PCH_PLTRST#[2,8,9,30,31,32,33,34,46]

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

*2N7002W-7-F_NC

*2N7002W-7-F_NC

Q13

Q13

GPIO

GPIO

3

NCTF

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

2

1227: Pop R196 for Intel ME setting.

C40

CONTACTLESS_DET#

B41

PCH_GPIO69

C41

PCIE_MCARD3_DET#

A40

USB_MCARD2_DET#

P4

SIO_A20GATE

AU16

H_PECI_R

PECI

P5

SIO_RCIN#

AY11

AY10

PCH_THRMTRIP#_R

T14

INIT_3.3V#

AY1

NV_CLE

AH8

AK11

AH10

AK10

P37

NC_1

BG2

VSS_NCTF_15

BG48

VSS_NCTF_16

BH3

VSS_NCTF_17

BH47

VSS_NCTF_18

BJ4

VSS_NCTF_19

BJ44

VSS_NCTF_20

BJ45

VSS_NCTF_21

BJ46

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ6

VSS_NCTF_24

C2

VSS_NCTF_25

C48

VSS_NCTF_26

D1

VSS_NCTF_27

D49

VSS_NCTF_28

E1

VSS_NCTF_29

E49

VSS_NCTF_30

F1

VSS_NCTF_31

F49

VSS_NCTF_32

PCIE_MCARD3_DET# [30]

USB_MCARD2_DET# [31]

R267 *0_NC

R267 *0_NC

+/-5%

+/-5%

T41T41

T145T145

T111T111

T143T143

T108T108

T142T142

T119T119

T113T113

T118T118

T140T140

T141T141

T137T137

T116T116

T138T138

T120T120

T139T139

T114T114

T136T136

T121T121

C166

C166

0.1uF

0.1uF

10V,X5R

10V,X5R

SIO_A20GATE [33]

H_PECI [2,33]

SIO_RCIN# [33]

H_CPUPWRGD [2,6]

R176 56 +/-5%R176 56 +/-5%

+1.05V_RUN

PLACE R638 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)

DMI & FDI Termination Voltage

NV_CLE Set to Vss when LOW

Set to Vcc when HIGH

PCH_GPIO15

PCH_GPIO28

KB_DET#

PCIE_MCARD1_DET#

SIO_RCIN#

SIO_EXT_SCI#

PCH_GPIO1

SIO_A20GATE

CONTACTLESS_DET#

EN_ESATA_RPTR

TEMP_ALERT#

MEDIA_DET#

FDI_OVRVLTG

SPEAKER_DET#

PCIE_MCARD3_DET#

USB_MCARD2_DET#

PCH_GPIO34

PCH_GPIO69

LED_B_DET#

IOR_B_DET#

PCH_GPIO36

USB_MCARD1_DET#

PCH_GPIO27

+VCCPNAND

NV_CLE

1

R196 1K +/-1%R196 1K +/-1%

R258 4.7K +/-5%R258 4.7K+/-5%

R259 10K +/-5%R259 10K +/-5%

R546 100K+/-5%R546 100K+/-5%

R257 10K +/-5%R257 10K +/-5%

R253 10K +/-5%R253 10K +/-5%

R628 10K +/-5%R628 10K +/-5%

R255 10K +/-5%R255 10K +/-5%

R632 10K +/-5%R632 10K +/-5%

R207 10K +/-5%R207 10K +/-5%

R653 10K +/-5%R653 10K +/-5%

R254 10K +/-5%R254 10K +/-5%

R246 *1K_NC +/-5%R246 *1K_NC +/-5%

R67 8.2K +/-5%R67 8.2K +/-5%

R503 100K+/-5%R503 100K+/-5%

R629 100K+/-5%R629 100K+/-5%

R203 10K +/-5%R203 10K +/-5%

R65 *10K_NC +/-5%R65 *10K_NC +/-5%

R56 10K +/-5%R56 10K +/-5%

R58 10K +/-5%R58 10K +/-5%

R206 *10K_NC +/-5%R206 *10K_NC +/-5%

R190 100K+/-5%R190 100K+/-5%

R130 10K +/-5%R130 10K +/-5%

R249

R249

2.2K

2.2K

+/-5%

+/-5%

+3.3V_ALW_PCH

+3.3V_RUN

A A

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

11 -- CBT 5/7 (GPIO, CPU)

11 -- CBT 5/7 (GPIO, CPU)

11 -- CBT 5/7 (GPIO, CPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

11 69Wednesday, February 16, 2011

11 69Wednesday, February 16, 2011

11 69Wednesday, February 16, 2011

1A

1A

1A

5

+1.05V_RUN

VCCCORE=1.3A max

C132

C132

10uF

10uF

6.3V,X5R

D D

C C

B B

A A

6.3V,X5R

+1.05V_RUN

+1.05V_RUN

+1.05V_RUN

R186 *0_NC +/-5%R186 *0_NC +/-5%

R23 *0_NC_SHORT +/-5%R23 *0_NC_SHORT +/-5%

+1.8V_RUN

R21 *0_NC +/-5%R21 *0_NC +/-5%

+1.05V_RUN

R22 *0_NC +/-5%R22 *0_NC +/-5%

+1.05V_RUN

close PCH 100mil,
trace width 20mil of L12,L14

+3.3V_RUN

C116

C116

C129

C129

1uF

1uF

1uF

1uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

L18 *1uH_NCL18 *1uH_NC

close PCH
100mil

C151

C151

10uF

10uF

6.3V,X5R

6.3V,X5R

C107

C107

C115

C115

1uF

1uF

1uF

1uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

+3.3V_RUN

+1.05V_+1.5V_1.8V_RUN

C170

C170

*10uF_NC

*10uF_NC

6.3V,X5R

6.3V,X5R

L12

L12

10uH

10uH

+/-10%

+/-10%

0805h14

0805h14

L14

L14

10uH

10uH

+/-10%

+/-10%

0805h14

0805h14

L13

L13

10uH +/-10%

10uH +/-10%

0805h14

0805h14

+VCCAPLL_FDI

C65

C65

10uF

10uF

6.3V,X5R

6.3V,X5R

C114

C114

1uF

1uF

6.3V,X5R

6.3V,X5R

+1.05V_RUN

+VCCAPLLEXP

C152

C152

*10uF_NC

*10uF_NC

6.3V,X5R

6.3V,X5R

C121

C121

1uF

1uF

6.3V,X5R

6.3V,X5R

C143

C143

1uF

1uF

6.3V,X5R

6.3V,X5R

C109

C109

0.1uF

0.1uF

10V,X5R

10V,X5R

+1.05V_RUN

+1.05V_RUN

+1.05V_+1.5V_1.8V_RUN

C443

C443
220uF

220uF

2.5V,<=15mOhm

2.5V,<=15mOhm

+3.3V_RUN_VCC_CLKF33

C83

C83

1uF

1uF

6.3V,X5R

6.3V,X5R

C61

C61

1uF

1uF

6.3V,X5R

6.3V,X5R

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

AN19

BJ22

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

U3G

U3G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

+1.05V_+1.5V_1.8V_RUN+1.5V_RUN

+1.05V_RUN_VCCA_A_DPL

+1.05V_RUN_VCCA_B_DPL

C444

C444
220uF

220uF

2.5V,<=15mOhm

2.5V,<=15mOhm

POWER

POWER

VCC CORE

VCC CORE

VCCIO

VCCIO

FDI

FDI

+1.05V_RUN

C62

C62

1uF

1uF

6.3V,X5R

6.3V,X5R

+1.05V_RUN

close PCH 100mil

5

CRTLVDS

CRTLVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

DMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

DFT / SPI HVCMOS

C445

C445
*330uF_NC

*330uF_NC

2V,<=9mOhm

2V,<=9mOhm

L16 *10uH_NCL16 *10uH_NC

close PCH
width 100mil

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

4

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+VCCAPLL_CPY_PCH

C136

C136

*10uF_NC

*10uF_NC

6.3V,X5R

6.3V,X5R

4

close PCH 100mil

+VCCADAC

C55

C55

10uF

10uF

10V,X5R

10V,X5R

VCCALVDS = 1mA max

VCCTX_LVDS = 60mA max

C82

C82

10nF

10nF

25V,X7R

25V,X7R

+3.3V_RUN

C111

C111

0.1uF

0.1uF

10V,X5R

10V,X5R

+1.05V_+1.5V_1.8V_RUN

C97

C97

1uF

1uF

6.3V,X5R

6.3V,X5R

+VCCPNAND

+3.3V_RUN

C177

C177

1uF

1uF

6.3V,X5R

6.3V,X5R

FB1

FB1
FB 1K Ohm, 300mA

FB 1K Ohm, 300mA

1 2

C59

C59

C58

C58

10nF

10nF

0.1uF

0.1uF

25V,X7R

25V,X7R

10V,X5R

10V,X5R

+3.3V_RUN

C92

C92

0.1uF

0.1uF

10V,X5R

10V,X5R

C75

C75

C57

C57

10nF

10nF

22uF

22uF

25V,X7R

25V,X7R

6.3V,X5R

6.3V,X5R

c0805h14

c0805h14

+1.05V_RUN

C142

C142

1uF

1uF

6.3V,X5R

6.3V,X5R

L11

L11

10uH

10uH

C113

C113

+/-10%

+/-10%

*10uF_NC

*10uF_NC

0805h14

0805h14

6.3V,X5R

6.3V,X5R

close PCH 100mil

R226 *0_NC_SHORT +/-5%R226 *0_NC_SHORT +/-5%

R227 *0_NC +/-5%R227 *0_NC +/-5%

C149

C149

0.1uF

0.1uF

10V,X5R

10V,X5R

3

COGAR POINT (POWER)

+3.3V_RUN

0603h10

0603h10

+3.3V_ALW_PCH

L10

L10

0.1uH,250mA

0.1uH,250mA

0805h11

0805h11

+/-10%

+/-10%

+1.05V_RUN

+1.05V_RUN

+1.05V_RUN

+1.05V_RUN

R102 *0_NC_SHORT +/-5%R102 *0_NC_SHORT +/-5%

+1.8V_RUN

+1.8V_RUN

+3.3V_RUN

trace width
40mil

R96 *0_NC

R96 *0_NC

C153

C153

0.1uF

0.1uF

10V,X5R

10V,X5R

+PCH_VCCDSW

C157

C157

*0.1uF_NC

*0.1uF_NC

10V,X5R

10V,X5R

+1.05V_RUN

C159

C159

1uF

1uF

6.3V,X5R

6.3V,X5R

C93

C93

1uF

1uF

6.3V,X5R

6.3V,X5R

+/-5%

+/-5%

C141

C141

*1uF_NC

*1uF_NC

6.3V,X5R

6.3V,X5R

C161

C161

C163

C163

4.7uF

4.7uF

0.1uF

0.1uF

10V,X5R

10V,X5R

10V,X5R

10V,X5R

c0603h9

c0603h9

+RTC_CELL

R51 *0_NC +/-5%R51 *0_NC +/-5%

3

+1.05V_RUN

R602 *0_NC +/-5%R602 *0_NC +/-5%

+VCCPDSW

+VCCSUS1

C133

C133

*1uF_NC

*1uF_NC

6.3V,X5R

6.3V,X5R

C137

C137

1uF

1uF

6.3V,X5R

6.3V,X5R

C154 0.1uF

C154 0.1uF

C91 1uF

C91 1uF

C134

C134

1uF

1uF

6.3V,X5R

6.3V,X5R

+VCCACLK

+3.3V_RUN_VCC_CLKF33

+VCCAPLL_CPY_PCH

+1.05V_RUN

C193

C193

C168

C168

22uF

22uF

22uF

22uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

c0805h14

c0805h14

c0805h14

c0805h14

C106

C106

C118

C118

1uF

1uF

1uF

1uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

+VCCRTCEXT

10V,X5R

10V,X5R

+1.05V_+1.5V_1.8V_RUN

+1.05V_RUN_VCCA_A_DPL

+1.05V_RUN_VCCA_B_DPL

6.3V,X5R

6.3V,X5R

C145 0.1uF

C145 0.1uF

10V,X5R

10V,X5R

+1.05V_M_VCCSUS

C164

C164

0.1uF

0.1uF

10V,X5R

10V,X5R

C144

C144

C150

C150

0.1uF

0.1uF

0.1uF

0.1uF

10V,X5R

10V,X5R

10V,X5R

10V,X5R

+1.05V_RUN_VCCA_B_DPL+1.05V_RUN_VCCA_A_DPL

+VCCSST

U3J

U3J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

2

POWER

POWER

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPCMISC

PCI/GPIO/LPCMISC

SATA USB

SATA USB

CPURTC

CPURTC

HDA

HDA

2

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

1

+1.05V_RUN

C119

C119

1uF

1uF

6.3V,X5R

6.3V,X5R

+3.3V_ALW_PCH

close PCH

C128

C128

width 100mil

0.1uF

0.1uF

10V,X5R

10V,X5R

+3.3V_ALW_PCH

C124 0.1uF10V,X5RC124 0.1uF10V,X5R

+1.05V_RUN

+PCH_V5REF_SUS

+VCCA_USBSUS

+PCH_V5REF_RUN

C96

C96

0.1uF

0.1uF

10V,X5R

10V,X5R

+3.3V_ALW_PCH

C139

C139

1uF

1uF

6.3V,X5R

6.3V,X5R

close PCH 100mil

C90

C90

0.1uF

0.1uF

10V,X5R

10V,X5R

trace width
40mil

C155

C155

1uF

1uF

6.3V,X5R

6.3V,X5R

+VCCSATAPLL

+1.05V_+1.5V_1.8V_RUN

+1.05V_RUN

+3.3V_ALW_PCH

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

R91 10+/-5% r0603h6R91 10+/-5% r0603h6

C A

D8 SDM10K45-7-FD8 SDM10K45-7-F

C117

C117

1uF

1uF

+3.3V_ALW_PCH

6.3V,X5R

6.3V,X5R

C126

C126

0.1uF

0.1uF

10V,X5R

10V,X5R

R75 10+/-5% r0603h6R75 10+/-5% r0603h6

C A

D7 SDM10K45-7-FD7 SDM10K45-7-F

+3.3V_RUN

+3.3V_RUN

C167 0.1uF 10V,X5RC167 0.1uF 10V,X5R

+1.05V_RUN

close PCH 100mil

L19 *10uH_NC +/-10%L19 *10uH_NC +/-10%

C174

C174

*10uF_NC

*10uF_NC

6.3V,X5R

6.3V,X5R

C147

C147

1uF

1uF

6.3V,X5R

6.3V,X5R

C112

C112

0.1uF

0.1uF

10V,X5R

10V,X5R

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

12 -- CBT 6/7 (POWER)

12 -- CBT 6/7 (POWER)

12 -- CBT 6/7 (POWER)

1

V5REF_SUS = 1mA max

+3.3V_RUN

C148

C148

0.1uF

0.1uF

10V,X5R

10V,X5R

+1.05V_RUN

+VCCA_USBSUS

+5V_RUN

+3.3V_RUN

12 69Wednesday, February 16, 2011

12 69Wednesday, February 16, 2011

12 69Wednesday, February 16, 2011

C127

C127

*1uF_NC

*1uF_NC

6.3V,X5R

6.3V,X5R

+5V_ALW_PCH

+3.3V_ALW_PCH

+1.05V_RUN

of

1A

1A

1A

5

4

3

2

1

Cougar Point (GND)

U3I

U3I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

D D

C C

B B

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

U3H

U3H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

BD82HM65[VER.B3,SLJ4P]

BD82HM65[VER.B3,SLJ4P]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

A A

Ever Light

Ever Light

Ever Light
Technology Limited

Technology Limited

Technology Limited

Title

Title

Title

13 -- CBT 7/7 (GND)

13 -- CBT 7/7 (GND)

13 -- CBT 7/7 (GND)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

13 69Wednesday, February 16, 2011

13 69Wednesday, February 16, 2011

13 69Wednesday, February 16, 2011

1A

1A

1A

5

4

3

2

1

DDR3 Length Matching Formulas

Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)

D D

Clock - 0.5"
Clock - 0.5"
Clock - 0.5"

Strobe - 20 mils

Clock - 0.0"
Clock - 0.5"
Clock - 1.0"

Strobe + 20 mils

JDIMMA1A

DDR_A_MA[0..15][3] DDR_A_D[0..63] [3]

DDR_A_BS0[3]
DDR_A_BS1[3]
DDR_A_BS2[3]
DDR_A_CS#0[3]
DDR_A_CS#1[3]
DDR_A_CLK0[3]
DDR_A_CLK#0[3]
DDR_A_CLK1[3]
DDR_A_CLK#1[3]

C348

C348

10uF

10uF

6.3V,X5R

6.3V,X5R

DDR_A_CKE0[3]
DDR_A_CKE1[3]
DDR_A_CAS#[3]
DDR_A_RAS#[3]
DDR_A_WE#[3]

MEM_XDP_HDD_SMBCLK[6,10,15,28,32]
MEM_XDP_HDD_SMBDAT[6,10,15,28,32]

DDR_A_ODT0[3]
DDR_A_ODT1[3]

DDR_A_DQS[0..7][3]

DDR_A_DQS#[0..7][3]

C351

C351

C338

C338

1uF

1uF

1uF

1uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

Address:0xA0

SA0

0

0CHB0

330uF x 1
10uF x 6
1uF x 4

C367

C367

10uF

10uF

6.3V,X5R

6.3V,X5R

+3.3V_RUN

R708 *10K_NC+/-5%R708 *10K_NC +/-5%
R709 10K +/-5%R709 10K +/-5%
R712 10K +/-5%R712 10K +/-5%

+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those capacitors should be placed on the same side of the motherboard as the
SO-DIMM connector

Place these Caps near So-DimmA.

C333

C333

C344

C344

C342

C342

10uF

10uF

10uF

10uF

10uF

10uF

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

6.3V,X5R

C C

SA1

CHA0

0

1

B B

C354

C354

10uF

10uF

6.3V,X5R

6.3V,X5R

JDIMMA1A

98

DDR_A_MA0

A0

97

DDR_A_MA1

A1

96

DDR_A_MA2

A2

95

DDR_A_MA3

A3

92

DDR_A_MA4

A4

91

DDR_A_MA5

A5

90

DDR_A_MA6

A6

86

DDR_A_MA7

A7

89

DDR_A_MA8

A8

85

DDR_A_MA9

A9

107

DDR_A_MA10

A10/AP

84

DDR_A_MA11

A11

83

DDR_A_MA12

A12/BC#

119

DDR_A_MA13

A13

80

DDR_A_MA14

A14

78

DDR_A_MA15

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DDR_A_DQS0

DQS0

29

DDR_A_DQS1

DQS1

47

DDR_A_DQS2

DQS2

64

DDR_A_DQS3

DQS3

137

DDR_A_DQS4

DQS4

154

DDR_A_DQS5

DQS5

171

DDR_A_DQS6

DQS6

188

DDR_A_DQS7

DQS7

10

DDR_A_DQS#0

DQS#0

27

DDR_A_DQS#1

DQS#1

45

DDR_A_DQS#2

DQS#2

62

DDR_A_DQS#3

DQS#3

135

DDR_A_DQS#4

DQS#4

152

DDR_A_DQS#5

DQS#5

169

DDR_A_DQS#6

DQS#6

186

DDR_A_DQS#7

DQS#7

AS0A626-J8RG-7H

AS0A626-J8RG-7H

+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN

C335

C346

C346

1uF

1uF

6.3V,X5R

6.3V,X5R

C335
330uF

330uF

2V,+/-20%

2V,+/-20%

C352

C352

1uF

1uF

6.3V,X5R

6.3V,X5R

5

DDR_A_D0

DQ0

7

DDR_A_D1

DQ1

15

DDR_A_D2

DQ2

17

DDR_A_D3

DQ3

4

DDR_A_D4

DQ4

6

DDR_A_D5

DQ5

16

DDR_A_D6

DQ6

18

DDR_A_D7

DQ7

21

DDR_A_D8

DQ8

23

DDR_A_D9

DQ9

33

DDR_A_D10

DQ10

35

DDR_A_D11

DQ11

22

DDR_A_D12

DQ12

24

DDR_A_D13

DQ13

34

DDR_A_D14

DQ14

36

DDR_A_D15

DQ15

39

DDR_A_D16

DQ16

41

DDR_A_D17

DQ17

51

DDR_A_D18

DQ18

53

DDR_A_D19

DQ19

40

DDR_A_D20

DQ20

42

DDR_A_D21

DQ21

50

DDR_A_D22

DQ22

52

DDR_A_D23

DQ23

57

DDR_A_D24

DQ24

59

DDR_A_D25

DQ25

67

DDR_A_D26

DQ26

69

DDR_A_D27

DQ27

56

DDR_A_D28

DQ28

58

DDR_A_D29

DQ29

68

DDR_A_D30

DQ30

70

DDR_A_D31

DQ31

129

DDR_A_D32

DQ32

131

DDR_A_D33

DQ33

141

DDR_A_D34

DQ34

143

DDR_A_D35

DQ35

130

DDR_A_D36

DQ36

132

DDR_A_D37

DQ37

140

DDR_A_D38

DQ38

142

DDR_A_D39

DQ39

147

DDR_A_D40

DQ40

149

DDR_A_D41

DQ41

157

DDR_A_D42

DQ42

159

DDR_A_D43

DQ43

146

DDR_A_D44

DQ44

148

DDR_A_D45

DQ45

158

DDR_A_D46

DQ46

160

DDR_A_D47

DQ47

163

DDR_A_D48

DQ48

165

DDR_A_D49

DQ49

175

DDR_A_D50

DQ50

177

DDR_A_D51

DQ51

164

DDR_A_D52

DQ52

166

DDR_A_D53

DQ53

174

DDR_A_D54

DQ54

176

DDR_A_D55

DQ55

181

DDR_A_D56

DQ56

183

DDR_A_D57

DQ57

191

DDR_A_D58

DQ58

193

DDR_A_D59

DQ59

180

DDR_A_D60

DQ60

182

DDR_A_D61

DQ61

192

DDR_A_D62

DQ62

194

DDR_A_D63

DQ63

All VREF traces should have 10 mil trace width

C493

C493

C494

C494

0.1uF

0.1uF

2.2uF

2.2uF

10V,X5R

10V,X5R

10V,X5R

10V,X5R

+1.5V_MEM

+3.3V_RUN

TS#_DIMMA0

DDR3_DRAMRST#[2,15]

M_VREF_DQ_A[5,16]

2.2uF

2.2uF

10V,X5R

10V,X5R

M_VREF_CA[15,16]

2.2uF

2.2uF

10V,X5R

10V,X5R

T104T104

C337

C337

C336

C336

0.1uF

0.1uF

10V,X5R

10V,X5R

C509

C509

C507

C507

0.1uF

0.1uF

10V,X5R

10V,X5R

1uF x 4

C505

C506

C506

1uF

1uF

6.3V,X5R

6.3V,X5R

C505

1uF

1uF

6.3V,X5R

6.3V,X5R

C504

C504

1uF

1uF

6.3V,X5R

6.3V,X5R

C503

C503

1uF

1uF

6.3V,X5R

6.3V,X5R

JDIMMA1B

JDIMMA1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

AS0A626-J8RG-7H

AS0A626-J8RG-7H

0810: Change P/N

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

+0.75V_DDR_VTT

203

VTT1

204

VTT2

G1

GND

G2

GND

A A

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14 -- SODIMM-204P_JDIMM A

14 -- SODIMM-204P_JDIMM A

14 -- SODIMM-204P_JDIMM A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

14 69Wednesday, February 16, 2011

14 69Wednesday, February 16, 2011

14 69Wednesday, February 16, 2011

1A

1A

1A

5

4

3

2

1

DDR3 Length Matching Formulas

Signal Group Min Length Max Length
Control-to-Clock
Command-to-Clock
Strobe-to-Clock
Data-to-Strobe (per byte lane)

D D

DDR_B_MA[0..15][3]

DDR_B_BS0[3]
DDR_B_BS1[3]
DDR_B_BS2[3]
DDR_B_CS#0[3]
DDR_B_CS#1[3]
DDR_B_CLK0[3]
DDR_B_CLK#0[3]
DDR_B_CLK1[3]
DDR_B_CLK#1[3]
DDR_B_CKE0[3]
DDR_B_CKE1[3]
DDR_B_CAS#[3]

R719 10K +/-5%R719 10K +/-5%
R720 *10K_NC+/-5%R720 *10K_NC +/-5%
R718 10K +/-5%R718 10K +/-5%

Address:0xA4

SA0

0

0CHB0

+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those capacitors should be placed on the same side of the motherboard as the
SO-DIMM connector

330uF x 1
10uF x 6
1uF x 4

C368

C350

C350

10uF

10uF

6.3V,X5R

6.3V,X5R

C368

10uF

10uF

6.3V,X5R

6.3V,X5R

C334

C334

10uF

10uF

6.3V,X5R

6.3V,X5R

CHA0

SA1

0

1

C341

C341

10uF

10uF

6.3V,X5R

6.3V,X5R

+3.3V_RUN

C C

B B

DDR_B_RAS#[3]
DDR_B_WE#[3]

MEM_XDP_HDD_SMBCLK[6,10,14,28,32]
MEM_XDP_HDD_SMBDAT[6,10,14,28,32]

DDR_B_ODT0[3]
DDR_B_ODT1[3]

DDR_B_DQS[0..7][3]

DDR_B_DQS#[0..7][3]

Place these Caps near So-DimmB.

C353

C355

C355

10uF

10uF

6.3V,X5R

6.3V,X5R

C353

1uF

1uF

6.3V,X5R

6.3V,X5R

C395

C395

10uF

10uF

6.3V,X5R

6.3V,X5R

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

C347

C347

1uF

1uF

6.3V,X5R

6.3V,X5R

JDIMMB1A

JDIMMB1A

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

C364

C364

1uF

1uF

6.3V,X5R

6.3V,X5R

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9
A10/AP

84

A11

83

A12/BC#
A13

80

A14

78

A15

BA0
BA1

79

BA2
S0#
S1#
CK0
CK0#
CK1
CK1#

73

CKE0

74

CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

11

DM0

28

DM1

46

DM2

63

DM3
DM4
DM5
DM6
DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3
DQS4
DQS5
DQS6
DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDRIII

DDRIII

5

DDR_B_D0

DQ0

7

DDR_B_D1

DQ1

15

DDR_B_D2

DQ2

17

DDR_B_D3

DQ3

4

DDR_B_D4

DQ4

6

DDR_B_D5

DQ5

16

DDR_B_D6

DQ6

18

DDR_B_D7

DQ7

21

DDR_B_D8

DQ8

23

DDR_B_D9

DQ9

33

DDR_B_D10

DQ10

35

DDR_B_D11

DQ11

22

DDR_B_D12

DQ12

24

DDR_B_D13

DQ13

34

DDR_B_D14

DQ14

36

DDR_B_D15

DQ15

39

DDR_B_D16

DQ16

41

DDR_B_D17

DQ17

51

DDR_B_D18

DQ18

53

DDR_B_D19

DQ19

40

DDR_B_D20

DQ20

42

DDR_B_D21

DQ21

50

DDR_B_D22

DQ22

52

DDR_B_D23

DQ23

57

DDR_B_D24

DQ24

59

DDR_B_D25

DQ25

67

DDR_B_D26

DQ26

69

DDR_B_D27

DQ27

56

DDR_B_D28

DQ28

58

DDR_B_D29

DQ29

68

DDR_B_D30

DQ30

70

DDR_B_D31

DQ31

129

DDR_B_D32

DQ32

131

DDR_B_D33

DQ33

141

DDR_B_D34

DQ34

143

DDR_B_D35

DQ35

130

DDR_B_D36

DQ36

132

DDR_B_D37

DQ37

140

DDR_B_D38

DQ38

142

DDR_B_D39

DQ39

147

DDR_B_D40

DQ40

149

DDR_B_D41

DQ41

157

DDR_B_D42

DQ42

159

DDR_B_D43

DQ43

146

DDR_B_D44

DQ44

148

DDR_B_D45

DQ45

158

DDR_B_D46

DQ46

160

DDR_B_D47

DQ47

163

DDR_B_D48

DQ48

165

DDR_B_D49

DQ49

175

DDR_B_D50

DQ50

177

DDR_B_D51

DQ51

164

DDR_B_D52

DQ52

166

DDR_B_D53

DQ53

174

DDR_B_D54

DQ54

176

DDR_B_D55

DQ55

181

DDR_B_D56

DQ56

183

DDR_B_D57

DQ57

191

DDR_B_D58

DQ58

193

DDR_B_D59

DQ59

180

DDR_B_D60

DQ60

182

DDR_B_D61

DQ61

192

DDR_B_D62

DQ62

194

DDR_B_D63

DQ63

+1.5V_MEM +0.75V_DDR_VTT+3.3V_RUN

1012: Cost down solution

C371

C371

C345

C345

*330uF_NC

*330uF_NC

1uF

1uF

2V,<=9mOhm

2V,<=9mOhm

6.3V,X5R

6.3V,X5R

DDR_B_D[0..63] [3]

All VREF traces should have 10 mil trace width

DDR3_DRAMRST#[2,14]

M_VREF_DQ_B[5,16]

M_VREF_CA[14,16]

C517

C517

2.2uF

2.2uF

10V,X5R

10V,X5R

C516

C516

0.1uF

0.1uF

10V,X5R

10V,X5R

10V,X5R

10V,X5R

10V,X5R

10V,X5R

+1.5V_MEM

JDIMMB1B

JDIMMB1B

75
76
81
82
87
88
93
94

99
100
105
106
111
112
117
118
123
124

199

+3.3V_RUN

77
122
125

198

TS#_DIMMB0

T106T106

C372

C372

C365

C365

2.2uF

2.2uF

0.1uF

0.1uF

10V,X5R

10V,X5R

C369

C369

C370

C370

0.1uF

0.1uF

2.2uF

2.2uF

10V,X5R

10V,X5R

30

1

126

2
3
8

9
13
14
19
20
25
26
31
32
37
38
43

DDRIII

DDRIII

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD

NC1
NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

GND#2-G2

VTT1
VTT2

GND

44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

+0.75V_DDR_VTT

203
204

G1
G2

1uF x 4

C511

C511

C513

C513

C512

C512

C514

C514

1uF

1uF

6.3V,X5R

6.3V,X5R

1uF

1uF

6.3V,X5R

6.3V,X5R

1uF

1uF

6.3V,X5R

6.3V,X5R

1uF

1uF

6.3V,X5R

6.3V,X5R

Clock - 0.5"
Clock - 0.5"
Clock - 0.5"

Strobe - 20 mils

Clock - 0.0"
Clock - 0.5"
Clock - 1.0"

Strobe + 20 mils

A A

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Title

15 -- SODIMM-204P_JDIMMB

15 -- SODIMM-204P_JDIMMB

15 -- SODIMM-204P_JDIMMB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

15 69Wednesday, February 16, 2011

15 69Wednesday, February 16, 2011

15 69Wednesday, February 16, 2011

1A

1A

1A

5

M1: Fixed SO-DIMM VREF_DQ (Default)

+1.5V_MEM

R496

R496
1K

1K

+/-1%

+1.5V_MEM

+/-1%

M_VREF_DQ_R

R482

R482
1K

1K

+/-1%

+/-1%

R510

R510
1K

1K

+/-1%

+/-1%

M_VREF_DQ_R

R513

R513
1K

1K

+/-1%

+/-1%

R481 *0_NC_SHORT +/-5%R481 *0_NC_SHORT +/-5%

C343

C343

0.1uF

0.1uF

10V,X5R

10V,X5R

R518 *0_NC_SHORT +/-5%R518 *0_NC_SHORT +/-5%

C366

C366

0.1uF

0.1uF

10V,X5R

10V,X5R

M_VREF_DQ_A [5,14]

M_VREF_DQ_B [5,15]

D D

C C

4

For SO-DIMM VREF_DQ

3

2

1

M2: Programmable SODIMM VREFDQ

B B

A A

+1.5V_MEM

R716

R716
1K

1K

+/-1%

+/-1%

M_VREF_CA_R

R715

R715
1K

1K

+/-1%

+/-1%

R714 *0_NC_SHORT +/-5%R714 *0_NC_SHORT +/-5%

C508

C508

0.1uF

0.1uF

10V,X5R

10V,X5R

5

M_VREF_CA [14,15]

For SO-DIMM VREF_CA

4

3

+0.75V_DDR_VTT

R717 *0_NC +/-5%R717 *0_NC +/-5%

R467 *0_NC +/-5%R467 *0_NC +/-5%

R519 *0_NC +/-5%R519 *0_NC +/-5%

M_VREF_CA [14,15]

M_VREF_DQ_A [5,14]

M_VREF_DQ_B [5,15]

2

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16 -- DDR3 VREF

16 -- DDR3 VREF

16 -- DDR3 VREF

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thunder 1A

Thunder 1A

Thunder 1A

Date: Sheet of

Date: Sheet of

Date: Sheet

1

of

16 69Wednesday, February 16, 2011

16 69Wednesday, February 16, 2011

16 69Wednesday, February 16, 2011

5

D D

C C

4

3

2

1

Blank Page

B B

A A

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Title

17 -- Blank Page (GPU)

17 -- Blank Page (GPU)

17 -- Blank Page (GPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

17 69Wednesday, February 16, 2011

17 69Wednesday, February 16, 2011

17 69Wednesday, February 16, 2011

1A

1A

1A

5

D D

C C

4

3

2

1

Blank Page

B B

A A

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Title

Title

18 -- Blank Page (GPU)

18 -- Blank Page (GPU)

18 -- Blank Page (GPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

1

of

18 69Wednesday, February 16, 2011

18 69Wednesday, February 16, 2011

18 69Wednesday, February 16, 2011

1A

1A

1A

5

D D

C C

4

3

2

1

Blank Page

B B

A A

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Title

19 -- Blank Page (GPU)

19 -- Blank Page (GPU)

19 -- Blank Page (GPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

19 69Wednesday, February 16, 2011

19 69Wednesday, February 16, 2011

19 69Wednesday, February 16, 2011

1A

1A

1A

5

D D

C C

4

3

2

1

Blank Page

B B

A A

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Title

20 -- Blank Page (GPU)

20 -- Blank Page (GPU)

20 -- Blank Page (GPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

20 69Wednesday, February 16, 2011

20 69Wednesday, February 16, 2011

20 69Wednesday, February 16, 2011

1A

1A

1A

5

D D

C C

4

3

2

1

Blank Page

B B

A A

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Title

21 -- Blank Page (GPU)

21 -- Blank Page (GPU)

21 -- Blank Page (GPU)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

KRUG 15" UMA

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

1

of

21 69Wednesday, February 16, 2011

21 69Wednesday, February 16, 2011

21 69Wednesday, February 16, 2011

1A

1A

1A