Dell Latitude E5270, Latitude E5470, Latitude E5570, Precision 3510 Schematics
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MB PCB
Part Number
DAZ1EO00101 PCB ADP80 LA-C841P LS-C641P
4 4
Description
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
A
B
C
D
Date : Sheet o f
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Document Number Re v
Document Number Re v
Document Number Re v
Cover Sheet
LA-C841P
LA-C841P
LA-C841P
E
1 74Tuesday, September 08, 2015
1 74Tuesday, September 08, 2015
1 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
A
1 1
2 2
B
C
D
E
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
A
B
C
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet of
Date: Sheet of
Date: Sheet of
Block diagram
Block diagram
Block diagram
Document Number Rev
Document Number Rev
Document Number Rev
LA-C841P
LA-C841P
LA-C841P
2 74Tuesday, September 08, 2015
2 74Tuesday, September 08, 2015
E
2 74Tuesday, September 08, 2015
0.1
0.1
0.1
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1
POWER STATES
RUN
State
Signal
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW
SLP
S3#
HIGH
SLP
SLP
S5#
S4#
HIGH HIGH
HIGH HIGH
ALWAYS
SLP
PLANE
A#
HIGH
ON
ON ON ON
HIGH
M
PLANE
ON
SUS
PLANE
ON ON ON
PLA NE
OFF
CLOCKS
OFF
S4 (Suspend to DISK) / M3
S5 (SOFT OFF) / M3
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF
S5 (SOFT OFF) / M-OFF
HIGH HIGH
LOW
LOW
LOW
LOW
HIGH HIGH
LOW
LOW LOW LOW
HIGH
LOW LOW LOW LOW
ON ON
HIGH
ON ON
ON ON
LOW
ON
ON
OFF
OFFLOW
OFF
OFF
OFF
OFF
OFF OFF OFF
OFF OFF OFF OFF
OFF OFF OFF OFF
PM TABLE
C C
power
plane
State
S0
B B
S3
S5 S4/AC
+5V_ALW
+3.3V _ALW
+3.3V_ALW_DSW
+3.3V_SUS
+3.3V_A LW_PCH +1.2V_MEM
+RTC_CELL
+1.8V_PRIM
+1.0V_VCCST
+2.5V_ME M
+1.0V_PRIM
+1.0V_PRIM_CORE
+5V_A LW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1.0V_MPHYGT
ON
ON
ON
ON ON
ON
OFF
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.5V_RUN
OFF
OFF
(M-OFF)
+3.3V_M +3.3V_M
+VCC_CORE
+VCC_GT
+1.0VS_VCCIO
+VCC_SA
ON
ON
ON
ON
OFF
OFF
S5 S4/AC doe sn't ex ist
A A
OFFOFF
OFF
OFFOFF
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date : Sheet o f
Date: Sheet o f
5
4
3
2
Date: Sheet o f
Compal Electronics, Inc.
Port assignment
Port assignment
Document Number Re v
Document Number Rev
Document Number Rev
Port assignment
LA-C841P
LA-C841P
LA-C841P
1
3 74Tuesday, September 08, 2015
3 74Tuesday, September 08, 2015
3 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
RT8207M
(PU201)
AP7175SP
ADAPTER
D D
CHARGER
BQ24777
(PU801)
+PWR_SRC
BATTERY
C C
SIC531CDT1GE
(PU602)
IMVP_V R_ON
B B
+VCC_SA
A A
IMVP_V R_ON
+VCC_GT
5
IMVP_V R_ON
+CPU_B++GPU_B++VCCSA_B+
+VCC_CORE
(PU1500)
SYX198D
(PU301)
SYX196DQNC
(PU401)
SY8286BRAC
(PU102)
SY8286CRAC
(PU100)
AO6405
(QV1)
EN_IN VPWR
+BL_PWR_SRC
SIO_SLP_S4#
SIO_SLP_S4#
SIO_SLP_SUS#
ALWON
ALWON
4
+1.2V_MEM
RUN_ ON
4
+2.5V_MEM
+1.0V_PRIM
+1.0VS_VCCIO
+5V_ALW
+5V_ALW2
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
LDOI N
RT8207
(PU201)
3
0.6V_DDR_VTT_ ON
3
+0.6V_DDR_VTT
TPS22961
(UV27)
TPS22961
(UZ19)
TPS22961
(UZ18)
TPS22967
(UZ23)
EM5209
(UZ4)
PI5USB2544
(UI3)
SY6288
(UI1)
SY6288
(UI2)
SY8032A
(PU501)
EM5209
(UZ3)
3.3V_WWA N_EN
EM5209
(UZ2)
AOZ1336
(UZ8)
EM5209
(UZ4)
TPS22967
(UZ18)
AP2821
(UV24)
+3.3V_RUN_GFX
SIO_SLP_S3#
SIO_SLP_S4#
HDD_ EN
RUN_ ON
USB_PWR_S HR_LFT_EN#
USB_PWR_E N1#
USB_PWR_E N2#
SIO_SLP_SUS#
SIO_SLP_LAN#
AUX_EN_WOWL
@SIO_SLP_WLAN#
@SIO_SLP_WLAN#
RUN_ ON
A_ON
SIO_SLP_SUS#
@PCH_A LW_ON
SUS_ON
ENVDD _PCH
2
+VGA_PCIE
+1.0V_VCCSTG
+1.0V_VCCST
+5V_HDD
+5V_RUN
+5V_USB_CHG_PWR
+USB_LEFT_PWR
+USB_REAR_PWR
+1.8V_PRIM
+3.3V_LAN
+3.3V_WLAN
+3.3V_WWAN
+3.3V_RUN
PJP10
+3.3V_RUN_AUDIO
+3.3V_M
+3.3V_ALW_PCH
+3.3V_CV2
USH/ B
+LCDVDD
2
EM5209
(UZ5)@
1
AUD_P WR_EN
PJP9
+5V_RUN_AUDIO
EM5209
(UV25)
LP2301
(QV8)
AP7175SP
(PU502)
LP2301A
(QZ1)
PJP36
EM5209
(UZ5)@
DGPU_PW R_EN
DGPU_PW R_EN
TS_EN
+3.3V_ RUN
3.3V_CAM_EN#
AUD_P WR_EN
+1.8V_RUN_GFX
+3.3V_RUN_GFX
+5V_TSP
+1.5V_RUN
+3.3V_CAM
+3.3V_HDD
+3.3V_RUN_AUDIO
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet of
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
Power rails
Power rails
Document Number Re v
Document Number Rev
Document Number Rev
Power rails
LA-C841P
LA-C841P
LA-C841P
1
0.1
0.1
4 74Tuesday, September 08, 2015
4 74Tuesday, September 08, 2015
4 74Tuesday, September 08, 2015
0.1
Vinafix.com
5
4
3
2
1
2.2K
2.2K
1K
1K
499
499
+3.3V _ALW_PCH
+3.3V_LAN
28
31
+3.3V_ALW
LOM
DMN66D0LDW
DMN66D0LDW
127
129
DOCKING
2.2K
2.2K
+3.3V_RUN
253
254
253
254
53
51
1
4
DIMM1
DIMM2
XDP1
LNG2DMTR
SMBUS Address [0x9a]
MEM_SMBCLK
D D
AW44
BB43
MEM_SMBDATA
PCH
LAN_SMBCLK
AY44
LAN_SMBDATA
BB39
AW42AW45
SML1_SMBDATA
SML1_SMBCLK
B6A5
1D
1D
B4
1A
A3
1A
1K
1K
DOCK_TNY_SMB_CLK
DOCK_TNY_SMB_DAT
+3.3V _ALW_PCH
AR PD
C C
19
JTHB1
18
2.2K
+3.3V_ALW
KBC
1C1CB59
1E
1E
A56
A50
B53
PBAT_SMBCLK
PBAT_SMBDAT
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
2.2K
100 ohm
100 ohm
+3.3V_SUS
7
6
5
6
BATTERY
CONN
LYNX(CV2)
MEC 5085
B B
2.2K
+3.3V _ALW
B50
A47
B49
B48
CHARGER_SMBCLK
CHARGER_SMBDAT
UPD_GPU_SMBCLK
UPD_GPU_SMBDAT
1G
1G
1H
1H
A A
2.2K
2.2K
2.2K
+3.3V _ALW
DMN66D0LDW
DMN66D0LDW
DMN66D0LDW
DMN66D0LDW
9
8
Charger
100K
+3.3V _RUN_GFX
100K
AJ23
GPU
AH23
4.7K
+3.3V_VDD _PIC
4.7K
AR PD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
Document Number Re v
Document Number Rev
Document Number Rev
LA-C841P
LA-C841P
LA-C841P
1
5 74Tuesday, September 08, 2015
5 74Tuesday, September 08, 2015
5 74Tuesday, September 08, 2015
0.1
0.1
0.1
5
Title
Title
Title
Size
Size
Size
Date: Sheet of
Date: Sheet o f
4
3
2
Date: Sheet o f
Vinafix.com
5
4
3
2
1
PEG_CRX_GTX_P[0..15]
PEG_CRX_GTX_N[0..15]
PEG_CTX_C_GRX_P[0..15]
PEG_CTX_C_GRX_N[0..15]
D D
C C
B B
PEG_COMP
A A
5
PEG_CRX_GTX_P[0..15] <50>
PEG_CRX_GTX_N[0..15] <50>
PEG_CTX_C_GRX_P[0..15] <50>
PEG_CTX_C_GRX_N[0..15] <50>
+1.0VS_VCCIO
12
RC224.9_0402_1%
CPU1C
PEG_CRX_GTX_P15
PEG_CRX_GTX_N15
PEG_CRX_GTX_P14
PEG_CRX_GTX_N14
PEG_CRX_GTX_P13
PEG_CRX_GTX_N13
PEG_CRX_GTX_P12
PEG_CRX_GTX_N12
PEG_CRX_GTX_P11
PEG_CRX_GTX_N11
PEG_CRX_GTX_P10
PEG_CRX_GTX_N10
PEG_CRX_GTX_P9
PEG_CRX_GTX_N9
PEG_CRX_GTX_P8
PEG_CRX_GTX_N8
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
PEG_CRX_GTX_P6
PEG_CRX_GTX_N6
PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
PEG_COMP
DMI_CRX_PTX_P0<17>
DMI_CRX_PTX_N0<17>
DMI_CRX_PTX_P1<17>
DMI_CRX_PTX_N1<17>
DMI_CRX_PTX_P2<17>
DMI_CRX_PTX_N2<17>
DMI_CRX_PTX_P3<17>
DMI_CRX_PTX_N3<17>
DMI_CRX_PTX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P3 DMI_CTX_PRX_P3
DMI_CRX_PTX_N3 DMI_CTX_PRX_N3
E25
PEG_RXP[0]
D25
PEG_RXN[0]
E24
PEG_RXP[1]
F24
PEG_RXN[1]
E23
PEG_RXP[2]
D23
PEG_RXN[2]
E22
PEG_RXP[3]
F22
PEG_RXN[3]
E21
PEG_RXP[4]
D21
PEG_RXN[4]
E20
PEG_RXP[5]
F20
PEG_RXN[5]
E19
PEG_RXP[6]
D19
PEG_RXN[6]
E18
PEG_RXP[7]
F18
PEG_RXN[7]
D17
PEG_RXP[8]
E17
PEG_RXN[8]
F16
PEG_RXP[9]
E16
PEG_RXN[9]
D15
PEG_RXP[10]
E15
PEG_RXN[10]
F14
PEG_RXP[11]
E14
PEG_RXN[11]
D13
PEG_RXP[12]
E13
PEG_RXN[12]
F12
PEG_RXP[13]
E12
PEG_RXN[13]
D11
PEG_RXP[14]
E11
PEG_RXN[14]
F10
PEG_RXP[15]
E10
PEG_RXN[15]
G2
PEG_RCOMP
D8
DMI_RXP[0]
E8
DMI_RXN[0]
E6
DMI_RXP[1]
F6
DMI_RXN[1]
D5
DMI_RXP[2]
E5
DMI_RXN[2]
J8
DMI_RXP[3]
J9
DMI_RXN[3]
REV = 1
SKL-H_BGA1440
BGA1440
3 OF 14
PEG_TXP[0]
PEG_TXN[0]
PEG_TXP[1]
PEG_TXN[1]
PEG_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
PEG_TXN[3]
PEG_TXP[4]
PEG_TXN[4]
PEG_TXP[5]
PEG_TXN[5]
PEG_TXP[6]
PEG_TXN[6]
PEG_TXP[7]
PEG_TXN[7]
PEG_TXP[8]
PEG_TXN[8]
PEG_TXP[9]
PEG_TXN[9]
PEG_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
PEG_TXN[11]
PEG_TXP[12]
PEG_TXN[12]
PEG_TXP[13]
PEG_TXN[13]
PEG_TXP[14]
PEG_TXN[14]
PEG_TXP[15]
PEG_TXN[15]
DMI_TXP[0]
DMI_TXN[0]
DMI_TXP[1]
DMI_TXN[1]
DMI_TXP[2]
DMI_TXN[2]
DMI_TXP[3]
DMI_TXN[3]
PEG_CTX_GRX_P15
B25
PEG_CTX_GRX_N15
A25
PEG_CTX_GRX_P14
B24
PEG_CTX_GRX_N14
C24
PEG_CTX_GRX_P13
B23
PEG_CTX_GRX_N13
A23
PEG_CTX_GRX_P12 PEG_CTX_C_GRX_P12
B22
PEG_CTX_GRX_N12 PEG_CTX_C_GRX_N12
C22
PEG_CTX_GRX_P11
B21
PEG_CTX_GRX_N11
A21
PEG_CTX_GRX_P10 PEG_CTX_C_GRX_P10
B20
C20
PEG_CTX_GRX_P9
B19
PEG_CTX_GRX_N9
A19
PEG_CTX_GRX_P8
B18
PEG_CTX_GRX_N8
C18
PEG_CTX_GRX_P7
A17
PEG_CTX_GRX_N7
B17
PEG_CTX_GRX_P6 PEG_CTX_C_GRX_P6
C16
B16
PEG_CTX_GRX_P5
A15
PEG_CTX_GRX_N5
B15
PEG_CTX_GRX_P4
C14
PEG_CTX_GRX_N4
B14
PEG_CTX_GRX_P3
A13
PEG_CTX_GRX_N3
B13
PEG_CTX_GRX_P2
C12
PEG_CTX_GRX_N2
B12
PEG_CTX_GRX_P1
A11
PEG_CTX_GRX_N1
B11
PEG_CTX_GRX_P0
C10
PEG_CTX_GRX_N0
B10
B8
A8
C6
B6
B5
A5
D4
B4
?
DMI_CTX_PRX_P0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CTX_PRX_N1DMI_CRX_PTX_N1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
Tropo@
CC67 0.22U_0402_10V6K
Tropo@
CC44 0.22U_0402_10V6K
Tropo@
CC68 0.22U_0402_10V6K
Tropo@
CC45 0.22U_0402_10V6K
Tropo@
CC51 0.22U_0402_10V6K
Tropo@
CC53 0.22U_0402_10V6K
Tropo@
CC52 0.22U_0402_10V6K
Tropo@
CC73 0.22U_0402_10V6K
Tropo@
CC69 0.22U_0402_10V6K
Tropo@
CC46 0.22U_0402_10V6K
Tropo@
CC54 0.22U_0402_10V6K
Tropo@
CC74 0.22U_0402_10V6K
Tropo@
CC55 0.22U_0402_10V6K
Tropo@
CC47 0.22U_0402_10V6K
Tropo@
CC70 0.22U_0402_10V6K
Tropo@
CC56 0.22U_0402_10V6K
DIS@
CC57 0.22U_0402_10V6K
DIS@
CC75 0.22U_0402_10V6K
DIS@
CC58 0.22U_0402_10V6K
DIS@
CC48 0.22U_0402_10V6K
DIS@
CC71 0.22U_0402_10V6K
DIS@
CC59 0.22U_0402_10V6K
DIS@
CC60 0.22U_0402_10V6K
DIS@
CC76 0.22U_0402_10V6K
DIS@
CC61 0.22U_0402_10V6K
DIS@
CC49 0.22U_0402_10V6K
DIS@
CC72 0.22U_0402_10V6K
DIS@
CC62 0.22U_0402_10V6K
DIS@
CC63 0.22U_0402_10V6K
DIS@
CC77 0.22U_0402_10V6K
DIS@
CC64 0.22U_0402_10V6K
DIS@
CC50 0.22U_0402_10V6K
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
DMI_CTX_PRX_P0 <17>
DMI_CTX_PRX_N0 <17>
DMI_CTX_PRX_P1 <17>
DMI_CTX_PRX_N1 <17>
DMI_CTX_PRX_P2 <17>
DMI_CTX_PRX_N2 <17>
DMI_CTX_PRX_P3 <17>
DMI_CTX_PRX_N3 <17>
PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_N15
PEG_CTX_C_GRX_P14
PEG_CTX_C_GRX_N14
PEG_CTX_C_GRX_P13
PEG_CTX_C_GRX_N13
PEG_CTX_C_GRX_P11
PEG_CTX_C_GRX_N11
PEG_CTX_C_GRX_N10PEG_CTX_GRX_N10
PEG_CTX_C_GRX_P9
PEG_CTX_C_GRX_N9
PEG_CTX_C_GRX_P8
PEG_CTX_C_GRX_N8
PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_N7
PEG_CTX_C_GRX_N6PEG_CTX_GRX_N6
PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_N5
PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_N4
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3
PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
?
SKYLAKE_HALO
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
SKL-H (1/8)
SKL-H (1/8)
Document Number Re v
Document Number Re v
Document Number Re v
SKL-H (1/8)
LA-C841P
LA-C841P
LA-C841P
6 74Tuesday, September 08, 2015
6 74Tuesday, September 08, 2015
6 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
12
RC13551_0402_5%
12
RC33551_0402_5%
12
RC30651_0402_5%
PCH_JTAG_TMS <20>
PCH_JTAG_TDI <20>
PCH_JTAG_TDO <20>
PCH_JTAGX <20>
PCH_XDP_PREQ# <22>
PCH_XDP_PRDY# <22>
+1.0V_PRIM_XDP
+3.3V_ALW_PCH
+1.0V_VCCSTG
XDP_DBRESET#
CFG0
CFG2
CFG4
CFG5
CFG6
CFG7
+3.3V_SPI
12
RC5
2.2K_0402_5%
0.1U_0402_25V6
CC35
12
XDP@
12
RC321
@
1K_0402_5%
12
RC181
1K_0402_5%
12
RC322
1K_0402_5%
12
Litho@
RC323
1K_0402_5%
12
RC324
@
1K_0402_5%
12
RC325
@
1K_0402_5%
SYS_PWROK_R
0.1U_0402_25V6
12
CC36@
Stall reset sequence after PCU
PLL lock until de-asserted
No Stall
Stall
1
0
PEG LANE REVERSAL
*
NORMAL
LANE
REVERSE D
1
0
eDP enable
Disable d
Enabled
PCI Express* Bifurcation
1x8, 2x4
Reserved
2x8
1x16
PEG Training
(default) PEG Train
immediately following
RESET# de-assertion
PEG Wait for BIOS for
trai ning
1
0
[6:5 ]
00
01
10
11
1
0
+1.0V_PRIM
RC216 0_0603_1%@
D D
T191
10/23 Intel review
+1.0V_PRIM_XDP
12
+1.0VS_VCCIO
C C
+1.0V_VCCST
1 2
RC329 150_0402_5%@
1 2
RC328 10K_0402_5%@
+1.0V_VCCST
+1.0V_VCCSTG
1 2
RC180 1K_0402_5%
B B
VR_SVID_DATA<63>
VR_SVID_ALERT#<63>
A A
RC13851_0402_5% @
12
RC132150_0402_5%
FIVR_EN
FIVR_EN
12
RC3261K_0402_5%
12
RC1661K_0402_5% @
12
RC1641K_0402_5%
12
RC17249.9_0402_1% @
VR_SVID_DATA
VR_SVID_ALERT#
1 2
@
PAD~D
SIO_PWRBTN#<20,36>
CPU_XDP_PREQ#
FIVR_EN_R
H_THERMTRIP#
PCH_JTAGX
VCCST_PWRGD
H_CATERR#
H_PROCHOT#
+1.0V_VCCST
12
12
+1.0V_PRIM_XDP
+1.0V_PRIM_XDP
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
12
CC37
CC33
PCH_RSMRST#_R H_VCCST_PWRGD_XDP
CFG0
PCH_SPI_D0<19>
RESET_OUT#<20,36>
1 2
RC124
XDP@ 1K_0402_5%
FIVR_EN
PCH_JTAG_TCK<20>
PCH_RSMRST#<36>
RC217 0_0402_5%@ 1 2
RC126 1K_0402_5%XDP@ 1 2
RC128 0_0402_5%XDP@ 1 2
1 2
RC129 0_0402_5%@
DDR_XDP_WAN_SMBDAT<14,15,20,45>
DDR_XDP_WAN_SMBCLK<14,15,20,45>
PCH_RSMRST#
ALW_PWRGD_3V_5V<58>
CPU_XDP_PREQ#
CPU_XDP_PRDY#
10/23 Intel review
10/23 Intel review
PCH_CPU_PCIBCLK_R_D<18>
PCH_CPU_PCIBCLK_R_D#<18>
56.2_0402_1%
100_0402_5%
12
RC155
220_0402_5%
RC157
RC156
VR_SVID_DATA
CPU_VIDALERT#
VR_SVID_CLK<63>
H_PROCHOT#<36,51,63,66,67>
DDR_VTT_CTRL<14>
VCCST_PWRGD<36>
H_PWRGD<20>
PLTRST_CPU#<16>
H_PM_SYNC_R<16>
H_PM_DOWN<16>
H_PECI<16,36>
H_THERMTRIP#< 14,15,16,36>
+1.0V_PRIM_XDP
CFG0
CFG1
CFG2
CFG3
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG5
CFG6
CFG7
SIO_PWRBTN#
FIVR_EN_R
SYS_PWROK_R
PCH_JTAG_TCK
CPU_XDP_TCLK
1
2
PCH_CPU_BCLK_R_D<18>
PCH_CPU_BCLK_R_D#<18>
CPU_24MHZ_R_D<18>
CPU_24MHZ_R_D#<18>
VR_SVID_CLK
H_PROCHOT#
RC158 499_0402_1%
DDR_VTT_CTRL
RC159 60.4_0402_1%
H_PWRGD
PLTRST_CPU#
H_PM_SYNC_R
RC167 30_0402_5%
H_PECI
RC168 20_0402_5%
RC319 0_0402_5%
RC171 0_0402_5%@
XDP_PRSNT_PIN1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
13
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
31
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
VCC_OBS_AB43VCC_OBS_CD
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
+3.3V_ALW
CH17
1 2
5
0.1U_0402_25V6
P
B
PM_RSMRST#_AND
4
O
A
G
UC4
3
TC7SH08FU_SSOP5~D
PCH_CPU_BCLK_R_D
PCH_CPU_BCLK_R_D#
PCH_CPU_PCIBCLK_R_D
PCH_CPU_PCIBCLK_R_D#
CPU_24MHZ_R_D
CPU_24MHZ_R_D#
1 2
1 2
1 2
1 2
1 2
RC169 0_0402_5%@
1 2
1 2
XDP@
CFG3
1 2
RC121 1K_0402_5%
1 2
RC122 0_0402_5%@
ITPCLK#/HOOK5
RESET#/HOOK6
RC154 0_0402_5%@
CPU_VIDALERT#
VR_SVID_DATA
H_PROCHOT#_R
VCCST_PWRGD_CPUVCCST_PWRGD
H_PM_SYNC
H_PM_DOWN_RH_PM_DOWN
H_THERMTRIP#_RH_THERMTRIP#
H_SKTOCC# CPU_XDP_PREQ#
SKL_CNL#
H_CATERR#
GND1
OBSFN_C0
OBSFN_C1
GND3
GND5
GND7
OBSFN_D0
OBSFN_D1
GND9
GND11
GND13
DBR#/HOOK7
GND15
TRST#
GND17
CONN@SAMTE_BSH-030-01-L-D-A
1 2
B31
A32
D35
C36
E31
D31
BH31
BH32
BH29
BR30
BT13
H13
BT31
BP35
BM34
BP31
BT34
J31
BR33
BN1
BM30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
TD0
54
56
TDI
58
TMS
60
CPU1E
BCLKP
BCLKN
PCI_BCLKP
PCI_BCLKN
CLK24P
CLK24N
VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#
DDR_VTT_CNTL
VCCST_PWRGD
PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#
SKTOCC#
PROC_SELECT#
CATERR#
SKL-H_BGA1440
+1.0V_PRIM_XDP
PCH_XDP_CLK_DP
PCH_XDP_CLK_DN
CPU_XDP_HOOK6
XDP_DBRESET#
CPU_XDP_TDO
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_PRS
PCH_RSMRST#_R
SKYLAKE_HALO
BGA1440
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
12
PCH_RSMRST#_R <20>
RC318
47K_0402_5%
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
CFG_RCOMP
PCH_XDP_CLK_DP <18>
PCH_XDP_CLK_DN <18>
1 2
RC144 0_0402_5%XDP@
XDP_DBRESET# <17>
CPU_XDP_TRST# <22>
1 2
RC127 1K_0402_5%XDP@
BN25
CFG[0]
BN27
CFG[1]
BN26
CFG[2]
BN28
CFG[3]
BR20
CFG[4]
BM20
CFG[5]
BT20
CFG[6]
BP20
CFG[7]
BR23
CFG[8]
BR22
CFG[9]
BT23
CFG[10]
BT22
CFG[11]
BM19
CFG[12]
BR19
CFG[13]
BP19
CFG[14]
BT19
CFG[15]
BN23
CFG[17]
BP23
CFG[16]
BP22
CFG[19]
BN22
CFG[18]
BR27
BPM#[0]
BT27
BPM#[1]
BM31
BPM#[2]
BT30
BPM#[3]
BT28
PROC_TDO
BL32
PROC_TDI
BP28
PROC_TMS
BR28
PROC_TCK
BP30
BL30
BP27
BT25
ITP_PMODE_CPU
PCH_SPI_D2_XDP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG17
CFG16
CFG19
CFG18
XDP_OBS0
XDP_OBS1
CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCLK
CPU_XDP_TRST#
CPU_XDP_PRDY#
12
RC222
49.9_0402_1%
SIO_PWRBTN#
1 2
1 2
RC312 0_0402_5%@
RC313 0_0402_5%@
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
ITP_PMODE_CPU <20>
PCH_SPI_D2_XDP <19>
+3.3V_ALW
1.5K_0402_5%
XDP@
12
RC241
0.1U_0402_25V6
XDP@
12
CC269
XDP_OBS0_R
XDP_OBS1_R
@
T184
@
T185
@
T180
@
T181
@
T179
@
T190
@
T189
CPU_XDP_HOOK6
10/23 I ntel review
XDP_DBRESET#
PCH_SPI_D0
EDS0.7
CPU_XDP_TDO
CPU_XDP_TRST#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TCLK
CPU_XDP_PREQ#
CPU_XDP_PRDY#
RC307 0_0402_5%@
RC308 0_0402_5%@
RC309 0_0402_5%@
RC143 0_0402_5%@
RC315 0_0402_5%@
RC314 0_0402_5%@
RC6 2.2K_0402_5%XDP@
RC316 1.5K_0402_5%XDP@
RC133 1.5K_0402_5%XDP@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKL-H (2/8)
SKL-H (2/8)
SKL-H (2/8)
Document Number Rev
Document Number Rev
Document Number Rev
LA-C841P
LA-C841P
LA-C841P
1
7 74Tuesday, September 08, 2015
7 74Tuesday, September 08, 2015
7 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
D D
C C
B B
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_A_CB0
DDR_A_CB1
DDR_A_CB2
DDR_A_CB3
DDR_A_CB4
DDR_A_CB5
DDR_A_CB6
DDR_A_CB7
CPU1A
BR6
DDR0_DQ[0]
BT6
DDR0_DQ[1]
BP3
DDR0_DQ[2]
BR3
DDR0_DQ[3]
BN5
DDR0_DQ[4]
BP6
DDR0_DQ[5]
BP2
DDR0_DQ[6]
BN3
DDR0_DQ[7]
BL4
DDR0_DQ[8]
BL5
DDR0_DQ[9]
BL2
DDR0_DQ[10]
BM1
DDR0_DQ[11]
BK4
DDR0_DQ[12]
BK5
DDR0_DQ[13]
BK1
DDR0_DQ[14]
BK2
DDR0_DQ[15]
BG4
DDR0_DQ[16]/DDR0_DQ[32]
BG5
DDR0_DQ[17]/DDR0_DQ[33]
BF4
DDR0_DQ[18]/DDR0_DQ[34]
BF5
DDR0_DQ[19]/DDR0_DQ[35]
BG2
DDR0_DQ[20]/DDR0_DQ[36]
BG1
DDR0_DQ[21]/DDR0_DQ[37]
BF1
DDR0_DQ[22]/DDR0_DQ[38]
BF2
DDR0_DQ[23]/DDR0_DQ[39]
BD2
DDR0_DQ[24]/DDR0_DQ[40]
BD1
DDR0_DQ[25]/DDR0_DQ[41]
BC4
DDR0_DQ[26]/DDR0_DQ[42]
BC5
DDR0_DQ[27]/DDR0_DQ[43]
BD5
DDR0_DQ[28]/DDR0_DQ[44]
BD4
DDR0_DQ[29]/DDR0_DQ[45]
BC1
DDR0_DQ[30]/DDR0_DQ[46]
BC2
DDR0_DQ[31]/DDR0_DQ[47]
AB1
DDR0_DQ[32]/DDR1_DQ[0]
AB2
DDR0_DQ[33]/DDR1_DQ[1]
AA4
DDR0_DQ[34]/DDR1_DQ[2]
AA5
DDR0_DQ[35]/DDR1_DQ[3]
AB5
DDR0_DQ[36]/DDR1_DQ[4]
AB4
DDR0_DQ[37]/DDR1_DQ[5]
AA2
DDR0_DQ[38]/DDR1_DQ[6]
AA1
DDR0_DQ[39]/DDR1_DQ[7]
V5
DDR0_DQ[40]/DDR1_DQ[8]
V2
DDR0_DQ[41]/DDR1_DQ[9]
U1
DDR0_DQ[42]/DDR1_DQ[10]
U2
DDR0_DQ[43]/DDR1_DQ[11]
V1
DDR0_DQ[44]/DDR1_DQ[12]
V4
DDR0_DQ[45]/DDR1_DQ[13]
U5
DDR0_DQ[46]/DDR1_DQ[14]
U4
DDR0_DQ[47]/DDR1_DQ[15]
R2
DDR0_DQ[48]/DDR1_DQ[32]
P5
DDR0_DQ[49]/DDR1_DQ[33]
R4
DDR0_DQ[50]/DDR1_DQ[34]
P4
DDR0_DQ[51]/DDR1_DQ[35]
R5
DDR0_DQ[52]/DDR1_DQ[36]
P2
DDR0_DQ[53]/DDR1_DQ[37]
R1
DDR0_DQ[54]/DDR1_DQ[38]
P1
DDR0_DQ[55]/DDR1_DQ[39]
M4
DDR0_DQ[56]/DDR1_DQ[40]
M1
DDR0_DQ[57]/DDR1_DQ[41]
L4
DDR0_DQ[58]/DDR1_DQ[42]
L2
DDR0_DQ[59]/DDR1_DQ[43]
M5
DDR0_DQ[60]/DDR1_DQ[44]
M2
DDR0_DQ[61]/DDR1_DQ[45]
L5
DDR0_DQ[62]/DDR1_DQ[46]
L1
DDR0_DQ[63]/DDR1_DQ[47]
BA2
DDR0_ECC[0]
BA1
DDR0_ECC[1]
AY4
DDR0_ECC[2]
AY5
DDR0_ECC[3]
BA5
DDR0_ECC[4]
BA4
DDR0_ECC[5]
AY1
DDR0_ECC[6]
AY2
DDR0_ECC[7]
DDR CHANNEL A
SKL-H_BGA1440
SKYLAKE_HALO
BGA1440
4
?
DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_CS#[2]
DDR0_CS#[3]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_ODT[2]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
1 OF 14
DDR0_ODT[3]
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
DDR0_ALERT#
DDR0_DQSN[0]
DDR0_DQSN[1]
DDR0_DQSP[0]
DDR0_DQSP[1]
DDR0_DQSP[8]
DDR0_DQSN[8]
?REV = 1
3
DDR_A_D16
DDR_A_CLK0 DDR_B_CLK#0
AG1
DDR_A_CLK#0
AG2
DDR_A_CLK#1 DDR_B_CLK1
AK1
DDR_A_CLK1
AK2
AL3
AK3
AL2
AL1
DDR_A_CKE0
AT1
DDR_A_CKE1
AT2
AT3
AT5
DDR_A_CS#0
AD5
DDR_A_CS#1
AE2
AD2
AE5
DDR_A_ODT0
AD3
DDR_A_ODT1
AE4
AE1
AD4
DDR_A_BA0
AH5
DDR_A_BA1
AH1
DDR_A_BG0
AU1
DDR_A_MA16
AH4
DDR_A_MA14
AG4
DDR_A_MA15
AD1
DDR_A_MA0
AH3
DDR_A_MA1
AP4
DDR_A_MA2
AN4
DDR_A_MA3
AP5
DDR_A_MA4
AP2
DDR_A_MA5
AP1
DDR_A_MA6
AP3
DDR_A_MA7
AN1
DDR_A_MA8
AN3
DDR_A_MA9
AT4
DDR_A_MA10
AH2
DDR_A_MA11
AN2
DDR_A_MA12
AU4
DDR_A_MA13
AE3
DDR_A_BG1
AU2
DDR_A_ACT#
AU3
DDR_A_PARITY
AG3
DDR_A_ALERT#
AU5
DDR_A_DQS#0
BR5
DDR_A_DQS#1
BL3
DDR_A_DQS#4
BG3
DDR_A_DQS#5
BD3
DDR_B_DQS0
AB3
DDR_B_DQS1
V3
DDR_B_DQS4
R3
DDR_B_DQS5
M3
DDR_A_DQS0
BP5
DDR_A_DQS1
BK3
DDR_A_DQS4
BF3
DDR_A_DQS5
BC3
DDR_B_DQS#0
AA3
DDR_B_DQS#1
U3
DDR_B_DQS#4
P3
DDR_B_DQS#5
L3
DDR_A_DQS8
AY3
DDR_A_DQS#8
BA3
DDR_A_CLK0 <14>
DDR_A_CLK#0 <14>
DDR_A_CLK#1 <14>
DDR_A_CLK1 <14>
DDR_A_CKE0 <14>
DDR_A_CKE1 <14>
DDR_A_CS#0 <14>
DDR_A_CS#1 <14>
DDR_A_ODT0 <14>
DDR_A_ODT1 <14>
DDR_A_BA0 <14>
DDR_A_BA1 <14>
DDR_A_BG0 <14>
DDR_A_BG1 <14>
DDR_A_ACT# <14>
DDR_A_PARITY <14>
DDR_A_ALERT# <14>
1 2
RD18 121_0402_1%
RD21 75_0402_1%
1 2
RD22 100_0402_1%
1 2
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_CB0
DDR_B_CB1
DDR_B_CB2
DDR_B_CB3
DDR_B_CB4
DDR_B_CB5
DDR_B_CB6
DDR_B_CB7
DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2
CPU1B
BT11
DDR1_DQ[0]/DDR0_DQ[16]
BR11
DDR1_DQ[1]/DDR0_DQ[17]
BT8
DDR1_DQ[2]/DDR0_DQ[18]
BR8
DDR1_DQ[3]/DDR0_DQ[19]
BP11
DDR1_DQ[4]/DDR0_DQ[20]
BN11
DDR1_DQ[5]/DDR0_DQ[21]
BP8
DDR1_DQ[6]/DDR0_DQ[22]
BN8
DDR1_DQ[7]/DDR0_DQ[23]
BL12
DDR1_DQ[8]/DDR0_DQ[24]
BL11
DDR1_DQ[9]/DDR0_DQ[25]
BL8
DDR1_DQ[10]/DDR0_DQ[26]
BJ8
DDR1_DQ[11]/DDR0_DQ[27]
BJ11
DDR1_DQ[12]/DDR0_DQ[28]
BJ10
DDR1_DQ[13]/DDR0_DQ[29]
BL7
DDR1_DQ[14]/DDR0_DQ[30]
BJ7
DDR1_DQ[15]/DDR0_DQ[31]
BG11
DDR1_DQ[16]/DDR0_DQ[48]
BG10
DDR1_DQ[17]/DDR0_DQ[49]
BG8
DDR1_DQ[18]/DDR0_DQ[50]
BF8
DDR1_DQ[19]/DDR0_DQ[51]
BF11
DDR1_DQ[20]/DDR0_DQ[52]
BF10
DDR1_DQ[21]/DDR0_DQ[53]
BG7
DDR1_DQ[22]/DDR0_DQ[54]
BF7
DDR1_DQ[23]/DDR0_DQ[55]
BB11
DDR1_DQ[24]/DDR0_DQ[56]
BC11
DDR1_DQ[25]/DDR0_DQ[57]
BB8
DDR1_DQ[26]/DDR0_DQ[58]
BC8
DDR1_DQ[27]/DDR0_DQ[59]
BC10
DDR1_DQ[28]/DDR0_DQ[60]
BB10
DDR1_DQ[29]/DDR0_DQ[61]
BC7
DDR1_DQ[30]/DDR0_DQ[62]
BB7
DDR1_DQ[31]/DDR0_DQ[63]
AA11
DDR1_DQ[32]/DDR1_DQ[16]
AA10
DDR1_DQ[33]/DDR1_DQ[17]
AC11
DDR1_DQ[34]/DDR1_DQ[18]
AC10
DDR1_DQ[35]/DDR1_DQ[19]
AA7
DDR1_DQ[36]/DDR1_DQ[20]
AA8
DDR1_DQ[37]/DDR1_DQ[21]
AC8
DDR1_DQ[38]/DDR1_DQ[22]
AC7
DDR1_DQ[39]/DDR1_DQ[23]
W8
DDR1_DQ[40]/DDR1_DQ[24]
W7
DDR1_DQ[41]/DDR1_DQ[25]
V10
DDR1_DQ[42]/DDR1_DQ[26]
V11
DDR1_DQ[43]/DDR1_DQ[27]
W11
DDR1_DQ[44]/DDR1_DQ[28]
W10
DDR1_DQ[45]/DDR1_DQ[29]
V7
DDR1_DQ[46]/DDR1_DQ[30]
V8
DDR1_DQ[47]/DDR1_DQ[31]
R11
DDR1_DQ[48]
P11
DDR1_DQ[49]
P7
DDR1_DQ[50]
R8
DDR1_DQ[51]
R10
DDR1_DQ[52]
P10
DDR1_DQ[53]
R7
DDR1_DQ[54]
P8
DDR1_DQ[55]
L11
DDR1_DQ[56]
M11
DDR1_DQ[57]
L7
DDR1_DQ[58]
M8
DDR1_DQ[59]
L10
DDR1_DQ[60]
M10
DDR1_DQ[61]
M7
DDR1_DQ[62]
L8
DDR1_DQ[63]
AW11
DDR1_ECC[0]
AY11
DDR1_ECC[1]
AY8
DDR1_ECC[2]
AW8
DDR1_ECC[3]
AY10
DDR1_ECC[4]
AW10
DDR1_ECC[5]
AY7
DDR1_ECC[6]
AW7
DDR1_ECC[7]
G1
DDR_RCOMP[0]
H1
DDR_RCOMP[1]
J2
DDR_RCOMP[2]
SKL-H_BGA1440
DDR CHANNEL B
REV = 1
2
?
SKYLAKE_HALO
BGA1440
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
2 OF 14
DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]
DDR1_MA[3]
DDR1_MA[4]
DDR1_PAR
DDR1_ALERT#
DDR1_DQSN[6]
DDR1_DQSN[7]
DDR1_DQSP[6]
DDR1_DQSP[7]
DDR1_DQSP[8]
DDR1_DQSN[8]
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
?
AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BP9
BL9
BG9
BC9
AC9
W9
R9
M9
BR9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_MA16
DDR_B_MA14
DDR_B_MA15
DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#
DDR_B_PARITY
DDR_B_ALERT#
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#7
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS8
DDR_B_DQS#8
1
DDR_B_CLK0 <15>
DDR_B_CLK#0 <15>
DDR_B_CLK#1 <15>
DDR_B_CLK1 <15>
DDR_B_CKE0 <15>
DDR_B_CKE1 <15>
DDR_B_CS#0 <15>
DDR_B_CS#1 <15>
DDR_B_ODT0 <15>
DDR_B_ODT1 <15>
DDR_B_BA0 <15>
DDR_B_BA1 <15>
DDR_B_BG0 <15>
DDR_B_BG1 <15>
DDR_B_ACT# <15>
DDR_B_PARITY <15>
DDR_B_ALERT# <15>
+DDR_VREF_CA
@
T199
PAD~D
+DDR_VREF_B_DQ
DDR_A_MA[0..16] <14>
DDR_B_MA[0..16] <15>
DDR_A_D[0..63]<14>
DDR_B_D[0..63]<15>
DDR_A_CB[0..7]<14>
A A
DDR_B_CB[0..7]<15>
DDR_A_DQS[0..8] <14>
DDR_B_DQS[0..8] <15>
DDR_A_DQS#[0..8] <14>
DDR_B_DQS#[0..8] <15>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SKL-H (3/8)
SKL-H (3/8)
Document Number Re v
Document Number Re v
Document Number Re v
SKL-H (3/8)
LA-C841P
LA-C841P
LA-C841P
1
8 74Tuesday, September 08, 2015
8 74Tuesday, September 08, 2015
8 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
CPU_DP1_P0<26>
CPU_DP1_N0<26>
CPU_DP1_P1<26>
DOCK, AR, HDMI
D D
DOCK, AR, WIGIG
C C
CPU_DP1_P2<26>
CPU_DP1_N2<26>
CPU_DP1_P3<26>
CPU_DP1_N3<26>
CPU_DP1_AUXP<26>
CPU_DP1_AUXN<26>
CPU_DP2_P0<27>
CPU_DP2_N0<27>
CPU_DP2_P1<27>
CPU_DP2_N1<27>
CPU_DP2_P2<27>
CPU_DP2_N2<27>
CPU_DP2_P3<27>
CPU_DP2_N3<27>
CPU_DP2_AUXP<27>
CPU_DP2_AUXN<27>
CPU_DP3_P0<28>
CPU_DP3_N0<28>
CPU_DP3_P1<28>
CPU_DP3_N1<28>
VGA
CPU_DP3_AUXP<28>
CPU_DP3_AUXN<28>
4
CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3
CPU_DP1_AUXP
CPU_DP1_AUXN
CPU_DP2_P0
CPU_DP2_N0
CPU_DP2_P1
CPU_DP2_N1
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_N3
CPU_DP2_AUXP
CPU_DP2_AUXN
CPU_DP3_P0
CPU_DP3_N0
CPU_DP3_P1
CPU_DP3_N1
CPU_DP3_AUXP
CPU_DP3_AUXN
CPU1D
K36
DDI1_TXP[0]
K37
DDI1_TXN[0]
J35
DDI1_TXP[1]
J34
DDI1_TXN[1]
H37
DDI1_TXP[2]
H36
DDI1_TXN[2]
J37
DDI1_TXP[3]
J38
DDI1_TXN[3]
D27
DDI1_AUXP
E27
DDI1_AUXN
H34
DDI2_TXP[0]
H33
DDI2_TXN[0]
F37
DDI2_TXP[1]
G38
DDI2_TXN[1]
F34
DDI2_TXP[2]
F35
DDI2_TXN[2]
E37
DDI2_TXP[3]
E36
DDI2_TXN[3]
F26
DDI2_AUXP
E26
DDI2_AUXN
C34
DDI3_TXP[0]
D34
DDI3_TXN[0]
B36
DDI3_TXP[1]
B34
DDI3_TXN[1]
F33
DDI3_TXP[2]
E33
DDI3_TXN[2]
C33
DDI3_TXP[3]
B33
DDI3_TXN[3]
A27
DDI3_AUXP
B27
DDI3_AUXN
SKL-H_BGA1440
3
SKYLAKE_HALO
BGA1440
4 OF 14
REV = 1
?
EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXP
EDP_AUXN
EDP_DISP_UTIL
EDP_RCOMP
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
2
EDP_TXP0
D29
EDP_TXN0
E29
EDP_TXP1
F28
EDP_TXN1CPU_DP1_N1
E28
B29
A29
B28
C28
EDP_AUXP
C26
EDP_AUXN
B26
A33
EDP_COMP
D37
G27
G25
G29
?
AUD_AZACPU_SDI AUD_AZACPU_SDI_R
@
PAD~D
AUD_AZACPU_SCLK
AUD_AZACPU_SDO
AUD_AZACPU_SDI
T194
1 2
RC66 20_0402_5%
EDP_TXP0 <30>
EDP_TXN0 <30>
EDP_TXP1 <30>
EDP_TXN1 <30>CPU_DP1_N1<26>
EDP_AUXP <30>
EDP_AUXN <30>
EDP_COMP
AUD_AZACPU_SCLK <20>
AUD_AZACPU_SDO <20>
1
+1.0VS_VCCIO
12
RC124.9_0402_1%
AUD_AZACPU_SDI_R <20>
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
2
Compal Electronics, Inc.
SKL-H (4/8)
SKL-H (4/8)
SKL-H (4/8)
LA-C841P
LA-C841P
LA-C841P
9 74Tuesday, September 08, 2015
9 74Tuesday, September 08, 2015
9 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
Vinafix.com
5
D D
4
3
2
1
+VCC_EDRAM
3.3A
+VCC_EDRAM_ED2
C C
+VCC_EOPIO
+VCC_EOPIO_ED2
B B
3.2A
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
CPU1J
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCOPC_SENSE
VSSOPC_SENSE
RSVD
RSVD
VCCEOPIO
VCCEOPIO
VCCEOPIO
RSVD
RSVD
RSVD
VCCEOPIO_SENSE
VSSEOPIO_SENSE
RSVD
RSVD
VCC_OPC_1P8
VCC_OPC_1P8
RSVD
RSVD
ZVM#
MSM#
ZVM2#
MSM2#
OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2
SKL-H_BGA1440
SKYLAKE_HALO
BGA1440
CPU1K
T1PAD~D @
T2PAD~D @
T3PAD~D @
T4PAD~D @
T5PAD~D @
T6PAD~D @
T7PAD~D @
T9PAD~D @
T10PAD~D @
T11PAD~D @
T8PAD~D @
T14PAD~D @
T13PAD~D @
T15PAD~D @
T12PAD~D @
PCH_2_CPU_TRIGGER<22>
CPU_2_PCH_TRIGGER<22>
PCH_2_CPU_TRIGGER
CPU_2_PCH_TRIGGER_R
TP_SKL_F30
T16PAD~D @
TP_SKL_E30
T17PAD~D @
T18PAD~D @
T19PAD~D @
T21PAD~D @
T20PAD~D @
T23PAD~D @ T47 PAD~D@
T24PAD~D @
T22PAD~D @
TP_SKL_F30
TP_SKL_E30
D1
RSVD_TP
E1
RSVD_TP
E3
RSVD_TP
E2
RSVD_TP
BR1
RSVD_TP
BT2
RSVD_TP
BN35
RSVD
J24
RSVD
H24
RSVD
BN33
RSVD
BL34
RSVD
N29
RSVD
R14
RSVD
AE29
RSVD
AA14
RSVD
A36
RSVD
A37
RSVD
H23
PROC_TRIGIN
J23
PROC_TRIGOUT
F30
RSVD
E30
RSVD
B30
RSVD
C30
RSVD
G3
RSVD
J3
RSVD
BR35
RSVD
BR31
RSVD
BH30
RSVD
SKL-H_BGA1440
1 2
RC177 30_0402_5%
1 2
RC178 0_0402_5%@
1 2
RC179 0_0402_5%@
CPU_2_PCH_TRIGGER_RCPU_2_PCH_TRIGGER
SKYLAKE_HALO
BGA1440
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
NCTF
NCTF
NCTF
NCTF
NCTF
NCTF
BM33
BL33
BJ14
BJ13
BK28
BJ28
BJ18
VSS
BJ16
BK16
BK24
BJ24
BK21
BJ21
BT17
BR17
BK18
VSS
BJ34
BJ33
G13
AJ8
BL31
B2
B38
BP1
BR2
C1
C38
T26 PAD~D@
T25 PAD~D@
T28 PAD~D@
T27 PAD~D@
T29 PAD~D@
T30 PAD~D@
T31 PAD~D@
T32 PAD~D@
T34 PAD~D@
T33 PAD~D@
T36 PAD~D@
T35 PAD~D@
T37 PAD~D@
T38 PAD~D@
T39 PAD~D@
T40 PAD~D@
T42 PAD~D@
T41 PAD~D@
T44 PAD~D@
T43 PAD~D@
T45 PAD~D@
T46 PAD~D@
T48 PAD~D@
T49 PAD~D@
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
SKL-H (5/8)
SKL-H (5/8)
Document Number Re v
Document Number Re v
Document Number Re v
SKL-H (5/8)
LA-C841P
LA-C841P
LA-C841P
1
10 74Tuesday, September 08, 2015
10 74Tuesday, September 08, 2015
10 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
+VCC_GT +VCC_SA
D D
C C
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ37
BJ38
BL36
BL37
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BT37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37
SKYLAKE_HALO
CPU1H
BGA1440
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKL-H_BGA1440
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
+VCC_GT
+1.0VS_VCCIO
AG12
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
CPU1I
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
SKL-H_BGA1440
SKYLAKE_HALO
BGA1440
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCPLL_OC
VCCPLL_OC
VCCST
VCCSTG
VCCSTG
VCCPLL
VCCPLL
VCCSA_SENSE
VSSSA_SENSE
VCCIO_SENSE
VSSIO_SENSE
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
+1.2V_MEM
12A
+VCC_FUSEPRG
+VCC_VDDQ_CLK
+VCC_SFR_OC
+1.0V_VCCST
+1.0V_VCCSTG
+1.0V_VCCSFR
VCC_SA_SENSE <63>
VSS_SA_SENSE <63>
VCC_IO_SENSE <61>
VSS_IO_SENSE <61>
RC218 0_0603_1%@
1 2
SIO_SLP_S3#<11,20,36,37,46,61,62>
SIO_SLP_SUS#<20,36,44,60,62>
SIO_SLP_S4#<1 1,20,36,37,59,71>
+1.0V_VCCSTG
+1.2V_MEM
12
CZ114 1U_0402_6.3V6K
+5V_ALW
1 2
RC305 0_0402_5%@
+3.3V_ALW
CZ115
@
1 2
5
0.1U_0402_10V7K
1
P
B
4
O
2
A
G
UC9
3
TC7SH08FU_SSOP5~D
+VCC_VDDQ_CLK +1.2V_MEM
PDDG page19, if don`t support DS3, contact to VDDQ directly
+VCC_SFR_OC
1 2
@
RC302 0_0402_5%
UZ26
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
VOUT
GND
6
5
@
CZ113 0.1U_0201_10V6K
1 2
+1.0V_VCCSTG +1.0V_VCCST
1 2
RC317 0_0402_5%@
B B
+1.0V_PRIM
+5V_ALW
0.1U_0402_25V6
1U_0402_6.3V6K
1
12
CZ88
2
+3.3V_ALW
C1421
@
1 2
0.1U_0402_25V6
5
1
RC320 0_0402_5%@
IN1
2
IN2
1 2
P
VCCSTG_ON
4
O
G
3
A A
SIO_SLP_S0#<20,37>
SIO_SLP_S3#<11,20,36,37,46,61,62>
SN74AHC1G08DCKR_SC70-5
UC1
5
@
CZ86
UZ19
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
VOUT
GND
+1.0V_VCCSTG
6
5
4
12
PJP1602
@
PAD-OPEN1x1m
+1.0V_VCCSTG_C
+1.0V_PRIM
1 2
CZ82 0.1U_0402_25V6@
SIO_SLP_S4#<11,20,36,37,59,71>
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
RC303 0_0402_5%@
1U_0402_6.3V6K
1
2
1 2
+5V_ALW
CZ107
0.1U_0402_25V6
12
VCCST_ON
@
CZ108
UZ18
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
ON
TPS22961DNYR_WSON8
1 2
RC220 0_0402_5%@
+1.0V_VCCST +1.0V_VCCSFR
VOUT
GND
6
5
+1.0V_VCCST_UZ18
12
@
PAD-OPEN1x1m
CZ63
0.1U_0402_25V6
PJP17
1 2
12
RC304 0_0402_5%@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SKL-H (6/8)
SKL-H (6/8)
Document Number Re v
Document Number Re v
Document Number Re v
SKL-H (6/8)
LA-C841P
LA-C841P
LA-C841P
1
11 74Tuesday, September 08, 2015
11 74Tuesday, September 08, 2015
11 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
D D
C C
+1.2V_MEM
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
1
B B
CC161
2
2
22U_0603_6.3V6M
12
CC81
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC170
2
22U_0603_6.3V6M
12
CC82
10U_0603_6.3V6M~D
1
1
CC168
CC164
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
CC84
CC83
+VCC_VDDQ_CLK +1.0V_VCCSTG
+1.0VS_VCCIO
PLACE CAP BACKSIDE
10U_0603_6.3V6M~D
1
1
CC166
CC163
2
2
1
2
12
+1.0V_VCCST
10U_0603_6.3V6M~D
1
CC171
2
10U_0603_6.3V6M~D
CC185
PLACE CAP BACKSIDE
22U_0603_6.3V6M
22U_0603_6.3V6M
CC188
CC189
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
CC194
CC193
1
1
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1
CC165
CC172
2
1
2
1U_0402_6.3V6K
2
1
22U_0603_6.3V6M
CC187
10U_0603_6.3V6M~D
CC167
PLACE CAP BACKSIDE
+1.0V_VCCSFR +1.0V_VCCST
1U_0402_6.3V6K
2
CC195
CC186
1
22U_0603_6.3V6M
CC272
12
+VCC_SFR_OC +VCC_GT +VCC_GTU
SKYLAKE_HALO
1U_0402_6.3V6K
1U_0402_6.3V6K
2
CC192
1
1U_0402_6.3V6K
2
CC191
1
1U_0402_6.3V6K
2
2
CC209
CC210
1
1
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
CPU1N
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
SKL-H_BGA1440
BGA1440
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGT_SENSE
VSSGTX_SENSE
VSSGT_SENSE
VCCGTX_SENSE
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH35
AH37
AH36
VCC_GT_SENSE <63>
VSS_GT_SENSE <63>
+VCC_CORE +VCC_CORE
SKYLAKE_HALO
CPU1G
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
RC221 49.9_0402_1%@
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SKL-H_BGA1440
1 2
BGA1440
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_SENSE
VSS_SENSE
VCC_SENSEVSS_SENSE
V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14
AG37
AG38
VCC_SENSE
VSS_SENSE
+VCC_CORE
12
12
RC140
100_0402_1%
RC141
100_0402_1%
VCC_SENSE <63>
VSS_SENSE <63>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
Date : Sheet o f
Compal Electronics, Inc.
SKL-H (7/8)
SKL-H (7/8)
Document Number Re v
Document Number Re v
Document Number Re v
SKL-H (7/8)
LA-C841P
LA-C841P
LA-C841P
1
12 74Tuesday, September 08, 2015
12 74Tuesday, September 08, 2015
12 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
SKYLAKE_HALO
CPU1F
BGA1440
Y38
VSS
Y37
W34
W33
W12
Y14
Y13
Y11
Y10
Y9
Y8
Y7
W5
W4
W3
W2
W1
V30
V29
V12
V6
U38
U37
U6
T34
T33
T14
T13
T12
T11
T10
T9
T8
T7
T5
T4
T3
T2
T1
R30
R29
R12
P38
P37
P12
P6
N34
N33
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
M14
M13
M12
M6
L34
L33
L30
L29
K38
K11
K10
K9
K8
K7
K5
K4
K3
K2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-H_BGA1440
NCTFVSS
REV = 1
D D
C C
B B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
4
?
K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27
D38
6 OF 14
BB4
BB3
BB2
BB1
BA38
BA37
BA12
BA11
BA10
BA9
BA8
BA7
BA6
B9
AY34
AY33
AY14
AY12
AW30
AW29
AW12
AW5
AW4
AW3
AW2
AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10
AU9
AU8
AU7
AU6
AT30
AT29
AT6
AR38
AR37
AR14
AR13
AR5
AR4
AR3
AR2
AR1
AP34
AP33
AP12
AP11
AP10
AP9
AP8
AN30
AN29
AN12
AN6
AN5
AM38
AM37
AM12
AM5
AM4
AM3
AM2
AM1
AL34
AL33
AL14
AL12
AL10
AL9
AL8
AL7
AL4
?
3
SKYLAKE_HALO
CPU1M
BGA1440
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-H_BGA1440
REV = 1
?
13 OF 14
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
?
SKYLAKE_HALO
CPU1L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-H_BGA1440
VSS
VSS
VSS
REV = 1
BGA1440
12 OF 14
BT32
BT26
BT24
BT21
BT18
BT14
BT12
BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12
BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12
BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12
BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12
BM9
BM6
BM2
BL29
BK29
BK15
BK14
BJ32
BJ31
BJ25
BJ22
BH14
BH12
BH9
BH8
BH5
BH4
BH1
BG38
BG13
BG12
BF33
BF12
BE29
BE6
BD9
BC34
BC12
BB12
C17
C13
BT9
BT5
BR7
BP7
BN9
BN7
BN4
BN2
C9
AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6
B37
B3
A34
A4
A3
?
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5
C2
BT36
BT35
BT4
BT3
BR38
?
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-H (8/8)
SKL-H (8/8)
Document Number Re v
Document Number Rev
Document Number Rev
SKL-H (8/8)
LA-C841P
LA-C841P
LA-C841P
13 74Tuesday, September 08, 2015
13 74Tuesday, September 08, 2015
13 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
5
Title
Title
Title
Size
Size
Size
Date : Sheet o f
Date : Sheet o f
4
3
Date : Sheet o f
2
Vinafix.com
5
4
3
2
1
12
12
10U_0603_6.3V6M
12
@
RD63
RD67
0_0402_5%
DDR_A_D[0..63]<8>
DDR_A_CB[0..7]<8>
DDR_A_D5 DDR_A_D4
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D9
DDR_A_D8
DDR_A_BA1<8>
DDR_A_MA14<8>
+2.5V_MEM
DDR_A_D15
DDR_A_D10
DDR_A_D33
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D42
DDR_A_D43
DDR_A_CB0
DDR_A_CB5
DDR_A_DQS#8
DDR_A_DQS8
DDR_A_CB6
DDR_A_CB7
DDR_A_CKE0
DDR_A_BG1
DDR_A_BG0
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA6
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_PARITY
DDR_A_BA1
DDR_A_CS#0
DDR_A_MA14
DDR_A_ODT0
DDR_A_CS#1
DDR_A_ODT1
T51PAD~D @
DDR_A_D17
DDR_A_D21
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19
DDR_A_D25
DDR_A_D26
DDR_A_D28
DDR_A_D29
DDR_A_D49
DDR_A_D50
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D55
DDR_A_D51
DDR_A_D60
DDR_A_D59
DDR_A_D61
+3.3V_RUN_DIMM1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
12
CD81
CD79
CD80
CD82
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD90
CD88
CD89
CD87
12
CD29
+3.3V_RUN+3.3V_RUN+3.3V_RUN
12
RD64
@
0_0402_5%
DIMM1_SA0
DIMM1_SA1
DIMM1_SA2
12
@
RD68
0_0402_5%
12
+2.5V_MEM
1
2
12
1U_0402_6.3V6K
1
CD70
2
+3.3V_RUN
12
1U_0402_6.3V6K
12
1
2
1U_0402_6.3V6K
CD83
10U_0603_6.3V6M
CD91
1
CD71
2
@
RD65
0_0603_5%
2.2U_0402_6.3V6M
CD31
4
1U_0402_6.3V6K
12
12
CD84
10U_0603_6.3V6M
CD92
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD72
2
+3.3V_RUN_DIMM1
0.1U_0201_10V6K
CD32
1
2
1U_0402_6.3V6K
CD85
10U_0603_6.3V6M
330U_D3_2.5VY_R6M
@
12
CD93
CD20
+
DDR_A_CB0<8>
DDR_A_CB5<8>
DDR_A_DQS#8<8>
DDR_A_DQS8<8>
DDR_A_CB6<8>
DDR_A_CB7<8>
DDR_A_CKE0<8>
DDR_A_BG1<8>
DDR_A_BG0<8>
DDR_A_CLK0<8>
DDR_A_CLK#0<8>
DDR_A_PARITY<8>
DDR_A_CS#0<8>
CD73
DDR_A_ODT0<8>
DDR_A_CS#1<8>
DDR_A_ODT1<8>
JDIMM1
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
75
DM3_n/DBI3_n
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
BELLW_SD-80886-1021
CONN@
3
EVENT_n/NF
CK1_c/NF
RAS_n/A16
CAS_n/A15
C0/CS2_n/NC
DM4_n/DBI4_n
DM6_n/DBI6_n
VSS2
VSS4
VSS6
VSS7
VSS9
VSS11
DQ12
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
RESET_n
CKE1
VDD2
ACT_n
ALERT_n
VDD4
VDD6
VDD8
VDD10
CK1_t/NF
VDD12
A10/AP
VDD14
VDD16
VDD18
VREFCA
VSS54
DQ36
VSS56
DQ32
VSS58
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
GND2
+1.2V_MEM+1.2V_MEM
2
4
DQ4
6
DDR_A_D0
8
DQ0
10
12
14
DDR_A_D6
16
DQ6
18
DDR_A_D7
20
DQ2
22
DDR_A_D12
24
26
DDR_A_D13
28
DQ8
30
DDR_A_DQS#1
32
DDR_A_DQS1
34
36
DDR_A_D14
38
40
DDR_A_D11
42
44
DDR_A_D32
46
48
DDR_A_D37
50
52
54
56
DDR_A_D38
58
60
DDR_A_D39
62
64
DDR_A_D44
66
68
DDR_A_D45
70
72
DDR_A_DQS#5
74
DDR_A_DQS5
76
78
DDR_A_D47
80
82
DDR_A_D46
84
86
DDR_A_CB1
88
90
DDR_A_CB4
92
94
96
98
DDR_A_CB3
100
102
DDR_A_CB2
104
106
DDR_DRAMRST#_R
108
DDR_A_CKE1
110
112
DDR_A_ACT#
114
DDR_A_ALERT#
116
118
DDR_A_MA11
120
A11
A7
A5
A4
A2
A0
BA0
A13
SA2
SDA
SA0
VTT
SA1
DDR_A_MA7
122
124
DDR_A_MA5
126
DDR_A_MA4
128
130
DDR_A_MA2
132
JDIMM1_EVENT#
134
136
DDR_A_CLK1
138
DDR_A_CLK#1
140
142
DDR_A_MA0
144
DDR_A_MA10
146
148
DDR_A_BA0
150
DDR_A_MA16
152
154
DDR_A_MA15
156
DDR_A_MA13
158
160
162
164
DIMM1_SA2
166
168
DDR_A_D16
170
172
DDR_A_D20
174
176
178
180
DDR_A_D23
182
184
DDR_A_D18
186
188
DDR_A_D30
190
192
DDR_A_D24
194
196
DDR_A_DQS#3
198
DDR_A_DQS3
200
202
DDR_A_D31
204
206
DDR_A_D27
208
210
DDR_A_D48
212
214
DDR_A_D54
216
218
220
222
DDR_A_D53
224
226
DDR_A_D52
228
230
DDR_A_D62
232
234
236
238
DDR_A_DQS#7
240
DDR_A_DQS7
242
244
DDR_A_D56
246
248
250
252
254
DIMM1_SA0
256
258
DIMM1_SA1
260
262
DDR_A_D57
DDR_A_D63DDR_A_D58
DDR_A_CB1 <8>
DDR_A_CB4 <8>
DDR_A_CB3 <8>
DDR_A_CB2 <8>
DDR_A_CKE1 <8>
DDR_A_ACT# <8>
DDR_A_ALERT# <8>
DDR_A_CLK1 <8>
DDR_A_CLK#1 <8>
DDR_A_BA0 <8>
DDR_A_MA16 <8>
DDR_A_MA15 <8>
T50 PAD~D@
+DDR_VREF_A_CA
DDR_XDP_WAN_SMBDAT <7,15,20,45>DDR_XDP_WAN_SMBCLK<7,15,20,45>
+0.6V_DDR_VTT
+DDR_VREF_A_CA
DDR_VTT_CTRL<7>
1
@
CD6
0.1U_0402_25V6
2
JDIMM1_EVENT#
1 2
@
RD29 0_0402_5%
RD61 1K_0402_5%@
UD1
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
+1.2V_MEM
470_0402_1%
12
RD2
DDR_DRAMRST#
+1.2V_MEM
1K_0402_1%
12
RD9
1 2
RD19 2_0402_1%
1K_0402_1%
12
RD20
24.9_0402_1%
1 2
9/17 delete ODT Genertation, connect directly to CPU
refer 546765_2014WW37_SkylakeU_Y_MOW_Rev_1_0
+1.2V_MEM
1 2
5
VCC
CD30@0.1U_0201_10V6K
4
Y
RD30 100K_0402_5%
1 2
H_THERMTRIP# <7,15,16,36>
0.6V_DDR_VTT_ON <59>
RD16
12
12
+3.3V_ALW
DDR4_DRAMRST#_PCH <20>DDR_DRAMRST#_R<15>
+DDR_VREF_CA+DDR_VREF_A_CA
0.022U_0402_25V7K
CD36
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
2
Date: Sheet o f
Compal Electronics, Inc.
DDR4
DDR4
Document Number Rev
Document Number Rev
Document Number Rev
DDR4
LA-C841P
LA-C841P
LA-C841P
1
14 74Tuesday, September 08, 2015
14 74Tuesday, September 08, 2015
14 74Tuesday, September 08, 2015
0.1
0.1
0.1
DDR_A_DQS#[0..8]<8>
DDR_A_DQS[0..8]<8>
DDR_A_MA[0..16]<8>
D D
+1.2V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD9
CD8
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
CD15
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CD25
1
1
2
2
12
CD4
CD17
12
CD26
CD7
CD12
1U_0402_6.3V6K
12
10U_0603_6.3V6M
12
1U_0402_6.3V6K
12
CD2
CD3
10U_0603_6.3V6M
CD13
CD14
12
+0.6V_DDR_VTT
1
2
12
12
1U_0402_6.3V6K
CD24
5
1U_0402_6.3V6K
12
+1.2V_MEM
10U_0603_6.3V6M
12
C C
B B
A A
1U_0402_6.3V6K
CD10
10U_0603_6.3V6M
1
2
12
12
12
CD18
12
1U_0402_6.3V6K
CD27
RD62
@
0_0402_5%
@
RD66
0_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD11
CD78
10U_0603_6.3V6M
10U_0603_6.3V6M
CD86
CD19
12
10U_0603_6.3V6M
12
CD28
12
@
0_0402_5%
12
@
Vinafix.com
5
4
3
2
1
JDIMM2
1
VSS1
3
DQ5
5
VSS3
7
DQ1
9
VSS5
DQS0_c11DM0_n/DBI0_n
13
DQS0_t
15
VSS8
17
DQ7
19
VSS10
21
DQ3
23
VSS12
25
DQ13
27
VSS14
29
DQ9
31
VSS16
33
DM1_n/DBI_n
35
VSS17
37
DQ15
39
VSS19
41
DQ10
43
VSS21
45
DQ21
47
VSS23
49
DQ17
51
VSS25
DQS2_c53DM2_n/DBI2_n
55
DQS2_t
57
VSS28
59
DQ23
61
VSS30
63
DQ19
65
VSS32
67
DQ29
69
VSS34
71
DQ25
73
VSS36
75
DM3_n/DBI3_n
77
VSS37
79
DQ30
81
VSS39
83
DQ26
85
VSS41
87
CB5/NC
89
VSS43
91
CB1/NC
93
VSS45
DQS8_c95DM8_n/DBI_n/NC
97
DQS8_t
99
VSS48
101
CB2/NC
103
VSS50
105
CB3/NC
107
VSS52
109
CKE0
111
VDD1
113
BG1
115
BG0
117
VDD3
119
A12
121
A9
123
VDD5
125
A8
127
A6
129
VDD7
131
A3
133
A1
135
VDD9
137
CK0_t
139
CK0_c
141
VDD11
143
PARITY
145
BA1
147
VDD13
149
CS0_n
151
WE_n/A14
153
VDD15
155
ODT0
157
CS1_n
159
VDD17
161
ODT1
163
VDD19
165
C1, CS3_n,NC
167
VSS53
169
DQ37
171
VSS55
173
DQ33
175
VSS57
177
DQS4_c
179
DQS4_t
181
VSS60
183
DQ38
185
VSS62
187
DQ34
189
VSS64
191
DQ44
193
VSS66
195
DQ40
197
VSS68
199
DM5_n/DBI5_n
201
VSS69
203
DQ46
205
VSS71
207
DQ42
209
VSS73
211
DQ52
213
VSS75
215
DQ49
217
VSS77
219
DQS6_c
221
DQS6_t
223
VSS80
225
DQ55
227
VSS82
229
DQ51
231
VSS84
233
DQ61
235
VSS86
237
DQ56
239
VSS88
241
DM7_n/DBI7_n
243
VSS89
245
DQ62
247
VSS91
249
DQ58
251
VSS93
253
SCL
255
VDDSPD
257
VPP1
259
VPP2
261
GND1
BELLW_SD-80886-1021
CONN@
3
RESET_n
EVENT_n/NF
CK1_c/NF
RAS_n/A16
CAS_n/A15
C0/CS2_n/NC
DM4_n/DBI4_n
DM6_n/DBI6_n
1U_0402_6.3V6K
12
10U_0603_6.3V6M
12
RD71
@
0_0402_5%
DIMM2_SA0
DIMM2_SA1
DIMM2_SA2
@
RD74
0_0402_5%
DDR_B_D[0..63]<8>
DDR_B_CB[0..7]<8>
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD105
10U_0603_6.3V6M
CD97
1U_0402_6.3V6K
1
CD74
2
+3.3V_RUN
12
12
1
2
12
12
12
CD106
10U_0603_6.3V6M
CD98
12
1U_0402_6.3V6K
CD75
@
RD60
0_0603_5%
+3.3V_RUN_DIMM2
2.2U_0402_6.3V6M
1
CD63
2
4
12
CD104
CD103
10U_0603_6.3V6M
CD96
CD95
12
+2.5V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD109
CD107
CD108
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD99
12
10U_0603_6.3V6M
1
1
CD76
2
2
0.1U_0201_10V6K
CD64
330U_D3_2.5VY_R6M
12
CD100
CD101
12
+
10U_0603_6.3V6M
CD77
DDR_B_CB6<8>
@
DDR_B_CB2<8>
CD53
DDR_B_DQS#8<8>
DDR_B_DQS8<8>
DDR_B_CB7<8>
DDR_B_CB3<8>
DDR_B_CKE0<8>
DDR_B_BG1<8>
DDR_B_BG0<8>
DDR_B_CLK0<8>
DDR_B_CLK#0<8>
DDR_B_PARITY<8>
DDR_B_BA1<8>
DDR_B_CS#0<8>
DDR_B_MA14<8>
DDR_B_ODT0<8>
DDR_B_CS#1<8>
DDR_B_ODT1<8>
+2.5V_MEM
DDR_B_DQS#[0..8]<8>
DDR_B_DQS[0..8]<8>
DDR_B_MA[0..16]<8>
D D
+1.2V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
12
12
+1.2V_MEM
10U_0603_6.3V6M
C C
B B
A A
12
CD37
CD45
12
CD38
10U_0603_6.3V6M
CD46
12
+0.6V_DDR_VTT
CD39
10U_0603_6.3V6M
CD47
12
1U_0402_6.3V6K
CD57
1
2
5
1U_0402_6.3V6K
12
12
CD41
CD40
CD42
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD50
CD48
CD49
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD58
CD59
1
1
1
2
2
2
12
@
RD69
0_0402_5%
12
@
RD72
0_0402_5%
12
12
CD60
1U_0402_6.3V6K
10U_0603_6.3V6M
CD43
CD51
12
12
12
10U_0603_6.3V6M
12
12
@
0_0402_5%
1U_0402_6.3V6K
CD44
10U_0603_6.3V6M
CD52
CD61
12
@
RD70
0_0402_5%
RD73
1U_0402_6.3V6K
12
CD102
10U_0603_6.3V6M
CD94
12
10U_0603_6.3V6M
@
CD62
+3.3V_RUN+3.3V_RUN+3.3V_RUN
12
12
DDR_B_D0
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D12
DDR_B_D9
DDR_B_D11
DDR_B_D10
DDR_B_D38
DDR_B_D32
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D37
DDR_B_D40
DDR_B_D44
DDR_B_D42
DDR_B_CB6
DDR_B_CB2
DDR_B_DQS#8
DDR_B_DQS8
DDR_B_CB7
DDR_B_CB3
DDR_B_CKE0
DDR_B_BG1
DDR_B_BG0
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA6
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_PARITY
DDR_B_BA1
DDR_B_CS#0
DDR_B_MA14
DDR_B_ODT0
DDR_B_CS#1
DDR_B_ODT1
T55PAD~D @
DDR_B_D22
DDR_B_D23
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D17
DDR_B_D16
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D51
DDR_B_D54
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D53
DDR_B_D49
DDR_B_D62
DDR_B_D59
DDR_B_D60
DDR_B_D56
+3.3V_RUN_DIMM2
VSS2
VSS4
VSS6
VSS7
VSS9
VSS11
DQ12
VSS13
VSS15
DQS1_c
DQS1_t
VSS18
DQ14
VSS20
DQ11
VSS22
DQ20
VSS24
DQ16
VSS26
VSS27
DQ22
VSS29
DQ18
VSS31
DQ28
VSS33
DQ24
VSS35
DQS3_c
DQS3_t
VSS38
DQ31
VSS40
DQ27
VSS42
CB4/NC
VSS44
CB0/NC
VSS46
VSS47
CB6/NC
VSS49
CB7/NC
VSS51
CKE1
VDD2
ACT_n
ALERT_n
VDD4
VDD6
VDD8
VDD10
CK1_t/NF
VDD12
A10/AP
VDD14
VDD16
VDD18
VREFCA
VSS54
DQ36
VSS56
DQ32
VSS58
VSS59
DQ39
VSS61
DQ35
VSS63
DQ45
VSS65
DQ41
VSS67
DQS5_c
DQS5_t
VSS70
DQ47
VSS72
DQ43
VSS74
DQ53
VSS76
DQ48
VSS78
VSS79
DQ54
VSS81
DQ50
VSS83
DQ60
VSS85
DQ57
VSS87
DQS7_c
DQS7_t
VSS90
DQ63
VSS92
DQ59
VSS94
GND2
+1.2V_MEM+1.2V_MEM
2
DDR_B_D1
4
DQ4
6
DDR_B_D5
8
DQ0
10
12
14
DDR_B_D2
16
DQ6
18
DDR_B_D6
20
DQ2
22
DDR_B_D8
24
26
DDR_B_D13
28
DQ8
30
DDR_B_DQS#1
32
DDR_B_DQS1
34
36
DDR_B_D14
38
40
DDR_B_D15
42
44
DDR_B_D36
46
48
DDR_B_D34
50
52
54
56
DDR_B_D33
58
60
DDR_B_D39
62
64
DDR_B_D45
66
68
DDR_B_D41
70
72
DDR_B_DQS#5
74
DDR_B_DQS5
76
78
DDR_B_D43DDR_B_D46
80
82
DDR_B_D47
84
86
DDR_B_CB1
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
A11
122
A7
124
126
A5
128
A4
130
132
A2
134
136
138
140
142
144
A0
146
148
150
BA0
152
154
156
158
A13
160
162
164
166
SA2
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
SDA
256
SA0
258
VTT
260
SA1
262
DDR_B_CB4
DDR_B_CB0
DDR_B_CB5
DDR_DRAMRST#_R
DDR_B_CKE1
DDR_B_ACT#
DDR_B_ALERT#
DDR_B_MA11
DDR_B_MA7
DDR_B_MA5
DDR_B_MA4
DDR_B_MA2
JDIMM2_EVENT#
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_MA0
DDR_B_MA10
DDR_B_BA0
DDR_B_MA16
DDR_B_MA15
DDR_B_MA13
DIMM2_SA2
DDR_B_D19
DDR_B_D18
DDR_B_D21
DDR_B_D20
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D30
DDR_B_D52
DDR_B_D48
DDR_B_D55
DDR_B_D50
DDR_B_D61
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D58
DIMM2_SA0
DIMM2_SA1
DDR_B_CB1 <8>
DDR_B_CB4 <8>
DDR_B_CB0 <8>
DDR_B_CB5 <8>
DDR_B_CKE1 <8>
DDR_B_ACT# <8>
DDR_B_ALERT# <8>
DDR_B_CLK1 <8>
DDR_B_CLK#1 <8>
DDR_B_BA0 <8>
DDR_B_MA16 <8 >
DDR_B_MA15 <8>
T54 PAD~D@
+DDR_VREF_B_CA
DDR_XDP_WAN_SMBDAT <7,14,20,45>DDR_XDP_WAN_SMBCLK<7,14,20,45>
+0.6V_DDR_VTT
+DDR_VREF_B_CA
JDIMM2_EVENT#
+DDR_VREF_B_CA
RD4 1K_0402_5%@
1
@
CD35
0.1U_0402_25V6
2
1 2
DDR_DRAMRST#_R <14>
+1.2V_MEM
1K_0402_1%
12
RD43
1 2
RD75 2_0402_1%
1K_0402_1%
12
RD24
H_THERMTRIP# <7,14,16,36>
+DDR_VREF_B_DQ
0.022U_0402_25V7K
CD54
12
24.9_0402_1%
12
RD25
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
2
Date: Sheet o f
Compal Electronics, Inc.
DDR4
DDR4
Document Number Rev
Document Number Rev
Document Number Rev
DDR4
LA-C841P
LA-C841P
LA-C841P
1
15 74Tuesday, September 08, 2015
15 74Tuesday, September 08, 2015
15 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
PCH_CL_CLK1<33>
PCH_CL_DATA1<33>
D D
C C
+3.3V_ALW_PCH
RH341 10K_0402_5%
+3.3V_RUN
RH319 10K_0402_5%
RH318 10K_0402_5%
RH324 10K_0402_5%
RH76 10K_0402_5%
RH344 10K_0402_5%
RH90 10K_0402_5%
RH323 10K_0402_5%
@
RH325 10K_0402_5%
RH326 10K_0402_5%
@
@
RH322 10K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
TBT_CIO_PLUG_EVENT#
CAM_MIC_CBL_DET#
M2_SLOT2_PCIE#_SATA
HDD_DET#
BIOS_REC
IFDET_SATA#_PCIE
CONTACTLESS_DET#
SATAGP3
SATAGP5
SATAGP6
SATAGP7
M.2 2280 SSD
M.2 2280 SSD
PCH_CL_RST1#<33>
CAM_MIC_CBL_DET#<30>
TBT_CIO_PLUG_EVENT#<46>
CONTACTLESS_DET#<37>
PCIE_PTX_DRX_P11<38>
PCIE_PTX_DRX_N11<38>
PCIE_PRX_DTX_P11<38>
PCIE_PRX_DTX_N11<38>
1 2
RH342 0_0402_5%
@
PCIE_PTX_DRX_N14<33>
PCIE_PTX_DRX_P14<33>
PCIE_PRX_DTX_N14<33>
PCIE_PRX_DTX_P14<33>
PCIE_PTX_DRX_P12<38>
PCIE_PTX_DRX_N12<38>
PCIE_PRX_DTX_P12<38>
PCIE_PRX_DTX_N12<38>
PCH_CL_CLK1
PCH_CL_DATA1
PCH_CL_RST1#
CAM_MIC_CBL_DET#
TBT_CIO_PLUG_EVENT#
CONTACTLESS_DET#
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
BIOS_REC
CS_CTR
PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12
UH1C
AV2
CL_CLK
AV3
CL_DATA
AW2
CL_RST#
R44
GPP_G8/FAN_PWM_0
R43
GPP_G9/FAN_PWM_1
U39
GPP_G10/FAN_PWM_2
N42
GPP_G11/FAN_PWM_3
U43
GPP_G0/FAN_TACH_0
U42
GPP_G1/FAN_TACH_1
U41
GPP_G2/FAN_TACH_2
M44
GPP_G3/FAN_TACH_3
U36
GPP_G4/FAN_TACH_4
P44
GPP_G5/FAN_TACH_5
T45
GPP_G6/FAN_TACH_6
T44
GPP_G7/FAN_TACH_7
B33
PCIE11_TXP
C33
PCIE11_TXN
K31
PCIE11_RXP
L31
PCIE11_RXN
AB33
GPP_F10/SCLOCK
AB35
GPP_F11/SLOAD
AA44
GPP_F13/SDATAOUT0
AA45
GPP_F12/SDATAOUT1
B38
PCIE14_TXN/SATA1B_TXN
C38
PCIE14_TXP/SATA1B_TXP
D39
PCIE14_RXN/SATA1B_RXN
E37
PCIE14_RXP/SATA1B_RXP
C36
PCIE13_TXN/SATA0B_TXN
B36
PCIE13_TXP/SATA0B_TXP
G35
PCIE13_RXN/SATA0B_RXN
E35
PCIE13_RXP/SATA0B_RXP
A35
PCIE12_TXP
B35
PCIE12_TXN
H33
PCIE12_RXP
G33
PCIE12_RXN
J45
PCIE20_TXP/SATA7_TXP
K44
PCIE20_TXN/SATA7_TXN
N38
PCIE20_RXP/SATA7_RXP
N39
PCIE20_RXN/SATA7_RXN
H44
PCIE19_TXP/SATA6_TXP
H43
PCIE19_TXN/SATA6_TXN
L39
PCIE19_RXP/SATA6_RXP
L37
PCIE19_RXN/SATA6_RXN
SKL-H-PCH_BGA837
SPT-H_PCH
PCIE_PRX_DTX_N9
THERMTRIP#
PM_SYNC
PM_DOWN
3 OF 12REV = 1.3
G31
PCIE_PRX_DTX_P9
H31
PCIE_PTX_DRX_N9
C31
PCIE_PTX_DRX_P9
B31
PCIE_PRX_DTX_N10
G29
PCIE_PRX_DTX_P10
E29
PCIE_PTX_DRX_N10
C32
PCIE_PTX_DRX_P10
B32
SATA_PRX_DTX_N2
F41
SATA_PRX_DTX_P2
E41
SATA_PTX_DRX_N2
B39
SATA_PTX_DRX_P2
A39
SATA_PRX_DTX_N3
D43
SATA_PRX_DTX_P3
E42
SATA_PTX_DRX_N3
A41
SATA_PTX_DRX_P3
A40
H42
H40
E45
F45
K37
G37
G45
G44
PCH_SATA_LED#
AD44
IFDET_SATA#_PCIE
AG36
M2_SLOT2_PCIE#_SATA
AG35
HDD_DET#
AG39
SATAGP3
AD35
AD31
SATAGP5
AD38
SATAGP6
AC43
SATAGP7
AB44
BIA_PWM_PCH
W36
PANEL_BKEN_PCH
W35
ENVDD_PCH
W42
PCH_THERMTRIP#
AJ3
PCH_PECI H_PECI
AL3
PECI
H_PM_SYNC_R
AJ4
PLTRST_CPU#
AK2
H_PM_DOWN
AH2
CLINK
FAN
PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP
PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
PCIe/SATA
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
GPP_E8/SATALED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
HOST
PLTRST_PROC#
PCIE_PRX_DTX_N9 <38>
PCIE_PRX_DTX_P9 <38>
PCIE_PTX_DRX_N9 <38>
PCIE_PTX_DRX_P9 <38>
PCIE_PRX_DTX_N10 <38>
PCIE_PRX_DTX_P10 <38>
PCIE_PTX_DRX_N10 <38>
PCIE_PTX_DRX_P10 <38>
SATA_PRX_DTX_N2 <45>
SATA_PRX_DTX_P2 <45>
SATA_PTX_DRX_N2 <45>
SATA_PTX_DRX_P2 <45>
SATA_PRX_DTX_N3 <41>
SATA_PRX_DTX_P3 <41>
SATA_PTX_DRX_N3 <41>
SATA_PTX_DRX_P3 <41>
PCH_SATA_LED# <38 ,43>
IFDET_SATA#_PCIE <38>
M2_SLOT2_PCIE#_SATA <35>
HDD_DET# <45>
Reser ve
Reser ve
Reser ve
BIA_PWM_PCH <30>
PANEL_BKEN_PCH <30>
ENVDD_PCH <30,36>
1 2
1 2
RH75 620_0402_5%
RH73 43_0402_1%
H_PM_SYNC_R <7>
PLTRST_CPU# <7>
H_PM_DOWN <7>
M.2 2280 SSD
SATA HDD
E DOCK ESATA
SPSGP0
SPSGP1
SPSGP2
SPSGP31SATAGP3 0=SATA 1=PCIE
PCH_PECI
IFDET_SATA #_PCIE
11M2_SLOT2_PC IE#_SA TA
HDD_DET#
0
H_THERMTRIP# <7,14,15,36>
H_PECI <7,36>
12
@
RH74
10K_0402_5%
0=SATA
1=PCIE
1=SATA
0=PCIE
0=SATA 1=PCIE
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (1/9)
SKYLAKE PCH-H (1/9)
Document Number Rev
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (1/9)
LA-C841P
LA-C841P
LA-C841P
1
16 74Tuesday, September 08, 2015
16 74Tuesday, September 08, 2015
16 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
XDP_DBRESET#<7>
RH70 8.2K_0402_5%@
D D
ME_RESET#
12
CIS LINK OK
4
1 2
RH66@ 0_0402_5%
+3.3V_RUN
CH10
@
1 2
5
0.1U_0402_25V6
1
P
B
4
Y
2
A
G
@
74AHC1G09GW_TSSOP5
3
3
UC3
SYS_RESET#
SYS_RESET# <20,37>
2
1
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_P0<6>
DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_P0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_P1<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_P1<6>
DMI_CTX_PRX_N2<6>
C C
B B
AR
DMI_CTX_PRX_P2<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_P2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P3<6>
1 2
RH192 100_0402_1%
PCIE_PRX_DTX_N1<33>
PCIE_PRX_DTX_P1<33>
PCIE_PTX_DRX_N1<33>
PCIE_PTX_DRX_P1<33>
PCIE_PTX_DRX_N2<33>
PCIE_PTX_DRX_P2<33>
PCIE_PRX_DTX_N2<33>
PCIE_PRX_DTX_P2<33>
PCIE_PRX_DTX_N3<32>
PCIE_PRX_DTX_P3<32>
PCIE_PTX_DRX_N3<32>
PCIE_PTX_DRX_P3<32>
PCIE_PRX_DTX_N4<31>
PCIE_PRX_DTX_P4<31>
PCIE_PTX_DRX_N4<31>
PCIE_PTX_DRX_P4<31>
PCIE_PRX_DTX_N5<46>
PCIE_PRX_DTX_P5<46>
PCIE_PTX_DRX_N5<46>
PCIE_PTX_DRX_P5<46>
PCIE_PRX_DTX_N6<46>
PCIE_PRX_DTX_P6<46>
PCIE_PTX_DRX_N6<46>
PCIE_PTX_DRX_P6<46>
PCIE_PRX_DTX_N7<46>
PCIE_PRX_DTX_P7<46>
PCIE_PTX_DRX_N7<46>
PCIE_PTX_DRX_P7<46>
PCIE_PRX_DTX_N8<46>
PCIE_PRX_DTX_P8<46>
PCIE_PTX_DRX_N8<46>
PCIE_PTX_DRX_P8<46>
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
PCIECOMP#
PCIECOMP
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6
PCIE_PTX_DRX_P6
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7
PCIE_PTX_DRX_N7
PCIE_PTX_DRX_P7
PCIE_PRX_DTX_N8
PCIE_PRX_DTX_P8
PCIE_PTX_DRX_N8
PCIE_PTX_DRX_P8
UH1B
L27
DMI_RXN0
N27
DMI_RXP0
C27
DMI_TXN0
B27
DMI_TXP0
E24
DMI_RXN1
G24
DMI_RXP1
B28
DMI_TXN1
A28
DMI_TXP1
G27
DMI_RXN2
E26
DMI_RXP2
B29
DMI_TXN2
C29
DMI_TXP2
L29
DMI_RXN3
K29
DMI_RXP3
B30
DMI_TXN3
A30
DMI_TXP3
B18
PCIE_RCOMPN
C17
PCIE_RCOMPP
H15
PCIE1_RXN/USB3_7_RXN
G15
PCIE1_RXP/USB3_7_RXP
A16
PCIE1_TXN/USB3_7_TXN
B16
PCIE1_TXP/USB3_7_TXP
B19
PCIE2_TXN/USB3_8_TXN
C19
PCIE2_TXP/USB3_8_TXP
E17
PCIE2_RXN/USB3_8_RXN
G17
PCIE2_RXP/USB3_8_RXP
L17
PCIE3_RXN/USB3_9_RXN
K17
PCIE3_RXP/USB3_9_RXP
B20
PCIE3_TXN/USB3_9_TXN
C20
PCIE3_TXP/USB3_9_TXP
E20
PCIE4_RXN/USB3_10_RXN
G19
PCIE4_RXP/USB3_10_RXP
B21
PCIE4_TXN/USB3_10_TXN
A21
PCIE4_TXP/USB3_10_TXP
K19
PCIE5_RXN
L19
PCIE5_RXP
D22
PCIE5_TXN
C22
PCIE5_TXP
G22
PCIE6_RXN
E22
PCIE6_RXP
B22
PCIE6_TXN
A23
PCIE6_TXP
L22
PCIE7_RXN
K22
PCIE7_RXP
C23
PCIE7_TXN
B23
PCIE7_TXP
K24
PCIE8_RXN
L24
PCIE8_RXP
C24
PCIE8_TXN
B24
PCIE8_TXP
SKL-H-PCH_BGA837
SPT-H_PCH
DMI
PCIe/USB 3
USB 2.0
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7
USB2_COMP
USB2_VBUSSENSE
RSVD_AB13
GPD7/RSVD
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB2_ID
2 OF 12REV = 1.3
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
AJ11
AJ13
AD43
AD42
AD39
AC44
Y43
Y41
W44
W43
AG3
USB2_VBUSSENSE
AD10
AB13
USB2_ID
AG2
BD14
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB2_COMP
3.3V_CAM_EN#
USB20_N1 <40>
USB20_P1 <40>
USB20_N2 <40>
USB20_P2 <40>
USB20_N3 <39>
USB20_P3 <39>
USB20_N5 <41>
USB20_P5 <41>
USB20_N6 <33>
USB20_P6 <33>
USB20_N7 <41>
USB20_P7 <41>
USB20_N8 <33>
USB20_P8 <33>
USB20_N9 <30>
USB20_P9 <30>
USB20_N10 <37>
USB20_P10 <37>
USB20_N11 <30>
USB20_P11 <30>
USB_OC0# <40>
USB_OC1# <40>
USB_OC2# <39>
Reser ve
RH193
RH364 1K_0402_5%1 2
RH365
@
3.3V_CAM_EN# <30>
1 2
1 2
113_0402_1%
0_0402_5%
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC0#
RPH6
1 8
2 7
3 6
4 5
10K_0804_8P4R_5%
+3.3V_ALW_PCH
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (2/9)
SKYLAKE PCH-H (2/9)
Document Number Rev
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (2/9)
LA-C841P
LA-C841P
LA-C841P
1
17 74Tuesday, September 08, 2015
17 74Tuesday, September 08, 2015
17 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
D D
4
3
2
1
1M_0402_1%
1 2
SPT-H_PCH
RH153
RH152 0_0402_5%@
1 2
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_PCIE_N6
CLKOUT_PCIE_P6
CLKOUT_PCIE_N7
CLKOUT_PCIE_P7
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
7 OF 12REV = 1.3
3
4
YH2
24MHZ_12PF_X3G024000DC1H
1
2
dGPU
WIGIG
WLAN
MMI
LAN
TBT
HDD
PCH_XDP_CLK_DN
PCH_XDP_CLK_DP
PCH_CPU_PCIBCLK_R_D
PCH_XDP_CLK_DN_R
L1
PCH_XDP_CLK_DP_R
L2
J1
PCH_CPU_PCIBCLK_D# PCH_CPU_PCIBCLK_R_D#
J2
PCH_CPU_PCIBCLK_D
CLK_PEG_N0
N7
CLK_PEG_P0
N8
CLK_PCIE_N1
L7
CLK_PCIE_P1
L5
CLK_PCIE_N2
D3
CLK_PCIE_P2
F2
CLK_PCIE_N3
E5
CLK_PCIE_P3
G4
CLK_PCIE_N4
D5
CLK_PCIE_P4
E6
CLK_PCIE_N5
D8
CLK_PCIE_P5
D7
R8
R7
U5
U7
W10
W11
CLK_PCIE_N9
N3
CLK_PCIE_P9
N2
P3
P2
R3
R4
CH13
1 2
15P_0402_50V8J
CH14
1 2
15P_0402_50V8J
RH154 0_0402_5%@
1 2
RH155 0_0402_5%@
1 2
1 2
RH168 0_0402_5%@
RH167 0_0402_5%@
1 2
CLK_PEG_N0 <50>
CLK_PEG_P0 <50>
CLK_PCIE_N1 <33>
CLK_PCIE_P1 <33>
CLK_PCIE_N2 <33>
CLK_PCIE_P2 <33>
CLK_PCIE_N3 <32>
CLK_PCIE_P3 <32>
CLK_PCIE_N4 <31>
CLK_PCIE_P4 <31>
CLK_PCIE_N5 <46>
CLK_PCIE_P5 <46>
CLK_PCIE_N9 <38>
CLK_PCIE_P9 <38>
PCH_XDP_CLK_DN <7>
PCH_XDP_CLK_DP <7>
PCH_CPU_PCIBCLK_R_D# <7>
PCH_CPU_PCIBCLK_R_D <7>
UH1G
AR17
CPU_24MHZ_R_D<7>
CPU_24MHZ_R_D#<7>
PCH_CPU_BCLK_R_D<7>
PCH_CPU_BCLK_R_D#<7>
DIS@
RH366 10K_0402_5%
dGPU
WIGIG
WLAN
C C
MMI
LAN
TBT
HDD
WWAN
B B
+3.3V_RUN
CLKREQ_PEG#0<51>
CLKREQ_PCIE#1<33>
CLKREQ_PCIE#2<33>
CLKREQ_PCIE#3<32>
CLKREQ_PCIE#4<31>
CLKREQ_PCIE#5<46>
CLKREQ_PCIE#9<38>
CLKREQ_PCIE#14<33>
RH124 10K_0402_5%
+3.3V_RUN
RH125 10K_0402_5%
+3.3V_RUN
RH126 10K_0402_5%
+3.3V_RUN
RH127 10K_0402_5%
+3.3V_RUN
RH131 10K_0402_5%
+3.3V_RUN
RH132 10K_0402_5%
+3.3V_RUN
RH133 10K_0402_5%
+3.3V_RUN
DGPU_PWR_EN<21,53>
15P_0402_50V8J
15P_0402_50V8J
1 2
1 2
CPU_24MHZ_R_D PCH_CPU_NSSC_CLK_D
CPU_24MHZ_R_D#
PCH_CPU_BCLK_R_D
PCH_CPU_BCLK_R_D#
12
12
12
12
12
12
12
12
CLKREQ_PEG#0
DMN65D8LW-7_SOT323-3
DIS@
13
D
2
CH4
CH5
QH5
G
S
PCH_RTCX1_R
12
YH1
32.768KHZ_12.5PF_9H03200042
+1.0V_CLK5
CLKREQ_PEG#0
CLKREQ_PCIE#1
CLKREQ_PCIE#2
CLKREQ_PCIE#3
CLKREQ_PCIE#4
CLKREQ_PCIE#5
CLKREQ_PCIE#9
CLKREQ_PCIE#14
1 2
RH43 0_0402_5%@
RH169 0_0402_5%@
1 2
RH170 0_0402_5%@
1 2
1 2
RH161 0_0402_5%@
RH166 0_0402_5%@
1 2
1 2
RH171 2.7K_0402_1%
WWAN
12
RH44
10M_0402_5%
PCH_RTCX2
CLK_PCIE_N14<33>
CLK_PCIE_P14<33>
PCH_RTCX1
PCH_CPU_NSSC_CLK_D#
PCH_CPU_BCLK_D
PCH_CPU_BCLK_D#
XTAL24_OUT_R1
XTAL24_IN_R
XCLK_RBIAS
PCH_RTCX1
PCH_RTCX2
CLK_PCIE_N14
CLK_PCIE_P14
GPP_A16/CLKOUT_48
G1
CLKOUT_CPUNSSC_P
F1
CLKOUT_CPUNSSC_N
G2
CLKOUT_CPUBCLK_P
H2
CLKOUT_CPUBCLK_N
A5
XTAL24_OUT
A6
XTAL24_IN
E1
XCLK_BIASREF
BC9
RTCX1
BD10
RTCX2
BC24
GPP_B5/SRCCLKREQ0#
AW24
GPP_B6/SRCCLKREQ1#
AT24
GPP_B7/SRCCLKREQ2#
BD25
GPP_B8/SRCCLKREQ3#
BB24
GPP_B9/SRCCLKREQ4#
BE25
GPP_B10/SRCCLKREQ5#
AT33
GPP_H0/SRCCLKREQ6#
AR31
GPP_H1/SRCCLKREQ7#
BD32
GPP_H2/SRCCLKREQ8#
BC32
GPP_H3/SRCCLKREQ9#
BB31
GPP_H4/SRCCLKREQ10#
BC33
GPP_H5/SRCCLKREQ11#
BA33
GPP_H6/SRCCLKREQ12#
AW33
GPP_H7/SRCCLKREQ13#
BB33
GPP_H8/SRCCLKREQ14#
BD33
GPP_H9/SRCCLKREQ15#
R13
CLKOUT_PCIE_N15
R11
CLKOUT_PCIE_P15
P1
CLKOUT_PCIE_N14
R2
CLKOUT_PCIE_P14
W7
CLKOUT_PCIE_N13
Y5
CLKOUT_PCIE_P13
U2
CLKOUT_PCIE_N12
U3
CLKOUT_PCIE_P12
SKL-H-PCH_BGA837
XTAL24_IN_R
XTAL24_OUT_R1 XTAL24_OUT_R
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (3/9)
SKYLAKE PCH-H (3/9)
Document Number Rev
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (3/9)
LA-C841P
LA-C841P
LA-C841P
18 74Tuesday, September 08, 2015
18 74Tuesday, September 08, 2015
18 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
Vinafix.com
5
+3.3V_ALW_PCH
SIO_EXT_SMI#
D D
+3.3V_RUN
C C
B B
A A
+3.3V_SPI
RH30 1K_0402_5%@
RH335 1K_0402_5%@
RH334 1K_0402_5%@
5
1 2
1 2
1 2
12
RH31010K_0402_5%
TOUCH_SCREEN_PD#
12
RH34810K_0402_5%
PCH_SPI_D2_XDP<7>
PCH_SPI_D2_R1
PCH_SPI_D3_R1
PCH_SPI_D3_R1
1 2
RH180 0_0402_5%@
MEDIACARD_IRQ#<32>
PCH_SPI_CS#0_R1
PCH_SPI_D2_R1 PCH_SPI_CLK_0_R
PCH_SPI_CS#1_R1
PCH_SPI_D2_R1
PCH_SPI_CLK_1_R
4
PME#
T178PAD~D @
T59PAD~D @
T60PAD~D @
T61PAD~D @
T58PAD~D @
T63PAD~D @
T62PAD~D @
1 2
1 2
1 2
1 2
11/17 RF request
4
PCH_SPI_D0
PCH_SPI_D1
PCH_SPI_CS#0
PCH_SPI_CLK
PCH_SPI_CS#1
PCH_SPI_D2PCH_SPI_D2_XDP
PCH_SPI_D3
PCH_SPI_CS#2
MEDIACARD_IRQ#
FFS_INT2
TPM_PIRQ#
12
@EMC@
33_0402_5%
1
@EMC@
27P_0402_50V8J
2
PCH_SPI_D0<7>
PCH_SPI_CS#2<37>
FFS_INT2<45>
TPM_PIRQ#<37>
@
RH37 0_0402_5%
RH351 33_0402_5%
RH352 0_0402_5%
@
RH353 33_0402_5%
@
BD17
AG15
AG14
AF17
AE17
AR19
AN17
BB29
BE30
BD31
BC31
AW31
BC29
BD30
AT31
AN36
AL39
AN41
AN38
AH43
AG44
PCH_SPI_CS#0_R2
PCH_SPI_D1_0_R
PCH_SPI_D2_0_R
PCH_SPI_CS#1_R2
PCH_SPI_D1_1_R
PCH_SPI_D2_1_R
RH354
CH271
PCH_PLTRST#
UH1A
GPP_A11/PME#
RSVD
RSVD
RSVD
RSVD
TP2
TP1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_CLK
GPP_D0/SPI1_CS#
GPP_D3/SPI1_MOSI
GPP_D2/SPI1_MISO
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2
SKL-H-PCH_BGA837
UC5
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q128FVSIQ_SO8
UC6
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
3
+3.3V_RUN+3.3V_ALW_PCH
12
1
2
SPT-H_PCH
VCC
/HOLD(IO3)
CLK
DI(IO0)
@
VCC
/HOLD(IO3)
CLK
DI(IO0)
12
RH356
0_0402_5%
5
UH2
P
B
4
Y
A
G
TC7SH08FU_SSOP5
3
GPP_B13/PLTRST#
GPP_G16/GSXCLK
GPP_G12/GSXDOUT
GPP_G13/GSXSLOAD
GPP_G14/GSXDIN
GPP_G15/GSXSRESET#
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
INTRUDER#
+3.3V_SPI
8
PCH_SPI_D3_0_R
7
6
PCH_SPI_D0_0_R
5
+3.3V_SPI
8
PCH_SPI_D3_1_R
7
PCH_SPI_CLK_1_R
6
PCH_SPI_D0_1_R
5
RH357
@
0_0402_5%
PCH_PLTRST#_EC
PCH_SPI_D1_R1<37>
PCH_SPI_D0_R1<37>
PCH_SPI_CLK_R1<37>
CH9
1 2
0.1U_0201_10V6K
@
CH270
1 2
0.1U_0201_10V6K
12
RH196
@
100K_0402_5%
BB27
TBT_FORCE_PWR
P43
RTD3_CIO_PWR_EN
R39
R36
R42
R41
SIO_EXT_SMI#
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
PCH_INTRUDER_HDR#
BE11
RH210 0_0402_5%@
RH187 0_0402_5%@
RH197 0_0402_5%@
PCH_PLTRST#
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
PCH_SPI_D1_R1
PCH_SPI_D0_R1
PCH_SPI_CLK_R1
PCH_SPI_D3_R1
1 2
1 2
1 2
TBT_FORCE_PWR <46>
RTD3_CIO_PWR_EN <35,46>
SIO_EXT_SMI# <36>
TOUCH_SCREEN_PD# <30>
TOUCHPAD_INTR# <42>
TOUCH_SCREEN_DET# <30>
+RTC_CELL
12
RPC1
1 8
2 7
3 6
4 5
33_0804_8P4R_5%
RPC2
@
4 5
3 6
2 7
1 8
33_0804_8P4R_5%
+3.3V_SPI
RH198
330K_0402_5%
PCH_SPI_D1_0_R
PCH_SPI_D0_0_R
PCH_SPI_CLK_0_R
PCH_SPI_D3_0_R
PCH_SPI_D1_1_R
PCH_SPI_D0_1_R
PCH_SPI_CLK_1_R
PCH_SPI_D3_1_R
2
PCH_PLTRST#_EC <36>
PCH_PLTRST#_AND <32,33,37,38>
PLTRST_TPM# <37>
PLTRST_TBT# <46>
1 2
RH194 0_0402_5%@
RH212 0_0402_5%@
1 2
RH195 0_0402_5%@
1 2
+3.3V_ALW_PCH
+3.3V_M
12
@
12
12
12
12
12
12
RH362 0_0402_5%
RH363 0_0402_5%@
RH185 0_0402_5%@
12
PLTRST_LAN# <31>
PLTRST_5048# <35>
PLTRST_GPU# <50>
PCH_SPI_CS#1_R1
RH1770_0402_5%
RH1780_0402_5%
RH1790_0402_5%
RH1810_0402_5%
PCH_SPI_CS#0_R1
RH1820_0402_5%
PCH_SPI_D2_R1
RH1830_0402_5%
PCH_SPI_D3_R1
RH1840_0402_5%
12
12
+3.3V_SPI_R
PCH_SPI_CLK_0_R
PCH_SPI_CS#1
PCH_SPI_D0_R1
PCH_SPI_D0
PCH_SPI_D1_R1
PCH_SPI_D1
PCH_SPI_CLK_R1
PCH_SPI_CLK
PCH_SPI_CS#0
PCH_SPI_D2
PCH_SPI_D3
12
@
RH1
33_0402_5%
1
@
CH269
27P_0402_50V8J
2
1
E-T_6705K-Y20N-00L
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSPI1
CONN@
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKYLAKE PCH-H (4/9)
SKYLAKE PCH-H (4/9)
Document Number Re v
Document Number Re v
Document Number Re v
SKYLAKE PCH-H (4/9)
LA-C841P
LA-C841P
LA-C841P
19 74Tuesday, September 08, 2015
19 74Tuesday, September 08, 2015
19 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Vinafix.com
5
+3.3V_ALW_PCH
1 2
RH56 1K_0402_5%
1 2
RH65 1K_0402_5%
1 2
RH67 499_0402_1%
1 2
RH77 499_0402_1%
D D
C C
B B
A A
1 2
RH80 1K_0402_5%
1 2
RH81 1K_0402_5%
+3.3V_PGPPBCH
1 2
RH61 4.7K_0402_5%
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
1 2
RH78 4.7K_0402_5%@
EC interface
HIGH
LOW(DEFAULT)
+3.3V_ALW_PCH
1 2
RH86 4.7K_0402_5%@
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
PCH_DPWROK PCH_RSMRST#_R
1
2
1 2
RH215 0_0402_5%@
100K_0402_5%
0.01U_0402_50V7K
12
RH308
CH266
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
PCH_SMB_ALERT#
ENABLE
DISABLE
GPP_C5
ESPI
LPC
SPKR
ENABLE
DISABLE
+3.3V_RUN +3.3V_ALW_PCH
11/29 ,MOW for DCI 2/24 ,INTEL recommended
150K_0402_5%
RC332
1 2
GPP_B23 GPP_B23_Q
SIO_SLP_A#<20,36,37>
SIO_SLP_SUS#<11,20,36,44,60,62>
WEAK INTERNAL PD
5
RC327
@
0_0402_5%
@
D
S
13
@
L2N7002WT1G_SC-70-3
G
2
12
RH367 0_0402_5%@
12
RH368@ 0 _0402_5%
+3.3V_ALW_PCH
12
12
QC3
@
R3728
1K_0402_5%
Right Side (Up) JUSB3
Right Sid e (Do wn) JUSB1
EMC@ 1 2
CH268 22P_0402_50V8J
HDA_BIT_CLK_R< 34>
HDA_SDOUT_R<34>
AUD_AZACPU_SDO<9>
AUD_AZACPU_SDI_R<9>
AUD_AZACPU_SCLK<9>
RH329
150K_0402_5%
1 2
ME_FWP_EC ME_FWP
PT,ST pop R3728 and SW2; MP pop RC301
ME_FWP_EC<35>
PCH_DPWROK<36>
SML0_SMBCLK<31>
SML0_SMBDATA<31>
SML1_SMBCLK<36>
SML1_SMBDATA<36>
AUD_AZACPU_SDI_R
RC301 0_0402_5%@
ME_FWP
4
M.2 3042 (LTE)
EDOCK
Rear Side JUSB2
11/17 RF request
ME_FWP
RH200 20K_0402_5%
RH201 20K_0402_5%
@
SW2
1
A
2
B
3
C
4
G1
5
G2
SS3-CMFTQR9_3P
4
RH46 33_0402_5%
RH50 33_0402_5%
RH328 1K_0402_5%
RH45 33_0402_5%
RH48 33_0402_5%
RH39 30_0402_5%
RH38 30_0402_5%
HDA_RST#_R<34>
HDA_SDIN0<34>
HDA_SYNC_R<34>
+RTC_CELL
PCH_DPWROK
MEM_SMBCLK
MEM_SMBDATA
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DGPU_PWROK<35,53,69>
1 2
1 2
PCH_PWROK<63>
PCH_RSMRST#_R<7>
USB3_PTX_DRX_N1<4 0>
USB3_PTX_DRX_P1<40>
USB3_PRX_DTX_N1<40>
USB3_PRX_DTX_P1<40>
USB3_PTX_DRX_N2<3 3>
USB3_PTX_DRX_P2<33>
USB3_PRX_DTX_N2<33>
USB3_PRX_DTX_P2<33>
USB3_PTX_DRX_N6<4 1>
USB3_PTX_DRX_P6<41>
USB3_PRX_DTX_N6<41>
USB3_PRX_DTX_P6<41>
USB3_PTX_DRX_P3<40>
USB3_PTX_DRX_N3<4 0>
USB3_PRX_DTX_P3<40>
USB3_PRX_DTX_N3<40>
USB3_PTX_DRX_P4<39>
USB3_PTX_DRX_N4<3 9>
USB3_PRX_DTX_P4<39>
USB3_PRX_DTX_N4<39>
HDA_BIT_CLK
HDA_RST#
HDA_SDIN0
HDA_SDOUT
HDA_SYNC
AUD_AZACPU_SDO_RAUD_AZACPU_SDO
AUD_AZACPU_SCLK_RAUD_AZACPU_SCLK
DGPU_PWROK
PCH_RTCRST#
SRTCRST#
PCH_PWROK
PCH_RSMRST#_R
PCH_SMB_ALERT#
GPP_C5
GPP_B23
CH41 1U_0402_6.3V6K
CH40 1U_0402_6.3V6K
USB3_PTX_DRX_N1
USB3_PTX_DRX_P1
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1
USB3_PTX_DRX_N2
USB3_PTX_DRX_P2
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_DRX_N6
USB3_PTX_DRX_P6
USB3_PRX_DTX_N6
USB3_PRX_DTX_P6
USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3
USB3_PTX_DRX_P4
USB3_PTX_DRX_N4
USB3_PRX_DTX_P4
USB3_PRX_DTX_N4
1 2
1 2
PCH_RTCRST#<3 7>
1
1
CMOS1 SHORT PADS~D@
MEM_SMBCLK
MEM_SMBDATA
C11
B11
B12
A12
B15
C15
K15
K13
B14
C14
G13
H13
D13
C13
B10
B13
A14
G11
E11
UH1D
BA9
HDA_BCLK
BD8
HDA_RST#
BE7
HDA_SDI0
BC8
HDA_SDI1
BB7
HDA_SDO
BD9
HDA_SYNC
BD1
RSVD_BD1
BE2
RSVD_BE2
AM1
DISPA_SDO
AN2
DISPA_SDI
AM2
DISPA_BCLK
AL42
GPP_D8/I2S0_SCLK
AN42
GPP_D7/I2S0_RXD
AM43
GPP_D6/I2S0_TXD
AJ33
GPP_D5/I2S0_SFRM
AH44
GPP_D20/DMIC_DATA0
AJ35
GPP_D19/DMIC_CLK0
AJ38
GPP_D18/DMIC_DATA1
AJ42
GPP_D17/DMIC_CLK1
BC10
RTCRST#
BB10
SRTCRST#
AW11
PCH_PWROK
BA11
RSMRST#
AV11
DSW_PWROK
BB41
GPP_C2/SMBALERT#
AW44
GPP_C0/SMBCLK
BB43
GPP_C1/SMBDATA
BA40
GPP_C5/SML0ALERT#
AY44
GPP_C3/SML0CLK
BB39
GPP_C4/SML0DATA
AT27
GPP_B23/SML1ALERT#/PCHHOT#
AW42
GPP_C6/SML1CLK
AW45
GPP_C7/SML1DATA
SKL-H-PCH_BGA837
SRTCRST#
PCH_RTCRST#
2
2
3
UH1F
USB3_1_TXN
USB3_1_TXP
B7
USB3_1_RXN
A7
USB3_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
C8
USB3_2_RXN/SSIC_1_RXN
B8
USB3_2_RXP/SSIC_1_RXP
USB3_6_TXN
USB3_6_TXP
USB3_6_RXN
USB3_6_RXP
USB3_5_TXN
USB3_5_TXP
USB3_5_RXN
USB3_5_RXP
USB3_3_TXP/SSIC_2_TXP
USB3_3_TXN/SSIC_2_TXN
A9
USB3_3_RXP/SSIC_2_RXP
USB3_3_RXN/SSIC_2_RXN
USB3_4_TXP
USB3_4_TXN
USB3_4_RXP
USB3_4_RXN
SKL-H-PCH_BGA837
AUDIO
+3.3V_RUN
DMN65D8LDW-7_SOT363-6
3 4
DMN65D8LDW-7_SOT363-6
QH4B
3
2
@
T228
PAD~D
@
T227
PAD~D
@
T226
SPT-H_PC H
LPC/eSPI
USB
SATA
SPT-H_PCH
GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
SMBUS
2
6 1
QH4A
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_G19/SMI#
GPP_G18/NMI#
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#
GPP_B2/VRALERT#
GPP_G17/ADR_COMPLETE
GPP_B12/SLP_S0#
GPD10/SLP_S5#
GPD0/BATLOW#
GPP_A13/SUSWARN#/SUSPWRDNACK
JTAG
GPP_A15/SUSACK#
GPD2/LAN_WAKE#
GPD1/ACPRESENT
GPD3/PWRBTN#
1 2
@
RZ106 0_0402_5%
1 2
@
RZ107 0_0402_5%
DDR_XDP_WAN_SMBCLK <7,14,15,45>
DDR_XDP_WAN_SMBDAT <7,14,15,45>
6 OF 12REV = 1.3
DRAM_RESET#
GPP_B1
GPP_B0
GPP_B11
SYS_PWROK
WAKE#
GPD6/SLP_A#
SLP_LAN#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD8/SUSCLK
SLP_SUS#
SYS_RESET#
GPP_B14/SPKR
PROCPWRGD
ITP_PMODE
JTAGX
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
AT22
AV22
AT19
BD16
BE16
BA17
AW17
AT17
BC18
BC17
AV19
M45
N43
AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41
BB17
AW22
AR15
AV13
BC14
BD23
AL27
AR27
N44
AN24
AY1
BC13
BC15
AV15
BC26
AW15
BD15
BA13
AN15
BD13
BB19
BD19
BD11
BB15
BB13
AT13
AW1
BD26
AM3
AT2
AR3
AR2
AP1
AP2
AN3
ME3_SMBCLK <44>
ME3_SMBDAT <44>
PAD~D
PAD~D
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
IRQ_SERIRQ
HDD_FALL_INT
SIO_RCIN#
GPP_A14
PCI_CLK_LPC0
PCI_CLK_LPC1
CLKRUN#
PM_LANPHY_ENABLE
SIO_SLP_WLAN#
DDR4_DRAMRST#_PCH
VRALERT#
RESET_OUT#
PCH_PCIE_WAKE#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
SUSCLK
PCH_BATLOW#
SUSACK#
ME_SUS_PWR_ACK
LAN_WAKE#
AC_PRESENT_R
SIO_PWRBTN#
SYS_RESET#
SPKR
H_PWRGD
ITP_PMODE_CPU
PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TCK
2
@
T225
LPC_LAD0 <35,36>
LPC_LAD1 <35,36>
LPC_LAD2 <35,36>
LPC_LAD3 <35,36>
PAD~D
LPC_LFRAME# <35,36>
IRQ_SERIRQ <35,36>
HDD_FALL_INT <45>
SIO_RCIN# <36>
RH96 22_0402_5%EMC@
RH97 22_0402_5%EMC@
RH99 22_0402_5%EMC@
RH98 22_0402_5%EMC@
HDD_DEVSLP <45>
M2_DEVSLP <38>
CLKRUN# <35,36>
PM_LANPHY_ENABLE <31>
SIO_SLP_WLAN# <35,44>
DDR4_DRAMRST#_PCH <14>
RESET_OUT# <7,36>
PCH_PCIE_WAKE# <35,36>
SIO_SLP_A# <20,36,37>
SIO_SLP_LAN# <36,44>
SIO_SLP_S0# <11,37>
SIO_SLP_S3# <11,36,37,46,61,62>
SIO_SLP_S4# <11,36,37,59,71>
SIO_SLP_S5# <36,37>
SUSCLK <33,38>
SUSACK# <36>
ME_SUS_PWR_ACK <36>
LAN_WAKE# <31,36>
SIO_SLP_SUS# <11,20,36,44,60,62>
SIO_PWRBTN# <7,36>
SYS_RESET# <17,37>
SPKR <34>
H_PWRGD <7>
ITP_PMODE_CPU <7>
PCH_JTAGX <7>
PCH_JTAG_TMS <7>
PCH_JTAG_TDO <7>
PCH_JTAG_TDI <7>
PCH_JTAG_TCK <7>
DELL CONFIDENTIAL/PROPRIETARY
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
@
T229
1 2
1 2
1 2
1 2
@
@
@
@
@
@
AC_PRESENT<36>
T192
T182
T183
T186
T187
T188
1
CLK_PCI_5048 <35>
CLK_PCI_MEC <36>
CLK_PCI_LPDEBUG <36>
CLK_PCI_DOCK <41>
CLK_PCI_5048
CLK_PCI_MEC
CLK_PCI_LPDEBUG
CLK_PCI_DOCK
GPP_A14
VRALERT#
SIO_SLP_LAN#
ME_SUS_PWR_ACK
PM_LANPHY_ENABLE
PCH_PCIE_WAKE#
LAN_WAKE#
PCH_BATLOW#
SIO_RCIN#
CLKRUN#
RESET_OUT#
10/23
ME_SUS_PWR_ACK
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
IRQ_SERIRQ
HDD_FALL_INT
PCH_JTAG_TCK
SUSCLK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Document Number Rev
Document Number Rev
Document Number Rev
1 2
CH42 1 2P_0402_50V8J@EMC@
1 2
CH49 1 2P_0402_50V8J@EMC@
1 2
CH50 1 2P_0402_50V8J@EMC@
1 2
CH51 1 2P_0402_50V8J@EMC@
RH338 100K_0402_5%
RH199 100K_0402_5%
SKYLAKE PCH-H (5/9)
SKYLAKE PCH-H (5/9)
SKYLAKE PCH-H (5/9)
LA-C841P
LA-C841P
LA-C841P
1
+3.3V_ALW_PCH
1 2
RH95 10K_0402_5%@
1 2
RH203 10K_0402_5%@
1 2
RH204 10K_0402_5%@
1 2
RH327 10K_0402_5%
12
RH31251_0402_5%
RH31451_0402_5%
RH31551_0402_5%
SUSACK#
AC_PRESENT_RAC_PRESENT
20 74Tuesday, September 08, 2015
20 74Tuesday, September 08, 2015
20 74Tuesday, September 08, 2015
RH31351_0402_5% @
RH831K_0402_5% @12
+1.0V_VCCSTG
+3.3V_RUN
12
RH3742.2K_0402_5%
12
RH3332.2K_0402_5%
+3.3V_DSW
+3.3V_RUN
1 2
1 2
RH92 1K_0402_5%
1 2
RH93 10K_0402_5%
1 2
RH94 8.2K_0402_5%
1 2
RH213 10K_0402_5%
1 2
RH202 8.2K_0402_5%
1 2
1 2
RH340 10K_0402_5%
1 2
RH355 10K_0402_5%
12
12
12
RH840_0402_5% @12
RH850_0402_5% @12
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
+3.3V_ALW_PCH
+3.3V_RUN
1 2
RH207 100K_0402_5%
1 2
RH347 100K_0402_5%
1 2
RH360 49.9K_0402_1%@
1 2
D D
C C
B B
RH361 49.9K_0402_1%@
1 2
RH79 10K_0402_5%
1 2
RH331 4.7K_0402_5%@
1 2
RH339 10K_0402_5%
1 2
RH345 10K_0402_5%
+3.3V_ALW_PCH
1 2
RH309 10K_0402_5%
1 2
RC330 49.9K_0402_1%
1 2
RC331 49.9K_0402_1%
GPP_C8
TS_EN
LPSS_UART2_TXD
LPSS_UART2_RXD
3.3V_TP_EN
NRB_BIT
SIO_EXT_SCI#
AUD_PWR_EN
SIO_EXT_WAKE#
LPSS_UART2_TXD
LPSS_UART2_RXD
HDD_EN
HDD_EN< 45>
TS_EN
TS_EN<30>
PCH_DP1_HPD<26>
PCH_DP2_HPD<27>
PCH_DP3_HPD<28>
Rese rve
EDP_HPD<30>
SIO_EXT_SCI#
3.3V_TP_EN
NRB_BIT
GPP_C8
HOST_SD_WP#
LCD_CBL_DET#
SIO_EXT_WAKE#
LPSS_UART2_TXD
LPSS_UART2_RXD
I2C_1_SCL
I2C_1_SDA
PCH_DP1_HPD
PCH_DP2_HPD
PCH_DP3_HPD
EDP_HPD
SIO_EXT_SCI#<36>
UART0_TXD<36>
HOST_SD_WP#<32>
LCD_CBL_DET#<30>
8/20
SIO_EXT_WAKE#<36>
I2C_1_SCL<42>
I2C_1_SDA<42> KB_DET# <42>
UH1K
AT29
GPP_B22/GSPI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GPP_B20/GSPI1_CLK
BC27
GPP_B19/GSPI1_CS#
BD28
GPP_B18/GSPI0_MOSI
BD27
GPP_B17/GSPI0_MISO
AW27
GPP_B16/GSPI0_CLK
AR24
GPP_B15/GSPI0_CS#
AV44
GPP_C9/UART0_TXD
BA41
GPP_C8/UART0_RXD
AU44
GPP_C11/UART0_CTS#
AV43
GPP_C10/UART0_RTS#
AU41
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
AT44
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AT43
GPP_C13/UART1_TXD/ISH_UART1_TXD
AU43
GPP_C12/UART1_RXD/ISH_UART1_RXD
AN43
GPP_C23/UART2_CTS#
AN44
GPP_C22/UART2_RTS#
AR39
GPP_C21/UART2_TXD
AR45
GPP_C20/UART2_RXD
AR41
GPP_C19/I2C1_SCL
AR44
GPP_C18/I2C1_SDA
AR38
GPP_C17/I2C0_SCL
AT42
GPP_C16/I2C0_SDA
AM44
GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
AJ44
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL
SKL-H-PCH_BGA837
UH1E
AW4
GPP_I0/DDPB_HPD0
AY2
GPP_I1/DDPC_HPD1
AV4
GPP_I2/DDPD_HPD2
BA4
GPP_I3/DDPE_HPD3
BD7
GPP_I4/EDP_HPD
SKL-H-PCH_BGA837
SPT-H_PCH
GPP_D16/ISH_UART0_CTS#
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
SPT-H_PCH
GPP_D15/ISH_UART0_RTS#
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/ISH_GP7
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_F14
GPP_F23
GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23
GPP_D9
GPP_D10
GPP_D11
GPP_D12
BB3
BD6
BA5
BC4
BE5
BE6
Y44
V44
W39
L43
L44
U35
R35
BD36
DIMM_TYPE
AL44
AL36
AL35
DGPU_PWR_EN
AJ39
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
IR_CAM_DET#
BC22
NON_DOCK
BD18
AUD_PWR_EN
BE21
KB_DET#
BD22
BD21
BB22
BC19
PCH_DP2_CTRL_CLK
PCH_DP2_CTRL_DATA
PCH_DP1_CTRL_CLK
PCH_DP1_CTRL_DATA
PCH_DP3_CTRL_DATA
GPP_F23
ISH_UART0_CTS# <33>
ISH_UART0_RTS# <33>
ISH_UART0_TXD <33>
ISH_UART0_RXD <33>
PCH_DP2_CTRL_CLK <27>
PCH_DP1_CTRL_CLK <26>
DGPU_HOLD_RST# <50>
DGPU_PWR_EN <18,53>
IR_CAM_DET# <30>
AUD_PWR_EN <34>
PCH_DP2_CTRL_DATA <27>
PCH_DP1_CTRL_DATA <26>
KB_DET#
8/21
LCD_CBL_DET#
PCH_DP2_CTRL_CLK
PCH_DP2_CTRL_DATA
PCH_DP1_CTRL_CLK
PCH_DP1_CTRL_DATA
PCH_DP3_CTRL_DATA
DGPU_PWR_EN
DGPU_HOLD_RST#
IR_CAM_DET#
DGPU_PWR_EN
GPP_F23
NON_DOCK
DIMM_TYPE
LPSS_UART2_TXD
LPSS_UART2_RXD
1 2
RC74 1 0K_0402_5%
1 2
RC79 10K_0402_5%
1 2
RH220 2. 2K_0402_5%
1 2
1 2
RH221 2. 2K_0402_5%
1 2
RH222 2. 2K_0402_5%
RH223 2. 2K_0402_5%
1 2
RH369 2. 2K_0402_5%
1 2
RH346 100K_0402_5%
1 2
RH350 100K_0402_5%
1 2
RH373 100K_0402_5%
1 2
RH349 100K_0402_5%
1 2
RH214 100K_0402_5%
1 2
RH359 100_0402_1%@
1 2
RH372 10K_0402_5%@
+5V_ALW
CONN@
JUART1
1
1
2
2
3
3
4
4
5
GND
6
GND
ACES_50207-00471-P01
+3.3V_RUN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (6/9)
SKYLAKE PCH-H (6/9)
Document Number Rev
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (6/9)
LA-C841P
LA-C841P
LA-C841P
1
21 74Tuesday, September 08, 2015
21 74Tuesday, September 08, 2015
21 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
4
3
2
1
+1.0V_PRIM +1.0V_ALW_PCH
1 2
RH254 0_1206_5%
+1.0V_ALW_PCH +1.0V_DSW
D D
RH255 0_0402_5%@
RH256 0_0402_5%@
RH257 0_0402_5%@
RH258 0_0402_5%@
RH259 0_0402_5%@
RH260 0_0402_5%@
RH286 0_0402_5%@
C C
RH287 0_0402_5%@
RH288 0_0402_5%@
2
RH289 0_0402_5%@
RH290 0_0402_5%@
+3.3V_ALW_PCH
B B
RH298 0_0402_5%@
RH299 0_0402_5%@
RH300 0_0402_5%@
RH306 0_0402_5%@
+3.3V_ALW
RH301 0_0603_5%@
+3.3V_RUN +3.3V_RUN_ATS
RH302 0_0402_5%@
+3.3V_ALW_PCH
A A
RH303 0_0402_5%@
RH304 0_0402_5%@
RH305 0_0402_5%@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PJP8
112
JUMP_43X79
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
0.0454A
+1.0V_CLK1
0.0348A
+1.0V_CLK3
0.0237A
+1.0V_CLK4
0.0327A
+1.0V_CLK2
0.205A
+1.0V_F24
0.0046A
+1.0V_DUSB
0.533A
+2.8V_FHV
0.0908A
+1.0V_DTS
0.0061A
+1.0V_MPHY
2.10A
+1.0V_AMPHYPLL
0.0248A
+1.0V_APLLEBB
0.095A
+3.3V_PRTCPRIM
0.0002A
+3.3V_PHVC
0.2875A
+3.3V_1.8V_FUSE
0.0811A
+3.3V_DSW
0.0811A
0.403A
0.0066A
+3.3V_PGPPEF
0.14107A
+3.3V_PGPPBCH
0.27262A
+3.3V_PGPPG
0.1318A
5
+3.3V_ALW +3.3V_PUSBDSW
1 2
RH276 0_0603_5%@
+3.3V_PRTC+RTC_CELL
0.0002A
1 2
RH297 0_0402_5%@
+3.3V_ALW_PCH +3.3V_ALW_PCHRES
1 2
RH279 0_0603_5%@
+3.3V_1.8V_GPPA+3.3V_ALW_PCHRES
0.0879A
1 2
RH291 0_0402_5%@
+1.8V_ALW_PCHRES
1 2
RH294 0_0402_5%@
+3.3V_ALW_PCHRES +3.3V_1.8V_AZIO
0.075A
1 2
RH292 0_0402_5%@
+1.8V_ALW_PCHRES
1 2
RH295 0_0402_5%@
+3.3V_1.8V_GPPD+3.3V_ALW_PCHRES
0.0395A
1 2
RH293 0_0402_5%@
+1.8V_ALW_PCHRES
+1.8V_ALW_PCHRES
+3.3V_M
RH296 0_0402_5%@
RH246 0_0603_5%@
RH358 0_0603_5%@
RH250 0_0603_5%@
RH247 0_0603_5%@
1 2
+3.3V_1.8V_SPI+3.3V_ALW_PCHRES
1 2
1 2
1 2
+1.8V_PRIM
1 2
+1.0V_AAZPLL
1 2
BLM15PX600SN1D_2P
4
+1.0V_CLK5
+1.0V_CLK2
+1.0V_CLK4
+1.0V_CLK3
NO CAP
NO CAP
NO CAP
+1.0V_AUSB
+1.0V_AAZPLL_R
LC2
+3.3V_1.8V_AZIO
1
CC311
2
0.1U_0402_25V6
1 2
BLM15PX600SN1D_2P
LC1
+1.0V_PRIM
NO CAP
+1.0V_DSW
+1.0V_CLK1
NO CAP
+1.0V_MPHY
+1.0V_AMPHYPLL
+1.0V_APLLEBB
+1.0V_DUSB
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
NO CAP
+3.3V_1.8V_AZIO_R
+3.3V_PUSBDSW
1
CC310
2
0.1U_0402_25V6
BD2
VSS
BD45
VSS
BD44
VSS
BE44
VSS
D45
VSS
A42
VSS
B45
VSS
B44
VSS
A4
VSS
A3
VSS
B2
VSS
A2
VSS
B1
VSS
BB1
VSS
BC1
VSS
A44
VSS
C1
RSVD
D1
RSVD
SKL-H-PCH_BGA837
PCH_2_CPU_TRIGGER_R
UH1J
UH1H
AA23
VCCPRIM_1P0
AA26
VCCPRIM_1P0
AA28
VCCPRIM_1P0
AC23
VCCPRIM_1P0
AC26
VCCPRIM_1P0
AC28
VCCPRIM_1P0
AE23
VCCPRIM_1P0
AE26
VCCPRIM_1P0
Y23
VCCPRIM_1P0
Y25
VCCPRIM_1P0
BA29
DCPDSW_1P0
N17
VCCCLK1
R19
VCCCLK3
U20
VCCCLK4
V17
VCCCLK2
R17
VCCCLK2
K2
VCCCLK5
K3
VCCCLK5
U21
VCCMPHY_1P0
U23
VCCMPHY_1P0
U25
VCCMPHY_1P0
U26
VCCMPHY_1P0
V26
VCCMPHY_1P0
A43
VCCMPHYPLL_1P0
B43
VCCMPHYPLL_1P0
C44
VCCPCIE3PLL_1P0
C45
VCCPCIE3PLL_1P0
V28
VCCAPLLEBB_1P0
AC17
VCCPRIM_1P0
AJ5
VCCUSB2PLL_1P0
AL5
VCCUSB2PLL_1P0
AN19
VCCHDAPLL_1P0
BA15
VCCHDA
W15
VCCDSW_3P3
SKL-H-PCH_BGA837
SPT-H_PCH
CPU_TRST#
PCH_TRIGOUT
PCH_TRIGIN
REV = 1.3 10 OF 12
1 2
RH42 30_0402_5%
SPT-H_PCH
CORE
MPHY
USB
REV = 1.3 8 OF 12
AR22
RSVD
W13
RSVD
U13
RSVD
P31
RSVD
N31
RSVD
P27
RSVD
R27
RSVD
N29
RSVD
P29
RSVD
AN29
RSVD
R24
RSVD
P24
RSVD
AT3
PREQ#
PRDY#
PCH_2_CPU_TRIGGER
PCH_XDP_PREQ#
AT4
PCH_XDP_PRDY#
AY5
CPU_XDP_TRST#
AL2
PCH_2_CPU_TRIGGER_R
AK1
CPU_2_PCH_TRIGGER
+2.8V_FHV
+1.0V_DTS
+DCPRTC
+3.3V_DSW
+3.3V_1.8V_GPPA
NO CAP
+3.3V_RUN_ATS
NO CAP
+3.3V_1.8V_GPPD
NO CAP
+3.3V_1.8V_FUSE
+3.3V_PGPPBCH
+3.3V_PRTCPRIM
+1.0V_PRIM
+3.3V_1.8V_SPI
+3.3V_PGPPEF
+3.3V_PRTC
+3.3V_PGPPG
0.1U_0201_10V6K
CH68
1
2
+3.3V_PHVC
VCCGPIO
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
PAD~D
VCCRTCPRIM_3P3
@
@
@
@
@
@
@
@
@
@
@
@
VCCPRIM_1P0
VCCDSW_3P3
VCCPGPPBCH
VCCPGPPBCH
VCCPGPPEF
VCCPGPPEF
VCCPRIM_3P3
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
T66
T67
T68
T69
T70
T71
T72
T74
T73
T76
T75
T77
PCH_2_CPU_TRIGGER <10>
AL22
BA24
BA31
VCCPGPPA
BC42
BD40
AJ41
AL41
AD41
VCCPGPPG
AN5
AD15
AD13
VCCATS
BA20
BA22
VCCRTC
BA26
DCPRTC
AJ20
AJ21
AJ23
AJ25
BE41
VCCSPI
BE43
VCCSPI
BE42
VCCSPI
BC44
VCCPGPPD
BA45
VCCPGPPD
BC45
VCCPGPPD
BB45
VCCPGPPD
BD3
BE3
BE4
PCH_XDP_PREQ# <7>
PCH_XDP_PRDY# <7>
CPU_XDP_TRST# <7>
CPU_2_PCH_TRIGGER <10>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
2
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (7/9)
SKYLAKE PCH-H (7/9)
Document Number Re v
Document Number Re v
Document Number Re v
SKYLAKE PCH-H (7/9)
LA-C841P
LA-C841P
LA-C841P
22 74Tuesday, September 08, 2015
22 74Tuesday, September 08, 2015
22 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
Vinafix.com
5
+1.0V_AMPHYPLL
4
+3.3V_PUSBDSW
+1.0V_MPHY
3
+3.3V_PRTCPRIM
2
1
1U_0402_6.3V6K
1
CH267
2
D D
+1.0V_ALW_PCH +VCCAUSB_VCCAAZPLL_1P0 +1.0V_AUSB
1 2
RH238 0_0603_1%@
+1.0V_F24 + 1.0V_CLK5
C C
RH241 0_0603_1%@
1 2
+3.3V_PRTC
1
2
22U_0805_6.3VAM
@
1
1
CH44
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
@
1
1
CH29
2
2
1U_0402_6.3V6K
@
CH33
0.1U_0402_25V6
1
2
1 2
RH239 0_0603_1%@
22U_0805_6.3VAM
@
CH45
1 2
RH240 0_0603_1%@
1U_0402_6.3V6K
@
@
1
CH46
CH32
2
@
CH65
+1.0V_AAZPLL
1
2
+3.3V_PGPPEF
1
2
+3.3V_PGPPBCH
1
2
+3.3V_PGPPG
1
2
1U_0402_6.3V6K
@
CH31
0.1U_0201_10V6K
@
CH62
0.1U_0402_25V6
@
CH63
0.1U_0201_10V6K
@
CH64
1
2
+1.0V_DSW
1U_0402_6.3V6K
1
2
+3.3V_RUN_ATS
1U_0402_6.3V6K
1
2
+3.3V_PHVC
0.1U_0402_25V6
1
2
1U_0402_6.3V6K
22U_0603_6.3V6M
1
CH47
CH34
2
CH35
CH36
@
CH66
1
2
+1.0V_DUSB
1
2
1U_0402_6.3V6K
0.1U_0402_25V6
1
CH37
CH67
2
1U_0402_6.3V6K
CH38
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (8/9)
SKYLAKE PCH-H (8/9)
Document Number Re v
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (8/9)
LA-C841P
LA-C841P
LA-C841P
1
23 74Tuesday, September 08, 2015
23 74Tuesday, September 08, 2015
23 74Tuesday, September 08, 2015
0.1
0.1
0.1
Vinafix.com
5
D D
C C
B B
A A
4
UH1I
AC18
VSS
AN4
VSS
AN10
VSS
BE14
VSS
BE18
VSS
BE23
VSS
BE28
VSS
BE32
VSS
BE37
VSS
BE40
VSS
BE9
VSS
C10
VSS
C2
VSS
C28
VSS
C37
VSS
J7
VSS
K10
VSS
K27
VSS
K33
VSS
K36
VSS
K4
VSS
K42
VSS
K43
VSS
L12
VSS
L13
VSS
L15
VSS
L4
VSS
L41
VSS
L8
VSS
M35
VSS
M42
VSS
N10
VSS
N15
VSS
N19
VSS
N22
VSS
N24
VSS
N35
VSS
N36
VSS
N4
VSS
N41
VSS
N5
VSS
P17
VSS
P19
VSS
P22
VSS
P45
VSS
R10
VSS
R14
VSS
R22
VSS
R29
VSS
R33
VSS
R38
VSS
R5
VSS
T1
VSS
T2
VSS
T4
VSS
Y18
VSS
Y20
VSS
Y21
VSS
Y26
VSS
Y28
VSS
Y29
VSS
A18
VSS
A25
VSS
A32
VSS
A37
VSS
AA17
VSS
AA18
VSS
AA20
VSS
AA21
VSS
AA25
VSS
AA29
VSS
AA4
VSS
AA42
VSS
AB10
VSS
SKL-H-PCH_BGA837
SPT-H_PCH
3
SPT-H_PCH
AR5
VSS
AR7
VSS
U15
VSS
AL4
VSS
AE29
VSS
AE4
VSS
AE42
VSS
AF18
VSS
AF20
VSS
AF21
VSS
AF23
VSS
AF25
VSS
AF26
VSS
AF28
VSS
AF29
VSS
AG11
VSS
AG13
VSS
AG31
VSS
AG32
VSS
AG33
VSS
AG38
VSS
AG4
VSS
AH1
VSS
AH17
VSS
AH18
VSS
AH20
VSS
AH21
VSS
AH23
VSS
AH25
VSS
AH26
VSS
AH28
VSS
AH29
VSS
AH45
VSS
AJ10
VSS
AJ14
VSS
AJ15
VSS
AJ17
VSS
AJ18
VSS
AJ26
VSS
AJ28
VSS
AJ29
VSS
AJ31
VSS
AJ32
VSS
AJ36
VSS
AK4
VSS
AK42
VSS
AU7
VSS
AV17
VSS
AV24
VSS
AV27
VSS
AV31
VSS
AV33
VSS
AV6
VSS
AW13
VSS
AW19
VSS
AW29
VSS
AW37
VSS
AW9
VSS
AY38
VSS
AY45
VSS
B25
VSS
B3
VSS
B37
VSS
B40
VSS
B6
VSS
BA1
VSS
BB11
VSS
BB16
VSS
BB21
VSS
BB25
VSS
BB30
VSS
BB34
VSS
BC2
VSS
BD43
VSS
9 OF 12REV = 1.3
UH1L
C42
VSS
D10
VSS
D12
VSS
D15
VSS
D16
VSS
D17
VSS
D19
VSS
D21
VSS
D24
VSS
D25
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
D33
VSS
D35
VSS
D36
VSS
E13
VSS
E15
VSS
E31
VSS
E33
VSS
F44
VSS
F8
VSS
G42
VSS
G9
VSS
H17
VSS
H19
VSS
H22
VSS
H24
VSS
H27
VSS
H29
VSS
H3
VSS
H35
VSS
J10
VSS
J11
VSS
J3
VSS
J39
VSS
J5
VSS
T42
VSS
U10
VSS
U11
VSS
U14
VSS
U17
VSS
U18
VSS
U28
VSS
U29
VSS
U31
VSS
U32
VSS
U33
VSS
U38
VSS
U4
VSS
U8
VSS
V18
VSS
V20
VSS
V21
VSS
V23
VSS
V25
VSS
V29
VSS
V3
VSS
V45
VSS
W14
VSS
W31
VSS
W32
VSS
W33
VSS
W38
VSS
W4
VSS
W8
VSS
Y17
VSS
SKL-H-PCH_BGA837
12 OF 12REV = 1.3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB11
AB7
AB14
AB31
AB32
AB38
AB4
AB5
AC1
AC20
AC21
AC25
AC29
AC45
AB8
AD11
AD14
AB15
AD32
AD33
AD36
AD4
AD8
AE18
AE20
AE21
AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38
AM15
AM17
AM19
AM22
AM24
AM27
AM29
AM45
AN11
AN22
AN27
AN31
AN39
AN7
AN8
AP11
AP4
AR33
AR34
AR42
AR9
AT10
AT15
AT36
AT9
AU1
AU35
AU36
AU39
AU45
C4
2
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size
Size
Size
Date: Sheet o f
Date: Sheet o f
Date: Sheet o f
Compal Electronics, Inc.
SKYLAKE PCH-H (9/9)
SKYLAKE PCH-H (9/9)
Document Number Re v
Document Number Rev
Document Number Rev
SKYLAKE PCH-H (9/9)
LA-C841P
LA-C841P
LA-C841P
24 74Tuesday, September 08, 2015
24 74Tuesday, September 08, 2015
24 74Tuesday, September 08, 2015
1
0.1
0.1
0.1
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