Dell Latitude 3480, Latitude 3488, Latitude 3580 Schematics

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5

D D

4

3

2

1

Taos Schematics

Skylake/Kabylake -U

C C

2016-12-23 REV : A00

B B

DY : None Installed

A A

UMA: UMA only installed OPS: DISCRTE OPTIMUS installed

5

4

3

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Monday, December 26, 2016

Date: Sheet of

Cover Page

Taos KBL-U

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

X00

Vinaﬁx.com

5

Project code: Taos14 -->4PD09Z010001 Taos15 -->4PD0A1010001

Taos KBL-U/SKL-U Block Diagram

PCB P/N: 16852 Revision: A00

D D

VRAM(GDDR3) *4

2GB

78,79

DDR3L

DIS only

DDR4 (2133 MHz)

SODIMM A

DDR4 (2133 MHz)

C C

14"/15" LCD

55

Touch Panel

IR Camera

Digital MIC

55

SODIMM B

USB2.0 x 1

LAN 10/100/1000 RJ45

Conn.

32

B B

HDMI V1.4a

Left side

57

RTL8111HSD

USB2.0 x 1

USB1(USB3.0)

36

Left side

USB3(USB3.0)

35,36

DDR4 2133 MHz Channel A

12

DDR4 2133 MHz Channel B

13

power share

TPS2544RTER-GP

GPU

AMD R16M-M1-30 18W

76,77,78,79,80

31

4

eDP

PCIE x 1

DDI1

34

USB3.0 x 1

USB2.0 x 1

USB3.0 x 1

PCIE x 4

USB2.0 x 1

Intel CPU

KabyLake U 2+2U Skylake

15W (UMA&DIS)

SKL PCH-LP

10 USB 2.0/1.1 ports

6 USB 3.0 ports

High Definition Audio

3 SATA ports 6 PCIE ports LPC I/F ACPI 5.0

3

DDI2

USB2.0 x 1

USB2.0

PCIE x 1

USB2.0 x 1

USB3.0 x 1

PCIe/SATA

USB2.0 x 1

SM Bus

SATA x 1 (Gen3)

LPC BUS

Flash ROM

16MB

SPI

HDD Re-driver

SN75LVCP601 RTJR-GP

Flash ROM

25

NGFF WLAN

802.11a/b/g/n BT V4.0 combo AC 3160

NGFF WWAN

LTE

60

8MB

25

SATA x 1 (Gen3)

2

DP/VGA Converter

REALTEK RTD2166-CGT

right side

USB2(USB2.0)

CardReader

Realtek RTS5144

FRINGERPRINT

NB-2023-U

61

62

uSIM

Free Fall Sensor

ST LNG2DM

HDD P11

HDD

60

KBC

SMSC

MEC1416-NU-GP

PS2

92

63

67

interposer board

LPC debug port

SMBUS

VGA

SD Card Slot

M.2 SSD

68

I2C

24

VGA Conn.

GPIO Expander

IT8010

FAN

DB

1

CHARGER

BQ24786RUYR-GP

INPUTS

AD+

BT+

SYSTEM DC/DC

SY8288CRAC-GP

INPUTS

DCBATOUT

CPU Core Power

NCP81208MNTXG NCP81382MNTXG*2 NCP81253MNTBG

INPUTS

DCBATOUT

DCBATOUT +VCCGT

DDR4

APW8861QBI-TRG-GP

INPUTS OUTPUTS

DCBATOUT 1D2V_S3

OUTPUTS

DCBATOUT

OUTPUTS

PWR_5V 5V_S5 5V_AUX_S5

OUTPUTS

VCC_CORE

+VCCSADCBATOUT

0D6V_S0

CPU DCDC-V1D00A

AOZ2261QI-10-GP-U

INPUTS OUTPUTS

DCBATOUT

LDO-V1D8V

APL5930KAI-TRG-GP

3D3V_S5

CPU VCCPRIM_CORE 1V

INPUTS OUTPUTS

1D0V_S5

OUTPUTSINPUTS

1D8V_S5

+VCCPRIM_CORE1D0V_S5

5V/3V S0

G5016KD1U

INPUTS

5V_S5

VCCSTG

APE8939GN3-GP

5V_S5

VCCST

APE8939GN3-GP

OUTPUTS

5V_S0 3D3V_S03D3V_S5

OUTPUTSINPUTS

+VCCIO +VCCSTG

OUTPUTSINPUTS

+V1.00U_CPU5V_S5 +VCCST_CPU

44

45

46~50

51

53

54

11

40

PCB LAYER

L1:Top L2:VCC L3:Signal L4:Signal L5:GND

96

L6:Bottom

26

TPM 2.0

Atmel: ATTPM20P-G1MA1-ABF

LPC

3

(UDFN, 3.3V, SPI)

China TPM

Z32H320TC

I2C

A A

Universal Jack

29

5

2CH SPEAKER (2CH 2W/4ohm)

29

MIC_IN/GND

HP_R/L

HDA CODEC

Realtek ALC3246

HDA

27

4

91

Flash ROM

128KB

EC

256KB

Precision Touch pad

24

2

Thermal

NUVOTON NCT7718W

65

Int. KB

65

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Block Diagram

Taos KBL-U

1

X00

2 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

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1

Main Func = CPU

D D

C C

(Blanking)

B B

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

(Reserved)

2

Taos KBL-U

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

3 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

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Main Func = CPU

D D

[PECI] and [PROCHOT#] Impedance control: 50 ohm

H_PECI[24]

H_PROCHOT#[24,44,46]

XDP_BPM[3:0][99]

#543016 Rev0.7: Ra = 500 ohm / Rb = 1k ohm #544669 Rev0.52: Ra = 56 ohm (TO BE CHANGED TO 100 OHMS) / Rb = 62 ohm and 150 ohm

C C

INT_TP#[24,65]

B B

TOUCH_PANEL_INTR#[24,55]

3D3V_S5_PCH

3D3V_S0

(#543016) PROCHOT# Routing Guidelines

20161024 0ohm to short pad

R411

1 2

DY

Do Not Stuff

R414

1 2

DS3

100KR2J-1-GP

R410

1 2

NON DS3

Do Not Stuff

Do Not Stuff D401

D401

DS3

RB751V-40H-GP

K A

83.R2004.G8F

R404

1 2

Do Not Stuff

4

+VCCSTG

12

Rb

+VCCSTG = 1.0 V

R401

R401 1KR2J-1-GP

1KR2J-1-GP

Do Not Stuff

R403

H_PROCHOT#_R_R H_PROCHOT#_R

Do Not Stuff

20160621 Merge R412,R413 to RN401 and R415,R418 to R402

R403

1 2

499R2F-2-GP

Ra

TP403

TOUCHPAD_INTR#

TP404

RN401

1 2 3

SRN49D9F-GP

RN402

1 2 3

DY

Do Not Stuff

1

Add resistor by NON DS3 function

TP401

H_CATERR#

1

PCH_THERMTRIP SKTOCC#

1

TP402

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3

GPP_E3/CPU_GP0

GPP_B4/CPU_GP3

CPU_POPIRCOMP

4

PCH_POPIRCOMP

EDRAM_OPIO_RCOMP

4

EOPIO_RCOMP

3

2

1

#544669 CRB Rev0.52

+VCCST_CPU

12

R419

R419 1KR2J-1-GP

1KR2J-1-GP

PCH_THERMTRIP

12

ED401

DY

Do Not Stuff

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

Do Not Stuff

XDP_TCLK [99]

XDP_TDI [99] XDP_TDO_CPU [99] XDP_TMS [99] XDP_TRST# [4,99]

PCH_JTAG_TCK [99] PCH_JTAG_TDI [99] PCH_JTAG_TDO [99] PCH_JTAG_TMS [99] XDP_TRST# [4,99] XDP_TCK_JTAGX [99]

CPU1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U-GP

SKYLAKE_ULT

CPU MISC

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

4 OF 20

JTAGX

+VCCST_CPU = 1.0 V

XDP_TMS XDP_TDI

XDP_TDO_CPU

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

XDP_TCK_JTAGX

XDP_TRST# XDP_TCLK

PCH_JTAG_TCK

20160712 modify Dummy name XDP

1 2

DY

1 2

DY

1 2

DY

1 2

XDP

1 2

XDP

1 2

XDP

1 2

DY

R402 Do Not Stuff

1 2

DY

R406 Do Not Stuff

R406 Do Not Stuff R407 Do Not Stuff

R407 Do Not Stuff

DY

1 2

XDP

1 2

DY

R421Do Not Stuff

R421Do Not Stuff R422Do Not Stuff

R422Do Not Stuff

R423Do Not Stuff

R408Do Not Stuff

R409Do Not Stuff

R416Do Not Stuff

R416Do Not Stuff R417Do Not Stuff

R417Do Not Stuff

+VCCST_CPU

2.DIS

A A

M1,2,3,4,5: <3 inches M6: 1-11 inches MCPU: 0.3-1.5 inches Mt <0.3 mils Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches

5

4

3

Title

Size Document Number Rev

Date: Sheet of

2

CPU_(JTAG/CPU SIDE BAND)

Custom

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

4 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

Main Func = CPU

5

4

3

2

1

DDR4 ball type: Interleaved Type

D D

M_A_DQ0[12] M_A_DQ1[12] M_A_DQ2[12]

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_A_DQ[16:23]

C C

M_A_DQ[24:31]

M_A_DQ[48:55]

M_A_DQ[56:63]

B B

M_A_DQ3[12] M_A_DQ4[12] M_A_DQ5[12] M_A_DQ6[12] M_A_DQ7[12] M_A_DQ8[12]

M_A_DQ9[12] M_A_DQ10[12] M_A_DQ11[12] M_A_DQ12[12] M_A_DQ13[12] M_A_DQ14[12] M_A_DQ15[12] M_A_DQ32[12] M_A_DQ33[12] M_A_DQ34[12] M_A_DQ35[12] M_A_DQ36[12] M_A_DQ37[12] M_A_DQ38[12] M_A_DQ39[12] M_A_DQ40[12] M_A_DQ41[12] M_A_DQ42[12] M_A_DQ43[12] M_A_DQ44[12] M_A_DQ45[12] M_A_DQ46[12] M_A_DQ47[12] M_A_DQ16[12] M_A_DQ17[12] M_A_DQ18[12] M_A_DQ19[12] M_A_DQ20[12] M_A_DQ21[12] M_A_DQ22[12] M_A_DQ23[12] M_A_DQ24[12] M_A_DQ25[12] M_A_DQ26[12] M_A_DQ27[12] M_A_DQ28[12] M_A_DQ29[12] M_A_DQ30[12] M_A_DQ31[12] M_A_DQ48[12] M_A_DQ49[12] M_A_DQ50[12] M_A_DQ51[12] M_A_DQ52[12] M_A_DQ53[12] M_A_DQ54[12] M_A_DQ55[12] M_A_DQ56[12] M_A_DQ57[12] M_A_DQ58[12] M_A_DQ59[12] M_A_DQ60[12] M_A_DQ61[12] M_A_DQ62[12] M_A_DQ63[12]

DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel. Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential clock pair to clock pair swapping within a channel is not allowed.

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

PDG: DDR/ODT

CPU1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

SKYLAKE-U-GP

SKYLAKE_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[ 5]

DDR0_DQ[16]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[ 9]

DDR0_DQ[17]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[ 6]

DDR0_DQ[18]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[ 8]

DDR0_DQ[19]

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[ 7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_DQ[20] DDR0_DQ[21]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[ 12]

DDR0_DQ[22]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[ 11]

DDR0_DQ[23]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[ 13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[ 2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[ 10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[ 1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[ 0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

DDR CH - A

2 OF 20

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 AH66 AH65 AG69 AG70 BA64 AY64 AY60 BA60 AR66 AR65 AR61 AR60

AW50 AT52

AY67 AY68 BA67

AW67

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_A2 M_A_A10

M_A_A1 M_A_A0 M_A_A3 M_A_A4

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1

M_A_DQS_DP1 M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN5 M_A_DQS_DP5

M_A_DQS_DN2

M_A_DQS_DP2

M_A_DQS_DN3

M_A_DQS_DP3 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7

SM_PGCNTL

M_A_CLK#0 [12] M_A_CLK0 [12] M_A_CLK#1 [12] M_A_CLK1 [12]

M_A_CKE0 [12] M_A_CKE1 [12]

M_A_CS#0 [12] M_A_CS#1 [12] M_A_DIMA_ODT0 [12] M_A_DIMA_ODT1 [12]

M_A_A5 [12] M_A_A9 [12] M_A_A6 [12] M_A_A8 [12] M_A_A7 [12]

M_A_BG0 [12]

M_A_A12 [12]

M_A_A11 [12] M_A_ACT_N [12] M_A_BG1 [12]

M_A_A13 [12]

M_A_A15 [12]

M_A_A14 [12]

M_A_A16 [12] M_A_BA0 [12]

M_A_A2 [12]

M_A_BA1 [12]

M_A_A10 [12]

M_A_A1 [12] M_A_A0 [12]

M_A_A3 [12] M_A_A4 [12]

M_A_DQS0

M_A_DQS1 M_A_DQS4 M_A_DQS5

M_A_DQS2

M_A_DQS3 M_A_DQS6 M_A_DQS7

M_A_ALERT_N [12] M_A_PARITY [12]

V_SM_VREF_CN TA [12] V_SM_VREF_CN TB [13]

SM_PGCNTL

M_B_DQ[0:7]

M_B_DQ[8:15]

M_B_DQ[32:39]

M_B_DQ[40:47]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[48:55]

M_B_DQ[56:63]

3D3V_S5

12

DS

G

R507

R507 10KR2J-3-GP

10KR2J-3-GP

Q501

Q501 DMN5L06K-7-G P

DMN5L06K-7-G P

84.05067.031

Q502_G

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQ0[13] M_B_DQ1[13] M_B_DQ2[13] M_B_DQ3[13] M_B_DQ4[13] M_B_DQ5[13] M_B_DQ6[13] M_B_DQ7[13] M_B_DQ8[13] M_B_DQ9[13] M_B_DQ10[13] M_B_DQ11[13] M_B_DQ12[13] M_B_DQ13[13] M_B_DQ14[13] M_B_DQ15[13] M_B_DQ32[13] M_B_DQ33[13] M_B_DQ34[13] M_B_DQ35[13] M_B_DQ36[13] M_B_DQ37[13] M_B_DQ38[13] M_B_DQ39[13] M_B_DQ40[13] M_B_DQ41[13] M_B_DQ42[13] M_B_DQ43[13] M_B_DQ44[13] M_B_DQ45[13] M_B_DQ46[13] M_B_DQ47[13] M_B_DQ16[13] M_B_DQ17[13] M_B_DQ18[13] M_B_DQ19[13] M_B_DQ20[13] M_B_DQ21[13] M_B_DQ22[13] M_B_DQ23[13] M_B_DQ24[13] M_B_DQ25[13] M_B_DQ26[13] M_B_DQ27[13] M_B_DQ28[13] M_B_DQ29[13] M_B_DQ30[13] M_B_DQ31[13] M_B_DQ48[13] M_B_DQ49[13] M_B_DQ50[13] M_B_DQ51[13] M_B_DQ52[13] M_B_DQ53[13] M_B_DQ54[13] M_B_DQ55[13] M_B_DQ56[13] M_B_DQ57[13] M_B_DQ58[13] M_B_DQ59[13] M_B_DQ60[13] M_B_DQ61[13] M_B_DQ62[13] M_B_DQ63[13]

AY39

AW39

AY37

AW37

BB39 BA39 BA37 BB37 AY35

AW35

AY33

AW33

BB35 BA35 BA33 BB33 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AY31

AW31

AY29

AW29

BB31 BA31 BA29 BB29 AY27

AW27

AY25

AW25

BB27 BA27 BA25 BB25 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

Q502

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

CPU1C

DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

SKYLAKE-U-GP

3D3V_S0

12

R506

R506 220KR2F-GP

220KR2F-GP

D

SKYLAKE_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[ 5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[ 9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[ 6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[ 8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[ 7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[ 12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[ 11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[ 13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[ 2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[ 10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[ 1]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[ 0]

DDR CH - B

SM_PGCNTL_R [51]

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR1_MA[4]

DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

Design Guideline:

Design Guideline: SM_RCOMP keep routing length less than 500 mils.

SM_RCOMP keep routing length less than 500 mils.

3 OF 20

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_A12 M_B_A11 M_B_ACT_N

M_B_A13 M_B_A15 M_B_A14 M_B_A16

M_B_A2 M_B_A10

M_B_A1 M_B_A0 M_B_A3 M_B_A4

M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN1

M_B_DQS_DP1 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5

M_B_DQS_DN2

M_B_DQS_DP2

M_B_DQS_DN3

M_B_DQS_DP3 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

SM_DRAMRST # SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

#543016

M_B_CLK#0 [13] M_B_CLK#1 [13] M_B_CLK0 [13] M_B_CLK1 [13]

M_B_CKE0 [13] M_B_CKE1 [13]

M_B_CS#0 [13] M_B_CS#1 [13] M_B_DIMB_ODT0 [13] M_B_DIMB_ODT1 [13]

M_B_A5 [13] M_B_A9 [13] M_B_A6 [13] M_B_A8 [13] M_B_A7 [13]

M_B_BG0 [13]

M_B_A12 [13]

M_B_A11 [13] M_B_ACT_N [13] M_B_BG1 [13]

M_B_A13 [13]

M_B_A15 [13]

M_B_A14 [13]

M_B_A16 [13] M_B_BA0 [13]

M_B_A2 [13]

M_B_BA1 [13]

M_B_A10 [13]

M_B_A1 [13] M_B_A0 [13] M_B_A3 [13] M_B_A4 [13]

M_B_DQS0 M_B_DQS1

M_B_DQS4 M_B_DQS5

M_B_DQS2

M_B_DQS3 M_B_DQS6 M_B_DQS7

M_B_ALERT_N [13]

M_B_PARITY [13]

R501 121R2F- GPR501 121R2F- GP

1 2

R502 80D6R2F -L-GPR 502 80D6R2F -L-GP

1 2

R503 100R2F- L1-GP-UR503 100R2F- L1-GP-U

1 2

Layout Note:Layout Note:

1D2V_S3

12

close to CPU

R505

R505 470R2F-GP

470R2F-GP

DY

1 2

R504

1 2

Do Not Stuff

ED502

Do Not Stuff

DDR4_DR AMRST# [12,13]

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6

3

M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

A A

5

4

M_A_DQS_DN[7: 0] [12] M_B_DQS_DN[7: 0] [13]

M_A_DQS_DP[7:0] [12]

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

2

M_B_DQS_DP[7:0] [13]

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(DDR)

Taos KBL-U

1

5 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

CPU1S

RESERVED SIGNALS-1

CFG[19:0][99]

D D

ITP_PMODE[99]

C C

TP601Do Not Stuff TP601Do Not Stuff TP602Do Not Stuff TP602Do Not Stuff

B B

PCH strap pin:

CFG3

DY

12

R604

R604 Do Not Stuff

Do Not Stuff

12

1 1

R60149D9R2F-GP R60149D9R2F-GP

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

CFG_RCOMP

RSVD_TP_BA70 RSVD_TP_BA68

G69 G68

H70 G71 H69 G70

E63

E66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

A52

BA70 BA68

G65

E61

E68 B67 D65 D67 E70 C68 D68 C67 F71

F70

F63

F66

F60

J71 J68

F65

F61

E8

D1 D3

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD#AY2

RSVD#AY1 RSVD#D1

RSVD#D3 RSVD#K46

RSVD#K45 RSVD#AL25

RSVD#AL27 RSVD#C71

RSVD#B70 RSVD#F60 RSVD#A52 RSVD_TP#BA70

RSVD_TP#BA68 RSVD#J71

RSVD#J68 VSS

VSS RSVD#F61

RSVD#E61

SKYLAKE-U-GP

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

RESERVED SIGNALS-1

SKYLAKE_ULT

RSVD_TP_AW71 RSVD_TP_AW70

1 : DISABLED

CFG4

12

R605

R605 1KR2J-1-GP

1KR2J-1-GP

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default) No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

19 OF 20

RSVD_TP#BB68 RSVD_TP#BB69

RSVD_TP#AK13 RSVD_TP#AK12

RSVD#BB2 RSVD#BA3

TP5 TP6

RSVD#D5 RSVD#D4 RSVD#B2 RSVD#C2

RSVD#B3 RSVD#A3

RSVD#AW1

RSVD#E1 RSVD#E2

RSVD#BA4 RSVD#BB4

RSVD#A4 RSVD#C4

TP4

RSVD#A69 RSVD#B69

RSVD#AY3 RSVD#D71

RSVD#C70 RSVD#C54

RSVD#D54

TP1 TP2

VSS

ZVM#

RSVD_TP#AW71 RSVD_TP#AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3 D71

C70 C54

D54 AY4

BB3 AY71

AR56 AW71

AW70 AP56

C64

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

TP5_AU5 TP6_AT5

TP4_BB5

TP1_AY4 TP2_BB3

VSS_AY71 ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM# PROC_SELECT#

R602

1 2

Do Not Stuff

1 2

R603

R603 Do Not Stuff

Do Not Stuff

DY

1 1

1

1 1

TP603 Do Not StuffTP603 Do Not Stuff TP604 Do Not StuffTP604 Do Not Stuff

TP605 Do Not StuffTP605 Do Not Stuff TP606 Do Not StuffTP606 Do Not Stuff

TP607 Do Not StuffTP607 Do Not Stuff TP608 Do Not StuffTP608 Do Not Stuff

TP609 Do Not StuffTP609 Do Not Stuff

TP610 Do Not StuffTP610 Do Not Stuff TP611 Do Not StuffTP611 Do Not Stuff

TP616 Do Not StuffTP616 Do Not Stuff TP614 Do Not StuffTP614 Do Not Stuff

TP615 Do Not StuffTP615 Do Not Stuff TP617 Do Not StuffTP617 Do Not Stuff

#54469 CRB.

CFG TERMINATIONS

20140807 david

#544669 Rev0.52 (CRB)

+VCCST_CPU

A A

5

SKL(#543016): Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*

4

3

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(RESERVED)

Taos KBL-U

6 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

CPU1M

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A48 A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69

J70 J69

CPU1M

CPU POWER 2 OF 4

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

SKYLAKE-U-GP

SKYLAKE_ULT

+VCCGT

CPU1L

AM32 AM33 AM35 AM37 AM38

AG62

AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AK32 AB62

AC63 AE63

AE62

AL63 AJ62

A30 A34 A39 A44

G30 K32

P62 V62

H63 G61

CPU1L

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

RSVD_K32

RSVD#K32

RSVD_AK32

RSVD#AK32 VCCOPC

VCCOPC VCCOPC

VCC_OPC_1P8 VCC_OPC_1P8 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO

VCCEOPIO VCCEOPIO_SENSE

VSSEOPIO_SENSE

SKYLAKE-U-GP

CPU POWER 1 OF 4

SKYLAKE_ULT

VCC_CORE VCC_C ORE

D D

12

FC701Do Not StuffDYFC701Do Not Stuff

DY

TP704Do N ot Stuff TP7 04Do Not Stuff

C C

Layout Note: The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch). Route the Alert signal between the Clock and the Data signals.

VCC_OPC_1P8 _H63

1

12 OF 20

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT VCCSTG

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

E32 E33

H_CPU_SVIDALR T#

B63

H_CPU_SVIDC LK

A63

H_CPU_SVIDD AT

D64

+VCCFUSE PRG

G20

20160607 add 0.1u to +Vccgt don’t DY

12

FC702Do Not StuffDYFC702Do Not Stuff

DY

VCC_SENSE [7,46] VSS_SENSE [7,46 ]

R703

1 2

Do Not Stuff

20161024 0ohm to short pad

VCCGT_SEN SE[7,46] VSSGT_SENSE[7,46]

+VCCSTG

12

FC703SCD1U25V2KX-GP

WWAN

SVID DATA

+VCCST_CP U

CLOSE TO CPU

H_CPU_SVIDD AT

SVID CLOCK

B B

H_CPU_SVIDC LK

12

R726

#543016

100R2F-L1-GP- U

1 2

20161024 0ohm to short pad

Do Not Stuff

R732

1 2

20161024 0ohm to short pad

Do Not Stuff

R709

+VCCST_CP U

12

R723

DY

Do Not Stuff

#543016 CLOSE TO VR

VR_SVID_DATA [46]

VR_SVID_CLK [46]

SVID_543016:

13 OF 20

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGTX_SENSE

VSSGTX_SENSE

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCCGT

+VDDQ_CPU _CLK

12

FC704Do Not StuffDYFC704Do Not Stuff

DY

20160617 follow up vegas as the same DY

12

DY

20160822 DY to stuff 1u to 470P by RF

C722

C722 Do Not Stuff

Do Not Stuff

FC705

20160712 stuff by location

#544669 CRB.

R705

1 2

Do Not Stuff

20161024 0ohm to short pad

SC470P50V2KX-L-GP

WWAN

12

DY

DY DY

DY

+VDDQ_CPU _CLK1D2V_S3

1D2V_S3

12

FC708Do Not StuffDYFC708Do Not Stuff

DY

12

C719

C719 Do Not Stuff

Do Not Stuff

+VDDQ_CPU _CLK

C715S C10U6D3V3MX- GP C715SC10U6D3V3MX-GP

+VCCST_CP U

C716D o Not Stuff

+VCCSTG

C717D o Not Stuff

1D2V_S3

C718D o Not Stuff

+V1.00U_CPU

12

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

+VCCIO

+VCCIO(ICCMAX.=2.73A)

+VCCSA

VCCSA_SENS E VSSSA_SENSE

12

FC706Do Not StuffDYFC706Do Not Stuff

DY

12

FC707Do Not StuffDYFC707Do Not Stuff

DY

VSSSA_SENSE [46] VCCSA_SENS E [ 46]

+VCCSA

12

R735

R735 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R734

R734 100R2F-L1-GP- U

100R2F-L1-GP- U

CPU1N

CPU POWER 3 OF 4

AU23

VDDQ

AU28

VDDQ

AU35

VDDQ

AU42

VDDQ

BB23

VDDQ

BB32

VDDQ

BB41

VDDQ

BB47

VDDQ

BB51

VDDQ

AM40

0.12 A

C721

Do Not Stuff

VCC_CORE

+VCCGT

A18 A22

AL23

K20 K21

12

R719

R719 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R720

R720 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R721

R721 100R2F-L1-GP- U

100R2F-L1-GP- U

12

R722

R722 100R2F-L1-GP- U

100R2F-L1-GP- U

VDDQC VCCST VCCSTG VCCPLL_OC VCCPLL

VCCPLL

SKYLAKE-U-GP

0.04 A

12

C720

DY

SCD1U16V2KX-3GP

14 OF 20

VCCIO VCCIO

SKYLAKE_ULT

VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

VCC_SENSE [7,46]

VSS_SENSE [7,46]

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Length match<25mil

VCCGT_SEN SE [7,46]

VSSGT_SENSE [7,46]

+VCCST_CP U

#543016

12

CLOSE TO CPU

R727

R727 56R2J-4-GP

56R2J-4-GP

R728

H_CPU_SVIDALR T#

A A

R728

12

220R2J-L2-GP

5

VR_SVID_ALERT# [46]

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Monday, Decemb er 26, 2016

Date: Sheet of

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU(VCC_CORE)

Taos KBL-U

1

7 105

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

D D

CPU1A

SKYLAKE_ULT

HDMI_DATA2#[57]

HDMI_DATA2[57]

HDMI

3D3V_S0

RN801

2 3 1

SRN2K2J-1-GP

C C

3D3V_S0

R804

1 2

2K2R2J-2-GP

2K2R2J-2-GP R803

R803

1 2

Do Not Stuff

DY

CPU_DP1_CTRL_DATA CPU_DP1_CTRL_CLK

4

CPU_DP2_CTRL_DATA

CPU_DP2_CTRL_CLK

DP to VGA

HDMI

Check

+VCCIO

HDMI_DATA1#[57]

HDMI_DATA1[57]

HDMI_DATA0#[57]

HDMI_DATA0[57]

HDMI_CLK#[57]

PCH_DPC_N0[66]

PCH_DPC_P0[66]

PCH_DPC_N1[66]

PCH_DPC_P1[66]

R801

1 2

24D9R2F-L-GP

HDMI_CLK[57]

CPU_DP1_CTRL_CLK[57]

CPU_DP1_CTRL_DATA[57]

Do Not Stuff

TP802

CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA

DDPD_CTRLDATA

1

EDP_COMP

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%

Isolation Spacing

Resistor Value

Length

Max = 100 mils

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22

N12

GPP_E23

E52

EDP_RCOMP

SKYLAKE-U-GP

(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.

SKYLAKE_ULT

DDI

DISPLAY SIDEBANDS

Strap

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

1 OF 20

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

RSVD#G46

RSVD#F46

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_DISP_UTIL

CPU_DP2_HPD1

1

R805

1 2

Do Not Stuff

eDP_TX_CPU_N0 [55] eDP_TX_CPU_P0 [55] eDP_TX_CPU_N1 [55] eDP_TX_CPU_P1 [55]

eDP_AUX_CPU_N [55] eDP_AUX_CPU_P [55]

TP801 Do Not StuffTP801 Do Not Stuff

PCH_DPC_AUXN [66] PCH_DPC_AUXP [66]

CPU_DP1_HPD [57] CPU_DP2_HPD [66] SIO_EXT_SMI#_R [24]

EDP_HPD [55]

L_BKLT_EN [24] L_BKLT_CTRL [55] EDP_VDD_EN [55]

3D3V_S0

(#543016) DDI Disabling and Termination Guidelines

B B

Port Strap Enable Port Disable Port

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

PU to 3.3 V with 2.2-k ±5% resistor

NC

SIO_EXT_SMI#_R

Strap pin:

Port B / Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

These two signals have weak internal pull-down.

Design Guideline: Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.

A A

5

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected. 1 = Port B is detected.

*

0 = Port C is not detected. 1 = Port C is detected.

*

4

3

12

R806

R806 100KR2J-1-GP

100KR2J-1-GP

R802 10KR2J-3-GPR802 10KR2J-3-GP

1 2

CPU_DP2_HPD

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(DISPLAY)

Taos KBL-U

8 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

D D

C C

(Blanking)

B B

2.DIS

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

(Reserved)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

9 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

Main Func = CPU

5

4

3

2

1

(#543016 PDG)

CORE

D D

C C

VCC_CORE

+VCCIO

PC1001

12

PC1010

12

PC1021

12

SC22U6D3V3MX-1-GP

PC1002

12

PC1011

12

PC1022

12

PC1003

12

SC22U6D3V3MX-1-GP

PC1012

12

SC22U6D3V3MX-1-GP

PC1023

12

SC22U6D3V3MX-1-GP

22U 0603 x 30

PC1005

PC1004

12

SC22U6D3V3MX-1-GP

PC1014

PC1013

12

SC22U6D3V3MX-1-GP

PC1024

PC1025

12

SC22U6D3V3MX-1-GP

PC1006

12

PC1015

12

PC1026

12

SC22U6D3V3MX-1-GP

PC1008

PC1007

12

SC22U6D3V3MX-1-GP

PC1016

PC1017

12

SC22U6D3V3MX-1-GP

PC1027

PC1028

12

SC22U6D3V3MX-1-GP

+VCCPRIM_COR E

PC1009

12

SC22U6D3V3MX-1-GP

20160607 add 0.1U to Vcc_CoreF DON’T DY

PC1019

PC1020

PC1018

12

SC22U6D3V3MX-1-GP

PC1030

PC1029

12

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

FC1002SCD1U25V2KX-GP

FC1001Do Not StuffDYFC1001Do Not Stuff

FC1003Do Not StuffDYFC1003Do Not Stuff

WWAN

DY

20160822 change 22u to 10 u and stuff by EMI

+VCCSA

12

VCCSA

1D2V_S3

12

PC1056SC10U6D3V3MX-GP PC1056SC10U6D3V3MX-GP

PC1055SC10U6D3V3MX-GP PC1055SC10U6D3V3MX-GP

12

EC1063Do Not StuffDYEC1063Do Not Stuff

EC1062Do Not StuffDYEC1062Do Not Stuff

DY

PC1046

PC1048

12

SC22U6D3V3MX-1-GP

20160822 stuff by EMI

20161208 change stuff to DY

12

PC1058SC10U6D3V3MX-GP PC1058SC10U6D3V3MX-GP

PC1057SC10U6D3V3MX-GP PC1057SC10U6D3V3MX-GP

12

EC1001Do Not StuffDYEC1001Do Not Stuff

PC1064

DY

Do Not Stuff

20160822 change EC to FC ,DY to stuff and 1u to 470P by RF

EC1059Do Not StuffDYEC1059Do Not Stuff

DY

FC1006

SC470P50V2KX-L-GP

WWAN

12

EC1060Do Not StuffDYEC1060Do Not Stuff

DY

12

EC1004Do Not StuffDYEC1004Do Not Stuff

DY

10U 0603 x 4

12

PC1061Do Not StuffDYPC1061Do Not Stuff

DY

12

FC1005

EC1002Do Not StuffDYEC1002Do Not Stuff

SC470P50V2KX-L-GP

WWAN

DY

22U 0603 x 9

PC1053

PC1049

12

PC1050

PC1051

12

SC22U6D3V3MX-1-GP

PC1053

PC1052

12

SC22U6D3V3MX-1-GP

DY

12

20160822 stuff by EMI 20160823 change EMI to RD and 1u to 470P

Do Not Stuff

+VCCIO(ICCMAX.=2.73A)

12

PC1037Do Not StuffDYPC1037Do Not Stuff

PC1036S C22U6D3V3MX-1-GP PC1036SC22U6D3V3MX-1-GP

PC1035S C22U6D3V3MX-1-GP PC1035SC22U6D3V3MX-1-GP

B B

+VCCGT

DY

VCCGT

PC1031

12

SC22U6D3V3MX-1-GP

PC1032

12

PC1033

12

SC22U6D3V3MX-1-GP

PC1038

PC1039

12

SC22U6D3V5MX-2GP

22U 0603 x28

PC1034

PC1041

12

SC22U6D3V3MX-1-GP

PC1097

PC1098

Do Not Stuff

PC1079

12

PC1098

12

Do Not Stuff

DY

SC22U6D3V3MX-1-GP

12

FC1004Do Not StuffDYFC1004Do Not Stuff

DY

PC1068

PC1066

PC1074

12

PC1065

12

SC22U6D3V3MX-1-GP

PC1075

12

PC1066

12

DY

PC1076

12

SC22U6D3V3MX-1-GP

PC1047

PC1054

PC1070

12

PC1054

12

SC22U6D3V3MX-1-GP

PC1072

PC1071

PC1073

12

SC22U6D3V3MX-1-GP

12

PC1069

PC1044

PC1042

12

SC22U6D3V3MX-1-GP

PC1044

PC1043

12

SC22U6D3V3MX-1-GP

12

SC22U6D3V3MX-1-GP

PC1068

PC1067

12

Do Not Stuff

DY

PC1078

PC1077

12

SC22U6D3V3MX-1-GP

PC1094

PC1085

PC1086

PC1084

12

PC1086

12

SC22U6D3V3MX-1-GP

PC1080

12

SC22U6D3V3MX-1-GP

A A

5

12

SC22U6D3V3MX-1-GP

PC1083

PC1081

PC1082

PC1080

PC1087

12

PC1089

PC1090

PC1088

12

SC22U6D3V3MX-1-GP

DY

PC1091

12

Do Not Stuff

DY

4

PC1092

12

PC1094

PC1093

PC1095

PC1096

12

Do Not Stuff

DY

Do Not Stuff

DY

Do Not Stuff

DY

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(Power CAP1)

Taos KBL-U

1

X00

10 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = CPU

20160712 DY

+VCCGT

12

C1136

C1138

DY

Do Not Stuff

D D

12

C1147

12

C1150

C1149

C1148

DY

Do Not Stuff

1U 0402 x 6

DY

Do Not Stuff

+VCCIO

+VCCIO(ICCMAX.=2.73A)

12

C1151

C1152

SC1U10V2KX-1GP

VCCIO

12

C1153

C1154

SC1U10V2KX-1GP

PCH DERIVED RAILS

R1117

1 2

Do Not Stuff

R1118

1 2

Do Not Stuff

R1112

Do Not Stuff

+VCCPRIM_COR E

20161026 0ohm to short pad

+V1.00A_SIP

C1113

Do Not StuffDYC1113

Do Not Stuff

12

DY

1D0V_S5

C C

20161024 0ohm to short pad

3D3V_S5_PCH +V3.3A_SIP

1 2

20161024 0ohm to short pad

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

20160630 change +1.8V to 1D8V_S5

1D8V_S5 +V1.8A_S IP

R1139

1 2

B B

A A

Do Not Stuff

20161024 0ohm to short pad

20160712 DY

VCC_CORE

C1122

Do Not StuffDYC1122

Do Not Stuff

12

DY

20160712 DY

+V3.3A_SIP

12

C1103

C1101

C1102

DY

Do Not Stuff

12

C1116

C1117

DY

Do Not Stuff

1U 0402 x 5

+V3.3A_SIP

C1123

Do Not StuffDYC1123

Do Not Stuff

20160720 change 78.10623.51L to 78.10610.5BL

12

DY

C1183

+VCCMPHYGTA ON_1P0_LS_SIP

12

C1182

C1174

C1182

SC1U10V2KX-1GP

DY

+VCCMPHYGTA ON_1P0_LS_SIP

R1101

Do Not Stuff

1 2

Do Not Stuff

20161024 0ohm to short pad

+VCCAPLLEBB_1 P0 +VCCMPHYGTA ON_1P0_LS_SIP

C1180

C1173

12

DY

Do Not Stuff

SC1U10V2KX-1GP

+VCCMPHYGTA ON_1P0_LS_SIP

R1102

1 2

Do Not Stuff

20161024 0ohm to short pad

+VCCAMPHYPLL_1P 0_L

SC22U6D3V3MX-1-GP

12

C1181

C1172

SC1U10V2KX-1GP

12

20161024 0ohm to short pad

20160720 change 78.10623.51L to 78.10610.5BL

R1106

1 2

Do Not Stuff

+VCCSRAM_1P 0

12

C1176

SC10U6D3V3MX-GP

C1175

SC1U10V2KX-1GP

U-line 23e 28W IccMax current-10ms max = 34 A

5

2.DIS

SC10U6D3V3MX-GP

4

3

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(Power CAP2)

Taos KBL-U

1

11 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

Main Func = DDR SODIMM

5

4

3

2

1

20160815 DM1 DM2 change symbol

M_A_A0[5]

M_A_A1[5] M_A_A2[5] M_A_A3[5] M_A_A4[5] M_A_A5[5] M_A_A6[5] M_A_A7[5] M_A_A8[5]

D D

C C

1D2V_S3

1 2

R1215 Do Not Stuff

ED1217

ED1217 Do Not Stuff

Do Not Stuff

R1215 Do Not Stuff

DDR4_DR AMRST#

12

DY

M_A_A9[5] M_A_A10[5] M_A_A11[5] M_A_A12[5] M_A_A13[5] M_A_A14[5] M_A_A15[5] M_A_A16[5]

M_A_BA0[5]

M_A_BA1[5]

M_A_BG0[5]

M_A_BG1[5]

M_A_CLK0[5]

M_A_CLK#0[5]

M_A_CLK1[5]

M_A_CLK#1[5]

M_A_CKE0[5] M_A_CKE1[5]

M_A_CS#0[5] M_A_CS#1[5]

M_A_DIMA_ODT0[5] M_A_DIMA_ODT1[5]

DDR4_DR AMRST#[5,13] M_A_ACT_N[5] M_A_ALERT_N[5]

DY

M_A_PARITY[5]

12

C1229

SCD1U16V2KX-3GP

PCH_SMBDAT A[13,18,65,66,67,99]

PCH_SMBCLK[13,18,65,66,67,99]

SA0_CHA_DIM0 SA1_CHA_DIM0 SA2_CHA_DIM0

TS#_DIMM0_1

M_VREF_CA_D IMMA

DM1A

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

WE#/A14

156

CAS#/A15

152

RAS#/A16

150

BA0

145

BA1

115

BG0

113

BG1

92

CB0/NC

91

CB1/NC

101

CB2/NC

105

CB3/NC

88

CB4/NC

87

CB5/NC

100

CB6/NC

104

CB7/NC

137

CK0_T

139

CK0_C

138

CK1_T/NF

140

CK1_C/NF

109

CKE0

110

CKE1

149

CS0#

157

CS1#

162

C0/CS2#/NC

165

C1/CS3#/NC

155

ODT0

161

ODT1

256

SA0

260

SA1

166

SA2

254

SDA

253

SCL

108

RESET#

114

ACT#

116

ALERT#

134

EVENT#/NF

143

PARITY

164

VREFCA

DDR4-260P-9-GP-U

062.10011.00J1

Layout note: closed to Dimm

1D2V_S3

RN1201

1

4

2 3

SRN1KJ-7-G P

B B

M_VREF_CA_D IMMA

R1206

1 2

2R2F-GP

12

C1222

C1222 SCD022U16V2KX -3GP

SCD022U16V2KX -3GP

+V_VREF_PATH 1

12

R1209

24D9R2F-L-G P

V_SM_VREF_CN TA [5]

1 OF 4

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

4 OF 4

DM1D

4 OF 4

0D6V_S0

12

C1225

10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

SC1U10V2KX-1GP

DM1D

VSS1VSS

2

VSS

5

VSS

6

VSS

9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR4-260P-9-GP-U

12

C1226

SC1U10V2KX-1GP

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

UN 0225

0D6V_S0

12

C1223

C1230

Do Not Stuff

DY

for placement modifu 2015/10/19

2D5V_S3

12

C1211

DY

12

C1231

Do Not Stuff

DY

C1232

0D6V_S0

DY

Do Not Stuff

12

C1227

C1224

Do Not Stuff

DY

12

C1213

C1212

DY

C1213

C1207

Do Not Stuff

SC1U10V2KX-1GP

DY

Do Not Stuff

8

DQ0

7

DQ1

20

DQ2

21

DQ3

4

DQ4

3

DQ5

16

DQ6

17

DQ7

28

DQ8

29

DQ9

41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

20160615 DDR swap

3D3V_S0

M_A_DQ0 [5] M_A_DQ1 [5] M_A_DQ2 [5] M_A_DQ3 [5] M_A_DQ4 [5] M_A_DQ5 [5] M_A_DQ6 [5] M_A_DQ7 [5] M_A_DQ8 [5] M_A_DQ9 [5] M_A_DQ10 [5] M_A_DQ11 [5] M_A_DQ12 [5] M_A_DQ13 [5] M_A_DQ14 [5] M_A_DQ15 [5] M_A_DQ16 [5] M_A_DQ17 [5] M_A_DQ18 [5] M_A_DQ19 [5] M_A_DQ20 [5] M_A_DQ21 [5] M_A_DQ22 [5] M_A_DQ23 [5] M_A_DQ24 [5] M_A_DQ25 [5] M_A_DQ26 [5] M_A_DQ27 [5] M_A_DQ28 [5] M_A_DQ29 [5] M_A_DQ30 [5] M_A_DQ31 [5] M_A_DQ45 [5] M_A_DQ40 [5] M_A_DQ47 [5] M_A_DQ46 [5] M_A_DQ41 [5] M_A_DQ44 [5] M_A_DQ43 [5] M_A_DQ42 [5] M_A_DQ37 [5] M_A_DQ33 [5] M_A_DQ35 [5] M_A_DQ39 [5] M_A_DQ32 [5] M_A_DQ36 [5] M_A_DQ34 [5] M_A_DQ38 [5] M_A_DQ51 [5] M_A_DQ50 [5] M_A_DQ55 [5] M_A_DQ54 [5] M_A_DQ52 [5] M_A_DQ53 [5] M_A_DQ48 [5] M_A_DQ49 [5] M_A_DQ57 [5] M_A_DQ56 [5] M_A_DQ58 [5] M_A_DQ61 [5] M_A_DQ59 [5] M_A_DQ63 [5] M_A_DQ62 [5] M_A_DQ60 [5]

󴴨󴴨󴴨󴴨sw󳠃󳠃󳠃󳠃󴧖󴧖󴧖󴧖

R1204 Do N ot Stuff

12

DY

1 2

Do Not Stuff

R1208 Do N ot Stuff

DY

1 2

Do Not Stuff

R1211 Do N ot Stuff

DY

1 2

Do Not Stuff

12

R1205

R1210

R1212

1D2V_S3

DM1B

20160615 DDR swap

DM0#/DBI0# DM2#/DBI2#

DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

DM8#/DBI#/NC

DDR4-260P-9-GP-U

SA0_CHA_DIM0

SA1_CHA_DIM0

SA2_CHA_DIM0

2 OF 4

DQS0_C DQS0_T DQS1_C DQS1_T DQS2_C DQS2_T DQS3_C DQS3_T DQS4_C DQS4_T DQS5_C DQS5_T DQS6_C DQS6_T DQS7_C DQS7_T DQS8_C DQS8_T

DM1#/DBI#

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

11 13 32 34 53 55 74 76 177 179 198 200 219 221 240 242 95 97

12 33 54 75 178 199 220 241 96

DM1C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-9-GP-U

1D2V_S3

M_A_DQS_DN0 M_A_DQS_DP0 M_A_DQS_DN1 M_A_DQS_DP1 M_A_DQS_DN2 M_A_DQS_DP2 M_A_DQS_DN3 M_A_DQS_DP3 M_A_DQS_DN5 M_A_DQS_DP5 M_A_DQS_DN4 M_A_DQS_DP4 M_A_DQS_DN6 M_A_DQS_DP6 M_A_DQS_DN7 M_A_DQS_DP7

3 OF 4

VDDSPD

VPP VPP

VTT

261 262

NP1 NP2

12

C1208

SC10U6D3V3MX-GP

12

C1214

SC1U10V2KX-1GP

12

C1202

12

C1215

1D2V_S3

3D3V_S0

255

257 259

258

261 262

NP1 NP2

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

12

C1209

Do Not Stuff

DY

12

C1216

SC1U10V2KX-1GP

M_A_DQS_DN0 M_A_DQS_DN1 M_A_DQS_DN2 M_A_DQS_DN3 M_A_DQS_DN4 M_A_DQS_DN5 M_A_DQS_DN6 M_A_DQS_DN7

M_A_DQS_DP0 M_A_DQS_DP1 M_A_DQS_DP2 M_A_DQS_DP3 M_A_DQS_DP4 M_A_DQS_DP5 M_A_DQS_DP6 M_A_DQS_DP7

DY

0D6V_S0

12

C1203

Do Not Stuff

12

C1217

Do Not Stuff

2D5V_S3

12

C1228

R1216

Do Not Stuff

DY

12

C1204

SC10U6D3V3MX-GP

12

C1218

Do Not Stuff

DY

12

C1206

C1205

C1210

Do Not Stuff

SC10U6D3V3MX-GP

DY

12

EC1220

C1221

C1219

SC1U10V2KX-1GP

Do Not Stuff

SCD1U25V2KX-GP

20160822 change C1220 to EC1220 and stuff by EMI

M_A_DQS_DN[7: 0] [5]

M_A_DQS_DP[7:0] [5]

A A

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Monday, Decemb er 26, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM1

Taos KBL-U

1

12 105

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = DDR4 SODIMM

DM2A

SA0_CHB_DIM0 SA1_CHB_DIM0 SA2_CHB_DIM0

TS#_DIMM1_1

144 133 132 131 128 126 127 122 125 121 146 120 119 158 151 156 152

150 145 115 113

92

91 101 105

88

87 100 104

137 139 138 140

109 110

149 157 162 165

155 161

256 260 166

254 253

108 114 116 134

143 164

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 WE#/A14 CAS#/A15 RAS#/A16

BA0 BA1 BG0 BG1

CB0/NC CB1/NC CB2/NC CB3/NC CB4/NC CB5/NC CB6/NC CB7/NC

CK0_T CK0_C CK1_T/NF CK1_C/NF

CKE0 CKE1

CS0# CS1# C0/CS2#/NC C1/CS3#/NC

ODT0 ODT1

SA0 SA1 SA2

SDA SCL

RESET# ACT# ALERT# EVENT#/NF

PARITY VREFCA

DDR4-260P-9-GP-U

M_B_A0[5] M_B_A1[5] M_B_A2[5] M_B_A3[5] M_B_A4[5] M_B_A5[5] M_B_A6[5] M_B_A7[5] M_B_A8[5] M_B_A9[5] M_B_A10[5] M_B_A11[5]

D D

C C

1D2V_S3

DDR4_DR AMRST#

12

ED1302

ED1302 Do Not Stuff

Do Not Stuff

DY

PCH_SMBDAT A[12,18,65,66,67,99]

R1312

1 2

DY

Do Not Stuff

M_B_A12[5] M_B_A13[5] M_B_A14[5] M_B_A15[5] M_B_A16[5]

M_B_BA0[5]

M_B_BA1[5]

M_B_BG0[5]

M_B_BG1[5]

M_B_CLK0[5]

M_B_CLK#0[5]

M_B_CLK1[5]

M_B_CLK#1[5]

M_B_CKE0[5] M_B_CKE1[5]

M_B_CS#0[5] M_B_CS#1[5]

M_B_DIMB_ODT0[5] M_B_DIMB_ODT1[5]

PCH_SMBCLK[12,18,65,66,67,99]

DDR4_DR AMRST#[ 5,12,13] M_B_ACT_N[5] M_B_ALERT_N[5]

M_B_PARITY[5]

M_VREF_CA_D IMMB

12

C1301

SCD1U16V2KX-3GP

Layout note: closed to Dimm

B B

1D2V_S3

RN1301

1 2 3

SRN1KJ-7-G P

4

M_VREF_CA_D IMMB

R1305

1 2

2R2F-GP

12

C1323

C1323 SCD022U16V2KX -3GP

SCD022U16V2KX -3GP

+V_VREF_PATH 2

12

R1309

R1309 24D9R2F-L-G P

24D9R2F-L-G P

1 OF 4

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

V_SM_VREF_CN TB [5]

3D3V_S0

R1311

R1303

20160615 DDR swap

󴴨󴴨󴴨󴴨sw󳠃󳠃󳠃󳠃󴧖󴧖󴧖󴧖

DY

R1302 Do Not Stuff

12

1 2

Do Not Stuff

R1306 10KR 2F-L1-GPR1306 10KR 2F-L1-GP

12

R1307 Do Not Stuff

12

DY

R1310 Do Not Stuff

12

1 2

Do Not Stuff

M_B_DQ1 [5] M_B_DQ5 [5] M_B_DQ7 [5] M_B_DQ3 [5] M_B_DQ0 [5] M_B_DQ4 [5] M_B_DQ6 [5] M_B_DQ2 [5]

M_B_DQ9 [5] M_B_DQ14 [5] M_B_DQ13 [5] M_B_DQ11 [5]

M_B_DQ8 [5] M_B_DQ12 [5] M_B_DQ10 [5] M_B_DQ15 [5] M_B_DQ16 [5] M_B_DQ17 [5] M_B_DQ18 [5] M_B_DQ19 [5] M_B_DQ20 [5] M_B_DQ21 [5] M_B_DQ22 [5] M_B_DQ23 [5] M_B_DQ24 [5] M_B_DQ25 [5] M_B_DQ26 [5] M_B_DQ27 [5] M_B_DQ28 [5] M_B_DQ29 [5] M_B_DQ30 [5] M_B_DQ31 [5] M_B_DQ32 [5] M_B_DQ33 [5] M_B_DQ34 [5] M_B_DQ35 [5] M_B_DQ36 [5] M_B_DQ37 [5] M_B_DQ38 [5] M_B_DQ39 [5] M_B_DQ40 [5] M_B_DQ41 [5] M_B_DQ42 [5] M_B_DQ43 [5] M_B_DQ44 [5] M_B_DQ45 [5] M_B_DQ46 [5] M_B_DQ47 [5] M_B_DQ48 [5] M_B_DQ49 [5] M_B_DQ54 [5] M_B_DQ50 [5] M_B_DQ52 [5] M_B_DQ53 [5] M_B_DQ51 [5] M_B_DQ55 [5] M_B_DQ61 [5] M_B_DQ56 [5] M_B_DQ59 [5] M_B_DQ63 [5] M_B_DQ57 [5] M_B_DQ58 [5] M_B_DQ60 [5] M_B_DQ62 [5]

20160615 DDR swap

SA0_CHB_DIM0

SA1_CHB_DIM0

SA2_CHB_DIM0

8 7 20 21 4 3 16 17 28 29 41 42 24 25 38 37 50 49 62 63 46 45 58 59 70 71 83 84 66 67 79 80 174 173 187 186 170 169 183 182 195 194 207 208 191 190 203 204 216 215 228 229 211 212 224 225 237 236 249 250 232 233 245 246

1D2V_S3

DM2B

DM8#/DBI#/NC

DDR4-260P-9-GP-U

12

C1303

Do Not Stuff

DY

12

C1315

Do Not Stuff

DY

111 112 117 118 123 124 129 130 135 136 141 142 147 148 153 154 159 160 163

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

DQS4_C

DQS4_T

DQS5_C

DQS5_T

DQS6_C

DQS6_T

DQS7_C

DQS7_T

DQS8_C

DQS8_T

DM0#/DBI0#

DM1#/DBI# DM2#/DBI2# DM3#/DBI3# DM4#/DBI4# DM5#/DBI5# DM6#/DBI6# DM7#/DBI7#

12

C1304

Do Not Stuff

DY

12

C1316

SC1U10V2KX-1GP

DM2C

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

DDR4-260P-9-GP-U

2 OF 4

12

C1305

12

C1317

SC10U6D3V3MX-GP

SC1U10V2KX-1GP

11 13 32 34 53 55 74 76 177 179 198 200 219 221 240 242 95 97

12 33 54 75 178 199 220 241 96

3 OF 4

VDDSPD

VPP VPP

VTT

NP1 NP2

M_B_DQS_DN0 M_B_DQS_DP0 M_B_DQS_DN1 M_B_DQS_DP1 M_B_DQS_DN2 M_B_DQS_DP2 M_B_DQS_DN3 M_B_DQS_DP3 M_B_DQS_DN4 M_B_DQS_DP4 M_B_DQS_DN5 M_B_DQS_DP5 M_B_DQS_DN6 M_B_DQS_DP6 M_B_DQS_DN7 M_B_DQS_DP7

12

C1306

Do Not Stuff

DY

12

C1318

Do Not Stuff

DY

255

257 259

258

261

262

NP1 NP2

20160615 DDR swap

20160706 RF need to reserve

12

C1307

C1308

SC10U6D3V3MX-GP

Do Not Stuff

DY

12

C1319

C1320

SC1U10V2KX-1GP

Do Not Stuff

DY

2D5V_S3

0D6V_S0

M_B_DQS_DN0 [5] M_B_DQS_DP0 [5] M_B_DQS_DN1 [5] M_B_DQS_DP1 [5] M_B_DQS_DN2 [5] M_B_DQS_DP2 [5] M_B_DQS_DN3 [5] M_B_DQS_DP3 [5] M_B_DQS_DN4 [5] M_B_DQS_DP4 [5] M_B_DQS_DN5 [5] M_B_DQS_DP5 [5] M_B_DQS_DN6 [5] M_B_DQS_DP6 [5] M_B_DQS_DN7 [5] M_B_DQS_DP7 [5]

1D2V_S3

12

C1309

SC10U6D3V3MX-GP

DY

12

C1321

SC1U10V2KX-1GP

DY

FC1301

12

C1310

Do Not Stuff

12

C1322

Do Not Stuff

3D3V_S0

12

C1328

C1329

Do Not Stuff

DY

12

C1325

C1324

Do Not Stuff

SC10U6D3V3MX-GP

DY

12

C1326

SC1U10V2KX-1GP

M_B_DQS_DN0 M_B_DQS_DN1 M_B_DQS_DN2 M_B_DQS_DN3 M_B_DQS_DN4 M_B_DQS_DN5 M_B_DQS_DN6 M_B_DQS_DN7

M_B_DQS_DP0 M_B_DQS_DP1 M_B_DQS_DP2 M_B_DQS_DP3 M_B_DQS_DP4 M_B_DQS_DP5 M_B_DQS_DP6 M_B_DQS_DP7

12

C1327

10 14 15 18 19 22 23 26 27 30 31 35 36 39 40 43 44 47 48 51 52 56 57 60 61 64 65 68 69 72 73 77 78 81 82 85 86 89 90 93 94 98

SC1U10V2KX-1GP

DM2D

VSS1VSS

2

VSS

5

VSS

6

VSS

9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DDR4-260P-9-GP-U

2D5V_S30D6V_S0 0D6V_S0 0D6V_S0

4 OF 4

99 102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

12

C1311

Do Not Stuff

DY

M_B_DQS_DN[7: 0] [5]

M_B_DQS_DP[7:0] [5]

C1330

12

Do Not Stuff

DY

C1331

12

C1312

C1313

C1314

DY

Do Not Stuff

SC1U10V2KX-1GP

Do Not Stuff

A A

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

DDR3-SODIMM2

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Monday, Decemb er 26, 2016

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Taos KBL-U

1

13 105

X00

Vinaﬁx.com

5

D D

4

3

2

1

C C

(Blanking)

B B

2.DIS

Wistron Corporation

A A

Title

(Reserved)_SODIMM _SODIMM4

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

14 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

Main Func = PCH

4

3

2

1

CPU1I

SKYLAKE_ULT

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

D D

C C

C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKYLAKE-U-GP

SKYLAKE_ULT

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F12/EMMC_CMD

9 OF 20

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F22/EMMC_CLK

EMMC_RCOMP

C37 D37 C32 D32 C29

DC resistance < 0.5ohm.

D29 B26 A26

CSI2_COMP

E13

GPP_D4/FLASHTRIG

B7

20161024 0ohm to short pad

AP2 AP1 AP3

GPP_F: VCCPGPPF = 1.8V Only

AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

EMMC_RCOMP

AT1

20160815 stuff

WIFI_RF_EN

R1501

100R2F-L1-GP-U

1 2 1 2

1 2

100R2F-L1-GP-U

R1503 Do Not StuffR1503 Do Not Stuff

20160616 DY R1710 stuff R1503

R1502

200R2F-L-GP

R1504 10KR2J-3-GPR1504 10KR2J-3-GP

12

WIFI_RF_EN [17,61]

[#545659 Rev0.7]

3D3V_S5

B B

A A

5

4

3

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(CS-2/EMMC)

Taos KBL-U

15 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

Main Func = PCH

5

4

3

2

1

#543016: 220 nF nominal capacitors are recommended for Gen 3. 100 nF nominal capacitors are recommended for Gen 2.

PEG_RX_CPU_N0[76] PEG_RX_CPU_P0[76] PEG_TX_GPU_N0[76] PEG_TX_GPU_P0[76]

PEG_RX_CPU_N1[76]

D D

Layout Note:

C C

B B

PEG_RX_CPU_P1[76] PEG_TX_GPU_N1[76] PEG_TX_GPU_P1[76]

PEG_RX_CPU_N2[76]

GPU

PEG_RX_CPU_P2[76] PEG_TX_GPU_N2[76] PEG_TX_GPU_P2[76]

PEG_RX_CPU_N3[76] PEG_RX_CPU_P3[76] PEG_TX_GPU_N3[76] PEG_TX_GPU_P3[76]

PCIE_RX_CPU_N5[31] PCIE_RX_CPU_P5[31] PCIE_TX_CON_N5[31]

LAN

PCIE_TX_CON_P5[31] PCIE_RX_CPU_N6[61]

PCIE_RX_CPU_P6[61]

WLAN

PCIE_TX_CON_N6[61] PCIE_TX_CON_P6[61]

SATA_RX_CPU_N0[60] SATA_RX_CPU_P0[60]

HDD1

SATA_TX_CPU_N0[60] SATA_TX_CPU_P0[60]

SATA_RN1/PERN6_L0[62] SATA_RP1/PERP6_L0[62]

WWAN

SATA_TN1/PETN6_L0[62] SATA_TP1/PETP6_L0[62]

1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) Note: Must maintain low DC resistance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent high speed I/O.

R1604

XDP_PRDY#[99]

XDP_PREQ#[99]

20160622 merge R1607 R1839 RN2012 to RN2001

PCIE Table

Port

Device

Share BUS

USB3.0_3

N/A

1

2

3

4

5(L0~L3)

6(L3)

6(L2)

6(L0~L1)

N/A

WLAN

LAN

GPU

HDD

N/A

USB3.0_4

SATA0

#545659 (SKL_PCH_U_Y_EDS Rev0.7)

C1606

C1606 C1605

C1605

C1608

C1608 C1607

C1607

C1610

C1610 C1609

C1609

C1612

C1612 C1611

C1611

C1603

C1603 C1604

C1604

C1601

C1601 C1602

C1602

1 2

100R2F-L1-GP-U

SCD22U10V2KX-1GP

1 2

OPS

1 2

OPS

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1 2

OPS

1 2

OPS

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1 2

OPS

1 2

OPS

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1 2

OPS

1 2

OPS

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2 1 2

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2 1 2

SCD1U16V2KX-3GP

PIRQA#[20]

USB 2.0 Table

PEG_TX_CPU_N0 PEG_TX_CPU_P0

PEG_TX_CPU_N1 PEG_TX_CPU_P1

PEG_TX_CPU_N2 PEG_TX_CPU_P2

PEG_TX_CPU_N3 PEG_TX_CPU_P3

PCIE_TX_CPU_N5 PCIE_TX_CPU_P5

PCIE_TX_CPU_N6 PCIE_TX_CPU_P6

PCIE_RCOMPN PCIE_RCOMPP

PIRQA#

Pair

Device

USB3.0 port1

0

USB3.0 Port2

1

USB2.0 Port3 (IOBD)

2

Fringer print

3

CAMERA

4

Card Reader

5

Touch Panel

6

WLAN

7

CPU1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U-GP

SKYLAKE_ULT

SSIC / USB3

USB3_2_RXN/SSIC_RXN

USB3_2_RXP/SSIC_RXP USB3_2_TXN/SSIC_TXN

USB3_2_TXP/SSIC_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

8 OF 20

(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.

H8

USB3_1_RXN

G8

USB3_1_RXP

C13

USB3_1_TXN

D13

USB3_1_TXP

J6 H6 B13 A13

J10

USB3_3_RXN

H10

USB3_3_RXP

B15

USB3_3_TXN

A15

USB3_3_TXP

E10

USB3_4_RXN

F10

USB3_4_RXP

C15

USB3_4_TXN

D15

USB3_4_TXP

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

AH7

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_ID USB2_VBUSSENSE

DC resistance < 0.5ohm.

AH8

USBCOMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4 A9

C9 D9

USB_OC3#

B9 J1

J2

SIO_EXT_SCI#_R

J3

GPP_E0/SATAXPCIE0/SATAGP0

H2

NGFF_PCIE#_SATA

H3

GPP_E2/SATAXPCIE2/SATAGP2

G4 H1

20161108 change RN1601 to short pad

R1601 Do Not StuffR1601 Do Not Stuff

1 2

R1602 Do Not StuffR1602 Do Not Stuff

1 2

(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND using 8.2 KΩ to 10 KΩ on the motherboard. Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.

USB30_RX_CPU_N1 [36] USB30_RX_CPU_P1 [36] USB30_TX_CPU_N1 [36] USB30_TX_CPU_P1 [36]

USB30_RX_CPU_N2 [62] USB30_RX_CPU_P2 [62] USB30_TX_CPU_N2 [62] USB30_TX_CPU_P2 [62]

USB30_RX_CPU_N3 [36] USB30_RX_CPU_P3 [36] USB30_TX_CPU_N3 [36] USB30_TX_CPU_P3 [36]

USB_CPU_PN0 [34] USB_CPU_PP0 [34]

USB_CPU_PN1 [36] USB_CPU_PP1 [36]

USB_CPU_PN2 [37] USB_CPU_PP2 [37]

USB_CPU_PN3 [92] USB_CPU_PP3 [92]

USB_CPU_PN4 [55] USB_CPU_PP4 [55]

USB_CPU_PN5 [33] USB_CPU_PP5 [33]

USB_CPU_PN6 [61] USB_CPU_PP6 [61]

USB_CPU_PN7 [55] USB_CPU_PP7 [55]

USB_WWAN_PN8 [62] USB_WWAN_PP8 [62]

R1603 113R2F-GPR1603 113R2F-GP

1 2

USB_OC0# [34] USB_OC1# [35] USB_OC2# [35]

HDD_DEVSLP [60] NGFF_DEVSLP1 [62] SIO_EXT_SCI#_R [24]

1 1

USB1 (USB3.0 Port1)

WWAN

USB2 (USB3.0 Port2)

USB1 (USB3.0 port1)

USB2 (USB3.0 Port2)

USB3 (IO BD/USB2.0 Port3)

Finger Print (USB2.0 Port4)

CAMERA (USB2.0 Port5)

Card Reader (USB2.0 Port6)

WLAN (USB2.0 Port7)

Touch Panel (USB2.0 Port8)

WWAN (USB2.0 Port9)

(#543016) When used as DEVSLP, no external pull-up or pull-down termination required from SATA Host DEVSLP.

TP1601 Do Not StuffTP1601 Do Not Stuff

20160616 due to Taos SSD interface only be SATA & KBC

TP1603 Do Not StuffTP1603 Do Not Stuff

SATA_LED#_R [64]

USB_OC2# USB_OC0# USB_OC3# USB_OC1#

RN1602

8 7 6

SRN10KJ-6-GP

3D3V_S5_PCH

1 2 3 45

update 0509

20160616 add

NGFF_PCIE#_SATA

20160621 add Dummy name!

SATA_LED#_R

SIO_EXT_SCI#_R

HWHDLED

R1609

R1608

R1610

Do Not Stuff

10KR2J-3-GP

12

10KR2J-3-GP

12

WWAN

3D3V_S5

3D3V_S0

A A

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(PCIE/SATA/USB)

Taos KBL-U

1

16 105Monday, December 26, 2016

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

20160630 SWAP by layout 20160617 merge RN1701/R1723/R1725 to one 8P4R

3D3V_S5

D D

20160622 R1703/R1733 merge placement is the same( two for 10K ohm is ok)

C C

RN1701

1

8

2

7

3

6

45

SRN10KJ-6-G P

RTC_AUX_S5

R1730

1 2

1MR2J-1-GP

3D3V_S5

20160617 DY

R1714

1 2

DY

Do Not Stuff

Do Not Stuff RN1703

RN1703

4

SRN10KJ-5-G P

R1732 10KR2F-2-GPR 1732 10KR2F-2-GP

1 2

R1717 D o Not Stuff

12

DY

+VCCMPHYGTAON_1P0

SKL: 1.0V

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

1D0V_S5 +VCCMPHYGTA ON_1P0_LS_SIP

EC1716

Do Not Stuff

12

DY

GPD11/LANPHYPC PCH_BATLOW # PCH_WA KE# AC_PRESENT

GPD11 pull high by Intel PDG1.3 request

#544669 (CRB): 330k.

SM_INTRUDER #

0422 R1730 change to 1M

#544669 Rev0.52 CRB:

PCIE_WLAN_W AKE#

23 1

PCH_DPW ROK PM_RSMRST#

PM_PCH_PW ROK

SYS_PWROK

20161024 0ohm to short pad

R1724

1 2

Do Not Stuff

R1735

1 2

Do Not Stuff

Follow Iris SKL 2015/11/30 modify

No PL resistor on THERMTRIP#.

H_CPUPW RGD

EC_WAKE#[24]

DY

PCIE_LAN_WA KE#[31]

PCIE_WLAN_W AKE#[61,62]

C1704

12

SC10U6D3V3MX- GP

20161024 0ohm to short pad

Layout note: 3 PAD SHARING

R405

R405 Do Not Stuff

Do Not Stuff

1 2

Do Not Stuff

12

DY

EC1701

Do Not Stuff

12

R1736

For EMI Reserved

EC1710

Do Not Stuff

R1711

1 2

Do Not Stuff

GPD2/LAN_W AKE#

H_CPUPWRGD

EC1713

DY

1 2

ME_SUS_PW R_ACK_R[20]

D1702

2

1

BAW56-9-G P

75.00056.07D

PM_PCH_PWROK

DY

Do Not Stuff

1 2

+VCCPDSW _3P33D3V_S5

+V3.3A_SIP

12

R1701

R1701 10KR2J-3-GP

10KR2J-3-GP

XDP_DBRESE T#[99]

SYS_PWROK[24] RESET_OUT #[24,26,40]

H_VCCST_PW RGD_R

R1706 Do Not StuffR1706 Do Not Stuff R1704 Do Not Stuff

R1704 Do Not Stuff

R1705 Do Not StuffR1705 Do Not Stuff

+VCCPDSW _3P3

WIFI_RF_EN[15,17,61]

(PDG#543016) WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.

PCIE_WAKE#

3

R1707 10KR2J-3-GPR1707 10KR2J-3-GP

R1709 Do Not Stuff

TP1709

Do Not Stuff

1 2 1 2

NON DS3

1 2 1 2 1 2

DY

20161012remove C1702,C1703,U1701 ,U1702 to increase the space

PM_RSMRST#[99]

1 2

1

ALL_SYS_PWRG D[24,40]

60D4R2F-GP

60D4R2F-GP R1734

R1734

PLT_RST#[24,31,55,61,62,68,76,91]

PCH_PLTRST # XDP_DBRESE T#

H_CPUPW RGD

H_VCCST_PW RGD SYS_PWROK

PM_PCH_PW ROK PCH_DPW ROKPM_RSMRST#

ME_SUS_PW R_ACK_R SUSACK#_R

PCH_WA KE#PCIE_WAKE# GPD2/LAN_W AKE# GPD11/LANPHYPC

Do Not Stuff

12

R1715

DY

CPU1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD#AT15

SKYLAKE-U-GP

1 2

R1716

R1716 100KR2F-L1-GP

100KR2F-L1-GP

12

DY

EC1709

Do Not Stuff

R1713

1 2

Do Not Stuff

C1701

C1701 Do Not Stuff

Do Not Stuff

SYSTEM POWER MANAGEMENT

PCH_PLTRST #

SKYLAKE_ULT

12

R1719

R1719 47KR2F-GP

47KR2F-GP

AC_PRESENT

EC1707

Do Not Stuff

GPP_B11/EXT_PWR_GATE#

+VCCSTG

12

R1722

R1722 Do Not Stuff

Do Not Stuff

DY

H_VCCST_PW RGD_R

EC1708

Do Not Stuff

12

DY

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B2/VRALERT#

12

DY

11 OF 20

SLP_SUS#

SLP_LAN#

INTRUDER#

DY

EC1715

Do Not Stuff

EC_SLP_S0IX#

AT11 AP15 BA16

SIO_SLP_S5#

AY16 AN15

SLP_LAN#

AW15

AUX_EN_W OWL_R

BB17

SIO_SLP_A#

AN16 BA15

AC_PRESENT

AY15

PCH_BATLOW #

AU13

Do Not Stuff

20160630 remove TP1707 for layout space

AU11

SM_INTRUDER #

AP16

EXT_PWR _GATE#

AM10

GPP_B2/VRALER T#

AM11

3D3V_AUX_S5

12

[#543016 Rev0.7] EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k pull-down that is active during the early portion of the power up sequence

EC_SLP_S0IX# [24,40,91] SIO_SLP_S3# [24,27,40,51]

SIO_SLP_S4# [24,40,54]

TP1703

1

Do Not Stuff

SIO_SLP_SUS# [24,41,53,54]

TP1704

1

Do Not Stuff

Do Not Stuff TP1706

TP1706

1

Do Not Stuff

R1710

12

20160616 DY R1710 stuff R1503

DY

1

TP1708 Do N ot StuffTP1708 Do Not Stuff

R1737

PM_RSMRST#_M

1 2

NON DS3

Do Not Stuff

R1721

1 2

DY

Do Not Stuff

SIO_PWRBTN # [24,9 9]

WIFI_RF_EN [15,17,61]

Q1702

2345

NON DS3

1

6

Do Not Stuff

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

AUX_EN_W OWL [61,96]

20160617 DY

EXT_PWR _GATE#

BATLOW#: Pull-up required even if not implemented.

D1703

D1703 RB751V-40H-G P

RB751V-40H-G P

KA

PWR_CH G_ACOK [24,44]

83.R2004.G8F

AC_PRESENT

R1720

PM_RSMRST#_R PM_RSMRST#

1 2

NON DS3

Do Not Stuff

R1731

DY

Do Not Stuff

+V3.3A_SIP

12

B B

NON DS3

R1708

SUSACK#_RME_SUS_PW R_ACK_R

1 2

Do Not Stuff

R1703 Do N ot StuffR1703 Do Not S tuff

SUSACK#[24]

ME_SUS_PW R_ACK[24]

A A

1 2

R1712 Do N ot StuffR1712 Do Not S tuff

1 2

20161108 change RN1702 to short pad

3D3V_AUX_S5

1 2

R1726

R1726 10KR2J-3-GP

10KR2J-3-GP

R1727

Do Not Stuff

1 2

NON DS3

6

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

5

Q1701

2N7002KDW -GP

DS3 BOM Option

PCH_DPW ROK[24]

SUSACK#_R ME_SUS_PW R_ACK_R

20160622 R1703/R1733 merge placement is the same( two for 10K ohm is ok)

1KR2J-1-GP

1KR2J-1-GP R1702

R1702

PM_RSMRST#

1 2

3V_5V_POK_C3V_5V_POK#

R1728

2345 1

R1728

1 2

NON DS3

Do Not Stuff

R1729

1 2

Do Not Stuff

20161024 0ohm to short pad

EC1714

SIO_SLP_SUS#

DY

Do Not Stuff

Layout Note:

close to CPU1

R1718 D o Not Stuff

1 2

DY

12

Change dummy property from DS3 to DY

Change location to net PCH_DPWROK

3V_5V_POK [17,40,45,53,5 4]

EC1712

EC1711

EC1712

12

DY

Do Not Stuff

12

DY

Do Not Stuff

4

3V_5V_POK [17,40,45,53,5 4]

PCH_RSMRS T# [24]

EC1706

XDP_DBRESE T#

SYS_PWROK PLT_RST# RESET_OUT #

3V_5V_POK

12

DY

EC1702

Do Not Stuff

12

DY

EC1703

Do Not Stuff

EC1705

EC1704

Do Not Stuff

VCCST_PWRGD / HWM201:

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST

3

2

Title

CPU_(POWER MANAGEMENT)

Size Document Num ber Rev

A2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Taos KBL-U

1

X00

17 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

Main Func = PCH

3D3V_S5_PCH

D D

RN1802

1 2 3

SRN1KJ-7-G P

3D3V_S0

R1838

1 2

10KR2J-3-GP

20160622 merge R1607 R1839 RN2012 to RN2001

C C

RCIN#: Frequency to Avoid: 33 MHz

20160630 SWAP by layout 20160629 CLKREQ_PCIE#3/ CLKREQ_PCIE#4 don't be used to RN1804 and DY

20160614 Merge

3D3V_S0

RN1803

1 2 3

B B

A A

4 5

SRN10KJ-6-G P

RN1804

4

Do Not Stuff

WWAN

5

PCH strap pin:

Sampled at rising edge of RSMRST#

eSPI or LPC

SML0ALERT# / GPP_C5

This signal has a weak internal pull-down.

SPI_HOLD_CPU

4

SPI_WP_CPU

SPI_SI_ROM[24,25,91] SPI_CLK_ROM[24,25,91]

SPI_SO_ROM[24,25,91]

SIO_RCIN# MEM_SMBDATA

SPI_WP_ROM[25]

SPI_CS_ROM_N0[24,25] SPI_CS_ROM_N1[25]

0204 modfiy HDD_PWR_EN to TP

CLKREQ_PEG#0

8

CLKREQ_PCIE#2

7

CLKREQ_PCIE#5

6

CLKREQ_PCIE#1

CLKREQ_PCIE#3

23

CLKREQ_PCIE#4

1

DY

PEG_CLK_CPU #[76]

GPU WLAN

LAN

PEG_CLK_CPU[76]

CLKREQ_PEG#0[79]

PEG_CLK1_CPU #[61] PEG_CLK1_CPU[61]

CLKREQ_PCIE#1[61]

PEG_CLK2_CPU #[31] PEG_CLK2_CPU[31]

CLKREQ_PCIE#2[31]

CLK_PCIE_N5_W WAN#[62 ] CLK_PCIE_P5_W WAN[62]

CLKREQ_PCIE#5[62]

5

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

SPI0_MOSI_XDP[99]

XDP_SPI0_IO2[99]

1 2 3 4 5

SRN10J-1-G P

SPI_HOLD_ROM[25]

SPI_CS2#_R[91]

HDD_FALL_INT[67]

CL_CLK[61] CL_DATA[61]

CL_RST#[61]

SIO_RCIN#[24]

SERIRQ[20,24]

PLACE WITHIN 1.1 INCH OF PCH

R1826

1 2

XDP

R1827

1 2

XDP

RN1805

8 7 6

20161024 0ohm to short pad

12

EC1805

DY

CLKREQ_PCIE#5

SPI_SI_CPU SPI_CLK_CPU SPI_SO_CPU SPI_WP_CPU

1 2 1 2 1 2

DY

1 2

Do Not Stuff

R181110R2F -L-GP R181110R2F- L-GP R1812Do N ot Stuff R1812Do Not Stuff R1828Do N ot Stuff

R1828Do N ot Stuff R1816Do N ot Stuff R1816Do Not Stuff

CLKREQ_PCIE#1

CLKREQ_PCIE#3

CLKREQ_PCIE#4

4

PCH Prim

3D3V_S5_PCH

12

R1822

DY

Do Not Stuff

GPP_C5/SML0ALER T#

(#543016)Optional, can be left as OPEN/No-Connect.

SPI_SI_CPU

SPI_WP_CPU

SPI_CLK_CPU SPI_SO_CPU SPI_SI_CPU

SPI_WP_CPU SPI_HOLD_CPU SPI_CS_CPU_N0 SPI_CS_CPU_N1 PCH_SPI_CS2#

CPU_D1_TP

TP1801Do Not Stuff TP18 01D o Not Stuff

1

CPU_D3_TP

TP1807Do Not Stuff TP18 07D o Not Stuff

1

CPU_D4_TP

TP1804Do Not Stuff TP18 04D o Not Stuff

1

CPU_D5_TP

TP1805Do Not Stuff TP18 05D o Not Stuff

1

CPU_D6_TP

TP1806Do Not Stuff TP18 06D o Not Stuff

1

4

DY

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

AW13 AY11

CPU1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U-GP

12

R1823

R1823 Do Not Stuff

Do Not Stuff

CPU1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

SKYLAKE-U-GP

Strap

PCH strap pin:

BOOT HALT

SPI0_MOSI

This signal has a weak internal pull-up.

CLOCK SIGNALS

SKYLAKE_ULT

0 = ENABLED 1 = DISABLED WEAK INTERNAL PU

SKYLAKE_ULT

LPC

20161103 change 7pF to 6.8pF

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_OUT

XCLK_BIASREF

3

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

Strap

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

Strap

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

20160819 vendor suggest 7P

10 OF 20

F43 E43

SUSCLK_R

BA17

XTAL24_IN

E37

XTAL24_IN

SRTCRST#

RTCRST#

RTCX1 RTCX2

E35 E42 AM18

AM20 AN18

AM16

XTAL24_OUT XCLK_BIASREF RTC_X1

RTC_X2 SRTC_RST #

RTC_RST#

3

PCH Prim

3D3V_S5_PCH

12

R1824

DY

Do Not Stuff

SPI_SI_CPU

LPC_LAD[3..0][24,68,9 1]

5 OF 20

MEM_SMBCLK

R7 R8

GPP_C2/SMBALER T#

R10

SML0_SMBCLK

R9

SML0_SMBDATA

W2

GPP_C5/SML0ALER T#

W1 W3

V3

GPP_B23/SML1ALERT #

AM7

LPC_LAD0_R

AY13

LPC_LAD1_R

BA13

LPC_LAD2_R

BB13

LPC_LAD3_R

AY12

LPC_LFRAME#_R

BA12

SUS_STAT#/LPC PD#

BA11

PCI_CLK_LPC0

AW9

PCI_CLK_LPC1

AY9

CLKRUN#_R

AW11

R1815 10M R2J-L-GPR1815 10MR2J-L- GP

20160617 change 82.30001.C01 to 082.30003.0201 for cost

12

C1804

SC6D8P50V2DN-GP

R1803

1 2

2K7R2F-GP

Intel recommend: 2.71k ohm 5%

RTCRST_O N[24]

12

R1825

DY

Do Not Stuff

20161212 RN1806 change 0 ohm to short pad

LPC_LAD[3..0]

LPC_LAD0 LPC_LAD2 LPC_LAD1 LPC_LAD3

SML1_SMBCLK [24,26, 79] SML1_SMBDATA [24,26, 79]

R1801 Do N ot StuffR1801 Do Not S tuff

1 2

R1819 Do N ot StuffR1819 Do Not S tuff

1 2

X1802

1 2

XTAL-32D768KH Z-89-GP

082.30003.0201

+V1.00A_SIP

Do Not Stuff

EC1808

DY

12

+V1.05S_AXCK_LCPLL

12

10KR2J-3-GP

12

PCH strap pin:

No Reboot

SMBALERT# / GPP_C2

The signal has a weak internal pull-down.

20161108 change RN1806 to short pad

RN1806

20161109 change short pad to RN1806

RN

1

8

2

7

3456

Do Not Stuff

LPC_LFRAME# [24,68,91]

CLKRUN# [24]

RTC_X1 RTC_X2

C1803

SC6D8P50V2DN-GP

PCIE_CLK_XDP_N [99]

PCIE_CLK_XDP_P [99]

R1813 D o Not Stuff

1 2

R1817 D o Not Stuff

1 2

G

R1837

S

20160617 follow Keystone by Keystone & Taos DTC planning

DY

DY DY

DY

Q1802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

(#514849)

Layout: Place at the open door area.

2

Sampled at rising edge of PCH_PWROK

0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

LPC_LAD0_R LPC_LAD2_R LPC_LAD1_R LPC_LAD3_R

SUS_STAT#/LPC PD#

CLKRUN#_R

20160617 follow Vegas by Keystone & Taos DTC planning file

SUS_CLK [24] SUS_CLK_W LAN_WW AN [61,62]

12

C1805

SC1U10V2KX-1GP

20140820 DAIVD

3D3V_S5_PCH

R1814

12

DY

Do Not Stuff

3D3V_S0

R1818

8K2R2F-1-GP

1 2

20160624 modify dummy name

PCI_CLK_LPC0 PCI_CLK_LPC1

XTAL24_IN XTAL24_IN_R

XTAL24_OUT

RTC_AUX_S5

23

21

G1801

Do Not Stuff

2

MEM_SMBDATA

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

MEM_SMBCLK

R1804 Do Not Stuff

1 2

CPM&LPC

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

12

DY

R1810

1 2

Do Not Stuff

R1802

R1802 1MR2J-1-GP

1MR2J-1-GP

23

12

DY

12

1

RN1801

RN1801 SRN20KJ-1-G P

SRN20KJ-1-G P

4

12

C1806

C1806 SC1U10V2KX-1G P

SC1U10V2KX-1G P

EC1801

Do Not StuffDYEC1801

Do Not Stuff

4 1

Do Not Stuff

EC1806

DY

SUSCLK_R

SRTC_RST # RTC_RST#

3D3V_S0

2N7002KDW -GP

6

Q1801

EC1802

Do Not StuffDYEC1802

Do Not Stuff

12

C1801

SC15P50V2JN-2- GP

X1801

X1801 XTAL-24MHZ- 81-GP

XTAL-24MHZ- 81-GP

82.30004.841

C1802

SC15P50V2JN-2- GP

Do Not Stuff

12

EC1807

DY

1

3D3V_S5_PCH

RN1807

SML0_SMBDATA SML1_SMBCLK SML1_SMBDATA SML0_SMBCLK

20160712 internal pull high , R1820 R2821 DY

GPP_B23/SML1ALERT #

GPP_C2/SMBALER T#

MEM_SMBCLK MEM_SMBDATA

1 2345

PCI_CLK_LPC1_B [91] CLK_PCI_LPC_MEC [24]

12

DY

2.DIS

Title

Size Document Num ber Rev

Date: Sheet of

RN1807

1

8

2

7

3

6

45

SRN2K2J-4-G P

R1820

Do Not Stuff

12

DY

R1821

Do Not Stuff

1 2

DY

SRN2K2J-1-G P

23 1

4

RN1811

RN1810

23

3D3V_S0

1

4

SRN10KJ-5-G P

PCH_SMBDAT A [12,13,65,66,67,99]

PCH_SMBCLK [12,13,65,66,67,99]

EC1803

1 2

Do Not Stuff

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

CPU_(LPC/SPI/SMBUS/CL/CLK)

A2

Taos KBL-U

1

18 105Monday, Decemb er 26, 2016

X00

Vinaﬁx.com

5

Main Func = PCH

PCH strap pin:

4

3

2

1

D D

C C

B B

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

Low = Default High = Enable

*

The internal pull-down is disabled after PLTRST# deasserts

Do Not Stuff

DGPU_PWROK[24,79,85]

PCH strap pin:

NO REBOOT

Low = Enable (Default)

HDA_SPKR

The internal pull-down is disabled after

*

High = Disable

CPU1G

AUDIO

HDA_SYNC HDA_BITCLK HDA_SDOUT

HDA_SDIN0[27]

TP1903

SPKR[27]

HDA_RST#

1

SPKR

FC1901Do Not StuffDYFC1901Do Not Stuff

DY

DGPU_PWROK

3D3V_S0

R2006 Do Not Stuff

R1904 Do Not Stuff

EC1901 Do Not Stuff

12

1 2

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

SKYLAKE-U-GP

1 2

DY

UMA

1 2

DY

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SPKR

DGPU_PWROK

HDA_CODEC_BITCLK

SKYLAKE_ULT

SDIO/SDXC

GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

HDA_CODEC_SYNC[27]

7 OF 20

GPP_G0/SD_CMD

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

CPU_A16_TP SD_RCOMP

200R2F-L-GP

1 2

R1901

1 2

R1908

Do Not Stuff

KB_LED_BL_DET [65]

TP1902

1

Do Not Stuff

HDA_SYNC

PLTRST# deasserts

RN1901

EC1903 Do Not Stuff

DY

12

DGPU_PWROK

RN1901

HDA_CODEC_BITCLK[27] HDA_CODEC_SDOUT[27]

ME_FWP_CPU[98]

2.DIS

2 3 1

SRN33J-5-GP-U

R1909 1KR2J-1-GPR1909 1KR2J-1-GP

1 2

4

HDA_BITCLK HDA_SDOUT

Wistron Corporation

A A

Title

CPU_(AUDIO/SDIO/SDXC)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

CPU_(AUDIO/SDIO/SDXC)

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

19 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

Main Func = PCH

EC2002

12

DY

Do Not Stuff

20161017 stuff RN2009

RN2009

D D

3D3V_S0

C C

3D3V_S5_PCH

RN2009

1

OPS

2 3

SRN10KJ-5-GP

20160712 stuff

RN2001

8 7 6

SRN10KJ-6-GP

R2002 Do Not Stuff

1 2

DY

RN2002

1 2 3

SRN10KJ-5-GP

R2050 Do Not Stuff

1 2

DY

R2051 10KR2J-3-GPR2051 10KR2J-3-GP

1 2

R2052 10KR2J-3-GPR2052 10KR2J-3-GP

1 2

20160725 add

R2039 10KR2J-3-GPR2039 10KR2J-3-GP

1 2 1

2 3

RN2013

SRN10KJ-5-GP

PCH strap pin:

No Reboot

GSPI0_MOSI / GPP_B18

DGPU_HOLD_RST# [76]

DGPU_HOLD_RST#

4

DGPU_PWR_EN

R2048Do Not Stuff

LPSS_UART2_RXD

12

UART

UART UART

UART

4

LPSS_UART2_TXD

R2049Do Not Stuff

12

R2046Do Not Stuff

LPSS_UART2_CTS#

12

20160622 merge R1607 R1839 RN2012 to RN2001

20160622 Merge R2044/R2047 to RN2002

1 2 3 45

KB_DET#

DBC_PANEL_EN PIRQA# SERIRQ

BLUETOOTH_EN

HDD_DET# LCD_MIC_CBL_DET#

SD_READ_MODE# IR_CAMERA_DET# LOM_CABLE_DETECT#

RTC_DET# SIO_EXT_WAKE#

PIRQA# [16] SERIRQ [18,24]

Sampled at rising edge of PCH_PWROK

0 = Disable “No Reboot” mode. 1 = Enable “No Reboot” mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

PCH strap pin:

No Reboot

GSPI1_MOSI / GPP_B22

The signal has a weak internal pull-down.

SD_READ_MODE#[66]

20160526 add 1500PF for EMI

ME_SUS_PWR_ACK_R [17]

Sampled at rising edge of PCH_PWROK

This field determines the destination of accesses to the BIOS memory range. Also controllable using Boot BIOS Destination bit (Chipset Configuration Registers: Offset 3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. Bit 10 Boot BIOS Destination 0 SPI 1 LPC

PCH Prim

3D3V_S5_PCH

The signal has a weak internal pull-down.

Do Not Stuff

20160712 stuff

56

DB2

1 2

UART

3

Do Not Stuff

4

B B

For debug USB/UART:

5V_S5

LPSS_UART2_TXD LPSS_UART2_RXD

LPSS_UART2_CTS#

1

TP2009

TP2009 Do Not Stuff

Do Not Stuff

DBC_PANEL_EN[55]

LOM_CABLE_DETECT#[31]

BLUETOOTH_EN[61]

12

EC2001

EC2001 SC1500P50V2KX-2GP

SC1500P50V2KX-2GP

PTP

12

R2007

DY

Do Not Stuff

GPP_B18/GSPI0_MOSI

12

R2019

DY

Do Not Stuff

4

CPU1F

AN8

GPP_B15/GSPI0_CS#

AP7

VRAM_ID1

GPP_B18/GSPI0_MOSI

LCD_MIC_CBL_DET#[55]

SIO_EXT_WAKE#[24]

I2C0_SDA_TCH_PAD[65] I2C0_SCL_TCH_PAD[65]

HDD_DET#[60]

BOARD_ID2

LPSS_UART2_RXD LPSS_UART2_TXD

LPSS_UART2_CTS#

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U-GP

BOARD_ID2

3

(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up to the same voltage rail as the device/end point.

LPSS ISH

SKYLAKE_ULT

Strap

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SX_EXIT_HOLDOFF#/GPP_A12/BM_BUSY#/ISH_GP6

Do Not Stuff

PROJECT_ID2

Do Not Stuff

R2017

R2018

3D3V_S0

OPS

UMA

12

SKL

12

KBL

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

R2008

R2008 Do Not Stuff

Do Not Stuff

BIOS strap pin:

BIOS VRAM Size Strap pin

KBL

SKL

BIOS strap pin:

BIOS UMA/DIS Strap pin

UMA

DIS

6 OF 20

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D15/ISH_UART0_RTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A19

PROJECT_ID2

0

1

GPP_C11

BOARD_ID2

0

1

2

USB_UART_SEL_D9

P2

DGPU_HOLD_RST#

P3 P4

RTC_DET#

P1

I2C0_SDA

M4

I2C0_SCL

N3

I2C1_SDA

N1

I2C1_SCL

N2

1.8V Only

AD11 AD12

U1

UART0_TXD

U2

UART0_RTS#

U3

UART0_CTS#

U4

UART1_RXD

AC1 AC2

UART1_RTS#

AC3

UART1_CTS#

AB4 AY8

PROJECT_ID2

BA8 BB7 BA7 AY7 AW7 AP13

(PDG#543016) If the UART/GPIO functionality is also not used, the signals can be left as no-connect.

TP2006 Do Not StuffTP2006 Do Not Stuff

1

TP2012 Do Not StuffTP2012 Do Not Stuff

1

TP2013 Do Not StuffTP2013 Do Not Stuff

1

TP2014 Do Not StuffTP2014 Do Not Stuff

1

TP2015 Do Not StuffTP2015 Do Not Stuff

FFS_INT2 [67]

1

TP2016 Do Not StuffTP2016 Do Not Stuff

1

TP2017 Do Not StuffTP2017 Do Not Stuff

KB_DET# [65]

PANEL_SIZE_ID [55]

IR_CAMERA_DET# [55]

I2C1_SDA I2C0_SDA

I2C0_SCL I2C1_SCL

RTC_DET# [25]

DGPU_PWR_EN [85,86]

Do Not Stuff

Do Not Stuff RN2007

RN2007

1

4

2 3

DY

RN2008

1

4

2 3

DY

Do Not Stuff

1

3D3V_S0

Intel has removed EHCI controller from BDW and proposed to use UART interface for Win7 debug.

A A

5

4

VRAM_ID1

VRAM_2G

VRAM_4G

3D3V_S0

12

3

R2023

R2023 Do Not Stuff

Do Not Stuff

R2024

Do Not Stuff

BIOS strap pin:

BIOS VRAM Size Strap pin

4G

2G

GPP_B17

VRAM_ID1

0

1

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

CPU_(LPSS/ISH)

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

1

X00

20 105Monday, December 26, 2016

X00

Vinaﬁx.com

5

Main Func = PCH

4

3

2

1

+V1.00A_SIP

D D

+VCCPRIM_CORE

2.57A

SC1U10V2KX-1GP

+V1.00A_SIP

C2109

12

+VCCDSW _1P0

+VCCAMPHYPLL_1P0

+VCCAPLL_1P0

+V1.00A_SIP

+VCCPDSW_3P3

+VCCPAZIO

+V3.3A_SIP

+VCCSRAM_1P0

+V3.3A_SIP +V1.00A_SIP

+VCCAPLLEBB_1P0

SC1U10V2KX-1GP

12

C2110

SCD1U16V2KX-3GP

Layout Note:

C2111

SCD1U16V2KX-3GP

1uF: C2105 near V19 C2106 near AK17 C2107 near AG15 C2109 near Y16 C2110 near T16 C2111 near AJ19

12

C2120

C2121

Do Not Stuff

12

C C

B B

+V3.3A_SIP

Do Not Stuff

12

DY

SC1U10V2KX-1GP

1 2

20161024 0ohm to short pad

C2105

C2106

SC1U10V2KX-1GP

12

SC1U10V2KX-1GP

12

+VCCMPHYGTAON_1P0_LS_SIP

R2101

R2101 Do Not Stuff

Do Not Stuff

C2107

12

CPU1O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0

N16

VCCMPHYGT_1P0

N17

VCCMPHYGT_1P0

P15

VCCMPHYGT_1P0

P16

VCCMPHYGT_1P0

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0

Y18

VCCPRIM_1P0

AD17

VCCDSW_3P3

AD18

VCCDSW_3P3

AJ17

VCCDSW_3P3

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3

AK20

VCCPRIM_1P0

N18

VCCAPLLEBB_1P0

SKYLAKE-U-GP

CPU POWER 4 OF 4

+V1.8A_SIP

SKYLAKE_ULT

1.8V Only

12

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

+VCCPRIM_CORE

C2108

SC1U10V2KX-1GP

DY

15 OF 20

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD

VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3 VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

C2102

Do Not Stuff

12

+VCCDSW _1P0

+V3.3A_SIP

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1 AA1 AK17 AK19

BB14

VCCRTCEXT

BB10 A14 K19 L21 N20 L19 A10

V0.85A_VID0

AN11

20160630 remove TP2102 for layout space

AN13

C2103

12

+V1.8A_SIP

+V1.00A_SIP +V1.8A_SIP +V3.3A_SIP

C2112 SCD1U16V2KX-3GPC2112 SCD1U16V2KX-3GP

+V1.00A_SIP +VCCCLK2 +V1.00A_SIP +VCCCLK4 +VCCCLK5 +V1.00A_SIP

+V1.00A_SIP

C2124

SC1U10V2KX-1GP

12

+VCCPRTC_3P3

1 2

1

12

DY

+V3.3A_SIP

TP2101 Do Not StuffTP2101 Do Not Stuff

C2104

C2101

SC1U10V2KX-1GP

Do Not Stuff

12

Layout Note:

1uF: C2101 near AB19 C2104 near K17 C2116 near A10 C2124 near AL1

+VCCPRTC_3P3

C2118

C2119

SCD1U16V2KX-3GP

Do Not Stuff

12

DY

12

C2117

SC1U10V2KX-1GP

CAP need close to AK19

R2111

R2109

Do Not Stuff

R2108

R2108 Do Not Stuff

Do Not Stuff

R2107

R2107 Do Not Stuff

Do Not Stuff

+VCCPRTC_3P3

+VCCAPLL_1P0+V1.00A_SIP

+VCCCLK2

+VCCCLK4

+VCCCLK5

RTC_AUX_S5

R2106

1 2

Do Not Stuff

20161024 0ohm to short pad

+VCCAMPHYPLL_1P0_L +VCCAMPHYPLL_1P0

+V1.00A_SIP

20161024 0ohm to short pad

+V1.00A_SIP

R2110

1 2

0R3J-0-U-GP

1 2

0R3J-0-U-GP

1 2

20161024 0ohm to short pad

1 2

20161024 0ohm to short pad

20161024 0ohm to short pad 20161108 short pad to 0ohm

+V1.00A_SIP

+VCCAMPHYPLL_1P0

SC22U6D3V3MX-1-GP

C2122

A A

12

Layout Note:

22uF: C2122 near K15

+VCCAPLL_1P0

C2123

12

Do Not StuffDYC2123

Do Not Stuff

Layout Note:

22uF: C2123 near K15

+VCCCLK2

C2116

SC1U10V2KX-1GP

12

DY

5

4

+VCCCLK4

Do Not Stuff

C2113

12

DY

3

+VCCCLK5

Do Not Stuff

12

DY

C2114

Do Not Stuff

12

DY

C2115

Layout Note:

1uF: C2116 near A10 22uF: C2115 near K19 C2114 near N20 C2113 near L19

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(POWER1)

Taos KBL-U

21 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

D D

CPU1T

AW69

RSVD#AW69

AW68

RSVD#AW68

AU56

RSVD#AU56

AW48

RSVD#AW48

C7

RSVD#C7

U12

RSVD#U12

U11

RSVD#U11

H11

RSVD#H11

SKYLAKE-U-GP

C C

SKYLAKE-U-GP

SKYLAKE_ULT

SPARE

20 OF 20

RSVD#F6

RSVD#E3 RSVD#C11 RSVD#B11 RSVD#A11 RSVD#D12 RSVD#C12

RSVD#F52

F6 E3 C11 B11 A11 D12 C12 F52

B B

2.DIS

Wistron Corporation

A A

Title

CPU_(RSVD)

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

CPU_(RSVD)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taos KBL-U

22 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = PCH

CPU1P

GND 1 OF 3

SKYLAKE_ULT

A5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-U-GP

SKYLAKE_ULT

TP2309Do Not Stuff TP2309Do Not Stuff

D D

C C

B B

TP2311Do Not Stuff TP2311Do Not Stuff TP2310Do Not Stuff TP2310Do Not Stuff

1 1

A67_TP A70_TP

A67 A70 AA2

AA4 AA65 AA68 AB15 AB16 AB18 AB21

AB8 AD13 AD16 AD19 AD20 AD21 AD62

AD8 AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2

AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71

AH13

AH6 AH63 AH64 AH67

AJ15 AJ18 AJ20

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

AJ4

A5_TP

1

16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

CPU1R

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66

H15 H18 H71

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

G5

G6

J11 J13 J25 J28 J32 J35 J38 J42

L11 L16 L17

F8

J8

CPU1R

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKYLAKE-U-GP

SKYLAKE_ULT

18 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

CPU1Q

GND 2 OF 3

AT63

VSS

AT68

VSS

AT71

VSS

AU10

VSS

AU15

VSS

AU20

VSS

AU32

VSS

AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38

AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

BA45

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

F68

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV1_TP

1

TP2307Do Not Stuff TP2307Do Not Stuff

AV71_TP

1

TP2304Do Not Stuff TP2304Do Not Stuff

B71_TP

1

TP2312Do Not Stuff TP2312Do Not Stuff TP2305Do Not Stuff TP2305Do Not Stuff

TP2306Do Not Stuff TP2306Do Not Stuff

1

BA1_TP

BA2_TP

SKYLAKE_ULT

17 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

BA71_TP

BB67_TP

1

BB70_TP

1

20160630 removeTP2308 for layout space

E71_TP

1

TP2303 Do Not StuffTP2303 Do Not Stuff

TP2302 Do Not StuffTP2302 Do Not Stuff TP2301 Do Not StuffTP2301 Do Not Stuff

1

TP2314 Do Not StuffTP2314 Do Not Stuff

SKYLAKE-U-GP

A A

5

4

3

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU_(VSS)

Taos KBL-U

1

23 105Monday, December 26, 2016

X00

Vinaﬁx.com

5

Main Func = KBC

1D0V_S 5

R2402

DY

R2440

DY

R2492

12

KSI0 KSI3 KSI1 KSI5

KSI2 KSI4 KSI6 KSI7

KSO6 KSO7 KSO4 KSO5

KSO2 KSO1 KSO3 KSO8

CMP_VOUT 1

12

DY

EC_VTT

12

C2406

20161108 RF change DY to stuff

3D3V_S 5_KBC

HW_GPS _DISAB LE2# [62]

boost_m on [4 4]

Layout Note:

R2432

1 2

1KR2J-1 -GP

G

S

SCD1U16V2KX-3GP

EC2401

R2401

C2402

1 2

Do Not Stuff

+VCCSTG

1 2

Do Not Stuff

+V1.00U_C PU

Layout Note:

Need very close to EC

RN2412

1 2 3 4 5

SRN10KJ -6-GP

RN2411

1 2 3 4 5

SRN10KJ -6-GP

RN2410

1 2 3 4 5

SRN100K J-5-GP

RN2409

1 2 3 4 5

SRN100K J-5-GP

R2498

12

C2441

DY

Do Not Stuff

1 2

0R2J-2-G P

8 7 6

Do Not Stuff

R2423

DY

Do Not Stuff

Need very close to EC

20161024 0ohm to short pad 20161108 short pad to 0ohm

D D

3D3V_S 5_KBC

C C

I_BATT

EC_AGND

B B

Power Switch Logic(PSL)

KBC_PW RBTN#[64]

EC_GPIO47 High Active

R2417

Do Not Stuff

A A

Do Not Stuff

3D3V_S 5 3D3V_S 5_KBC

20161104 RF add

12

WWAN

FC2403

SC470P50V2KX-L-GP

12

FC2402SCD1U25V2KX-GP

WWAN

RN2403

1

8

2

7

3

6

4 5

SRN100K J-5-GP

RN2404

1

8

2

7

3

6

4 5

SRN100K J-5-GP

12

DY

Do Not Stuff

12

DY

Do Not Stuff

PCH_PLT RST#_E C

1 2

DY

Do Not Stuff

Layout Note:

Need very close to EC

R2418

R2418 Do Not Stuff

Do Not Stuff

1 2

DY

Q2408

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

5

12

C2421

SCD1U16V2KX-3GP

EC_AGND

KSO10 KSO11 KSO14 KSO13

KSO15 KSO16 KSO12 KSO0

DGPU_PW ROK

CLKRUN#

0518 modify correct location

ECVBAT

H_PROCHO T#_EC

3D3V_S 5

20160617 modify DY

12

FC2401Do Not StuffDYFC2401Do Not Stuff

12

C2412

C2420

DY

C2416

C2415

DY

Do Not Stuff

SCD1U16V2KX-3GP

3D3V_S 5_KBC

R2450

R2450 100KR2 J-1-GP

100KR2 J-1-GP

1 2

R2449

R2449 Do Not Stuff

Do Not Stuff

DY

1 2

PCH_RSMR ST#[17]

LPC_LA D[3..0][18 ,68,91]

LPC_LF RAME#[18,6 8,91]

PLT_RS T#[17,31,55,61 ,62,68,76 ,91]

CLK_PC I_LPC_ MEC[1 8]

CLKRUN#[18]

SERIRQ[18,20]

TP_EN#[65 ] SIO_RC IN#[18]

20160617 10 ohm*3 follow up vegas as 8P4R

SPI_CL K_ROM[18 ,25,91]

SPI_SI _ROM[1 8,25,91]

SPI_SO _ROM[18,25,91]

EC_SLP _S0IX#[17,40,9 1]

RTCRST _ON[1 8]

SPI_CS _ROM_N0[18,25 ]

SIO_SL P_S4#[17,40,54]

AC_DIS[43,44]

PCH_ALW _ON[41 ]

ME_SUS_P WR_AC K[17]

INT_TP#[4,65 ]

PM_LAN_E NABLE[31]

ALL_SYS _PWRG D[17,4 0]

RESET_ OUT#[1 7,26,40]

SUS_CLK[18]

ALL_SYS_PWRGD a ssert, delay 10ms; RES ET_OUT# assert .

20160617 change 82.30001.C01 to 082.30003.0201 for cost

R2451

R2451 100KR2 J-1-GP

100KR2 J-1-GP

1 2

POWER _SW_I N#

C2426

12

SC1U10V 2KX-1GP

R2416

1 2

Do Not Stuff

20161024 0ohm to short pad

H_PROCHO T# [4,44,46]

12

C2403

C2403 Do Not Stuff

Do Not Stuff

DY

12

C2411

DY

Do Not Stuff

KSO[0..16 ][65]

KSI[0..7][65]

CLK_TP _SIO[6 5] DAT_TP _SIO[65 ] SIO_PW RBTN#[17,99]

R2410

SRN10J-1 -GP

R2431

R2431 R2491

R2491

R2481

R2428 Do Not Stuff

1 2

R2446

1 2

Do Not Stuff

20161024 0ohm to short pad

12

C2410

C2414

C2413

DY

Do Not Stuff

SCD1U16V2KX-3GP

SCD1U16 V2KX-3G P

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

CAP_LE D#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

LPC_LA D0 LPC_LA D1 LPC_LA D2 LPC_LA D3

PCH_PLT RST#_E C

12

Do Not Stuff

SIO_EX T_SMI# TP_EN#

SIO_EX T_SCI#

RN2401

1

8 2 3 4 5

20161024 0ohm to short pad

C2425

C2425 SC10P5 0V2JN-4G P

SC10P5 0V2JN-4G P

Dummy R2422 & C2427 by EC control PCH_DPWROK 20150416

EC_SPI _CLK

7

EC_SPI _MOSI

6

EC_SPI _MISO EC_SLP _S0IX#

R2490

EC_SPI _CS0#

12

Do Not Stuff

12

Do Not Stuff

12

Do Not Stuff

12

Do Not Stuff

XTAL2

12

DY

XTAL1

X2401

1 2

XTAL-32 D768KHZ -89-GP

082.30003.0201

Microchip: Use CL=9p Xtal󶁜C = 10p

3D3V_S 5_KBC

4

If don't need RTC alarm wake up, can change to 3D3V_AUX_S5

12

C2417

DY

PTP_INT #_EC LAN_EN

USB_EN# RUNPWRO K

DY

R2414

1 2

DY

Do Not Stuff

C2428

1 2

XTAL_K BC_2

1 2

3D3V_S 5_KBC

DB3

Do Not Stuff

RTC_AUX _S53D3V_A UX_S5

R2472

R2473

DY

Do Not Stuff

20161024 0ohm to short pad

1 2

ECVBAT

12

KBC24

2

GPIO027/KSO00/PVT_IO1

14

GPIO015/KSO01/PVT_CS#

15

GPIO016/KSO02/PVT_SCLK

16

GPIO017/KSO03/PVT_IO0

37

GPIO045/BCM_INT1#/KSO04

38

GPIO046/BCM_DAT1/KSO05

39

GPIO047/BCM_CLK1/KSO06

50

GPIO025/KSO07/PVT_IO2

46

GPIO055/PWM2/KSO08/PVT_IO3

68

GPIO102/KSO09/CR_STRAP

72

GPIO106/KSO10

74

GPIO110/KSO11

75

GPIO111/KSO12

76

GPIO112/PS2_CLK1A/KSO13

77

GPIO113/PS2_DAT1A/KSO14

86

GPIO125/KSO15

92

GPIO132/KSO16

93

GPIO140/KSO17

98

GPIO143/KSI0/DTR#

99

GPIO144/KSI1/DCD#

6

GPIO005/SMB00_DATA/SMB00_DATA18/KSI2

7

GPIO006/SMB00_CLK/SMB00_CLK18/KSI3

104

GPIO147/KSI4/DSR#

105

GPIO150/KSI5/RI#

107

GPIO151/KSI6/RTS#

108

GPIO152/KSI7/CTS#

78

GPIO114/PS2_CLK0

79

GPIO115/PS2_DAT0

52

GPIO026/PS2_CLK1B

88

GPIO127/PS2_DAT1B

59

GPIO040/LAD0

60

GPIO041/LAD1

61

GPIO042/LAD2

62

GPIO043/LAD3

58

GPIO044/LFRAME#

56

GPIO064/LRESET#

57

GPIO034/PCI_CLK

63

GPIO067/CLKRUN#

55

GPIO063/SER_IRQ

10

GPIO011/SMI#/EMI_INT#

49

GPIO060/KBRST

53

GPIO061/LPCPD#

66

GPIO100/EC_SCI#

32

GPIO126/SHD_SCLK

28

GPIO133/SHD_IO0

29

GPIO134/SHD_IO1

30

GPIO135/SHD_IO2

31

GPIO136/SHD_IO3

27

GPIO123/SHD_CS#

67

GPIO101/SPI_CLK

69

GPIO103/SPI_IO0

71

GPIO105/SPI_IO1

42

GPIO052/SPI_IO2

33

GPIO062/SPI_IO3

3

GPIO001/SPI_CS#/32KHZ_OUT

13

RESET_IN#/GPIO014

48

GPIO057/VCC_PWRGD

73

GPIO107/RESET_OUT#

125

XTAL2

123

XTAL1

MEC1404 -NU-GP

R2458

071.01404.000E

Do Not Stuff

C2424

C2424 SC10P5 0V2JN-4G P

SC10P5 0V2JN-4G P

20161223 change short pad to 0ohm

I_SYS

EC_AGND

3D3V_S 5_KBC

R2478

R2478 Do Not Stuff

Do Not Stuff

ICSP_C LOCK ICSP_D ATA

1 2

HOST_DE BUG_TX E51_TX D_R

ICSP_C LR

R2497

0R2J-2-G P

20161024 0ohm to short pad

R2425

DY

Do Not Stuff

12

DY

C2427

Do Not Stuff

R2476 Do Not Stuff

12

DB3

R2463 Do Not Stuff

12

DB3

R2464 Do Not Stuff

12

DB3

R2466 Do Not Stuff

12

DB3

R2465 Do Not Stuff

12

DB3

4

VSS_VBAT

124

1 2

43

103

122

VTR5VTR19VTR

VBAT

GPIO007/SMB01_DATA/SMB01_DATA18

GPIO010/SMB01_CLK/SMB01_CLK18

GPIO012/SMB02_DATA/SMB02_DATA18

GPIO013/SMB02_CLK/SMB02_CLK18

GPIO130/SMB03_DATA/SMB03_DATA18

GPIO131/SMB03_CLK/SMB03_CLK18

GPIO141/SMB04_DATA/SMB04_DATA18

GPIO142/SMB04_CLK/SMB04_CLK18

MEC1404

GPIO116/TFDP_DATA/UART_RX

GPIO033/PECI_DAT/SB_TSI_DAT

GPIO166/CMP_VREF1/UART_CLK

VSS

VSS64VSS

84

112

100

EC_AGND

VR_CAP

12

R2445

Do Not Stuff

EC_AGND

12

PCH_DPW ROK [17]

12

P_SYS [44,46]

3D3V_A UX_KBC_ R ICSP_C LK_R

ICSP_D ATA_R

ICSP_C LR_R

3D3V_S 5_KBC

R2462

R2462 Do Not Stuff

Do Not Stuff

1 2

20161024 0ohm to short pad

12

C2423

SCD1U16V2KX-3GP

3D3V_AUX_KBC_33

54

VTR_33_18

VTR65VTR82VTR

GPIO050/TACH0 GPIO051/TACH1

GPIO053/PWM0 GPIO054/PWM1

GPIO056/PWM3 GPIO030/BCM_INT0#/PWM4 GPIO031/BCM_DAT0/PWM5 GPIO032/BCM_CLK0/PWM6

GPIO002/PWM7

GPIO157/LED0/TST_CLK_OUT

GPIO156/LED1 GPIO104/LED2

GPIO117/TFDP_CLK/UART_TX

GPIO035/SB-TSI_CLK

VREF_CPU

GPIO145/ICSP_CLOCK

GPIO146/ICSP_DATA

ICSP_MCLR

BGPO/GPIO004

SYSPWR_PRES/GPIO003

VCI_OUT/GPIO036 VCI_IN1#/GPIO162 VCI_IN0#/GPIO163

VCI_OVRD_IN/GPIO164

GPIO160/DAC_0

GPIO161/DAC_1

DAC_VREF

GPIO124/CMP_VOUT0

GPIO020/CMP_VIN0

GPIO165/CMP_VREF0 GPIO120/CMP_VOUT1

GPIO021/CMP_VIN1

GPIO024/CMP_STRAP0

GPIO023/ADC6/A20M

GPIO022/ADC5 GPIO153/ADC4 GPIO154/ADC3 GPIO155/ADC2 GPIO122/ADC1 GPIO121/ADC0

ADC_VREF

VR_CAP18VSS17VSS51AVSS

C2418

C2418 SC1U10V 2KX-1GP

SC1U10V 2KX-1GP

Layout Note:

Connect GND and AGND planes v ia either 0R resistor or connect direct ly.

7 1

2 3 4 5 6 8

Do Not Stuff

SMBDA1

8

SMBCLK1KSO9

9

SMBDA2

11

SMBCLK2

12

SYS_PW ROK

89

L_BKLT _EN_EC

91 96

PBAT_P RES#

97

FAN1_TA CH

40 41

44 45

47 34 35 36 4

BAT1_L ED#

1

BAT2_L ED#

106

PWR_L ED#

70 80

81

PTP_DI S#

90

PECI_E C

94

EC_VTT

95

ICSP_C LOCK

101

ICSP_D ATA

102

ICSP_C LR

87

EC_MUTE#

119

+3VLP

120

ALWON

121

VCI_IN1 #

126

POWER _SW_I N#

127

ACAV_I N

128

20161213 R2427 change 0 ohm to short pad

23

DGPU_PW ROK_K BC

24 22

CMP_VOUT 0

85 20 25

CMP_VOUT 1

83 21

LCD_TS T

26 118

PANEL_B KEN_EC

117 116

MODEL_I D

109

I_ADP

110

BOARD_ ID

111

I_SYS

113

I_BATT

114 115

3D3V_S 5_KBC

C2422

12

EC_AGND

DAT_IT E8010[96]

CLK_IT E8010[96]

DB3

3

3D3V_S 5

12

R2443

R2443 Do Not Stuff

Do Not Stuff

PCB_REV

BOARD_ ID

12

R2444

C2408

100KR2 F-L1-GP

1 2

EC_AGND

SCD1U16V2KX-3GP

ALL_SYS_PWRGD d e-assert, delay 100ms; SY S_PWROK assert .

SYS_PW ROK [17]

FAN1_DA C

1 2

Do Not Stuff

R2437

C2405

43R2J-G P

12

Need very close to EC

DY

EC_MUTE# [27] ALWON [40]

R2469 Do Not Stuf fR2469 Do Not Stuff

12

PWR_C HG_ACOK [17 ,44]

12

DGPU_PW ROK [19,79,85 ]

C2429

1 2

USBCHARG ER_CB0 [34]

12

R2421

12

330R2J -3-GP

Need very close to EC

SC2200P50V2KX-2GP

Do Not Stuff

LCD_TS T

SRN2K2J -1-GP

R2471

12

SMBDA2

12

SMBCLK2

MASK_BA SE_LED S# [64 ]

3D3V_S 5_KBC

GPU_PW R_LEVE L [79]

BLON_OUT [55]

SIO_EX T_WAK E# [20] AD_IA [44 ]

R2480

1 2

DY

Do Not Stuff

R2435

100KR2 J-1-GP

SMBDA2 SML1_SMBDATA

RN2407

84.2N702.A3F

2nd = 84.2N 702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

R2427

Do Not Stuff

SCD1U16 V2KX-3G P

20161013 add config2.3 to detect different SSD vendor

R2439 Do Not Stuf fR2439 Do Not Stuff

12

C2435

SCD1U16V2KX-3GP

EC_AGND

20161012 remove D2401 R2488 add R2435 R2436 to let EC push BLON

L_BKLT _EN[8]

eDP backlight C ontrol from PC H

20161107 change 10K to 2.2K Vendor suggest for I2C hold time SPEC,location name change RN2603 to RN2407

20161024 0ohm to short pad

Do Not Stuff

20161024 0ohm to short pad

R2474

Do Not Stuff

Taos_X00 Taos_X01 Taos_X02 Taos_A00

Reserved Reserved Reserved Reserved Reserved Reserved 100.0K

SMBDA1 [4 3,44] SMBCLK1 [43,44]

SIO_SL P_SUS# [17,41,53,54 ] PBAT_P RES# [43 ,44]

LID_CL _SIO# [70]

BKLGT_ PWM [65] BEEP [27]

SUSACK# [17] EC_WA KE# [17 ]

PS_ID [43 ]

SIO_SL P_S3# [1 7,27,40,5 1]

ME_FWP _EC [98]

HOST_DE BUG_TX [61]

H_PECI [4]

ECVBAT

R2452

100KR2 J-1-GP

1 2

20160713 DY

CMP_VOUT 0 [26] NGFF_CO NFIG_2 [62] NGFF_CO NFIG_3 [62]

BLON_OUT

20161212 R2435 change 0 ohm to short pad

L_BKLT _EN_EC

12

R2422

R2436

1 2

DY

Do Not Stuff

R2419

1 2

DY

Do Not Stuff

NON DS3

1 2

R2482 Do Not Stuff

NON DS3

1 2

R2483 Do Not Stuff

3D3V_S 5_KBC 3D3V_S5_PC H

1

23

DS3

2N7002K DW-GP

4

6

DS3

Q2604

R2453 10KR2 J-3-GPR2453 10KR 2J-3-GP

1 2

LCD_VC C_TEST _EN [55,96]

LCD_TS T [55]

SML1_SMB CLKSMBCLK2

1 2345

Reserved for DS3 circuit

3

100.0K

3D3V_S 0

1 2

83.R2004.G8F

12

+3VLP

20160616 modify for 1416

3D3V_S 5_PCH

USB_EN#

INT#_IT E8010 [9 6]

20160608 modify

4.99K(64.49925.6DL)

16.2K(64.16225.6DL)

28.7K(64.28725.6DL) 43K(64.43025.6DL) 59K(64.59025.6DL)

76.8K(64.76825.6DL) 100K(64.10035.6DL) 130K(64.13035.6DL) 169K(64.16935.6DL) 226K(64.22635.6DL)

R2430

R2430 10KR2J -3-GP

10KR2J -3-GP

D2403

KA

RB751V -40H-GP

C2401

C2401 SC10U6D 3V3MX-GP

SC10U6D 3V3MX-GP

3D3V_A UX_S5

12

R2467

R2467 1KR2J-1 -GP

1KR2J-1 -GP

12

R2454

R2454 100KR2 J-1-GP

100KR2 J-1-GP

3D3V_S 5_PCH

12

DY

R2461

Do Not Stuff

20161024 0ohm to short pad

Do Not Stuff

SML1_SMB DATA [18 ,26,79]

SML1_SMB CLK [1 8,26,79]

2

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORBoard_ID_DET(GPIO153)

3.143V

2.840V

2.564V

2.307V

2.075V

1.866V

1.650V

1.435V

1.227V

1.012V

FAN_TAC H1 [26]

FAN1_DA C_1 [26]

CHG_AMBE R_LED#[64]

PWR_L ED#_S[64]

3D3V_S 5

12

R2434

G

DY

S

Do Not Stuff

R2479

Q2401

12

R2434 100KR2 J-1-GP

100KR2 J-1-GP

D

USB_PW R_EN# [35]

SPI Flash ROM(1or 2M) for EC

EC_SPI _CS0# EC_SP I_CS0 #_R

R2426 Do Not Stuff

SPI3_S O_ROM

R2522 Do Not Stuff

R2522 Do Not Stuff R2456 Do Not Stuff

R2456 Do Not Stuff

3D3V_S 5_KBC

20160615 SPI Flash ROM(1or 2M) for EC-Power change to 3D3V_S5_KBC

R2457 Do Not Stuff

2

20160608 modify

R2442

Do Not Stuff

MODEL_ID

MODEL_I D

C2407

1 2

EC_AGND

SCD1U16V2KX-3GP

BAT1_L ED#

3D3V_S 5 3D3V_S 5

CAP_LE D#

3D3V_S 5 3D3V_S 5

TP_EN# LID_CL _SIO#

MASK_BA SE_LED S#

HW_GPS _DISAB LE2#

TOUCH_PA NEL_INTR #

Touch Panel PH internally.

'CMP_STRAP0' pu ll high to ena ble Comparator func tion 11/24

LID_CL _SIO#

PTP_DI S#

1 2

DY

1 2

DY

1 2

DY

EC2507

Do Not Stuff

1 2

SPI3_S O_ROMEC_SPI _MISO

DY

20160804 modify model ID table

3D3V_S 5

Reserved

12

UMA

Reserved Reserved

Reserved Reserved Reserved Reserved

12

Reserved

R2441

R2441 100KR2 F-L1-GP

100KR2 F-L1-GP

SMBCLK1 SMBDA1

PCH_ALW _ON

PBAT_P RES# SIO_EX T_SCI# SIO_EX T_SMI#

20160629 add follow Keystone

MASK_BA SE_LED S#

Q2417

1

6

2

5

BAT2_L ED#

3 4

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2N 702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

Q2418

1

6

2

5

PWR_L ED#

3 4

2N7002K DW-GP

84.2N702.A3F

2nd = 84.2N 702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

20160622 Merge R2433/R2409 to RN2406

20160728 Change 066.10436.L001 to 66.10436.04L

RN2406

1 2 3

SRN100K J-6-GP

R2438 Do Not Stuff

1 2

DY

R2413 100KR 2J-1-GPR2413 100KR2J -1-GP

1 2

R2429 Do Not Stuff

1 2

DY

D2402

K A

83.R2004.G8F

RB751V -40H-GP

D2405

K A

83.R2004.G8F

RB751V -40H-GP

20160615 SPI Flash ROM(1or 2M) for EC-Power change to 3D3V_S5_KBC

3D3V_S 5_KBC

R2518

DY

Do Not Stuff

1 2

SPI3_S O_ROM_R SPI3_W P_ROM_ R SPI3_CLK_R OM_R

12

DY

PULL-LOW RESISTOR

RN2402

1234

SRN4K7J -8-GP

R2496 100KR2 J-1-GP

1 2

DS3

R2415 10KR2J -3-GPR2415 10KR2 J-3-GP

1 2

R2411 Do Not StuffR2411 Do Not Stuff

1 2

R2412 Do Not StuffR2412 Do Not Stuff

1 2

R2499 100KR2 J-1-GPR2499 100KR2J-1 -GP

1 2

BATT_W HITE_L ED# [6 4]

CAP_LE D#_S [65]

3D3V_S 5

4

0516 EE DY and SW PP

3D3V_S 0

TOUCH_PA NEL_INTR # [4,55]

TP_LOC K# [65]

20160720 change 78.10623.51L to 78.10610.5BL

SPI241

1

CE#

2

SO/IO1

HOLD#/IO3

3

DY

WP#/IO2

4

GND

SI/IO0

Do Not Stuff

100.0K 3.143V

100.0K

100.0KDIS

100.0K

3D3V_S 5_KBC

BAT1_L ED# BAT2_L ED# CAP_LE D# PWR_L ED#

20160725 follow Keystone13 to change pull high to pull low

USBCHARG ER_CB0

0519 add pull high

3D3V_S PIVCC2

8

VCC

SPI3_HO LD_ROM_ R

7 6

SCK

SPI3_S I_ROM_R

5

EC2509

1

PULL-HIGH RESISTORMODEL_ID_DET(GPIO153)

4.99K(64.49925.6DL)

16.2K(64.16225.6DL)

28.7K(64.28725.6DL) 59K(64.59025.6DL)

76.8K(64.76825.6DL) 100K(64.10035.6DL) 130K(64.13035.6DL) 169K(64.16935.6DL) 1.227V 226K(64.22635.6DL) 1.012V

SIO_EX T_SCI# _R [16] SIO_EX T_SMI#_ R [8]

1 2 3 4 5

SRN100K J-5-GP

R2447 10KR2 J-3-GPR2447 10KR 2J-3-GP

20160615 SPI Flash ROM(1or 2M) for EC-Power change to 3D3V_S5_KBC

12

DY

2.DIS

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

VOLTAGE

2.840V

2.564V

2.307V43K(64.43025.6DL)

2.075V

1.866V

1.650V

1.435V

3D3V_S 5

RN2405

8 7 6

1 2

3D3V_S 5_KBC

R2420

R2420 Do Not Stuff

Do Not Stuff

DY

3D3V_S PIVCC2

1 2

12

C2506

C2507

DY

Do Not Stuff

R2455 Do Not Stuff

1 2

DY

R2519 Do Not Stuff

1 2

DY

R2521 Do Not Stuff

1 2

DY

EC2508

EC2508 Do Not Stuff

Do Not Stuff

20160615 SPI Flash ROM(1or 2M) for EC-Power change to 3D3V_S5_KBC

R2459 Do Not Stuff

R2459 Do Not Stuff R2460 Do Not Stuff

R2460 Do Not Stuff

KBC SMSC 1404

Taos KBL-U

Monday, Decem ber 26, 20 16

1

SPI3_C LK_ROM

1 2

DY

1 2

DY

Wistron Corporation

21F, 88, S ec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, S ec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 22 1, Taiwan, R.O.C.

Taipei Hsien 22 1, Taiwan, R.O.C.

SPI3_S I_ROM

EC_SPI _CLKSPI3_CLK_ ROM EC_SPI _MOSISPI3_SI_RO M

24 105

3D3V_S 5_KBC

X00

Vinaﬁx.com

5

Main Func = SPI Flash

4

3

2

1

R2501

4K7R2J-2-GP

SPI_WP_ROM_R

12

DY

R2515

Do Not Stuff

12

DY

3D3V_S5_PCH

DY

1 2

3D3V_S5_PCH

DY

1 2

SPI1_SO_ROM_R SPI1_WP_ROM_R

4

1

DY

2 3

4

1

2 3

RN2501

RN2501 Do Not Stuff

Do Not Stuff

20160720 change 78.10623.51L to 78.10610.5BL

SPI25

1

CS#

2

DO/IO1

3 4

RN2502

RN2502 Do Not Stuff

Do Not Stuff

HOLD#/RESET#/IO3 WP#/IO2 GND

W25Q128FVSIQ-GP

72.25128.0E1

20160720 change 78.10623.51L to 78.10610.5BL

SPI252

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

Do Not Stuff

BIOS

HOLD#/IO3

DY

VCC

DI/IO0

Do Not Stuff

VCC

CLK

DI/IO0

Do Not Stuff

8 7 6

CLK

5

Do Not Stuff

8 7 6 5

EC2506

3D3V_S5_PCH

SPI_HOLD_ROM_RSPI_SO_ROM_R SPI_CLK_ROM_R SPI_SI_ROM_R

EC2501

C2505

DY

3D3V_S5_PCH

SPI1_HOLD_ROM_R

SPI1_CLK_ROM_R SPI1_SI_ROM_R

12

DY

12

DY

12

DY

SPI Flash ROM(16M) for PCH

SKT25

SPI_CS_ROM_N0[18,24]

SKT25

1

8

2

7

3 6

BIOS_SKT

4

5

Do Not Stuff

D D

SPI_CS_ROM_N0 SPI_SO_ROM_R SPI_WP_ROM_R

3D3V_S5_PCH

SPI_HOLD_ROM_R SPI_CLK_ROM_R SPI_SI_ROM_R

Do Not Stuff

EC2502

SPI Flash ROM(8M) for PCH

C C

SPI_CS_ROM_N1[18] SPI_SO_ROM[18,24,25,91]

SPI_WP_ROM[18,25]

R2513 Do Not Stuff

1 2

DY

R2514 Do Not Stuff

1 2

DY

EC2504

Do Not Stuff

3D3V_S5_PCH

C2501

Do Not Stuff

EC2503

EC2503 Do Not Stuff

Do Not Stuff

12

C2504

C2504 Do Not Stuff

Do Not Stuff

1 2 1 2 1 2

DY

DY DY

DY

12

C2502

C2502 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

DY

12

DY

3D3V_S5_PCH

DY

R2509 Do Not Stuff

R2509 Do Not Stuff R2511 Do Not Stuff

R2511 Do Not Stuff R2512 Do Not Stuff

R2512 Do Not Stuff

EC2505

EC2505 Do Not Stuff

Do Not Stuff

R2503 10R2F-L-GPR2503 10R2F-L-GP

1 2

12

FC2501Do Not StuffDYFC2501Do Not Stuff

DY

20160620 Merge R2507,R2508,R2507,R2506 to RN2503

SPI_HOLD_ROM [18,25] SPI_CLK_ROM [18,24,25,91] SPI_SI_ROM [18,24,25,91]

SPI_HOLD_ROM [18,25]

RN2503

SPI_SO_ROM[18,24,25,91]

SPI_WP_ROM[18,25]

SPI_CLK_ROM[18,24,25,91]

SPI_SI_ROM[18,24,25,91]

1 2 3 4 5

SRN10J-1-GP

SPI_SO_ROM_R

8

SPI_WP_ROM_R

7

SPI_CLK_ROM_R

6

SPI_SI_ROM_R

B B

Main Func = RTC

RTC_AUX_S5+RTC_VCC 3D3V_AUX_S5

AFTP2502AFTP2502

RTC1

ACES-CON2-39-GP-U

20.F2299.002

A A

5

+RTC_VCC

1

R2502

1KR2J-1-GP

3 1

2 4

1

4

1KR2J-1-GP

AFTP2501AFTP2501

12

R2504

R2504 10MR2J-L-GP

10MR2J-L-GP

RTC_PW R

D2501

1

2

BAS40C-2-GP

75.00040.07D

75.00040.07D 2nd = 75.00040.C7D

2nd = 75.00040.C7D 3rd = 75.00040.A7D

3rd = 75.00040.A7D

Q2505

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

3

12

C2503

DY

Do Not Stuff

2.DIS

D

3

RTC_DET# [20]

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Monday, December 26, 2016

Date: Sheet of

Flash/RTC

Taos KBL-U

Taipei Hsien 221, Taiwan, R.O.C.

25 105

1

X00

Vinaﬁx.com

5

Main Func = Thermal Sensor

3D3V_S0

R2601

R2601 Do Not Stuff

Do Not Stuff

1 2

SML1_SMBDATA[18,24,79]

SML1_SMBCLK[18,24,79]

20160622 change P/N 74.83771.ABG to 74.07718.0B9

T_CRIT#

RESET_OUT#[17,24,40]

THERM_SYS_SHDN#

D D

12

C2601

C2602

DY

84.T3904.H11

Q2603

C

T8

E

LMBT3904LT1G-GP

2.System Sensor, Put on palm rest

C C

3D3V_S0

R2603 14KR2F-GP

R2603 14KR2F-GP R2604 2KR2F-3-GP

R2604 2KR2F-3-GP

20161110 temperature change 89 degree to 83 degree

12

C2606

DY

1 2

T8

1 2

T8

C2606 Do Not Stuff

Do Not Stuff

B

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

C2602

T8

SCD1U16V2KX-3GP

Do Not Stuff

NCT7718_DXP

12

T8

NCT7718_DXN

Layout Note:

C2812 close U2801

NCT7718_ALERT#

T_CRIT#

C2607

C2607 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

20161024 0ohm to short pad

4

84.2N702.A3F

2nd = 84.2N702.E3F

3rd = 75.00601.07C

4th = 84.DMN66.03F

THM26

1

VDD

2

D+

3

DT_CRIT#4GND

NCT7718W-GP

74.07718.0B9

T8

SCL SDA

ALERT#

3D3V_S0 3D3V_S0

2N7002KDW-GP

6 5

T8

Q2601

8 7

NCT7718_ALERT#

6 5

1 2 34

Q2602

G

T8

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

1

23

T8

4

RN2602

RN2602 SRN2K2J-1-GP

SRN2K2J-1-GP

12

DY

C2608

12

DY

3

THM_SML1_DATA

THM_SML1_CLK

THM_SML1_CLK THM_SML1_DATA

12

DY

C2609

Do Not Stuff

R2612 Do Not Stuff

C2610

Do Not Stuff

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW _SHUTDOWN# [40,79]

DY

CMP_VOUT0

1 2

need to check with NTD team Barkley 1404 test result

Do Not Stuff

KBC T8

2

Fan controller1

R2605

Do Not Stuff

1 2

5V_S0

FAN1_DAC_1[24]

Layout Note:

Need 10 mil trace width.

KA

12

C2604

20160617DY C2603 & changed Name to EC2603

DY

Do Not Stuff

EC2602

12

DY

3D3V_S5_KBC

R2607

1 2

DY

R2602 Do Not Stuff

DY

FAN_VCC1

D2601

Do Not Stuff

FAN_TACH1[24]

Do Not Stuff

1 2

Do Not Stuff

FON#

FAN_VCC1

12

EC2603

DY

FAN_TACH1 FAN_VCC1

EC2601

12

DY

20160720 DY

DY

Do Not Stuff

FAN261

1

FON#

2

VIN

3

VOUT VSET4GND

AP2113MTR-G1-GP

74.02113.0E1

FAN_TACH1_C

1 2

AFTP2802AFTP2802 AFTP2801AFTP2801

8

GND

7

GND

6

GND

5

R2606

R2606 Do Not Stuff

Do Not Stuff

CMP_VOUT0 [24]

6 4

3 2

1 5

ACES-CON4-17-GP-U1

20.F1621.004

FAN_TACH1_C

1

FAN_VCC1

1

FAN1

12

5V_S0

C2605

12

C2611

SC4D7U6D3V3KX-GP

SCD1U16V2KX-3GP

1

AFTP2803AFTP2803

B B

A A

5

4

3

201601013 remove R2609 R2608 R2610 C2612 C2613 R2611

2

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL NCT7718W/Fan

Size Document Number Rev

Size Document Number Rev A3

A3

Taos KBL-U

Monday, December 26, 2016

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

X00

Vinaﬁx.com

Main Func = Audio

5

4

3

2

1

3D3V_S0

R2731

1 2

Do Not Stuff

D D

20161024 0ohm to short pad

moat

C C

0129 remove R2710 ALC3246 PIN40 use 1.8V only.

1D8V_S0

R2713

1 2

Do Not Stuff

20161024 0ohm to short pad

25mA

20161024 0ohm to short pad

1D8V_S0

R2726

1 2

Do Not Stuff

20161024 0ohm to short pad

1.5A

5V_S0 +5V_PVDD

R2702

1 2

Do Not Stuff

Do Not Stuff R2704

R2704

1 2

Do Not Stuff

+3V_1D8V_AVDD

12

AUD_AGND

C2715

+3V_AVDD

CPVDD

C2714

12

C2701

SC4D7U6D3V 3KX-GP

Close pin36

SCD1U16V2KX-3GP

20160617 DY 10uF*1+ 0.1uF* as like Vegas/OPP

C2708

C2707

C2709

12

SCD1U16V2KX-3GP

C2709

12

DY

Do Not Stuff

Layout Note:

Close pin46

Do Not Stuff

C2706

12

SC10U6D3V3MX-GP

Layout Note:

Close pin41

Speaker trace width >40mil @ 2W4ohm speaker power

12

C2721

SC4D7U6D3V3KX-GP

Close pin40

SCD1U16V2KX-3GP

+3V_AVDD

AUD_AGND AUD_AGND

Layout Note:

EC_MUTE#[24]

R2724

1 2

DY

Do Not Stuff

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

+3V_1D8V_AVDD

AUD_SPK_L+[29]

AUD_SPK_L-[29] AUD_SPK_R-[29] AUD_SPK_R+[29]

R2708

1 2

Do Not Stuff

Azalia I/F EMI

HDA_CODE C_SDOUT HDA_CODE C_BITCLK

DMIC_DATA_R

EC2709

EC2708

12

Do Not Stuff

DY

B B

20160617 DY C2723 (Also Re-Name to EC2723)

EC2701

12

Do Not Stuff

DY

20161024 0ohm to short pad

DMIC_CLK[55]

Do Not Stuff

Close pin3

EC2723

DY

1 2

12

FC2701Do Not StuffDYFC2701Do Not Stuff

DY

DMIC_DATA[55]

HDA_CODE C_SDOUT[19]

20160617 Change R2720 & R2718 to 0 ohm

HDA_CODE C_BITCLK[19]

HDA_SDIN0[19]

HDA_CODE C_SYNC[19]

Audio Codec Chip ALC3246

LINE1_VREFO_R[29] LINE1_VREFO_L[29]

AUD_HP1_JAC K_L[29] AUD_HP1_JAC K_R[29]

C2704

1 2

SC1U10V2KX-1G P

12

LDO2_CAP

+5V_PVDD

AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+

+5V_PVDD

PD#

SC4D7U6D3V 3KX-GP

R2714Do Not Stuff R2714Do Not Stuff

1 2

R2716

1 2

100R2J-2-GP

20160822 change 0ohm to 100R by EMI

CPVDD

C2703

C2703 SC1U10V2KX-1G P

SC1U10V2KX-1G P

36

HDA27

CBP

C2716

+3V_AVDD

1 2 1 2 1 2

37 38 39 40 41 42 43 44 45 46 47 48 49

R2719

R2719 R2720

R2720 R2718

R2718

HDA_CODE C_SYNC

CPVDD

CBP AVSS2 LDO2-CAP AVDD2 PVDD1 SPK-OUT-L+ SPK-OUT-LSPK-OUT-RSPK-OUT-R+ PVDD2 PDB SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC -CLK-IN GND

DVDD1GPIO0/DMIC-DATA122GPIO1/DMIC-CLK3DC_DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10I2C-DATA11I2C-CLK

ALC3246-CG-G P-U

C2717

12

SCD1U16V2KX-3GP

DMIC_DATA_R DMIC_CLK_R

HDA_SDOU T_CODEC_R

Do Not Stuff

HDA_BITCLK_C ODEC_R

Do Not Stuff

HDA_CODE C_SDIN0

Do Not Stuff

CPVEE

CBN

34

35

CBN

CPVEE

R2721

31

32

33

LINE1-VREFO-L

HPOUT-L_PORT-I-L

HPOUT-R_PORT-I-R

071.03246.0003

DVSS

12

Do Not Stuff

DY

30

LINE1-VREFO-R

SPDIFO/FRONT-JD_JD3/GPIO3

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

C2705

12

C2702

SC2D2U10V3KX-1GP

SC4D7U6D3V3KX-GP

AUD_VREF

LDO1_CAP

25

26

27

28

29

VREF

AVSS1

AVDD1

LDO1-CAP

LINE2-L_PORT-E-L

MIC2-VREFO

LINE2-R_PORT-E-R

LINE1-L_PORT-C-L

LINE1-R_PORT-C-R

VD33STB

MIC2-CAP

MIC2-R_PORT-F-R/SLEEVE

MIC2-L_PORT-F-L/RING2

PCBEEP

MIC2/LINE2-JD_JD2

HP/LINE1-JD_JD1

12

+3V_AVDD

C2719SCD1U16V2KX-3GP C2719SCD1U16V2KX-3GP

12

MIC2_VREFO [29]

AUD_AGND

R2711

R2711 100KR2J-1-GP

100KR2J-1-GP

+5V_AVDD AUD_AGND

24 23 22 21 20 19 18 17 16 15 14 13

V3D3_STB MIC_CAP

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

AUD_PC_BEEP _3246 JDREF

R2707 D o Not Stuff

AUD_SENSE_A

SPKR[19]

C2710

SCD1U16V2KX-3GP

1 2

DY

1 2

R2709

200KR2F-L-GP

moat

BEEP[24]

12

C2711

LINE1_L [29] LINE1_R [29]

SLEEVE [29] RING2 [29]

moat

R2703

1 2

Do Not Stuff

12

20161024 0ohm to short pad

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

moat

R2712

1 2

Do Not Stuff

R2723

1 2

Do Not Stuff

AUD_SENSE

Layout Note:

Place close to Pin 13

RN2701

2 3 1

SRN1KJ-7-G P

5V_S0+5V_AVD D

RTC_AUX_S5

AUD_AGND

Layout Note:

AUD_PC_BEEP _R

AUD_AGND

AUD_SENSE [29]

4

moat

EC2707 Do Not Stuff

1 2

DY

EC2706 Do Not Stuff

1 2

DY

EC2705 Do Not Stuff

1 2

DY

EC2704 Do Not Stuff

1 2

DY

EC2703 Do Not Stuff

1 2

DY

AUD_AGND

R2706 Do Not StuffR270 6 Do Not Stuff

1 2

R2727 Do Not StuffR272 7 Do Not Stuff

1 2

R2730 Do Not StuffR273 0 Do Not Stuff

1 2

Layout Note:

AUD_AGND

Tied at point only under Codec or near the Codec

20161012 change power rail from 3D3V_S5 to 3D3V_AUX_S5 . Unexpected Noise in S4 DC Mode

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

moat

+3V_AVDD

R2722

HDA_SPKR_R

KBC_BEEP_R

75.00054.E7D

75.00054.E7D 2nd = 83.R2003.W81

2nd = 83.R2003.W81 3rd = 75.00054.A7D

3rd = 75.00054.A7D

D2701

2

1

BAT54C-7-F- 3-GP

AUD_SENSE_A

+3.3VD@3234 follow Pin1 Power setting@3246

AUD_PC_BEEP _C

3

12

C2720

1 2

R2717

R2717 2K2R2J-2-GP

2K2R2J-2-GP

R2722

100KR2J-1-GP

AUD_PC_BEEP _R

SCD1U16V2KX- 3GP

12

1D8V_S01D8V_S5

Q2701

DMP2130L-7-GP

150mA

12

C2724

R2715

3D3V_S0

SIO_SLP_S3#[17,24,40,51]

A A

5

4

DY

Do Not Stuff

R2728

1 2

Do Not Stuff

Q4009_G

Q2702

G

S

2N7002K-2-GP

R2729

1 2

R2715 10KR2J-3-GP

10KR2J-3-GP

SCD1U16V2KX-3GP

1D8V_EN#

D

3

R2733

1 2

4K7R2J-2-GP

12

1D8V_EN_R#

S

C2722

SCD22U10V2KX- 1GP

84.02130.031

84.02130.031 2nd = 84.00102.031

2nd = 84.00102.031 3rd = 84.03413.B31

3rd = 84.03413.B31

DMP2130L-7-GP

D

G

12

C2725

Do Not Stuff

DY

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size D ocument Numb er Rev

A2

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Audio Codec ALC3234

Taos KBL-U

1

27 105Monday, Decem ber 26, 2016

X00

Vinaﬁx.com

5

D D

C C

4

3

2

1

(Blanking)

B B

2.DIS

Wistron Corporation

A A

Title

Size Document Number Rev

A4

Date: Sheet of

5

4

3

Date: Sheet of

2

Taos KBL-U

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

(Reserved)

28 105Monday, December 26, 2016

1

X00

Vinaﬁx.com

5

Main Func = Audio

4

3

2

1

Layout Note:

Speaker trace width >40mil @ 2W4ohm speaker power

D D

C C

MIC2_VREFO[27]

SLEEVE[27]

AUD_HP1_JACK_L[27]

LINE1_L[27]

LINE1_VREFO_L[27]

AUD_HP1_JACK_R[27]

LINE1_R[27]

LINE1_VREFO_R[27]

RING2[27]

C2907

C2908

1 2

AUD_SPK_L+[27] AUD_SPK_L-[27]

AUD_SPK_R+[27] AUD_SPK_R-[27]

20160615 remove RF CAP by Mars

RN2901

2 3 1

SRN2K2J-1-GP

20160818 R2908 & R2910 modify to 16.5 ohm

LINE1-L_C

SC10U6D3V3MX-GP

LINE1-L_R

SC10U6D3V3MX-GP

R2908 16D5R2F-GPR2908 16D5R2F-GP R2922 1KR2J-1-GPR2922 1KR2J-1-GP R2912 4K7R2J-2-GPR2912 4K7R2J-2-GP

R2910 16D5R2F-GPR2910 16D5R2F-GP R2921 1KR2J-1-GPR2921 1KR2J-1-GP R2913 4K7R2J-2-GPR2913 4K7R2J-2-GP

EC2901Do Not StuffDYEC2901Do Not Stuff

DY

1 2

4

1 2 1 2 1 2

DY

EC2903Do Not StuffDYEC2903Do Not Stuff

EC2902Do Not StuffDYEC2902Do Not Stuff

DY

1 2

EC2904Do Not StuffDYEC2904Do Not Stuff

DY

1 2

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1 AUD_PORTA_R_HPMIC1

EC2908

SC100P50V2JN-3GP

EC2908

SC100P50V2JN-3GP

R2920

Do Not StuffDYR2920

Do Not Stuff

12

DY

Width>40mil, to improve Headpohone Crosstalk noise Change it to sharp will be better. Add 2 vias (>0.5A) when trace layer change.

B B

Layout Note:

20160726 change to EMI element

EL2904PBY160808T-121Y-GP EL2904PBY160808T-121Y-GP

12

EL2903PBY160808T-121Y-GP EL2903PBY160808T-121Y-GP

12

EL2902PBY160808T-121Y-GP EL2902PBY160808T-121Y-GP

12

EL2901PBY160808T-121Y-GP EL2901PBY160808T-121Y-GP

12

20160822 reserve by EMI

EC2907

SC100P50V2JN-3GP

EC2907

SC100P50V2JN-3GP

R2919

Do Not StuffDYR2919

Do Not Stuff

12

EC2909 Do Not StuffDYEC2909 Do Not Stuff

12

DY

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

EC2906

SC100P50V2JN-3GP

12

DY

AUD_AGND AUD_AGND

AUD_SPK_L+_C AUD_SPK_L-_C

AUD_SPK_L-_C AUD_SPK_R+_C AUD_SPK_R-_C

ACES-CON4-29-GP

EC2912 Do Not StuffDYEC2912 Do Not Stuff

EC2910 Do Not StuffDYEC2910 Do Not Stuff

EC2911 Do Not StuffDYEC2911 Do Not Stuff

12

DY

EC2905

12

Speaker

SPK1

5

1 2

3 4

6

20.F1639.004

R2906Do Not Stuff R2906Do Not Stuff

1 2

R2911Do Not Stuff R2911Do Not Stuff

1 2

R2907Do Not Stuff R2907Do Not Stuff

1 2

R2909Do Not Stuff R2909Do Not Stuff

1 2

JACK_PLUG

CONN Pin Pin1 Pin2 Pin3 Pin4

AUD_SPK_L-_C AUD_SPK_L+_C AUD_SPK_R-_C

AUD_SPK_R+_C

10 mils 10 mils

AFTP2901AFTP2901

1

AFTP2902AFTP2902

1

AFTP2903AFTP2903

1

AFTP2904AFTP2904

1

SLEEVE_HPMIC1 RING2_HPMIC1 AUD_PORTA_L_HPMIC1

JACK_PLUG JACK_PLUG_DET

AUD_AGND

R2923

1 2

Do Not Stuff

Net name SPK_R+ SPK_RSPK_L+ SPK_L-

3 4 1

5 6 2

MS

AUDIO-JK577-GP

022.10002.01B1

HPMIC1

AUD_SENSE [27]

AUD_PORTA_R_HPMIC1

SLEEVE_HPMIC1 JACK_PLUG_DET

JACK_PLUG_DET

10 mils

AUD_AGND

A A

5

20161024 0ohm to short pad

12

R2901

R2901 Do Not Stuff

Do Not Stuff

4

moat

2

1

ED2901

AZ5125-02S-R7G-GP

3

2

1

ED2902

AZ5125-02S-R7G-GP

3

2

ED2903

AZ5125-02S-R7G-GP

3

JACK_PLUG

RING2_HPMIC1

AUD_PORTA_L_HPMIC1

1

2.DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Audio IO

Taos KBL-U

Monday, December 26, 2016

Taipei Hsien 221, Taiwan, R.O.C.

29 105

1

X00

Vinaﬁx.com

5

4

3

2

1

Main Func = Audio

D D

C C

(Blanking)

B B

2.DIS

Wistron Corporation

A A

Title

(Reserved)

Size Document Number Rev

Size Document Number Rev A4

A4

A4 Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

(Reserved)

Taos KBL-U

Monday, December 26, 2016

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

X00

30 105

1

X00

Dell Latitude 3480, Latitude 3488, Latitude 3580 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual