Dell Latitude 3330 Schematics

Vinaﬁx.com

5

4

3

2

1

Austin 13" Schematics Document

D D

Ivy Bridge ULV

Panther Point

2013-02-26

C C

DY : None Installed

B B

REV : A00

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

Cover Page

Cover Page Austin 13

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

1 106

1

A00

Vinaﬁx.com

5

D D

HDMI board

HDMI

USB 2.0 + Power share CONN

C C

USB PowerShare

PERICOM PI5USB1457AZAE

LCD

Connector SD/SDHC/SDXC/SD UHS-I MMC/MMC+, MS/MS Pro

CardReader

O2 OZ600FJ0

Mini-Card

Micro SIM

66

INT 2 SATA GenIII x 1

B B

WWAN/MSATA

HDD

Flash ROM

8MB

Flash ROM

4MB

FFS

ST LNG3DM

A A

5

4

51

49

3274

66

56

60

51

FAN

4

3

Austin 13 Block Diagram

Intel CPU

TMDS

USB2.0 x 1

LVDS

PCIE x 1

SATA GEN3 & USB2.0*1

SPI BUS

INT1

SMBUS

Thermal

SMSC EMC4021

JTAG

28

BC Link

Ivy Bridge

17W

BGA1023

4,5,6,7,8,9,10

DMIx4FDIx4x2

Intel

PCH Panther Point

BGA989

HM77

14 USB 2.0/1.1 ports

4 USB 3.0 ports

High Definition Audio

6 SATA ports 8 PCIE ports

LPC I/F

ACPI 4.0a

17,18,19,20,21,22,23,24,25

KBC

SMSC

MEC5055

PS2

Touch PAD

69 69

27

Keyboard controller

EC1117

3

DDRIII 1600MHz Channel A

DDRIII 1600MHz Channel B

PCIE x 1

USB3.0 x 1

USB2.0 x 1

USB3.0 x 1

USB2.0 x 1

HDA

USB2.0 x 1

LPC BUS

BC link

BC Link

Int. KB (Backlight supported)

69

USB2.0 x 1PCIE x 1

RGB CRT

SIO Expander

SMSC

ECE5048

2

Project Code: PCB P/N : Revision :

DDRIII1600MHz

Slot A

Slot B

LAN

Intel Lewisville 82579LM

14

15

31

91.4LA01.001 12275

A00

1

CHARGER

ISL88731CHRTZ

INPUTS

AD+

SYSTEM DC/DC

TPS51125RGER

INPUTS

DCBATOUT +5V_ALW

VT1318+VT1323

INPUTS

+5V_ALW

INPUTS

+5V_ALW

INPUTS

+5V_ALW +3.3V_ALW

5V_PWR_2 +3.3V_ALW2

+3.3V_ALW +15V_ALW

CPU DC/DC

GFX DC/DC

VT1318+VT1323

VCC_GFXCORE

SYSTEM DC/DC

VT386+RT8085

+1.05V_RUN_VTT

SYSTEM DC/DC

OUTPUTS

BT+

OUTPUTS

VCC_CORE

OUTPUTS

+1.05V_M

40

41

42,43

44

45

RT8207

Mini-Card

802.11a/b/g/n BT V4.0 combo

CRT

Codec

IDT

29 58

92HD93

Camera

Internal Digital MIC

49

RJ45

Right side

USB 3.0

Right side

USB 3.0

Combo Jack

2CH Speaker

Daughter Board

INPUTS

DCBATOUT

26

SYSTEM DC/DC

INPUTS

+3.3V_ALW

SYSTEM DC/DC

INPUTS

+3.3V_ALW

SYSTEM DC/DC

INPUTS OUTPUTS

+5V_ALW

INPUTS OUTPUTS

26

INPUTS OUTPUTS

+1.35V_MEM +5V_ALW

+1.05V_N +1.05V_RUN +3.3V_ALW +3.3V_M +3.3V_ALW +5V_ALW

OUTPUTS

+1.35V_MEM +0.675_DDR_VTT +V_DDR_REF

RT8068A

OUTPUTS

+1.8V_RUN

APL5930

OUTPUTS

+1.5V_RUN

SY8037

+VCC_SA

N.A

Switches

+1.35V_CPU_VDDQ

+5V_RUN +3.3V_RUN+3.3V_ALW

+3.3V_ALW_PCH

+5V_ALW_PCH

46

47

48

PCB LAYER

L1:Top L2:GND L3:Signal

LPC debug port

71

L4:Signal

TPM

78

AT97SC3204-X2A1D-AB

77

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Austin 13

1

L5:GND L6:Bottom

2 106Tuesday, February 26, 2013

A00

Vinaﬁx.com

PCH Strapping

A

Name Schematics Notes

Chief River Schematic Checklist Rev.0_72

B

Sandy & Ivy Bridge Compatibility

C

Pin Name Configuration Schematic Notes

D

Chief River Schematic Checklist Rev.0_xx

E

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

4 4

INTVRMEN GNT3#/GPIO55

GNT2#/GPIO53 GNT1#/GPIO51

DF_TVS HAD_DOCK_EN#

/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. HDA_SYNC GPIO15

3 3

Power Plane

+5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +1.05V_RUN_VTT +1.05V_M +VCC_SA +VCC_CORE +VCC_GFXCORE

2 2

+1.35V_MEM +0.675V_DDR_VTT

The signal has a weak internal pull-down. If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (Panther Point will disable the TCO Timer system reboot feature).

Integrated 1 V VRMs is enabled when high, External when low. GNT[3:0]# functionality is not available on Mobile.

Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

DF_TVS needs to be pulled up to VccDFTERM power rail through 2.2 kOhms ±5% resistor. This signal controls the external Intel HD Audio docking isolation logic. This is

an active-low-signal. When deasserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the Intel HD Audio dock signals to the corresponding Panther Point signals. This signal can instead be used as GPIO33.

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. Low (0)

Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Voltage DescriptionActice StatusPower Plane

5V

3.3V

1.8V

1.5V

1.05V

0.75V~0.9V

0.3V to 1.3V 0 to 1.25V

1.5V

0.75V

S0

S3

CPU Core Rail Graphics Core Rail

DDR3 VREF

PROC_SELECT# & DF_TVS

VCCIO_SEL

VCCSA_VID[0:1]

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Sandy Bridge + Ivy Bridge

Ivy Bridge

Processor Strapping

Pin Name Strap Description

CFG[2]

CFG[4]

CFG[6:5]

PCI-Express Static Lane Reversal

PCI-Express Port Bifurcation Straps

DDR3 VREF, M1 and M3 function are required.

No change.

Connect DF_TVS signal of the PCH to PROC_SELECT# of the processor through a 1K±5% series resistor. PROC_SELECT# also needs a 2.2K±5% pull up resistor to PCH VccDFTERM rail.

No change.

The POR for Ivy Bridge mobile parts is now 1.05 V. There is no longer a need for a separate VR for the processor at 1.0 V and the PCH at 1.05 V. A single VR may be shared for both.

No change.

VCCSA[0:1] are the select pin of VCCSA's power control.

No change.

Chief River Schematic Checklist Rev.0_72

Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort. Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11:

1x16 PCI Express 2 x8 - PCI Express

10:

Reserved

01:

1x8, 2x4 PCI Express

00:

Default Value

1

11

POP Value

1

11

PCIE Table SATA TableUSB Table

BT+ DCBATOUT +15V_ALW +5V_ALW +3.3V_ALW

+3.3V_LAN 3.3V

+3.3V_ALW2 DSW, Sx ON for supporting

RTC_AUX_S5

1 1

6V~14.1V 6V~14.1V 15V 5V

3.3V

All S states

WOL_EN

G3, Sx

AC Brick Mode only

Legacy WOL

Deep Sleep states

Powered by Li Coin Cell in G3 and +V3ALW in Sx

Pair

USB0(Left side-HDMI/B)

0

USB1(Right side-IO/B, for USB3.0)

1

USB2(Right side-IO/B, for USB3.0)

2

NC

3

WLAN

4

WWAN

5

NC

6

NC

7

NC

8

NC

9

NC

10

NC

11

CAMERA

12

NC

13

Device

Lane

1 2 3 4 5 6 7 8

PCIE Device

NC WLAN NC NC NC Card Reader Onboard LAN NC

SATA

Pair

0 1 2 3 4 5

Title

Size Document Number Rev

A3

Date: Sheet of

Device

HDD1 mSATA NC NC NC NC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Austin 13

3 106Tuesday, February 26, 2013

A00

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

Layout Note:

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.

D D

1 OF 9

CPU1A

DMI_TXN[3:0](19)

Layout Note:

DMI trace length 2000~8000mil

C C

Layout Note:

FDI trace length 2000~6500mil

B B

Layout Note:

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

+1.05V_RUN_VTT

DMI_TXP[3:0](19)

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

FDI_TXN[7:0](19)

FDI_TXP[7:0](19)

FDI_FSYNC0(19) FDI_FSYNC1(19)

FDI_INT(19) FDI_LSYNC0(19)

FDI_LSYNC1(19)

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

DP_COMP

M2

DMI_RX#0

P6

DMI_RX#1

P1

DMI_RX#2

P10

DMI_RX#3

N3

DMI_RX0

P7

DMI_RX1

P3

DMI_RX2

P11

DMI_RX3

K1

DMI_TX#0

M8

DMI_TX#1

N4

DMI_TX#2

R2

DMI_TX#3

K3

DMI_TX0

M7

DMI_TX1

P4

DMI_TX2

T3

DMI_TX3

U7

FDI0_TX#0

W11

FDI0_TX#1

W1

FDI0_TX#2

AA6

FDI0_TX#3

W6

FDI1_TX#0

V4

FDI1_TX#1

Y2

FDI1_TX#2

AC9

FDI1_TX#3

U6

FDI0_TX0

W10

FDI0_TX1

W3

FDI0_TX2

AA7

FDI0_TX3

W7

FDI1_TX0

T4

FDI1_TX1

AA3

FDI1_TX2

AC8

FDI1_TX3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

EDP_COMPIO

AD2

EDP_ICOMPO

AG11

EDP_HPD#

AG4

EDP_AUX#

AF4

EDP_AUX

AC3

EDP_TX#0

AC4

EDP_TX#1

AE11

EDP_TX#2

AE7

EDP_TX#3

AC1

EDP_TX0

AA4

EDP_TX1

AE10

EDP_TX2

AE6

EDP_TX3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DMI

Intel(R) FDI

eDP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PCI EXPRESS -- GRAPHICS

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_IRCOMP_R

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

+1.05V_RUN_VTT

1 2

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(PCIE/DMI/FDI)

Austin 13

4 106Tuesday, February 26, 2013

A00

Vinaﬁx.com

SSID = CPU

5

D D

+1.05V_RUN_VTT

H_SNB_IVB#(22)

R502

1 2

56R2J-4-GP

C C

H_THERMTRIP#

DY

R501

1 2

62R2J-GP

R505 49D9R2F-GP

H_PROCHOT#

H_CATERR#

1 2

DY

Layout Note:

R501, R513 place near to CPU

CPU_DETECT#(78)

H_PECI(27)

H_PROCHOT#(27,40)

H_THERMTRIP#(28)

H_PM_SYNC(19)

H_CPUPW RGD(22,71)

B B

1 2

R512 0R0402-PAD-2-GPR512 0R0402-PAD-2-GP

R513

1 2

56R2J-4-GP

1 2

R514 0R0402-PAD-2-GPR514 0R0402-PAD-2-GP

1 2

R504 1KR2J-1-GPR504 1KR2J-1-GP

1 2

DY

R503 10KR2J-3-GP

PM_DRAM_PWRGD_CPU

4

CPU1B

F49

PROC_SELECT#

CPU_DETECT#_R

H_CATERR#

H_PECI

H_PROCHOT#_R

H_THERMTRIP#_R

H_PM_SYNC

H_CPUPW RGD_R

BUF_CPU_RST#

12

Layout Note:

C501 place near to CPU

C57

C49

A48

C45

D45

C48

B46

BE45

D44

C501

C501 SC100P50V2JN-3GP

SC100P50V2JN-3GP

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

IVY-BRIDGE-GP-NF

71.00IVY.A0U

3

2 OF 9

CLK_EXP_P

J3

MISC

CLOCKS

THERMAL

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

TDI

CLK_EXP_N

H2

CLK_DP_P_R

AG3

CLK_DP_N_R

AG1

DDR3_DRAMRST#_CPU

AT30

SM_RCOMP_0

BF44

SM_RCOMP_1

BE43

SM_RCOMP_2

BG43

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils. Trace width = 15mil

XDP_PRDY#

N53

XDP_PREQ#

N55

XDP_TCLK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI_R

M60

XDP_TDO_R

L59

XDP_DBRESET#_R

K58

XDP_OBS0_R

G58

XDP_OBS1_R

E55

XDP_OBS2_R

E59

XDP_OBS3_R

G55

XDP_OBS4_R

G59

XDP_OBS5_R

H60

XDP_OBS6_R

J59

XDP_OBS7_R

J61

RN503

1 2 3

4

SRN1KJ-7-GP

R507

4K99R2F-L-GP

1 2

R506 140R2F-GPR506 140R2F-GP

1 2

R508 25D5R2F-GPR508 25D5R2F-GP

1 2

R511 200R2F-L-GPR511 200R2F-L-GP

1 2

XDP_PRDY# (71)

XDP_PREQ# (71)

XDP_TMS (71) XDP_TRST# (71)

1 2

XDP

R531 0R2J-2-GP

1 2

XDP

R530 0R2J-2-GP

1 2

R529 0R2J-2-GPR529 0R2J-2-GP

1 2

XDP

R515 0R2J-2-GP

1 2

XDP

R516 0R2J-2-GP

1 2

XDP

R523 0R2J-2-GP

1 2

XDP

R524 0R2J-2-GP

1 2

XDP

R525 0R2J-2-GP

1 2

XDP

R526 0R2J-2-GP

1 2

XDP

R527 0R2J-2-GP

1 2

XDP

R528 0R2J-2-GP

2

CLK_EXP_P (20) CLK_EXP_N (20)

+1.05V_RUN_VTT

XDP_TDI XDP_TDO

XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7

+3.3V_ALW_PCH

A00_0206

S

G

SCD047U16V2KX-1-GP

12

R532 0R0402-PAD-2-GPR532 0R0402-PAD-2-GP

C505

R533 0R2J-2-GP

XDP_TDI (71) XDP_TDO (71)

XDP_DBRESET# (19,71)

XDP_OBS0 (71) XDP_OBS1 (71) XDP_OBS2 (71) XDP_OBS3 (71) XDP_OBS4 (71) XDP_OBS5 (71) XDP_OBS6 (71) XDP_OBS7 (71)

C504

SCD1U16V2KX-3GP

C504

SCD1U16V2KX-3GP

12

+1.35V_CPU_VDDQ

XDP_TDI XDP_TMS XDP_TDO

XDP_TRST# XDP_TCLK

Q511

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

1 2 1 2

DY

RN501

1

8

2

7

3

6

XDP

4 5

SRN51J-1-GP

RN502

1

4

2 3

XDP

SRN51J-GP

+1.35V_MEM

R535

R535 1KR2J-1-GP

1KR2J-1-GP

1 2

R534

1KR2J-1-GP

DDR_HVREF_RST_PCH (20) DDR_HVREF_RST_GATE (27)

DDR_HVREF_RST (12)XDP_TCLK (71)

1

+1.05V_RUN_VTT

DDR3_DRAMRST# (14,15)

U502

RUNPWROK(27,78)

PM_DRAM_PWRGD(19)

+3.3V_ALW_PCH

H_PECI

EC501

EC501 SC100P50V2JN-3GP

SC100P50V2JN-3GP

1 2

R519 200R2F-L-GPR519 200R2F-L-GP

Buffered reset to CPU

U501

1

B

PCH_PLTRST#(18)

A A

2

A GND3Y

74AHC1G09GW-GP

73.01G09.0AB

2ND = 73.01G09.BAH

3rd = 73.7SH09.0AG

Open Drain Buffer

VCC

5

BUFO_CPU_RST# BUF_CPU_RST#

4

+3.3V_RUN

12

+1.05V_RUN_VTT

12

C503

SCD1U16V2KX-3GP

C503

SCD1U16V2KX-3GP

R518

R518 75R2J-1-GP

75R2J-1-GP

1 2

R517 43R2J-GPR517 43R2J-GP

DY

12

1

B

2

A GND3Y

74AHC1G09GW-GP

73.01G09.0AB

2ND = 73.01G09.BAH

3rd = 73.7SH09.0AG

Open Drain Buffer

RUN_ON_CPU1.5VS3#(36)

5

VCC

RUNPWROK_AND PM_DRAM_PWRGD_CPU

4

DY

G

12

Q510_D

D

R522

R522 39R2J-L-GP

39R2J-L-GP

S

R520

200R2F-L-GP

1 2

R521 130R2F-1-GPR521 130R2F-1-GP

Q510

Q510 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

CPU(THERMAL/CLOCK/PM)

Taipei Hsien 221, Taiwan, R.O.C.

Austin 13

5 106Tuesday, February 26, 2013

A00

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

4 OF 9

CPU1D

AL4

AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13 BF12

BF8

BD10 BD14 BE13 BF16 BE17 BE18 BE21

BE14 BG14 BG18

BF19

BD50

BF48

BD53

BF52

BD49

BE49

BD54

BE53

BF56

BE57

BC59

AY60

BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59 AM60

AL59

AF61 AH60

BG39

BD42 AT22

AV43 BF40 BD45

CPU1D

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

DDR SYSTEM MEMORY B

3 OF 9

CPU1C

D D

C C

B B

M_A_DQ[63:0](14)

M_A_DQ[63:0]

M_A_BS0(14) M_A_BS1(14) M_A_BS2(14)

M_A_CAS#(14) M_A_RAS#(14) M_A_WE#(14)

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AJ6 AL6 AJ8

AL8 AL7

CPU1C

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

3 OF 9

SA_CK0

SA_CK#0

SA_CKE0

SA_CK1

SA_CK#1

SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIMA_CLK_DDR0 (14) M_A_DIMA_CLK_DDR#0 (14) M_A_DIMA_CKE0 (14)

M_A_DIMA_CLK_DDR1 (14) M_A_DIMA_CLK_DDR#1 (14) M_A_DIMA_CKE1 (14)

M_A_DIMA_CS#0 (14) M_A_DIMA_CS#1 (14)

M_A_DIMA_ODT0 (14) M_A_DIMA_ODT1 (14)

M_A_DQS#[7:0] (14)

M_A_DQS[7:0] (14)

M_A_A[15:0] (14)

M_B_DQ[63:0](15)

M_B_DQ[63:0]

M_B_BS0(15) M_B_BS1(15) M_B_BS2(15)

M_B_CAS#(15) M_B_RAS#(15) M_B_WE#(15)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

4 OF 9

SB_CK0 SB_CK#0 SB_CKE0

SB_CK1 SB_CK#1 SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIMB_CLK_DDR0 (15) M_B_DIMB_CLK_DDR#0 (15) M_B_DIMB_CKE0 (15)

M_B_DIMB_CLK_DDR1 (15) M_B_DIMB_CLK_DDR#1 (15) M_B_DIMB_CKE1 (15)

M_B_DIMB_CS#0 (15) M_B_DIMB_CS#1 (15)

M_B_DIMB_ODT0 (15) M_B_DIMB_ODT1 (15)

M_B_DQS#[7:0] (15)

M_B_DQS[7:0] (15)

M_B_A[15:0] (15)

IVY-BRIDGE-GP-NF

71.00IVY.A0U

A A

5

4

3

IVY-BRIDGE-GP-NF

71.00IVY.A0U

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

CPU (DDR)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

6 106

1

A00

Vinaﬁx.com

5

SSID = CPU

4

3

2

1

CFG6

CFG2

CFG5

DY

12

R701

R701 1KR2J-1-GP

1KR2J-1-GP

DY

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

R704

1KR2J-1-GP

PEG Static Lane Reversal

CFG[2]

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

PCIE Port Bifurcation Straps

CFG[6:5]

11:

1x16 PCI Express

2 x8 - PCI Express

10:

Reserved

01:

1x8, 2x4 PCI Express

00:

5 OF 9

CPU1E

D D

CFG0(71) CFG1(71) CFG2(71) CFG3(71) CFG4(71) CFG5(71) CFG6(71) CFG7(71) CFG8(71) CFG9(71) CFG10(71)

TP701TPAD14-OP-GP TP701TPAD14-OP-GP TP702TPAD14-OP-GP TP702TPAD14-OP-GP TP703TPAD14-OP-GP TP703TPAD14-OP-GP TP704TPAD14-OP-GP TP704TPAD14-OP-GP

TP715TPAD14-OP-GP TP715TPAD14-OP-GP TP716TPAD14-OP-GP TP716TPAD14-OP-GP

C C

B B

TP717TPAD14-OP-GP TP717TPAD14-OP-GP TP718TPAD14-OP-GP TP718TPAD14-OP-GP

TP719TPAD14-OP-GP TP719TPAD14-OP-GP TP720TPAD14-OP-GP TP720TPAD14-OP-GP

CFG11(71)

1 1 1 1

CFG16(71) CFG17(71)

VCC_VAL_SENSE

1

VSS_VAL_SENSE

1

VAXG_VAL_SENSE

1

VSSAXG_VAL_SENSE

1

VCC_DIE_SENSE

1

VSS_DIE_SENSE

1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

CPU1E

B50

CFG0

C51

CFG1

B54

CFG2

D53

CFG3

A51

CFG4

C53

CFG5

C55

CFG6

H49

CFG7

A55

CFG8

H51

CFG9

K49

CFG10

K53

CFG11

F53

CFG12

G53

CFG13

L51

CFG14

F51

CFG15

D52

CFG16

L53

CFG17

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

G48

RSVD47

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

RESERVED

5 OF 9

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

TP_DC_TEST_A4

A4 C4

DC_TEST_C4_D3

D3

TP_DC_TEST_D1

D1

TP_DC_TEST_A58

A58 A59

TP_DC_TEST_A59_C59

C59 A61

TP_DC_TEST_A61_C61

C61

TP_DC_TEST_D61

D61

TP_DC_TEST_BD61

BD61 BE61

TP_DC_TEST_BE59_BE61

BE59 BG61

DC_TEST_BG59_BG61

BG59

TP_DC_TEST_BG58

BG58

TP_DC_TEST_BG4

BG4 BG3

DC_TEST_BE3_BG3

BE3 BG1

DC_TEST_BE1_BG1

BE1

TP_DC_TEST_BD1

BD1

CLK_XDP_ITP (71) CLK_XDP_ITP# (71)

TP723 TPAD14-OP-GPTP723 TPAD14-OP-GP

1

TP724 TPAD14-OP-GPTP724 TPAD14-OP-GP

1

TP725 TPAD14-OP-GPTP725 TPAD14-OP-GP

1

TP726 TPAD14-OP-GPTP726 TPAD14-OP-GP

1

TP727 TPAD14-OP-GPTP727 TPAD14-OP-GP

1

TP728 TPAD14-OP-GPTP728 TPAD14-OP-GP

1

TP729 TPAD14-OP-GPTP729 TPAD14-OP-GP

1

TP730 TPAD14-OP-GPTP730 TPAD14-OP-GP

1

IVY-BRIDGE-GP-NF

71.00IVY.A0U

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

CPU (RESERVED)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

7 106

1

A00

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

POWER

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76

POWER

CORE SUPPLY

CPU1F

VCC_CORE

D D

12

C801

C821

DY

SC22U6D3V5MX-2GP

12

C811

SC22U6D3V5MX-2GP

12

C825

C830

SC22U6D3V5MX-2GP

C C

B B

12

C802

C803

SC22U6D3V5MX-2GP

VCC Output Decoupling Recommendation:

1.9m ohm loadline design:(for SV) 470u x 4(Remove) 22u x 20(0805)

2.2u x 35(0402)

2.9m ohm loadline design:(for ULV/LV) 330u x 3(Remove) 22u x 12(0805)

2.2u x 16(0402)

12

SC22U6D3V5MX-2GP

12

C812

SC22U6D3V5MX-2GP

12

C831

SC22U6D3V5MX-2GP

12

C814

SC22U6D3V5MX-2GP

12

C804

C822

C813

12

SC22U6D3V5MX-2GP

C805

C806

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

DY

C832

SC10U6D3V5KX-1GP

12

C823

C824

SC22U6D3V5MX-2GP

12

C843

C847

DY

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

12

C815

C817

C819

DY

SC10U6D3V3MX-GP

SC10U6D3V5KX-1GP

12

C807

C808

SC22U6D3V5MX-2GP

12

C828

C816

SC22U6D3V5MX-2GP

12

C833

DY

SC10U6D3V3MX-GP

SC22U6D3V5MX-2GP

C818

SC22U6D3V3MX-1-GP

12

C809

SC22U6D3V5MX-2GP

22 uf x24 10 uf x7

2.2uf x2

12

C827

SC2D2U6D3V2MX-GP

12

C810

SC10U6D3V5KX-1GP

12

C820

SC22U6D3V5MX-2GP

12

C840

C829

DY

SC2D2U6D3V2MX-GP

SC10U6D3V3MX-GP

33A

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

IVY-BRIDGE-GP-N F

71.00IVY.A0U

6 OF 9

VCCIO1 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29

VCCIO30 VCCIO31 VCCIO32

PEG IO AND DDR IO

VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42 VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE1 VCCPQE2

RAILS

VIDALERT#

VIDSCLK VIDSOUT

SVID QUIET

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

H_CPU_SVIDALR T# H_CPU_SVIDC LK H_CPU_SVIDD AT

VCCSENSE VSSSENSE

12

DY

H_SNB_IVB#_PW RCTRL

+V1.05S_VCCPQE _R

C862

SC1U6D3V2KX-GPDYC862

SC1U6D3V2KX-GP

12

DY

12

C871

DY

SC22U6D3V5MX-2GP

Added, cause the

1.05V far away CPU

C885

SC1U6D3V2KX-GPDYC885

SC1U6D3V2KX-GP

C883

SC1U6D3V2KX-GPDYC883

SC1U6D3V2KX-GP

12

DY

1

1 2

R812 0R0402-PAD-2-GPR812 0R0402-PAD-2-GP

12

C826

C826 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

+1.05V_RUN_VT T

12

R807

R807 10R2F-L-GP

10R2F-L-GP

12

R806

R806 10R2F-L-GP

10R2F-L-GP

C869

SC1U6D3V2KX-GPDYC869

SC1U6D3V2KX-GP

C866

SC1U6D3V2KX-GPDYC866

C864

SC1U6D3V2KX-GPDYC864

SC1U6D3V2KX-GP

C872

SC22U6D3V5MX-2GP

C884

SC1U6D3V2KX-GPDYC884

SC1U6D3V2KX-GP

R803

R803 43R2J-GP

43R2J-GP

1 2

SC1U6D3V2KX-GP

C865

SC1U6D3V2KX-GPDYC865

SC1U6D3V2KX-GP

12

DY

C874

SC1U6D3V2KX-GP

C874

SC1U6D3V2KX-GP

12

C873

SC22U6D3V5MX-2GP

C886

SC1U6D3V2KX-GP

C886

SC1U6D3V2KX-GP

C888

SC1U6D3V2KX-GP

C888

SC1U6D3V2KX-GP

12

C895

SC10U6D3V3MX-GPDYC895

SC10U6D3V3MX-GP

12

DY

TP801 TP AD14-OP-GPTP801 TPAD14-OP- GP

75R2F-2-GP

VCCIO_SENSE (45) VSSIO_SENSE ( 45)

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

R805

12

DY

12

DY

12

DY

C876

SC1U6D3V2KX-GP

C876

SC1U6D3V2KX-GP

C879

SC10U6D3V3MX-GP

C879

SC10U6D3V3MX-GP

C887

SC1U6D3V2KX-GPDYC887

SC1U6D3V2KX-GP

C897

SC10U6D3V3MX-GPDYC897

SC10U6D3V3MX-GP

+1.05V_RUN_VT T+1.05V_R UN_VTT

12

VCC_CORE

12

C867

SC1U6D3V2KX-GPDYC867

SC1U6D3V2KX-GP

12

DY

C875

SC1U6D3V2KX-GP

C875

SC1U6D3V2KX-GP

12

C880

SC10U6D3V3MX-GP

C880

SC10U6D3V3MX-GP

12

C889

SC1U6D3V2KX-GPDYC889

SC1U6D3V2KX-GP

12

DY

C893

SC10U6D3V3MX-GP

C893

SC10U6D3V3MX-GP

12

R804

R804 130R2F-1-GP

130R2F-1-GP

R801

R801 100R2F-L1-GP- U

100R2F-L1-GP- U

R802

R802 100R2F-L1-GP- U

100R2F-L1-GP- U

DY

8.5A

C868

SC1U6D3V2KX-GPDYC868

SC1U6D3V2KX-GP

12

DY

C877

SC1U6D3V2KX-GP

C877

SC1U6D3V2KX-GP

12

C881

SC10U6D3V3MX-GPDYC881

SC10U6D3V3MX-GP

12

C890

SC1U6D3V2KX-GP

C890

SC1U6D3V2KX-GP

12

DY

C894

SC10U6D3V3MX-GPDYC894

SC10U6D3V3MX-GP

12

DY

+1.05V_RUN_VT T

C870

SC1U6D3V2KX-GPDYC870

SC1U6D3V2KX-GP

12

C878

SC1U6D3V2KX-GP

C878

SC1U6D3V2KX-GP

12

C882

SC10U6D3V3MX-GP

C882

SC10U6D3V3MX-GP

12

C891

SC1U6D3V2KX-GPDYC891

SC1U6D3V2KX-GP

12

C896

SC10U6D3V3MX-GPDYC896

SC10U6D3V3MX-GP

12

Layout Note:

R803, R804, R805 need close to CPU Alert# signal must be routed between the Clock and Data lines to reduce the cross talk between them

VR_SVID_ALERT# (42)

H_CPU_SVIDC LK (42)

H_CPU_SVIDD AT (42)

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

+1.05V_RUN_VT T

C892

SC1U6D3V2KX-GPDYC892

SC1U6D3V2KX-GP

12

DY

VCCSENSE (42) VSSSENSE (42)

22 uf x3 10 ufx9 1 uf x23

Voltage Rail

VCC_CORE(ULV) VAXG(ULV) VCCIO VDDQ 1.5 VCCSA VCCPLL

VCCIO Output Decoupling Recommendation: 330u x 2(Remove) 10u x 10(0603) 1u x 26(0402)

VCCPQ Output Decoupling Recommendation: 1u x 1(0402)

Need place Pull Hi at IMVP page

Voltage(V)

0.3~1.52 0~1.52

1.05

0.9

1.8

Iccmax(A)

33 33

8.5 5 4

1.2

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Febr uary 26, 2013

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU (VCC_CORE)

Austin 13

1

8 106

A00

Vinaﬁx.com

5

4

3

2

1

SSID = CPU

Layout Note:

POWER

CPU1G

VCC_GFXCO RE

D D

C C

B B

VCCAXG Output Decoupling Recommendation:

3.9m ohm loadline design:(for GT2) 470u x 2(remove) 22u x 6(0805) 10u x 6(0603) 1u x 11(0402)

4.6m ohm loadline design:(for GT1) 330u x 2(remove) 22u x 5(0805) 10u x 6(0603) 1u x 6(0402)

VCCPLL Output Decoupling Recommendation: 330u x 1(Remove) 1u x 2(0402)

VCCSA Output Decoupling Recommendation: 330u x 1(Remove) 10u x 5(0603) 1u x 5(0402)

22 uf x17 1 uf x7

12

C901

12

C955

12

C906

12

Layout Note:

1. PH/PL resisors place close CPU

2. SENSE signal recommend differential routing

12

C902

C903

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C923

SC22U6D3V5MX-2GP

12

C907

C908

SC22U6D3V5MX-2GP

12

C912

C914

C913

SC1U6D3V2KX-GP

+VCC_SA

12

C905

C904

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C921

C920

SC22U6D3V5MX-2GP

12

VCC_AXG_SEN SE(42) VSS_AXG_SENSE(42)

C922

SC10U6D3V5KX-1GP

12

C909

C910

SC22U6D3V5MX-2GP

12

C915

C916

SC1U6D3V2KX-GP

6A

C930

SC10U6D3V3MX-GPDYC930

SC10U6D3V3MX-GP

C929

SC10U6D3V3MX-GPDYC929

SC10U6D3V3MX-GP

12

DY

C935

SC1U6D3V2KX-GP

C935

SC1U6D3V2KX-GP

12

SC22U6D3V5MX-2GP

C917

SC1U6D3V2KX-GP

+1.8V_RUN

12

C934

12

33A

12

C919

C911

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C918

SC1U6D3V2KX-GP

VCC_GFXCO RE

12

R903

R903 100R2F-L1-GP- U

100R2F-L1-GP- U

VCC_AXG_SEN SE

VSS_AXG_SENSE

12

R904

R904 100R2F-L1-GP- U

100R2F-L1-GP- U

1.2A

C925

SC1U6D3V2KX-GP

C925

SC1U6D3V2KX-GP

C924

SC1U6D3V2KX-GPDYC924

SC1U6D3V2KX-GP

12

DY

C927

SC10U6D3V3MX-GPDYC927

SC10U6D3V3MX-GP

C926

SC10U6D3V3MX-GPDYC926

C928

SC10U6D3V3MX-GPDYC928

SC10U6D3V3MX-GP

DY

SC1U6D3V2KX-GP

DY

SC10U6D3V3MX-GP

12

C933

12

DY

SC1U6D3V2KX-GPDYC933

SC1U6D3V2KX-GP

C932

SC1U6D3V2KX-GPDYC932

SC1U6D3V2KX-GP

12

DY

CPU1G

AA46

VAXG1

AB47

VAXG2

AB50

VAXG3

AB51

VAXG4

AB52

VAXG5

AB53

VAXG6

AB55

VAXG7

AB56

VAXG8

AB58

VAXG9

AB59

VAXG10

AC61

VAXG11

AD47

VAXG12

AD48

VAXG13

AD50

VAXG14

AD51

VAXG15

AD52

VAXG16

AD53

VAXG17

AD55

VAXG18

AD56

VAXG19

AD58

VAXG20

AD59

VAXG21

AE46

VAXG22

N45

VAXG23

P47

VAXG24

P48

VAXG25

P50

VAXG26

P51

VAXG27

P52

VAXG28

P53

VAXG29

P55

VAXG30

P56

VAXG31

P61

VAXG32

T48

VAXG33

T58

VAXG34

T59

VAXG35

T61

VAXG36

U46

VAXG37

V47

VAXG38

V48

VAXG39

V50

VAXG40

V51

VAXG41

V52

VAXG42

V53

VAXG43

V55

VAXG44

V56

VAXG45

V58

VAXG46

V59

VAXG47

W50

VAXG48

W51

VAXG49

W52

VAXG50

W53

VAXG51

W55

VAXG52

W56

VAXG53

W61

VAXG54

Y48

VAXG55

Y61

VAXG56

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL1

BC1

VCCPLL2

BC4

VCCPLL3

L17

VCCSA1

L21

VCCSA2

N16

VCCSA3

N20

VCCSA4

N22

VCCSA5

P17

VCCSA6

P20

VCCSA7

R16

VCCSA8

R18

VCCSA9

R21

VCCSA10

U15

VCCSA11

V16

VCCSA12

V17

VCCSA13

V18

VCCSA14

V21

VCCSA15

W20

VCCSA16

C931

SC1U6D3V2KX-GPDYC931

SC1U6D3V2KX-GP

IVY-BRIDGE-GP-N F

71.00IVY.A0U

POWER

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

DDR3 - 1.5V RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID0 VCCSA_VID1

lines

SM_VREF

+V_SM_VREF_CNT should have 10 mil trace width

7 OF 9

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26

VCCDQ1 VCCDQ2

+V_SM_VREF_C NT

AY43

+DIMM0_1_VREF_CP U

BE7

+DIMM0_1_CA_CPU

BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

TP_VDDQ_SEN SE

BC43

TP_VDDQ_VSS

BA43

U10

VCCSA_SEL0

D48

VCCSA_SEL1

D49

C944

12

1KR2J-1-GP

SC1U6D3V2KX-GP

12

DY

C954

SC1U6D3V2KX-GP

C954

SC1U6D3V2KX-GP

12

1 1

12

R911

+DIMM0_1_VREF_CP U +DIMM0_1_CA_CPU

5A

C945

SC1U6D3V2KX-GPDYC945

SC1U6D3V2KX-GP

C946

SC1U6D3V2KX-GPDYC946

SC1U6D3V2KX-GP

12

DY

C936

SC10U6D3V3MX-GPDYC936

SC10U6D3V3MX-GP

12

DY

VDDQ Output Decoupling Recommendation: 330u x 1(Remove) 10u x 8(0603) 1u x 10(0402)

VCCDQ Output Decoupling Recommendation: 1u x 1(0402)

1 2

R909 0R0402-PAD-2-GPR909 0R0402-PAD-2-GP

TP901 TP AD14-OP-GPTP901 TPAD14-OP- GP TP902 TP AD14-OP-GPTP902 TPAD14-OP- GP

VCCSA_SENS E (48)

VCCSA_SEL0 ( 48) VCCSA_SEL1 ( 48)

12

R910

R910 1KR2J-1-GP

1KR2J-1-GP

C947

SC1U6D3V2KX-GPDYC947

SC1U6D3V2KX-GP

12

DY

C937

SC10U6D3V3MX-GP

C937

SC10U6D3V3MX-GP

12

10 uf x8 1 uf x10

C948

SC1U6D3V2KX-GPDYC948

SC1U6D3V2KX-GP

12

DY

C938

SC10U6D3V3MX-GPDYC938

SC10U6D3V3MX-GP

12

DY

+1.35V_CPU_VD DQ+V1.35S_VCCD_ Q

C949

SC1U6D3V2KX-GPDYC949

SC1U6D3V2KX-GP

12

DY

C939

SC10U6D3V3MX-GPDYC939

SC10U6D3V3MX-GP

12

Voltage Rail

VCC_CORE(ULV) VAXG(ULV) VCCIO VDDQ 1.5 VCCSA VCCPLL

C951

SC1U6D3V2KX-GPDYC951

SC1U6D3V2KX-GP

C950

SC1U6D3V2KX-GPDYC950

SC1U6D3V2KX-GP

12

DY

C941

SC10U6D3V3MX-GP

C941

SC10U6D3V3MX-GP

C940

SC10U6D3V3MX-GP

C940

SC10U6D3V3MX-GP

12

DY

VCCSA Power Select

Voltage(V)

0.9

0.85

0.775

0.75

Voltage(V)

0.3~1.52 0~1.52

C952

SC1U6D3V2KX-GP

C952

SC1U6D3V2KX-GP

12

DY

C942

SC10U6D3V3MX-GPDYC942

SC10U6D3V3MX-GP

VID[0] VID[1]

1.05

0.9

1.8

+1.35V_CPU_VD DQ

C953

SC1U6D3V2KX-GPDYC953

SC1U6D3V2KX-GP

DY

3

0

0 1

Iccmax(A)

33 33

8.5 5 6

1.2

+1.35V_MEM+1.35V_CPU_VD DQ

C957

1 2

SCD1U16V2KX- 3GP

C958

PTC901

ST330U2D5VDM-24-GP-UDYPTC901

ST330U2D5VDM-24-GP-U

12

Layout Note:

For S3 reduction circuit's 1D5V return pass.

C958

1 2

SCD1U16V2KX- 3GP

C959

1 2

SCD1U16V2KX- 3GP

C960

1 2

SCD1U16V2KX- 3GP

0

01

11

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Febr uary 26, 2013

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

CPU (VCC_GFXCORE)

Austin 13

1

9 106

A00

Vinaﬁx.com

5

SSID = CPU

CPU1H

4

8 OF 9

3

CPU1I

2

9 OF 9

1

A13

VSS1

A17

VSS2

A21

VSS3

A25

VSS4

D D

C C

B B

A A

A28 A33 A37 A40 A45 A49 A53

AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56

AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AC6 AD17 AD20

AD4 AD61 AE13

AE8

AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AJ7

AK1

AK52

AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

A9

VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

VSS

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9

C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6

G61

H10 H14 H17 H21

H4 H53 H58

J1 J49 J55

K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249

VSS

NCTF TEST PINA5,A57,BC61,BG5

NCTF

VSS_NCTF_1#A5

VSS_NCTF_2#A57

VSS_NCTF_3#BC61

VSS_NCTF_8#BG5

VSS_NCTF_9#BG57

VSS_NCTF_10#C3

VSS_NCTF_13#E1

VSS_NCTF_14#E61

BG57,C3,E1,E61

VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6

VSS_NCTF_7 VSS_NCTF_11 VSS_NCTF_12

VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59

A5 A57 BC61 BG5 BG57 C3 E1 E61

BD3 BD59 BE4 BE58 C58 D59

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

IVY-BRIDGE-GP-NF

71.00IVY.A0U

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

CPU (VSS)

Austin 13

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

10 106

1

A00

Vinaﬁx.com

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

XDP

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

11 106

1

A00

Vinaﬁx.com

5

4

3

2

1

SSID = MEMORY

D D

R1203

R1203 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q1201

AP2302GN-GP

DY

G

Q1202

G

DS

84.02302.A31

2nd = 84.02302.B31

3rd = 84.02300.D31

DS

84.02302.A31

2nd = 84.02302.B31

3rd = 84.02300.D31

+V_DDR_REFA_M3+DIMM0_1_VREF_CPU

+V_DDR_REFB_M3

C C

B B

From CPU BE7

From CPU BG7

DDR_HVREF_RST(5)

+DIMM0_1_CA_CPU

DDR_HVREF_RST

R1202

R1202 0R2J-2-GP

0R2J-2-GP

1 2

AP2302GN-GP

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DDRM1 & M3 solution

Size Document Number Rev

A3

Date: Sheet of

DDRM1 & M3 solution

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

12 106Tuesday, February 26, 2013

1

A00

Vinaﬁx.com

5

D D

4

3

2

1

C C

B B

A A

(Blanking)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

(Reserved)

Size Document Number Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

(Reserved)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

13 106Tuesday, February 26, 2013

1

A00

Vinaﬁx.com

5

SSID = MEMORY

M_A_A[15:0](6)

D D

Layout Note:

Place these caps close to VREF_CA

Layout Note:

Place these caps close to VREF_DQ

C C

+0.675V_DDR_VT T

12

B B

12

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

12

C1420

C1418

C1419

SC1U6D3V2KX-GP

C1418

DY

SC1U6D3V2KX-GP

M_A_BS2(6) M_A_BS0(6)

M_A_BS1(6)

M_A_DQ[63:0](6)

Layout Note:

Place these caps close to VTT1 and VTT2.

M_A_DQS#[7:0](6)

M_A_DQS[7:0](6)

M_A_DIMA_ODT0(6) M_A_DIMA_ODT1(6)

M_VREF_CA_D IMMA M_VREF_DQ_D IMMA

DDR3_DR AMRST#(5, 15)

+0.675V_DDR_VT T

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

X01 12/15 X01 12/02

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P- 106-GP

62.10017.X31

2ND = 62.10024.G11

3RD = 62.10017.M41

RAS# CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

4

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMA

197

SA0

SA1_DIMA

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

+1.35V_MEM

M_A_RAS# (6) M_A_WE# (6) M_A_CAS# (6)

M_A_DIMA_CS#0 (6) M_A_DIMA_CS#1 (6)

M_A_DIMA_CKE0 (6) M_A_DIMA_CKE1 (6)

M_A_DIMA_CLK_DD R0 (6) M_A_DIMA_CLK_DD R#0 (6)

M_A_DIMA_CLK_DD R1 (6) M_A_DIMA_CLK_DD R#1 (6)

PCH_SMBDAT A (15,20,66,71,79,82) PCH_SMBCLK (15,20,66,71,79,82)

+3.3V_RUN

12

C1401

C1401 SCD1U16V2KX- 3GP

SCD1U16V2KX- 3GP

DY

Layout Note:

Place these Caps near SO-DIMMA.

+1.35V_MEM

3

SA0_DIMA SA1_DIMA

12

R1401

R1402

0R0402-PAD-2- GP

12

DY

12

DY

TC1401

C1403

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

12

C1407

C1406

SC10U6D3V5KX-1GP

R1402 0R0402-PAD-2- GP

0R0402-PAD-2- GP

EC1407

EC1406

SCD1U16V2KX-3GP

EC1406

SCD1U16V2KX-3GP

12

C1404

SC10U6D3V5KX-1GP

12

C1416

SC1U6D3V2KX-GP

12

C1405

SC10U6D3V5KX-1GP

C1417

SC1U6D3V2KX-GP

Note: SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

SCD1U16V2KX-3GP

EC1408

SCD1U16V2KX-3GP

EC1408

SCD1U16V2KX-3GP

12

2

1

+V_DDR_RE FA_M3

1 2

R1405

0R0402-PAD-2- GP

+V_DDR_RE F

A A

1 2

R1408

0R0402-PAD-2- GP

C1412

12

SCD1U16V2KX-3GP

M_VREF_CA_D IMMA

12

DY

5

C1430

SCD1U16V2KX-3GP

C1430

SCD1U16V2KX-3GP

12

C1426

SC2D2U10V3KX-1GP

+V_DDR_RE F

0R0402-PAD-2- GP

1 2

R1406

0R0402-PAD-2- GP

C1411

12

Populate R1406, De-Populate R1405 for Intel DDR3 VREFDQ multiple methods M1

M_VREF_DQ_D IMMA

SCD1U16V2KX-3GP

C1429

SCD1U16V2KX-3GP

C1429

SCD1U16V2KX-3GP

12

DY

C1423

SC2D2U10V3KX-1GP

4

PopulateR1405, De-Populate R1406 for Intel DDR3 VREFDQ multiple methods M3

3

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Febr uary 26, 2013

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM1

Austin 13

1

14 106

A00

Vinaﬁx.com

5

SSID = MEMORY

D D

Layout Note:

Place these caps close to VREF_CA

C C

+0.675V_DDR_VT T

12

C1518

DY

SC1U6D3V2KX-GP

B B

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

12

C1519

C1521

SC1U6D3V2KX-GP

M_B_A[15:0](6)

M_B_BS2(6) M_B_BS0(6)

M_B_BS1(6)

M_B_DQ[63:0](6)

Layout Note:

Place these caps close to VREF_DQ

Layout Note:

Place these caps close to VTT1 and VTT2.

M_B_DQS#[7:0](6)

M_B_DQS[7:0](6)

M_B_DIMB_ODT0(6) M_B_DIMB_ODT1(6)

M_VREF_CA_D IMMB M_VREF_DQ_D IMMB

DDR3_DR AMRST#(5, 14)

+0.675V_DDR_VT T

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

107

119

109 108

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

135 152 169 186

137 154 171 188

116 120

126

203 204

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9 A10/AP

84

A11

83

A12 A13

80

A14

78

A15

79

A16/BA2 BA0

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3# DQS4# DQS5# DQS6# DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

1

VREF_DQ

30

RESET#

VTT1 VTT2

DDR3-204P- 108-GP

62.10017.X41

2ND = 62.10017.V51

3rd = 62.10017.M51

4

EVENT#

VDDSPD

NC#/TEST

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104 11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198 199

SA0_DIMB

197

SA0

SA1_DIMB

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

+1.35V_MEM

M_B_RAS# (6) M_B_WE# (6) M_B_CAS# (6)

M_B_DIMB_CS#0 (6) M_B_DIMB_CS#1 (6)

M_B_DIMB_CKE0 (6) M_B_DIMB_CKE1 (6)

M_B_DIMB_CLK_DD R0 (6) M_B_DIMB_CLK_DD R#0 (6)

M_B_DIMB_CLK_DD R1 (6) M_B_DIMB_CLK_DD R#1 (6)

PCH_SMBDAT A (14,20,66,71,79,82) PCH_SMBCLK (14,20,66,71,79,82)

C1501

12

DY

Layout Note:

Place these Caps near SO-DIMMA.

SCD1U16V2KX-3GPDYC1501

SCD1U16V2KX-3GP

+1.35V_MEM

+3.3V_RUN

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

+3.3V_RUN

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

SA1_DIMB SA0_DIMB

12

R1502

0R0402-PAD-2- GP

X03 2/21

EC1511

SCD1U16V2KX-3GP

EC1511

SCD1U16V2KX-3GP

12

TC1502

C1508

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

12

C1512

C1513

SC10U6D3V5KX-1GP

12

C1510

C1509

SC10U6D3V5KX-1GP

12

C1528

C1530

SC1U6D3V2KX-GP

EC1510

SCD1U16V2KX-3GP

EC1510

SCD1U16V2KX-3GP

EC1509

SCD1U16V2KX-3GP

EC1509

SCD1U16V2KX-3GP

12

2

1

+V_DDR_RE FB_M3

1 2

R1504

0R0402-PAD-2- GP

+V_DDR_RE F

1 2

R1503

0R0402-PAD-2- GP

A A

0R0402-PAD-2- GP

M_VREF_CA_D IMMB

C1413

SCD1U16V2KX-3GP

C1413

SCD1U16V2KX-3GP

12

C1431

SCD1U16V2KX-3GP

C1431

12

DY

SCD1U16V2KX-3GP

12

C1427

SC2D2U10V3KX-1GP

5

+V_DDR_RE F

0R0402-PAD-2- GP

1 2

R1505

0R0402-PAD-2- GP

C1414

12

Populate R1504, De-Populate R1505 for Intel DDR3 VREFDQ multiple methods M1

M_VREF_DQ_D IMMB

C1432

SCD1U16V2KX-3GP

C1432

SCD1U16V2KX-3GP

12

DY

SCD1U16V2KX-3GP

12

C1428

SC2D2U10V3KX-1GP

4

PopulateRR1505, De-Populate R1504 for Intel DDR3 VREFDQ multiple methods M3

3

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Febr uary 26, 2013

Date: Sheet of

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

DDR3-SODIMM2

Austin 13

1

15 106

A00

Vinaﬁx.com

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 106Tuesday, February 26, 2013

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

D D

+3.3V_RUN

RN1701

1 2 3

DY

SRN2K2J-1-GP

100KR2J-1-GP

R1703

C C

+3.3V_RUN

RN1707

SRN2K2J-1-GP

B B

4

1

2 3

678

4 5

L_CTRL_DATA

4

L_CTRL_CLK

ENVDD_PCH

12

Layout Note:

Place near PCH; trace to trace spacing=20mil

CRT_DDC_DATA

CRT_DDC_CLK

CRT_BLUE CRT_GREEN CRT_RED

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

Layout Note:

Close to PCH side

PANEL_BKEN_PCH(49) ENVDD_PCH(49,78)

L_BKLT_CTRL(49) LVDS_DDC_CLK_R(49)

LVDS_DDC_DATA_R(49)

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

Layout Note:

LVDS signal trace length max 4000mil

CRT_HSYNC_CON_1(82) CRT_VSYNC_CON_1(82)

Layout Note:

Place near PCH; trace to trace spacing=30mil

LVDSA_CLK#(49) LVDSA_CLK(49)

LVDSA_DATA0#(49) LVDSA_DATA1#(49) LVDSA_DATA2#(49)

LVDSA_DATA0(49) LVDSA_DATA1(49) LVDSA_DATA2(49)

CRT_DDC_CLK(82) CRT_DDC_DATA(82)

TP1701TPAD14-OP-GP TP1701TPAD14-OP-GP

CRT_BLUE(82) CRT_GREEN(82) CRT_RED(82)

1 2 3

SRN33J-5-GP-U

1KR2F-L-GP

RN1708

R1702

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

CRT_HSYNC

4

CRT_VSYNC

DAC_IREF_R

12

M45 P45

K47

P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47

AJ48

AN47 AM49 AK49

AJ47

AF40 AF39

AH45 AH47

AF49 AF45

AH43 AH49

AF47 AF43

N48 P49

M40

M47 M49

J47

T40

T45

T49

T39

T43 T42

PCH1D

L_BKLTEN L_VDD_EN

L_BKLTCTL L_DDC_CLK

L_DDC_DATA L_CTRL_CLK

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

PANTHER-GP-NF

71.PANTH.00U

LVDS

Digital Display Interface

CRT

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J-1-GP

RN1706

+3.3V_RUN

4

1

2 3

Layout Note:

Close HDMI port

HDMI_DDC_CLK (51) HDMI_DDC_DATA (51)

HDMI_PCH_DET (51) HDMI_DATA2_R# (82)

HDMI_DATA2_R (82) HDMI_DATA1_R# (82) HDMI_DATA1_R (82) HDMI_DATA0_R# (82) HDMI_DATA0_R (82) HDMI_CLK_R# (82) HDMI_CLK_R (82)

Layout Note:

HDMI trace length to DC CAP. max 10000mil

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

PCH (LVDS/CRT/DDI)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

17 106

1

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

5 OF 10

PCH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

D D

USB3.0/2.0 Mapping Table

USB 3.0 Port USB 2.0 port Port 1 Port 2 Port 3

+3.3V_RUN

RN1803

SRN10KJ-6-GP

8 7

C C

6

1 2 3 45

1 2

1KR2F-L-GP

PCI_REQ1# BT_DET# LCD_CBL_DET# PCIE_MCARD2_DET#

R1803

DY

Port 4

BBS_BIT1

Port 0 Port 1 Port 2 Port 3

Layout Note:

Trace Length : PCH ~~9000mil~~Cap~~1000mil~~CONN

USB3_RX2_N(82) USB3_RX3_N(82)

USB3_RX2_P(82) USB3_RX3_P(82)

USB3_TX2_N(82) USB3_TX3_N(82)

USB3_TX2_P(82) USB3_TX3_P(82)

USB3_RX2_N USB3_RX3_N

USB3_RX2_P USB3_RX3_P

USB3_TX2_N USB3_TX3_N

USB3_TX2_P USB3_TX3_P

BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5 Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

TP5 TP6 TP7 TP8 TP9 TP10 TP11

H3

TP12 TP13 TP14 TP15 TP16 TP17

L24

TP18 TP19 TP20

RSVD

TP21 TP22 TP23 TP24

USB3RN1 USB3RN2 USB3RN3 USB3RN4 USB3RP1 USB3RP2 USB3RP3 USB3RP4 USB3TN1 USB3TN2 USB3TN3 USB3TN4 USB3TP1 USB3TP2 USB3TP3 USB3TP4

RSVD

Boot Bios Strap

INT_PIRQA#

GNT1#/GPIO51

0 0

0

B B

1

1 2

DY

R1815

R1815 1KR2F-L-GP

1KR2F-L-GP

1

0

1

PCI_GNT3#

Boot BIOS LocationSATA1GP/GPIO19

LPC

Reserved

SPI(Default)

HDD_FALL_INT(79)

R1808

1 2

0R0402-PAD-2-GP

PCIE_MCARD2_DET#(66)

LCD_CBL_DET#(49)

CAM_MIC_CBL_DET#(49)

A16 Swap Override jumper

R1817 22R2J-2-GPR1817 22R2J-2-GP

1 2

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806

R1806 22R2J-2-GP

22R2J-2-GP

EC1804

1 2

SC4D7P50V2CN-1GP

PLT_RST# (27,66,71,77,78,82)

PLTRST_MMI# (32) PLTRST_XDP# (71)

CLK_PCI_LOOPBACK(20)

+3.3V_RUN

CLK_PCI_5048(78) CLK_PCI_MEC(27)

12

C1802

C1802 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

0R0402-PAD-2-GP

XDP

DY

R1814

12

R18130R2J-2-GP

12

4

PCI_GNT#3 Low = A16 swap override/Top-Block

A A

Swap Override enabled High = Default

PCH_PLTRST#(5)

PCH_PLTRST#

5

U1801

1

A

2

B GND3Y

U74LVC1G08G-AL5-R-GP-U

73.01G08.EHG

2ND = 73.7SZ08.DAH

3rd = 73.7SZ08.EAH

VCC

5

4

INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ1#

BT_DET# BBS_BIT1 PCI_GNT3#

LCD_CBL_DET# PCH_GPIO3 CAM_MIC_CBL_DET# FFS_PCH_INT

TP1802TP1802

1

PCH_PLTRST#

PCI_5048

PCI_MEC

CLK_PCI_LOOPBACK_R

PCI_PME#

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1#/GPIO50

C44

REQ2#/GPIO52

E40

REQ3#/GPIO54

D47

GNT1#/GPIO51

E42

GNT2#/GPIO53

F46

GNT3#/GPIO55

G42

PIRQE#/GPIO2

G40

PIRQF#/GPIO3

C42

PIRQG#/GPIO4

D44

PIRQH#/GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-GP-NF

+3.3V_ALW_PCH

3

+3.3V_RUN

PCI

USB_OC#1_R USB_OC#3 SIO_EXT_SMI#

INT_PIRQB# PCH_GPIO3

USB

5 OF 10

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

USBRBIAS#

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

1 2 3 4 5 6

C33

B33

USBRBIAS

A14 K20 B17 C16 L16 A16 D14 C14

RN1802

RN1802 SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

1 2 3 4 5 6

RN1801

RN1801 SRN8K2J-2-GP-U

SRN8K2J-2-GP-U

USB2.0 Signal Group

USB_RBIAS

USB_OC#0_R USB_OC#1_R USB_OC#2 USB_OC#3 USB_OC#4

USB_OC#5 USB_OC#6

10

USB_OC#6

9

USB_OC#4

8

USB_OC#5USB_OC#0_R

7

USB_OC#2

10

INT_PIRQD#

9 8

INT_PIRQC#INT_PIRQA#

7

CAM_MIC_CBL_DET#

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

R1809 0R0402-PAD-2-GPR1809 0R0402-PAD-2-GP R1812 0R0402-PAD-2-GPR1812 0R0402-PAD-2-GP

+3.3V_ALW_PCH

+3.3V_RUN

2

USB Table

Pair

USB0(Left side-HDMI/B)

0

USB1(Right side-IO/B, for USB3.0)

1

USB2(Right side-IO/B, for USB3.0)

2

NC

3

WLAN

USB_PN0 (82) USB_PP0 (82) USB_PN1 (82) USB_PP1 (82) USB_PN2 (82) USB_PP2 (82)

USB_PN4 (82) USB_PP4 (82) USB_PN5 (66) USB_PP5 (66)

USB_PN12 (49) USB_PP12 (49)

1 2 1 2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

4

WWAN

5

NC

6

NC

7

NC

8

NC

9

NC

10

NC

11

CAMERA

12

NC

13

1. USB Ext. port 9 (HS) External debug port use on Chief River platform.

2. 2011 July; Microsoft will support USB3.0 debug--> Port1 useable.

Layout Note:

1. USBRBIAS/# use 50ohm single-ended impedance spacing to other signal=15mil

2. Length < 500mil

PCH (PCI/USB/NVRAM)

Austin 13

Tuesday, February 26, 2013

Austin 13

Device

USB_OC#0 (82) USB_OC#1 (82)

SIO_EXT_SMI# (27)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

18 106

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

RN1901

8 7 6

SRN10KJ-6-GP

DY

DY DY

DY

PCH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

PANTHER-GP-NF

71.PANTH.00U

1 2 3 45

12 12

PCH_BATLOW# PM_RI# ME_SUS_PWR_ACK PCH_PCIE_WAKE#

SIO_SLP_LAN# SUS_STAT#/LPCPD#

DMI

SUS_STAT#/GPIO61

System Power Management

DMI_RXN[3:0](4)

D D

Layout Note:

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

C C

B B

Sequence: S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

A A

SUSACK#(78)

+3.3V_RUN

XDP_DBRESET#(5,71)

SYS_PWROK(71,78)

RESET_OUT#(27)

PM_DRAM_PWRGD(5)

PCH_RSMRST#_Q(37)

ME_SUS_PWR_ACK(27)

SIO_PWRBTN#(27)

SIO_PWRBTN#_R(71)

AC_PRESENT(27)

5

DMI_RXP[3:0](4)

DMI_TXN[3:0](4)

DMI_TXP[3:0](4)

+1.05V_RUN

R1901 49D9R2F-GPR1901 49D9R2F-GP

1 2

R1902 750R2F-GPR1902 750R2F-GP

1 2

ME_SUS_PWR_ACK_R

1 2

R1931 0R2J-2-GP

1 2

R1928 0R0402-PAD-2-GPR1928 0R0402-PAD-2-GP

R1905 1KR2J-1-GPR1905 1KR2J-1-GP

DY

R1932 0R0402-PAD-2-GPR1932 0R0402-PAD-2-GP

R1933 0R0402-PAD-2-GPR1933 0R0402-PAD-2-GP R1934 0R0402-PAD-2-GPR1934 0R0402-PAD-2-GP

R1924 0R0402-PAD-2-GPR1924 0R0402-PAD-2-GP

R1935 0R0402-PAD-2-GPR1935 0R0402-PAD-2-GP

R1936 0R0402-PAD-2-GPR1936 0R0402-PAD-2-GP

1 2 1 2

DY

R1923 0R2J-2-GP

1 2

R1930 0R0402-PAD-2-GPR1930 0R0402-PAD-2-GP

1 2

DY

PM_APW ROK_R

R1916

1 2 1 2

1 2

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_COMP_R RBIAS_CPY

SUSACK#_R

SYS_PWROK_R

PCH_PW ROK

0R2J-2-GP

PM_DRAM_PWRGD_R PCH_RSMRST#_RPCH_DPW ROK

ME_SUS_PWR_ACK_R

SIO_PWRBTN#_R

AC_PRESENT

PCH_BATLOW#

PM_RI#

+3.3V_ALW_PCH

R1920 10KR2J-3-GP

R1920 10KR2J-3-GP R1921 10KR2J-3-GP

R1921 10KR2J-3-GP

4

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

PM_APW ROK(27)

3

FDI_TXN0

BJ14

FDI_TXN1

AY14

FDI_TXN2

BE14

FDI_TXN3

BH13

FDI_TXN4

BC12

FDI_TXN5

BJ12

FDI_TXN6

BG10

FDI_TXN7

BG9

FDI_TXP0

BG14

FDI_TXP1

BB14

FDI_TXP2

BF14

FDI_TXP3

BG13

FDI_TXP4

BE12

FDI_TXP5

BG12

FDI_TXP6

BJ10

FDI_TXP7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWODVREN

A18

PCH_DPW ROK

E22

PCH_PCIE_WAKE#

B9

CLKRUN#

N3

SUS_STAT#/LPCPD#

G8

SUSCLK

N14

SIO_SLP_S5#

D10

SIO_SLP_S4#

H4

SIO_SLP_S3#

F4

SIO_SLP_A#

G10

SIO_SLP_SUS#

G16

H_PM_SYNC

AP14

SIO_SLP_LAN#

K14

SIO_SLP_A# PM_APW ROK

FDI_TXN[7:0] (4)

FDI_TXP[7:0] (4)

FDI_INT (4) FDI_FSYNC0 (4) FDI_FSYNC1 (4) FDI_LSYNC0 (4) FDI_LSYNC1 (4)

TP1901TP1901

1

TP1902TP1902

1

U1902

1

A

VCC

2

B GND3Y

U74LVC1G08G-AL5-R-GP-U

73.01G08.EHG

2ND = 73.7SZ08.DAH

3rd = 73.7SZ08.EAH

1 2

DY

R1912 0R2J-2-GP

CLKRUN# (27,77,78)

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

SIO_SLP_S3# (36,45,47,78)

SIO_SLP_A# (36,45,78)

SIO_SLP_SUS# (78)

H_PM_SYNC (5)

SIO_SLP_LAN# (78,82)

+3.3V_ALW

5

4

PM_APW ROK_R

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

DSWODVREN

PCH_DPW ROK (78)

PCH_PCIE_WAKE# (27)

SIO_SLP_S5# (27,36)

SIO_SLP_S4# (36,46,78)

C1912

SCD1U16V2KX-3GP

C1912

SCD1U16V2KX-3GP

12

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

+3.3V_RUN

PCH (DM I/FDI/PM)

Austin 13

Tuesday, February 26, 2013

Austin 13

RTC_AUX_S5

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

19 106

1

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

S5 power rail CLKREQ#: PCIECLKRQ[0]#

+3.3V_ALW_PC H

D D

+3.3V_ALW_PC H

RN2001

1 2 3 4 5

SRN10KJ-6-G P

RN2002

1 2 3 4 5

SRN10KJ-6-G P

8 7 6

PCIECLKRQ6# MINI3CLK_REQ# MINI1CLK_REQ# EXPCLK_REQ#

PEG_B_CLKRQ# PCIECLKRQ7# PCH_SMB_ALER T#

PCH_GPIO74

PCIECLKRQ[7:3]#

PCIE_CLK_RQ6# PCIE_CLK_RQ3# PCIE_CLK_RQ0# PCIE_CLK_RQ4#

PCIE_CLK_RQ5# PCIE_CLK_RQ7#

+3.3V_RUN

RN2018

1 2 3

SRN10KJ-5-G P

4

MMICLK_REQ# LANCLK_REQ#

PCIE_CLK_RQ2# PCIE_CLK_RQ1#

S0 power rail CLKREQ#: PCIECLKRQ[2:1]#

RN2004

8

SRN2K2J-2-G P

7 6

+3.3V_ALW_PC H

C C

B B

A A

CRB : 1K CEKLT: 10K

RN2022

1 2 3

SRN2K2J-1-G P

Layout Note:

Layout trace < 14000mil

1 2 3

SML1_SMBDATA

45

R201110KR2 J-3-GP R201110KR 2J-3-GP

12

DDR_HVR EF_RST_PCH

12

R20091KR2J-1-GP R20091KR2J -1-GP

PEG_A_CLKRQ#

12

R201510KR2 J-3-GP R201510KR 2J-3-GP

LAN_SMBCLK

4

LAN_SMBDATA

5

SMB_DATA

SMB_CLK

SML1_SMBCLK

MINI2CLK_REQ#

+3.3V_RUN

RN2007

12

RN2007

2 3 1

SRN2K2J-1-G P

6

Q2001

Q2001 2N7002KDW -GP

2N7002KDW -GP

2 3

82.30020.D41

2nd = 82.30020.G61

4

1 2345

X2001

41

XTAL-25MHZ- 155-GP

PCH_SMBDAT A (14,15,66,71,79,82)

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PCH_SMBCLK (14,15,66,71,79,82)

1 2

C2008

SC15P50V2JN-2- GP

C2007

SC15P50V2JN-2- GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Austin 13

1

Taipei Hsie n 221, Taiwan, R.O. C.

20 106

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Tuesday, Febr uary 26, 2013

Date: Sheet of

A00

2 OF 10

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

NC

PETN1

AU32

PETP1

PCIE_RXN2(82) PCIE_RXP2(82)

PCIE_TXN2(82) PCIE_TXP2(82)

PCH_RXN_C _MMI_TXN6(32) PCH_RXP_C _MMI_TXP6(32)

MMI_RXN_C_PCH _TXN6(32) MMI_RXP_C_PCH_T XP6(32)

PCH_RXN_C _LAN_TXN7(82) PCH_RXP_C _LAN_TXP7(82)

LAN_RXN_C_ PCH_TXN7(82) LAN_RXP_C_PC H_TXP7(82)

C2005 SC D1U16V2KX-3G PC2005 SCD 1U16V2KX-3GP C2006 SC D1U16V2KX-3G PC2006 SCD 1U16V2KX-3GP

C2001 SC D1U16V2KX-3G PC2001 SCD 1U16V2KX-3GP C2002 SC D1U16V2KX-3G PC2002 SCD 1U16V2KX-3GP

C2009 SC D1U16V2KX-3G PC2009 SCD 1U16V2KX-3GP C2010 SC D1U16V2KX-3G PC2010 SCD 1U16V2KX-3GP

CLK_PCIE_LAN#(82) CLK_PCIE_LAN(82)

LANCLK_REQ#(82)

CLK_PCIE_MMI#(32) CLK_PCIE_MMI(32)

MMICLK_REQ#(32)

CLK_PCIE_MINI2#(82) CLK_PCIE_MINI2(82)

MINI2CLK_REQ#(82)

CLK_CPU_ITP#(71) CLK_CPU_ITP(71)

1 2 1 2

RN2023

2 3 1

0R4P2R-PAD

RN2024

1 2 3

0R4P2R-PAD

RN2028

1 2 3

0R4P2R-PAD

RN2026

1 2 3

0R4P2R-PAD

4

RN

4

RN

4

RN

4

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN6_C PCIE_TXP6_C

PCIE_TXN7_C PCIE_TXP7_C

MINI1CLK_REQ#

PCIE_LAN# PCIE_LAN

PCIE_MMI# PCIE_MMI

MINI3CLK_REQ#

EXPCLK_REQ#

PCIE_MINI2# PCIE_MINI2

PEG_B_CLKRQ#

PCIECLKRQ6#

PCIECLKRQ7#

CLK_BCLK_ITP# CLK_BCLK_ITP

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER- GP-NF

71.PANTH.00U

WLAN

NC

MMI

LOM

NC

LAN

MMI

NC

PCI-E*

NC

WLAN

NC

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

Link

CLOCKS

FLEX CLOCKS

2 OF 10

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64 CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

3

PCH_SMB_ALER T#

E12

SMB_CLK

H14

SMB_DATA

C9

DDR_HVR EF_RST_PCH

A12

LAN_SMBCLK

C8

LAN_SMBDATA

G12

PCH_GPIO74

C13

SML1_SMBCLK

E14

SML1_SMBDATA

M16

PCH_CL_CLK 1

M7

PCH_CL_DAT A1

T11

PCH_CL_RST 1#

P10

PEG_A_CLKRQ#

M10

AB37 AB38

CLKOUT_DM I_N

AV22

CLKOUT_DM I_P

AU22

AM12 AM13

CLK_BUF_EXP_N

BF18

CLK_BUF_EXP_P

BE18

CLK_BUF_CP YCLK_N

BJ30

CLK_BUF_CP YCLK_P

BG30

CLK_BUF_DO T96_N

G24

CLK_BUF_DO T96_P

E24

CLK_BUF_CK SSCD_N

AK7

CLK_BUF_CK SSCD_P

AK5

CLK_BUF_RE F14

K45

CLK_PCI_LOOPBAC K

H45

XTAL25_IN

V47 V49

XCLK_RCOMP

Y47

CLKOUTFLEX 0

K43

SIO_14M

F47

PCI_TPM_TCM

H47

PCH_GPIO67

K49

DDR_HVR EF_RST_PCH (5) LAN_SMBCLK (82)

LAN_SMBDATA (82)

SML1_SMBCLK (27) SML1_SMBDATA (27)

TP2002TP2002

1

TP2003TP2003

1

TP2004TP2004

1

R2007

1 2

90D9R2F-1-G P

1

R2016 3 3R2J-2-GPR2016 33R2J-2-GP R2018 3 3R2J-2-GPR2018 33R2J-2-GP

1

Layout Note:

CLKOUT termination place close to PCH <500mil

RN2017

2 3 1

4

0R4P2R-PAD

RN

2 3

RN2019

1

SRN10KJ-5-G P

2 3

RN2008

1

SRN10KJ-5-G P

2 3

RN2020

1

SRN10KJ-5-G P

2 3

RN2021

1

SRN10KJ-5-G P

R2008

1 2

10KR2J-3-GP

+1.05V_RUN

TP2001TP2001

1 2 1 2

TP2005TP2005

CLK_EXP_N (5) CLK_EXP_P (5)

4

CLK_PCI_LOOPBAC K (18)

Can Place Far away PCH

SMB_DATA

SMB_CLK

Layout Note:

1500mil < Layout trace < 10000mil

CLK_SIO_14M (78) CLK_PCI_TPM_TC M (71,77)

2

XTAL25_INXTAL25_OUT

1MR2J-1-GP

XTAL25_OUT

R2006

Vinaﬁx.com

5

SSID = PCH

D D

Place it at the open door location.

R2123

R2123 33R2J-2-GP

HDA_SPKR

33R2J-2-GP

R2125

R2125 33R2J-2-GP

33R2J-2-GP

R2126

R2126 33R2J-2-GP

33R2J-2-GP

HDA_CODEC_SDOUT(82)

C C

HDA_CODEC_RST#(82)

HDA_CODEC_BITCLK(82)

Layout Note:

Place at the separated point

+3.3V_RUN

R2106 1KR2J-1-GP

1 2

DY

RTC_AUX_S5

RN2102

1 2 3

SRN20KJ-1-GP

Layout Note:

SC1U6D3V2KX-GP

Layout Note:

HDA_SDOUT

12

HDA_RST#

12

HDA_BITCLK

12

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

Place close together. For RNxxxx later.

Low = Default High = Enable

No Reboot Strap

1 2

Low = Default High = No Reboot

B B

HDA_SPKR

+3.3V_ALW_PCH

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

100KR2J-1-GP

100KR2J-1-GP R2132

R2132

1 2

DY

*

HDA_SYNC

PLL ODVR VOLTAGE

HDA_SYNC

HDA_CODEC_SYNC(82)

A A

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

Low = 1.8V High = 1.5V

*

R2124

33R2J-2-GP

5

HDA_CODEC_SYNC_R

12

+5V_RUN

12

R2117

R2117 1MR2J-1-GP

1MR2J-1-GP

4

Layout Note:

Place it at the open door location.

4

C2104

12

C2103

Layout Note:

HDA_SDO and HDA_BCLK must be length matched to within 500 mils

ME_FWP(78)

*

Q2101

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

4

21

12

SC1U6D3V2KX-GP

G2102

G2102 GAP-OPEN

GAP-OPEN

2 1

+3.3V_ALW_PCH

D

DY

G2101

G2101 GAP-OPEN

GAP-OPEN

RTC_AUX_S5

1KR2J-1-GP

R2111 51R2J-2-GP

1 2

R2118 210R2F-L-GP

1 2

R2119 210R2F-L-GP

1 2

R2120 210R2F-L-GP

1 2

HDA_SYNC

HDA_CODEC_BITCLK

EC2102

1 2

SC4D7P50V2CN-1GP

Integrated SUS 1V VRM Enable

INTVRMEN

HDA_SPKR(82)

HDA_SDIN0(82)

R2107

1 2

DY

DY DY

DY

SPI_CLK_R(60) SPI_CS0#(60) SPI_CS1#(60)

SPI_SI_R(60)

SPI_SO_R(60)

Low = External VRs High = Internal VRs

1MR2J-1-GP

R2104

1 2

R2105

1 2

330KR2F-L-GP

330KR2F-L-GP R2131

R2131

1 2

DY

330KR2F-L-GP

HDA_SDOUT

HDA_CODEC_SDOUT

EC2103

DY

1 2

SC4D7P50V2CN-1GP

RTC_X1 RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INTVRMEN

HDA_BITCLK HDA_SYNC

HDA_RST#

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

3

PCH_GPIO33 PCH_GPIO13

C2101

SC15P50V2JN-2-GP

3

*

PCH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-GP-NF

71.PANTH.00U

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

1

12

2 3

X-32D768KHZ-40GPU

82.30001.841

2nd = 82.30001.A41

1 2

X2101

JTAG

RTCIHDA

SPI

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

2

LPC_LAD0_PCH

C38

LPC_LAD1_PCH

A38

LPC_LAD2_PCH

B37

LPC_LAD3_PCH

C37

LPC_LFRAME#_PCH

D36 E36

LPC_LDRQ1#

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

SATA_ACT#

P3

HDD_DET#_R

V14

BBS_BIT0

P1

Layout Note:

1228

R2116 22R2J-2-GPR2116 22R2J-2-GP

1 2

R2121 22R2J-2-GPR2121 22R2J-2-GP

1 2

R2127 22R2J-2-GPR2127 22R2J-2-GP

1 2

R2128 22R2J-2-GPR2128 22R2J-2-GP

1 2 1 2

R2136 22R2J-2-GPR2136 22R2J-2-GP

LPC_LDRQ1# (78)

IRQ_SERIRQ (27,77,78)

SATA_RXN0 (56) SATA_RXP0 (56) SATA_TXN0 (56) SATA_TXP0 (56)

SATA_RXN1 (66) SATA_RXP1 (66) SATA_TXN1 (66) SATA_TXP1 (66)

Layout Note:

HDD < 6000mil, mSATA < 6000mil, ODD < 12500mil

SATA_COMP

SATA3_COMP

RBIAS_SATA3

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

1 2

R2210 0R0402-PAD-2-GPR2210 0R0402-PAD-2-GP

Place near PCH

WWAN

1 2

SATA_ACT# (68)

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

LPC_LFRAME# (27,71,77,78)

HDD1

1

LPC_LAD[3..0]

+1.05V_RUN

Layout Note:

Place close PCH(<500mil)

HDD_DET# (56)

LPC_LAD[3..0] (27,71,77,78)

BBS_BIT0 - BIOS BOOT STRAP BIT0

+3.3V_ALW_PCH

PCH_GPIO13 BBS_BIT0 RTC_X1 RTC_X2

4

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

2

1 2

R2130

R2130 100KR2J-1-GP

100KR2J-1-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

PCH_GPIO33 IRQ_SERIRQ

HDD_DET#

PCH (SPI/RTC/LPC/SATA/IHDA)

Austin 13

R2102 4K7R2J-2-GPR2102 4K7R2J-2-GP

1 2

R2129 100KR2J-1-GPR2129 100KR2J-1-GP

1 2 1

2 3

RN2103

RN2103 SRN10KJ-5-GP

SRN10KJ-5-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

21 106

1

+3.3V_RUN

4

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

6 OF 10

+3.3V_RUN

D D

C C

+3.3V_ALW_PCH

RN2203

RN2203 SRN10KJ-5-GP

SRN10KJ-5-GP

1

4

2 3

12

DY

R2202 100KR2J-1-GP

R2202 100KR2J-1-GP R2204 100KR2J-1-GPR2204 100KR2J-1-GP

12

R2205

R2205 4K7R2J-2-GP

4K7R2J-2-GP

12

R2252

DY

1KR2F-3-GP

12

SLP_ME_CSW_DEV#

Note: PCH has internal pull up 20k ohm on E3_PAID_TS_DET#(GPIO27)

SIO_A20GATE SIO_RCIN#

PCIE_MCARD1_DET# USB_MCARD1_DET#

SIO_EXT_SCI#(27)

PM_LANPHY_ENABLE(78)

PCIE_MCARD1_DET#(82)

SLP_ME_CSW_DEV#(78)

USB_MCARD1_DET#(82)

1 2

R2206 0R0402-PAD-2-GPR2206 0R0402-PAD-2-GP

SIO_EXT_W AKE#(78)

FFS_INT2(79)

TEMP_ALERT#(78)

KB_DET#(69)

SIO_EXT_SCI#_R PCH_GPIO1 IO_LOOP# PCH_GPIO7 SIO_EXT_W AKE# PM_LANPHY_ENABLE PCH_GPIO15

PCH_GPIO16

PCH_GPIO17 PCH_GPIO22 PCIE_MCARD1_DET# PCH_GPIO27 SLP_ME_CSW_DEV# PCH_GPIO34 USB_MCARD1_DET# PCH_GPIO36 PCH_GPIO37 TPM_ID0 TPM_ID1 FFS_INT2 TEMP_ALERT# KB_DET# PCH_NCTF_BH3

SLP_ME_CSW_DEV# PULL ON DIE VR ENABLE

ENABLED

DISABLED

B B

+3.3V_ALW_PCH

DY

12 12 12 12 12 12

R2245 10KR2J-3-GPR2245 10KR2J-3-GP R7851 1KR2F-3-GPR7851 1KR2F-3-GP R2247 10KR2J-3-GPR2247 10KR2J-3-GP R2248 10KR2J-3-GPR2248 10KR2J-3-GP R2201 100KR2J-1-GPR2201 100KR2J-1-GP R2246 10KR2J-3-GP

R2246 10KR2J-3-GP

A A

HIGH(DEFAULT)

LOW

SIO_EXT_W AKE# PCH_GPIO15 PCH_GPIO27 KB_DET# PCIE_MCARD1_DET# PM_LANPHY_ENABLE

TPM_ID0

TP2211TPAD14-OP-GP TP2211TPAD14-OP-GP TP2212TPAD14-OP-GP TP2212TPAD14-OP-GP

DY

12

R2243

R2243 10KR2J-3-GP

10KR2J-3-GP

R2244

R2244 10KR2J-3-GP

10KR2J-3-GP

PCH_NCTF_B3

1

PCH_NCTF_B47

1

TPM_ID1

+3.3V_RUN+3.3V_RUN

12

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49/TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1#A4

A44

VSS_NCTF_2#A44

A45

VSS_NCTF_3#A45

A46

VSS_NCTF_4#A46

A5

VSS_NCTF_5#A5

A6

VSS_NCTF_6#A6

B3

VSS_NCTF_7#B3

B47

VSS_NCTF_8#B47

BD1

VSS_NCTF_9#BD1

BD49

VSS_NCTF_10#BD49

BE1

VSS_NCTF_11#BE1

BE49

VSS_NCTF_12#BE49

BF1

VSS_NCTF_13#BF1

BF49

VSS_NCTF_14#BF49

PANTHER-GP-NF

71.PANTH.00U

R2223

R2223 20KR2J-L2-GP

20KR2J-L2-GP

GPIO

NCTF

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

No TPM, No China TPM

TPM

TBD

5

4

3

6 OF 10

TACH4/GPIO68 TACH5/GPIO69 TACH6/GPIO70 TACH7/GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15#BG2

VSS_NCTF_16#BG48

VSS_NCTF_17#BH3

VSS_NCTF_18#BH47

VSS_NCTF_19#BJ4 VSS_NCTF_20#BJ44 VSS_NCTF_21#BJ45 VSS_NCTF_22#BJ46

VSS_NCTF_23#BJ5

VSS_NCTF_24#BJ6

VSS_NCTF_25#C2

VSS_NCTF_26#C48

VSS_NCTF_27#D1

VSS_NCTF_28#D49

VSS_NCTF_29#E1

VSS_NCTF_30#E49

VSS_NCTF_31#F1

VSS_NCTF_32#F49

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

TPM_ID1TPM_ID0

0

1 1

CONTACTLESS_DET# PCH_GPIO69 PCIE_MCARD3_DET# USB_MCARD2_DET#

SIO_A20GATE

SIO_RCIN# H_CPUPW RGD PCH_THERMTRIP_R INIT3_3V# DF_TVS

PCH_NCTF_BG2 PCH_NCTF_BG48

PCH_NCTF_BH47

PCH_NCTF_C2 PCH_NCTF_C48

1

USB_MCARD2_DET# (66)

SIO_A20GATE (27)

SIO_RCIN# (27) H_CPUPW RGD (5,71)

TP2213TP2213

Layout Note:

Check these four balls are connected firstly, then to GND

1 1 1 1

1 1

2

12

C2210

C2210 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

TP2203 TPAD14-OP-GPTP2203 TPAD14-OP-GP TP2204 TPAD14-OP-GPTP2204 TPAD14-OP-GP TP2205 TPAD14-OP-GPTP2205 TPAD14-OP-GP TP2206 TPAD14-OP-GPTP2206 TPAD14-OP-GP

TP2207 TPAD14-OP-GPTP2207 TPAD14-OP-GP TP2208 TPAD14-OP-GPTP2208 TPAD14-OP-GP

Title

Size Document Number Rev

Size Document Number Rev A3

A3

A3 Date: Sheet of

Date: Sheet of

DF_TVS

Tuesday, February 26, 2013

R2211

1 2

56R2J-4-GP

1 2

1KR2F-L-GP

USB_MCARD2_DET# PCIE_MCARD3_DET#

SIO_RCIN# SIO_EXT_SCI# PCH_GPIO1 PCH_GPIO36 PCH_GPIO37 PCH_GPIO16 TEMP_ALERT# PCH_GPIO22 PCH_GPIO7 PCH_GPIO17 IO_LOOP# PCH_GPIO34 CONTACTLESS_DET#

PCH_GPIO36 PCH_GPIO37 PCH_GPIO17 PCH_GPIO16 PCH_GPIO69

PCH (GPIO/CPU)

Austin 13

+1.05V_RUN_VTT

+VCCDFTERM

12

R2207

R2207 2K2R2J-2-GP

2K2R2J-2-GP

R2209

R2254 100KR2J-1-GPR2254 100KR2J-1-GP R7848 100KR2J-1-GPR7848 100KR2J-1-GP

R2230 10KR2J-3-GPR2230 10KR2J-3-GP R2231 10KR2J-3-GPR2231 10KR2J-3-GP R7849 100KR2J-1-GPR7849 100KR2J-1-GP R2232 10KR2J-3-GP

R2232 10KR2J-3-GP R2249 1KR2F-3-GP

R2249 1KR2F-3-GP R2233 10KR2J-3-GPR2233 10KR2J-3-GP R2234 10KR2J-3-GPR2234 10KR2J-3-GP R2235 10KR2J-3-GPR2235 10KR2J-3-GP R2236 10KR2J-3-GPR2236 10KR2J-3-GP R2222 8K2R2J-3-GPR2222 8K2R2J-3-GP R2237 10KR2J-3-GPR2237 10KR2J-3-GP R2238 10KR2J-3-GPR2238 10KR2J-3-GP R2239 10KR2J-3-GPR2239 10KR2J-3-GP

R2240 10KR2J-3-GPR2240 10KR2J-3-GP R2241 10KR2J-3-GPR2241 10KR2J-3-GP R2250 1KR2F-3-GP

R2250 1KR2F-3-GP R2242 10KR2J-3-GP

R2242 10KR2J-3-GP R2214 1K5R2F-2-GPR2214 1K5R2F-2-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DY

1 2

DY

DY DY

DY

1 2

1

H_SNB_IVB# (5)

12 12

12 12 12 12 12 12 12 12 12 12 12 12 12

12 12

12

22 106

+3.3V_RUN

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

10 uf x1

12

C2301

SC10U6D3V5KX-1GP

12

C2306

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 uf x3

12

DY

C2302

SC1U6D3V2KX-GP

TP2301TPAD14-OP-GP TP2301TPAD14-OP-GP

10 uf x4 1 uf x3

12

C2307

SCD1U16V2KX-3GP

DY

12

TP2302TPAD14-OP-GP TP2302TPAD14-OP-GP

12

C2303

SC1U6D3V2KX-GP

+1.05V_RUN

1

12

C2308

SCD1U16V2KX-3GP

+1.05V_+1.5V_1.8V_RUN

1

+1.05V_RUN

+1.05V_RUN_VTT

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

C2309

SC1U6D3V2KX-GP

VCCFDIPLL

+1.05V_RUN

D D

C C

+1.05V_RUN

B B

+3.3V_RUN

12

1.7A

3.711A

EC2305

SCD1U16V2KX-3GP

EC2305

SCD1U16V2KX-3GP

0.228A

DY

AA23 AC23 AD21 AD23

AF21

AF23 AG21 AG23 AG24 AG26 AG27 AG29

AJ23

AJ26

AJ27

AJ29

AJ31

AN19

BJ22

AN16 AN17

AN21 AN26 AN27 AP21 AP23 AP24 AP26

AT24

AN33 AN34

BH29

AP16

BG6

AP17

AU20

PCH1G

VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE17

VCCIO28

VCCAPLLEXP

VCCIO15 VCCIO16

VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26

VCC3_3_3

VCCVRM2

VCCAFDIPLL

VCCIO27

VCCDMI2

PANTHER-GP-NF

71.PANTH.00U

POWER

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

DFT / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS1 VCCTX_LVDS2 VCCTX_LVDS3 VCCTX_LVDS4

VCC3_3_6

VCC3_3_7

VCCVRM3

VCCDMI1

VCCCLKDMI

VCCDFTERM1

VCCDFTERM2

VCCDFTERM3

VCCDFTERM4

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

SCD01U50V2KX-1GP

12

C2313

+3VS_VCCA_LVDS

+1.8VS_VCCTX_LVDS

12

C2319

C2319 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

0.167A

+1.05VS_VCC_DMI

12

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+1.05VS_VCC_DMI_CCI

12

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2322

C2322 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C2314

SCD1U16V2KX-3GP

SCD01U50V2KX-1GP

12

C2316

+1.05V_+1.5V_1.8V_RUN

12

C2315

SC10U6D3V3MX-GP

SCD01U50V2KX-1GP

C2317

+VCCDFTERM

0.061A

VCCDAC

0.001A

R2308 0R0402-PAD-2-GPR2308 0R0402-PAD-2-GP

0.04A

12

C2318

SC22U6D3V5MX-2GP

0.228A

0.047A

R2306 0R0402-PAD-2-GPR2306 0R0402-PAD-2-GP

0.07A

R2307 0R0603-PAD-2-GPR2307 0R0603-PAD-2-GP

0.002A

R2312 0R0603-PAD-2-GPR2312 0R0603-PAD-2-GP

0.01A

3D3V_LDO_DAC 3D3V_LDO_DAC

R2309

1 2

0R0603-PAD-2-GP

1 2

MMZ1608S181C-GP

1 2

L2302

68.00040.201

MMZ1608S181C-GP

12

+3.3V_RUN

L2301

12

68.00040.201

+3.3V_RUN

+1.8V_RUN

+3.3V_RUN

+1.05V_RUN_VTT

+1.05V_RUN

+1.8V_RUN

+3.3V_M

DY

+5V_RUN

12

DY

C2325

SC1U6D3V2KX-GP

12

C2324

C2324 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

Refer to chipset EDS V.0.7

Voltage Rail

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS VccTX_LVDS

U2305

1 2 3 4 5

Voltage(V)

1.05 5 5

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

EN GND VIN

DY

VOUT NC#5

G9091-330T12U-GP

Iccmax(A)

0.001

0.228

0.063

0.08

1.7

0.047

3.711

0.903

0.01

0.001

0.002 6uA

0.095

0.01

0.167

0.07

0.095

0.055

0.001

0.04

+1.05V_+1.5V_1.8V_RUN +1.5V_RUN

A A

5

4

1 2

R2311 0R0603-PAD-2-GPR2311 0R0603-PAD-2-GP

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

PCH (POWER1)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

23 106

1

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

DY

1

C2405

SC1U6D3V2KX-GPDYC2405

SC1U6D3V2KX-GP

12

1

SCD1U16V2KX-3GP

C2418

12

SCD1U16V2KX-3GP

C2421

12

VCCACLK

DCPSUSBYP

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+1.05V_RUN

+VCCSUS1

C2419

SC1U6D3V2KX-GPDYC2419

SC1U6D3V2KX-GP

12

DY

+VCCRTCEXT

0.167A

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

+VCCSST

DCPSUS

12

C2420

C2420 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C2422

12

SC22U6D3V5MX-2GP

+VCCDIFFCLKN

C2415

C2417

C2436

TP2401TPAD14-OP-GP TP2401TPAD14-OP-GP

TP2402

TPAD14-OP-GP

TP2403

TPAD14-OP-GP

TP2404

TPAD14-OP-GP

C2406

SC1U6D3V2KX-GP

C2406

SC1U6D3V2KX-GP

12

+1.05V_+1.5V_1.8V_RUN

12

TP2405

TPAD14-OP-GP

12

4

+3.3V_ALW_PCH

DG: none

+3.3V_RUN

D D

+1.05V_RUN

C C

CRB: 10uH

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.1001E.10N

L2402

L2403

SC10U6D3V5KX-1GP

+V3.3S_VCC_CLKF33

12

DY

C2401

0.08A

+1.05VS_VCCA_A_DPL

12

DY

C2408

0.08A

SC10U6D3V5KX-1GP

+1.05VS_VCCA_B_DPL

EC2409

SCD1U16V2KX-3GP

EC2409

SCD1U16V2KX-3GP

12

+1.05V_M

12

X03 2/16

B B

+1.05V_RUN

A A

+1.05V_RUN

R2403

1 2

0R0402-PAD-2-GP

R2404

1 2

0R0402-PAD-2-GP

+VCCDIFFCLK

12

C2412

SC1U6D3V2KX-GP

0.095A

+V1.05S_SSCVCC

12

C2413

SC1U6D3V2KX-GP

5

0.001A

SCD1U16V2KX-3GP

12

C2402

C2402 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.93A

SC22U6D3V5MX-2GP

12

C2403

DY

0.055A

1 2

0R0603-PAD-2-GP

+1.05V_RUN_VTT

RTC_AUX_S5

12

TC2402

DY

ST220U2D5VAM-GP

12

TC2401

DY

ST220U2D5VAM-GP

SCD1U16V2KX-3GP

R2412

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

C2407

C2407 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

4.7 uf x1

0.1 uf x1

C2416

22 uf x2 1 uf x3

12

C2404

C2411

C2414

0.001A

6uA

AD49

V12

BH23 AL29

AL24

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47 BF47

AF17 AF33 AF34

AG34

AG33

V16

V19

A22

T16

T38

T17

BJ8

PCH1J

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_5

VCCAPLLDMI2 VCCIO14

DCPSUS3

VCCASW1 VCCASW2 VCCASW3 VCCASW4 VCCASW5 VCCASW6 VCCASW7 VCCASW8 VCCASW9 VCCASW10 VCCASW11 VCCASW12 VCCASW13 VCCASW14 VCCASW15 VCCASW16 VCCASW17 VCCASW18 VCCASW19 VCCASW20

DCPRTC

VCCVRM4

VCCADPLLA VCCADPLLB

VCCIO7 VCCDIFFCLKN1 VCCDIFFCLKN2 VCCDIFFCLKN3

VCCSSC

DCPSST

DCPSUS1 DCPSUS2

V_PROC_IO

VCCRTC

PANTHER-GP-NF

71.PANTH.00U

POWER

Clock and Miscellaneous

CPURTC

3

PCI/GPIO/LPCMISC

SATA USB

HDA

10 OF 10

N26

VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33

VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9

VCCSUS3_3_10

VCCSUS3_3_6

VCCIO34

V5REF_SUS

DCPSUS4

VCCSUS3_3_1

P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

12

C2438

C2438 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.095A

12

C2424

C2424 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+1.05V_RUN

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

0.001A

+5VS_PCH_VCC5REF

P34

V5REF

VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5

VCCAPLLSATA

VCCASW22

VCCASW23

VCCASW21

VCCSUSHDA

N20 N22 P20 P22

AA16

VCC3_3_1

W16

VCC3_3_8

T34

VCC3_3_4

AJ2

VCC3_3_2

AF13

VCCIO5

AH13

VCCIO12

AH14

VCCIO13

AF14

VCCIO6

AK1

AF11

VCCVRM1

AC16

VCCIO2

AC17

VCCIO3

AD17

VCCIO4

T21

V21

T19

P32

VCCSUSHDA need to be at either 3.3V or 1.5V. All the CODEC I/O Voltages need to be at the same level either 3.3 V or 1.5 V.

12

+V1.05S_VCCAPLL_SATA3

+1.05V_M

12

C2428

SC1U6D3V2KX-GP

+3.3V_RUN

C2431

C2431 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C2432

SC1U6D3V2KX-GP

+1.05V_+1.5V_1.8V_RUN

C2435

SC1U6D3V2KX-GP

+3VS_+1.5VS_HDA_IO

0.01A

C2433

C2433 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+1.05V_RUN

+3.3V_ALW_PCH

(0.1uFx1)

12

C2425

C2425 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+3.3V_ALW_PCH

12

C2434

C2434 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C2429

C2429 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

DY

1

TPAD14-OP-GP

12

R2402

1 2

0R0402-PAD-2-GP

2

+3.3V_ALW_PCH

+3.3V_RUN

12

C2430

C2430 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+3.3V_RUN

+1.05V_RUN

TP2406

+1.05V_RUN

+3.3V_ALW_PCH

+VCCA_USBSUS

83.R0304.A8F

2nd = 83.R3004.A8F

3rd = 83.R2004.M8F

+5VA_PCH_VCC5REFSUS

83.R0304.A8F

2nd = 83.R3004.A8F

3rd = 83.R2004.M8F

+5VS_PCH_VCC5REF

12

C2437

DY

SC1U10V2KX-1GP

+3.3V_ALW_PCH

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

12

C2426

C2426 SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+3.3V_RUN

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

12

C2427

C2427 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

R2408

1 2

10R2F-L-GP

R2409

1 2

10R2F-L-GP

+5V_ALW _PCH

+5V_RUN

Refer to chipset EDS V.0.7

Voltage Rail

V_PROC_IO V5REF V5REF_Sus Vcc3_3 VccADAC VccADPLLA VccADPLLB VccCore VccDMI VccIO VccASW VccSPI VccDSW3_3 VccDFTERM VccRTC VccSus3_3 VccSusHDA VccVRM VccClkDMI VccSSC VccDIFFCLKN VccALVDS

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

VccTX_LVDS

PCH (POWER2)

Austin 13

Voltage(V)

1.05

3.3

1.05

1.1

1.05

3.3

1.8

3.3

1.5

1.05

3.3

1.8

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

Iccmax(A)

0.001 5 5

0.001

0.228

0.063

0.08

1.7

0.047

3.711

0.903

0.01

0.001

0.002

6uA

0.095

0.01

0.167

0.07

0.095

0.055

0.001

0.04

24 106

A00

Vinaﬁx.com

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS0

AA17

VSS1

AA2

VSS2

AA3

VSS3

AA33

VSS4

AA34

VSS5

AB11

VSS6

AB14

VSS7

AB39

VSS8

AB4

VSS9

AB43

VSS10

AB5

VSS11

AB7

VSS12

AC19

VSS13

AC2

VSS14

AC21

VSS15

AC24

VSS16

AC33

VSS17

AC34

VSS18

AC48

VSS19

AD10

VSS20

AD11

VSS21

AD12

VSS22

AD13

VSS23

AD19

VSS24

AD24

VSS25

AD26

VSS26

AD27

VSS27

AD33

VSS28

AD34

VSS29

AD36

VSS30

AD37

VSS31

AD38

VSS32

AD39

VSS33

AD4

VSS34

AD40

VSS35

AD42

VSS36

AD43

VSS37

AD45

VSS38

AD46

VSS39

AD8

VSS40

AE2

VSS41

AE3

VSS42

AF10

VSS43

AF12

VSS44

AD14

VSS45

AD16

VSS46

AF16

VSS47

AF19

VSS48

AF24

VSS49

AF26

VSS50

AF27

VSS51

AF29

VSS52

AF31

VSS53

AF38

VSS54

AF4

VSS55

AF42

VSS56

AF46

VSS57

AF5

VSS58

AF7

VSS59

AF8

VSS60

AG19

VSS61

AG2

VSS62

AG31

VSS63

AG48

VSS64

AH11

VSS65

AH3

VSS66

AH36

VSS67

AH39

VSS68

AH40

VSS69

AH42

VSS70

AH46

VSS71

AH7

VSS72

AJ19

VSS73

AJ21

VSS74

AJ24

VSS75

AJ33

VSS76

AJ34

VSS77

AK12

VSS78

AK3

VSS79

PANTHER-GP-NF

71.PANTH.00U

8 OF 10

VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

B31

VSS168

B35

VSS169

B39

VSS170

B7

VSS171

F45

VSS172

BB12

VSS173

BB16

VSS174

BB20

VSS175

BB22

VSS176

BB24

VSS177

BB28

VSS178

BB30

VSS179

BB38

VSS180

BB4

VSS181

BB46

VSS182

BC14

VSS183

BC18

VSS184

BC2

VSS185

BC22

VSS186

BC26

VSS187

BC32

VSS188

BC34

VSS189

BC36

VSS190

BC40

VSS191

BC42

VSS192

BC48

VSS193

BD46

VSS194

BD5

VSS195

BE22

VSS196

BE26

VSS197

BE40

VSS198

BF10

VSS199

BF12

VSS200

BF16

VSS201

BF20

VSS202

BF22

VSS203

BF24

VSS204

BF26

VSS205

BF28

VSS206

BD3

VSS207

BF30

VSS208

BF38

VSS209

BF40

VSS210

BF8

VSS211

BG17

VSS212

BG21

VSS213

BG33

VSS214

BG44

VSS215

BG8

VSS216

BH11

VSS217

BH15

VSS218

BH17

VSS219

BH19

VSS220

H10

VSS221

BH27

VSS222

BH31

VSS223

BH33

VSS224

BH35

VSS225

BH39

VSS226

BH43

VSS227

BH7

VSS228

D3

VSS229

D12

VSS230

D16

VSS231

D18

VSS232

D22

VSS233

D24

VSS234

D26

VSS235

D30

VSS236

D32

VSS237

D34

VSS238

D38

VSS239

D42

VSS240

D8

VSS241

E18

VSS242

E26

VSS243

G18

VSS244

G20

VSS245

G26

VSS246

G28

VSS247

G36

VSS248

G48

VSS249

H12

VSS250

H18

VSS251

H22

VSS252

H24

VSS253

H26

VSS254

H30

VSS255

H32

VSS256

H34

VSS257

F3

VSS258

PANTHER-GP-NF

71.PANTH.00U

3

9 OF 10

VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS328 VSS329 VSS330 VSS331 VSS333 VSS334 VSS335 VSS337 VSS338 VSS340 VSS342 VSS343 VSS344 VSS345 VSS346 VSS347 VSS348 VSS349 VSS350 VSS351 VSS352

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

25 106

1

A00

Vinaﬁx.com

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Tuesday, February 26, 2013

Date: Sheet of

Reserved

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

26 106

1

A00

Vinaﬁx.com

SSID = KBC

+3.3V_ALW

D D

C C

B B

FLASH KBC ROM Stuff: R2766, C2717, R2746, RN2701, R2747 DY: R2760, C2718.

A A

R2780 100KR2J -1-GP

R2780 100KR2J -1-GP R2757 10KR2J -3-GPR2757 10KR2J-3-GP R2758 100KR2J -1-GPR2758 100KR2J -1-GP R2759 100KR2J -1-GPR2759 100KR2J -1-GP

R2761 2K2R2J -2-GPR2761 2K2R2J-2-GP R2762 2K2R2J -2-GPR2762 2K2R2J-2-GP R2763 100KR2J -1-GP

R2763 100KR2J -1-GP R2764 2K2R2J -2-GPR2764 2K2R2J-2-GP R2765 2K2R2J -2-GPR2765 2K2R2J-2-GP R2768 2K2R2J -2-GPR2768 2K2R2J-2-GP R2769 2K2R2J -2-GPR2769 2K2R2J-2-GP R2770 2K2R2J -2-GPR2770 2K2R2J-2-GP R2771 2K2R2J -2-GPR2771 2K2R2J-2-GP R2772 2K2R2J -2-GPR2772 2K2R2J-2-GP R2773 2K2R2J -2-GPR2773 2K2R2J-2-GP R2774 2K2R2J -2-GPR2774 2K2R2J-2-GP R2775 2K2R2J -2-GPR2775 2K2R2J-2-GP R2776 100KR2J -1-GPR2776 100KR2J -1-GP R2777 100KR2J -1-GP

R2777 100KR2J -1-GP R2782 2K2R2J -2-GPR2782 2K2R2J-2-GP R2783 2K2R2J -2-GPR2783 2K2R2J-2-GP R2784 2K2R2J -2-GPR2784 2K2R2J-2-GP R2785 2K2R2J -2-GPR2785 2K2R2J-2-GP R2702 10KR2J -3-GPR2702 10KR2J-3-GP R2704 10KR2J -3-GPR2704 10KR2J-3-GP R2714 10KR2J -3-GPR2714 10KR2J-3-GP

R2747 10KR2J -3-GPR2747 10KR2J-3-GP R2748 100KR2J -1-GPR2748 100KR2J -1-GP R2749 100KR2J -1-GPR2749 100KR2J -1-GP R2750 100KR2J -1-GP

R2750 100KR2J -1-GP R2751 100KR2J -1-GPR2751 100KR2J -1-GP R2752 10KR2J -3-GPR2752 10KR2J-3-GP R2753 8K2R2J -3-GP

R2753 8K2R2J -3-GP R2754 100KR2J -1-GPR2754 100KR2J -1-GP R2755 10KR2J -3-GPR2755 10KR2J-3-GP R2756 2K7R2F -GPR2756 2K7R2F-GP

C2718

SCD1U16V2KX-3GPDYC2718

SCD1U16V2KX-3GP

R2760

12

DY

1 2

DY

1 2 1 2 1 2

DY

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

DY

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

DY

1 2 1 2 1 2

DY

1 2 1 2 1 2

+3.3V_ALW

100KR2J-1-GPDYR2760

100KR2J-1-GP

DY

1 2

5

+3.3V_ALW

12

C2701

C2701 SCD1U16V2KX- 3GP

U2701

1

VCCSAPW ROK(48)

1.05V_VTTPW RGD(45,48)

BC_INT#_EMC4022 PCIE_WAKE# BC_DAT_EMC 4022 BC_DAT_ECE 5048

PBAT_SMBDAT PBAT_SMBCLK LPC_LDRQ#_ME C CHARGER _SMBDAT CHARGER _SMBCLK GPU_SMBDAT GPU_SMBCLK LCD_SMBCLK LCD_SMBDAT DOCK_SMB_DA T PCH_ALW _ON DOCK_SMB_CL K BAY_SMBDAT BAY_SMBCLK DYN_TUR_C URRNT_S ET#

1.05V_A_PWR GD_SIO CARD_SMBD AT CARD_SMBC LK USH_SMBDAT USH_SMBCLK HOST_DEBU G_TX HOST_DEBU G_RX

MSCLK

MSDATA DDR_ON PCH_ALW _ON DOCK_POR_R ST# EN_INVPWR

1.05V_0.8V_PWR OK RESET_OUT # CPU1.5V_S3_GAT E PCH_RSMRS T# AUX_ON_R

A

VCC

2

B GND3Y

U74LVC1G08G-A L5-R-GP-U

73.01G08.EHG

2ND = 73.7SZ08.DAH

3rd = 73.7SZ08.EAH

EC_32KHZ_EC E5048(78)

5

4

SCD1U16V2KX- 3GP

1.05V_0.8V_PWR OK (42)

SML1_SMBDATA(20)

SML1_SMBCLK(20)

CLK_TP_SIO(69)

DAT_TP_SIO(69)

PBAT_SMBDAT(39)

BC_CLK_ECE504 8(78)

BC_DAT_ECE 5048(78)

BC_INT#_ECE5048(78)

BC_CLK_EMC4022(28)

BC_DAT_EMC 4022( 28)

BC_INT#_EMC4022(28) PCH_PCIE_W AKE#(19) BC_CLK_ECE111 7(69)

BC_DAT_ECE 1117(69)

BC_INT#_ECE1117(69)

R2711

0R0402-PAD-2- GP

MEC_XTAL2

1 2

R2710 0R0402-PAD -2-GPR2710 0R0402-PAD-2- GP

32 KHZ Clock

X2701

10KR2J-3-GP

12

R2767

1 2

0R2J-2-GP

X2701

1

2 3

X-32D768KHZ- 40GPU

82.30001.841

2nd = 82.30001.A41

R2778

10KR2J-3-GP

R2778

10KR2J-3-GP

12

DB2

DY

R2715

4

R2786

10KR2J-3-GP

R2786

10KR2J-3-GP

R2779

10KR2J-3-GP

R2779

10KR2J-3-GP

12

DB2

JTAG_TMS JTAG_CLK JTAG_TDO

USB_PWR _SHR_EN# (78,82)

EC5048_TX

12

R2766

R2766 10KR2J-3-GP

10KR2J-3-GP

12

C2717

C2717 SCD1U16V2KX- 3GP

SCD1U16V2KX- 3GP

ACES-CON 10-28-GP

20.K0460.010

JTAG_RST#

DB2

1219 1219

C2724

SC39P50V2JN-1GP

C2724

SC39P50V2JN-1GP

12

JTAG Debug port

+3.3V_ALW +3.3V_ALW

12

DB2

R2746

49D9R2F-GP

DB2

11 1

2 3 4 5 6 7 8 9 10 12

DB2

JTAG_PU

MSCLK MSDATA HOST_DEBU G_TX HOST_DEBU G_RX

PBAT_SMBCLK(39)

AUX_ON_R(82)

PCH_ALW _ON(36) BIA_PWM_EC(49)

PCIE_WAKE#(66,82)

SIO_SLP_S5#(19,36) ACAV_IN_NB(40)

SIO_EXT_SMI#(18)

SIO_RCIN#(22) IRQ_SERIRQ(21,77,78)

PLT_RST#(18,66 ,71,77,78,82) CLK_PCI_MEC( 18)

LPC_LFRAME#(21,71,7 7,78) LPC_LAD0(21,71,77,78) LPC_LAD1(21,71,77,78) LPC_LAD2(21,71,77,78) LPC_LAD3(21,71,77,78) CLKRUN#( 19,77,78) SIO_EXT_SCI#(22)

C2723

JTAG_TDI

BEEP(82)

12

SC39P50V2JN-1GP

12

Place near KBC

5

4

RTC_AUX_S5 +3.3V_ALW

SML1_SMBDATA SML1_SMBCLK

GPIO112 GPIO113 GPIO114 GPIO115

JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#

DOCK_POR_R ST#

AUX_ON_R

BC_CLK_ECE504 8 BC_DAT_ECE 5048 BC_INT#_ECE5048 BC_CLK_EMC4022 BC_DAT_EMC 4022 BC_INT#_EMC4022

PCH_PCIE_W AKE# PCIE_WAKE# BC_CLK_ECE111 7 BC_DAT_ECE 1117 BC_INT#_ECE1117 BEEP SIO_SLP_S5# ACAV_IN_NB

SIO_EXT_SMI# SIO_RCIN#

LPC_LDRQ#_ME C

IRQ_SERIRQ PLT_RST# CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 CLKRUN# SIO_EXT_SCI#

MEC_XTAL1 MEC_XTAL2_R

EC_32KHZ_EC E5048_R

MEC_XTAL1

MEC_XTAL2

R2701

+RTC_CELL_E C

12

0R0402-PAD-2- GP

U2702

A5

GPIO7/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA

B6

GPIO10/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK

A37

GPIO110/PS2_CLK2/GPTP_IN6

B40

GPIO111/PS2_DAT2/GPTP_OUT6

A38

GPIO112/PS2_CLK1A

B41

GPIO113/PS2_DAT1A

A39

GPIO114/PS2_CLK0A

B42

GPIO115/PS2_DAT0A

B59

GPIO154/I2C1C_DATA/PS2_CLK1B

A56

GPIO155/I2C1C_CLK/PS2_DAT1B

A51

GPIO145/I2C1K_DATA/JTAG_TDI

B55

GPIO146/I2C1K_CLK/JTAG_TDO

B56

GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK

A53

GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS

B57

JTAG_RST#

B22

GPIO50/FAN_TACH1

A21

GPIO51/FAN_TACH2

B23

GPIO52/FAN_TACH3

B24

GPIO53/PWM0

A23

GPIO54/PWM1

B25

GPIO55/PWM2

A24

GPIO56/PWM3

A43

GPIO123/BCM_A_CLK

B45

GPIO122/BCM_A_DAT

A42

GPIO121/BCM_A_INT#

A12

GPIO22/BCM_B_CLK

B13

GPIO23/BCM_B_DAT

A13

GPIO24/BCM_B_INT#

B20

GPIO44/BCM_C_CLK

A18

GPIO43/BCM_C_DAT

B19

GPIO42/BCM_C_INT#

A20

GPIO47/LSBCM_D_CLK

B21

GPIO46/LSBCM_D_DAT

A19

GPIO45/LSBCM_D_INT#

A16

GPIO32/GPTP_IN3/BCM_E_CLK

B16

GPIO31/GPTP_OUT2/BCM_E_DAT

A15

GPIO30/GPTP_IN2/BCM_E_INT#

A6

GPIO11/SMI#

A27

GPIO61/LPCPD#

B29

LDRQ#

A28

SER_IRQ

B30

LRESET#

A29

PCI_CLK

B31

LFRAME#

A30

LAD0

B32

LAD1

A31

LAD2

B33

LAD3

A32

CLKRUN#

A33

GPIO100/EC_SCI#

A61

XTAL1

A62

XTAL2

B62

GPIO160/32KHZ_OUT

MEC5055-LZY-AUS 00-GP

71.05055.B03

C2702

SCD1U16V2KX-3GP

C2702

SCD1U16V2KX-3GP

12

AGND

NC#B34

NC#A64

NC#B68

B66

B34

A64

B68

15mil

B64

A11

A22

VTR

VBAT

VSS

B11

B60

C2713

SC4D7U6D3V 3KX-GP

12

B35

A41

A58

A52

A26

VTR

VTRB3VTR

GPIO124/GPTP_OUT5/UART_RX

GPIO14/GPTP_IN7/HSPI_CS1

GPIO40/GPTP_OUT3/HSPI_CS2

GPIO107/RESET_OUT#

GPIO12/I2C1H_DATA/I2C2D_DATA

GPIO13/I2C1H_CLK/I2C2D_CLK

GPIO141/I2C1F_DATA/I2C2B_DATA

GPIO142/I2C1F_CLK/I2C2B_CLK

VR_CAP

VSS_RO

B12

B54

15mil

+VR_CAP

12

C2703

SCD1U16V2KX-3GP

C2703

SCD1U16V2KX-3GP

12

GPIO25/UART_CLK GPIO120/UART_TX

GPIO101/ECGP_SCLK GPIO103/ECGP_MISO GPIO105/ECGP_MOSI

GPIO102/HSPI_SCLK

GPIO104/HSPI_MISO GPIO106/HSPI_MOSI

GPIO116/MSDATA

GPIO117/MSCLK

PROCHOT#/PWM4

GPIO1/ECSPI_CS1 GPIO2/ECSPI_CS2

GPIO15/GPTP_OUT7

GPIO16/GPTP_IN8

GPIO17/GPTP_OUT8

GPIO26/GPTP_IN1

GPIO27/GPTP_OUT1

GPIO125/GPTP_IN5 GPIO151/GPTP_IN4

GPIO152/GPTP_OUT4

GPIO3/I2C1A_DATA

GPIO4/I2C1A_CLK

GPIO5/I2C1B_DATA

GPIO6/I2C1B_CLK

GPIO130/I2C2A_DATA

GPIO131/I2C2A_CLK

GPIO132/I2C1G_DATA

GPIO140/I2C1G_CLK

GPIO143/I2C1E_DATA

GPIO144/I2C1E_CLK

GND

C1

C2704

SCD1U16V2KX-3GP

C2704

SCD1U16V2KX-3GP

12

GPIO21/RC_ID1 GPIO20/RC_ID2

VCC_PWRGD

GPIO60/KBRST

GPIO127/A20M GPIO153/LED3 GPIO156/LED1 GPIO157/LED2

FWP#

GPIO41

GPIO126

BGPO0 VCI_IN2# VCI_OUT VCI_IN1# VCI_IN0#

VCI_OVRD_IN

VCI_IN3#

PECI_VREF

I2S_DAT I2S_CLK

I2S_WS

C2705

SCD1U16V2KX-3GP

C2705

SCD1U16V2KX-3GP

PECI

3

C2706

SCD1U16V2KX-3GP

C2706

SCD1U16V2KX-3GP

12

SYSTEM_ID

A10

BOARD_ID

B10

DDR_ON

B14

HOST_DEBU G_TX

B44

HOST_DEBU G_RX

B46

RUNPW ROK

B26

EN_INVPWR

A25 B36 B37 B38

DDR_HVR EF_RST_GAT E

A34

DYN_TUR_C URRNT_S ET#

A35

CPU1.5V_S3_GAT E

A36

MSDATA

A40

MSCLKMSCLK

B43 A45 A55 A57 B61

FWP#

B65

PROCHOT #_EC

A46

B2 A2 B8 B18 A8 B9 A9

1.05V_A_PWR GD_SIO

A14 B15

DEVICE_DET#

A17

RESET_OUT #

B39 A44

PCH_RSMRS T#

B47

AC_PRESENT

A54 B58

DOCK_SMB_DA T

A3

DOCK_SMB_CL K

B4

LCD_SMBDAT

A4

LCD_SMBCLK

B5

BAY_SMBDAT

B7

BAY_SMBCLK

A7

GPU_SMBDAT

B48

GPU_SMBCLK

B49

CHARGER _SMBDAT

A47

CHARGER _SMBCLK

B50

CARD_SMBD AT

B52

CARD_SMBC LK

A49

USH_SMBDAT

B53

USH_SMBCLK

A50

A59

LAT_ON_SW #

B63 A60

VCI_IN1#

A63

POWER_S W_IN#

B67 B1

DOCK_PW R_SW#

A1

+PECI_VREF

B51

PECI_EC_R

A48 B17

SIO_B27

B27

SIO_B28

B28

R2730

10KR2J-3-GP

FWP#

R2731

10KR2J-3-GP

BOARD_ID rise time is measured from 5%~68%.

C2722

R2735

130K 62K 33K

8.2K

4.3K 2K 1K

4

4700P240K 4700P 4700P 4700P 4700P 4700P 4700P 4700P

REV X00 X01 X02 A00

BOARD_ID

SC4700P50V2KX-1G P

3

C2709

SCD1U16V2KX-3GP

C2709

SCD1U16V2KX-3GP

C2708

SCD1U16V2KX-3GP

C2708

SCD1U16V2KX-3GP

C2707

SCD1U16V2KX-3GP

C2707

SCD1U16V2KX-3GP

12

1 2

R2707 43R 2J-GPR2707 43R2J-GP

R2708 1 00KR2J-1-GPR2708 10 0KR2J-1-GP

1 2

R2709 1 00KR2J-1-GPR2709 10 0KR2J-1-GP

1 2

+3.3V_ALW

12

DY

+3.3V_ALW

12

R2735

R2735 33KR2F-GP

33KR2F-GP

12

C2722

SYSTEM_ID for BID function *Pop R2734 130k for non-vPro

C2710

SCD1U16V2KX-3GP

C2710

SCD1U16V2KX-3GP

12

C2711

SC10U6D3V3MX-GP

DDR_ON (46)

HOST_DEBU G_TX ( 82)

HOST_DEBU G_RX (82) RUNPW ROK (5,78) EN_INVPWR (49)

DDR_HVR EF_RST_GAT E (5) DYN_TUR_C URRNT_S ET# (40) CPU1.5V_S3_GAT E (36)

MSDATA (82)

MSCLK (82) SIO_A20GATE (22) PSID_EC (38)

ME_SUS_PW R_ACK (19)

1.35V_SUS_PW RGD (46) PM_APWRO K (19)

PWR_5V3D 3V_PGOOD (41) RESET_OUT # (19) PCH_RSMRS T# (37)

AC_PRESENT (19) SIO_PWRBTN # (19)

CHARGER _SMBDAT (40)

CHARGER _SMBCLK (40)

ALWON (36)

ACAV_IN (28,40)

H_PECI (5)

PCH_PW RGD#(28)

RESET_OUT #

0220

SYSTEM_ID

SC4700P50V2KX-1G P

0R0402-PAD-2- GP

12

100KR2J-1-GP

Q2703

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

+3.3V_ALW

12

C2721

R2705

1 2

R2706

1 2

0R0402-PAD-2- GP

C2712

SCD1U16V2KX-3GP

C2712

SCD1U16V2KX-3GP

R1205 close to U51 & least 250 mils

12

R2732

D

R2734

130KR2F-GP

R2734

130KR2F-GP

2

POWER_S W_IN#(28)

1.05V_A_PWR GD ( 45)

+1.05V_RUN_VT T

RUN_ON_EN ABLE#(36)

2

RTC_AUX_S5

12

R2712

R2712 100KR2J-1-GP

100KR2J-1-GP

12

C2714

C2714 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

AC_PRESENT

GPIO112 GPIO113 GPIO114 GPIO115

0109

DEVICE_DET#

VCI_IN1# LAT_ON_SW # DOCK_PW R_SW#

+3.3V_RUN+3.3V_M

R2729

10KR2J-3-GP

RUNPW ROK

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

Place closely pin A29

Place closely pin A29Place closely pin A29

CLK_PCI_MEC

R2713

1 2

10KR2J-3-GP

R2716 10KR2J-3-GPR2716 10KR2J -3-GP

R2717 4K7R2J-2-GPR2717 4K7R2J -2-GP R2718 4K7R2J-2-GPR2718 4K7R2J -2-GP R2719 4K7R2J-2-GPR2719 4K7R2J -2-GP R2720 4K7R2J-2-GPR2720 4K7R2J -2-GP

R2733 100KR2J-1-GP

DY

R2724 100KR2J-1-GPR2724 100KR2J-1-GP R2725 100KR2J-1-GPR2725 100KR2J-1-GP R2781 100KR2J-1-GPR2781 100KR2J-1-GP

12

D

12

R3725

R3725 10R2J-2-GP

10R2J-2-GP

DY

CLK_PCI_MEC_R

12

C2720

C2720 SC4D7P50V2CN -1GP

SC4D7P50V2CN -1GP

DY

1

DY

1 2

C2715

C2715 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

KBC_PWR BTN# (68)

+3.3V_ALW_PC H

12

+5V_RUN

12 12 12 12

+3.3V_RUN

12

RTC_AUX_S5

12 12 12

1 2

R2726 0 R0402-PAD-2- GPR2726 0R0402- PAD-2-GP

Q2701

PROCHOT #_EC

Q2701

G

D

DY

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.2N702.W31

PROCHOT #_EC

Title

Size Document Num ber Rev

A2

Date: Sheet of

H_PROCHO T# (5,40)

+1.05V_RUN_VT T

12

R2727

R2727 10KR2J-3-GP

10KR2J-3-GP

DY

R2728

R2728 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

KBC - MEC5055

Austin 13

1

A00

27 106Tuesday, Feb ruary 26, 2013

A00

Vinaﬁx.com

5

4

3

2

1

SSID = Thermal

Layout note:

+FAN1_VOUT

+3.3V_RUN

C2827

SCD1U16V2KX-3GP

C2827

SCD1U16V2KX-3GP

+3.3V_M

+5V_RUN

1 2

12

C2825

SC1U6D3V2KX- GP

THERM_VDD _PWRGD

1 2

R2831 0R 0402-PAD-2-GPR2831 0R0402- PAD-2-GP

BC_INT#_EMC4022(27)

+1.05V_RUN_VT T

R2826

R2826 2K2R2J-2-GP

2K2R2J-2-GP

FAN1_DET#

FAN1_TACH _FB

THERM_VDD _PWRGD

BC_INT#_EMC4022

+3.3V_M

1 2

H_THERMT RIP#(5)

THERM_B1

D D

C C

12

R2819 10KR2J- 3-GPR2819 10KR2J-3-GP

12

R2810 10KR2J- 3-GPR2810 10KR2J-3-GP

12

R2833 10KR2J- 3-GPR2833 10KR2J-3-GP

12

R2812 10KR2J- 3-GPR2812 10KR2J-3-GP

R2807

1 2

8K2R2J-3-GP

C

MMBT3904-7-F-1 -GP

MMBT3904-7-F-1 -GP Q2809

Q2809

B

E

84.M3904.B11

2ND = 84.03904.U11

3rd = 84.03904.L06

+3.3V_M

1 2

R2809 22R 2J-2-GPR2809 22R2J -2-GP

PCH_PW RGD#(27)

ACAV_IN(2 7,40)

POWER_S W_IN#(27)

DY

R2825

47KR2J-2-GP

FAN1_DET#(78)

12

PURE_HW _SHUTDO WN#(36)

C2833

SCD1U16V2KX-3GP

C2833

SCD1U16V2KX-3GP

RTC_AUX_S5

1 2

C2818

SC10U10V5KX-2GP

C2818

SC10U10V5KX-2GP

12

R2832

R2832 1KR2J-1-GP

1KR2J-1-GP

POWER_S W_IN#_L

THERMTRIP2#

BC_INT#_EMC4022

C2823

SCD1U16V2KX-3GP

C2823

SCD1U16V2KX-3GP

12

C2824

SCD1U16V2KX-3GP

C2824

SCD1U16V2KX-3GP

3V_PWROK #

12

FAN1_DET#

BC_DAT_EMC 4022(27) BC_CLK_EMC4022(27)

SC10U10V5KX-2G P

10KR2J-3-GP

C2826

1 2

THERM_VDD

U2801

12

3V_PWROK#

13

VDD_PWRGD

21

ACAVAIL_CLR

20

POWER_SW#

15

GPIO3/PWM/THERMTRIP_SIO

17

THERMTRIP2#

19

SYS_SHDN#

9

ATF_INT#/BC_IRQ#

EMC4021-1-EZK- TR-GP

74.04021.073

12

R2821

12

1

VDD

NC#18

NC#2929NC#30

18

THERM_TEST 1 THERM_TEST 2

R2806

R2806 10KR2J-3-GP

10KR2J-3-GP

+FAN1_VOUT

3

VDD_H2VDD_H

30

FAN1_TACH_FB

5

6

10

16

VDD_L

FAN_OUT4FAN_OUT

RTC_PWR3V

SMDATA/BC_DATA7SMCLK/BC_CLK

TEST3

TEST1

TEST2

8

11

14

22

33

1 2

TACH/GPIO1

DN1/THERM

DP1/VREF_T

ADDR_MODE/XEN

GND

C2828S C1U6D3V2KX- GP C2828S C1U6D3V2KX- GP

DN2/DP4 DP2/DN4

RTC_AUX_S5

VIN

VSET

VCP

Layout Note:

Routing together; Trace width / Spacing = 10 / 10 mil

CPU sensor:

REM_DIODE1_N_4 022

SC2200P50V2KX-2G P

23 24

26 27

R2811

VCP_4021

25

1 2

10KR2J-3-GP

28 31

32

10KR2J-3-GP

3VSUS_THRM _1 THERM_VDD

SC2200P50V2KX-2G P

REM_DIODE1_P_4022 REM_DIODE2_N

SC2200P50V2KX-2G P

REM_DIODE2_P VSET_4021

Please Place C2829 and C2813 as close as possible to U2801 (EMC4021)

VCP2

1 2

R2820 4K7R2J- 2-GPR2820 4K7R2J-2-GP

12

C2829

Skin Temp Sensor:

12

C2813

Layout Note:

12

R2824 4K7R2J-2-GPR2824 4K7R2J-2-GP

15 mial; at least

D2802

CH551H-30PT-GP

D2802

CH551H-30PT-GP

21

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.R5003.G8H

E

B

C

MMBT3904-7-F-1 -GP

MMBT3904-7-F-1 -GP Q2805

Q2805

B

E

R2818

953R2F-GP

AD_IA (40)

SC2200P50V2KX-2GP

C2810

12

C2811

DY

SC10U10V5KX-2G P

FAN1_TACH _FB

AFTP2801A FTP2801

1

+FAN1_VOUT

AFTP2802A FTP2802

1

FAN1_DET#

AFTP2803A FTP2803

1

84.M3904.B11

2ND = 84.03904.U11

3rd = 84.03904.L06

Q2803

Q2803 MMBT3904-7-F-1 -GP

MMBT3904-7-F-1 -GP

12

C2803

DY

SC100P50V2JN-3 GP

12

C2830

DY

SC100P50V2JN-3 GP

84.M3904.B11

2ND = 84.03904.U11

3rd = 84.03904.L06

SC100P50V2JN-3 GP

12

C2832

SCD1U16V2KX-3GP

C2832

SCD1U16V2KX-3GP

12

R2818 783 ohm for 85 degree C. * 953 ohm(88 degree C)

1.24k ohm(92 degree C)

Layout Note:

1.Place C2803 as close as possible to Q2803

2.Place C2830 as close as possible to Q2805

3.Place C2831 as close as possible to Q2810

SODIMM Sensor:

B

84.M3904.B11

2ND = 84.03904.U11

3rd = 84.03904.L06

FAN1_TACH _FB FAN1_DET#

E

Q2810

Q2810 MMBT3904-7-F-1 -GP

MMBT3904-7-F-1 -GP

C

+FAN1_VOUT

C2831

DY

SC100P50V2JN-3 GP

1 2

FAN1

5

1 2

3 4

6

ACES-CON 4-29-GP

20.F1639.004

2nd = 20.F1804.004

B B

A A

Wistron Corporation

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,

21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih, Taipei Hsie n 221, Taiwan, R.O. C.

Taipei Hsie n 221, Taiwan, R.O. C.

Title

Size Document Num ber Rev

A2

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsie n 221, Taiwan, R.O. C.

Thermal, Fan controller

Austin 13

1

28 106Tuesday, Feb ruary 26, 2013

A00

Vinaﬁx.com

5

4

3

2

1

SSID = AUDIO

D D

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec 92HD94

Size Document Number Rev

A3

Date: Sheet of

Audio Codec 92HD94

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

29 106Tuesday, February 26, 2013

1

A00

Vinaﬁx.com

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Austin 13

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 106Tuesday, February 26, 2013

A00

Dell Latitude 3330 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual