DELL D510, DM3D Schematics

1

2

3

4

5

6

7

8

DRAM Power

DC/DC

A A

+3V_SRC
+5VSUS

PG 45

CPU VR

AC/BATT

PG 42

RUN POWER
SW

PG 46

POWER DC/DC

B B

DDR2-SODIMM1

CONNECTOR

BATT
SELECTOR

BATT
CHARGER

400/533 MHZ DDR II

1.8V, 0.9V

PG 43

1.5VSUS, 1.05V

PG 44

PG 47

PG 40

PG 41

PG 13,14

400/533 MHZ DDR II

DDR2-SODIMM2

PG 13,14

PG 19

PATA

88SA8040

PG 19

USB2.0 1 port(P0)

PATA - HDD

PG 19

Internal Media Bay

C C

CD-ROM

SATA

ATA 66/100

AC97

RJ11 to
DOCK

PG 38

MDC

PG 24

Tip
Ring

PG 24

AUDIO

PG 31,32

S/PDIF to
DOCK

D D

PG 38

Audio
Jacks

PG 34

IrDA

PG 37

1

2

TAHITI-INTEGRATED

Keyboard

PG 26

Dothan

(478 Micro-FCPGA)

PG 3,4

Alviso-GM

1257 PCBGA

PG 5,6,7,8,9

DMI interface

ICH6-M

609 BGA

PG 10,11,12

LPC

LPC

SIO(Macallan 3)

256 Pins LBGA

PG 25,26

PG 27

3

4X133MHZ

ParallelSerial

PG 28

sDVO

USB2.0 (P5,P7)
USB2.0 (P4,P6)

USB2.0 (P1)

LAN (100/10)
BCM4401

PG 35

USB2.0 (P2)

X-Bus

PS/2

Touchpad

PG 30

4

SI1362

PG 16

Flash

PG 29

CLOCKS

PG 15

1394 CONN

PG 22

Bluetooth

PG 30

SWTICH & LED &
IO CONN

PG 32

5

SYSTEM
RESET CKT

LVDS

DVI

TVOUT

VGA

2 Rear Ports
2 right Side

33MHz PCI

CARDBUS

PCI4515
PG 21

PG 39

PG 32
PG 32

E-Switch

PI3L110Q

DOCK LPC

FAN & THERMAL

PG 31

PG 36

6

Panel Connector

PG 17

S-Video

PG 18

CRT

PG 18

PCMCIA
CON.

PG 21

MINI-PCI

Wireless LAN

I/O Board CONN

PG 32

Title

Schematic Block Diagram1

Size Document Number Rev

Tahiti 1A

Date: Sheet

星期二

PG 23

QUANTA
COMPUTER

29, 2005

三月

7

DOCKING
CONNECTOR

PG 38

of

149,

8

1

Pg# Description

1

Schematic Block Diagram 1

2

Front Page

3-4

A A

B B

C C

Dothan

5-9

Alviso

10-12

ICH6

13-14

DDRII SO-DIMM(200P)

15

Clock Generator

16

SI1362

17

LCD Conn. & SSP

18

CRT & TV Conn.

19

SATA & IDE Conn.

20

PAD & Screw Hole

21

TI PIC4510

22

CB/1394 CONN

23

Mini PCI Conn.

24

MDC Conn.

25-26

SIO (LPC47N354)

27 Parallel Port
28

Serial Port

29

Flash ROM

30

Touch Pad CONN.& Bluetooth CONN

31

Switch Board Conn. & LED & IO Board

FAN & Thermal

32

33-34

Audio CODEC (STAC9751) & Phone Jack
LAN Interface

35-36

37

FIR

38

MISCELLANEA

2

INDEX

3

DNI LIST

4

5

6

Power & Ground

Label Description

DC_IN+
PBATT+
PWR_SRC

VHCORE

1.05V AGTL+ POWER (1.05V) I/O

+3VRUN
+3VSUS
+5VALW
+5VRUN
+5VSUS
+5VHDD
+5VMOD
STRB#/5V
+5VRUN
VDDA
1_8VSUS
1_8VRUN
+3VALW 8051 POWER (3V)
V1_5RUN

GND ALL PAGES DIGIT AL GROUND

Pg#

AC ADAPTER (20V)
MAIN BATTERY + (10~17V)
MAIN POWER (10~20V)

CPU CORE POWER (1.25/1.15V)

SLP_S3# CTRLD POWER
SLP_S5# CTRLD POWER
8051 POWER (5V)
SLP_S3# CTRLD POWER
SLP_S5# CTRLD POWER
HDD POWER (5V)
MODULE POWER (5V)
EXTERNAL FDD POWER (5V)
FAN POWER (5V)
AUDIO ANALOG POWER (5V)
RESUME WELL IN ICH
SLP_S3# CTRLD POWER

ALVISO POWE R Non -CPU I/O

COMBO CONN GND

7

8

Control Signal

RUNPWROK
RUNPWROK

RUN_ON
SUS_ON

RUN_ON
SUS_ON
HDDC_EN#
MODC_EN#
FDD/LPT#
FAN_OFF/ON#
RUN_ON

39 Docking Conn.
40

SYSTEM RESET/POWER GOOD

41-42

Battery Selector & Charger

43

CPU Power

44

1.8VSUS/0.9V

D D

45

1.5V/1.05V

46

D/D Power

47

RUN Power Switch

48

RUN POWER SW

1

QUANTA

Title

Size Document Number Rev

2

3

4

5

6

Date: Sheet

COMPUTER

Index, DNI, Power & Ground

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

249,

8

1

HADSTB0#5
HADSTB1#5

IGNNE#10

INTR10
NMI10
STPCLK#10

CPUSLP#5,10

DPSLP#10

HREQ#05
HREQ#15
HREQ#25
HREQ#35
HREQ#45

ADS#5

HBREQ0#5

BPRI#5

BNR#5

HLOCK#5

HIT#5

HITM#5

DEFER#5

HTRDY#5

RS#05
RS#15
RS#25

A20M#10

FERR#10

SMI#10

T11 PAD
T7 PAD

DBR#39

HA#[3..31]

HA#[3..31]5

A A

B B

C C

CPUPWRGD10

DPRSTP#10

G1: NC for

D D

Dothan and
DPRSTP# for
Yonah

THERMDA31
THERMDC31

THERMTRIP#31

1

2

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

IERR#

BPM0#
BPM1#
BPM2#
BPM3#

A20M#
FERR#
IGNNE#
CPUPWRGD
SMI#

TCK
TDO
TDI
TMS
TRST#

PREQ#
PRDY#
DBR#

STPCLK#
CPUSLP#
DPSLP#

THERMDA
THERMDC

THERMTRIP#

CPU_PROCHOT#

2

AA3
AA2

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

AE5

A13
A12
C12
C11
B13
A16
A15
B10
A10

B18
A18

C17
B17

P4

U4

V3

R3

V2

W1

T4

W2

Y4
Y1

U1

Y3

U3

R2

P3
T2
P1
T1

N2

A4

N4

J3

L1

J2

K3
K4
L4

C8

B8

A9
C9
M3
H1

K1

L2
C2

D3

A3

E4

B4

A7
D1

D4
C6

A6

B7
G1

U7A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

ADSTB0#
ADSTB1#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADS#

IERR#
BREQ0#

BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

BPM0#
BPM1#
BPM2#
BPM3#
TRDY#
RS0#
RS1#
RS2#

A20M#
FERR#
IGNNE#
PWRGOOD
SMI#

TCK
TDO
TDI
TMS
TRST#
ITP_CLK0
ITP_CLK1
PREQ#
PRDY#
DBR#

LINT0
LINT1
STPCLK#
SLP#
DPSLP#
DPRSTP#

THERMDA
THERMDC

THERMTRIP#
PROCHOT#

Dothan Processor

Dothan

REQUEST
PHASE
SIGNALS

ERROR
SIGNALS

ARBITRATION
PHASE
SIGNALS

SNOOP PHASE
SIGNALS

RESPONSE
PHASE
SIGNALS

PC
COMPATIBILITY
SIGNALS

DIAGNOSTIC
& TEST
SIGNALS

EXECUTION
CONTROL
SIGNALS

THERMAL DIODE

3

1 OF 3

3

DATA
PHASE
SIGNALS

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DSTBN0#
DSTBP0#
DSTBN1#
DSTBP1#
DSTBN2#
DSTBP2#
DSTBN3#
DSTBP3#

DINV0#
DINV1#
DINV2#
DINV3#

DBSY#
DRDY#

BCLK1
BCLK0

INIT#

RESET#

DPWR#

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

C23
C22
K24
L24
W25
W24
AE24
AE25

D25
J26
T24
AD20

M2
H2

B14
B15

B5
B11
C19

4

CPUINIT#
CPURST#

4

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#[0..63]

HDSTBN0# 5
HDSTBP0# 5
HDSTBN1# 5
HDSTBP1# 5
HDSTBN2# 5
HDSTBP2# 5
HDSTBN3# 5
HDSTBP3# 5

HDBI0# 5
HDBI1# 5
HDBI2# 5
HDBI3# 5

DBSY# 5
DRDY# 5

HCLK_CPU# 15
HCLK_CPU 15

CPUINIT# 10
CPURST# 5
DPWR# 5

5

HD#[0..63] 5

5

6

VCCP

THERMTRIP#

IERR#

CPUPWRGD

R25 56

1 2

R30 56

1 2

R31 200

1 2

CPU_PROCHOT#

VCCP

12

R24
56

R23

*330_NC

Thermal Level Shift

ITP disable guidelines

Signal
TDI
TMS
TRST#

TDO

Resistor Value
150 ohm +/- 5%
39 ohm +/- 5% VTT
680 ohm +/- 5% GND
27 ohm +/- 5%TCK

Open

Note: Populate All NC component when
ITP connector is populated.

R236

54.9/F

TDI
TMS
TCK

TDO
TRST#

CPURST#

TCK

HCLK_ITP#15
HCLK_ITP15

Connect To Resistor Placement

VCCP VCCP

12

12

R239

R238

39.2/F

54.9/F

1 2

R237 *22.6/F_NC

1 2

R235 *22.6/F_NC

ITP DEBUG PORT

6

TCK
TRST#

+3VRUN +3VALW

R22
*1.5K_NC

1 2

Q11

12

2

*3904_NC

1 3

VTT

GND
VTT

12

12

R240
150

JITP2

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLKN

9

BCLKP

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

*ITP700_NC

Title

Size Document Number Rev

Date: Sheet

R29 27.4/F

1 2
1 2

R28 680

2

7

R34
*330_NC

1 2
31

Q12
*RHU002N06_NC

PROCHOT# 26

8

Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU

VTT0
VTT1

VTAP

DBR#
DBA#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

NC0
NC1

VCCP

27
28
26

25
24

BPM0#

23

BPM1#

21

BPM2#

19

BPM3#

17

PRDY#

15

PREQ#

13
4

6

C359

*.1U_10V_NC

1 2

DBR#

+3VSUS

12

QUANTA
COMPUTER

Dothan Processor (HOST)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

349,

8

R234
150

1

2

3

4

5

6

7

8

COMP0
COMP1
COMP2
COMP3

R20

R19

R211

1 2

12

C334

10U_4V

12

C310

10U_4V

12

C278

10U_4V

C303

10U_4V

1 2

27.4/F

R212

54.9/F

1 2

12

C290

10U_4V

12

C307

10U_4V

12

C283

10U_4V

C282

10U_4V

1 2

12

C286

10U_4V

12

C329

10U_4V

12

C336

10U_4V

C305

10U_4V

1 2

12

.01U

12

C31

10U_4V

12

C335

10U_4V

C332

10U_4V

1 2

C42

27.4/F

54.9/F

1 2

C328

C280

C291

C279

12

C287

10U_4V

12

C34

10U_4V

12

C309

10U_4V

C331

10U_4V

1 2

1 2

VHCORE

VHCORE

VHCORE

A A

18mils Trace Width of COMP0,2
5mils Trace Width of COMP1,3

B B

12

10U_4V

12

10U_4V

12

C C

10U_4V

10U_4V

1 2

VHCORE

Total caps = 1670 uF > 1430 uF (Intel Recommendation)
ESR = 9m ohm/4 // 5m ohm/35 ---> = 0.1343m ohm

VCCP

C43
150U/6.3V

1

12

C314
.1U_10V

12

C322
.1U_10V

12

C315
.1U_10V

2

12

C321
.1U_10V

12

C325
.1U_10V

C, mF---------ESR, mW-----------ESL, nH
1 x 150 mF-----42 mW (typ) / 2--------2.5 nH / 12
10 x 0.1 mF----16 mW (typ) / 10-------0.6 nH / 10

D D

12

+

12

10U_4V

12

C302

10U_4V

12

C26

10U_4V

C330

10U_4V

1 2

VCCP

Z0 = 55 ohm, 25 mils
spacing for switching

R16

signals

1K/F

1 2

R15
2K/F

1 2

CPU_VCCA

C41

+1_5VRUN

VHCORE

12

12

C288

10U_4V

10U_4V

VHCORE

12

12

C285

10U_4V

10U_4V

VHCOREVHCORE

C289

10U_4V

10U_4V

1 2

1 2

VCCP

12

12

C313

C317

.1U_10V

.1U_10V

C284

C333

C304

3

12

C316
.1U_10V

R21 0_0603

12

C281

10U_4V

12

C308

10U_4V

C306

10U_4V

1 2

12

C323
.1U_10V

T9 PAD
T47 PAD

T10 PAD
T8 PAD

T2 PAD
T5 PAD
T6 PAD

12

12

C324
.1U_10V

COMP0
COMP1
COMP2
COMP3

GTLREF0

TEST1
TEST2

VHCORE

P25
P26
AB2
AB1

AD26

C5

F23

B2
C3

AF7

AC1

E26

AC26

N1
B1

F26

D18
D20
D22

E17
E19
E21

F18
F20
F22

G5

G21

H6

H22

J21

K22

U5
V6

V22

W5

W21

Y22
AA5
AA7

AA9
AA11
AA13
AA15
AA17
AA19
AA21

AB6

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8
AF10
AF12
AF14
AF16
AF18

4

U7B

COMP0
COMP1
COMP2
COMP3

GTLREF0

TEST1
TEST2

NC1
RSVD2

RSVD3
RSVD4
RSVD5

VCCA3
VCCA2
VCCA1
VCCA0

D6

VCC00

D8

VCC01
VCC02
VCC03
VCC04

E5

VCC05

E7

VCC06

E9

VCC07
VCC08
VCC09
VCC10

F6

VCC11

F8

VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19

J5

VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27

Y6

VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

Dothan Processor

Dothan

2 OF 3

POWER,
GROUND,
RESERVED
SIGNALS

VSS00
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

5

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4

SELPSB2_CLK6,15
SELPSB1_CLK6,15

CPU_VID042
CPU_VID142
CPU_VID242
CPU_VID342
CPU_VID442
CPU_VID542

Differential Probe
Test Using

SELPSB2_CLK
SELPSB1_CLK

PSI

STP_CPU#11,15,42

NO PSI (Power Saving
Indicator )

DothanA

R26 Install

NC

6

SELPSB2_CLK
SELPSB1_CLKCPU_VCCA

T3 PA D
T4 PA D

R26

1 2
1 2

R27 0

R32 *0_NC

R33
*0_NC

1 2

DothanB

0

VCCP

BSEL0
BSEL1

12

D10

VCCP0

D12

VCCP1

D14

VCCP2

D16

VCCP3

E11

VCCP4

E13

VCCP5

E15

VCCP6

F10

VCCP7

F12

VCCP8

F14

VCCP9

F16

VCCP10

K6

VCCP11

L5

VCCP12

L21

VCCP13

M6

VCCP14

M22

VCCP15

N5

VCCP16

N21

VCCP17

P6

VCCP18

P22

VCCP19

R5

VCCP20

R21

VCCP21

T6

VCCP22

T22

VCCP23

U21

VCCP24

P23

VCCQ0

W4

VCCQ1

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AE7

VCCSENSE

AF6

VSSSENSE

C16

BSEL0

C14

BSEL1

E1

PSI

R6

VSS100

R22

VSS101

R25

VSS102

T3

VSS103

T5

VSS104

T21

VSS105

T23

VSS106

T26

VSS107

U2

VSS108

U6

VSS109

U22

VSS110

U24

VSS111

V1

VSS112

V4

VSS113

V5

VSS114

V21

VSS115

V25

VSS116

W3

VSS117

W6

VSS118

W22

VSS119

Dothan Processor

U7C

Dothan

3 OF 3

POWER, GROUND AND NC

VID

VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

Dothan Processor (POWER)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

of

449,

8

1

2

3

4

5

6

7

8

HXRCOMP

12

R50
100/F

R56
100/F

VCCP

VCCP

VCCP

VCCP

12

12

12

12

12

12

12

R44

24.9/F

R43

54.9/F

HXSCOMP

R48
221/F

HXSWING

.1U_10V

1 2

HYRCOMP

R63

24.9/F

R51

54.9/F

HYSCOMP

R53
221/F

HYSWING

.1U_10V

1 2

C72

C82

A A

B B

C C

One pulled-down
resistor per pin.
Trace should be
10-mil wide with
20-mil spacing.

Signal voltage
level =

0.3125*VCCP.
C1a=0.1 µF. C1b=0.1
µF.Trace should be
10-mil wide with
20-mil spacing..

One pulled-down
resistor per pin.
Trace should be
10-mil wide with
20-mil spacing.

Signal voltage
level =

0.3125*VCCP.
C1a=0.1 µF. C1b=0.1
µF.Trace should be
10-mil wide with
20-mil spacing..

HD#[0..63]3

HD#[0..63]

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6

W6

U3

V5
W8
W7

U2

U1

Y5

Y2

V4

Y7
W1
W3

Y3

Y6
W2

C1

C2

D1

T1

L1

P1

U11A

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

ALVISO

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HADS#
HADSTB0#
HADSTB1#

HVREF

HBNR#

HBPRI#

BREQ0#

HCPURST#

HCLKINN
HCLKINP

HDBSY#

HDEFER#

HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#

HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ0#

HREQ1#

HREQ2#

HREQ3#

HREQ4#

HRS0#
HRS1#
HRS2#

HCPUSLP#

HTRDY#

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

F8
B9
E13
J11
A5
D5
E7
H10

AB1
AB2

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5

HA#[3..31]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HCPUSLP#_GMCH

HA#[3..31] 3

ADS# 3
HADSTB0# 3
HADSTB1# 3

BNR# 3
BPRI# 3
HBREQ0# 3
CPURST# 3

HCLK_MCH# 15
HCLK_MCH 15

DBSY# 3
DEFER# 3
HDBI0# 3
HDBI1# 3
HDBI2# 3
HDBI3# 3

DPWR# 3

DRDY# 3
HDSTBN0# 3
HDSTBN1# 3
HDSTBN2# 3
HDSTBN3# 3
HDSTBP0# 3
HDSTBP1# 3
HDSTBP2# 3
HDSTBP3# 3

HIT# 3
HITM# 3
HLOCK# 3

HREQ#0 3
HREQ#1 3
HREQ#2 3
HREQ#3 3
HREQ#4 3
RS#0 3
RS#1 3
RS#2 3

HTRDY# 3

VCCP

R284
100/F

1 2

Signal voltage level = 2/3 of
VCCP. One 0.1 µF decoupling
capacitor should be placed 100

12

mils or less from GMCH pin.

R276
200/F

12

C381
.1U_10V

HVREF

Concern about HVREF
Trace Length & Width

T77
PAD

T15
PAD

R37

1 2

0

CPUSLP# 3,10

Do not install R37 for Dothan-A and
install for Dothan-B

Concern about Trace Length and Width

D D

QUANTA

Title

Size Document Number Rev

1

2

3

4

5

6

Date: Sheet

COMPUTER

Alviso (Host)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

549,

8

1

DMI_TXN011
DMI_TXN111
DMI_TXN211

CLK_SDRAM0#13
CLK_SDRAM1#13

CLK_SDRAM3#13
CLK_SDRAM4#13

12

R315
*40.2/F_NC

SMDDR_VREF

12

C714

.1U_10V

+1_8VSUS

1

DMI_TXN311

DMI_TXP011
DMI_TXP111
DMI_TXP211
DMI_TXP311

DMI_RXN011
DMI_RXN111
DMI_RXN211
DMI_RXN311

DMI_RXP011
DMI_RXP111
DMI_RXP211
DMI_RXP311

CLK_SDRAM013
CLK_SDRAM113

PAD

T94

CLK_SDRAM313
CLK_SDRAM413

T89PAD

T90PAD

PAD

T91

CKE013,14
CKE113,14
CKE213,14
CKE313,14

SM_CS0#13,14
SM_CS1#13,14
SM_CS2#13,14
SM_CS3#13,14

SMDDR_VREF

12

C715

.1U_10V

Place these 2 Caps near
Alviso SMVREF pins.

12

R326

80.6/F

M_RCOMPN
M_RCOMPP

12

R318

80.6/F

M_OCDCOMP0
M_OCDCOMP1

M_ODT013,14
M_ODT113,14
M_ODT213,14
M_ODT313,14

CLK_SDRAM2

CLK_SDRAM5

CLK_SDRAM2#

CLK_SDRAM5#

CKE0
CKE1
CKE2
CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_RCOMPN
M_RCOMPP

SMXSLEW
SMYSLEW

A A

B B

12

R314

*40.2/F_NC

C C

D D

On-Die OCD driver
compensation (DDR2 only)

AA31

AB35
AC31
AD35

AA35

AB31
AC35

AA33

AB37
AC33
AD37

AA37

AB33
AC37

AM33

AE11

AJ34
AC10
AN33

AE10

AJ33
AD10

AP21
AM21
AH21

AK21
AN16

AM14
AH15
AG16

AF22

AF16

AP14

AL15
AM11
AN10

AK10

AK11

AF37

AD1
AE27
AE28

AF9
AF10

2

Y31

Y33

AL1

AF6

AK1

AF5

2

U11C

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

ALVISO

CFG[2:0]
001=FSB533
010=FSB800
101=FSB400

DMIDDR MUXING

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

CFG/RSVDPMLCKNC

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

DREF_CLKN

DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11

3

VCCP

12

CFG0

G16

SELPSB1_CLK

H13

SELPSB2_CLK

G14

CFG3

F16

CFG4

F15

CFG5

G15

CFG6

E16

CFG7

D17

CFG8

J16

CFG9

D15

CFG10

E15

CFG11

D14

CFG12

E14

CFG13

H12

CFG14

C14

CFG15

H15

CFG16

J15

CFG17

H14

CFG18

G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
C37
D37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

3

DREFSSCLK#_R
DREFSSCLK_R

DREFSSCLK#_R
DREFSSCLK_R

R269 *1K_NC

CFG19

R271 *1K_NC

CFG20

VCCP

R49
56

1 2

PLTRST#_R

DOT96#
DOT96

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11

1
3

3
1

Populate RP2 if using CK-SSCD.
Populate Rp12 if using CK410M

R286
10K

T66

PAD

T68

PAD

T59 PAD
T53 PAD
T74 PAD

T48 PAD
T67 PAD
T49 PAD
T71 PAD
T75 PAD

T138

PM_EXTTS#0
PM_EXTTS#1

1 2

R312 100

RP2

*4P2R-S-0_NC

RP12

4P2R-S-0

4

Low=DMIx2
High=DMIx4

PAD

DOT96# 15
DOT96 15

T40

PAD

T39

PAD

T42

PAD

T98

PAD

T41

PAD

T97

PAD

T16

PAD

T17

PAD

T12

PAD

T14

PAD

T13

PAD

2
4

4
2

4

CFG6

SELPSB1_CLK 4,15
SELPSB2_CLK 4,15

12

R273
*2.2K_NC

+2.5VRUN

PM_BMBUSY# 11

THERMTRIP_GMCH# 31
IMVP_PWRGD 11,39,42
PLTRST# 10,11,16,19,25

DREFSSCLK#_R
DREFSSCLK_R

DREFSSCLK# 17
DREFSSCLK 17

DOT100#_SS 15
DOT100_SS 15

12

R254

2.2K

Low=DDR2
High=DDR1

TV_COMP18,38

TV_Y/G18,38
TV_C/R18,38

R241 150/F

1 2

R248 150/F

1 2

R243 150/F

1 2

R267 *150 /F _N C

1 2

R251 *150/F_NC

1 2

R242 *150/F_NC

1 2

VGAVSYNC18
VGAHSYNC18

REFCLK/SSCLK

5

SDVO_CTRLDATA16
SDVO_CTRLCLK16
CLK_MCH_3GPLL#15
CLK_MCH_3GPLL15

1 2

R277

4.99K/F

CLK_DDC218
DAT_DDC218

VGA_BLU18,38
VGA_GRN18,38
VGA_RED18,38

R275 39

1 2

R274 39

1 2
1 2

R285
255/F

BIA_PWM25
FPBACK17

DDC_CLK17
DDC_DATA17

FPVCC17,26

1 2

R247

1.5K/F

TXLCLKOUT-17

TXLCLKOUT+17

TXLOUT0-17
TXLOUT1-17
TXLOUT2-17

TXLOUT0+17
TXLOUT1+17
TXLOUT2+17

+2.5VRUN

R282 10K

1 2

R283 10K

1 2

For Memory throttling

External Thermal Sensor Input

5

AB29
AC29

H24
H25

A15
C16
A17

B15
B16
B17

E24
E23
E21
D21
C20
B20
A19
B19
H21
G21

E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27

B30
B29
C25
C24

B34
B33
B32

A34
A33
B31

C29
D28
C27

C28
D27
C26

J18

J20

6

U11F

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

ALVISO

PM_EXTTS#0

PM_EXTTS#1

6

7

SDVOB_R-_C
SDVOB_G-_C
SDVOB_B-_C
SDVOB_CLK-_C

SDVOB_R+_C
SDVOB_G+_C
SDVOB_B+_C
SDVOB_CLK+_C

R268 24.9/F

1 2

SDVOB_INT- 16

SDVOB_INT+ 16

MISC

TV VGA LVDS

EXP_COMPI

EXP_ICOMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

PCI-EXPRESS GRAPHICS

EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

SDVOB_R-_C
SDVOB_G-_C
SDVOB_B-_C
SDVOB_CLK-_C

SDVOB_R+_C
SDVOB_G+_C
SDVOB_B+_C
SDVOB_CLK+_C

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9

C67 .1U_10V
C49 .1U_10V
C69 .1U_10V
C51 .1U_10V

C66 .1U_10V
C48 .1U_10V
C68 .1U_10V
C50 .1U_10V

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

VCC3G_PCIE_R

SDVO Output

QUANTA

Title

Size Document Number Rev

Custom

Date: Sheet

COMPUTER

Alviso (VGA,DMI)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

8

VCC3G_PCIE

SDVOB_R- 16
SDVOB_G- 16
SDVOB_B- 16
SDVOB_CLK- 16

SDVOB_R+ 16
SDVOB_G+ 16
SDVOB_B+ 16
SDVOB_CLK+ 16

of

649,

8

1

A A

2

3

4

5

6

7

8

R_A_MD[0..63]13

B B

C C

R_A_MD0
R_A_MD1
R_A_MD2
R_A_MD3
R_A_MD4
R_A_MD5
R_A_MD6
R_A_MD7
R_A_MD8
R_A_MD9
R_A_MD10
R_A_MD11
R_A_MD12
R_A_MD13
R_A_MD14
R_A_MD15
R_A_MD16
R_A_MD17
R_A_MD18
R_A_MD19
R_A_MD20
R_A_MD21
R_A_MD22
R_A_MD23
R_A_MD24
R_A_MD25
R_A_MD26
R_A_MD27
R_A_MD28
R_A_MD29
R_A_MD30
R_A_MD31
R_A_MD32
R_A_MD33
R_A_MD34
R_A_MD35

R_A_MD37
R_A_MD38
R_A_MD39
R_A_MD40
R_A_MD41
R_A_MD42
R_A_MD43
R_A_MD44
R_A_MD45
R_A_MD46
R_A_MD47
R_A_MD48
R_A_MD49
R_A_MD50
R_A_MD51
R_A_MD52
R_A_MD53
R_A_MD54
R_A_MD55
R_A_MD56
R_A_MD57
R_A_MD58
R_A_MD59
R_A_MD60
R_A_MD61
R_A_MD62
R_A_MD63

AG35
AH35

AL35
AL37

AH36

AJ35

AK37

AL34
AM36
AN35
AP32
AM31
AM34
AM35

AL32
AM32
AN31
AP31
AN28
AP28

AL30
AM30
AM28

AL28
AP27
AM27
AM23
AM22

AL23
AM24
AN22
AP22

AM9

AL9
AL6

AP7
AP11
AP10

AL7

AM7
AN5
AN6
AN3

AP3

AP6

AM6

AL4

AM3

AK2

AK3

AG2
AG1

AL3

AM2
AH3
AG3

AF3

AE3

AD6
AC4

AF2

AF1

AD4
AD5

U11B

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63

ALVISO

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR SYSTEM MEMORY A

SA_CAS#
SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AK15
AK16
AL21

AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3

AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

R_A_BS0#
R_A_BS1#
R_A_BS2#

R_A_DM0
R_A_DM1
R_A_DM2
R_A_DM3
R_A_DM4
R_A_DM5
R_A_DM6
R_A_DM7

R_A_DQS0
R_A_DQS1
R_A_DQS2
R_A_DQS3
R_A_DQS4
R_A_DQS5
R_A_DQS6
R_A_DQS7

R_A_DQS#0
R_A_DQS#1
R_A_DQS#2
R_A_DQS#3
R_A_DQS#4
R_A_DQS#5
R_A_DQS#6
R_A_DQS#7

R_A_MA0
R_A_MA1
R_A_MA2
R_A_MA3
R_A_MA4
R_A_MA5
R_A_MA6
R_A_MA7
R_A_MA8
R_A_MA9
R_A_MA10
R_A_MA11
R_A_MA12
R_A_MA13

R_A_SCASA#
R_A_SRASA#

R_A_BMWEA#

PAD

R_A_BS0# 13,14
R_A_BS1# 13,14
R_A_BS2# 13,14
R_A_DM[0..7] 13

R_A_DQS[0..7] 13

R_A_DQS#[0..7] 13

R_A_MA[0..13] 13,14

R_A_SCASA# 13,14
R_A_SRASA# 13,14

T123

R_A_BMWEA# 13,14

R_B_MD[0..63]13

R_B_MD0
R_B_MD1
R_B_MD2
R_B_MD3
R_B_MD4
R_B_MD5
R_B_MD6
R_B_MD7
R_B_MD8
R_B_MD9
R_B_MD10
R_B_MD11
R_B_MD12
R_B_MD13
R_B_MD14
R_B_MD15
R_B_MD16
R_B_MD17
R_B_MD18
R_B_MD19
R_B_MD20
R_B_MD21
R_B_MD22
R_B_MD23
R_B_MD24
R_B_MD25
R_B_MD26
R_B_MD27
R_B_MD28
R_B_MD29
R_B_MD30
R_B_MD31
R_B_MD32
R_B_MD33
R_B_MD34
R_B_MD35
R_B_MD36R_A_MD36
R_B_MD37
R_B_MD38
R_B_MD39
R_B_MD40
R_B_MD41
R_B_MD42
R_B_MD43
R_B_MD44
R_B_MD45
R_B_MD46
R_B_MD47
R_B_MD48
R_B_MD49
R_B_MD50
R_B_MD51
R_B_MD52
R_B_MD53
R_B_MD54
R_B_MD55
R_B_MD56
R_B_MD57
R_B_MD58
R_B_MD59
R_B_MD60
R_B_MD61
R_B_MD62
R_B_MD63

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31

AJ31

AK30

AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23

AJ22
AK22
AH24
AH23
AG22

AJ21
AG10

AG9
AG8

AH8
AH11
AH10

AK9

AK6

AH5

AK8

AK4

AG5

AG4

AD8

AD9

AH4

AG6

AE8

AD7

AC5

AB8

AB6

AA8

AC8

AC7

AA4

AA5

U11G

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37

AJ9

SBDQ38
SBDQ39

AJ7

SBDQ40
SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44

AJ8

SBDQ45

AJ5

SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

ALVISO

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR SYSTEM MEMORY B

SB_CAS#
SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

R_B_BS0#
R_B_BS1#
R_B_BS2#

R_B_DM0
R_B_DM1
R_B_DM2
R_B_DM3
R_B_DM4
R_B_DM5
R_B_DM6
R_B_DM7

R_B_DQS0
R_B_DQS1
R_B_DQS2
R_B_DQS3
R_B_DQS4
R_B_DQS5
R_B_DQS6
R_B_DQS7

R_B_DQS#0
R_B_DQS#1
R_B_DQS#2
R_B_DQS#3
R_B_DQS#4
R_B_DQS#5
R_B_DQS#6
R_B_DQS#7

R_B_MA0
R_B_MA1
R_B_MA2
R_B_MA3
R_B_MA4
R_B_MA5
R_B_MA6
R_B_MA7
R_B_MA8
R_B_MA9
R_B_MA10
R_B_MA11
R_B_MA12
R_B_MA13

R_B_SCASA#
R_B_SRASA#

R_B_BMWEA#

PAD

R_B_BS0# 13,14
R_B_BS1# 13,14
R_B_BS2# 13,14
R_B_DM[0..7] 13

R_B_DQS[0..7] 13

R_B_DQS#[0..7] 13

R_B_MA[0..13] 13,14

R_B_SCASA# 13,14
R_B_SRASA# 13,14

T124

R_B_BMWEA# 13,14

D D

QUANTA

Title

Size Document Number Rev

1

2

3

4

5

6

Date: Sheet

COMPUTER

Alviso (DDR)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

749,

8

5

VCCP

12

12

12

C385
.1U_10V

12

C366
.1U_10V

12

C368
.1U_10V

12

C88
.1U_10V

12

C90
.1U_10V

12

C723

*10U_4V_NC

C54

4.7U_10V_0805

12

C388
.1U_10V

12

+

12

+

12

+

12

+

12

12

VCCA_DPLLA

C44
470U_4V

VCCA_DPLLB

C341
470U_4V

C86
150U_2V_L

VCCA_MPLL

C96
150U_2V_L

C380
.1U_10V

C393
.1U_10V

D D

+1_5VRUN

L12

12

10uH

C C

B B

+2.5VRUN

VCCP

D16

2 1

RB751V

+2.5VRUN

A A

1.05V(VTT - FSB POWER SUPPLY)

L16
10uH

L18
BLM11A121S

L19
BLM11A121S

R230 10

VCCP

12

C409

2.2U_6.3V

12

12

12

L31

BLM18PG181SN1

12

12

5

C55
10U_4V

VCCA_HPLL

VCCA_CRTDAC

12

C345
.1U_10V

12

12

C78
10U_4V

ALL PLL POWER
Needs To Have
Clear Power(No
Any Noise)

R231 0

1 2

12

C346

3

.022U

C60 .47U_10V

1 2

C59 .47U_10V

1 2

C84 .22U_10V

1 2

C73 .22U_10V

1 2

4

C56
10U_4V

VCCA_CRTDAC_R

1

C353

2

*22nF_3P_NC

VCCP

VCCP_GMCH_CAP1

VCCP_GMCH_CAP2
VCCP_GMCH_CAP3

VCCP_GMCH_CAP4

4

T29
R29
N29

M29

K29
J29
V28

U28

T28

R28

P28
N28
M28

L28

K28

J28
H28
G28

V27
U27

T27
R27

P27
N27
M27

L27

K27

J27
H27

K26
H26

K25

J25

K24

K23

K22

K21
W20
U20

T20

K20

V19
U19

K19
W18

V18

T18

K18

K17
AC2

AC1

B23
C35
AA1
AA2

F19

E19
G19

H20

K13

J13

K12
W11

V11
U11

T11
R11

P11
N11
M11

L11

K11
W10

V10
U10

T10
R10

P10
N10
M10

K10

J10

Y9
W9
U9
R9

P9
N9
M9

L9

J9
N8
M8
N7
M7
N6
M6

A6
N5
M5
N4
M4
N3
M3
N2
M2

B2

V1
N1
M1
G1

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCC_SYNC
VTT0

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

U11H
ALVISO

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

POWER

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

VCCHV0
VCCHV1
VCCHV2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0

VCC3G1

VCC3G2

VCC3G3

VCC3G4

VCC3G5

VCC3G6

3

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

3

VCC_TVDACA_R
VCC_TVDACB_R
VCC_TVDACC_R

VCC_TVBG_R
VSS_TVBG

VCCD_TVDAC_R
VCCQ_TVDAC_R

Note: All VCCSM pins
shorted internally.

Note: All VCCSM pins
shorted internally.

V1.8_DDR_CAP6
V1.8_DDR_CAP3
V1.8_DDR_CAP4

VCC_DDRDLL

VCC3G_PCIE

VCCA_3GPLL

VCCA_3GBG
VSSA_3GBG

12

C363
.1U_10V

12

C355

.01U

12

C361
.1U_10V

V1.8_DDR_CAP1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

C422 .1U_10V

1 2

C423 .1U_10V

1 2

C91 .1U_10V

1 2

ALL PLL POWER
Needs To Have
Clear Power(No
Any Noise)

12

C45
10U_4V

12

C367
.1U_10V

12

C53
10U_4V

C425 .1U_10V

1 2

C415 .1U_10V

1 2

C428 .1U_10V

1 2

+1_8VSUS

12

C107
10U_4V

12

C373
.1U_10V

+1_5VRUN

+2.5VRUN

+2.5VRUN

12

C106
10U_4V

12

C57

4.7U_10V_0805

+2.5VRUN

2

VCC_TVDACA_R

VCC_TVDACB_R

VCC_TVDACC_R

VCC_TVBG_R

VSS_TVBG

VCCD_TVDAC_R

*22nF_3P_NC

VCCQ_TVDAC_R

*22nF_3P_NC

2

1

12

12

12

12

C338
.1U_10V

C52
.1U_10V

C343
.1U_10V

C47
.1U_10V

12

+

L29
BLM18PG181SN1

L14
BLM18PG181SN1

L30
BLM18PG181SN1

12

12

C74
150U_2V_L

+2.5VRUN

12

12

12

L13
BLM18PG181SN1

C716

2.2U_6.3V

R35 10

D6
RB751V

2 1

L20

12

BLM18PG330SN1

L34

12

BLM18PG330SN1

L33

12

BLM18PG181SN1

12

12

R219 0

1 2

1

3

C340

2

*22nF_3P_NC

R39 0

1 2

1

3

C62

2

*22nF_3P_NC

R226 0

1 2

1

3

C351

2

*22nF_3P_NC

R36 0

1 2

1

3

C58

2

*22nF_3P_NC

R227 0

1 2

3

C352

R38 0

1 2

3

C61

Note: Choose the Inductor with Low-DC loss and
High-Impedance at over 100MHz to isolate
SSN/SN(Switch Noise) from other aggressor .

VCCA_3GPLL

1

2

1

2

VCC_DDRDLL

VCC3G_PCIE

12

C408
.1U_10V

VCCA_3GBG

VSSA_3GBG

12

.022U

12

.022U

VCCD_TVDAC

C347

VCCQ_TVDAC

C64

12

C110

+

100U

12

C76
10U_4V

R278

1 2

12

0.5/F
C376
10U_4V

12

C354
.1U_10V

VCC_TVDACA

12

C339

.022U

VCC_TVDACB

12

C65

.022U

VCC_TVDACC

12

C344

.022U

VCC_TVBG

12

C46

.022U

12

C342
.1U_10V

12

C63
.1U_10V

12

C412
.1U_10V

12

C77
10U_4V

L15
BLM18PG181SN1

VCC3G_PCIE

VCCA_3GPLL_R

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

Alviso (Power)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

1

of

849,

+3VRUN

+3VRUN

+3VRUN

+3VRUN

+3VRUN

+1_5VRUN

+1_5VRUN

+1_5VRUN

+1_5VRUN

5

4

3

2

1

B36

G2

D2

Y1

D D

C C

VSS270

VSS271

VSSALVDS

VSS134

VSS135

B24

D24

VSS269

VSS133

F24

AL24

J2

VSS268

VSS132

J24

AG24

A26

AN24

VSS266

VSS267

VSS130

VSS131

E27

AJ24

G26

E26

VSS264

VSS265

VSS128

VSS129

G27

W27

J26

VSS262

VSS263

VSS126

VSS127

AA27

Y12

VSS_NCTF68

T2

P2

L2

B27

VSS258

VSS259

VSS260

VSS261

VSS122

VSS123

VSS124

VSS125

AJ27

AF27

AB27

AG27

L14

AA13

Y13

AA12

VSS_NCTF64

VSS_NCTF65

VSS_NCTF66

VSS_NCTF67

AE2

AD2

V2

VSS255

VSS256

VSS257

VSS119

VSS120

VSS121

E28

AL27

AN27

P14

N14

M14

VSS_NCTF61

VSS_NCTF62

VSS_NCTF63

A3

AN2

AL2

AH2

VSS251

VSS252

VSS253

VSS254

VSS115

VSS116

VSS117

VSS118

W28

AB28

AA28

AC28

V14

U14

T14

R14

VSS_NCTF57

VSS_NCTF58

VSS_NCTF59

VSS_NCTF60

AB3

AA3

C3

VSS248

VSS249

VSS250

VSS112

VSS113

VSS114

E29

A29

D29

AA14

Y14

W14

VSS_NCTF54

VSS_NCTF55

VSS_NCTF56

H4

C4

AJ3

AC3

VSS244

VSS245

VSS246

VSS247

VSS108

VSS109

VSS110

VSS111

L29

F29

H29

G29

N15

M15

L15

AB14

VSS_NCTF50

VSS_NCTF51

VSS_NCTF52

VSS_NCTF53

U4

P4

L4

VSS241

VSS242

VSS243

VSS105

VSS106

VSS107

V29

P29

U29

T15

R15

P15

VSS_NCTF47

VSS_NCTF48

VSS_NCTF49

E5

AN4

AF4

Y4

VSS237

VSS238

VSS239

VSS240

VSS101

VSS102

VSS103

VSS104

W29

AA29

AD29

AG29

Y15

W15

V15

U15

VSS_NCTF43

VSS_NCTF44

VSS_NCTF45

VSS_NCTF46

AP5

AL5

W5

VSS234

VSS235

VSS236

VSS98

VSS99

VSS100

C30

AJ29

AM29

L16

AB15

AA15

VSS_NCTF40

VSS_NCTF41

VSS_NCTF42

P6

L6

J6

B6

VSS230

VSS231

VSS232

VSS233

VSS94

VSS95

VSS96

VSS97

Y30

AB30

AA30

AC30

R16

P16

N16

M16

VSS_NCTF36

VSS_NCTF37

VSS_NCTF38

VSS_NCTF39

AC6

AA6

T6

VSS227

VSS228

VSS229

VSS91

VSS92

VSS93

D31

AP30

AE30

V16

U16

T16

VSS_NCTF33

VSS_NCTF34

VSS_NCTF35

V7

G7

AJ6

AE6

VSS223

VSS224

VSS225

VSS226

VSS87

VSS88

VSS89

VSS90

F31

E31

H31

G31

AB16

AA16

Y16

W16

VSS_NCTF29

VSS_NCTF30

VSS_NCTF31

VSS_NCTF32

AK7

AG7

AA7

VSS220

VSS221

VSS222

VSS84

VSS85

VSS86

J31

L31

K31

AA17

Y17

R17

VSS_NCTF26

VSS_NCTF27

VSS_NCTF28

L8

E8

C8

AN7

VSS216

VSS217

VSS218

VSS219

VSS80

VSS81

VSS82

VSS83

P31

R31

N31

M31

AA19

AB18

AA18

AB17

VSS_NCTF22

VSS_NCTF23

VSS_NCTF24

VSS_NCTF25

AL8

Y8

P8

VSS213

VSS214

VSS215

U11E
ALVISO

VSS77

VSS78

VSS79

T31

V31

U31

AB20

AA20

AB19

VSS_NCTF19

VSS_NCTF20

VSS_NCTF21

T9

K9

H9

A9

VSS209

VSS210

VSS211

VSS212

VSS

VSS73

VSS74

VSS75

VSS76

W31

AL31

AD31

AG31

AB21

AA21

Y21

R21

VSS_NCTF15

VSS_NCTF16

VSS_NCTF17

VSS_NCTF18

AC9

AA9

V9

VSS206

VSS207

VSS208

VSS70

VSS71

VSS72

Y32

A32

C32

AB22

AA22

Y22

VSS_NCTF12

VSS_NCTF13

VSS_NCTF14

D10

AN9

AH9

AE9

VSS202

VSS203

VSS204

VSS205

VSS66

VSS67

VSS68

VSS69

AB32

AA32

AD32

AC32

Y24

AB23

AA23

Y23

VSS_NCTF8

VSS_NCTF9

VSS_NCTF10

VSS_NCTF11

AA10

Y10

L10

VSS199

VSS200

VSS201

VSS63

VSS64

VSS65

D33

AJ32

AN32

Y25

AB24

AA24

VSS_NCTF5

VSS_NCTF6

VSS_NCTF7

AA11

Y11

H11

F11

VSS196

VSS197

VSS198

VSS60

VSS61

VSS62

F33

E33

H33

G33

AA26

Y26

AB25

AA25

VSS_NCTF2

VSS_NCTF3

VSS_NCTF4

AJ11

AG11

AF11

VSS192

VSS193

VSS194

VSS195

VSS56

VSS57

VSS58

VSS59

J33

L33

K33

AB26

VSS_NCTF0

VSS_NCTF1

AN11

AL11

VSS191

VSS55

N33

M33

B12

VSS189

VSS190

VSS53

VSS54

P33

D12

R33

L12

B14

A14

J12

VSS185

VSS186

VSS187

VSS188

VSS49

VSS50

VSS51

VSS52

T33

V33

U33

P12

N12

M12

VTT_NCTF14

VTT_NCTF15

VTT_NCTF16

VTT_NCTF17

AG14

K14

J14

F14

VSS181

VSS182

VSS183

VSS184

VSS45

VSS46

VSS47

VSS48

W33

AL33

AF33

AD33

V12

U12

T12

R12

VTT_NCTF10

VTT_NCTF11

VTT_NCTF12

VTT_NCTF13

AN14

AL14

AJ14

VSS178

VSS179

VSS180

VSS42

VSS43

VSS44

C34

AB34

AA34

M13

L13

W12

VTT_NCTF7

VTT_NCTF8

VTT_NCTF9

D16

A16

K15

C15

VSS175

VSS176

VSS177

VSS39

VSS40

VSS41

AN34

AH34

AD34

AC34

T13

R13

P13

N13

VTT_NCTF4

VTT_NCTF5

VTT_NCTF6

AL16

K16

H16

VSS171

VSS172

VSS173

VSS174

VSS35

VSS36

VSS37

VSS38

E35

B35

D35

VCCP

W13

V13

U13

VTT_NCTF0

VTT_NCTF1

VTT_NCTF2

VTT_NCTF3

B18

A18

AN17

AJ17

AF17

G17

C17

VSS164

VSS165

VSS166

VSS167

VSS168

VSS169

VSS170

VSS28

VSS29

VSS30

VSS31

VSS32

VSS33

VSS34

J35

L35

F35

K35

H35

G35

M35

All NCTF Pin is to enchance the
solder Joint Characteristic
Thermal Expansion (CTE) mismatch
of the Die to package interface.

AL18

U18

VSS163

VSS27

P35

N35

H19

C19

VSS161

VSS162

VSS25

VSS26

T35

R35

T19

J19

VSS159

VSS160

VSS23

VSS24

V35

U35

W19

VSS157

VSS158

VSS21

VSS22

W35

AN19

AG19

VSS156

VSS20

Y35

AE35

D20

A20

VSS154

VSS155

VSS18

VSS19

C36

AA36

F20

E20

VSS152

VSS153

VSS16

VSS17

AB36

AC36

G20

VSS150

VSS151

VSS14

VSS15

AD36

AK20

V20

VSS149

VSS13

AF36

AE36

F21

C21

VSS147

VSS148

VSS11

VSS12

AJ36

AL36

AF21

VSS145

VSS146

VSS9

VSS10

AN36

A22

AN21

VSS144

VSS8

E37

H37

VSS143

VSS7

E22

D22

VSS142

VSS6

K37

M37

AH22

J22

VSS140

VSS141

VSS4

VSS5

T37

P37

H23

AL22

VSS138

VSS139

VSS2

VSS3

Y37

V37

AF23

VSS136

VSS137

VSS0

VSS1

AG37

U11D

NCTF

W21

ALVISO

VCCSM_NCTF0

VCCSM_NCTF1

VCCSM_NCTF2

VCCSM_NCTF3

VCCSM_NCTF4

VCCSM_NCTF5

VCCSM_NCTF6

VCCSM_NCTF7

VCCSM_NCTF8

VCCSM_NCTF9

VCCSM_NCTF10

VCCSM_NCTF11

VCCSM_NCTF12

VCCSM_NCTF13

VCCSM_NCTF14

VCCSM_NCTF15

VCCSM_NCTF16

VCCSM_NCTF17

VCCSM_NCTF18

VCCSM_NCTF19

VCCSM_NCTF20

VCCSM_NCTF21

VCCSM_NCTF22

VCCSM_NCTF23

VCCSM_NCTF24

VCCSM_NCTF25

VCCSM_NCTF26

VCCSM_NCTF27

VCCSM_NCTF28

VCCSM_NCTF29

VCCSM_NCTF30

VCCSM_NCTF31

VCC_NCTF0

VCC_NCTF1

VCC_NCTF2

VCC_NCTF3

VCC_NCTF4

VCC_NCTF5

VCC_NCTF6

VCC_NCTF7

VCC_NCTF8

VCC_NCTF9

VCC_NCTF10

VCC_NCTF11

VCC_NCTF12

VCC_NCTF13

VCC_NCTF14

VCC_NCTF15

VCC_NCTF16

VCC_NCTF17

VCC_NCTF18

VCC_NCTF19

VCC_NCTF20

VCC_NCTF21

VCC_NCTF22

VCC_NCTF23

VCC_NCTF24

VCC_NCTF25

VCC_NCTF26

VCC_NCTF27

VCC_NCTF28

VCC_NCTF29

VCC_NCTF30

VCC_NCTF31

VCC_NCTF32

VCC_NCTF33

VCC_NCTF34

VCC_NCTF35

VCC_NCTF36

VCC_NCTF37

VCC_NCTF38

VCC_NCTF39

VCC_NCTF40

VCC_NCTF41

VCC_NCTF42

VCC_NCTF43

VCC_NCTF44

VCC_NCTF45

L22

N22

M22

L23

T22

V22

P22

R22

N23

U22

M23

W22

L24

T23

V23

P23

R23

N24

U23

M24

W23

L25

T24

V24

P24

R24

N25

U24

M25

W24

L26

W25

T26

V26

P26

U26

R26

N26

M26

W26

VCCP

AB12

AC12

AD12

AB13

AC13

AD13

AC14

AD14

AC15

AD15

AC16

AD16

AC17

AD17

AC18

AD18

AC19

AD19

AC20

AD20

AC21

AD21

AC22

AD22

AC23

AD23

AC24

AD24

AC25

AD26

AC26

AD25

+1_8VSUS

T25

V25

P25

U25

R25

B B

VCC_NCTF46

VCC_NCTF47

VCC_NCTF48

VCC_NCTF49

VCC_NCTF50

VCC_NCTF51

VCC_NCTF52

VCC_NCTF53

VCC_NCTF54

VCC_NCTF55

VCC_NCTF56

VCC_NCTF57

VCC_NCTF58

VCC_NCTF59

VCC_NCTF60

VCC_NCTF61

VCC_NCTF62

VCC_NCTF63

VCC_NCTF64

VCC_NCTF65

VCC_NCTF66

VCC_NCTF67

VCC_NCTF68

VCC_NCTF69

VCC_NCTF70

VCC_NCTF71

VCC_NCTF72

VCC_NCTF73

VCC_NCTF74

VCC_NCTF75

VCC_NCTF76

VCC_NCTF77

VCC_NCTF78

L21

L20

L19

L17

M17

A A

L18

T17

V17

P17

U17

N17

W17

Y18

P18

N19

R18

N18

M19

M18

P20

Y19

P19

N20

R19

M20

T21

V21

P21

Y20

U21

N21

R20

M21

QUANTA

Title

Size Document Number Rev

5

4

3

2

Date: Sheet

COMPUTER

Alviso (VSS,NCTF)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

1

of

949,

1

VCCRTC

A A

PDD[0..15]19

PDDREQ19
PDIOW#19
PDIOR#19
PIORDY19
PDDACK#19
IRQ1419
PDA119
PDA019
PDCS1#19
PDA219
PDCS3#19

Reset Circuit

B B

(NB/PCI/PCIE)

PLTRST#6,11,16,19,25

PCLK_ICH15

C C

12

R153
100K

SM_INTRUDER#

PDD[0..15]
PDDREQ

PDIOW#
PDIOR#
PIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
PDA2
PDCS3#

4

R422
*33_NC

1 2

C546
*18P_NC

1 2

AC-Terminator

IAC_SYNC_MDC24

D D

IAC_SYNC_AUDIO33

C214
22P

12

C216
*10P_NC

1 2

AC97-MDC & AUDIO

1

R154 20K/F

U17

7SH32

R143 39

12

R142 39

2

+3VSUS

5

2
1

X1,X2 Docking
IAC_SYNC Port X Line R144

C227
1U_10V

C215

.047U

C228 15P

C222 15P

12

PLTRST#_1

12

12

SM_INTRUDER#31

CPUINIT#3

+3VRUN

NMI3
A20M#3

FERR#3

IGNNE#3
INTR3

RCIN#25

GATEA2026

ICH_PME#25

PCIRST#21,23,35

CLKRUN#21,23,25,35

101X2,2X1

4X1

+3VRUN

R144
*1K_NC

1 2

IAC_SYNC

12

2

IAC_BITCLK_ICH

23

AD[0..31]21,23,35

14

STUFF
UNSTUFF

R135

*47_NC

3

CLK_32KX1

32.768KHZ
W2

CLK_32KX2

R133 10K

1 2

C209
*22P_NC

1 2

3

R150
10M

1 2

RTC_RST#
SM_INTRUDER#

1 2

R127 56

PCIRST#
PLTRST#_1

12

IAC_SDATAO

R_FERR#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDCS1#
PDCS3#
PDA0
PDA1
PDA2
PDIOR#
PDIOW#
PIORDY
IRQ14
PDDREQ

PDDACK#

Y1

Y2
AA2
AA3

AA5

AF25
AF23
AF24
AG26
AG24
AF27
AD23
AF22

E2

E5

C2

F5

F3

E9

F2

D6

E6

D3

A2

D2

D5

H3

B4

J5
K2
K5
D4

L6
G3
H4
H2
H5
B3
M6
B2
K6
K3
A5

L1
K4

P6
G6
R2
R5

AF19

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AD16
AE17
AC16
AB17
AC17
AE16
AC14
AF16
AB16
AB14
AB15

R140 39

R141 39

U16A

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN

NMI
A20M#
FERR#
IGNNE#
INTR
INIT#
RCIN#
A20GATE

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PME#
PCICLK
PCIRST#
PLTRST#
CLKRUN#/GPIO32

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#
DA0
DA1
DA2
DIOR#
DIOW#
IORDY
IDEIRQ
DDREQ
DDACK#

ICH6-M

12

12

12

C212
*10P_NC

4

RTC

CPU

LAD1/FB1
LAD2/FB2
LAD3/FB3

LDRQ1#/GPI41

LPC

LFRAME#

CPUPWRGD/GPO49

INIT3_3V#

THRMTRIP#

STPCLK#

CPUSLP#

DPSLP#/TP[2]

DPRSLP#/TP[4]

DEVSEL#

PCI

REQ4#/GPI40

REQ5#/GPI1
REQ6#/GPI0

GNT4#/GPO48
GNT5#/GPO17
GNT6#/GPO16

PIRQE#/GPI2

PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5

SATALED#

SATA0_RXN

SATA0_RXP

IDE

12

C213
10P

4

SATA0_TXN
SATA0_TXP

SATA2_RXN

SATA2_RXP
SATA2_TXN

SATA

SATA2_TXP

SATA_CLKN

SATA_CLKP

SATARBIAS#

SATARBIAS

ACZ_BIT_CLK

ACZ_SYNC

ACZ_RST#

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

ACZ_SDO

AC-97/

AZALIA

IAC_SDATAO_MDC 24

IAC_SDATAO_AUDIO 33 IAC_RESET#_AUDIO 33

5

P2

LAD0

N3
N5
N4

LPC_DRQ0#

N6

LDRQ0#

SMI#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

FRAME#

IRDY#

TRDY#
STOP#

PAR
SERR#
PERR#

PLOCK#

REQ0#
REQ1#
REQ2#
REQ3#

GNT0#
GNT1#
GNT2#
GNT3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

P4
P3

AG25
AE22
AE23
AG27
AE26
AE27
AD27
AE24

J6
H6
G4
G2

J3
A3
J2
C3
J1
E1
G5
E3
C5

L5
B5
M5
B8
F7
E8
B7

C1
B6
F1
C8
E7
F6
D8

N2
L2
M1
L3
D9
C7
C6
M3

AC19
AE3

AD3
AG2
AF2

AD7
AC7
AF6
AG6

AC2
AC1

AG11
AF11

PLOCK#
REQ0#

REQ1#
REQ2#
REQ3#
REQ4#
REQ5#
LAMP_STAT

PIRQA#
PIRQB#
PIRQC#
PIRQD#

LPC_DRQ1#

THERMTRIP#_ICH

R_CPUSLP#

GNT1#
GNT3#

GNT4#

ICH_GPIO2
ICH_GPIO3
ICH_GPIO4
ICH_GPIO5

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

SATABIAS

C/BE0# 21,23,35
C/BE1# 21,23,35
C/BE2# 21,23,35
C/BE3# 21,23,35

FRAME# 21,23,35
IRDY# 21,23,35
TRDY# 21,23,35
DEVSEL# 21,23,35
STOP# 21,23,35
PAR 21,23,35
SERR# 21,23,35
PERR# 21,23,35
PLOCK#

R412 24 . 9 /F

Place within 500mils of ICH6 ball

C10

IAC_SYNC

B9

IAC_RESET#

A10
F11

F10
B10

IAC_SDATAO

C9

R138 39

IAC_RESET#

5

R136 39

LAD0/FWH0 25
LAD1/FWH1 25
LAD2/FWH2 25
LAD3/FWH3 25
LPC_DRQ0# 26
LPC_DRQ1# 25
LFRAME#/FWH4 25

CPUPWRGD 3

R130

1 2

SMI# 3
STPCLK# 3

DPSLP# 3

LAMP_STAT 17

GNT1# 21
GNT3# 23

GNT4# 35

PIRQA#
PIRQB# 23
PIRQC# 21,35
PIRQD# 21,23

SATA_LED# 32

T45PAD
T44PAD

CLK_PCIE_SATA# 15
CLK_PCIE_SATA 15

1 2

IAC_BITCLK_ICH 33

IAC_SDATAIN0 33
IAC_SDATAIN1 24

T43PAD

12

12

12

C211
*10P_NC

6

VCCP

75

+3VRUN

1 2

LAMP_STAT

REQ1# 21
REQ3# 23

REQ4# 35

REQ1 : Card Bus
REQ3 : MINI PCI
REQ4 : BCM4401 LAN

R421 NP boot from FWH,
populate boot from
MiniPCI.

1 2

R421 *1K_NC

IAC_RESET#_MDC 24

12

C210
*10P_NC

6

7

PCI Pullups

+3VRUN

1 2
1 2

REQ3#

SERIRQ

DPRSTP#

R399*0_NC
R126*0_NC

ICH6_GPI711

SERIRQ11,21,25

Install R399 for Dothan-A and don't
install for Dothan-B

Install R126 for Dothan-B and don't
install for Dothan-A

RP9

6
7
8
9

10

10P8R-8.2K

1 2

R125 *56_NC

PCI Pullups

R501
*10K_NC

FRAME#
TRDY#
PLOCK# REQ5#

+3VRUN

REQ1#

6
7
8
9

10

PCI Pullups

PIRQD#

PIRQA# PIRQC#

REQ2#

+3VRUN

ICH_GPIO2
ICH_GPIO3
ICH_GPIO4
ICH_GPIO5

FERR#

Distance between the ICH-6 M and cap
on the "P" signal should be identical
distance between the ICH-6 M and cap
on the "N" signal for same pair.

SATA_RXN0_C

SATA_RXP0_C

SATA_TXN0_C

SATA_TXP0_C

C226 3900P

1 2

C225 3900P

1 2

6
7
8
9

10

RP7

7 8
5 6
3 4
1 2

8P4R-8.2K

1 2

R128 56

SATA_RXN0_C 19

SATA_RXP0_C 19

SATA

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

ICH6-M (CPU,PCI,IDE,SATA,AC97)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

CPUSLP# 3,5
DPRSTP# 3

RP33

10P8R-8.2K

RP34

10P8R-8.2K

+3VRUN

VCCP

SATA_TXN0 19

SATA_TXP0 19

5
4
3
2
1

VCCP

+3VRUN

IRDY#
DEVSEL#
PERR#
IRQ14

5
4
3
2
1

5
4
3
2
1

8

+3VRUN

SERR#
REQ4#

+3VRUN

PIRQB#

REQ0#

STOP#

10 49,

8

of

1

CLK48_USB

12

R124
10

2

3

4

5

6

7

8

12

C200

A A

+3VSUS

7 8
5 6
3 4
1 2

+3VSUS

7 8
5 6
3 4
1 2

B B

+3VRUN

C C

10P

AC terminator

RP36

PDAT_SMB

SMB_LINK_ALERT#

RP35

R132 8.2K

1 2

R152 10K

1 2
1 2

R151 10K

SMBALERT#

ICH_RI#
SYS_RESET#
BATLOW#

8P4R-2.2K

8P4R-10K

IMVP_PWRGD6,39,42

PM_BMBUSY#6

ICH_PWROK31,39

DMI_RXN06
DMI_RXP06

DMI_TXN06
DMI_TXP06

DMI_RXN16
DMI_RXP16

DMI_TXN16
DMI_TXP16

PWRBTN#25

SUSPWROK21,31,39

ICH6_GPI710

EXT_SMI#25

EXT_WAK#25

EXT_SCI#25

T146 PAD

PCLK_SMB15
PDAT_SMB15

THRM#25

T103 PAD
T100 PAD

SPKR33

USB_VD0+19

USB_VD0-19

USB_VD2+30

USB_VD2-30

USB_VD4+32

USB_VD4-32

OC4#32

USB_VD6+32

USB_VD6-32

OC6#32

T126PAD
T128PAD
T130PAD
T132PAD

CLK48_USB

SMBALERT#

ICH_RI#
THRM#
ICH_PWROK

BATLOW#

SUSPWROK
IMVP_PWRGD

EXT_SMI#
EXT_WAK#
EXT_SCI#

OC0#

OC2#

OC4#

OC6#

For USB FDD To Dock

For Bluetooth

To IO/B To IO/B

CLK48_USB15

CLK_PCIE_ICH#15
CLK_PCIE_ICH15

THRM#

ICH_PWROK
SUSPWROK MCH_SYNC#

DPRSLPVR42

R503
100K

1 2

14M_ICH15

R405

*33_NC

1 2

C525

*10P_NC

1 2

D21

USBP0P

C21

USBP0N

C27

OC0#

C19

USBP2P

D19

USBP2N

B26

OC2#

D17

USBP4P

E17

USBP4N

C23

OC4#/GPI9

D15

USBP6P

C15

USBP6N

C25

OC6#/GPI14

A27

CLK48

T25

DMI0_RXN

T24

DMI0_RXP

R27

DMI0_TXN

R26

DMI0_TXP

V25

DMI1_RXN

V24

DMI1_RXP

U27

DMI1_TXN

U26

DMI1_TXP

AD25

DMI_CLKN

AC25

DMI_CLKP

H25

HSIN0

H24

HSIP0

G27

HSON0

G26

HSOP0

K25

HSIN1

K24

HSIP1

J27

HSON1

J26

HSOP1

Y4

SMBCLK

W5

SMBDATA

W6

SMBALERT#/GPI11

T2

RI#

AC20

THRM#

AA1

PWROK

AE20

DPRSLPVR/TP1

V2

BATLOW#/TP0

U1

PWRBTN#

Y3

RSMRST#

AF21

VRMPWRGD

AD19

BM_BUSY#/GPIO6

W3

SUS_STAT#/LPCPD#

V6

SUSCLK

E10

CLK14

F8

SPKR

AE19

GPI7

R1

GPI8

M2

GPI12

R6

GPI13

AB21

GPO19

AD20

GPO21

AD21

GPO23

V3

GPIO24

D12

EE_CS

B12

EE_SHCLK

D11

EE_DOUT

F13

EE_DIN

AC5

RSVD1

AD5

RSVD2

AF4

RSVD3

AG4

RSVD4

AC9

RSVD5

U16B

PCI-EXPRESS

SM&SMI

MISC&GPIO

RESERVED

ICH6-M

USB

DMI

PM

LAN

USBP1P
USBP1N

OC1#
USBP3P
USBP3N

OC3#
USBP5P
USBP5N

OC5#/GPI10

USBP7P
USBP7N

OC7#/GPI15

USBRBIAS

USBRBIAS#

DMI2_RXN

DMI2_RXP
DMI2_TXN
DMI2_TXP

DMI3_RXN

DMI3_RXP
DMI3_TXN
DMI3_TXP

DMI_ZCOMP

DMI_IRCOMP

HSIN2

HSIP2

HSON2

HSOP2

HSIN3

HSIP3

HSON3

HSOP3

SMLINK0
SMLINK1

LINKALERET#

SLP_S3#
SLP_S4#
SLP_S5#

SYS_RESET#

WAKE#

MCH_SYNC#

STP_PCI#/GPO18

STP_CPU#/GPO20

SERIRQ

GPIO25

SATA0GP/GPIO26

GPIO27

GPIO28
SATA1GP/GPIO29
SATA2GP/GPIO30
SATA3GP/GPIO31

GPIO33

GPIO34

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RST#

LAN_CLK

LAN_RSTSYNC

RSVD6
RSVD7
RSVD8
RSVD9

B20
A20
B27
B18
A18
C26
A16
B16
D23
B14
A14
C24
B22
A22

Y25
Y24
W27
W26

AB24
AB23
AA27
AA26

F24
F23

M25
M24
L27
L26

P24
P23
N27
N26

W4
U6
Y5

T4
T5
T6

U2
U5
AG21

AC21
AD22
AB20

P5
AF17
R3
T3
AE18
AF18
AG18

AF20
AC18

E12
E11
C13
C12
C11
E13
V5
F12
B11

AD9
AF8
AG8
U3

OC1#

OC3#

OC5#

OC7#PCLK_SMB

DMI_COMP

SMLINK0
SMLINK1

SMB_LINK_ALERT#

SYS_RESET#
MCH_SYNC#

USB_VD1+ 38
USB_VD1- 38

USB_VD3+ 21
USB_VD3- 21

USB_VD5+ 32
USB_VD5- 32
OC5# 32
USB_VD7+ 32
USB_VD7- 32
OC7# 32

USBRBIAS

DMI_RXN2 6
DMI_RXP2 6
DMI_TXN2 6
DMI_TXP2 6

SLP_S3# 25
SLP_S5# 25

ICH_PCIE_WAKE# 25

STP_PCI# 15
STP_CPU# 4,15,42
SERIRQ 10,21,25

T125PAD
T127PAD
T129PAD
T131PAD
T133PAD
T134PAD

PLTRST#

T136PAD
T137PAD

Cardbus-USB card

DMI_RXN3 6
DMI_RXP3 6
DMI_TXN3 6
DMI_TXP3 6

T99PAD

T101PAD
T102PAD

T104PAD

UAI_8040 19
UAO_8040 19

+3VSUS

R129 22.6/F

12

Place within 500mils
of ICH-6

Place within 500mils
of ICH-6

R396 24.9/F

12

12

R407
33

PLTRST# 6,10,16,19,25

OC0#
OC3#
OC1#
OC2#

10

+1_5VRUN

ICH_PCIE_WAKE#

SMLINK0

SMLINK1

RP31

6
7
8
9

10P8R-10K

R415 680

1 2

R424 10K

1 2

R416 10K

1 2

R131 10K

1 2

5

OC4#

4

OC5#

3

OC7#

2

OC6#

1

+3VRUN

+3VSUS

+3VSUS

D D

QUANTA

Title

Size Document Number Rev

1

2

3

4

5

6

Date: Sheet

COMPUTER

ICH6-M (USB,DMI,LPC)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

11 49,

8

1

L21

+5VSUS

+5VRUN

+3VRUN

+5VALW

+5VSUS

+3VSUS

1 2

BLM41P600SPG

R146 *10_NC

1 2

R145 100

1 2

D10

2 1

RB751V

R406 *10_NC

1 2

R404 10

1 2

D17

2 1

RB751V

+1_5VRUN

A A

B B

12

150U_2V

C218
.1U_10V

1 2

C512
.1U_10V

1 2

+

+1_5V_PCIE

C199

V5REF

V5REF_SUS

Sequence : Reference Volatge ---> Core Volatge

+1_5VRUN +1_5VSUS

+1_5V_SATA_RX

+1_5VRUN

+3VRUN

C C

+3VRUN

+3VSUS

+3VSUS

D D

C203

10U_4V

1 2

C497

.1U_10V

1 2

R395 1R

1 2

R394

1 2

1R

+1_5VRUN

C521

.1U_10V

1 2

C535
.1U_10V

1 2

C520
.1U_10V

1 2

1

BLM11A121S

+3VRUN

.1U_10V

1 2

.1U_10V

1 2

.1U_10V

1 2

L42

C529

C524

C543

12

C208

.1U_10V

1 2

2

C202
.1U_10V

1 2

C219
.1U_10V

1 2

C511
.1U_10V

1 2

+1_5V_SATA_TX

+1_5VRUN

C496

.01U

1 2

2

3

U16C

C204

C516
.1U_10V

1 2

VCCDMIPLL V5REF

.1U_10V

1 2

C544

.1U_10V

1 2

C536
.1U_10V

1 2

AA22

VCC1_5_1

AA23

VCC1_5_2

AA24

VCC1_5_3

AA25

VCC1_5_4

AB25

VCC1_5_5

AB26

VCC1_5_6

AB27

VCC1_5_7

F25

VCC1_5_8

F26

VCC1_5_9

F27

VCC1_5_10

G22

VCC1_5_11

G23

VCC1_5_12

G24

VCC1_5_13

G25

VCC1_5_14

H21

VCC1_5_15

H22

VCC1_5_16

J21

VCC1_5_17

J22

VCC1_5_18

K21

VCC1_5_19

K22

VCC1_5_20

L21

VCC1_5_21

L22

VCC1_5_22

M21

VCC1_5_23

M22

VCC1_5_24

N21

VCC1_5_25

N22

VCC1_5_26

N23

VCC1_5_27

N24

VCC1_5_28

N25

VCC1_5_29

P21

VCC1_5_30

P25

VCC1_5_31

P26

VCC1_5_32

P27

VCC1_5_33

R21

VCC1_5_34

R22

VCC1_5_35

T21

VCC1_5_36

T22

VCC1_5_37

U21

VCC1_5_38

U22

VCC1_5_39

V21

VCC1_5_40

V22

VCC1_5_41

W21

VCC1_5_42

W22

VCC1_5_43

Y21

VCC1_5_44

Y22

VCC1_5_45

AA6

VCC1_5_46

AB4

VCC1_5_47

AB5

VCC1_5_48

AB6

VCC1_5_49

AC4

VCC1_5_50

AD4

VCC1_5_51

AE4

VCC1_5_52

AE5

VCC1_5_53

AF5

VCC1_5_54

AG5

VCC1_5_55

AA7

VCC1_5_56

AA8

VCC1_5_57

AA9

VCC1_5_58

AB8

VCC1_5_59

AC8

VCC1_5_60

AD8

VCC1_5_61

AE8

VCC1_5_62

AE9

VCC1_5_63

AF9

VCC1_5_64

AG9

VCC1_5_65

AC27

VCCDMIPLL

E26

VCC3_3_1

AE1

VCCSATAPLL

AG10

VCC3_3_22

A13

VCCLAN3_3/VCCSUS3_3_1

F14

VCCLAN3_3/VCCSUS3_3_2

G13

VCCLAN3_3/VCCSUS3_3_3

G14

VCCLAN3_3/VCCSUS3_3_4

A11

VCCSUS3_3_1

U4

VCCSUS3_3_2

V1

VCCSUS3_3_3

V7

VCCSUS3_3_4

W2

VCCSUS3_3_5

Y7

VCCSUS3_3_6

A17

VCCSUS3_3_7

B17

VCCSUS3_3_8

C17

VCCSUS3_3_9

F18

VCCSUS3_3_10

G17

VCCSUS3_3_11

G18

VCCSUS3_3_12

ICH6-M

VCC

VCCSUS3_3_20

VCCLAN1_5/VCCSUS1_5_1
VCCLAN1_5/VCCSUS1_5_2

VCCSUS3_3_13
VCCSUS3_3_14
VCCSUS3_3_15
VCCSUS3_3_16
VCCSUS3_3_17
VCCSUS3_3_18
VCCSUS3_3_19

3

VCC1_5_79
VCC1_5_80
VCC1_5_81
VCC1_5_82
VCC1_5_83
VCC1_5_84
VCC1_5_85
VCC1_5_86
VCC1_5_87
VCC1_5_88
VCC1_5_89
VCC1_5_90
VCC1_5_91
VCC1_5_92
VCC1_5_93
VCC1_5_94
VCC1_5_95
VCC1_5_96
VCC1_5_97
VCC1_5_98

VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8

VCC3_3_9
VCC3_3_10
VCC3_3_11

VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20
VCC3_3_21

VCCSUS1_5_1
VCCSUS1_5_2

VCCSUS1_5_3

VCC1_5_67
VCC1_5_68

VCC1_5_69
VCC1_5_70
VCC1_5_71
VCC1_5_72
VCC1_5_73
VCC1_5_74
VCC1_5_75
VCC1_5_76
VCC1_5_77
VCC1_5_78

VCC2_5_2

VCC2_5_4

V5REF1

V5REF2
V5REF_SUS
VCCUSBPLL

VCCRTC

V_CPU_IO1
V_CPU_IO2
V_CPU_IO3

AA19
AA20
AA21
L11
L12
L14
L16
L17
M11
M17
P11
P17
T11
T17
U11
U12
U14
U16
U17
F9

A6
B1
E4
H1
H7
J7
L4
L7
M7
P1

AA12
AA14
AA15
AA17
AC15
AD17
AG13
AG16
AG19
AA10

G19
R7

U7
G8
D24

D25
D26
D27
E20
E21
E22
E23
E24
F20
G20

P7
AB18

A8
AA18

F21
A25

A24
AB3

G10
G11

AB22
AD26
AG23

C16
D16
E16
F15
F16
G15
G16

4

C201
.1U_10V

1 2

C540
.1U_10V

1 2

C220
.1U_10V

1 2

+1_5VRUN

V5REF_SUS

VCCRTC

+1_5VRUN

4

C205
.1U_10V

1 2

+3_3V_PCI

C539
.1U_10V

1 2

+3_3V_ICH

C523
.1U_10V

1 2

VCCRTC

.1U_10V

1 2

C547

C522

C553

.1U_10V

1 2

C528
.1U_10V

1 2

C541
.1U_10V

1 2

C517
.1U_10V

1 2

C550
.1U_10V

1 2

C518

.1U_10V

1 2

C207

.1U_10V

1 2

C206

.1U_10V

1 2

.01U

.1U_10V

1 2

1 2

+3VRUN

+3VRUN

C542

.1U_10V

1 2

C538

.1U_10V

1 2

+3VSUS

VCCP

3.3V Can drop to 2.0V
min. in G3 state)

5

C515

5

+1_5VSUS

+1_5VRUN

+2.5VRUN

C217

.01U

1 2

+1_5VRUN

+1_5VRUN

6

U16D

A1

VSS001

A12

VSS002

A15

VSS003

A19

VSS004

A21

VSS005

A23

VSS006

A26

VSS007

A4

VSS008

A7

VSS009

A9

VSS010

AA11

VSS011

AA13

VSS012

AA16

VSS013

AA4

VSS014

AB1

VSS015

AB10

VSS016

AB19

VSS017

AB2

VSS018

AB7

VSS019

AB9

VSS020

AC10

VSS021

AC12

VSS022

AC22

VSS023

AC23

VSS024

AC24

VSS025

AC26

VSS026

AC3

VSS027

AC6

VSS028

AD1

VSS029

AD10

VSS030

AD15

VSS031

AD18

VSS032

AD2

VSS033

AD24

VSS034

AD6

VSS035

AE10

VSS036

AE11

VSS037

AE12

VSS038

AE2

VSS039

AE21

VSS040

AE25

VSS041

AE6

VSS042

AE7

VSS043

AF1

VSS044

AF10

VSS045

AF12

VSS046

AF26

VSS047

AF3

VSS048

AF7

VSS049

AG1

VSS050

AG12

VSS051

AG14

VSS052

AG17

VSS053

AG20

VSS054

AG22

VSS055

AG3

VSS056

AG7

VSS057

B13

VSS058

B15

VSS059

B19

VSS060

B21

VSS061

B23

VSS062

B24

VSS063

B25

VSS064

C14

VSS065

C18

VSS066

C20

VSS067

C22

VSS068

C4

VSS069

D1

VSS070

D10

VSS071

D13

VSS072

D14

VSS073

D18

VSS074

D20

VSS075

D22

VSS076

D7

VSS077

E14

VSS078

E15

VSS079

E18

VSS080

E19

VSS081

E25

VSS082

F17

VSS083

F19

VSS084

F22

VSS085

F4

VSS086

7

GND

ICH6-M

VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172

G1
G12
G21
G7
G9
H23
H26
H27
J23
J24
J25
J4
K1
K23
K26
K27
K7
L13
L15
L23
L24
L25
M12
M13
M14
M15
M16
M23
M26
M27
M4
N1
N11
N12
N13
N14
N15
N16
N17
N7
P12
P13
P14
P15
P16
P22
R11
R12
R13
R14
R15
R16
R17
R23
R24
R25
R4
T1
T12
T13
T14
T15
T16
T23
T26
T27
T7
U13
U15
U23
U24
U25
V23
V26
V27
V4
W1
W23
W24
W25
W7
Y23
Y26
Y27
Y6
E27

8

QUANTA

Title

Size Document Number Rev

6

Date: Sheet

COMPUTER

ICH6-M (POWER&GND)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

12 49,

8

1

+1_8VSUS

R_A_MD0
R_A_MD1

R_A_DQS#0

A A

B B

CKE06,14 CKE26,14 CKE3 6,14

R_A_BS2#7,14

R_A_BS0#7,14

R_A_BMWEA#7,14

R_A_SCASA#7,14

SM_CS1#6,14
M_ODT16,14

C C

D D

+3VRUN

R_A_DQS0
R_A_MD2

R_A_MD3
R_A_MD8

R_A_MD9
R_A_DQS#1

R_A_DQS1
R_A_MD10 R_B_MD14

R_A_MD11

R_A_MD16
R_A_MD17

R_A_DQS#2
R_A_DQS2

R_A_MD18
R_A_MD19

R_A_MD24
R_A_MD25

R_A_DM3

R_A_MD26
R_A_MD27

CKE0

R_A_BS2#
R_A_MA12

R_A_MA9
R_A_MA8

R_A_MA5
R_A_MA3
R_A_MA1

R_A_MA10
R_A_BS0#

R_A_BMWEA#
R_A_SCASA#

SM_CS1#
M_ODT1
R_A_MD32

R_A_MD33
R_A_DQS#4

R_A_DQS4
R_A_MD34

R_A_MD35
R_A_MD40

R_A_MD41
R_A_DM5
R_A_MD42 R_A_MD46

R_A_MD43
R_A_MD48

R_A_MD49

R_A_DQS#6
R_A_DQS6

R_A_MD50

R_A_MD56
R_A_MD57

R_A_DM7
R_A_MD58

R_A_MD59

CGCLK_SMB

1

SMDDR_VREF

JDIM1

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

PC4800 DDR2

CLOCK 0,1,2

2

+1_8VSUS

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

SO-DIMM (200P)

PC4800 DDR2 SDRAM

84

A15

86

A14

88

VDD11

90

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

2

R_A_MD4
R_A_MD5

R_A_DM0
R_A_MD6

R_A_MD7
R_A_MD12

R_A_MD13
R_A_DM1

CLK_SDRAM0

CLK_SDRAM0#

R_A_MD14
R_A_MD15

R_A_MD20
R_A_MD21

R_A_DM2
R_A_MD22

R_A_MD23
R_A_MD28

R_A_MD29
R_A_DQS#3

R_A_DQS3
R_A_MD30

R_A_MD31
CKE1

R_A_MA11
R_A_MA7
R_A_MA6

R_A_MA4
R_A_MA2
R_A_MA0

R_A_BS1#
R_A_SRASA#

SM_CS0#

M_ODT0
R_A_MA13

R_A_MD36
R_A_MD37

R_A_DM4
R_A_MD38

R_A_MD39
R_A_MD44

R_A_MD45
R_A_DQS#5

R_A_DQS5

R_A_MD47
R_A_MD52

R_A_MD53
CLK_SDRAM1

CLK_SDRAM1#
R_A_DM6
R_A_MD54

R_A_MD55R_A_MD51
R_A_MD60

R_A_MD61
R_A_DQS#7

R_A_DQS7
R_A_MD62

R_A_MD63

R466
10K

1 2

3

CLK_SDRAM0 6
CLK_SDRAM0# 6

CKE1 6,14

R_A_BS1# 7,14
R_A_SRASA# 7,14
SM_CS0# 6,14

M_ODT0 6,14

CLK_SDRAM1 6
CLK_SDRAM1# 6

R467
10K

1 2

SMbus address A0

3

R_A_DM[0..7] 7
R_A_MD[0..63] 7
R_A_DQS[0..7] 7
R_A_DQS#[0..7] 7
R_A_MA[0..13] 7,14

R_B_BS2#7,14

R_B_BS0#7,14

R_B_BMWEA#7,14

R_B_SCASA#7,14

SM_CS3#6,14
M_ODT36,14

CGDAT_SMB15,17
CGCLK_SMB15,17

+3VRUN

4

+1_8VSUS +1_8VSUS

SMDDR_VREF

R_B_MD0
R_B_MD1

R_B_DQS#0
R_B_DQS0

R_B_MD2
R_B_MD3

R_B_MD8
R_B_MD9

R_B_DQS#1
R_B_DQS1

R_B_MD10
R_B_MD11

R_B_MD16
R_B_MD17

R_B_DQS#2
R_B_DQS2

R_B_MD18
R_B_MD19

R_B_MD24
R_B_MD25

R_B_DM3

R_B_MD26
R_B_MD27

CKE2

R_B_BS2#
R_B_MA12

R_B_MA9
R_B_MA8

R_B_MA5
R_B_MA3
R_B_MA1

R_B_MA10
R_B_BS0#

R_B_BMWEA#
R_B_SCASA#

SM_CS3#
M_ODT3
R_B_MD32

R_B_MD33
R_B_DQS#4

R_B_DQS4
R_B_MD34

R_B_MD35
R_B_MD40

R_B_MD41
R_B_DM5
R_B_MD42 R_B_MD46

R_B_MD43
R_B_MD48

R_B_MD49

R_B_DQS#6
R_B_DQS6

R_B_MD50

R_B_MD56
R_B_MD57

R_B_DM7
R_B_MD58

R_B_MD59

CGDAT_SMBCGDAT_SMB
CGCLK_SMB

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

JDIM2

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

PC4800 DDR2_R

5

SMDDR_VREFSMDDR_VREF

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

SO-DIMM (200P)

PC4800 DDR2 SDRAM

84

A15

86

A14

88

VDD11

90

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

CLOCK 3,4,5

CKE 2,3CKE 0,1

4

5

+3VRUN

R_B_MD4
R_B_MD5

R_B_DM0
R_B_MD6

R_B_MD7
R_B_MD12

R_B_MD13
R_B_DM1

CLK_SDRAM3

CLK_SDRAM3#

R_B_MD15

R_B_MD20
R_B_MD21

R_B_DM2
R_B_MD22

R_B_MD23
R_B_MD28

R_B_MD29
R_B_DQS#3

R_B_DQS3
R_B_MD30

R_B_MD31
CKE3

R_B_MA11
R_B_MA7
R_B_MA6

R_B_MA4
R_B_MA2
R_B_MA0

R_B_BS1#
R_B_SRASA#

SM_CS2#

M_ODT2
R_B_MA13

R_B_MD36
R_B_MD37

R_B_DM4
R_B_MD38

R_B_MD39
R_B_MD44

R_B_MD45
R_B_DQS#5

R_B_DQS5

R_B_MD47
R_B_MD52

R_B_MD53
CLK_SDRAM4

CLK_SDRAM4#
R_B_DM6
R_B_MD54

R_B_MD55R_B_MD51
R_B_MD60

R_B_MD61
R_B_DQS#7

R_B_DQS7
R_B_MD62

R_B_MD63

R468
10K

1 2

6

R_B_DM[0..7] 7
R_B_MD[0..63] 7
R_B_DQS[0..7] 7
R_B_DQS#[0..7] 7
R_B_MA[0..13] 7,14

CLK_SDRAM3 6
CLK_SDRAM3# 6

R_B_BS1# 7,14
R_B_SRASA# 7,14
SM_CS2# 6,14

M_ODT2 6,14

CLK_SDRAM4 6
CLK_SDRAM4# 6

R469
10K

1 2

SMbus address A4

6

7

+1_8VSUS

8

Place these Caps near So-Dimm1.

12

12

C662

C663

2.2U_6.3V

2.2U_6.3V

+1_8VSUS

Place these Caps near So-Dimm1.

12

12

C668

C667

.1U_10V

.1U_10V

SMDDR_VREF

12

12

C672

C671

2.2U_6.3V

.1U_10V

12

2.2U_6.3V

12

C669
.1U_10V

C664

12

C670
.1U_10V

+3VRUN

12

12

C665

2.2U_6.3V

C673

2.2U_6.3V

12

C666

2.2U_6.3V

12

C674

.1U_10V

Place these Caps near So-Dimm1.
No Vias Between the Trace of
PIN to CAP.

+1_8VSUS

Place these Caps near So-Dimm2.

12

C675

2.2U_6.3V

+1_8VSUS

Place these Caps near So-Dimm2.

12

C680
.1U_10V

SMDDR_VREF

12

C684
.1U_10V

12

C676

2.2U_6.3V

12

C681
.1U_10V

12

C685

2.2U_6.3V

12

2.2U_6.3V

12

C682
.1U_10V

C677

12

C683
.1U_10V

+3VRUN

12

2.2U_6.3V

12

C686

2.2U_6.3V

C678

12

C679

2.2U_6.3V

12

C687

.1U_10V

Place these Caps near So-Dimm2.
No Vias Between the Trace of
PIN to CAP.

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

System DRAM Expansion (200P-DDR_SODIMM X 2)

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

13 49,

8

1

2

3

4

5

6

7

8

DDRII DUAL CHANNEL A,B.

A A

SMDDR_VTERM

12

C688

.1U_10V

DDRII A CHANNEL DDRII B CHANNEL

R_A_MA[0..13] 7,13 R_B_MA[0..13] 7,13

No Vias Between the Trace of PIN to CAP. No Vias Between the Trace of PIN to CAP.

12

C689

.1U_10V

12

C690

.1U_10V

12

C691

.1U_10V

12

C692

.1U_10V

12

C693

.1U_10V

12

C694

.1U_10V

12

C695

.1U_10V

12

C696

.1U_10V

12

C697

.1U_10V

12

C698

.1U_10V

12

C699

.1U_10V

12

C700

.1U_10V

SMDDR_VTERM

12

C701

.1U_10V

12

C702

.1U_10V

12

C703

.1U_10V

12

C704

.1U_10V

12

C705

.1U_10V

12

C706

.1U_10V

12

C707

.1U_10V

12

C708

.1U_10V

12

C709

.1U_10V

12

C710

.1U_10V

12

C711

.1U_10V

12

C712

.1U_10V

12

C713

.1U_10V

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM. Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

R_A_MA7
R_A_MA11
R_A_MA4
R_A_MA6

R_A_SRASA#7,13

B B

C C

R_A_BS1#7,13

M_ODT06,13

R_A_BS2#7,13

R_A_BS0#7,13

R_A_BMWEA#7,13

R_A_SCASA#7,13

R_A_SRASA#
R_A_BS1#

R_A_MA13
M_ODT0
R_A_BS2#
R_A_MA12
R_A_MA9
R_A_MA8
R_A_MA5
R_A_MA3

R_A_MA10
R_A_BS0#
R_A_BMWEA#
R_A_SCASA#
R_A_MA0
R_A_MA2

R_A_MA1

M_ODT16,13

SM_CS0#6,13

SM_CS1#6,13

M_ODT1

CKE06,13

CKE16,13

SM_CS0#

SM_CS1#

2
4
2
4
2
4

2
4
2
4
2
4
2
4

2
4
2
4
2
4

R470 56

1 2

R472 56

1 2

R474 56

1 2

R476 56

1 2

R479 56

1 2

R481 56

1 2

1
3
1
3
1
3

1
3
1
3
1
3
1
3

1
3
1
3
1
3

RP41 4P2R-S-56
RP43 4P2R-S-56
RP45 4P2R-S-56

RP47 4P2R-S-56
RP49 4P2R-S-56
RP51 4P2R-S-56
RP53 4P2R-S-56

RP55 4P2R-S-56
RP57 4P2R-S-56
RP59 4P2R-S-56

CKE0

CKE1

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

R_B_SRASA#7,13

R_B_BS1#7,13

R_B_BS0#7,13

R_B_BMWEA#7,13

SM_CS3#6,13

M_ODT26,13

R_B_SCASA#7,13

R_B_SRASA#
R_B_BS1#
R_B_MA12
R_B_MA9
R_B_MA8
R_B_MA5

R_B_MA3
R_B_MA1
R_B_MA10
R_B_BS0#
R_B_BMWEA#
SM_CS3#
R_B_MA7
R_B_MA11

R_B_MA4
R_B_MA6
R_B_MA0
R_B_MA2
R_B_MA13
M_ODT2

R_B_BS2#7,13

M_ODT36,13

CKE26,13

CKE36,13

SM_CS2#6,13

2

RP42 4P2R-S-56

4
2

RP44 4P2R-S-56

4
2

RP46 4P2R-S-56

4

2

RP48 4P2R-S-56

4
2

RP50 4P2R-S-56

4
2

RP52 4P2R-S-56

4
2

RP54 4P2R-S-56

4

2

RP56 4P2R-S-56

4
2

RP58 4P2R-S-56

4
2

RP60 4P2R-S-56

4

CKE2

CKE3

R471 56

1 2

R473 56

1 2

R475 56

1 2

R477 56

1 2

R478 56

1 2

R480 56

1 2

R_B_BS2#

M_ODT3

SM_CS2#

R_B_SCASA#

1
3
1
3
1
3

1
3
1
3
1
3
1
3

1
3
1
3
1
3

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERMSMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

D D

QUANTA

Title

Size Document Number Rev

1

2

3

4

5

6

Date: Sheet

COMPUTER

DDR RES.ARRAY

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

14 49,

8

1

FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33

2

3

4

5

6

7

8

Place these termination to
close CK410M. Cause those
Pin-out is for Cu rrent-Mode.

0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33

A A

1 1 0 400 100 33
1 1 1 RSVD 100 33

R368 *10K_NC

1 2

R351 *0_N C

1 2

R337 *0_NC

1 2

SELPSB0_CLK

SELPSB1_CLK

SELPSB2_CLK

Depop R337 for Dothan-B

B B

+3VRUN

L36

1 2

ACB2012L-120

120 ohms@100Mhz

R358 10K

1 2

R350 *0_NC

1 2

R342 *10K_NC

1 2

CLKVDD

12

12

C454

C434

.047U

.047U

12

C455
.047U

VCCP

+3VRUN

12

C436
.047U

CLK48_USB11

12

C421

4.7U_10V_0805

SELPSB1_CLK4,6
SELPSB2_CLK4,6

C448 27P

12

C451 27P

12

CLK_EN#17,42

STP_PCI#11

STP_CPU#4 ,11,42

SMbus address D2

R367 33

1 2

12

Y3

14.318MHZ

SELPSB0_CLK
SELPSB1_CLK
SELPSB2_CLK

VDDREF_CR

CLKVDD
CLKVDD1

CLKVDD

VDD48_CR

R338 475/F

1 2

XIN

XOUT

CLK_EN#

CGCLK_SMB
CGDAT_SMB

IREF

Iref=5mA, Ioh=4*Iref

RP29

R346 2.2

1 2

+3VRUN

C C

L37
ACB2012L-120

120 ohms@100Mhz

CLKVDD1

12

R356 2.2

1 2

R336 1R

1 2

VDDA_CR

12

C457
.047U

VDD48_CR

VDDREF_CR

12

C435
.047U

12

C458
.047U

12

C456
.047U

12

C446

4.7U_10V_0805

12

C459

4.7U_10V_0805

12

C460

4.7U_10V_0805

12

C437
.047U

DOT966
DOT96#6

4
2

4P2R-S-33

R_DOT96

3

R_DOT96#

1

SMBus

PDAT_SMB11

U30

50

XTAL_IN

49

XTAL_OUT

10

VTT_PWRGD#/PD#

55

PCI_STOP#

54

CPU_STOP#

46

SCLK

47

SDATA

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

48

VDD_REF

42

VDD_CPU

1

VDD_PCI_1

7

VDD_PCI_2

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

11

VDD_48

39

IREF

14

DOT96

15

DOT96#

VDDA_CR

GND_48

13

+3VRUN

3 1

Q37 2N7002

+3VRUN

37

VDDA

CPU2#_ITP/SRC7#

CK-410M

GND_REF

GND_PCI_26GND_SRC29GND_CPU

GND_PCI_1

2

51

45

2

38

REF

VSSA

CPU0

CPU0#

CPU1

CPU1#

CPU2_ITP/SRC7

SRC6

SRC6#

SRC5

SRC5#

SRC4

SRC4#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

PCI5
PCI4
PCI3
PCI2

PCIF1

PCIF0/ITP_EN

ICS954201/CY28411

250mA ( MAX. )

2

4

RP25
4P2R-S-10K

1

3

CGDAT_SMB

14M_REF

52

R_HCLK_MCH

44

R_HCLK_MCH#

43

R_HCLK_CPU

41

R_HCLK_CPU#

40

R_HCLK_ITP

36

R_HCLK_ITP#

35
33

32

R_MCH_3GPLL

31

R_MCH_3GPLL#

30

R_PCIE_SATA

26

R_PCIE_SATA#

27

R_PCIE_ICH

24

R_PCIE_ICH#

25
22

23

R_DOT100_SS DOT100_SS

19
20

17
18

R_PCLK_PCM

5

R_PCLK_SIO

4

R_PCLK_DOCK

3

R_PCLK_MINI

56

R_PCLK_ICH

9

R_PCLK_LAN

8

CGDAT_SMB 13,17

Split Power Plane to avoid SSN/SN.

2

D D

PCLK_SMB11

3 1

Q36 2N7002

These are for backdrive issue

1

2

3

4

CGCLK_SMB

CGCLK_SMB 13,17

5

1 2

+3VRUN

R357
*10K_NC

R333 49.9/F

1 2

R332 49.9/F

1 2

R335 49.9/F

1 2

R334 49.9/F

1 2

R331 49.9/F

1 2

R330 49.9/F

1 2

RP28

4P2R-S-33

1 2
1 2
1 2

RP24

3
1

4P2R-S-33
RP23

3
1

4P2R-S-33
RP22

3
1

4P2R-S-33

RP21

3
1

4P2R-S-33
RP26

1
3

4P2R-S-33
RP27

1
3

4P2R-S-33

1
3

R354 39
R343 39
R492 39

6

4
2

4
2

4
2

4
2

2
4

2
4

2
4

R353 39
R355 39
R352 39

DOT100#_SSR_DOT100#_SS

1 2
1 2
1 2

R339 24

1 2

R340 24

1 2

R341 24

1 2

HCLK_MCH 5
HCLK_MCH# 5

HCLK_CPU 3
HCLK_CPU# 3

HCLK_ITP 3
HCLK_ITP# 3

CLK_MCH_3GPLL 6
CLK_MCH_3GPLL# 6

CLK_PCIE_SATA 10
CLK_PCIE_SATA# 10

CLK_PCIE_ICH 11
CLK_PCIE_ICH# 11

DOT100_SS 6
DOT100#_SS 6

PCLK_PCM 21
PCLK_SIO 26
PCLK_DOCK 38
PCLK_MINI 23
PCLK_ICH 10
PCLK_LAN 35

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_ICH
CLK_PCIE_ICH#

DOT96
DOT96#

DOT100_SS
DOT100#_SS

12

C429
*10P_NC

R329 49.9/F

1 2

R328 49.9/F

1 2

R360 49.9/F

1 2

R359 49.9/F

1 2

R362 49.9/F

1 2

R361 49.9/F

1 2

R366 49.9/F

1 2

R365 49.9/F

1 2

R364 49.9/F

1 2

R363 49.9/F

1 2

12

C430
*10P_NC

CLK_SSC_IN 17

14M_SIO 26

14M_ICH 11

Place these termination to
close CK410M. Cause those
Pin-out is for Cu rrent-Mode.

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

CLOCK GENERATOR

Tahiti(DM3L) 1A

星期二

29, 2005

三月

7

of

15 49,

8