Dell Alienware Area 51M Schematics

A

1 1

B

C

D

E

LA-G881P Coffee Lake-S 95W CNL PCH-H with nVIDIA N18E

2 2

REV : 1.0

2018.12.14

@ : Nopop Component EMI@,ESD@,RF@ : EMI/ESD/RF part CONN@ : Connector Component @EMI@,@ESD@,@RF@ : Total debug Component

3 3

CNVI@:For WLAN NOCP@/OCP@:For Hinge up OCP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page LA-G881P

LA-G881P

E

1.0

1 101Tuesday, January 08, 201 9

1.0

A

HDMI 2.0

P.30

I2C

DP4+3

DP 1.4

eDP 1.3

I2C/USB2

Thunderbolt Alpine Ridge SP

USB3.1 TypeC connector

1 1

USB3.1 TypeC connector

USB PD

Mini DP connector

HDMI connector

eDP panel support G-SYNC

CYPD4126

P.26

P.27

P.25

CIO/USB3.1

USB PD

TPS65982DC

B

DGFF CARD N18E-G1 N18E-G2 N18E-G3

P.28~ 29P.30

P.46

PEG(Gen3)x8 port8~port15

DP 1.4 (DDI 1) DP 1.4 (DDI 2)

PCIE(Gen3)x4 port21~port24

C

Block Diagram

P.7~1 5

Intel CPU Coffee Lake-S LGA881P 95W

FFS KXCNL-1010

Memory Bus 2DPC

1.2V DDR4 2133 MHz

P.36

D

DDR4-SODIMM x4

E

P.12~ 15

PEG(Gen3)x4

P.31

Caldera connector

2 2

3 3

RJ45 connector

P.33

Transformer QVPA2014R

2.5GB

P.33

30 pin connector with cable 2.5 HDD x1

PCIe re-driver DS80PCI402

2.5 Gigabit LAN RTL8125-CG

M.2 2230 WiFi + BT Intel/Killer

SSD1 M.2 2280 PCIe+SATA

SSD2 M.2 2280 PCIe+SATA

SPI ROM 128Mbit

P.32

P.33

P.34

P.35

P.36

P.17

P.39

Touch pad

port4~port7

USB3.0 port8 USB2.0 port3

PCI-E port15

PCI-E port16 USB2.0 port14 CNVi

PCI-E port 17~20 SATA 3.0

PCI-E port 09~12 SATA3.0

SATA3.0 option:HDD

SPI

I2C

DMI x 4

Intel PCH CNL PCH-H BGA 874

Z390

P.16~ 22

USB2.0 port4

USB2.0 port10

USB2.0 port7

USB3.0 port6 USB2.0 port1

USB3.0 port7 USB2.0 port2

USB3.0 port5 USB2.0 port8

USB2.0 port9

ISH

HD Audio

Audio codec Realtek ALC3282

I2S

AMP TI TAS2557

AlienFX / ELC , STM32F070CB

Keyboard

Digital camera(with digital MIC)

USB connector 1 , left side USB3.0(Gen1) with power share

USB TypeA connector 2 USB3.0(Gen1) right side

USB TypeA connector 3 USB3.0(Gen1) Right side

Tobii (17" only)

Gyro+Accel Sensor

digital MIC

Headphone/MIC Global headset combo JACK

Headphone/MIC Retaskable combo JACK

Speaker

P.38

P.41

P.26

P.27

P.25

P.23

Head/B

Tron/B

PWR/B

P.46

P.39

AMP TI TAS2557

DC in Battery

3V/5V

4 4

System

1.2V

1.00V

2.5V

CPU Vcore

dGPU Core

Charger

dGPU

1.35V

A

B

PS2

KC3810

P.42

eSPI Bus

I2C

FAN1 FAN2

ENE KB95 42QB

P.43

C

SMBI2C

Thermal Sensor

SPI

AMP TI TAS2557

AMP TI

P.37

TAS2557

Hall Sensor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

2018/03/29 2019/03/29

Speaker

Compal Secret Data

Deciphered Date

D

Audio/B

Compal Electronics, Inc.

Title

Block Diagrams

Size

Document Number Re v

LA-G881P

Date : Sheet of

E

2 101Tuesday, January 08, 2019

1.0

Board ID Table for AD channel

Vcc 3.3V +/- 1%

100K +/- 1%Ra

Board ID

Rb V min

0

0 0.000 V

1

12K +/- 1%

2

15K +/- 1%

3

20K +/- 1% 27K +/- 1%

4

33K +/- 1%

5

43K +/- 1%

6 7 56K +/- 1% 8975K +/- 1% 1.398V

Board ID table

PCB Revision

NV

0

EVT

1

DVT-1

2

DVT-2

3

Pilot

Voltage Rails

Power Plane Description

VIN

Adapter power supply

BATT+

Battery power supply

+19VB

AC or battery power rail for power circuit

+VCC_COR E

Core voltage for CPU

Sliced graphics power rail

+VCC_GT +0.6VS_VTT DDR +0.6VS power rail for DDR terminator +1VALW System +1VALW power rail +1V_PRI M System +1V ALW power rail +VCCI O +1.0VS IO power rail +VGA_PCI E +1.0VS power rail for GPU +MEM_GFX +1.5VS power rail for GPU

DDR-IV +1.2V power rail+1.2V_V DDQ

+1VS_VCCST

+1.0V power rail for CPU

+1VS_VCCSTG

+1.0VS power rail for CPU +3VALW System +3VALW always on power rail +3VLP +19VB to +3VLP power rail for suspend power +3VALW_DS W +3VALW power for PCH DSW rails +3V_LAN +3VALW power for LAN power rails +3VS

System +3VS power rail +1.8VALW +1.8VALW power rail for PCH

+3VS power rail for GPU+3VGS +5VALW

System +5VALW power rail +5VS System +5VS power rail

RTC power

+3VL_RTC

System Agent power rail

+VCC_SA

Note : O N* means that this power plane is ON only with AC power available, otherwise it is OFF

V typ

AD_BID

AD_BIDVAD_BID

0.000V 0.300V

0.347V

0.423V 0.430V

0.541V

0.691V

0.807V

0.978V 0.992V

1.169V

1.634V 1.667V

0.360V

0.354V

0.438V

0.550V

0.559V

0.713V

0.702V

0.819V

0.831V

1.006V

1.200V

1.185V

1.414V 1.430V0x65 - 0x76

S0S3S4 / S5

N/A N/A N/A ON ON ON

ON ON ON ON ON ON ON ON ON ON ON

ON

ON ON ON ON ON

max

EC AD3

0x00 - 0x13 0x14 - 0x1E 0x1F - 0x25 0x26 - 0x30 0x31 - 0x3A 0x3B - 0x45 0x46 - 0x54 0x55 - 0x64

0x77 - 0x87100K +/- 1% 1.650V

N/A

OFF

ON*ONON ON*

ON

OFF

ON

OFF

ON

OFF

ON*

ON

ON*

ON

ON*

ON

OFF

ON*

ON

OFF

ON

OFFOFFON

PCH-H Z390

HSIO

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

USB3.1

10

2 3 4 5 6 7 8 9

PCIe SATA3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Function

JUSB3 JUSB1(Powershare) JUSB2 Caldera

JSSD2 , 2280 SATA/PCIe x4

0a 1a

JHDD

0b 1b

LAN

2 3

WLAN

4 5

JSSD1 , 2280 SATA/PCIe x4

Thunderbolt

Function

USB2

1

JUSB1(Powershare)1

2

JUSB2

3

Caldera

4

ELC 5 6 7

Camera 8

JUSB3 9

Tobii

10

Per-key

Thunderbolt PD

11 12 13

Bluetooth

14

Symbol Note :

A

Digital Ground

Analog Ground

1K

2.2K

1K

499

1K

2.2K

+3VALW

+3VS

SMBUS Address [ 0x6A]

11

PI6CEQ20200

10

+3V_PCH

N-MOS N-MOS

+3VS

0 ohm

SCL

0 ohm

SDA 100 ohm 100 ohm

0 ohm PUS1 0 ohm

0 ohm PUS2 0 ohm

AMP TAS2557

EC_SMB_CK2

EC_SMB_DA 2

4 3

5 6

22 21

B5

A5

50 49

11 10

PU703 Power Charger

PBATT1

ISL95338

UT4

TPS65982

UT6

DS80PCI402S Q

UT7

PI6CEQ20200

SMBUS Address [?]

N-MOS N-MOS

SMBUS Address [ 0x12]

SMBUS Address [ 0x16]

SMBUS Address [ 0x90]

SMBUS Address [ 0x92]

SMBUS Address [ 0x70]

SMBUS Address [0x]

SMBUS Address [ 0x9A]

BE26

PCH_SMBCLK

BF26

1 1

Cannon Lak e PCH-H

ENE KB9542Q B

PCH_SMBDATA

BF25

SML0CLK

BE24

SML0DATA

BF27

SML1CLK

BE27

SML1DATA

79

EC_SMB_CK2

80

EC_SMB_DA 2

77

EC_SMB_CK1

78

EC_SMB_DA 1

17

EC_ESB_CLK

18

EC_ESB_DAT

119/120/12 6

AMP_SPI_MISO/AMP_SPI_MOSI/A MP_SPI _SCL K

128

AMP_SPI_CS_L1

68

AMP_SPI_CS_L2

34

AMP_SPI_CS_R1

15

AMP_SPI_CS_R2

4.7K

VGA_SMB_CK2 VGA_SMB_DA2

4

Free Fall Sensor

SMBUS Address [ 0x1D]

6

253

DIMM1

SMBUS Address [ 0xA0]

254

253

DIMM2

SMBUS Address [ 0xA2]

254

253

DIMM3

SMBUS Address [ 0xA4]

254

253

DIMM4

SMBUS Address [ 0xA6]

254

15

JTP

SMBUS Address [0x2C]

16

10

U2407

SMBUS Address [ 0x9A]

Thermal sensor

9

+3VS

U2408

SMBUS Address [ 0x98]

8

Thermal sensor

7

+3VS

UG9

BJ8

SMBUS Address [0x9E]

GPU

BH8

UM8

SMBUS Address [0xB2]

PCIE redriver

50 49

16

JPK

SMBUS Address [0xC2]

Per-key KB

17

4.7k

+3VALW

4.7k

UE6

1

KB3810

4

UE10

1

KB3810

4

Speaker x4

Audio/B

Lid +Codec AMP x4 +AMP PWR

Battery

PWR TBN/B

on / off SW

LED x2

Default:FPC

DTC:PCB

Wire 30 Pin

Wire 13 Pin

FFC 6 Pin

Coaxia/wire 20 pin

Fbeam FPC 68 Pin x2

JAUDIO

JPWR

JHDD

2.5" HDD

20 Pin

Per-key

Keyboard

DGFF

JDGFF1 JDGFF 2

M/B

Backlight FPC 6 Pin

KSI/KSO FPC 20 Pin

Tron light

LED x 1

Coaxial/Wir e 30/ 40 Pin(eDP+MIC+Camera)

JTRON

Wire 24Pin

6 Pin6 Pin 6 Pin6 Pin

Tron light

LED x 1

Wire 10Pin Alien Head 6Pin+LCDVDD 4Pin

FFC 16 Pi n

JTP

Wire 6 Pin

Tron light

LED x 1

Hinge

TP module

LED x 6

Tobii Host

FPC

Tobii Eye Sensor

Coaxial/Wire(eDP+LC DVDD) 30 Pin(60Hz) 40 Pin(144Hz)

Wire 14Pin (Alien Head+MIC+Camera)

Function/B

Thermal sensor

Wire 2 Pin

4Pin - 2Pin

30 Pin | 24 Pin

FFC 6 Pin

FFC 10 Pi n

Tobii Illumination

Panel

Head/B

LEDx2

Cemera

PCB

FPC

Module

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2018/03/29 2019/03/29

Deciphered Date

Compal Electronics, Inc.

Title

Notes List

Size

Document Number Rev

LA-G881P

Date: Sheet o f

1.0

3 101Tuesday, January 08, 2019

5

IMVP_VR_ON

ISL95829CH RTZ

MB

(PUZ01)

Audio Board

DGFF Board

IMVP_VR_ON

SYSON

PCH_PWR _EN

NVVDD1_EN

NVVDD2_EN

FBVDD/Q_EN

NVVDD2_PGOOD

PCH_PWR_EN

3/5V_B+

(PU301)

3/5V_B+

TPS512 25CRUKR (PU301)

PQ8 B+_BIAS

ISL95870 BHRZ (PUA01)

RT8207PGQW

(PU201)

TPS512 12DSCR (PU101)

UP9511PQG J (PU6000)

UP1666 QQKF (PU6400)

SY8286RAC (PU509)

RT8812AGQW (PUW1)

SY8286RAC (PU801)

SY8286RAC (PU1801)

Fuse +INV_PWR _SRC

EC_EN_AMP

D D

ADAPTER

ISL95338HRT Z

(PUS1)

ADAPTER

ISL95338HRT Z

(PUS2)

+SDC_IN

CHARGE R

ISL88739AHR Z

(PU703)

+PWR_SRC

ISL88739A

BATTERY

C C

B B

A A

5

ISL6617CR Z (PUI07)

ISL6617CR Z (PUI08)

ISL6617CR Z (PUI09)

+VCCSA

13600mA

+1.2VP

2100mA

+0.6VSP

5820mA

+1VALWP

118000mA

+NVVDD 1

39000mA

+NVVDD 2

4480mA

+VCCIOP +VCC IO

23000mA

+1.35VS_VG AP

2100mA

9128mA

+3VALWP

13330mA

+5VALWP

SY8286C RAC (PU501)

(PJP200 PJP201)

(PJP102 PJP103)

(PJPF02)SUSP#

+1.0VS_VGAP

+1.8VSP

(PJP301)TPS512 25CRUKR

(PJP302 PJP303)

4400mA

(PJP202)

(PJPW2, PJPW3, PJPW4)

(PJP801)

(PJP1802)

(PJP304)

+5VP_AMP

4

SIC632CDT1 GE3 (PUI01) (PUI02)

SIC632CDT1 GE3 (PU507) (PU510)

+1.2V_DD R

+0.6VS

+1VALW

+PEX_V DD

+1.8VALW

+3VALW

+5VALW

(PJP502)

4

+1.35VS_VG A

PCH_PWR _EN

SUSP#

EN_WOL#

3V_ELC_O N

PCH_ENVD D

SUSP#

PCH_PWR _EN

USB_PWR_ EN

PWRSHARE_EN_ EC#

USB_PWR_ EN

SUSP#

5VS_GATE

+5V_AMP

+VCC_C ORE

+VCCGT

SYSON

SUSP#

+1V8_AON

APE8937GN2 (UZ21)

JDIMM1/2 /3/ 4

TPS22961 (U19)

TPS22961 (U20)

1V8_AON_EN

KB9542 QB (UE5)

KC3810 (UE6/ UE10)

SY6288C20 AAC (U18)

AOZ1331 (U17)

SY6288D20 AAC (UL14)

1V8_MAIN_EN

+1.2V_V CCPLL_OC

+VCCST

+VCCSTG

AOZ1331

(UG12)

+EC_VC CA

+3V_PC H

+3VALW_LAN

+3VALW_PDRT53

SY6288C20 AAC (UE9)

RT95

RT97

AOZ1334DI-02 (UV64)

AOZ1334DI-02 (U16)

(RT111)TP_EN

AOZ1336 TP Conn.

RN22

DS80PCI40 2SQ (UT6)

RT9059G SP (PU1801)

RT9059G SP (PU2501)

SY6288C20 AAC (UU3)

TPS2546 RTER (UU1)

TPS258 10RVCR (UU7)

AOZ1331 (U17)

SY6288D20 AAC

(UE12)

+3.3V_EL C

+3VALW_TBT ALPINE- RIDGE

+3VS_TBT _SX

+LCDVD D

+3VSP_S SD

+3VS_T OUCH

+3V_WLAN

+1.8VSP

(PJP1301)PM_SLP_S4#

JKB1

EM5209VF (UA11)

RT9058-33G X

RT9059G SP (PU1301)

+5VS_AUDI O

105mA

+3.3VP_AMP +3.3V_AMP

266mA

+1.8VP_AMP +1.8V_AMP

3

+1V8_AON

+1V8_MAIN N17E-G1 G B4-256

N17E-G1 GB4-256

(UG9)

(J5)

RTL8125-C G (UL1)

(UT1)

EDP FC Conn. (JFC)

(JP6)

+3VALW_SS D

(JTP)(UT5)

NGFF Conn. (JWLAN)

(PJP1802)

+1.8VALW

+2.5V_MEMP

(PJP2502)

+5V_US B_PWR2

+5V_US B_PWR1

+5V_U SBC_VBUS

(J4)

+5V_TOBII

(PJP402)

(PJP1303)

3

NGFF Conn. (JSSD1/2)

+2.5V _MEM

+5VS_ AVDD1LA31

EM5209VF (UA11)(PU401)

AOZ1336 (UT5)

TAS2557YZR

(UA3/UA5/UA6/UA7 )

+3VS

+5VS

+3VS_AUDI O

+1.8VS_AUDI O

F75305M (U2407)

F75397M (U2408)

PI6CEQ20200L IEX (UM4)

DS80PCI4 02 (UM8)

(RT111)TP_EN

AOZ1336 TP Conn. (UT5)

RN20

RH614

KXCNL-10 10 (US1)

JEDP Conn. (JEDP)

AP2337SA-7 (UV18)

3V3_SYS_EN

TPS2296 1DNYR (UG14)

RT9297GQW (PU1201)

SI3456DD V (Q2409)

FV3

(JP3)

+5V_H DD

+3VS_TOUCH

+3V_WLAN

+3VS_ACC

JPK

JKBB L

JKB3

LA33

LA32

+3VS_ CPVDD

+3.3V_1.8V _DVDD

+1.8VS_ AVDD2RA201

2

(JTP)

NGFF Conn. (JWLAN)

+3VS_D P

JDP Conn.

+3V3_SYS

+12VP +1 2V_FAN

+5VS_TP_ LED

(PJP1202)

JTP Conn.

+HDMI_5V_OU T JHDMI Conn.

ALC3282-CG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(UA1)

Compal Secret Data

2018/03 /29 2019/03 /29

Deciphered Date

1

Compal Electronics, Inc.

Title

Power MAP

Size

Document Number Rev

LA-G881P

Date: Sheet of

1

4 101Tuesday, January 08, 2019

1.0

5

+5VALW

PR14

PQ3

B+_BIAS

SI3457CDV

D D

PMOS

DGPU_PWR_EN

1

ACIN

110 110

POK

ACIN

A1

AC

VIN

MODE

BATT+

DC MODE

B1

C C

BATT+

5

PU700

BQ24780SRU YR CHARGER

PQ703 NMOS

7

A2

PU100

B+

TPS51225

CRUKR

B2

SW1

A5

B6

+3VALW +5VALW

+3VLP,VL

B3

A3

VCOUT0_PH#

A4

B5

EC_ON

A6

B4

ON/OFFBTN#

UE5 EC90 22QD

104

112

114

+1VALWP_PGOOD

122

101

121

15

B B

VR_PWRGD

IMVP_VR_ ON

16

IMVP_VR_ ON

for power down sequence

A A

Q8A

@

PM_SLP_ S4#

Q7A

@

Q7B

@

Q8B

@

DMN65D8LDW (Q9)

@

5

IMVP_VR_ ON

H_VCCST_PWR GDPM_SLP_ S3#

SUSP#

SYSON

4

123

71

38

6

97

74

127

100

13

107

H_VCCST_PWR GD

SUSACK# 9

PCH_DPWROK

EC_RSMRST#

PCIRST#

PCH_PWR_EN

15

ME_SUS_PWR_A CK

PM_SLP_SUS#

PBTN_ OUT#

PM_SLP_ S5#

PM_SLP_ S3#

7

10

4

+3VALW +1VALWP_PGOOD

9

PR301

3

ACIN1_AV_IN

9

TC7SH08 FU (UH3)

TPS512212 (PU300)

SY6288C20AAC

(U18)

11

7a

8

12

14

+1VALW

+3V_PCH

32

PM_SLP_ S4#

73

15

SYSON

13a

SYSON

SM_PG_CTRL

+3VS

13

95

116

14a

AOZ1331

SUSP#

(U17) +5VS, +3VS

SY8286RAC

SUSP#

(PU509)

+VCCIO

APE8937GN2

SUSP#

(UZ21) +1.2V_VCCPLL_OC

TPS22961DNYR

SUSP#

(U20)

+VCCSTG

TPS22961DNYR

(U19)

8

RT8207MZQW (PU201)

7

43,44,45

7

SY8003DF C (PU13 00)

+VCCST

+2.5V _MEMP

+1.2VP

+0.6VSP

13b

15a

SVID Bus

+3VS

48

PR515

ISL95855 (PU500)

47

VR_PWRGD

SIC632 (PU502/503/504)

16

SIC632 (PU507/510)

SIC531 (PU511)

PR523

AC_PRESENT

18

19

PCH_PWROK

SM_PG_CTRL

+VCC_CORE

+VCCGT

+VCCSA

3

SYS_PWROK

PCH_PLTRST#

KB_RST #

UC1

15

SOC

H13RH154

CPU1

BD19

BB15

BB13

AT13106

AJ44

AJ39

AW27

DGPU_PWROK

GPU_GC6_FB_EN

BA1314

AW15

BB19

PCH

UH1

AY1

BC24 BL26

AV11

BA11

BB27

17

AW11

AT172

BD15

BT13

BH29

BH31

BH32

DGPU_HOLD_RST #

AL36

PCH_PLTRST#

BB27

G9

SVID Bus

UE6 KC38 10

+1.35VS_VGA_PGOOD

QG5

SYS_PEX_RST_ MON#

UG10

G8

PEX_CLKREQ#CLKREQ#_GPU

GPU power on

PCH_PLTRST#

CALDER A_RST#

16

CALDERA_ PWRGD

15

DGPU_PWROK

19

BB5

GPU UG9

BE2

G10

BE1

G0 G1 G2 G4 G5 G6 G7

UM3

TC7SH08 FU

2

1V8_MAIN_EN

+1V8_AON

Compal Net

+1.8VS_AON

+1.8VS_ MAIN

+3V3_SYS

+NVVDD1

+NVVDD2

+PEX_VDD

+1.35VS_ VGA

CDRA_R ST#

G5A

G4A

UE10 KC3810

G3

15

16

GPU_GC6_FB_EN

+1.0VS_VGA_PGOOD

OVERT#

10

NVVDD2_PGOO D

17

NVVDD1_PGOO D

19

+3V3_SYS

20

22

G1A

G1

G2

G3

G4

G5

G6

G7

22

JCDRA Caldera

2

1V8_EN

FBVDD/Q_EN

PEX_VDD_EN

1.8VS_PGOOD

NVVDD_EN

1.8VS_PGOOD

G0A

Will M odify

3V3_SYS_EN

G2

1V8_MAIN_EN

1V8_AON_EN

+3VS

PR802

DG5

Will M odify

NVVDD1_PGOO D

PR823

NVVDD_EN

G0A

Will M odify

PR6103

@

10K

PG515

PU802

UG12

PR6201

@

+1.8VALW

G6A

+1.0VS_VGA_PGOOD

FBVDD/Q_EN

+3VS

PR801

DG6

PR6230

DG3 OVERT#

DG3

NVVDD1_EN

PR6131

SY6288+1V8_MAIN

+1V8_MAIN

+1V8_AON

G0

PR8216

PR821

+1.0VS_VGA_PGOOD

9

PU800 SY8286

NVVDD2_EN

+3V3_SYS

G2

G1

1

+3VS

PR8212

20K

+PEX_VDD

NVVDD2_PGOO D

13

PU6200

NCP81278

+3V3_SYS

PR6107

NVVDD1_PGOO D

13

PU6100 +NVVDD1

NCP81278

G3UG14

GPU power off

PR8204

+1.35VS_VGA_PGOOD

PU8200

RT8812A

G6A

G6

+NVVDD2

G7 G6 G5 G4

+1.35VS_ VGA

G5A

G5

G4A

G4

Compal Net

+1.8VS_AON

+1.8VS_ MAIN

+3V3_SYS

+NVVDD1

+NVVDD2

+PEX_VDD

+1.35VS_ VGA

G7

G1

G2

G3

G4

G5

G6

G7

G3

G2

G1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2018/03/29 2019/03/29

Deciphered Date

Compal Electronics, Inc.

Title

Power Sequence

Size

Document Number Rev

LA-G881P

Date: Sheet of

1

5 101Tuesday, January 08 , 2019

1.0

5

4

3

2

1

UC1E

PCH_CPU_BC LK_P<15> PCH_CPU_BC LK_N<15>

PCH_CPU_PC IBCLK_P<15> PCH_CPU_PC IBCLK_N<15>

CPU_24MHZ_ P<15> CPU_24MHZ_ N<15>

1 2

RC4 499_040 2_1%

1 2

RC356 0_040 2_5%

RC5

1 2

20_0402_1 %

TC2

1 2

RC693 51_040 2_1%

H_CPU_SVIDALRT# VR_SVID_CLK_R VR_SVID_OUT_R H_PROCHOT# _R

DDR_VTT_C NTL

@

VCCST_PW EGD_R

CPU_PLTRS T#

PM_DOWN_ R

12

CPU_PECI

THERMTRIP#_ R

PROC_SELECT #

H_CATERR#

+1.05V_VCCST

RC16

RC19

CPU_PECI

12

+1.05V_VCCST

12

RC17

100_0402_ 1%

VR_SVID_CLK_R VR_SVID_OUT_R H_CPU_SVIDALRT#

+1.05V_VCCST

12

RC3

1K_0402_1 %

H_PROCHOT#<58,82,85,91>

Orion use

+1.05V_VCCST

12

RC2

1K_0402_1 %

H_THERMT RIP#<13>

H_CPUPW RGD<12> CPU_PLTRS T#<13 > H_PM_SYNC_R<13>

H_PM_DOW N<13>

+1.05V_VCCST

PROC_DETEC T#<13>

R395 0_0402_5%

1 2

EC_PECI<58>

D D

H_PECI<13>

CC1

CC2

CC3

CC4

R394 0_0402_5%

RC11 43_0402_1%@

ESD@

@ESD@

ESD@

CPU_PLTRS T#

CPU_PECI

H_PM_SYNC_R

H_CPUPW RGD

12

100P_0402 _50V8J

12

5P_0402_5 0V8C

12

100P_0402 _50V8J

12

100P_0402 _50V8J

12

ESD request Close to CPU as possible

C C

56_0402_1 %

R396

VR_SVID_ALRT#_L

VR_SVID_ALRT#<91>

To Power

VR_SVID_CLK<91>

VR_SVID_OUT<91>

1 2

0_0402_5%

220_0402_ 1%

1 2

R397 0_0402_5%

1 2

R398 0_0402_5%

W5

BCLKP

W4

BCLKN

W1

PCI_BCLKP

W2

PCI_BCLKN

K9

CLK24P

J9

CLK24N

E39

VIDALERT#

E38

VIDSCK

E40

VIDSOUT

C39

PROCHOT#

AC36

DDR_VTT_CNTL

AC38

SKTOCC#

U2

VCCST_PWRGD

F8

PROCPWRGD

E7

RESET#

E8

PM_SYNC

D8

PM_DOWN

G7

PECI

D11

THERMTRIP#

AB36

PROC_SELECT#

D13

CATERR#

CFL_S62_IP_CR B_CFLS_LGA

@

PROC_PREQ# PROC_PRDY#

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8

CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15

CFG_17 CFG_16 CFG_19 CFG_18

BPM#_0 BPM#_1 BPM#_2 BPM#_3

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST#

CFG_RCOMP

H15 F15 F16 H16 F19 H18 G21 H20 G16 E16 F17 H17 G20 F20 F21 H19

F14 E14 F18 G18

D16 D17 G14 H14

XDP_TDO

H13

XDP_TDI

G12

XDP_TMS

F13

PCH_JTAG_TC K

F11

CPU_XDP_TRS T#

F12

XDP_PREQ#

B9

XDP_PRDY#

B10

CFG_RCOMP

M11

CFG0 <79>

CFG2 <79> CFG3 <79> CFG4 <79> CFG5 <79> CFG6 <79> CFG7 <79> CFG8 <79> CFG9 <79> CFG10 <79> CFG11 <79> CFG12 <79> CFG13 <79> CFG14 <79> CFG15 <79>

CFG17 <79> CFG16 <79> CFG19 <79> CFG18 <79>

XDP_TDO <1 2,79> XDP_TDI < 12,79> XDP_TMS <12,79> PCH_JTAG_TC K < 12,79>

CPU_XDP_TRS T# <17,79 > XDP_PREQ# <17,79> XDP_PRDY# < 17,79>

1 2

RC26 49.9_0402_ 1%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

Display Port Presence Strap

CFG4

1 2

CFG0

CFG2

CFG4

CFG5

CFG6

CFG7

XDP_TMS

XDP_TDI

XDP_TDO

@

RH637 1K_0402_5%

1 2

RH184 1K_0402_5%

1 2

@

RH185 1K_0402_5%

1 2

RH186 1K_ 0402_5%

1 2

RH187 1K_ 0402_5%

1 2

@

RH188 1K_0402_5%

12

RH10351_0402_5 % CMC@

12

RH49551_0402_5 % CMC@

12

RH627100_0402_ 1% CMC@

CFL-S schematic check list v1.6 P16

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

1 : Disabled; No Physical Display Port attached to Embedded Display Port

*

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

+1.05V_VCCST

PCIE Port Bifurcation Straps

To Thunderbolt

CPU_DP1_P0<42>

+1.05V_VCCST

B B

H_VCCST_PW RGD<58,78>

A A

To Power

SM_PG_CTRL<87 >

12

RC12 1K_0402_5 %

1 2

RC13 60.4_040 2_1%

@

1 2

RC684 0_04 02_5%

1 2

RC685 0_04 02_5%

5

@

RH525

330K_0402 _5%

VCCST_PW EGD_R

+3VS

@

12

CH197

0.1U_0402_ 10V7K

PM_SLP_S3# < 12,58,62,78,83,85>

+1.2V_DDR

1

2

For ODT & VTT power control

UC2

5

4

74AUP1G07GW _TSSOP5

@

CPU_DP1_N 0<42> CPU_DP1_P1<42> CPU_DP1_N 1<42> CPU_DP1_P2<42> CPU_DP1_N 2<42> CPU_DP1_P3<42> CPU_DP1_N 3<42>

CPU_DP1_AUXP<42> CPU_DP1_AUXN<42>

CPU_DP2_P0<42> CPU_DP2_N 0<42> CPU_DP2_P1<42> CPU_DP2_N 1<42> CPU_DP2_P2<42> CPU_DP2_N 2<42> CPU_DP2_P3<42> CPU_DP2_N 3<42>

CPU_DP2_AUXP<42> CPU_DP2_AUXN<42>

1

NC

VCC

Y

4

GND

A

2

3

DDR_VTT_C NTL

UC1D

C21

DDI1_TXP_0

D21

DDI1_TXN_0

D22

DDI1_TXP_1

E22

DDI1_TXN_1

B23

DDI1_TXP_2

A23

DDI1_TXN_2

C23

DDI1_TXP_3

D23

DDI1_TXN_3

B13

DDI1_AUXP

C13

DDI1_AUXN

B18

DDI2_TXP_0

A18

DDI2_TXN_0

D18

DDI2_TXP_1

E18

DDI2_TXN_1

C19

DDI2_TXP_2

D19

DDI2_TXN_2

D20

DDI2_TXP_3

E20

DDI2_TXN_3

A12

DDI2_AUXP

B12

DDI2_AUXN

B14

DDI3_TXP_0

A14

DDI3_TXN_0

C15

DDI3_TXP_1

B15

DDI3_TXN_1

B16

DDI3_TXP_2

A16

DDI3_TXN_2

C17

DDI3_TXP_3

B17

DDI3_TXN_3

B11

DDI3_AUXP

C11

DDI3_AUXN

CFL_S62_IP_CR B_CFLS_LGA

@

E10

EDP_TXP_0

D10

EDP_TXN_0

D9

EDP_TXP_1

C9

EDP_TXN_1

H10

EDP_TXN_2

G10

EDP_TXP_2

G9

EDP_TXN_3

F9

EDP_TXP_3

D12

EDP_AUXP

E12

EDP_AUXN

DISP_RCOMP

D14

EDP_RCOMP

M9

V3 V2 U1

RC10 24.9_0402_1%

EDP_RCOMP Min Trace Width = 20 mils Isolation Spacing = 25 mils Trace Length < 100 mils

CPU_DISPA_SDI

12

1 2

RC1 30_0402_5 %

+VCCIO

RC1 Close to CPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

EDP_DISP_UTIL

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

CFG[6: 5]

CPU_DISPA_BCLK <12> CPU_DISPA_SDO <12>

CPU_DISPA_SDI_R <1 2>

2

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

*

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion

*

0: PEG Wait for BIOS for training

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

Compal Electronics, Inc.

CFL-S JTAG/XDP/DDI

LA-G881P

1.0

6 101Tuesday, January 08, 201 9

1

6 101Tuesday, January 08, 201 9

1.0

5

D D

4

UC1C

3

2

1

B8

PEG_RXP_0

B7

PEG_RXN_0

C7

PEG_RXP_1

C6

PEG_RXN_1

D6

PEG_RXP_2

D5

C C

PEG_CRX _GTX_P11<74> PEG_CRX _GTX_N11<74>

PEG_CRX _GTX_P10<74>

Caldera TX

GPU TX

B B

PEG_RCOMP Trace Width = 5 mils Trace Spacing to Other Signals =15 mils Trace Length < 600 mils

A A

+VCCIO

12

RC14

24.9_040 2_1%

PEG_RCO MP

PEG_CRX _GTX_N10<74>

PEG_CRX _GTX_P9<74> PEG_CRX _GTX_N9<74>

PEG_CRX _GTX_P8<74> PEG_CRX _GTX_N8<74>

PEG_CRX _GTX_P7<37> PEG_CRX _GTX_N7<37>

PEG_CRX _GTX_P6<37> PEG_CRX _GTX_N6<37>

PEG_CRX _GTX_P5<37> PEG_CRX _GTX_N5<37>

PEG_CRX _GTX_P4<37> PEG_CRX _GTX_N4<37>

PEG_CRX _GTX_P3<37> PEG_CRX _GTX_N3<37>

PEG_CRX _GTX_P2<37> PEG_CRX _GTX_N2<37>

PEG_CRX _GTX_P1<37> PEG_CRX _GTX_N1<37>

PEG_CRX _GTX_P0<37> PEG_CRX _GTX_N0<37>

DMI_CRX_P TX_P0<14> DMI_CRX_P TX_N0<14>

DMI_CRX_P TX_P1<14> DMI_CRX_P TX_N1<14>

DMI_CRX_P TX_P2<14> DMI_CRX_P TX_N2<14>

DMI_CRX_P TX_P3<14> DMI_CRX_P TX_N3<14>

DMI_CRX_P TX_P0 DMI_CRX_P TX_N0

DMI_CRX_P TX_P1 DMI_CRX_P TX_N1

DMI_CRX_P TX_P2 DMI_CRX_P TX_N2

DMI_CRX_P TX_P3 DMI_CRX_P TX_N3

PEG_RXN_2

E5

PEG_RXP_3

E4

PEG_RXN_3

F6

PEG_RXP_4

F5

PEG_RXN_4

G5

PEG_RXP_5

G4

PEG_RXN_5

H6

PEG_RXP_6

H5

PEG_RXN_6

J5

PEG_RXP_7

J4

PEG_RXN_7

K6

PEG_RXP_8

K5

PEG_RXN_8

L5

PEG_RXP_9

L4

PEG_RXN_9

M6

PEG_RXP_10

M5

PEG_RXN_10

N5

PEG_RXP_11

N4

PEG_RXN_11

P6

PEG_RXP_12

P5

PEG_RXN_12

R5

PEG_RXP_13

R4

PEG_RXN_13

T6

PEG_RXP_14

T5

PEG_RXN_14

U5

PEG_RXP_15

U4

PEG_RXN_15

L7

PEG_RCOMP

Y3

DMI_RXP_0

Y4

DMI_RXN_0

AA4

DMI_RXP_1

AA5

DMI_RXN_1

AB4

DMI_RXP_2

AB3

DMI_RXN_2

AC4

DMI_RXP_3

AC5

DMI_RXN_3

CFL_S62 _IP_CRB_CFLS_L GA

@

PEG_TXP_0 PEG_TXN_0

PEG_TXP_1 PEG_TXN_1

PEG_TXP_2 PEG_TXN_2

PEG_TXP_3 PEG_TXN_3

PEG_TXP_4 PEG_TXN_4

PEG_TXP_5 PEG_TXN_5

PEG_TXP_6 PEG_TXN_6

PEG_TXP_7 PEG_TXN_7

PEG_TXP_8 PEG_TXN_8

PEG_TXP_9 PEG_TXN_9

PEG_TXP_10 PEG_TXN_10

PEG_TXP_11 PEG_TXN_11

PEG_TXP_12 PEG_TXN_12

PEG_TXP_13 PEG_TXN_13

PEG_TXP_14 PEG_TXN_14

PEG_TXP_15 PEG_TXN_15

DMI_TXP_0 DMI_TXN_0

DMI_TXP_1 DMI_TXN_1

DMI_TXP_2 DMI_TXN_2

DMI_TXP_3 DMI_TXN_3

A5 A6

B4 B5

C3 C4

D2 D3

PEG_CTX _GRX_P11

E1

PEG_CTX _GRX_N11

E2

PEG_CTX _GRX_P10

F2

PEG_CTX _GRX_N10

F3

PEG_CTX _GRX_P9

G1

PEG_CTX _GRX_N9

G2

PEG_CTX _GRX_P8

H2

PEG_CTX _GRX_N8

H3

PEG_CTX _GRX_P7

J1

PEG_CTX _GRX_N7

J2

PEG_CTX _GRX_P6

K2

PEG_CTX _GRX_N6

K3

PEG_CTX _GRX_P5

L1

PEG_CTX _GRX_N5

L2

PEG_CTX _GRX_P4

M2

PEG_CTX _GRX_N4

M3

PEG_CTX _GRX_P3

N1

PEG_CTX _GRX_N3

N2

PEG_CTX _GRX_P2

P2

PEG_CTX _GRX_N2

P3

PEG_CTX _GRX_P1

R2

PEG_CTX _GRX_N1

R1

PEG_CTX _GRX_P0

T2

PEG_CTX _GRX_N0

T3

DMI_CTX_P RX_P0

AC2

DMI_CTX_P RX_N0

AC1

DMI_CTX_P RX_P1

AD3

DMI_CTX_P RX_N1

AD2

DMI_CTX_P RX_P2

AE2

DMI_CTX_P RX_N2

AE1

DMI_CTX_P RX_P3

AF2

DMI_CTX_P RX_N3

AF3

1 2

CC58 0.22U_0201 _6.3V

1 2

CC63 0.22U_0201 _6.3V

1 2

CC61 0.22U_0201 _6.3V

1 2

CC62 0.22U_0201 _6.3V

1 2

CC59 0.22U_0201 _6.3V

1 2

CC56 0.22U_0201 _6.3V

1 2

CC57 0.22U_0201 _6.3V

1 2

CC60 0.22U_0201 _6.3V

1 2

CC20 0.22U_0402 _6.3V7K

1 2

CC21 0.22U_0402 _6.3V7K

1 2

CC18 0.22U_0402 _6.3V7K

1 2

CC19 0.22U_0402 _6.3V7K

1 2

CC16 0.22U_0402 _6.3V7K

1 2

CC17 0.22U_0402 _6.3V7K

1 2

CC14 0.22U_0402 _6.3V7K

1 2

CC15 0.22U_0402 _6.3V7K

1 2

CC12 0.22U_0402 _6.3V7K

1 2

CC13 0.22U_0402 _6.3V7K

1 2

CC10 0.22U_0402 _6.3V7K

1 2

CC11 0.22U_0402 _6.3V7K

1 2

CC8 0.22U_0402_6 .3V7K

1 2

CC9 0.22U_0402_6 .3V7K

1 2

CC6 0.22U_0402_6 .3V7K

1 2

CC7 0.22U_0402_6 .3V7K

DMI_CTX_P RX_P0 <14 > DMI_CTX_P RX_N0 < 14>

DMI_CTX_P RX_P1 <14 > DMI_CTX_P RX_N1 < 14>

DMI_CTX_P RX_P2 <14 > DMI_CTX_P RX_N2 < 14>

DMI_CTX_P RX_P3 <14 > DMI_CTX_P RX_N3 < 14>

PEG_CTX _C_GRX_P11 <74> PEG_CTX _C_GRX_N11 <74>

PEG_CTX _C_GRX_P10 <74> PEG_CTX _C_GRX_N10 <74>

PEG_CTX _C_GRX_P9 < 74> PEG_CTX _C_GRX_N9 <74>

PEG_CTX _C_GRX_P8 < 74> PEG_CTX _C_GRX_N8 <74>

PEG_CTX _C_GRX_P7 <37> PEG_CTX _C_GRX_N7 <37>

PEG_CTX _C_GRX_P6 <37> PEG_CTX _C_GRX_N6 <37>

PEG_CTX _C_GRX_P5 <37> PEG_CTX _C_GRX_N5 <37>

PEG_CTX _C_GRX_P4 <37> PEG_CTX _C_GRX_N4 <37>

PEG_CTX _C_GRX_P3 <37> PEG_CTX _C_GRX_N3 <37>

PEG_CTX _C_GRX_P2 <37> PEG_CTX _C_GRX_N2 <37>

PEG_CTX _C_GRX_P1 <37> PEG_CTX _C_GRX_N1 <37>

PEG_CTX _C_GRX_P0 <37> PEG_CTX _C_GRX_N0 <37>

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

Caldera RX

GPU RX

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CFL-S DMI/PEG

LA-G881P

7 101Tuesday, January 08, 201 9

1

1.0

5

4

3

2

1

DDR_A_D[0..63]<23,25> DDR_A_MA[0..13]<23,25>

UC1A

AE38

DDR0_DQ_0/DDR0_DQ_0

AE37

DDR0_DQ_1/DDR0_DQ_1

AG38

DDR0_DQ_2/DDR0_DQ_2

AG37

DDR0_DQ_3/DDR0_DQ_3

AE39

DDR0_DQ_4/DDR0_DQ_4

AE40

DDR0_DQ_5/DDR0_DQ_5

AG39

DDR0_DQ_6/DDR0_DQ_6

AG40

DDR0_DQ_7/DDR0_DQ_7

AJ38

DDR0_DQ_8/DDR0_DQ_8

AJ37

DDR0_DQ_9/DDR0_DQ_9

AL38

DDR0_DQ_10/DDR0_DQ_10

AL37

DDR0_DQ_11/DDR0_DQ_11

AJ40

DDR0_DQ_12/DDR0_DQ_12

AJ39

DDR0_DQ_13/DDR0_DQ_13

AL39

DDR0_DQ_14/DDR0_DQ_14

AL40

DDR0_DQ_15/DDR0_DQ_15

AN38

DDR0_DQ_16/DDR0_DQ_32

AN40

DDR0_DQ_17/DDR0_DQ_33

AR38

DDR0_DQ_18/DDR0_DQ_34

AR37

DDR0_DQ_19/DDR0_DQ_35

AN39

DDR0_DQ_20/DDR0_DQ_36

AN37

DDR0_DQ_21/DDR0_DQ_37

AR39

DDR0_DQ_22/DDR0_DQ_38

AR40

DDR0_DQ_23/DDR0_DQ_39

AW37

DDR0_DQ_24/DDR0_DQ_40

AU38

DDR0_DQ_25/DDR0_DQ_41

AV35

DDR0_DQ_26/DDR0_DQ_42

AW35

DDR0_DQ_27/DDR0_DQ_43

AU37

DDR0_DQ_28/DDR0_DQ_44

AV37

DDR0_DQ_29/DDR0_DQ_45

AT35

DDR0_DQ_30/DDR0_DQ_46

AU35

DDR0_DQ_31/DDR0_DQ_47

AY8

DDR0_DQ_32/DDR1_DQ_0

AW8

DDR0_DQ_33/DDR1_DQ_1

AV6

DDR0_DQ_34/DDR1_DQ_2

AU6

DDR0_DQ_35/DDR1_DQ_3

AU8

DDR0_DQ_36/DDR1_DQ_4

AV8

DDR0_DQ_37/DDR1_DQ_5

AW6

DDR0_DQ_38/DDR1_DQ_6

AY6

DDR0_DQ_39/DDR1_DQ_7

AY4

DDR0_DQ_40/DDR1_DQ_8

AV4

DDR0_DQ_41/DDR1_DQ_9

AT1

DDR0_DQ_42/DDR1_DQ_10

AT2

DDR0_DQ_43/DDR1_DQ_11

AV3

DDR0_DQ_44/DDR1_DQ_12

AW4

DDR0_DQ_45/DDR1_DQ_13

AT4

DDR0_DQ_46/DDR1_DQ_14

AT3

DDR0_DQ_47/DDR1_DQ_15

AP2

DDR0_DQ_48/DDR1_DQ_32

AM4

DDR0_DQ_49/DDR1_DQ_33

AP3

DDR0_DQ_50/DDR1_DQ_34

AM3

DDR0_DQ_51/DDR1_DQ_35

AP4

DDR0_DQ_52/DDR1_DQ_36

AM2

DDR0_DQ_53/DDR1_DQ_37

AP1

DDR0_DQ_54/DDR1_DQ_38

AM1

DDR0_DQ_55/DDR1_DQ_39

AK3

DDR0_DQ_56/DDR1_DQ_40

AH1

DDR0_DQ_57/DDR1_DQ_41

AK4

DDR0_DQ_58/DDR1_DQ_42

AH2

DDR0_DQ_59/DDR1_DQ_43

AH4

DDR0_DQ_60/DDR1_DQ_44

AK2

DDR0_DQ_61/DDR1_DQ_45

AH3

DDR0_DQ_62/DDR1_DQ_46

AK1

DDR0_DQ_63/DDR1_DQ_47

AU33

DDR0_ECC_0

AT33

DDR0_ECC_1

AW33

DDR0_ECC_2

AV31

DDR0_ECC_3

AU31

DDR0_ECC_4

AV33

DDR0_ECC_5

AW31

DDR0_ECC_6

AY31

DDR0_ECC_7

DDR CHANNEL A

CFL_S62_IP_CR B_CFLS_LGA

@

DDR_A_DQS#[0..7]<23 ,25> DDR_A_DQS[0..7]<23,25>

D D

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22

C C

B B

DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

Channel A Channel B

DDR0_CKP_0

DDR0_CKN_0

DDR0_CKP_1

DDR0_CKN_1

DDR0_CKP_2

DDR0_CKN_2

DDR0_CKP_3

DDR0_CKN_3

DDR0_CKE_0 DDR0_CKE_1 DDR0_CKE_2 DDR0_CKE_3

DDR0_CS#_0 DDR0_CS#_1 DDR0_CS#_2 DDR0_CS#_3

DDR0_ODT_0 DDR0_ODT_1 DDR0_ODT_2 DDR0_ODT_3

DDR0_BA_0 DDR0_BA_1 DDR0_BG_0

DDR0_MA_16 DDR0_MA_14 DDR0_MA_15

DDR0_MA_0 DDR0_MA_1 DDR0_MA_2 DDR0_MA_3 DDR0_MA_4 DDR0_MA_5 DDR0_MA_6 DDR0_MA_7 DDR0_MA_8

DDR0_MA_9 DDR0_MA_10 DDR0_MA_11 DDR0_MA_12 DDR0_MA_13

DDR0_BG_1

DDR0_ACT#

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8 DDR0_DQSN_8/DDR0_DQSN_8

AW18 AV18 AW17 AY17 AW16 AV16 AT16 AU16

AY24 AW24 AV24 AV25

AW12 AU11 AV13 AV10

AW11 AU14 AU12 AY10

AY13 AV15 AW23

AW13 AV14 AY11

AW15 AU18 AU17 AV19 AT19 AU20 AV20 AU21 AT20 AT22 AY14 AU22 AV22 AV12 AV23 AU24

AY15 AT23

AF39 AK39 AP39 AU36 AW7 AU3 AN3 AJ3

AF38 AK38 AP38 AV36 AV7 AU2 AN2 AJ2

AV32 AU32

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_RAS# DDR_A_WE # DDR_A_CAS#

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_CLK0 <25> DDR_A_CLK#0 <25> DDR_A_CLK1 <25> DDR_A_CLK#1 <25> DDR_A_CLK2 <23> DDR_A_CLK#2 <23> DDR_A_CLK3 <23> DDR_A_CLK#3 <23>

DDR_A_CKE0 <25> DDR_A_CKE1 <25> DDR_A_CKE2 <23> DDR_A_CKE3 <23>

DDR_A_CS#0 <25> DDR_A_CS#1 <25> DDR_A_CS#2 <23> DDR_A_CS#3 <23>

DDR_A_ODT0 <25> DDR_A_ODT1 <25> DDR_A_ODT2 <23> DDR_A_ODT3 <23>

DDR_A_BA0 <23,25> DDR_A_BA1 <23,25> DDR_A_BG0 < 23,25>

DDR_A_RAS# <23,25> DDR_A_WE # <23,25> DDR_A_CAS# <23,25>

DDR_A_BG1 < 23,25> DDR_A_ACT# <23,25>

DDR_A_PAR <23,25> DDR_A_ALERT# <23,25> DDR_B_ALERT # <24,26>

DIMM2

DIMM1

DIMM2

DIMM1

DIMM2

DIMM1

DIMM2

DIMM1

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_D[0..63 ]<24,26> DDR_B_MA[0..13]<24,26> DDR_B_DQS# [0..7]< 24,26> DDR_B_DQS[0 ..7]< 24,26>

UC1B

AD34

DDR1_DQ_0/DDR0_DQ_16

AD35

DDR1_DQ_1/DDR0_DQ_17

AG35

DDR1_DQ_2/DDR0_DQ_18

AH35

DDR1_DQ_3/DDR0_DQ_19

AE35

DDR1_DQ_4/DDR0_DQ_20

AE34

DDR1_DQ_5/DDR0_DQ_21

AG34

DDR1_DQ_6/DDR0_DQ_22

AH34

DDR1_DQ_7/DDR0_DQ_23

AK35

DDR1_DQ_8/DDR0_DQ_24

AL35

DDR1_DQ_9/DDR0_DQ_25

AK32

DDR1_DQ_10/DDR0_DQ_26

AL32

DDR1_DQ_11/DDR0_DQ_27

AK34

DDR1_DQ_12/DDR0_DQ_28

AL34

DDR1_DQ_13/DDR0_DQ_29

AK31

DDR1_DQ_14/DDR0_DQ_30

AL31

DDR1_DQ_15/DDR0_DQ_31

AP35

DDR1_DQ_16/DDR0_DQ_48

AN35

DDR1_DQ_17/DDR0_DQ_49

AN32

DDR1_DQ_18/DDR0_DQ_50

AP32

DDR1_DQ_19/DDR0_DQ_51

AN34

DDR1_DQ_20/DDR0_DQ_52

AP34

DDR1_DQ_21/DDR0_DQ_53

AN31

DDR1_DQ_22/DDR0_DQ_54

AP31

DDR1_DQ_23/DDR0_DQ_55

AL29

DDR1_DQ_24/DDR0_DQ_56

AM29

DDR1_DQ_25/DDR0_DQ_57

AP29

DDR1_DQ_26/DDR0_DQ_58

AR29

DDR1_DQ_27/DDR0_DQ_59

AM28

DDR1_DQ_28/DDR0_DQ_60

AL28

DDR1_DQ_29/DDR0_DQ_61

AR28

DDR1_DQ_30/DDR0_DQ_62

AP28

DDR1_DQ_31/DDR0_DQ_63

AR12

DDR1_DQ_32/DDR1_DQ_16

AP12

DDR1_DQ_33/DDR1_DQ_17

AM13

DDR1_DQ_34/DDR1_DQ_18

AL13

DDR1_DQ_35/DDR1_DQ_19

AR13

DDR1_DQ_36/DDR1_DQ_20

AP13

DDR1_DQ_37/DDR1_DQ_21

AM12

DDR1_DQ_38/DDR1_DQ_22

AL12

DDR1_DQ_39/DDR1_DQ_23

AP10

DDR1_DQ_40/DDR1_DQ_24

AR10

DDR1_DQ_41/DDR1_DQ_25

AR7

DDR1_DQ_42/DDR1_DQ_26

AP7

DDR1_DQ_43/DDR1_DQ_27

AR9

DDR1_DQ_44/DDR1_DQ_28

AP9

DDR1_DQ_45/DDR1_DQ_29

AR6

DDR1_DQ_46/DDR1_DQ_30

AP6

DDR1_DQ_47/DDR1_DQ_31

AM10

DDR1_DQ_48/DDR1_DQ_48

AL10

DDR1_DQ_49/DDR1_DQ_49

AM7

DDR1_DQ_50/DDR1_DQ_50

AL7

DDR1_DQ_51/DDR1_DQ_51

AM9

DDR1_DQ_52/DDR1_DQ_52

AL9

DDR1_DQ_53/DDR1_DQ_53

AM6

DDR1_DQ_54/DDR1_DQ_54

AL6

DDR1_DQ_55/DDR1_DQ_55

AJ6

DDR1_DQ_56/DDR1_DQ_56

AJ7

DDR1_DQ_57/DDR1_DQ_57

AE6

DDR1_DQ_58/DDR1_DQ_58

AF7

DDR1_DQ_59/DDR1_DQ_59

AH7

DDR1_DQ_60/DDR1_DQ_60

AH6

DDR1_DQ_61/DDR1_DQ_61

AE7

DDR1_DQ_62/DDR1_DQ_62

AF6

DDR1_DQ_63/DDR1_DQ_63

AR25

DDR1_ECC_0

AR26

DDR1_ECC_1

AM26

DDR1_ECC_2

AM25

DDR1_ECC_3

AP26

DDR1_ECC_4

AP25

DDR1_ECC_5

AL25

DDR1_ECC_6

AL26

DDR1_ECC_7

CFL_S62_IP_CR B_CFLS_LGA

@

DDR CHANNEL B

DDR1_CKP_0 DDR1_CKN_0 DDR1_CKP_1 DDR1_CKN_1 DDR1_CKP_2 DDR1_CKN_2 DDR1_CKP_3 DDR1_CKN_3

DDR1_CKE_0 DDR1_CKE_1 DDR1_CKE_2 DDR1_CKE_3

DDR1_CS#_0 DDR1_CS#_1 DDR1_CS#_2 DDR1_CS#_3

DDR1_ODT_0 DDR1_ODT_1 DDR1_ODT_2 DDR1_ODT_3

DDR1_MA_16 DDR1_MA_14 DDR1_MA_15

DDR1_BA_0 DDR1_BA_1

DDR1_BG_0

DDR1_MA_0 DDR1_MA_1 DDR1_MA_2 DDR1_MA_3 DDR1_MA_4 DDR1_MA_5 DDR1_MA_6 DDR1_MA_7 DDR1_MA_8

DDR1_MA_9 DDR1_MA_10 DDR1_MA_11 DDR1_MA_12 DDR1_MA_13

DDR1_BG_1

DDR1_ACT#

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8 DDR1_DQSN_8/DDR1_DQSN_8

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

AM20 AM21 AP22 AP21 AN20 AN21 AP19 AP20

AY29 AV29 AW29 AU29

AP17 AN15 AN17 AM15

AM16 AL16 AP15 AL15

DDR_B_RAS#

AN18

DDR_B_W E#

AL17

DDR_B_CAS#

AP16

AL18 AM18 AW28

AL19 AL22 AM22 AM23 AP23 AL23 AW26 AY26 AU26 AW27 AP18 AU27 AV27 AR15 AY28 AU28

AL20 AY25

AF34 AK33 AN33 AN29 AN13 AR8 AM8 AG6

AF35 AL33 AP33 AN28 AN12 AP8 AL8 AG7

AN25 AN26

AB40 AC40 AC39

DDR_B_BA0 DDR_B_BA1 DDR_B_BG0

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

DDR_B_BG1 DDR_B_ACT#

DDR_B_DQS# 0 DDR_B_DQS# 1 DDR_B_DQS# 2 DDR_B_DQS# 3 DDR_B_DQS# 4 DDR_B_DQS# 5 DDR_B_DQS# 6 DDR_B_DQS# 7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

Trace width / Spacing = 10 / 12 mils

SA_DIMM_VREFDQ

Trace width / Spacing = 10 / 12 mils

+0.6V_VREF_CA

TC7

+0.6V_VREF_DQ

DDR_B_CLK 0 <26> DDR_B_CLK #0 <26> DDR_B_CLK 1 <26> DDR_B_CLK #1 <26> DDR_B_CLK 2 <24> DDR_B_CLK #2 <24> DDR_B_CLK 3 <24> DDR_B_CLK #3 <24>

DDR_B_CKE0 <26> DDR_B_CKE1 <26> DDR_B_CKE2 <24> DDR_B_CKE3 <24>

DDR_B_CS# 0 <26> DDR_B_CS# 1 <26> DDR_B_CS# 2 <24> DDR_B_CS# 3 <24>

DDR_B_ODT 0 <2 6> DDR_B_ODT 1 <2 6> DDR_B_ODT 2 <2 4> DDR_B_ODT 3 <2 4>

DDR_B_RAS# <24,26> DDR_B_W E# <24,26> DDR_B_CAS# <24,26>

DDR_B_BA0 <24,26> DDR_B_BA1 <24,26> DDR_B_BG0 < 24,26>

DDR_B_BG1 < 24,26> DDR_B_ACT# <24,26>

DDR_B_PAR <24,26>

DIMM4

DIMM3

DIMM4

DIMM3

DIMM4

DIMM3

DIMM4

DIMM3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

CFL-S DDR4

LA-G881P

1

8 101Tuesday, January 08, 201 9

1.0

5

4

3

2

1

+VCC_CORE +VCC_CORE

49A

D D

C C

B B

UC1G

A25

VCC1

A26

VCC2

A27

VCC3

A28

VCC4

A29

VCC5

A30

VCC6

B25

VCC24

B27

VCC25

B29

VCC26

B31

VCC27

B32

VCC28

B33

VCC29

B34

VCC30

B35

VCC31

B36

VCC32

B37

VCC33

C25

VCC34

C26

VCC35

C27

VCC36

C28

VCC37

C29

VCC38

C30

VCC39

C32

VCC40

C34

VCC41

C36

VCC42

D25

VCC43

D27

VCC44

D29

VCC45

D31

VCC46

D32

VCC47

D33

VCC48

D34

VCC49

D35

VCC50

D36

VCC51

E24

VCC52

E25

VCC53

E26

VCC54

E27

VCC55

E28

VCC56

E29

VCC57

E30

VCC58

E32

VCC59

E34

VCC60

E36

VCC61

F23

VCC62

F24

VCC63

F25

VCC64

F27

VCC65

F29

VCC66

F31

VCC67

G30

VCC80

G32

VCC81

H22

VCC84

H23

VCC85

H25

VCC86

H27

VCC87

H29

VCC88

H31

VCC89

AJ11

VCC7

AJ13

VCC9

AJ15

VCC11

AJ17

VCC13

AJ19

VCC15

AJ21

VCC17

M32

VCC146

L31

VCC134

K32

VCC115

J33

VCC104

H33

VCC91

G34

VCC82

AJ25

VCC18

AJ26

VCC19

AJ27

VCC20

AJ28

VCC21

CFL_S62_IP_CR B_CFLS_LGA

@

VCC90 VCC93 VCC68 VCC69 VCC70 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC94 VCC95 VCC96 VCC97 VCC98

VCC99 VCC100 VCC101 VCC102 VCC103 VCC106 VCC107 VCC108 VCC109 VCC110 VCC111 VCC112 VCC113 VCC114 VCC117 VCC118 VCC119 VCC120 VCC121 VCC122 VCC123 VCC124 VCC125 VCC126 VCC127 VCC128 VCC129 VCC130 VCC131 VCC132 VCC133 VCC136 VCC137 VCC138 VCC139 VCC140 VCC141 VCC142 VCC143 VCC144 VCC145

VCC8 VCC10 VCC12 VCC14 VCC16

VCC22 VCC23 VCC71 VCC72 VCC83 VCC92

VCC105 VCC116 VCC135

VCC_SENSE VSS_SENSE

H32 J21 F32 F33 F34 G23 G24 G25 G26 G27 G28 G29 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 K16 K18 K20 K21 K23 K25 K27 K29 K31 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M13 M14 M16 M18 M20 M22 M24 M26 M28 M30 AJ12 AJ14 AJ16 AJ18 AJ20

AJ29 AK21 F35 F37 G35 H34 J35 K34 L33

C38 D38

22U_0805_ 6.3V6M~D

+VCC_CORE

12

1

CC52

2

47U_0805_ 6.3V6M

1

CC29

22U_0603_ 6.3V6M

1

CC33

2

22U_0603_ 6.3V6M

2

1

2

22U_0603_ 6.3V6M

+VCCIO

CC32

9/12:change from SE000000I10 to SE00000M000*2

RC197 100_0402_ 1%

VCORE_VCC_SEN <91> VCORE_VSS_SEN <91>

RC686 100_0402_ 1%

PLACE ALL BELOW CAPS ON TOP SIDE NEAR CPU SOCKET

47U_0805_ 6.3V6M

1

CC51

CC50

2

47U_0805_ 6.3V6M

PLACE ALL ABOVE CAPS ON TOP SIDE OF CPU CAVITY

1

CC28

22U_0603_ 6.3V6M

2

PLACE ALL ABOVE CAPS ON TOP SIDE OF CPU CAVITY

22U_0603_ 6.3V6M

1

CC34

CC35

2

1

2

1

CC26

2

1

CC36

2

22U_0603_ 6.3V6M

47U_0805_ 6.3V6M

CC49

22U_0603_ 6.3V6M

1

2

+1.05V_VCCST

Place as close to socket as possible

1

2

CC27

CC37

1

CC47

2

22U_0603_ 6.3V6M

1

2

0.95V/5.5A

1

2

+1.05V_VCCST

22U_0603_6.3V6M

CC38

1

2

22U_0603_ 6.3V6M

1

CC48

2

1.05V / 11A

1.05V/120mA

22U_0603_6.3V6M

CC30

1

CC31 1U_0201_6 .3V6M

2

SE00000UC0 0

+VCCSA

UC1I

AA7

VCCSA2

AB6

VCCSA3

AB7

VCCSA4

AB8

VCCSA5

AC7

VCCSA6

AC8

VCCSA7

N7

VCCSA8

P7

VCCSA9

R7

VCCSA10

T7

VCCSA11

U7

VCCSA12

Y6

VCCSA15

Y7

VCCSA16

Y8

VCCSA17

W7

VCCSA14

V7

VCCSA13

AA6

VCCSA1

AK11

VCCIO2

AK14

VCCIO3

AK24

VCCIO4

AJ23

VCCIO1

M8

VCCIO5

P8

VCCIO6

T8

VCCIO7

U8

VCCIO8

W8

VCCIO9

V5

VCCST1

V6

VCCST2

V4

VCCPLL

CFL_S62_IP_CR B_CFLS_LGA

@

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16

VCCPLL_OC

VCCSA_SENSE VCCIO_SENSE

VSS_SAIO_SENSE

AT18 AT21 AU13 AU15 AU19 AU23 AV11 AV17 AV21 AW10 AW14 AW25 AY12 AY16 AY18 AY23

AJ9

100mA

AD5 AF4 AE4

PLACE ALL BELOW CAPS ON TOP SIDE NEAR CPU SOCKET

2.5A

VCCPLL_OC

VCCSA_SENSE VCCIO_SENSE VSSSAIO_SENSE

1

CC22

2

22U_0603_ 6.3V6M

RC21 0_0402_5%

RC25 0_0402_5%

2

CC46 1U_0201_6 .3V6M

SE00000UC0 0

1

22U_0603_ 6.3V6M

CC23

S0IX@

1 2

NS0IX@

1 2

For NON-S0IX

@

1

CC24

2

22U_0603_ 6.3V6M

+1.2V_VCCPLL_OC

VCCSA_SENSE <96> VCCIO_SENSE <89> VSSSAIO_SENSE <96>

22U_0603_ 6.3V6M

CC25

+VCCGT

+1.2V_DDR

1

2

+1.2V_DDR

35A

UC1H

AA34

VCCGT1

AA35

VCCGT2

AA36

VCCGT3

AA37

VCCGT4

AA38

VCCGT5

AB33

VCCGT6

AB34

VCCGT7

G36

VCCGT8

G37

VCCGT9

G38

VCCGT10

G39

VCCGT11

G40

VCCGT12

H36

VCCGT13

H38

VCCGT14

H40

VCCGT15

J36

VCCGT16

J37

VCCGT17

J38

VCCGT18

J39

VCCGT19

J40

VCCGT20

K36

VCCGT21

K38

VCCGT22

K40

VCCGT23

L34

VCCGT24

L35

VCCGT25

L36

VCCGT26

L37

VCCGT27

L38

VCCGT28

L39

VCCGT29

L40

VCCGT30

M33

VCCGT31

M34

VCCGT32

M36

VCCGT33

M38

VCCGT34

M40

VCCGT35

N34

VCCGT36

N35

VCCGT37

N36

VCCGT38

N37

VCCGT39

N38

VCCGT40

N39

VCCGT41

N40

VCCGT42

P33

VCCGT43

P34

VCCGT44

P36

VCCGT45

P38

VCCGT46

P40

VCCGT47

R34

VCCGT48

R35

VCCGT49

R36

VCCGT50

R37

VCCGT51

R38

VCCGT52

R39

VCCGT53

R40

VCCGT54

T33

VCCGT55

T34

VCCGT56

T36

VCCGT57

T38

VCCGT58

T40

VCCGT59

U34

VCCGT60

U35

VCCGT61

U36

VCCGT62

U37

VCCGT63

U38

VCCGT64

U39

VCCGT65

U40

VCCGT66

V33

VCCGT67

V34

VCCGT68

V36

VCCGT69

V38

VCCGT70

V40

VCCGT71

W34

VCCGT72

W35

VCCGT73

W36

VCCGT74

W37

VCCGT75

W38

VCCGT76

Y33

VCCGT77

Y34

VCCGT78

Y36

VCCGT79

Y38

VCCGT80

CFL_S62_IP_CR B_CFLS_LGA

@

VCCGT_SENSE

VSSGT_SENSE

F39 F38

+VCCGT

12

RC691 100_0402_ 1%

12

RC690 100_0402_ 1%

VCCGT_VCC_SEN <9 1> VCCGT_VSS_SEN <91>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date : Sheet of

2

Date : Sheet of

Compal Electronics, Inc.

CFL-S POWER

LA-G881P

1

9 101Tuesday, January 08, 201 9

1.0

5

4

3

2

1

UC1F

A4

VSS_NCTF_A4

AG2

VSS_AG2

AG3

VSS_AG3

AG33

VSS_AG33

AG36

VSS_AG36

AG4

VSS_AG4

AG5

VSS_AG5

D D

C C

B B

AH33

VSS_AH33

AG8

VSS_AG8

AH36

VSS_AH36

AH37

VSS_AH37

AH38

VSS_AH38

AH39

VSS_AH39

AH5

VSS_AH5

AH40

VSS_AH40

AJ1

VSS_AJ1

AH8

VSS_AH8

AG1

VSS_AG1

A15

VSS_A15

A13

VSS_A13

A24

VSS_A24

AA3

VSS_AA3

AA33

VSS_AA33

A11

VSS_A11

A17

VSS_A17

AA8

VSS_AA8

AB39

VSS_AB39

AC33

VSS_AC33

AC3

VSS_AC3

AB5

VSS_AB5

AC34

VSS_AC34

AC35

VSS_AC35

AC6

VSS_AC6

AD33

VSS_AD33

AD1

VSS_AD1

AD38

VSS_AD38

AD39

VSS_AD39

AD4

VSS_AD4

AD6

VSS_AD6

AD40

VSS_AD40

AD7

VSS_AD7

AD8

VSS_AD8

AE3

VSS_AE3

AE36

VSS_AE36

AE5

VSS_AE5

AE33

VSS_AE33

AF1

VSS_AF1

AE8

VSS_AE8

AF33

VSS_AF33

AF36

VSS_AF36

AF37

VSS_AF37

AF40

VSS_AF40

AF5

VSS_AF5

AF8

VSS_AF8

A7

VSS_A7

AJ31

VSS_AJ31

AJ32

VSS_AJ32

AJ33

VSS_AJ33

AJ34

VSS_AJ34

AJ35

VSS_AJ35

AJ36

VSS_AJ36

AD37

VSS_AD37

CFL_S62 _IP_CRB_CFLS_L GA

@

VSS_AK5 VSS_AK8

VSS_AK9 VSS_AL14 VSS_AL11

VSS_AL1

VSS_AL2 VSS_AL21 VSS_AL24 VSS_AL27

VSS_AL3 VSS_AL30 VSS_AL36

VSS_AL4

VSS_AL5

VSS_AM11 VSS_AM14 VSS_AM17 VSS_AM19 VSS_AM24 VSS_AM27 VSS_AM30 VSS_AM31 VSS_AM32 VSS_AM33 VSS_AM34 VSS_AM35 VSS_AM36 VSS_AM37 VSS_AM38 VSS_AM39 VSS_AM40

VSS_AM5

VSS_AK7

VSS_AK6 VSS_AK40 VSS_AK37 VSS_AK36 VSS_AK30 VSS_AK29 VSS_AJ24 VSS_AJ30 VSS_AK22 VSS_AK27

VSS_AJ4 VSS_AJ5

VSS_AJ8 VSS_AK10 VSS_AK12 VSS_AK13 VSS_AK15 VSS_AK16 VSS_AK17 VSS_AK18 VSS_AK19 VSS_AK20 VSS_AK23 VSS_AK25 VSS_AK26 VSS_AK28

VSS_AD36

AK5 AK8 AK9 AL14 AL11 AL1 AL2 AL21 AL24 AL27 AL3 AL30 AL36 AL4 AL5 AM11 AM14 AM17 AM19 AM24 AM27 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AM40 AM5 AK7 AK6 AK40 AK37 AK36 AK30 AK29 AJ24 AJ30 AK22 AK27 AJ4 AJ5 AJ8 AK10 AK12 AK13 AK15 AK16 AK17 AK18 AK19 AK20 AK23 AK25 AK26 AK28 AD36

UC1K

AR3

VSS_AR3

AR4

VSS_AR4

AR5

VSS_AR5

AR24

VSS_AR24

AR27

VSS_AR27

AR30

VSS_AR30

AR31

VSS_AR31

AR32

VSS_AR32

AR33

VSS_AR33

AR34

VSS_AR34

AR35

VSS_AR35

AR36

VSS_AR36

AT5

VSS_AT5

AT6

VSS_AT6

AT7

VSS_AT7

AT8

VSS_AT8

AT9

VSS_AT9

AT10

VSS_AT10

AT11

VSS_AT11

AT12

VSS_AT12

AT13

VSS_AT13

AT14

VSS_AT14

AT17

VSS_AT17

AT24

VSS_AT24

AT25

VSS_AT25

AT26

VSS_AT26

AT27

VSS_AT27

AT28

VSS_AT28

AT29

VSS_AT29

AT30

?

VSS_AT30

AT31

VSS_AT31

AT32

VSS_AT32

AT34

VSS_AT34

AT36

VSS_AT36

AT37

VSS_AT37

AT38

VSS_AT38

AT39

VSS_AT39

AT40

VSS_AT40

AU1

VSS_AU1

AU4

VSS_AU4

AU5

VSS_AU5

AU7

VSS_AU7

AU25

VSS_AU25

AU30

VSS_AU30

AU34

VSS_AU34

AV2

VSS_AV2

AV5

VSS_AV5

AV9

VSS_AV9

AV26

VSS_AV26

AV28

VSS_AV28

AV30

VSS_AV30

AV34

VSS_AV34

AV38

VSS_AV38

AW3

VSS_AW3

AW5

VSS_AW5

AW9

VSS_AW9

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AY5

VSS_AY5

AY7

VSS_AY7

AY9

VSS_AY9

AY27

VSS_AY27

AY30

VSS_AY30

CFL_S62 _IP_CRB_CFLS_L GA

@

VSS_AN1 VSS_AN4 VSS_AN5 VSS_AN6 VSS_AN7 VSS_AN8

VSS_AN9 VSS_AN10 VSS_AN11 VSS_AN14 VSS_AN16 VSS_AN19 VSS_AN22 VSS_AN23 VSS_AN24 VSS_AN27 VSS_AN30 VSS_AN36

VSS_AP5 VSS_AP11 VSS_AP14 VSS_AP24 VSS_AP27 VSS_AP30 VSS_AP36 VSS_AP37 VSS_AP40

VSS_AR1

VSS_AR2 VSS_AR11 VSS_AR14 VSS_AR16 VSS_AR17 VSS_AR18 VSS_AR19 VSS_AR20 VSS_AR21 VSS_AR22 VSS_AR23

VSS_AT15 VSS_AU39 VSS_AU40 VSS_AV39

VSS_AW38

VSS_C5

VSS_C8 VSS_C10 VSS_C37

VSS_B24 VSS_B26 VSS_B28 VSS_B30 VSS_B38

VSS_NCTF_C2

VSS_C12 VSS_C14 VSS_C16 VSS_C18 VSS_C20 VSS_C22 VSS_C24 VSS_C31 VSS_C33 VSS_C35

VSS_B6

AN1 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN14 AN16 AN19 AN22 AN23 AN24 AN27 AN30 AN36 AP5 AP11 AP14 AP24 AP27 AP30 AP36 AP37 AP40 AR1 AR2 AR11 AR14 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AT15 AU39 AU40 AV39 AW38 C5 C8 C10 C37 B24 B26 B28 B30 B38 C2 C12 C14 C16 C18 C20 C22 C24 C31 C33 C35 B6

UC1L

D40

VSS_NCTF_D40

K4

VSS_K4

K7

VSS_K7

K39

VSS_K39

L3

VSS_L3

L6

VSS_L6

L9

VSS_L9

L13

VSS_L13

L32

VSS_L32

M1

VSS_M1

M4

VSS_M4

M7

VSS_M7

M10

VSS_M10

M12

VSS_M12

M15

VSS_M15

M17

VSS_M17

M19

VSS_M19

M21

VSS_M21

M23

VSS_M23

M25

VSS_M25

M27

VSS_M27

M29

VSS_M29

M35

VSS_M35

M37

VSS_M37

M39

VSS_M39

N3

VSS_N3

N6

VSS_N6

N8

VSS_N8

N33

VSS_N33

P1

VSS_P1

P4

VSS_P4

P35

VSS_P35

P37

VSS_P37

P39

VSS_P39

R3

VSS_R3

R6

VSS_R6

R8

VSS_R8

R33

VSS_R33

T1

VSS_T1

T4

VSS_T4

T35

VSS_T35

T37

VSS_T37

T39

VSS_T39

U3

VSS_U3

U6

VSS_U6

U33

VSS_U33

V1

VSS_V1

V8

VSS_V8

V35

VSS_V35

V37

VSS_V37

V39

VSS_V39

W3

VSS_W3

W6

VSS_W6

W33

VSS_W33

Y5

VSS_Y5

Y35

VSS_Y35

Y37

VSS_Y37

K15

VSS_K15

K17

VSS_K17

K19

VSS_K19

K22

VSS_K22

K24

VSS_K24

K26

VSS_K26

K28

VSS_K28

K30

VSS_K30

K33

VSS_K33

K35

VSS_K35

K37

VSS_K37

L11

VSS_L11

CFL_S62 _IP_CRB_CFLS_L GA

@

VSS_D4

VSS_D7 VSS_D24 VSS_D26 VSS_D28 VSS_D30 VSS_D37 VSS_D39

VSS_E3

VSS_E6

VSS_E9 VSS_E11 VSS_E13 VSS_E15 VSS_E17 VSS_E19 VSS_E21 VSS_E23 VSS_E31 VSS_E33 VSS_E35 VSS_E37

VSS_F1

VSS_F4

VSS_F7 VSS_F10 VSS_F22 VSS_F26 VSS_F28 VSS_F30 VSS_F36 VSS_F40

VSS_G3

VSS_G6

VSS_G11 VSS_G13 VSS_G15 VSS_G17 VSS_G19 VSS_G22 VSS_G31 VSS_G33

VSS_H1

VSS_H4

VSS_H7

VSS_H9 VSS_H11 VSS_H12 VSS_H21 VSS_H24 VSS_H26 VSS_H28 VSS_H30 VSS_H35 VSS_H37 VSS_H39

VSS_J3

VSS_J6 VSS_J10 VSS_J12 VSS_J16 VSS_J18 VSS_J20 VSS_J32 VSS_J34

VSS_K1

VSS_K14

D4 D7 D24 D26 D28 D30 D37 D39 E3 E6 E9 E11 E13 E15 E17 E19 E21 E23 E31 E33 E35 E37 F1 F4 F7 F10 F22 F26 F28 F30 F36 F40 G3 G6 G11 G13 G15 G17 G19 G22 G31 G33 H1 H4 H7 H9 H11 H12 H21 H24 H26 H28 H30 H35 H37 H39 J3 J6 J10 J12 J16 J18 J20 J32 J34 K1 K14

TC16 @ TC15 @ TC13 @ TC12 @

For debug

PCH_TRIGG ER<17> CPU_TRIGG ER<17>

TC17 @ TC18 @

TC19 @ TC14 @

1 2

RC692 30_04 02_5%

1 2

RC36 20_0402_5 %

RSVD_TP 2 RSVD_TP 1 IST_TRIG RSVD_TP 3

RSVD8 RSVD9

RSVD20 RSVD24

CPU_2_P CH_TRIG_C

UC1J

J8

RSVD_TP2

J7

RSVD_TP1

L8

IST_TRIG

K8

RSVD_TP3

AV1

RSVD8

AW2

RSVD9

H8

RSVD13

K10

RSVD20

L10

RSVD24

J17

RSVD18

B39

RSVD10

C40

RSVD11

J19

RSVD19

G8

VSS_G8

AY3

VSS_AY3

D1

PROC_TRIGIN

B3

PROC_TRIGOUT

L12

RSVD25

K12

RSVD22

CFL_S62 _IP_CRB_CFLS_L GA

@

RSVD4 RSVD1 RSVD2 RSVD3

RSVD5 RSVD12 RSVD21

RSVD17 RSVD16

RSVD7

RSVD6

RSVD15 RSVD23 RSVD14

AC37 AB35 AB37 AB38 AJ22 D15 K11

J15 J14

AU9 AU10

J13 K13 J11

A A

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Custom

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

CFL-S GND, RSVD

LA-G881P

1

1.0

10 101Tu esday, January 08, 2019

5

4

3

2

1

+3V_PCH

#571182_CNL_PCH_H_ EDS_V1_Re v0.7

External pull-up is required. Recommend 100K if pull ed up to 3.3V or 75K if pulled up to 1.8V. 57100 7_CFL_MOW_A rchive _WW22 _2017

D D

C C

STUFF R on GPP_H15

+3V_PCH

This signal has a weak internal pull -down. 0 = Master Attached Flash Sharing (MAFS) enabled (Default) 1 = Slave Attached Flash Sharing (SAFS) enabled. Notes:

1. This signal is in the primary well.

Warning: This strap must be configured to ‘0’ if t he eSPI or LPC strap is configured to ‘0’

+3V_PCH

12

RH99 100K_0402_5%

1 2

RH100 4.7K_0402_5%@

1 2

RH631 100K_0402_5%

1 2

RH632 100K_0402_5%

1 2

RH633 100K_0402_5%

1 2

RH634 100K_0402_5%

1 2

RH635 20K_0402_5%~D

1 2

RH636 20K_0402_5%~D

CFL-H PDG rev1.1 pull-up 20K for SPI0_MOSI, SPI0_MISO,SPI0_IO2/3 pull-down 20K for SPI0_MLK, SPI0_CS[2:0]#

GPP_H15

GPP_H12

PCH_SPI_0_SI

PCH_SPI_0_SO

PCH_SPI_0_WP#

PCH_SPI_0_HOLD#

PCH_SPI_0_CS#

PCH_SPI_0_CLK

EMI@

CH246 22P_0402_50V8J

CNP-H

1 OF 13

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_K15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

Rev1.0

AV29

Y47 Y46 Y48 W46 AA45

AL47 AM45 BF32 BC33

AE44 AJ46 AE43 AC47 AD48 AF47 AB47 AD47 AE48

BB44

PCH_PLTRST#

GPP_H15

GPP_H12

INTRUDER#

PCH_SPI_0_CS#

PCH_SPI_0_WP#_R

PCH_PLTRST# <74>

TBT_FORCE_PWR <42>

UH4

1

CS#

2

DO(IO1)

3

IO2

4

GND

W25Q128JVSIQ_SO8

DI(IO0)

VCC

CLK

IO

+3V_PCH

8

PCH_SPI_0_HOLD#_RPCH_SPI_0_SO_R

7

PCH_SPI_0_CLK_R

6

PCH_SPI_0_SI_R

5

+RTC_CELL

1 2

1

2

RH531 1M_0402_5%

CH49

0.1U_0402_16V7K

PCH_PLTRST#

12

RH1024 100K_0402_5%

@EMI@

RH591 33_0402_5%

1

@EMI@

CH232 33P_0402_50V8J

2

UH1A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

RH1 intel check list spec : Route from XDP_HOOK[3] to PCH-H SPI0_MOSI by placing a 1.5K± 5 % s eri es resi stor.

RH1 close to UH4

1 2

XDP_SPI_SI<79>

RH1 1K_0402_1%

PCH_SPI_0_WP#<79>

FFS_INT2<15,67> FFS_INT1<15,67>

PCH_SPI_0_HOLD# PCH_SPI_0_SO PCH_SPI_0_SI PCH_SPI_0_WP#

TC29 TC30

PCH_SPI_0_SI PCH_SPI_0_SO PCH_SPI_0_CS# PCH_SPI_0_CLK

PCH_SPI_0_WP# PCH_SPI_0_HOLD#

FFS_INT2 FFS_INT1

RPH5

4 5 3 6 2 7 1 8

33_0804_8P4R_5%

1 2

RH104 33_0402_1%EMI@

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_BGA874

@

PCH_SPI_0_HOLD#_R PCH_SPI_0_SO_R PCH_SPI_0_SI_R PCH_SPI_0_WP#_R

PCH_SPI_0_CLK_RPCH_SPI_0_CLK

1

2

1

B

2

A

+3VS

UH3

5

TC7SH08FU_SSOP5

P

Y

G

3

1

CH201

0.1U_0201_6.3V6K

2

4

12

RH199 100K_0402_5%

PCIRST# <42, 51,52,58,68>

UH1F

B B

USB3_PTX_DRX_N6<71>

Left JUSB1 Charger

Right JUSB3

A A

5

USB3_PTX_DRX_P6<71> USB3_PRX_DTX_N6<71> USB3_PRX_DTX_P6<71> USB3_PTX_DRX_N5<72> USB3_PTX_DRX_P5<72> USB3_PRX_DTX_N5<72> USB3_PRX_DTX_P5<72>

4

F9

F7 D11 C11

C3 D4

B9

C9

C17 C16

G14 F14 C15 B15

J13

K13

G12 F11 C10 B10

C14 B14

J15

K16

USB31_1_TXN USB31_1_TXP USB31_1_RXN USB31_1_RXP

USB31_2_TXN USB31_2_TXP USB31_2_RXN USB31_2_RXP

USB31_6_TXN USB31_6_TXP USB31_6_RXN USB31_6_RXP USB31_5_TXN USB31_5_TXP USB31_5_RXN USB31_5_RXP

USB31_3_TXP USB31_3_TXN USB31_3_RXP USB31_3_RXN

USB31_4_TXP USB31_4_TXN USB31_4_RXP USB31_4_RXN

CNP-H_BGA874

@

CNP-H

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_K19/SMI#

GPP_K18/NMI#

GPP_E6/SATA_DEVSLP2 GPP_E5/SATA_DEVSLP1 GPP_E4/SATA_DEVSLP0 GPP_F9/SATA_DEVSLP7 GPP_F8/SATA_DEVSLP6 GPP_F7/SATA_DEVSLP5 GPP_F6/SATA_DEVSLP4 GPP_F5/SATA_DEVSLP3

6 OF 13

Security Classification

3

BB39 AW37 AV37 BA38

ESPI_FRAME#

BE38

ESPI_SERIRQ

AW35 BA36

ESPI_KB_RST#

BE39

ESPI_RST#

BF38

BB36 BB34

T48 T47

AH40 AH35 AL48 AP47 AN37 AN46 AR47 AP48

Rev1.0

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RH89 33_0402_5%EMI@

ESPI_IO0 <58> ESPI_IO1 <58> ESPI_IO2 <58> ESPI_IO3 <58>

ESPI_FRAME# <58> ESPI_SERIRQ <58>

ESPI_KB_RST# <58> ESPI_RST# < 58>

1 2

@RF@

1

CH244

10P_0402_50V8J

DEVSLP1 <68> DEVSLP0 <67>

DEVSLP4 <68>

2018/03/29 2019/03/29

2

Compal Secret Data

Deciphered Date

CLK_PCI_ESPI <58>

2

ESPI_SERIRQ

ESPI_KB_RST#

Title

Size

Date: Sheet of

Date: Sheet o f

1 2

RH111 10K_0402_5%~D

1 2

RH518 10K_0402_5%~D

Compal Electronics, Inc.

PCH (1/7) SPI, ESPI

Document Number Re v

LA-G881P

1

+1.8VS_EC

1.0

11 101T uesday, January 08, 2019

1.0

5

HDA_SDOUT_R<56> HDA_SYNC_R<56>

D D

EC interface

High eSPI

+3V_PCH

C C

B B

Low(default) LPC

1 2

RH1023 4.7K_0402_5%

1 2

RH95 4.7K_0402_5%@

This signal has a weak internal Pull-down. 0 = D isable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default) 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Int el AMT with TLS. Notes:

1. The internal Pull-down is disabled after RSMRST# de-asserts .

2. This signal is in the primary well.

SML0ALERT#

SMBALERT#

+RTC_CELL

1 2

RH83 20K_0402_5%~D

+RTC_CELL

1 2

RH84 20K_0402_5%~D

1U_0603_10V6K~D

TC28 RH515 8.2K_0402_5%

HDA_BIT_CLK_R<56>

CPU_DISPA_SDO<6> CPU_DISPA_SDI_R< 6> CPU_DISPA_BCLK<6>

EC_RSMRST#<58>

1

CH52

2

1

12

CH53

SHORT PADS

2

RP2 33_0201_5% RP6 33_0201_5% RP7 33_0201_5%

RF@

12

CH243 10P_0402_50V8J

HDA_SDIN<56>

ME_EN<58>

PCH_SRTCRST#

PCH_RTCRST#

CLRP1

CLRP1 in DIMM door

4

1 2 1 2 1 2

RT707 33_0402_5%

RH16 33_0402_5%

RH39 20_0402_5%

RH38 30_0402_5%

RH1017 0_0402_5%

PCH_SMBCLK<23,24,25,26,63,67> PCH_SMBDATA<23,24,25,26,63,67>

HDA_SDOUT HDA_SYNC HDA_RST#

1 2

CLKREQ_CNV#<52> TBT_PCIE_WAKE# <42,58> CNV_RF_RESET#<52>

PCH_RTCRST#<59> PCH_SRTCRST#<59>

PCH_PWROK<58>

SML0CLK<74> SML0DATA<74>

HDA_BIT_CLK

HDA_SDOUT HDA_SYNC

HDA_RST#

CPU_DISPA_SDO_R

CPU_DISPA_BCLK_R

PCH_RTCRST# PCH_SRTCRST#

EC_RSMRST#

PCH_DPWROK

12

SMBALERT# PCH_SMBCLK

PCH_SMBDATA SML0ALERT#

SML0CLK SML0DATA

PCH_SML1ALERT#

SML1CLK SML1DATA

UH1D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_CLK

AV16

GPP_D18/DMIC_DATA1/SNDW3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_CLK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWROK

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BGA874

@

+3V_PCH

RH63 150K_0402_1%@

This signal has an internal pul l-down. 0 = D isable IntelR DCI-OOB (Default) 1 = Enable IntelR DCI-OOB

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. When used as PCHHOT# and strap low, a 150K pull-up is needed to ensure it does not override the internal pull-down s trap sampling.

3

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

GPP_A13/SUSWARN#/SUSPWRDNACK

4 OF 13

1 2

PCH_SML1ALERT#

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX

PCH_JTAG_TMS

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

Rev1.0

BF36 AV32

BF41

BD42

BB46 BE32 BF33 BE29 R47 AP29 AU3

BB47 BE40 BF40 BC28 BF42 BE42 BC42

BE45 BF44 BE35 BC37

BG44 BG42 BD39 BE46 AU2 AW29 AE3

AL3 AH4 AJ4 AH3 AH2 AJ3

CLKRUN#

WAKE#

RH4 0_0402_5%

RH1018 0_0402_5%

PCH_BATLOW# SUSACK#

RH1016 0_0402_5%@

ME_SUS_PWR_ACK

WAKE_PCH# AC_PRESENT

PBTN_OUT# SYS_RESET# HDA_SPKR

2

H_DRAMRST# <23>

SYS_PWROK < 58>

12

@

12

PBTN_OUT# <58>

HDA_SPKR <56> H_CPUPWRGD <6>

XDP_ITP_PMODE <79> PCH_JTAG_TCK <6, 79> XDP_TMS <6,79>

XDP_TDO <6> XDP_TDI <6,79> XDP_TCK1 <79>

WAKE#

PCH_BATLOW#

AC_PRESENT

WAKE_PCH#

ME_SUS_PWR_ACK

SYS_RESET#

CLKRUN#

PCIE_WAKE# <51,58>

PM_SLP_S3# <6,58,62,78,83,85> PM_SLP_S4# <58,78> PM_SLP_S5# <58,62>

SUSCLK <68> PCH_BATLOW# <42>

PCH_PWR_EN <12,58,78,88,98>

12

DH1

@

RB751V-40_SOD323-2

10K_0402_5%

@

12

RH1025

HDA_SPKR

Top Swap Override 0 = Disable Top Swap mode (Default) 1 = Enable Top Swap m ode. The i nternal Pull-down is disabled af t er PCH P WROK i s hi gh.

1 2

RH453 1K_0402_5%

1 2

RH533 8.2K_0402_5%@

1 2

RH545 10K_0402_5%

1 2

RH506 1M_0402_5%@

1 2

RH571 8.2K_0402_5%

1 2

RH85 8.2K_0402_5%

VCIN1_AC_IN <58,85>

1 2

RH600 100K_0402_5%@

1

+3V_PCH

+3VS

+3VALW

12

RH2

+3V_PCH

1 2

RH460 1K_0402_5%

1 2

RH461 1K_0402_5%

+3VS

1 2

RH501 499_0402_1%

1 2

RH502 499_0402_1%

1 2

RH463 1K_0402_5%

1 2

RH462 1K_0402_5%

1 2

RH88 10K_0402_5%

A A

5

SML1CLK

SML1DATA

SML0CLK

SML0DATA

PCH_SMBCLK

PCH_SMBDATA

EC_RSMRST#

SML1CLK

SML1DATA

4

+3VS

5

3

QH5B

DMN66D0LDW-7

2

6 1

QH5A

DMN66D0LDW-7

4

EC_SMB_CK2 <37,58,63,74,77>

EC_SMB_DA2 <37,58,63,74,77>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

10K_0402_5%

PBTN_OUT# SYS_RESET#

12

CH174

0.1U_0402_10V

+3VS

12

@

RH5 1K_0402_5%

0.1U_0402_10V

CH175

12

@

Compal Secret Data

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

2

+1.8VALW +3VALW

RH1027

10K_0402_5%

1 2

SUSACK#

12

RH1026 10K_0402_5%

G

123

D

S

QH1 MESS138W-G_SOT323-3

PCH_PWR_EN

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

PCH (2/7) PM,HDA,SMB,JTAG

Document Number Re v

LA-G881P

PCH_PWR_EN <12,58,78,88,98>

12 101T uesday, January 08, 2019

1

12 101T uesday, January 08, 2019

1.0

5

UH1

S IC A31 FHSSKU04 QNDQ A1 BGA 874P PCH-H

SA0000B4I0L

D D

M.2 SSD Slot#2 PCIe/SATA

C C

SATA HDD

M.2 SSD Slot#2 PCIe/SATA

M.2 SSD Slot#1 PCIe/SATA

CPCHES@

UH1

S IC A31 FHZ390 QQLP B0 BGA 874P PCH-H

SA0000C500L CPCHQS@

PCIE_PTX_C_DRX_P 11<68> PCIE_PTX_C_DRX_N 11<68>

PCIE_PRX_DTX_P11<68> PCIE_PRX_DTX_N11<68>

SATA_PTX_C_DRX_N 0< 67> SATA_PTX_C_DRX_P 0<67>

SATA_PRX_C_DTX_N 0<67> SATA_PRX_C_DTX_P 0<67>

PCIE_PTX_C_DRX_P 12<68> PCIE_PTX_C_DRX_N 12<68>

PCIE_PRX_DTX_P12<68> PCIE_PRX_DTX_N12<68>

PCIE_PTX_C_DRX_P 20<68> PCIE_PTX_C_DRX_N 20<68>

PCIE_PRX_DTX_P20<68>

PCIE_PRX_DTX_N20<68> PCIE_PTX_C_DRX_P 19<68> PCIE_PTX_C_DRX_N 19<68>

PCIE_PRX_DTX_P19<68>

PCIE_PRX_DTX_N19<68>

CH227 0 .01U_0201_16V7 CH228 0 .01U_0201_16V7 CH229 0 .01U_0201_16V7 CH230 0 .01U_0201_16V7

1 2 1 2 1 2 1 2

4

UH1C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

XMP1<87> XMP2<87>

PCIE_PTX_DRX_P11

12

CH2060.22U_0201_ 6.3V

PCIE_PTX_DRX_N11

12

CH2070.22U_0201_ 6.3V

SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0

PCIE_PTX_DRX_P12

12

CH2080.22U_0201_ 6.3V

PCIE_PTX_DRX_N12

12

CH2090.22U_0201_ 6.3V

PCIE_PTX_DRX_P20

12

CH2170.22U_0201_ 6.3V

PCIE_PTX_DRX_N20

12

CH2160.22U_0201_ 6.3V

PCIE_PTX_DRX_P19

12

CH2150.22U_0201_ 6.3V

PCIE_PTX_DRX_N19

12

CH2140.22U_0201_ 6.3V

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BGA874

@

3

CNP-H

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE15_RXN/SATA2_RXN PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THRMTRIP#

PM_SYNC

3 OF 13

PLTRST_CPU#

PM_DOWN

PECI

Rev1.0

G36 F36 C34 D34

K37 J37 C35 B35

F44 E45 B40 C40

L41 M40 B41 C41

K43 K44 A42 B42

P41 R40 C42 D42

AK48

AH41 AJ43 AK47 AN47 AM46 AM43 AM47 AM48

AU48 AV46 AV44

AD3 AF2 AF3 AG5 AE2

PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9

PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10

PCIE_PTX_DRX_N17 PCIE_PTX_DRX_P17

PCIE_PTX_DRX_N18 PCIE_PTX_DRX_P18

PCH_SATADET#

H_THERMT RIP#_R

H_PM_SYNC

12 12

PCIE_PRX_DTX_N15 <51>

PCIE_PRX_DTX_P15 <5 1>

PCIE_PTX_DRX_N15 <51> PCIE_PTX_DRX_P15 <5 1>

PCIE_PRX_DTX_N16 <52>

PCIE_PRX_DTX_P16 <5 2>

PCIE_PTX_DRX_N16 <52> PCIE_PTX_DRX_P16 <5 2>

PCH_SATADET# < 67>

SATA_GP0 < 67> SATA_GP1 < 68>

SATA_GP4 < 68>

1 2

RH79 620_0402 _5%

1 2

RH15 30_0402_ 5%

12

@

RH14

12.1_0402_ 1%

2

PCIE_PRX_DTX_N9 <6 8>

CH2020.22U_0201_6 .3V CH2030.22U_0201_6 .3V

CH2040.22U_0201_6 .3V CH2050.22U_0201_6 .3V

PCIE_PRX_DTX_P9 <68 > PCIE_PTX_C_DRX_N 9 <68> PCIE_PTX_C_DRX_P 9 < 68>

PCIE_PRX_DTX_N10 < 68> PCIE_PRX_DTX_P10 <6 8> PCIE_PTX_C_DRX_N 10 <68> PCIE_PTX_C_DRX_P 10 <68>

M.2 SSD Slot#1 PCIe/SATA

1

LAN

WLAN

PCIE_PRX_DTX_N17 < 68>

12

CH2100.22U_0201_6 .3V

12

CH2110.22U_0201_6 .3V

12

CH2120.22U_0201_6 .3V

12

CH2130.22U_0201_6 .3V

PCIE_PRX_DTX_P17 <6 8> PCIE_PTX_C_DRX_N 17 <68> PCIE_PTX_C_DRX_P 17 <68>

PCIE_PRX_DTX_N18 < 68>

PCIE_PRX_DTX_P18 <6 8> PCIE_PTX_C_DRX_N 18 <68> PCIE_PTX_C_DRX_P 18 <68>

PCH_SATADET#

H_THERMT RIP# <6 >

H_PECI <6> H_PM_SYNC_R <6 > CPU_PLTRS T# <6> H_PM_DOW N < 6>

M.2 SSD Slot#1 PCIe/SATA

1 2

RH512 10K_0402_5%

+3VS

B B

UH1E

CPU_DP1_HPD<42> CPU_DP2_HPD<42>

12

RH9

100K_0402 _5%

A A

5

4

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DPPD_HPD2/DISP_MISC2

AL15

GPP_I3/DPPE_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_BGA874

@

CNP-H

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

5 OF 13

CPU_DP1_C TRL_CLK

GPP_K21 GPP_K20

Issued Date

Rev1.0

AL13

CPU_DP1_C TRL_DATA

AR8

CPU_DP2_C TRL_CLK

AN13

CPU_DP2_C TRL_DATA

AL10 AL9

PCH_DP3_C TRL_DATA

AR3

PCH_DP4_C TRL_DATA

AN40 AT49

AP41

M45 L48 T45 T46 AJ47

2018/03/29 2019/03/29

PROC_DETEC T# <6>

STRAP3_PCH <3 7> STRAP5_PCH <3 7>

Compal Secret Data

Deciphered Date

2

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_F22/DDPF_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1 GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCH_DP3_C TRL_DATA

PCH_DP4_C TRL_DATA

CPU_DP1_C TRL_CLK

CPU_DP1_C TRL_DATA

CPU_DP2_C TRL_CLK

CPU_DP2_C TRL_DATA

DDP[B..F]CTRLDAT A

This signal has a weak internal Pull-down. 0 = Port B~D is not det ected. 1 = Port B,C,D is detected. ( Default) Notes:

1. The internal Pull-down is disabled after PCH_PWROK de-asserts.

2. This signal is in the primary well.

Title

Size Document Number Re v

Date : Sheet of

2.2K_0402_5 %

Compal Electronics, Inc.

PCH (3/7) SATA,DDC,PCIE

PCH (3/7) SATA,DDC,PCIE LA-G881P

LA-G881P

1

+3VS

RH601

12

RH602

12

RH604

12

RH605

12

RH607

12

RH606

12

1.0

13 101Tuesday, January 08, 2019

1.0

5

CNP-H

UH1B

DMI_CTX _PRX_N0< 7> DMI_CTX _PRX_P 0<7>

DMI_CRX _PTX_N0< 7>

DMI_CRX _PTX_P 0<7> DMI_CTX _PRX_N1< 7> DMI_CTX _PRX_P 1<7>

DMI_CRX _PTX_N1< 7>

DMI_CRX _PTX_P 1<7> DMI_CTX _PRX_N2< 7>

D D

Right JUSB2

Caldera

C C

B B

A A

DMI_CTX _PRX_P 2<7>

DMI_CRX _PTX_N2< 7>

DMI_CRX _PTX_P 2<7> DMI_CTX _PRX_N3< 7> DMI_CTX _PRX_P 3<7>

DMI_CRX _PTX_N3< 7>

DMI_CRX _PTX_P 3<7>

USB3_PR X_DTX_ N7<72> USB3_PR X_DTX_ P7<72 > USB3_PT X_DRX_ N7<72> USB3_PT X_DRX_ P7<72 > USB3_PR X_DTX_ N8<74> USB3_PR X_DTX_ P8<74 > USB3_PT X_DRX_ N8<74> USB3_PT X_DRX_ P8<74 >

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

DMI7_TXP

B25

DMI7_TXN

P24

DMI7_RXP

R24

DMI7_RXN

C26

DMI6_TXP

B26

DMI6_TXN

F26

DMI6_RXP

G26

DMI6_RXN

B27

DMI5_TXP

C27

DMI5_TXN

L26

DMI5_RXP

M26

DMI5_RXN

D29

DMI4_TXP

E28

DMI4_TXN

K29

DMI4_RXP

M29

DMI4_RXN

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BGA8 74

@

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3# GPP_F15/USB2_OC4# GPP_F16/USB2_OC5# GPP_F17/USB2_OC6# GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_COMP

USB2_ID

PCIE24_TXP PCIE24_TXN PCIE24_RXP

PCIE24_RXN

PCIE23_TXP PCIE23_TXN PCIE23_RXP

PCIE23_RXN

PCIE22_TXP PCIE22_TXN PCIE22_RXP

PCIE22_RXN

PCIE21_TXP PCIE21_TXN PCIE21_RXP

PCIE21_RXN

RSVD1

GPD7

Rev1.0

J3 J2 N13 N15 K4 K3 M10 L9 M1 L2 K7 K6 L4 L3 G4 G5 M6 N8 H3 H2 R10 P9 G1 G2 N3 N2 E5 F6

AH36 AL40 AJ44 AL41 AV47 AR35 AR37 AV43

F4 F3 U13 G3

BE41

G45 G46 Y41 Y40 G48 G49 W44 W43 H48 H47 U41 U40 F46 G47 R44 T43

4

USB_OC0 # USB_OC1 # USB_OC2 # USB_OC3 #

USB2_CO MP

GPD_7

PCIE_C TX_C_T RX_P2 4 PCIE_C TX_C_T RX_N24 PCIE_C RX_C_T TX_P2 4 PCIE_C RX_C_T TX_N24 PCIE_C TX_C_T RX_P2 3 PCIE_C TX_C_T RX_N23 PCIE_C RX_C_T TX_P2 3 PCIE_C RX_C_T TX_N23 PCIE_C TX_C_T RX_P2 2 PCIE_C TX_C_T RX_N22 PCIE_C RX_C_T TX_P2 2 PCIE_C RX_C_T TX_N22 PCIE_C TX_C_T RX_P2 1 PCIE_C TX_C_T RX_N21 PCIE_C RX_C_T TX_P2 1 PCIE_C RX_C_T TX_N21

USB20_N1 <71> USB20_P 1 <71> USB20_N2 <72> USB20_P 2 <72> USB20_N3 <74> USB20_P 3 <74> USB20_N4 <62> USB20_P 4 <62>

USB20_N6 <37> USB20_P 6 <37> USB20_N7 <37> USB20_P 7 <37> USB20_N8 <72> USB20_P 8 <72> USB20_N9 <75> USB20_P 9 <75> USB20_N1 0 <6 3> USB20_P 10 <63 > USB20_N1 1 <4 4> USB20_P 11 <44 >

USB20_N1 4 <5 2> USB20_P 14 <52 >

USB_OC0 # <7 1> USB_OC1 # <7 2>

1 2

RH109 113_0402 _1%

1 2

RH580 1K_0402_ 5%

1K_040 2_5%

1 2

RH581

1 2

CH247 0.22 U_0201 _6.3V

1 2

CH248 0.22 U_0201 _6.3V

1 2

CH249 0.22 U_0201 _6.3V

1 2

CH250 0.22 U_0201 _6.3V

1 2

CH251 0.22 U_0201 _6.3V

1 2

CH252 0.22 U_0201 _6.3V

1 2

CH253 0.22 U_0201 _6.3V

1 2

CH254 0.22 U_0201 _6.3V

1 2

CH255 0.22 U_0201 _6.3V

1 2

CH256 0.22 U_0201 _6.3V

1 2

CH257 0.22 U_0201 _6.3V

1 2

CH258 0.22 U_0201 _6.3V

1 2

CH259 0.22 U_0201 _6.3V

1 2

CH260 0.22 U_0201 _6.3V

1 2

CH261 0.22 U_0201 _6.3V

1 2

CH262 0.22 U_0201 _6.3V

+3VS

RH517 8.2K_04 02_5%@

RH520 8.2K_04 02_5%@

RH521 10K_04 02_5%

RC62 49.9 K_0402 _1%

RC63 49.9 K_0402 _1%

RH516 10K_04 02_5%@

RH588 10K_04 02_5%@

RH589 10K_04 02_5%@

UART_2_ PTXD_D RXD UART_2_ PRXD_D TXD

JUSB1 (Left) sid e (Power Share,Debug Port) JUSB2 (Right) Caldera AlienFX/ELC

Touch screen

Digital camera JUSB3 (Right) Tobii (17" o nly) Per key Thunderbolt PD

BT

USB2_COMP Trace Width = 5 mils Trace Spacing to Other Signals = 15 mils Trace Length < 1000 mils

PCIE_C TX_TRX _P24 <45>

PCIE_C TX_TRX _N24 <45> PCIE_C RX_TTX _P24 < 45> PCIE_C RX_TTX _N24 <45>

PCIE_C TX_TRX _P23 <45>

PCIE_C TX_TRX _N23 <45> PCIE_C RX_TTX _P23 < 45> PCIE_C RX_TTX _N23 <45>

PCIE_C TX_TRX _P22 <45>

PCIE_C TX_TRX _N22 <45> PCIE_C RX_TTX _P22 < 45> PCIE_C RX_TTX _N22 <45>

PCIE_C TX_TRX _P21 <45>

PCIE_C TX_TRX _N21 <45> PCIE_C RX_TTX _P21 < 45> PCIE_C RX_TTX _N21 <45>

12

+5VALW

JWDB

1

2

3

G1

4

G2

ACES_8 8266-04 001

CONN@

BT_OFF #

WL_OF F#

EC_SCI #

UART_2_ PRXD_D TXD

UART_2_ PTXD_D RXD

DGPU_PW ROK

VROM_SE L

5 6

1 2

USB_OC0 # USB_OC1 # USB_OC3 # USB_OC2 #

Thunderbolt

+3VALW

RH706 8.2K_04 02_5%@

RH707 8.2K_04 02_5%@

HDMI_HPD_ PCH<37 > DP_HPD_ PCH<37>

TBT_PC IE_WA KE_N<42 >

TBT_RT D3_RST #<42>

TBT_CI O_PLUG_ EVENT#<42 >

UART_2_ PTXD_D RXD<52>

UART_2_ PRXD_D TXD<52>

RTD3_US B_PWR _EN<42> RTD3_C IO_PW R_EN< 42>

1 2

ELC_BO OT_MODE<62>

TP_INT#<58 ,63>

GC6_EV ENT#<37>

ELC_RE SET<62>

EC_SCI #<58>

GC6_FB _EN<37>

WL_OF F#<52>

BT_OFF #<52>

I2C_0_ SCL<63> I2C_0_ SDA<6 3>

4 5 3 6 2 7 1 8

10K_8P 4R_5%

RPH6

3

+3V_PCH

GPD_7

X'tal Input: High: Differential Low: Single ended

BT_OFF #

WL_OF F#

BBS_BI T0

EC_SCI # VROM_SE L

NRB_BIT

WL_OF F# BT_OFF #

1 2

RT694 0_0201 _5%RT D3@

UART_2_ PTXD_D RXD UART_2_ PRXD_D TXD

I2C_0_ SCL I2C_0_ SDA

DGPU_PW ROK

12

RH594 100K_0 402_5%

12

RH11 10K_04 02_5%

@

UH1K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BGA8 74

@

BOARD_ ID

CNP-H

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GS PI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/ GSPI2_MOSI

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

1 2

RH21 10K _0201_ 5%

GPP_D9/ISH_SPI_CS#/GSPI2_CS0# GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0

2

nVidia GPU_ID

N17EG3

N17EG2

N17EG1

N17PG1

+3V_PCH +3V_PCH

N17_ID1

N17_ID0

GSYNC_ID

BOARD_ ID

BA20

DGPU_HOLD _RST#

BB20

PEX_RS T#

BB16

DGPU_PW R_EN

AN18

N17_ID1

BF14

N17_ID0

AR18

I2C2_S CL

BF17

I2C2_S DA

BE17

AG45 AH46

AH47 AH48

PCH_ACC 1_INT1

AV34

PCH_GYRO_ INT2

AW32 BA33 BE34

ISH_GP1

BD34 BF35

CLKDET # DGPU_PR SNT#

BD38

Rev1.0

@

RH135 10K_04 02_5%

1 2

N17_ID0

N17_ID1

H

L

1 2

RH25 10K _0201_ 5%@

1 2

RH26 10K _0201_ 5%@

1 2

RH27 10K _0201_ 5%@

1 2

RH28 10K _0201_ 5%@

@GSYNC@

1 2

RH29 10K _0201_ 5%

1 2

RH30 10K _0201_ 5%

@NGSYNC@

DGPU_HOLD _RST# <3 7> PEX_RS T# <3 7> DGPU_PW R_EN <58 >

I2C2_S CL <6 6> I2C2_S DA <6 6>

To G+Gyro sensor

ISH_I2C 0_SCL <66> ISH_I2C 0_SDA <66>

ISH_I2C 1_SCL <66> ISH_I2C 1_SDA <66>

PCH_ACC 1_INT1 <66 > PCH_GYRO_ INT2 <66>

ISH_GP1 <58>

H

L

H

L

RH25

N17EG3@

S RES 1/20W 10K +-5% 0201

SD0431 00280

RH25

N17EG2@

S RES 1/20W 10K +-5% 0201

SD0431 00280

RH26

N17EG1@

S RES 1/20W 10K +-5% 0201

SD0431 00280

I2C_0_ SDA I2C_0_ SCL I2C2_S DA I2C2_S CL

DGPU_PW R_EN

RH537 10K_02 01_5%

CLKDET #

RH558 10K_02 01_5%@

BBS_BI T0

RH130 4.7K_04 02_5% ~D@

Boot BIOS Strap Bit (internal PD) HIGH

LOW(DEFAULT)

NRB_BIT

RH524 4.7K_04 02_5% ~D@

NO REBOOT mode (internal PD) HIGH

LOW(DEFAULT)

RH27

S RES 1/20W 10K +-5% 0201

SD0431 00280

RH28

S RES 1/20W 10K +-5% 0201

SD0431 00280

RH27

S RES 1/20W 10K +-5% 0201

SD0431 00280

RPC7

1 8 2 7 3 6 4 5

10K_08 04_8P4 R_5%

1 2

12

LPC SPI

12

Enable Disabl e

1

N17EG3@

N17EG2@

N17EG1@

+3VS

+3V_PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Data

2018/03/29 2019/03/29

Deciphered Date

Compal Electronics, Inc.

Title

PCH (4/7) DMI,PCIE,USB,I2C

Size

Document Number Rev

LA-G881P

Date: Sheet of

1

14 101T uesday, January 08 , 2019

1.0

+1.8VALW

5

4

3

2

1

1 2

RH181 20K_0402_1%@

1 2

RH182 20K_0402_1%@

RH180

1 2

D D

RH603 4.7K_0402_5%

575179_Intel_Pulsar_CNVio_Schematic_Checklist_Rev 3.1

+1.8V_PRIM

1 2

RH219 20K_0402_1%

1 2

RH220 10K_0402_5%@

An e xternal pull-high or pull-down is required

0 = Intergrated CNVi enable 1 = Intergrated CNVi disable

+1.8V_PRIM

+3VS

10K_0804_8P4R_5%

1 2 1 2 1 2 1 2

12

RP3

4 5 3 6 2 7 1 8

C C

B B

RH218 10K_0402_5%@

The signal has a weak internal pull-dow n 0 = VCCPSPI is connected to 3.3V rail 1 = VCCPSPI is connected to 1.8V rail Note: If VCCPSPI is connected to 1.8V rail, this pin strap must be a 1 fo r the proper functionality of the SPI (Flash) I /Os

+3VS

RP5 10K_0201_5% RP8 10K_0201_5% RP9 10K_0201_5% RP10 10K_0201_5%

CNV_BRI_PRX_DTX

CNV_RGI_PRX_DTX

CPU_VCCIO_PWR_GATE#

10K_0402_5%@

CNV_BRI_PTX_DRX

CNV_RGI_PTX_DRX_R

CNV_BRI_PTX_DRX_R<52>

CNV_BRI_PRX_DTX<52>

CNV_RGI_PTX_DRX_R<52>

CNV_RGI_PRX_DTX<52>

GPP_J9

Net : XCLK_BIASREF Trace Width/Space: 15mil /15 mil Max Trace Length: 1000 mil

CLKREQ_PEG#0 CLKREQ_PCIE#1 CLKREQ_PCIE#2 CLKREQ_PCIE#4

CLKREQ_PEG#6 CLKREQ_PCIE#5 FFS_INT2 FFS_INT1

FFS_INT2 <11,67> FFS_INT1 <11,67>

RH1021 0_0201_5%

RH200 0_0201_5%

+1VALW

1 2

RH590 60.4_0402_1%

PEG(dGPU) SSD1 SSD2 Thunderbolt LAN WLAN Caldera

1 2

CPU_24MHZ_P<6> CPU_24MHZ_N<6>

PCH_CPU_BCLK_P< 6> PCH_CPU_BCLK_N<6>

RH71 2.7K_0402_1%

1 2

@

XCLK_BIASREF

CLKREQ_PEG#0<37> CLKREQ_PCIE#1<68> CLKREQ_PCIE#2<68> CLKREQ_PCIE#3<42> CLKREQ_PCIE#4<51> CLKREQ_PCIE#5<52> CLKREQ_PEG#6<58,74>

CPU_VCCIO_PWR_GATE#

CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX

GPP_J9

XTAL24_OUT XTAL24_IN

XCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

UH1M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_DATA0

BF8

GPP_G2/SD_DATA1

BF9

GPP_G3/SD_DATA2

BG8

GPP_G4/SD_DATA3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_C10_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J4/CNV_BRI_DT/UART0B_RTS#

AY2

GPP_J5/CNV_BRI_RSP/UART0B_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0B_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CNP-H_BGA874

@

UH1G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BGA874

@

CNP-H

CNV_WT_RCOMP

GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P82 GPPJ_RCOMP_1P83

13 OF 13

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

7 OF 13

CLKIN_XTAL

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WT_D0N CNV_WT_D0P CNV_WT_D1N CNV_WT_D1P

PCIE_RCOMPN PCIE_RCOMPP

RSVD2 RSVD3

RSVD1

Rev1.0

BD4 BE3

BB3 BB4 BA3 BA2

BC5 BB6

BE6 BD7 BG6 BF6

CNV_WT_RCOMP

BA1

PCIE_RCOMPN

B12

PCIE_RCOMPP

A13

SD_RCOMP_1P8

BE5

SD_RCOMP_3P3

BE4 BD1 BE1

GPPJ_RCOMP_1P8

BE2

Y35 Y36

BC1 AL35

TP

#571483_CFL_H_RVP_CRB_TDK_Rev0p7

CNV_WR_CLKN CNV_WR_CLKP

CNV_WT_CLKN CNV_WT_CLKP

SD_1P8_RCOMP SD_3P3_RCOMP

Recommend external test point

PCH_XDP_CLK_N

Y3

PCH_XDP_CLK_P

Y4

B6 A6

AJ6 AJ7

AH9 AH10

AE14 AE15

AE6 AE7

AC2 AC3

AB2 AB3

W4 W3

W7 W6

AC14 AC15

U2 U3

AC9 AC11

AE9 AE11

REFCLK_CNV_H REFCLK_CNV

Rev1.0

R6

CNVI@

RH628 10K_0402_5%

1 2

RH213 150_0402_1%

1 2

RH193 100_0402_1%

1 2

RH214 200_0402_1%

1 2

RH215 200_0402_1%

1 2

RH216 200_0402_1%

T372 PAD~D @ T135 PAD~D @

T49 PAD~D TP@ T50 PAD~D TP@

PCH_CPU_PCIBCLK_N <6> PCH_CPU_PCIBCLK_P <6>

CLK_PEG_N0 <37> CLK_PEG_P0 <37>

CLK_PCIE_N1 <68> CLK_PCIE_P1 <68>

CLK_PCIE_N2 <68> CLK_PCIE_P2 <68>

CLK_PCIE_N3 <45> CLK_PCIE_P3 <45>

CLK_PCIE_N4 <51> CLK_PCIE_P4 <51>

CLK_PCIE_N5 <52> CLK_PCIE_P5 <52>

CLK_PEG_N6 <74> CLK_PEG_P6 <74>

RN117

1 2

0_0201_5%

12

15P_0402_50V

REFCLK_CNV <52>

CLK_CNV_PRX_DTX_N <52> CLK_CNV_PRX_DTX_P <52>

CNV_PRX_DTX_N0 <52> CNV_PRX_DTX_P0 <52> CNV_PRX_DTX_N1 <52> CNV_PRX_DTX_P1 <52>

CLK_CNV_PTX_DRX_N <52>

CLK_CNV_PTX_DRX_P <52>

CNV_PTX_DRX_N0 <52>

CNV_PTX_DRX_P0 <52>

CNV_PTX_DRX_N1 <52>

CNV_PTX_DRX_P1 <52>

24MHZ 12PF +-10PPM 7M24090001

1

CH47

2

10P_0402_50V8J

RH72 1M_0402_5%~D

1 2

YH2

123

CH45

4

RH70 10M_0402_5%

1 2

32.768KHZ_X1A000141000300

1 2

1

2

XTAL24_IN_R

XTAL24_OUT_R

1

CH48 15P_0402_50V

2

PCH_RTCX1

PCH_RTCX2

YH1

1

CH46 10P_0402_50V8J

2

EMI@

RH91 33_0201_5%

1 2

EMI@

RH92 33_0201_5%

XTAL24_IN

XTAL24_OUT

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size

Date: Sheet o f

Compal Electronics, Inc.

PCH (5/7) CNVI, CLK

Document Number Re v

LA-G881P

1

15 101T uesday, January 08, 2019

1.0

5

D D

+1VALW

1 2

RH12 0_0805_5%

+1.05V_XTAL +1.05V_VCCAMPHYPLL +1.05V_VCCAMPHYPLL

1

CH56

47U_0805_6.3V6M

C C

2

+1V_MPHY

CH263

47U_0805_6.3V6M

1

2

Close to P2, P3 Close to C49, D49, E49

4

+1V_MPHY

+1VALW

LH2

1 2

2.2UH_FCI1608F_10%

LH1

1 2

2.2UH_FCI1608F_10%

+1VALW

+1.05V_XTAL

UH1H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

@

3

8 OF 13

CNP-H

VCCPRIM_3P32

VCCPRIM_3P35

VCCPGPPG_3P3

VCCPRIM_3P33 VCCPRIM_3P34

VCCPRIM_3P31 VCCDSW_3P31 VCCDSW_3P32

VCCPRIM_1P83 VCCPRIM_1P84 VCCPRIM_1P85 VCCPRIM_1P86 VCCPRIM_1P87

VCCPRIM_1P81 VCCPRIM_1P82

VCCPRIM_1P0520 VCCPRIM_1P0519

VCCPRIM_1P241 VCCPRIM_1P242

VCCDPHY_1P241 VCCDPHY_1P242 VCCDPHY_1P243

VCCMPHY_SENSE

VSSMPHY_SENSE

DCPRTC1 DCPRTC2

VCCSPI

VCCRTC1 VCCRTC2

VCCPGPPHK1 VCCPGPPHK2 VCCPGPPEF1 VCCPGPPEF2

VCCPGPPD VCCPGPPBC1 VCCPGPPBC2

VCCPGPPA

VCCHDA

Rev1.0

AW9

BF47 BG47

V23

AN44

BC49 BD49

AN21 AY8 BB7

AC35 AC36 AE35 AE36

AN24 AN26 AP26

AN32

AT44 BE48 BE49

BB14 AG19 AG20 AN15 AR15 BB11

AF19 AF20

AG31 AF31 AK22 AK23

AJ22 AJ23 BG5

K47 K46

1 2

CH226 0.1U_0402_10V7K

RH598 0_0402_5%@

4.7U_0402_6.3V6M

1

2

+RTC_CELL

1 2

CH36

2

+VCCRTCEXT

+1.24V_DPHY

+3V_PCH

+1VALW

+1.8V_PRIM

RH6 0_0402_5%@ RH7 0_0402_5%

+1.8V_PRIM

+VCCRTCEXT

1 2 1 2

1 2

RH599 0_0402_5%

2

0.1U_0402_10V7K

1

+1.8VALW

1

CH264

+3VALW

+3V_PCH

2.2P_0402_50V8

CH231

1

2

CH245

0.1U_0402_10V7K

2

1

9/11:change from SE000000K80 to SE00000UC00*2

+1V_MPHY

CH83

1U_0201_6.3V6M

CH82

1U_0201_6.3V6M

1

SE00000UC00

2

B B

2

9/12:change from SE000000I10 to SE00000M000*2

Close to B1,B2,B3,C1,C2 Close to U26,U29V25,V27,V28,V30,V31 Close to AG19,AG20

+3V_PCH

1U_0603_10V6K

CH182

1

2

A A

Close to AY8,BB7 Close to AG19,AG20

5

+3V_PCH

Close to BE48,BE49

+1VALW

22U_0603_6.3V6M

CH181

CH189

1

2

0.1U_0402_10V7K

1

CH186

2

CH183

1U_0201_6.3V6M

CH180

1U_0201_6.3V6M

1

SE00000UC00

2

+RTC_CELL

CH80

1U_0201_6.3V6M

CH81

1U_0201_6.3V6M

1

2

1

SE00000UC00

2

+1V_MPHY

Close to C49,D49,E49

0.1U_0402_10V7K

CH173

CH184

1U_0201_6.3V6M

CH187

1U_0201_6.3V6M

1

SE00000UC00

2

,AB20,AB22,AB23,AB27,AB28,AB30 ,AD20,AD23,AD27,AD28,AD30,AF23 ,AF27,AF30,AE17

Close to BC49,BD49

4

+1VALW

CH185

1U_0201_6.3V6M

CH188

1U_0201_6.3V6M

1

SE00000UC00

2

1

2

+1.8V_PRIM

CH177

1U_0201_6.3V6M

SE00000UC00

CH176

1U_0201_6.3V6M

1

SE00000UC00

2

,AR15,AN15,BB11

+1.8V_PRIM

4.7U_0603_6.3V6M

CH233

1

@

2

,AR15,AN15,BB11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

2

+3V_PCH +3V_PCH

0.1U_0402_10V7K

1

CH190

2

Close to AE35,AE36 Close to AC35,AC36Close to AF31,AG31,AD31,AA22,AA23

Title

PCH (6/7) PWR

Size

Document Number Re v

LA-G881P

Date: Sheet o f

0.1U_0402_10V7K

1

CH192

2

Compal Electronics, Inc.

16 101T uesday, January 08, 2019

1

16 101T uesday, January 08, 2019

1.0

5

D D

CNP-H

UH1I

A2

VSS

A28

VSS

A3

VSS

A33

VSS

A37

VSS

A4

VSS

A45

VSS

A46

VSS

A47

VSS

A48

VSS

A5

VSS

A8

VSS

AA19

VSS

AA20

VSS

AA25

VSS

AA27

VSS

AA28

VSS

AA30

VSS

AA31

VSS

AA49

VSS

AA5

VSS

AB19

VSS

AB25

VSS

AB31

VSS

AC12

C C

B B

AC17 AC33 AC38

AC46

AD19

AD22 AD25 AD49 AE12 AE33 AE38

AE46 AF22 AF25 AF28

AG22 AG23 AG25 AG27 AG28 AG30 AG49 AH12 AH17 AH33 AH38

AJ19 AJ20 AJ25 AJ27 AJ28 AJ30

AJ31 AK19 AK20 AK25 AK27 AK28 AK30 AK31

AK46

AC4

AD1

AD2

AE4

AG1

AK4

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

9 OF 13

VSS

CNP-H_BGA874

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1.0

AL12 AL17 AL21 AL24 AL26 AL29 AL33 AL38 AM1 AM18 AM32 AM49 AN12 AN16 AN34 AN38 AP4 AP46 AR12 AR16 AR34 AR38 AT1 AT16 AT18 AT21 AT24 AT26 AT29 AT32 AT34 AT45 AV11 AV39 AW10 AW4 AW40 AW46 B47 B48 B49 BA12 BA14 BA44 BA5 BA6 BB41 BB43 BB9 BC10 BC13 BC15 BC19 BC24 BC26 BC31 BC35 BC40 BC45 BC8 BD43 BE44 BF1 BF2 BF3 BF48 BF49 BG17 BG2 BG22 BG25 BG28

4

CNP-H

BG3 BG33 BG37

BG4 BG48

C12

C25

C30

C48

D12

D16

D17

D30

D33

G44

M16

M18

M21

C4

C5

D8 E10 E13 E15 E17 E19 E22 E24 E26 E31 E33 E35 E40 E42

E8 F41 F43 F47

G6

H8 J10 J26 J29

J4 J40 J46 J47 J48

J9 K11 K39

UH1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

12 OF 13

VSS

CNP-H_BGA874

@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev1.0

M24 M32 M34 M49 M5 N12 N16 N34 N35 N37 N38 P26 P29 P4 P46 R12 R16 R26 R29 R3 R34 R38 R4 T17 T18 T32 T4 T49 T5 T7 U12 U15 U17 U21 U24 U33 U38 V20 V22 V4 V46 W25 W27 W28 W30 Y10 Y12 Y17 Y33 Y38 Y9

3

UH1J

TRIGGER_OUT

10 OF 13

CNP-H_BGA874

@

CNP-H

RSVD7 RSVD8 RSVD6 RSVD5

RSVD3 RSVD4

RSVD2 RSVD1

PREQ# PRDY#

CPU_TRST#

TRIGGER_IN

Rev1.0

2

Y14 Y15 U37 U35

N32 R32

AH15 AH14

AL2 AM5 AM4 AK3 AK2

XDP_PREQ# <6,79> XDP_PRDY# <6,79>

CPU_XDP_TRST# <6,79> PCH_TRIGGER <10> CPU_TRIGGER <10>

1

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (7/7) GND

LA-G881P

1

1.0

17 101Tuesday, January 08, 2019

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Reserved

Reserved LA-G881P

LA-G881P

E

1.0

18 101Tuesday, January 08, 2019

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Reserved

Reserved LA-G881P

LA-G881P

E

1.0

19 101Tuesday, January 08, 2019

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Reserved

Reserved LA-G881P

LA-G881P

E

1.0

20 101Tuesday, January 08, 2019

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Reserved

Reserved LA-G881P

LA-G881P

E

1.0

21 101Tuesday, January 08, 2019

1.0

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date : Sheet of

D

Date : Sheet of

Compal Electronics, Inc.

Reserved

Reserved LA-G881P

LA-G881P

E

1.0

22 101Tuesday, January 08, 2019

1.0

A

B

C

D

E

Interleaved

Layout Note:

2

1

VDDSPD1

2

CD23

2.2U_0402_6.3V6M

1

1 2

Place near JDIMM1

1

2

2.2uF* 1

0.1uF* 1

CD19

2.2U_0402_6.3V6M

+1.2V_DDR

1 2

RD9 2_0402_ 1%

1

2

10uF*8 1uF*8 330uF* 1

10U_0603_6.3V6M

CD3

CD2

CD1

1

2

12

RD51 470_0402_1%

H_DRAMRST# <12>

0.1U_0402_16V7K~D

CD125

@ESD@

1

2

10U_0603_6.3V6M

CD4

1

2

+0.6V_DDR_REFCA_A

10U_0603_6.3V6M

CD6

CD5

1

2

+1.2V_DDR+1.2V_DDR

10U_0603_6.3V6M

CD8

CD9

1U_0201_6.3V6M

CD10

CD7

1

2

VDDSPD1

1U_0201_6.3V6M

1

SE00000UC00

2

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS1

2

VSS2

5

VSS3

6

VSS4

9

VSS5

10

VSS6

14

VSS7

15

VSS8

18

VSS9

19

VSS10

22

VSS11

23

VSS12

26

VSS13

27

VSS14

30

VSS15

31

VSS16

35

VSS17

36

VSS18

39

VSS19

40

VSS20

43

VSS21

44

VSS22

47

VSS23

48

VSS24

51

VSS25

52

VSS26

56

VSS27

57

VSS28

60

VSS29

61

VSS30

64

VSS31

65

VSS32

68

VSS33

69

VSS34

72

VSS35

73

VSS36

77

VSS37

78

VSS38

81

VSS39

82

VSS40

85

VSS41

86

VSS42

89

VSS43

90

VSS44

93

VSS45

94

VSS46

98

VSS47

262

GND1

LOTES_ADDR0205-P001A02~D

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94

GND2

CD11

1U_0201_6.3V6M

1

SE00000UC00

2

VTT

CPU SideDIMM1/2 Side

1

CD31

0.022U_0402_25V7K

2

RD11

24.9_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

D

+1.2V_DDR

CD13

1U_0201_6.3V6M

CD14

1U_0201_6.3V6M

CD12

1U_0201_6.3V6M

1

SE00000UC00

2

+1.2V_DDR+1.2V_DDR

141 142 147 148 153 154 159 160 163

258

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

CD15

1U_0201_6.3V6M

1

SE00000UC00

2

+0.6VS

+2.5V_MEM

1

CD16

1U_0201_6.3V6M

+

CD17 330U_D2_2VM_R6M

SE00000UC00

2

Layout Note: Place near JDIMM1

+0.6VS

1

2

Layout Note: Place near JDIMM1

+2.5V_MEM

1

2

Compal Electronics, Inc.

Title

Size

Document Num ber Re v

Date : Sheet of

JDIMM1

1 1

2 2

+1.2V_DDR

1 2

3 3

4 4

RD7 240_0402_1%

DDR_A_DRAMRST#<25>

+3VS +3VS +3VS

@

1 2

RD2 0_0402_5%

RD5 0_0402_5%

RD1 0_0402_5%

1 2

SA0_DIM1 SA1_DIM1 SA2_DIM1

@

RD4

0_0402_5%

1 2

@

RD3 0_0402_5%

0_0402_5%

RD6

PLACE ALL THE BELOW RESIS TORS CLOSE TO SODIMM

(4.0 mm) STD

DDR_A_CLK2<8>

DDR_A_CLK#2<8>

DDR_A_CLK3<8>

DDR_A_CLK#3<8>

DDR_A_CKE2<8> DDR_A_CKE3<8>

DDR_A_CS#2<8> DDR_A_CS#3<8>

TD1 @ TD2 @

DDR_A_ODT2<8> DDR_A_ODT3<8>

DDR_A_BG0<8,25> DDR_A_BG1<8,25> DDR_A_BA0<8,25> DDR_A_BA1<8,25>

DDR_A_MA[0..13]<8,25>

DDR_A_WE#<8,25> DDR_A_CAS#<8,25> DDR_A_RAS#<8,25>

DDR_A_ACT#<8,25>

DDR_A_PAR<8,25>

DDR_A_ALERT#<8,25>

PCH_SMBDATA<12,24,25,26,63,67> PCH_SMBCLK<12,24,25,26,63,67>

DDR_A_DRAMRST#

A

1

2

0.1U_0402_16V7K~D

CD134

TP_DIMM1_CHA_S2# TP_DIMM1_CHA_S3#

DIMM1_CHA_EVENT# DDR_A_DRAMRST#

@ESD@

+1.2V_DDR

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

SA2_DIM1 SA1_DIM1 SA0_DIM1

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0205-P001A02~D

CONN@

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DDR_A_D0

8

DDR_A_D1

DQ0

7

DQ1

DDR_A_D2

20

DQ2

DDR_A_D3

21

DQ3

DDR_A_D4

4

DQ4

DDR_A_D5

3

DDR_A_D6

DQ5

16

DQ6

DDR_A_D7

17

DQ7

13 11

DDR_A_D8

28

DQ8

DDR_A_D9

29

DQ9

DDR_A_D10

41

DDR_A_D11

42

DDR_A_D12

24

DDR_A_D13

25

DDR_A_D14

38

DDR_A_D15

37 34 32

DDR_A_D16

50

DDR_A_D17

49

DDR_A_D18

62

DDR_A_D19

63

DDR_A_D20

46

DDR_A_D21

45

DDR_A_D22

58

DDR_A_D23

59 55 53

DDR_A_D24

70

DDR_A_D25

71

DDR_A_D26

83

DDR_A_D27

84

DDR_A_D28

66

DDR_A_D29

67

DDR_A_D30

79

DDR_A_D31

80 76 74

DDR_A_D32

174

DDR_A_D33

173

DDR_A_D34

187

DDR_A_D35

186

DDR_A_D36

170

DDR_A_D37

169

DDR_A_D38

183

DDR_A_D39

182 179 177

DDR_A_D40

195

DDR_A_D41

194

DDR_A_D42

207

DDR_A_D43

208

DDR_A_D44

191

DDR_A_D45

190

DDR_A_D46

203

DDR_A_D47

204 200 198

DDR_A_D48

216

DDR_A_D49

215

DDR_A_D50

228

DDR_A_D51

229

DDR_A_D52

211

DDR_A_D53

212

DDR_A_D54

224

DDR_A_D55

225 221 219

DDR_A_D56

237

DDR_A_D57

236

DDR_A_D58

249

DDR_A_D59

250

DDR_A_D60

232

DDR_A_D61

233

DDR_A_D62

245

DDR_A_D63

246 242 240

B

DIMM1

DIMM2

DIMM3

DIMM4

DDR_A_D[0..7] <8,25>

DDR_A_DQS0 <8,25> DDR_A_DQS#0 <8,25>

DDR_A_D[8..15] <8,25>

DDR_A_DQS1 <8,25> DDR_A_DQS#1 <8,25>

DDR_A_D[16..23] <8,25>

DDR_A_DQS2 <8,25> DDR_A_DQS#2 <8,25>

DDR_A_D[24..31] <8,25>

DDR_A_DQS3 <8,25> DDR_A_DQS#3 <8,25>

DDR_A_D[32..39] <8,25>

DDR_A_DQS4 <8,25> DDR_A_DQS#4 <8,25>

DDR_A_D[40..47] <8,25>

DDR_A_DQS5 <8,25> DDR_A_DQS#5 <8,25>

DDR_A_D[48..55] <8,25>

DDR_A_DQS6 <8,25> DDR_A_DQS#6 <8,25>

DDR_A_D[56..63] <8,25>

DDR_A_DQS7 <8,25> DDR_A_DQS#7 <8,25>

SA0 SA1 SA2

1 0 0

0 0

0

1

0 1

0

DDR_B_DRAMRST#<24,26>

.1U_0402_16V7K

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM1

+0.6V_DDR_REFCA_A

1

CD18

0.1U_0402_16V7K

2

+3VS

RD58 0_0603_5%

1 2

1

CD22

.1U_0402_16V7K

2

PLACE NEAR TO PIN

DDR_A_DRAMRST#

DDR_B_DRAMRST#

+1.2V_DDR

1

CD29

2

1 2

RD8 1K_0402_1%

RD10 1K_0402_1%

RD52 0_0402_5%

RD62 0_0402_5%

+0.6V_DDR_REFCA_A +0.6V_VREF_CA

CD30

@

.1U_0402_16V7K

C

10U_0603_6.3V6M

1

CD20

2

10uF*1 1uF*1

10U_0603_6.3V6M

CD27

1U_0201_6.3V6M

1

CD25

SE00000UC00

2

DDR4_DIMM1

LA-G881P

E

Layout Note: For RF Place near JDIMM1

+1.2V_DDR

@RF@

0.5P_0402_50V8

CH240

1

2

10uF*1 1uF*2

CD21

1U_0201_6.3V6M

CD28

1U_0201_6.3V6M

1

CD24

SE00000UC00

2

23 10 1Tuesday, January 08, 2019

@RF@

10P_0402_50V8J

CH241

1

2

1.0

A

Interleaved

B

C

D

E

JDIMM2

1 1

DIMM1

DIMM2

DIMM3

DIMM4

SA0 SA1 SA2

1 0 0

0 0

0

1

0 1

0

+3VS +3VS +3VS

RD26 0_0402_5%

1 2

SA0_DIM3 SA1_DIM3 SA2_DIM3

@

RD29

0_0402_5%

1 2

RD27 0_0402_5%

@

RD30 0_0402_5%

1 2

@

RD28 0_0402_5%

0_0402_5%

RD31

Layout Note: Place near JDIMM3

10U_0603_6.3V6M

CD65

CD66

CD64

1

2

10uF*8 1uF*8 330uF* 1

+1.2V_DDR+1.2V_DDR

10U_0603_6.3V6M

CD68

CD67

1

2

10U_0603_6.3V6M

CD69

CD70

CD71

1

2

CD73

1U_0201_6.3V6M

CD72

1U_0201_6.3V6M

1

SE00000UC00

2

CD76

1U_0201_6.3V6M

CD74

CD75

1U_0201_6.3V6M

1

SE00000UC00

2

CD77

1U_0201_6.3V6M

1

SE00000UC00

2

+1.2V_DDR

CD78

1U_0201_6.3V6M

1

SE00000UC00

2

1

CD79

1U_0201_6.3V6M

+

CD80 330U_D2_2VM_R6M

SE00000UC00

2

Layout Note: For RF Place near JDIMM3

+1.2V_DDR

@RF@

10P_0402_50V8J

0.5P_0402_50V8

CH237

CH236

1

2

PLACE ALL THE BELOW RESIS TORS CLOSE TO SODIMM

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM3

(8.0 mm) RVS

JDIMM2A

REVERSE

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

SA2_DIM3 SA1_DIM3 SA0_DIM3

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0070-P025A~D

CONN@

2 2

+1.2V_DDR

1 2

RD32 240_0402_1%

3 3

DDR_B_DRAMRST#<23,26>

4 4

DDR_B_CLK#2<8>

DDR_B_CLK#3<8>

DDR_B_CKE2<8> DDR_B_CKE3<8>

DDR_B_CS#2<8> DDR_B_CS#3<8>

DDR_B_ODT2<8> DDR_B_ODT3<8>

DDR_B_MA[0..13]<8,26>

DDR_B_ALERT#<8,26>

PCH_SMBDATA<12,23,25,26,63,67> PCH_SMBCLK<12,23,25,26,63,67>

DDR_B_DRAMRST#

A

DDR_B_CLK2<8>

DDR_B_CLK3<8>

TP_DIMM3_CHB_S2#

TD5 @

TD6 @

DDR_B_BG0<8,26>

DDR_B_BG1<8,26>

DDR_B_BA0<8,26>

DDR_B_BA1<8,26>

DDR_B_WE#<8,26> DDR_B_CAS#<8,26> DDR_B_RAS#<8,26>

DDR_B_ACT#<8,26>

DDR_B_PAR<8,26>

0.1U_0402_16V7K~D

1

2

TP_DIMM3_CHB_S3#

DIMM3_CHB_EVENT#

DDR_B_DRAMRST#

CD133

@ESD@

+1.2V_DDR

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DDR_B_D0

8

DDR_B_D1

DQ0

7

DQ1

DDR_B_D2

20

DQ2

DDR_B_D3

21

DQ3

DDR_B_D4

4

DQ4

DDR_B_D5

3

DDR_B_D6

DQ5

16

DQ6

DDR_B_D7

17

DQ7

13 11

DDR_B_D8

28

DQ8

DDR_B_D9

29

DQ9

DDR_B_D10

41

DDR_B_D11

42

DDR_B_D12

24

DDR_B_D13

25

DDR_B_D14

38

DDR_B_D15

37 34 32

DDR_B_D16

50

DDR_B_D17

49

DDR_B_D18

62

DDR_B_D19

63

DDR_B_D20

46

DDR_B_D21

45

DDR_B_D22

58

DDR_B_D23

59 55 53

DDR_B_D24

70

DDR_B_D25

71

DDR_B_D26

83

DDR_B_D27

84

DDR_B_D28

66

DDR_B_D29

67

DDR_B_D30

79

DDR_B_D31

80 76 74

DDR_B_D32

174

DDR_B_D33

173

DDR_B_D34

187

DDR_B_D35

186

DDR_B_D36

170

DDR_B_D37

169

DDR_B_D38

183

DDR_B_D39

182 179 177

DDR_B_D40

195

DDR_B_D41

194

DDR_B_D42

207

DDR_B_D43

208

DDR_B_D44

191

DDR_B_D45

190

DDR_B_D46

203

DDR_B_D47

204 200 198

DDR_B_D48

216

DDR_B_D49

215

DDR_B_D50

228

DDR_B_D51

229

DDR_B_D52

211

DDR_B_D53

212

DDR_B_D54

224

DDR_B_D55

225 221 219

DDR_B_D56

237

DDR_B_D57

236

DDR_B_D58

249

DDR_B_D59

250

DDR_B_D60

232

DDR_B_D61

233

DDR_B_D62

245

DDR_B_D63

246 242 240

B

DDR_B_D[0..7] <8,26>

DDR_B_DQS0 <8,26> DDR_B_DQS#0 <8,26>

DDR_B_D[8..15] <8,26>

DDR_B_DQS1 <8,26> DDR_B_DQS#1 <8,26>

DDR_B_D[16..23] <8,26>

DDR_B_DQS2 <8,26> DDR_B_DQS#2 <8,26>

DDR_B_D[24..31] <8,26>

DDR_B_DQS3 <8,26> DDR_B_DQS#3 <8,26>

DDR_B_D[32..39] <8,26>

DDR_B_DQS4 <8,26> DDR_B_DQS#4 <8,26>

DDR_B_D[40..47] <8,26>

DDR_B_DQS5 <8,26> DDR_B_DQS#5 <8,26>

DDR_B_D[48..55] <8,26>

DDR_B_DQS6 <8,26> DDR_B_DQS#6 <8,26>

DDR_B_D[56..63] <8,26>

DDR_B_DQS7 <8,26> DDR_B_DQS#7 <8,26>

CD131

.1U_0402_16V7K

1

2

+1.2V_DDR

+0.6V_DDR_REFCA_B

1

2

.1U_0402_16V7K

RD55 1K_0402_1%

1 2

RD54 1K_0402_1%

1 2

CD81

.1U_0402_16V7K

CD85

2.2uF* 1

0.1uF* 1

2

CD82

2.2U_0402_6.3V6M

1

+3VS

RD60 0_0603_5%

1 2

VDDSPD3

2

1

CD86

2.2U_0402_6.3V6M

1

2

PLACE NEAR TO PIN

+0.6V_DDR_REFCA_B +0.6V_VREF_DQ

1 2

RD57 2_0402_1%

1

CD132

@

.1U_0402_16V7K

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

CPU SideDIMM3/4 Side

Issued Date

+0.6V_DDR_REFCA_B

1

CD130

0.022U_0402_25V7K

2

RD56

24.9_0402_1%

1 2

2018/03/29 2019/03/29

VDDSPD3

JDIMM2B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR0070-P025A~D

CONN@

Compal Secret Data

Deciphered Date

D

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

+1.2V_DDR+1.2V_DDR

141 142 147 148 153

+0.6VS

154 159 160 163

258

VTT

257 259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+2.5V_MEM

Layout Note: Place near JDIMM3

+0.6VS

1

2

Layout Note: Place near JDIMM3

+2.5V_MEM

1

2

Compal Electronics, Inc.

Title

Size

Document Num ber Re v

Date : Sheet of

10U_0603_6.3V6M

1

CD83

2

10uF*1 1uF*1

10U_0603_6.3V6M

CD89

1U_0201_6.3V6M

1

CD88

SE00000UC00

2

DDR4_DIMM2

LA-G881P

E

10uF*1 1uF*2

CD90

1U_0201_6.3V6M

CD84

1U_0201_6.3V6M

1

CD87

SE00000UC00

2

24 10 1Tuesday, January 08, 2019

1.0

A

Interleaved

B

C

D

E

JDIMM3

1 1

+3VS +3VS +3VS

@

RD12 0_0402_5%

1 2

SA0_DIM2 SA1_DIM2 SA2_DIM2

RD15

0_0402_5%

1 2

@

RD13 0_0402_5%

RD16 0_0402_5%

1 2

@

RD14 0_0402_5%

0_0402_5%

SA0 SA1 SA2

DIMM1

RD17

DIMM2

DIMM3

DIMM4

1 0 0

0 0

0

1

0 1

0

Layout Note: Place near JDIMM2

10U_0603_6.3V6M

CD33

CD32

1

2

10uF*8 1uF*8 330uF* 1

10U_0603_6.3V6M

CD36

CD34

CD35

CD37

1

2

+1.2V_DDR+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M

CD38

1

2

1U_0201_6.3V6M

CD39

1

2

CD42

1U_0201_6.3V6M

CD43

CD40

1

SE00000UC00

2

1U_0201_6.3V6M

CD41

1U_0201_6.3V6M

1

SE00000UC00

2

CD44

1U_0201_6.3V6M

1

SE00000UC00

2

CD46

1U_0201_6.3V6M

CD47

1U_0201_6.3V6M

CD45

1U_0201_6.3V6M

1

SE00000UC00

2

1

+

SE00000UC00

CD48

SE00000UC00

330U_D2_2VM_R6M

2

Layout Note: For RF Place near JDIMM2

+1.2V_DDR

@RF@

10P_0402_50V8J

0.5P_0402_50V8

CH239

CH238

1

2

PLACE ALL THE BELOW RESIS TORS CLOSE TO SODIMM

Layout Note: PLACE THE CAP WITHIN 200 MILS

REVERSE

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

STD

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

8 7 20 21 4 3 16 17 13 11

28 29 41 42 24 25 38 37 34 32

50 49 62 63 46 45 58 59 55 53

70 71 83 84 66 67 79 80 76 74

174 173 187 186 170 169 183 182 179 177

195 194 207 208 191 190 203 204 200 198

216 215 228 229 211 212 224 225 221 219

237 236 249 250 232 233 245 246 242 240

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_D[0..7] <8,23>

DDR_A_DQS0 <8,23> DDR_A_DQS#0 <8,23>

DDR_A_D[8..15] <8,23>

DDR_A_DQS1 <8,23> DDR_A_DQS#1 <8,23>

DDR_A_D[16..23] <8,23>

DDR_A_DQS2 <8,23> DDR_A_DQS#2 <8,23>

DDR_A_D[24..31] <8,23>

DDR_A_DQS3 <8,23> DDR_A_DQS#3 <8,23>

DDR_A_D[32..39] <8,23>

DDR_A_DQS4 <8,23> DDR_A_DQS#4 <8,23>

DDR_A_D[40..47] <8,23>

DDR_A_DQS5 <8,23> DDR_A_DQS#5 <8,23>

DDR_A_D[48..55] <8,23>

DDR_A_DQS6 <8,23> DDR_A_DQS#6 <8,23>

DDR_A_D[56..63] <8,23>

DDR_A_DQS7 <8,23> DDR_A_DQS#7 <8,23>

(8.0 mm)

JDIMM3A

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0069-P009A

CONN@

DDR_A_CLK0<8>

DDR_A_CLK#0<8>

DDR_A_CLK1<8>

2 2

+1.2V_DDR

1 2

RD18 240_0402_1%

3 3

DDR_A_CLK#1<8>

DDR_A_CKE0<8> DDR_A_CKE1<8>

DDR_A_CS#0<8> DDR_A_CS#1<8>

DDR_A_ODT0<8> DDR_A_ODT1<8>

DDR_A_BG0<8,23> DDR_A_BG1<8,23> DDR_A_BA0<8,23> DDR_A_BA1<8,23>

DDR_A_MA[0..13]<8,23>

DDR_A_WE#<8,23> DDR_A_CAS#<8,23> DDR_A_RAS#<8,23>

DDR_A_ACT#<8,23>

DDR_A_PAR<8,23>

DDR_A_ALERT#<8,23>

DDR_A_DRAMRST#<23>

PCH_SMBDATA<12,23,24,26,63,67>

PCH_SMBCLK<12,23,24,26,63,67>

TD3 @ TD4 @

TP_DIMM2_CHA_S2# TP_DIMM2_CHA_S3#

DIMM2_CHA_EVENT#

SA2_DIM2 SA1_DIM2 SA0_DIM2

+1.2V_DDR

4 4

CD51

.1U_0402_16V7K

CD54

.1U_0402_16V7K

FROM THE JDIMM2

+0.6V_DDR_REFCA_A

2

1

+3VS

RD59 0_0603_5%

1 2

VDDSPD2

1

2

CD55

2.2U_0402_6.3V6M

2

1

PLACE NEAR TO PIN

2.2uF* 1

0.1uF* 1

2

CD52

2.2U_0402_6.3V6M

1

+0.6V_DDR_REFCA_A

VDDSPD2

JDIMM3B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR0069-P009A

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

+1.2V_DDR+1.2V_DDR

141 142 147 148 153

+0.6VS

154 159 160 163

258

VTT

257 259

99

VSS

102

VSS

103

VSS

106

VSS

107

VSS

167

VSS

168

VSS

171

VSS

172

VSS

175

VSS

176

VSS

180

VSS

181

VSS

184

VSS

185

VSS

188

VSS

189

VSS

192

VSS

193

VSS

196

VSS

197

VSS

201

VSS

202

VSS

205

VSS

206

VSS

209

VSS

210

VSS

213

VSS

214

VSS

217

VSS

218

VSS

222

VSS

223

VSS

226

VSS

227

VSS

230

VSS

231

VSS

234

VSS

235

VSS

238

VSS

239

VSS

243

VSS

244

VSS

247

VSS

248

VSS

251

VSS

252

VSS

261

GND

+2.5V_MEM

Layout Note: Place near JDIMM2

+0.6VS

Layout Note: Place near JDIMM2

+2.5V_MEM

1

2

10uF*1 1uF*2

10U_0603_6.3V6M

1

CD53

CD49

2

10uF*1 1uF*1

10U_0603_6.3V6M

CD59

1U_0201_6.3V6M

1

CD56

SE00000UC00

2

CD58

1U_0201_6.3V6M

CD50

1U_0201_6.3V6M

1

SE00000UC00

2

need to change footprint

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Document Num ber Re v

Date : Sheet of

DDR4_DIMM3

LA-G881P

E

25 10 1Tuesday, January 08, 2019

1.0

A

Interleaved

B

C

D

E

JDIMM4

1 1

+3VS +3VS +3VS

@

RD38 0_0402_5%

1 2

SA0_DIM4 SA1_DIM4 SA2_DIM4

RD41

0_0402_5%

1 2

RD39 0_0402_5%

@

RD42 0_0402_5%

1 2

@

RD40 0_0402_5%

RD43

0_0402_5%

DIMM1

DIMM2

DIMM3

DIMM4

SA0 SA1 SA2

1 0 0

0 0

0

1

0 1

0

Layout Note: Place near JDIMM4

10U_0603_6.3V6M

CD96

CD94

CD95

1

2

10uF*8 1uF*8 330uF* 1

+1.2V_DDR+1.2V_DDR +1.2V_DDR

10U_0603_6.3V6M

CD97

CD98

1

2

10U_0603_6.3V6M

CD100

CD99

CD101

1

2

1U_0201_6.3V6M

CD102

1U_0201_6.3V6M

1

SE00000UC00

2

CD105

1U_0201_6.3V6M

CD103

CD104

1U_0201_6.3V6M

1

SE00000UC00

2

CD108

1U_0201_6.3V6M

CD109

1U_0201_6.3V6M

CD107

1U_0201_6.3V6M

CD106

1

SE00000UC00

2

1

+

SE00000UC00

CD110

SE00000UC00

330U_D2_2VM_R6M

2

Layout Note: For RF Place near JDIMM4

+1.2V_DDR

@RF@

0.5P_0402_50V8

10P_0402_50V8J

CH234

CH235

1

2

PLACE ALL THE BELOW RESIS TORS CLOSE TO SODIMM

Layout Note: PLACE THE CAP WITHIN 200 MILS

REVERSE

DQS0(T)

DQS0#(C)

DQS1(T)

DQS1#(C)

DQS2(T)

DQS2#(C)

DQS3(T)

DQS3#(C)

DQS4(T)

DQS4#(C)

DQS5(T)

DQS5#(C)

DQS6(T)

DQS6#(C)

DQS7(T)

DQS7#(C)

RVS

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

8 7 20 21 4 3 16 17 13 11

28 29 41 42 24 25 38 37 34 32

50 49 62 63 46 45 58 59 55 53

70 71 83 84 66 67 79 80 76 74

174 173 187 186 170 169 183 182 179 177

195 194 207 208 191 190 203 204 200 198

216 215 228 229 211 212 224 225 221 219

237 236 249 250 232 233 245 246 242 240

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7

DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15

DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23

DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39

DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_D[0..7] <8,24>

DDR_B_DQS0 <8,24> DDR_B_DQS#0 <8,24>

DDR_B_D[8..15] <8,24>

DDR_B_DQS1 <8,24> DDR_B_DQS#1 <8,24>

DDR_B_D[16..23] <8,24>

DDR_B_DQS2 <8,24> DDR_B_DQS#2 <8,24>

DDR_B_D[24..31] <8,24>

DDR_B_DQS3 <8,24> DDR_B_DQS#3 <8,24>

DDR_B_D[32..39] <8,24>

DDR_B_DQS4 <8,24> DDR_B_DQS#4 <8,24>

DDR_B_D[40..47] <8,24>

DDR_B_DQS5 <8,24> DDR_B_DQS#5 <8,24>

DDR_B_D[48..55] <8,24>

DDR_B_DQS6 <8,24> DDR_B_DQS#6 <8,24>

DDR_B_D[56..63] <8,24>

DDR_B_DQS7 <8,24> DDR_B_DQS#7 <8,24>

(4.0 mm)

JDIMM4A

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0206-P001A02~D

CONN@

DDR_B_CLK0<8>

DDR_B_CLK#0<8>

DDR_B_CLK1<8>

2 2

+1.2V_DDR

1 2

RD44 240_0402_1%

3 3

DDR_B_CLK#1<8>

DDR_B_CKE0<8> DDR_B_CKE1<8>

DDR_B_CS#0<8> DDR_B_CS#1<8>

DDR_B_ODT0<8> DDR_B_ODT1<8>

DDR_B_BG0<8,24> DDR_B_BG1<8,24> DDR_B_BA0<8,24> DDR_B_BA1<8,24>

DDR_B_MA[0..13]<8,24>

DDR_B_WE#<8,24> DDR_B_CAS#<8,24> DDR_B_RAS#<8,24>

DDR_B_ACT#<8,24>

DDR_B_PAR<8,24>

DDR_B_ALERT#<8,24>

DDR_B_DRAMRST#<23,24>

PCH_SMBDATA<12,23,24,25,63,67> PCH_SMBCLK<12,23,24,25,63,67>

TD7 @ TD8 @

TP_DIMM4_CHB_S2# TP_DIMM4_CHB_S3#

DIMM4_CHB_EVENT#

SA2_DIM4 SA1_DIM4 SA0_DIM4

+1.2V_DDR

4 4

CD113

.1U_0402_16V7K

CD116

.1U_0402_16V7K

FROM THE JDIMM4

+0.6V_DDR_REFCA_B

2

1

+3VS

RD61 0_0603_5%

1 2

VDDSPD4

2

1

CD117

2.2U_0402_6.3V6M

1

2

PLACE NEAR TO PIN

2.2uF* 1

0.1uF* 1

2

CD114

2.2U_0402_6.3V6M

1

+0.6V_DDR_REFCA_B

VDDSPD4

JDIMM4B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS1

2

VSS2

5

VSS3

6

VSS4

9

VSS5

10

VSS6

14

VSS7

15

VSS8

18

VSS9

19

VSS10

22

VSS11

23

VSS12

26

VSS13

27

VSS14

30

VSS15

31

VSS16

35

VSS17

36

VSS18

39

VSS19

40

VSS20

43

VSS21

44

VSS22

47

VSS23

48

VSS24

51

VSS25

52

VSS26

56

VSS27

57

VSS28

60

VSS29

61

VSS30

64

VSS31

65

VSS32

68

VSS33

69

VSS34

72

VSS35

73

VSS36

77

VSS37

78

VSS38

81

VSS39

82

VSS40

85

VSS41

86

VSS42

89

VSS43

90

VSS44

93

VSS45

94

VSS46

98

VSS47

262

GND1

LOTES_ADDR0206-P001A02~D

CONN@

VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19

VPP1 VPP2

VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94

GND2

+1.2V_DDR+1.2V_DDR

141 142 147 148 153 154 159 160 163

258

VTT

257 259

99 102 103 106 107 167 168 171 172 175 176 180 181 184 185 188 189 192 193 196 197 201 202 205 206 209 210 213 214 217 218 222 223 226 227 230 231 234 235 238 239 243 244 247 248 251 252

261

+0.6VS

+2.5V_MEM

Layout Note: Place near JDIMM4

+0.6VS

Layout Note: Place near JDIMM4

+2.5V_MEM

1

2

10uF*1 1uF*2

10U_0603_6.3V6M

1

CD115

CD111

2

10uF*1 1uF*1

10U_0603_6.3V6M

CD120

1U_0201_6.3V6M

1

CD118

SE00000UC00

2

CD112

1U_0201_6.3V6M

CD119

1U_0201_6.3V6M

1

SE00000UC00

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO A NY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELECTRONICS, INC.

2018/03/29 2019/03/29

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size

Document Num ber Re v

Date : Sheet of

DDR4_DIMM4

LA-G881P

E

26 10 1Tuesday, January 08, 2019

1.0

5

D D

C C

4

3

2

1

B B

A A

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reversed

Reversed LA-G881P

LA-G881P

1.0

27 101Tu esday, January 08, 2019

1

5

D D

C C

4

3

2

1

B B

A A

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reversed

Reversed LA-G881P

LA-G881P

1.0

28 101Tu esday, January 08, 2019

1

5

D D

C C

4

3

2

1

B B

A A

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reversed

Reversed LA-G881P

LA-G881P

1.0

29 101Tu esday, January 08, 2019

1

5

D D

C C

4

3

2

1

B B

A A

Security Classificat ion

2018/03/ 29 2019/03/ 29

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2018/03/ 29 2019/03/ 29

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Re v

Date : Sheet o f

2

Date : Sheet o f

Compal Electronics, Inc.

Reversed

Reversed LA-G881P

LA-G881P

1.0

30 101Tu esday, January 08, 2019

1

Dell Alienware Area 51M Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual