Dell 15-7537 Schematic

5

D D

4

3

2

1

Hadley15" Schematics Document

Haswell ULT

C C

2013-06-28

REV : A00

B B

DY : None Installed UMA: UMA only installed OPS: Optimus solution installed. eDP: Support eDP Panel installed. LVDS: Support LVDS Panel installed.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Hadley 15"

1

1 101Friday, June 28, 201 3

X02

5

4

3

2

1

Project code : 91.47L01.001

Had

y15 Block Diagram

l

PCB P/N

: 12311-1

Revision : A00

eDP

/

eDP L

USB 2.0

VDS Option circuit

52, 53

eDP

S

Converter

Realtek

LVD

RTD2136R

USB PowerShare

PERICOM

PI5USB1457AZAE

PCI-E

USB 2.0

to LVDS

35

5

3

TMDS

USB 2.0

USB 3.0

USB 2.0

USB 3.0

eDP

Intel CPU

Haswell ULT

15W/25W

Lynx Point-LP

8 USB 2.0/1.1 ports

2-4 USB 3.0 ports

High Definition Audio

4 SATA ports

8-12 PCIE ports

LPC I/F

ACPI 4.0a

DDR

L Channel A

3

DDR3L Channel B

PCI-E x4

USB 2.0

SMBUS

INT1

N14P-GT

Touch Screen

2M 720P Camera

D D

15.6" LCD

FHD(1920 x 1080)

52

HDMI CONN

54

USB 3.0 / Power share

34

C C

USB 3.0 CONN

34

Mini-Card

802.11a/b/g/n BT

58

Daughter board

USB 2.0

SATA3

SATA repeater

TI

SN75LVCP601

USB 3.0 CONN

USB 3.0

B B

USB3.0 Redriver

TI

SN65LVPE502RGER

USB 3.0

USB 2.0

PCI-E

LAN+Card reader

(10/100/1000M)

Realtek

RTL8411B

USB 3.0 CONN

USB 3.0

mSATA

SATA3

USB3.0 Redriver

TI

SN65LVPE502RGER

SATA repeater

TI

USB 3.0

SATA3

LPC

LPC debug port

SN75LVCP601

Nuvoton

NPCE985PA0DX

PS2

Touch Pad

62

Flash ROM

3

SPI

8MB

25

Internal Digital MIC

A A

Universal jack

29

2CH SPEAKER

5

52

Audio Codec

Realtek

HDA

ALC3223

27

SMBus

29

4

GPU

25W

KBC

3

L

DDR 1600MHz

DDR3L 1600MHz

73~77

52

30

65

24

Backlight Int. KB

Slot A

Slot B

GDDR5 Ch A

GDDR5 Ch B

SATA3

SMBus

62

2

1

2

13

VRAM(GDDR5)

128M x 16 x4(1GB)

VRAM(GDDR5)

128M x 16 x 4(1GB)

FFS

ST

DE351DL

INT2

67

HDD

RJ45

31

MMI Card Connector (SD/SDHC/SDXC/ SD-UHS/MS/MS-Pro)

Thermal

Nuvoton

NCT7718W

DC Fan Contrroller

ANPEC

APL5606AKI

Title

Size Document Number Rev

Date: Sheet of

56

Custom

INP

DCBATOUT

INPUTS OUTPUTS

DCBATOUT

INPUTS

DCBATOUT

INPUTS

DCBATOUT

5V_S5 3D3V_S5

3D3V_S0 1D05V_S0

1D35V_S3 1D35V_VGA_S0

3D3V_S5

PCB LAYER

33

26

DC Fan

26

Module

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Hadley 15"

R

GER

CHA

BQ24717

AD+ B

OUTPUTSINPUTS

T

+ DCBATOUT

T

EM DC/DC

SYS

TPS

1225

5

TS OUTPUTS

U

5V_AUX_S5 3D3V_AUX_S5 5V_CHARGER 3D3V_PWR

CPU DC/DC TPS51622

VCC_CORE

SYSTEM DC/DC

TPS51363

OUTPUTSINPUTS

1D05V_S0

SYSTEM DC/DC

TPS51216

OUTPUTS

1D35V_S3 0D675V_S0

SYSTEM DC/DC

NCP81172

OUTPUTS

VGA_CORE

Switches

OUTPUTSINPUTS

5V_S0 3D3V_S0

3D3V_VGA_S0 1D05V_VGA_S0

LDO

TLV70215DBVR

OUTPUTSINPUTS

L1 : TOP

L2 : GND

L3 : Signal

L4 : Signal

L5 : VCC

L6 : Signal

L7 : GND

L8 : Bottom

26

2 101Friday, June 28, 2013

1

46~47

36, 83

44

45

48

49

82

51

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

(Reserved)

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

3 101Friday, June 28, 201 3

1

X02

D = CPU

SSI

5

4

3

2

1

D D

1D05S_V CCST

12

R401

62R2J-GP

H_PROCH OT#[24,42,44,4 6]

C C

R407 200R2F-L -GPR407 200R2F-L -GP

1 2

R408 120R2F-G PR40 8 120R2F-G P

1 2

R409 100R2F-L 1-GP-UR409 100R2F-L 1-GP-U

1 2

Layout Note:

Design Guidelin e: SM_RCOMP keep r outing length less than 500 m ils.

Layout Note:

Impedance contr ol:50 ohm

SM_RCOM P_0

SM_RCOM P_1

SM_RCOM P_2

TP401TP401 TP402TP402

H_PECI[24]

1 2

TP403TP403

DDR_PG_ CTRL[12]

R403

R403 56R2J-4-G P

56R2J-4-G P

SKTOCC#

1

H_CATER R#

1

H_PROCH OT#_R

H_CPUPW RGD

1

R405

12

10KR2J-3 -GP

SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2 SM_DRAM RST# DDR_PG_ CTRL

B B

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

CPU1B

PROC_DETECT# CATERR# PECI

PROCHOT#

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# SM_PG_CNTL1

HASW ELL-6-GP

SM_DRAM RST#

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1D35V_S 3

12

R410

R410 470R2J-2 -GP

470R2J-2 -GP

R404

1 2

0R0402-P AD-2-GP

JTAG

2 OF 19

XDP_PRD Y#

J62

PRDY#

PREQ# PROC_TCK PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0

BPM#1

BPM#2

BPM#3

BPM#4

BPM#5

BPM#6

BPM#7

Layout Note:

Place close to DIMM

XDP_PRE Q#

K62

XDP_TCL K

E60

XDP_TMS

E61

XDP_TRS T#

E59

XDP_TDI

F63

XDP_TDO

F62

XDP_BPM 0

J60

XDP_BPM 1

H60

XDP_BPM 2

H61

XDP_BPM 3

H62

XDP_BPM 4

K59

XDP_BPM 5

H63

XDP_BPM 6

K60

XDP_BPM 7

J61

DDR3_DR AMRST# [12,13]

XDP_PRD Y# [96] XDP_PRE Q# [96]

XDP_BPM [7:0]

XDP_BPM [7:0] [96]

XDP_TDO XDP_TDI

XDP_TMS

R402 51R2J-2-G P

XDP_TRS T# XDP_TCL K

R406 51R2J-2-G PR406 51R2J-2-G P

RN401

1 2 3

XDP

4 5

SRN51J-1 -GP

XDP

1 2 1 2

1D05S_V CCST

8 7 6

X01 change to short pad

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK)

Size Document N umber Rev

Date: Sheet of

CPU (THERMAL/CLOCK)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

4 101Friday, June 28, 201 3

X02

5

S

SID = CPU

HSW

_ULT_DDR3L

CPU

CPU1C

M_A

_DQ[63:0][12]

D D

C C

_DQ[63:0]

M_A

_DQ0

M_A

_DQ1 _DQ2

M_A M_A

_DQ3

M_A

_DQ4 _DQ5

M_A M_A

_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQS7 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AH63 AH62

AK63

AK62 AH61 AH60

AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58 AR58 AM57

AK57

AL58

AK58 AR57 AN57

AP55 AR55 AM54

AK54

AL55

AK55 AR54 AN54

AY58 AW58

AY56 AW56

AV58 AU58

AV56 AU56

AY54 AW54

AY52 AW52

AV54 AU54

AV52 AU52

AK40

AK42 AM43 AM45

AK45

AK43 AM40 AM42 AM46

AK46 AM49

AK49 AM48

AK48 AM51

AK51

1C

SA_

DQ0

SA_

DQ1 DQ2

SA_ SA_

DQ3

SA_

DQ4 DQ5

SA_ SA_

DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

_ULT_DDR3L

DDR CHANNEL A

4

3 O

3 OF 19

F 19

SA_

CLK#0

SA_

CLK0

CLK#1

SA_

CLK1

CKE0

SA_ SA_

CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

+V_SM_VREF_CNT

_DIMA_CLK_DDR#0 [12]

M_A M_A

_DIMA_CLK_DDR0 [12]

M_A

_DIMA_CLK_DDR#1 [12] _DIMA_CLK_DDR1 [12]

M_A

_DIMA_CKE0 [12] _DIMA_CKE1 [12]

M_A

M_A_DIMA_CS#0 [12] M_A_DIMA_CS#1 [12]

TP_M_A_DIMA_ODT0

M_A_RAS# [12]

M_A_WE# [12]

M_A_CAS# [12]

M_A_BS0 [12] M_A_BS1 [12] M_A_BS2 [12]

3

TP501TP501

1

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

+V_SM_VREF_CNT [37] DDR_WR_VREF01 [12] DDR_WR_VREF02 [13]

2

HSW

_ULT_DDR3L

CPU

1D

_DQ[63:0]

_DQ[63:0][13]

M_B

_DQ0 _DQ1

M_B M_B

_DQ2

M_B

_DQ3 _DQ4

M_B M_B

_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23 AW23

AY21 AW21

AV23 AU23

AV21 AU21

AY19 AW19

AY17 AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

SB_

DQ0 DQ1

SB_ SB_

DQ2

SB_

DQ3 DQ4

SB_ SB_

DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

_ULT_DDR3L

DDR CHANNEL B

4 O

SB_

CK#0

SB_

CK#1

SB_

CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

F 19

AM38 AN38

CK0

AK38 AL38

CK1

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

TP_M_B_DIMB_ODT0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

1

M_B M_B M_B M_B

M_B M_B_DIMB_CKE1 [13]

M_B_DIMB_CS#0 [13] M_B_DIMB_CS#1 [13]

M_B_RAS# [13]

M_B_WE# [13]

M_B_CAS# [13]

_DIMB_CLK_DDR#0 [13] _DIMB_CLK_DDR0 [13] _DIMB_CLK_DDR#1 [13] _DIMB_CLK_DDR1 [13]

_DIMB_CKE0 [13]

TP503TP503

1

M_B_BS0 [13] M_B_BS1 [13] M_B_BS2 [13]

M_B_A[15:0] [13]

M_B_DQS#[7:0] [13]

M_B_DQS[7:0] [13]

B B

HASWELL-6-GP

A A

5

4

3

HASWELL-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Hadley 15"

1

X02

5 101Friday, June 28, 2013

X02

5

4

3

2

1

SSI

D D

C C

= CPU

D

CFG

HSW_ULT_DDR3L

CPU

S

1

[

19:0]

[

19:0][96]

CFG

1 2

R601

R601 49D9R2F -GP

49D9R2F -GP

1 2

R603

R603 8K2R2F-1 -GP

8K2R2F-1 -GP

0

CFG CFG

1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCO MP

TD_IREF

CFG3

A

C60 AC62 AC63 AA63 AA60

Y62

Y61

Y60

V62

V61

V60

U60

T63

T62

T61

T60

AA62

U63 AA61

U62

V63

H18

B12

A5

E1 D1

J20

0

CFG CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD#A5

RSVD#E1 RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF

12

DY

R604

R604 1KR2J-1-G P

1KR2J-1-G P

HSW_ULT_DDR3L

RESERVED

PHYSICAL_DEBUG_ ENABLED (DFX P RIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

19

D

_TP#AV63

RSV RSVD_TP#AU63

RSVD_TP#C63 RSVD_TP#C62

RSVD#B43

RSVD_TP#A51 RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

PROC_OPI_RCOMP

RSVD#AV62

RSVD#D58

VSS VSS

RSVD#P20 RSVD#R20

F 19

O

AV63 AU63

C63 C62

EDP_SPA RE

B43

A51 B51

L60

N60

W23

PROC_OP I_COMP3

Y22

PROC_OP I_COMP

AY15

AV62 D58

P22 N21

HVM_CLK #

P20

HVM_CLK

R20

1

TP605TP605

R606 49D9R2F -GP

1 2

DY

R602 49D9R2F -GPR602 49D9R2F -GP

1 2

1

TP619TP619

1

TP620TP620

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1 : DISABLED

CFG4

B B

A A

5

4

12

R605

R605 1KR2J-1-G P

1KR2J-1-G P

DISPLAY PORT PR ESENCE STRAP

0 : ENABLED AN EXTERNAL DIS PLAY PORT DEVI CE IS CONNECTED TO THE EMBEDD ED DISPLAY PORT

CFG[4]

1 : DISABLED

NO PHYSICAL DIS PLAY PORT ATTA CHED TO EMBEDDE D DISPLAY PORT

3

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

Hadley 15"

6 101Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

1D05S_V CCST

R703 75R2F-2-G PR703 75R2F-2-G P

1 2

R704 130R2F-1 -GPR704 130R2F-1 -GP

1 2

C C

1D05V_V TT_PWRGD[36,48]

EC701

SCD1U25V2KX-GP

12

DY

B B

VR_SVID_A LERT#

H_CPU_S VIDDAT

SCD1U10 V2KX-5GP

U701

1

NC#1

2

A

DY

GND3Y

74LVC1G 07GW-GP

73.01G07.0HG

1 2

R707

R707 100KR2F -L1-GP

100KR2F -L1-GP

VCC

C702

DY

5

4

12

4

3D3V_S5

1D05S_V CCST

12

R709

R709 51KR2J-1 -GP

51KR2J-1 -GP

12

R706

R706 10KR2J-3 -GP

10KR2J-3 -GP

DY

H_VCCST _PWRGD

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

H_VR_EN ABLE[46]

C705

SCD1U25 V2KX-GP

1D05S_V CCST

VR_SVID_A LERT#[46] H_CPU_S VIDCLK[46] H_CPU_S VIDDAT[46]

1 2

3

100R2F-L 1-GP-U

VCC_SEN SE[46]

IMVP_PW RGD_R

DY

R705 150R2J-L 1-GP-UR 705 150 R2J-L1-GP-U

1 2

VCC_COR E

R702

1 2

12

TP701TP701

R701

43R2J-GP

1 2

H_CPU_S VIDCLK H_CPU_S VIDDAT H_VCCST _PWRGD

DY

1D35V_S 3

VCC_COR E

1

+VCCIOA_OU T

H_CPU_S VIDALRT#

10KR2J-3 -GP

10KR2J-3 -GP R710

R710

PWR_ DEBUG

1D05S_V CCST

VCC_COR E

TP_VCCIO_ OUT

L59

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

J58

2

CPU

1L

RSVD#L59 RSVD#J58

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD#N58 RSVD#AC58

VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59

VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HASW ELL-6-GP

HSW

_ULT_DDR3L

HSW ULT POWER

1

_CORE

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

VCC

12

OF 19

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

A00 0619

H_VR_EN ABLE

PR714

1D05S_V CCST1D05V_S 0

1 2

R711

0R0805-P AD-2-GP-U

A A

5

DY

12

C701

C703

DY

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

4

IMVP_PW RGD[24,46]

1 2

R713

R713 100KR2F -L1-GP

100KR2F -L1-GP

47KR2F-G P

IMVP_PW RGD_L IMVP_PWR GD_R

C704

SCD1U25V2KX-GP

12

R712

DY

3

1 2

0R2J-2-GP

PD701

DY

BAT54LP S-7-GP

KA

12

PR715

DY

10KR2F-2 -GP

12

PC706

DY

SCD047U 10V2KX-2GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Hadley 15"

7 101Friday, June 28, 201 3

1

X02

D = CPU

SSI

5

4

3

2

1

D D

HSW_ULT_DDR3L

X01 remove

CPU1A

HSW_ULT_DDR3L

1 OF 19

HDMI_DATA 2#[54]

HDMI_DATA 2[54]

HDMI

HDMI_DATA 1#[54]

HDMI_DATA 1[54]

HDMI_DATA 0#[54]

HDMI_DATA 0[54]

HDMI_CLK#[54]

HDMI_CLK[54]

C C

C54 C55

B58

C58

B55 A55 A57 B57

C51 C50 C53

B54

C49

B50 A53 B53

HASW ELL-6-GP

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

EDPDDI

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_TX0 _DN [53] EDP_TX0 _DP [53] EDP_TX1 _DN [53] EDP_TX1 _DP [53]

EDP_AUX _DN [5 3] EDP_AUX _DP [53]

EDP_COM P EDP_BRIGHT NESS

R801

24D9R2F -L-GP

1

TP801TP801

+VCCIOA_OU T

Design Guidelin e:

12

EDP_COMP keep r outing length max 100 mils. Trace Width:20 mils.

B B

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Hadley 15"

8 101Friday, June 28, 201 3

X02

5

SSI

D = CPU

D D

C C

B B

4

CPU1P

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61

G18 G22

G3

G5

G6

G8 H13

HASW ELL-6-GP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HSW_ULT_DDR3L

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

3

VSS_SEN SE

2

VSS_SEN SE [46]

12

R901

100R2F-L1-GP-U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)

Size Document N umber Rev

A3

Date: Sheet of

CPU (VSS)

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

9 101Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

1D3

5V_S3

D D

SC10U6D3V3MX-GP

C10

12

01

17

12

C10

SC2D2U6D3V2MX-GP

C C

C1003

C1002

C1018

DY

SC2D2U6D3V2MX-GP

12

C1019

DY

SC2D2U6D3V2MX-GP

C1005

C1004

12

C1020

SC2D2U6D3V2MX-GP

C1006

12

DY

Layout Note:

Direct tie to CPU VccIn/Vss balls

4

SC10U6D3V3MX-GP

Layout Note:

As close to CPU as possible

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP1)

Hadley 15"

10 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

4

3

2

1

MAX: 1.92A

1.838A 41mA 42mA

1D05V_H SIO +V1.05DX _MODPHY_PCH

1 2

R1101

0R0805-P AD-2-GP-U

12

SC1U6D3V2KX-GP

C1101

C1102

12

L1101 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

C1103

12

+V1.05S_ AUSB3PLL

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

C1104

12

+V1.05S_ AUSB3PLL1D05V_H SIO

SC10U6D3V3MX-GP

C1123

12

DY

1D05V_H SIO +V1.05S_ ASATA3PLL

L1102 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

SC1U6D3V2KX-GP

C1105

12

+V1.05S_ ASATA3PLL

SC10U6D3V3MX-GP

C1106

C1107

DY

C1107

12

SC10U6D3V3MX-GP

CAP need close to pin K9 L10

C C

1 2

R1102

0R0603-P AD-2-GP-U

+V1.05S_ APLLOPI

SC1U6D3V2KX-GP

C1109

12

SC10U6D3V3MX-GP

C1110

CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18

CAP need close to pin B18 CAP need close to pin B11

+V1.05S_ APLLOPI1D05V_S 0

SC10U6D3V3MX-GP

C1124

12

DY

3D3V_S5 _PCH +V3.3A_P SUS

1 2

R1103

0R0603-P AD-2-GP-U

1205 Add

SC10U6D3V3MX-GP

C1108

12

1D05V_S 0 +V1.05S_ AXCK_DCB

L1103 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

1205 Add

200mA62mA57mA

+V1.05S_ AXCK_DCB

SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

C1112

C1111

12

DY

SC10U6D3V3MX-GP

C1125

12

1205 Add

31mA 658mA 1.632A 1mA

IND-2D2UH-1 96-GP

IND-2D2UH-1 96-GP L1104

L1104

1 2

68.2R21D.10R

B B

+V1.05S_ AXCK_LCPLL1D05V_S 0

SC1U6D3V2KX-GP

C1113

C1114

12

DY

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11

1D05V_S 0 +1.05M_A SW 1D05V_S0

1 2

R1104

0R0603-P AD-2-GP-U

SC10U6D3V3MX-GP

0R0603-P AD-2-GP-U

SC22U6D3V5MX-2GP

C1115

12

DY

RTC_AUX _S5

SC1U6D3V2KX-GP

C1116

12

SC1U6D3V2KX-GP

C1117

C1118

12

SC10U6D3V3MX-GP

C1119

12

DY

SCD1U10V2KX-5GP

C1120

12

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C1122

C1121

12

CAP need close to pin AG10

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP2)

Hadley 15"

11 10 1Friday, June 28, 201 3

1

X02

5

S

SID = MEMORY

M_A

_A[15:0][5]

D D

M_A_BS2[5]

M_A_BS0[5] M_A_BS1[5]

M_A_DQ[63:0][5]

12

DY

C1202

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

12

DY

C1206

SCD1U10V2KX-5GP

16

C12

SC1U6D3V2KX-GP

M_A_DQS#[7:0][5]

M_A_DQS[7:0][5]

DDR3_DRAMRST#[4,13]

Layout Note:

Place these caps close to VREF_CA

Layout Note:

Place these caps close to VTT1 and VTT2.

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

C1217

SCD1U10V2KX-5GP

DY

M_VREF_CA_DIMMA

12

DY

01

18

C12

SCD1U10V2KX-5GP

C C

M_VREF_DQ_DIMMA

12

04

C12

0D675V_S0

14

12

C12

B B

A A

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

SCD1U10V2KX-5GP

05

12

C12

DY

SC2D2U6D3V2MX-GP

SCD1U10V2KX-5GP

15

12

C12

DY

SC1U6D3V2KX-GP

M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A_A13 M_A_A14 M_A_A15

M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ25 M_A_DQ24 M_A_DQ27 M_A_DQ26 M_A_DQ44 M_A_DQ41 M_A_DQ43 M_A_DQ47 M_A_DQ45 M_A_DQ40 M_A_DQ42 M_A_DQ46 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ22 M_A_DQ23 M_A_DQ36 M_A_DQ33 M_A_DQ34 M_A_DQ38 M_A_DQ37 M_A_DQ32 M_A_DQ35 M_A_DQ39 M_A_DQ62 M_A_DQ58 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ59 M_A_DQ56 M_A_DQ57

M_A_DQS#1 M_A_DQS#3 M_A_DQS#5 M_A_DQS#6 M_A_DQS#0 M_A_DQS#2 M_A_DQS#4 M_A_DQS#7

M_A_DQS1 M_A_DQS3 M_A_DQS5 M_A_DQS6 M_A_DQS0 M_A_DQS2 M_A_DQS4 M_A_DQS7

M_A_DIMA_ODT0 M_A_DIMA_ODT1

0D675V_S0

12

_A0 _A1 _A2 _A3 _A4 _A5 _A6 _A7 _A8 _A9 _A10 _A11 _A12

close to dimm

5

4

DM1

8

9

A

0

9

7

1

A

6

9

A

2

5

9

A

3

9

2

4

A

9

1

5

A

0

9

A

6

8

A

7

8

9

8

A

5

8

A

9

107

A10

/AP

4

8

A11

8

3

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

D

DR3-204P-122-GP-U1

62.10017.Z51

4

RAS

WE#

CAS

CS0 CS1

CKE CKE

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

N

P1

NP1

P2

N

NP2

110

#

13

1 115

#

114

#

121

#

73

0

74

1

101

CK0

103

102

CK1

104

11 28 46 63 136 153 170 187

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SA1_DIMA

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D35V_S3

M_A

_RAS# [5] _WE# [5]

M_A M_A

_CAS# [5]

M_A

_DIMA_CS#0 [5]

M_A

_DIMA_CS#1 [5]

M_A

_DIMA_CKE0 [5]

M_A

_DIMA_CKE1 [5]

M_A_DIMA_CLK_DDR0 [5] M_A_DIMA_CLK_DDR#0 [5]

M_A_DIMA_CLK_DDR1 [5] M_A_DIMA_CLK_DDR#1 [5]

PCH_SMBDATA [13,18,58,62,67] PCH_SMBCLK [13,18,58,62,67]

C1203

SCD1U10V2KX-5GP

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

X01 change to short pad

DDR_PG_CTRL[4]

1 2

Q1201 Need check Vth=1V

3

3D3V_S0

12

DY

12

0R0402-PAD-2-GP

R1205

0R0402-PAD-2-GP

C1207

12

DY

12

C1211

C1210

SCD1U10V2KX-5GP

DDR_PG_CTRL_R

SA0

_DIMA

SA1

_DIMA

12

02

R12

C1208

SC10U6D3V3MX-GP

12

C1212

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1D35V_S3

Q1201

Q1201 DMN5L06K-7-GP

DMN5L06K-7-GP

84.05067.031

C1209

SC10U6D3V3MX-GP

C1213

SC1U6D3V2KX-GP

G

01

R12

R12 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

C1220

SCD1U10V2KX-5GP

DS

12

C1221

5V_S5

DY

12

C1222

SCD1U10V2KX-5GP

12

R1208

R1208 220KR2J-L2-GP

220KR2J-L2-GP

DDR_VTT_PG_CTRL

12

R1204

R1204 2MR2-GP

2MR2-GP

2

e:

Not SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF01[5]

SCD1U10V2KX-5GP

1D35V_S3

D

Q1202

Q1202 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

2

M_A_B_DIMM_ODT

1

1D35V_S30D675V_VTTREF

12

R1215

0R2J-2-GP

DY

2R2F-GP

2R2F-GP R1210

R1210

1 2

12

C1219

C1219 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH1

12

R1212

R1212 24D9R2F-L-GP

24D9R2F-L-GP

DDR_VTT_PG_CTRL [49]

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

R1211

R1211 1K8R2F-GP

1K8R2F-GP

12

R1213

R1213 1K8R2F-GP

1K8R2F-GP

R1206 66D5R2F-GPR1206 66D5R2F-GP

1 2

R1207 66D5R2F-GPR1207 66D5R2F-GP

1 2

R1203 66D5R2F-GPR1203 66D5R2F-GP

1 2

R1209 66D5R2F-GPR1209 66D5R2F-GP

1 2

DDR3L-SODIMM1

Hadley 15"

Friday, June 28, 2013

Hadley 15"

M_A_DIMA_ODT0

M_A_DIMA_ODT1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

M_VREF_DQ_DIMMA

M_B_DIMB_ODT0 [13]

M_B_DIMB_ODT1 [13]

12 101

X02

5

S

SID = MEMORY

M_B

_A[15:0] [5]

D D

M_B_BS2[5]

M_B_BS0[5] M_B_BS1[5]

12

DY

12

DY

12

C1318

M_B_DQ[63:0][5]

Layout Note:

Place these caps close to VREF_CA

C1302

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

C1306

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VTT1 and VTT2.

SC1U6D3V2KX-GP

M_B_DQS#[7:0] [5]

M_B_DQS[7:0] [5]

M_B_DIMB_ODT0[12] M_B_DIMB_ODT1[12]

M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

DDR3_DRAMRST#[4,12]

C1319

SCD1U10V2KX-5GP

12

DY

M_VREF_CA_DIMMB

12

01

DY

C C

M_VREF_DQ_DIMMB

12

0D675V_S0

B B

A A

12

DY

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

302

C13

EC1

SCD1U10V2KX-5GP

05

12

C13

04

DY

C13

SC2D2U6D3V2MX-GP

SCD1U10V2KX-5GP

17

16

12

C13

SC1U6D3V2KX-GP

close to dimm

5

_A0

M_B

_A1

M_B M_B

_A2

M_B

_A3 _A4

M_B M_B

_A5

M_B

_A6 _A7

M_B M_B

_A8

M_B

_A9 _A10

M_B M_B

_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ8 M_B_DQ14 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ9 M_B_DQ13 M_B_DQ15 M_B_DQ28 M_B_DQ29 M_B_DQ26 M_B_DQ27 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ40 M_B_DQ41 M_B_DQ46 M_B_DQ42 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ43 M_B_DQ56 M_B_DQ57 M_B_DQ59 M_B_DQ58 M_B_DQ61 M_B_DQ60 M_B_DQ63 M_B_DQ62 M_B_DQ4 M_B_DQ1 M_B_DQ3 M_B_DQ7 M_B_DQ5 M_B_DQ0 M_B_DQ2 M_B_DQ6 M_B_DQ21 M_B_DQ20 M_B_DQ22 M_B_DQ23 M_B_DQ16 M_B_DQ17 M_B_DQ19 M_B_DQ18 M_B_DQ36 M_B_DQ33 M_B_DQ35 M_B_DQ39 M_B_DQ37 M_B_DQ32 M_B_DQ34 M_B_DQ38 M_B_DQ52 M_B_DQ49 M_B_DQ48 M_B_DQ53 M_B_DQ51 M_B_DQ55 M_B_DQ54 M_B_DQ50

M_B_DQS#1 M_B_DQS#3 M_B_DQS#5 M_B_DQS#7 M_B_DQS#0 M_B_DQS#2 M_B_DQS#4 M_B_DQS#6

M_B_DQS1 M_B_DQS3 M_B_DQS5 M_B_DQS7 M_B_DQS0 M_B_DQS2 M_B_DQS4 M_B_DQS6

0D675V_S0

4

DM2

9

8

0

A

7

9

A

1

6

9

A

2

9

5

3

A

9

2

4

A

1

9

A

5

0

9

A

6

8

6

7

A

9

8

A

8

5

8

A

9

107

/AP

A10

8

4

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

D

DR3-204P-122-GP-U1

62.10017.Z51

4

RAS

WE#

CAS

CS0 CS1

CKE CKE

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

P1

N

NP1

N

P2

NP2

110

#

13

1 115

#

114

#

121

#

73

0

74

1

101

CK0

103

102

CK1

104

11 28 46 63 136 153 170 187

200

SDA

202

SCL

198

199

197

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SA1_DIMB

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D35V_S3

3

_RAS# [5]

M_B M_B

_WE# [5]

M_B

_CAS# [5]

M_B

_DIMB_CS#0 [5]

M_B

_DIMB_CS#1 [5]

M_B

_DIMB_CKE0 [5] _DIMB_CKE1 [5]

M_B

M_B_DIMB_CLK_DDR0 [ 5] M_B_DIMB_CLK_DDR#0 [5]

M_B_DIMB_CLK_DDR1 [ 5] M_B_DIMB_CLK_DDR#1 [5]

PCH_SMBDATA [12,18,58,62,67] PCH_SMBCLK [12,18,58,62,67]

DY

C1303

SCD1U10V2KX-5GP

1D35V_S3

12

DY

12

Layout Note:

Place these Caps near SO-DIMMA.

3

3D3V_S0

12

C1312

C1311

SC10U6D3V3MX-GP

12

DY

12

C1314

C1313

SCD1U10V2KX-5GP

2

Not

e: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

3D3V_S0

12

R1301

R1301 10KR2J-3-GP

10KR2J-3-GP

SA1_DIMB

SA0_DIMBSA0_DIMB

12

R1302

R1302 0R0402-PAD-2-GP

0R0402-PAD-2-GP

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF02[5]

C1307

C1308

C1310

SC10U6D3V3MX-GP

12

DY

12

C1315

DY

SCD1U10V2KX-5GP

C1308

C1309

SC10U6D3V3MX-GP

12

EC1301

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

12

2

0D675V_VTTREF

R1308

0R2J-2-GP

2R2F-GP

2R2F-GP R1304

R1304

1 2

12

C1320

C1320 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH2

12

R1307

R1307 24D9R2F-L-GP

24D9R2F-L-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

1D35V_S3

12

DY

Friday, June 28, 2013

1

12

R1306

R1306 1K8R2F-GP

1K8R2F-GP

12

DDR3L-SODIMM2

Hadley 15"

M_VREF_DQ_DIMMB

R1303

R1303 1K8R2F-GP

1K8R2F-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

13 101

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

M1&M3

Hadley 15"

14 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

C C

RN1504

4

OPS

SRN10KJ -5-GP

100KR2J -1-GP

100KR2J -1-GP R1509

R1509

DGPU_PW R_EN DGPU_HO LD_RST#

DGPU_PW ROK

1 2 3

1 2

4

0R0402-P AD-2-GP

L_BKLT_ CTRL_R

R1501

L_BKLT_ CTRL[53 ] L_BKLT_ EN[24]

EDP_VDD _EN[52]

A00 change to PIRQB#

HDD_FAL L_INT[67]

DGPU_PW R_EN[82,83] DGPU_HO LD_RST#[73]

DGPU_PW ROK[24,82,83]

1 2

0R0402-P AD-2-GP

0R0402-P AD-2-GP R1503

R1503

1 2

TP1501TP1501

TP1503TP1503

TP1502TP1502

1

MCP_GPIO55

1

DGPU_PW R_EN DGPU_HO LD_RST# DGPU_PW ROK

PCH_SD_ CD#

1

PIRQA# PIRQB# PIRQC# PIRQD# PCI_PME#

3

AD4

CPU1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA#/GPIO77

P4

PIRQB#/GPIO78

N4

PIRQC#/GPIO79

N2

PIRQD#/GPIO80 PME#

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

2

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

3D3V_S0

1

23

4

RN1501

RN1501 SRN2K2J -1-GP

SRN2K2J -1-GP

PCH_HDM I_CLK [54] PCH_HDM I_DATA [54]

HDMI_PCH_D ET [54]

EDP_HPD [52,53 ]

1

3D3V_S0

B B

A A

5

RN1505

8 7 6

SRN10KJ -6-GP

PIRQD#

1

PIRQC#

2

PIRQB#

3

PIRQA#

45

4

3

HASW ELL-6-GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU ( EDP SIDEBAND/GPIO/DDI )

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

X02

15 10 1Friday, June 28, 201 3

1

X02

SSI

D = CPU

5

4

3

2

1

D D

PCIE Table

Port

1

2

3

4

5(4lane)

6(4lane)

C C

B B

Device

N/A

WLAN

LAN+ Card reader

GPU

N/A

Share BUS

USB3.0_3

USB3.0_4

SATA0~3

CPU_RXN _C_dGPU_TXN0[73] CPU_RXP _C_dGPU_TXP0[73]

dGPU_RX N_C_CPU_TXN0[73] dGPU_RX P_C_CPU_TXP0[73]

CPU_RXN _C_dGPU_TXN1[73] CPU_RXP _C_dGPU_TXP1[73]

dGPU_RX N_C_CPU_TXN1[73] dGPU_RX P_C_CPU_TXP1[73]

CPU_RXN _C_dGPU_TXN2[73] CPU_RXP _C_dGPU_TXP2[73]

dGPU_RX N_C_CPU_TXN2[73] dGPU_RX P_C_CPU_TXP2[73]

CPU_RXN _C_dGPU_TXN3[73] CPU_RXP _C_dGPU_TXP3[73]

dGPU_RX N_C_CPU_TXN3[73] dGPU_RX P_C_CPU_TXP3[73]

PCIE_PRX_ WLANTX_N3[58] PCIE_PRX_ WLANTX_P3[58 ]

PCIE_PTX_ WLANRX_N3 _C[58] PCIE_PTX_ WLANRX_P3 _C[58]

PCIE_PRX_ LANTX_N4[30] PCIE_PRX_ LANTX_P4[30]

PCIE_PTX_ LANRX_N4_C[30] PCIE_PTX_ LANRX_P4_C[30]

USB3_PR X_DTX_N2[63] USB3_PR X_DTX_P2[63]

USB3_PT X_DRX_N2[63] USB3_PT X_DRX_P2[63]

USB3_PR X_DTX_N3[63] USB3_PR X_DTX_P3[63]

USB3_PT X_DRX_N3[63] USB3_PT X_DRX_P3[63]

+V1.05S_ AUSB3PLL

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1606

C1606

1 2

OPS

1 2

OPS

C1605

C1605 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1608

C1608

1 2

OPS

1 2

OPS

C1607

C1607 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1610

C1610

1 2

OPS

1 2

OPS

C1609

C1609 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1612

C1612

1 2

OPS

1 2

OPS

C1611

C1611 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1601

C1601

1 2 1 2

C1602

C1602 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1603

C1603

1 2 1 2

C1604

C1604 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

R1601

3KR2F-GP

1 2

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trac e width=12~15mi l

2. Isolation Sp acing: 12mil

3. Total trace length<500mil

dGPU_RX N_CPU_TXN0

dGPU_RX P_CPU_TXP0

dGPU_RX N_CPU_TXN1

dGPU_RX P_CPU_TXP1

dGPU_RX N_CPU_TXN2

dGPU_RX P_CPU_TXP2

dGPU_RX N_CPU_TXN3

dGPU_RX P_CPU_TXP3

PCIE_PTX_ WLANRX_N3 PCIE_PTX_ WLANRX_P3

PCIE_PTX_ LANRX_N4 PCIE_PTX_ LANRX_P4

PCIE_RCOM P

CPU

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD#E15

E13

RSVD#E13

A27

PCIE_RCOMP

B27

PCIE_IREF

1K

WLAN

LAN+Card reader

HASW ELL-6-GP

HSW

_ULT_DDR3L

PCIE USB

11

OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS#

USBRBIAS RSVD#AN10 RSVD#AM10

OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_PN7 USB_PP7

USB_COM P

USB_OC# 0_1 USB_OC# 2_3 USB_OC# 4_5 USB_OC# 6_7

1 1

USB_PN0 [34] USB_PP0 [34 ]

USB_PN1 [35] USB_PP1 [35 ]

USB_PN2 [63] USB_PP2 [63 ]

USB_PN3 [63] USB_PP3 [63 ]

USB_PN4 [52] USB_PP4 [52 ]

USB_PN5 [58] USB_PP5 [58 ]

USB_PN6 [52] USB_PP6 [52 ]

TP1602TP1602 TP1601TP1601

1 2

R1602

R1602 22D6R2F -L1-GP

22D6R2F -L1-GP

USB_OC# 0_1 [3 5] USB_OC# 2_3 [3 5]

USB 2.0 Table

Pai

0

1

2

3

4

5

6

7

USB3_PR X_CTX_N0 [34] USB3_PR X_CTX_P0 [34]

USB3_PT X_CRX_N0 [34] USB3_PT X_CRX_P0 [34]

USB3_PR X_CTX_N1 [34] USB3_PR X_CTX_P1 [34]

USB3_PT X_CRX_N1 [34] USB3_PT X_CRX_P1 [34]

1. USB_COMP usi ng 50 ohm

2. Isolation Sp acing :15mil

3. Total trace length<500mil

USB_OC# 0_1 USB_OC# 2_3 USB_OC# 4_5 USB_OC# 6_7

Dev

r

ice

USB3.0 Port2

USB3.0 port1 (with Power Share)

USB3.0 Port3

USB3.0 Port4

CAMERA

WL

N

A

Touch Panel

N/A

Layout Note:

single-ended i mpedance

3D3V_S5 _PCH

RN1601

1

8

2

7

3

6

4 5

SRN10KJ -6-GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/USB)

Hadley 15"

16 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

RN1

703

1

4

2 3

SRN10KJ -5-GP

1 2

DY

R1717 10KR2J -3-GP

3D3V_S0

RN1704

1 2 3

SRN8K2J -3-GP

C C

B B

XDP_DBR ESET#

4

PM_CLKR UN#

SYS_PW ROK[24,96] PCH_PW ROK[24,26,36]

PM_PW RBTN#[24,96] AC_PRES ENT[24,76 ]

PCH_SLP _S0#[48] PM_SLP_ SUS# [24,38]

3D3V_S5

3D3V_S5 _PCH

PM_

RSMRST#

PM_PCH_ PWROK

SYS_PW ROK

R1706 0R0402-PAD -2-GPR1706 0R0402-PAD -2-GP

1 2

PLT_RST #[24,30,58,6 5,73]

100KR2J -1-GP

RN1701

1

4

2 3

SRN10KJ -5-GP

1 2

DY

R1724 10KR2J-3 -GP

1 2

R1727 10KR2J-3 -GPR1727 10KR2J-3-GP

0R0402-P AD-2-GP

TP1705TP1705

R1715

DY

BATLOW # AC_PRES ENT

PM_SUS_ STAT#

PM_SUSW ARN#

R1707

1 2

12

DY

4

PM_SUSA CK#_R

XDP_DBR ESET# SYS_PW ROK PM_PCH_ PWROK MPWR OK PCI_PLTRS T#

PM_RSMR ST#

PM_SUSW ARN#_R

PM_PW RBTN# AC_PRES ENT BATLOW # PCH_SLP _S0#

R1713

PCH_SLP _WLAN#

PCI_PLTRS T#

PM_SUSA CK#[2 4]

PM_SUSW ARN#[24 ]

1

0R0402-P AD-2-GP

1 2

C1701

C1701 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

CPU1H

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPIO72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPIO29

HASW ELL-6-GP

RN

A00 0618

1

4

2 3

0R4P2R-P AD

RN1702

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

PM_SUSA CK#_R PM_SUSW ARN#_R

3D3V_AU X_S5

R1726

R1726 10KR2J-3 -GP

10KR2J-3 -GP

1 2

3

8 OF 19

DPWROK

WAKE#

SLP_S4# SLP_S3#

SLP_A#

SLP_SUS#

SLP_LAN#

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

PCH_DPW ROK

PM_RSMR ST#

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

NON DS3

1 2

R1708

R1708 100KR2J -1-GP

100KR2J -1-GP

Q1701

5

6

2N7002K DW-GP

34

2

1

3V_5V_P OK# 3V_5V_P OK_C

2

Die DSW VR Enable

On

= Disable

DSW

ODVREN

DSWO DVREN PCH_DPW ROK PM_RS MRST#

PCH_W AKE#

PM_CLKR UN# PM_SUS_ STAT# SUS_CLK PM_SLP_ S5#

PM_SLP_ S4# PM_SLP_ S3# PM_SLP_ A# PM_SLP_ SUS# PM_SLP_ LAN#

R1703 1KR2J-1-GPR1 703 1KR2J-1-G P

1

Low High = Enable (default)

*

NON DS3

0R2J-2-GP

0R2J-2-GP R1704

R1704

1 2 1 2

0R0402-P AD-2-GP

R1709

1 2

TP1702TP1702 R1710

R1710

1 2

TP1703TP1703

0R0402-P AD-2-GP

TP1704TP1704

TP1707TP1707

A00 0618

PM_SLP_ S4# [24,49]

PM_SLP_ S3# [24,36,48,49,5 1]

A00 0618

R1718

1 2

0R0402-P AD-2-GP

R1725

100KR2F -L1-GP

1KR2J-1-G P

1KR2J-1-G P R1702

R1702

1 2

R1728

1 2

0R2J-2-GP

NON DS3

1 2

R1729

0R0402-P AD-2-GP

12

DS3

RSMRST# _KBC [2 4]

3V_5V_P OK [45]

PM_SLP_ SUS#

3D3V_S5

0311 PCH WAKE# pin PH 1K

PM_CLKR UN#_EC [24]

PCH_SUS CLK_KBC [24 ]

KBC_DPW ROK [2 4]

PCH_SUS CLK_KBC

DSW

ODVREN

1

20

R17

330KR2J -L1-GP

1 2

DY

R17

21

330KR2J -L1-GP

EC1701

SC4D7P5 0V2CN-1GP

EC1701

RTC

DY

_AUX_S5

1 2

A00 0618

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PM)

Hadley 15"

X02

17 10 1Friday, June 28, 201 3

1

X02

5

S

ID = CPU

S

3

3V_S0

D

D D

C C

SRN10KJ -6-GP

CLK_PCIE_ WLAN_N3[5 8] CLK_PCIE_ WLAN_P3[58]

CLK_PCIE_ WLAN_REQ3 #[58]

CLK_PCIE_ LAN_N4[30] CLK_PCIE_ LAN_P4[30 ]

CLK_PCIE_ LAN_REQ4#[30]

R

1801

N

1 2 3 4 5

CLK_PCIE_ VGA#[73] CLK_PCIE_ VGA[73 ]

PEG_CLK REQ#[73]

C

K_PCIE_RE Q#

L

8

C

K_PCIE_W LAN_REQ3#

L

7

P

G_CLKRE Q#

E

6

C

K_PCIE_LA N_REQ4#

L

X01 0321

RN1806

LPC_AD[3 ..0][24,65]

B B

LPC_AD[3 ..0]

LPC_FRA ME#[24,65]

SPI_CLK_R[24,25] SPI_CS0#_ R[24,25]

SPI_SI_R[24,25]

SPI_SO_R[24,25]

SPI_WP #[25] SPI_HOLD#[25]

RN1802

SRN1KJ-1 1-GP-U

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

3D3V_S5

1

23

4

RN1806 0R8P4R-P AD-1-GP

0R8P4R-P AD-1-GP

8 7 6

X01 0321

PCH_SPI_D Q3 PCH_SPI_D Q2

RN

1 2 1 2 1 2 1 2

1 2 3 45

R18010R 0402-PAD-2-GP R18010R 0402-PAD-2-GP

1 2

R18070R 0402-PAD-2-GP R18070R 0402-PAD-2-GP

1 2

R18080R 0402-PAD-2-GP R18080R 0402-PAD-2-GP R18090R 0402-PAD-2-GP R18090R 0402-PAD-2-GP R18110R 0402-PAD-2-GP R18110R 0402-PAD-2-GP R18120R 0402-PAD-2-GP R18120R 0402-PAD-2-GP

4

CLK_PCIE_ REQ#

LPC_LAD 0_PCH LPC_LAD 1_PCH LPC_LAD 2_PCH LPC_LAD 3_PCH LPC_LFR AME#_PCH

PCH_SPI_C LK

R180633R2 J-2-GP R1 80633R2J-2-GP

PCH_SPI_C S0#

PCH_SPI_S I PCH_SPI_S O PCH_SPI_D Q2 PCH_SPI_D Q3

P

C

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASW ELL-6-GP

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASW ELL-6-GP

U1F

HSW_ULT_DDR3L

CLOCK

WLAN

SIGNALS

LAN/ Card reader

GPU

HSW_ULT_DDR3L

LPC

SMBUS

SML1ALERT#/PCHHOT#/GPIO73

C-LINKSPI

3

XTAL24_IN

XTAL24_OUT

RSVD#K21 RSVD#M21

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK CL_DATA CL_RST#

OF 19

6

7 OF 19

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

XTAL24_ IN XTAL24_ OUT

XCLK_BIAS REF

MCP_TES TLOW1 MCP_TES TLOW2 MCP_TES TLOW3 MCP_TES TLOW4

CLK_PCI_L PC_R CLK_PCI_K BC_R

MCP_GPIO11 SMB_CLK SMB_DAT A CARD_PW R_EN SML0_CL K SML0_DA TA MCP_GPIO73 SML1_CL K SML1_DA TA

TP_CL_C LK

1

TP_CL_D ATA

1

TP_CL_R ST#

1

2

A00 0618

0R0402-P AD-2-GP

www.qdzbwx.com

+V1.05S_ AXCK_LCPLL

3KR2F-GP

R1803

1 2

RN1803

RN1803 SRN10KJ -5-GP

SRN10KJ -5-GP

2 3 1

4

RN1808

RN1808 SRN10KJ -5-GP

SRN10KJ -5-GP

1

4

2 3

R1804 0R2J-2-GP

1 2

LPC

R1805

1 2

0R0402-P AD-2-GP

A00 0618

12

DY

SML0_CL K [53] SML0_DA TA [53]

SML1_CL K [24,26,76] SML1_DA TA [24,26,76]

TP1803TP1803 TP1804TP1804 TP1805TP1805

SMB_DAT A

SMB_CLK

SC10P50V2JN-4GP

EC1801

3D3V_S0

6

5

DY

T

AL24_IN

X

AL24_OU T

T

SC10P50V2JN-4GP

EC1802

12

Q1801

1

2

34

2N7002K DW-GP

0R0402-P AD-2-GP

R

1 2

12

R

802

1

1M1R2J-G P

CLK_PCI_L PC [65]

CLK_PCI_K BC [24 ]

PCIE_CLK_ XDP_N [9 6] PCIE_CLK_ XDP_P [96]

SML0_DA TA SML0_CL K SML1_CL K SML1_DA TA

MCP_GPIO73 MCP_GPIO11 CARD_PW R_EN

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

1

810

SMB_DAT A SMB_CLK

T

AL24_IN_R

X

23

4 1

2 3 1

82.30004.891

RN1807

4 5 3 2 1

SRN2K2J -4-GP

SRN2K2J -4-GP RN1809

RN1809 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2 3 4 5

RN1804

2 3 1

SRN2K2J -1-GP

RN1805

4

SRN2K2J -1-GP

PCH_SMB DATA [12 ,13,58,62,67]

PCH_SMB CLK [12,13,58,6 2,67]

1

801

C

1 2

SC15P50 V2JN-2-GP

XTAL-24M HZ-86-GP

XTAL-24M HZ-86-GP X

X

801

1

802

C

1 2

SC15P50 V2JN-2-GP

6 7 8

8 7 6

4

3D3V_S0

3D3V_S5 _PCH

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CLK/SMB/LPC/SPI)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

18 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

Q1901

RTCRST_ ON[24]

R1902

10KR2J-3 -GP

C C

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled a fter PLTRST# deasserts

B B

Low = Default High = Enable

R1913

1 2

DY

330KR2J -L1-GP

*

PCH_INTVR MEN

Integrated SUS 1V VRM Enable

INTVRMEN

Low = External VRs High = Internal VRs

*

G

12

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

HDA_COD EC_BITCLK[27]

HDA_COD EC_SYNC[27] HDA_COD EC_RST#[27,29 ] HDA_COD EC_SDOUT[27]

ME_UNLO CK[24]

D

R1907 33R2J-2-GPR1907 33R2J-2-GP

R1905 0R0402-PAD -2-GPR1905 0R0402-PAD -2-GP R1908 0R0402-PAD -2-GPR1908 0R0402-PAD -2-GP R1910 0R0402-PAD -2-GPR1910 0R0402-PAD -2-GP

R1909 1KR2J-1-GPR1 909 1KR2J-1-G P

1D05S_V CCST

R1916 51R2J-2-G P

R1917 51R2J-2-G P

R1918 51R2J-2-G P

R1919 1KR2J-1-G P

C1901

SC1U6D3V2KX-GP

1 2

1 2 1 2 1 2

1 2

4

RN1901

SRN20KJ -1-GP

21

12

G1901

GAP-OPEN

DY

12

DY

12

DY

12

DY

RTC_AUX _S5

1

23

4

12

C1902

C1902 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

330KR2J -L1-GP

HDA_SDIN0[27]

HDA_BITCL K

HDA_SYNC HDA_RST # HDA_SDO UT

R1903

TP1902TP1902

TP1901TP1901

RTC

_AUX_S5

12

R1901

R1901 1M1R2J-G P

1M1R2J-G P

RTC_X1 RTC_X2

SM_INTRUD ER#

PCH_INTVR MEN SRTC_RS T# RTC_RST #

HDA_BITCL K HDA_SYNC HDA_RST # HDA_SDIN0

HDA_SDO UT TP_HDA_ DOCK_EN#

1

PCH_JTA G_TRST#

1

PCH_JTA G_TCK PCH_JTA G_TDI PCH_JTA G_TDO PCH_JTA G_TMS

XDP_TCK _JTAGX

3

CPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER#

AV7

INTVRMEN

AV6

SRTCRST#

AU7

RTCRST#

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST#/I2S_MCLK#

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN#/I2S1_TXD#

AV10

HDA_DOCK_RST#/I2S1_SFRM#

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD#AL11

AC4

RSVD#AC4

AE63

JTAGX

AV2

RSVD#AV2

HASW ELL-6-GP

12

C19

SC15P50V2JN-2-GP

1 2

R19

15 10MR2J-L -GP

X19

01

41

2 3

03

X-32D768 KHZ-65-GP

82.30001.A41

2nd = 82.30001.841

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

2

_X1

RTC

_X2

RTC

02 0502 change C1903 C1904 from 18pF to 15 pF

X

12

C19

04

SC15P50V2JN-2-GP

5 OF 19

RSVD#L11 RSVD#K10

SATALED#

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

SATA_RCOMP

EC_SMI#

MCP_GPIO35

SATA_OD D_PRSNT#

SATA_IREF

SATA_RC OMP SATA_LE D#

EC_SMI#

MCP_GPIO35

MSATA_D ET#

SATA_OD D_PRSNT#

1

SATA3_P RX_DTX_N0 [56] SATA3_P RX_DTX_P0 [56] SATA3_P TX_DRX_N0 [56] SATA3_P TX_DRX_P0 [56]

SATA3_P RX_DTX_N1 [63] SATA3_P RX_DTX_P1 [63] SATA3_P TX_DRX_N1 [63] SATA3_P TX_DRX_P1 [63]

EC_SMI# [24]

MSATA_D ET# [63]

SATA_LE D# [61]

Layout Note:

4mil trace at b reak-out and 3 12-15mil trace with <0.2 ohms and length tota l <= 500mils.

RN1902

1 2 3 4 5

SRN10KJ -6-GP

HDD1

mSATA

+V1.05S_ ASATA3PLL

0R0402-P AD-2-GP

R1904

1 2

R1906

R1906 3KR2F-GP

3KR2F-GP

3D3V_S0

8 7 6

1 2

DY

R1920 51R2J-2-G P

A A

5

4

PCH_JTA G_TCK

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RTC/SATA/HDA/JTAG)

Size Document N umber Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

X02

19 10 1Friday, June 28, 201 3

1

X02

SSI

= CPU

D

5

4

HSW

CPU

J

1

HSW

ULT_DDR3L

_

3

10

F 19

O

2

1D05S_VCCST

12

R20

R20 1KR2J-1-G P

1KR2J-1-G P

8

1

FFS

INT2

04

3D3V_S0

OPS

UMA

_

MCP

GPIO8

_

MCP

GPIO12

_

MCP

GPIO15

_

MCP

GPIO16

_

1

A

_ODD_DA #

SAT RTC

DET#

_

GPIO27

MCP MCP

GPIO28

_

MCP_GPIO2 6

MCP_GPIO5 6 MCP_GPIO5 7 MCP_GPIO5 8 WLAN _PLT_RST#

DRAM_SE L0 DRAM_SE L3

BOARD_ID1 BOARD_ID2 MCP_GPIO5 0

1

MCP_GPIO1 3 MCP_GPIO1 4 CAMERA_ PWR_EN

1

DRAM_SE L1 DRAM_SE L2

EC_SW I# EC_SCI#

MCP_GPIO7 0

1

MCP_GPIO3 9

1

12

R2005

R2005 10KR2J-3 -GP

10KR2J-3 -GP

12

R2008

R2008 10KR2J-3 -GP

10KR2J-3 -GP

4

FFS

INT2[6 7]

RTC

_

0

TP2

_

DET#[2 5]

3D3

_S5

V

RN2

06

0

MCP

GPIO12

D D

1 2 3

SRN10KJ -5-GP

_

4

_

GPIO27

MCP

GPIO[47:44]=[1,1,1,1] for SODIMM configuration

RN2005

RN2005 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2

DY

1 2

DY

TP2002TP2002

TP2020TP2020

TP2009TP2009

TP2003TP2003

FFS_INT2

8

BOARD_ID1 I2C0_SCL

7

SATA_OD D_DA#

6

BLUETOO TH_EN

HDD_DEV SLP

MSATA_D EVSLP

HSIOPC[21]

3D3V_S5 _PCH

12

R2013

R2013 10KR2J-3 -GP

10KR2J-3 -GP

MCP_GPIO_ PH

C C

3D3V_S5 _PCH

3D3V_S0

B B

A00 0618

R20010R0402 -PAD-2-GP R20010R0402 -PAD-2-GP

1 2

R20020R0402 -PAD-2-GP R20020R0402 -PAD-2-GP

1 2

R20040R0402 -PAD-2-GP R20040R0402 -PAD-2-GP

1 2

R20070R0402 -PAD-2-GP R20070R0402 -PAD-2-GP

1 2

R20150R0402 -PAD-2-GP R20150R0402 -PAD-2-GP

1 2

R20160R0402 -PAD-2-GP R20160R0402 -PAD-2-GP

1 2

R20170R0402 -PAD-2-GP R20170R0402 -PAD-2-GP

1 2

R20190R0402 -PAD-2-GP R20190R0402 -PAD-2-GP

1 2

R20200R0402 -PAD-2-GP R20200R0402 -PAD-2-GP

1 2

R20210R0402 -PAD-2-GP R20210R0402 -PAD-2-GP

1 2

R20220R0402 -PAD-2-GP R20220R0402 -PAD-2-GP

1 2

R20230R0402 -PAD-2-GP R20230R0402 -PAD-2-GP

1 2

RN2012

RN2012 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2 3 4 5

R2024

1 2

100KR2J -1-GP

8 7 6

MCP_GPIO5 8

DRAM_SE L0 DRAM_SE L2

MCP_GPIO2 6 MCP_GPIO5 6

DRAM_SE L1

MCP_GPIO1 4 MCP_GPIO2 8 MCP_GPIO8 MCP_GPIO1 3

DRAM_SE L3

MCP_GPIO5 7

EC_SCI#

EC_SW I# RTC_DET #

WLAN _PLT_RST#

HSIOPC

3D3V_S0

10KR2J-3 -GP

EC_SW I#[24] EC_SCI#[24]

HDD_DEV SLP[56]

MSATA_D EVSLP[63]

HDA_SPK R[27]

1 2 3 4 5

R2009

R2010

BIOS strap pin:

BIOS UMA/DIS Strap pin

BOARD_ID2BOARD_ID1

PX(AMD)

DIS

UMA

Optimus(NV)

A A

0 0

0

1

5

1

BOARD_ID2

0

1

P1

BMB

SY#/GPIO76

U

AU2

GPI

8

O

AM7

LAN

PHY_PWR_CTRL/GPIO12

_

AD6

GPI

15

O

Y1

GPI

16

O

T3

O

17

GPI

AD5

GPI

24

O

AN5

O

27

GPI

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASW ELL-6-GP

PCH strap pin:

The internal pull-down is disabled a fter PLTRST# deasserts

The internal pull-down is disabled a fter RSMRST# deasserts.

The internal pull-down is disabled a fter PLTRST# deasserts

GPIO

NO REBOOT

Low = Disable (Default)

HDA_SPKR

*

High = Enable

Top-Block Swap Override mode

SDIO_D0 / GPIO66

High = Enable "Top-Block swap"

Low = Disable "Top-Block swap" mode

*

TLS Confidentiality

Low = Disable Intel ME Crypto TLS

GPIO15

*

High = Enable Intel ME Crypto TLS

Boot BIOS Strap Bit BBS

Boot BIOS Destination

Low = SPI

*

High = LPC

CPU/

CPU/ MISC

MISC

SERIAL IO

mode (Default)

3

THR

TRIP#

M

RCI

#/GPIO82

N

SER

PCH

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92 UART0_RTS#/GPIO93 UART0_CTS#/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST#/GPIO2 UART1_CTS#/GPIO3

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

I

OPI_RCOMP

_

RSV

#AF20

D D

#AB21

RSV

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

RQ

PCH

D60

H_R

V4

INT

T4

PCH

AW15 AF20 AB21

MCP_GPIO83

R6

MCP_GPIO84

L6

SATA_OD D_PWRGT

N6

LPSS_GS PI0_MOSI_BBS0_R

L8

MCP_GPIO87

R7

MCP_GPIO88

L5

TOUCH_P WR_EN

N7 K2 J1 K3

MCP_GPIO93

J2

MCP_GPIO94

G1

MCP_GPIO0

K4

MCP_GPIO1

G2

MCP_GPIO2

J3 J4

I2C0_SDA

F2

I2C0_SCL

F3

I2C1_SDA

G4

I2C1_SCL

F1

COLOR_E NGINE

E3

MCP_GPIO65

F4

LPSS_SD IO_D0_CM NHDR

D3

MCP_GPIO67

E4

MCP_GPIO68

C3

MCP_GPIO69

E2

3D3V_S0

1KR2J-1-G P

1KR2J-1-G P R2006

R2006

1 2

3D3V_S0

12

R2011

DY

1KR2J-1-G P

LPSS_SD IO_D0_CM NHDR

3D3V_S5 _PCH

12

R2014

DY

1KR2J-1-G P

3D3V_S0

12

R2012

DY

1KR2J-1-G P

LPSS_GS PI0_MOSI_BBS0_R

THERMTR IP

_

IN#

C SERIRQ

_

OPIRCOMP

_

DY

KB_DET# [62] KB_LED_ BL_DET [6 2] DBC_EN [52 ]

HDA_SPK R

MCP_GPIO15

1 1 1

1 1 1 1 1

1

1 1 1

2

1 2

R20

R20 49D9R2F -GP

49D9R2F -GP

TP2010TP2010 TP2011TP2011 TP2021TP2021

TP2012TP2012 TP2013TP2013 TP2014TP2014

TP2015TP2015 TP2016TP2016 TP2017TP2017 TP2018TP2018 TP2019TP2019

TP2005TP2005

TP2006TP2006 TP2007TP2007 TP2008TP2008

0

3

COLOR_E NGINE [52]

H_R

IN# [24]

C

INT

SERIRQ [2 4]

_

Layout Note:

1

.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

BLUETOO TH_EN [58]

RN2014

SRN10KJ -6-GP

INT_SERIRQ KB_DET#

H_RCIN# DBC_EN

I2C0_SDA

I2C1_SCL I2C1_SDA

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (GPIO)

Size Document N umber Rev

A3

Date: Sheet of

CPU (GPIO)

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

SRN10KJ -6-GP

1 2 3 4 5

RN2007

SRN10KJ -6-GP

8 7 6

20 10 1Friday, June 28, 201 3

1

3D3V_S0

8 7 6

3D3V_S0

1 2 3 45

X02

5

S

SID = CPU

D D

1D05V_S0

0R0402-PAD-2-GP

A00 0618

1 2

R2105

0R0402-PAD-2-GP

3D3V_S5

C C

1D05V_S0

R2101

1 2

0R0402-PAD-2-GP

R2117

1 2

0R0402-PAD-2-GP

12

DY

+V3.3A_DSW_P

C2136

SCD1U10V2KX-5GP

+V1.05S_SSCF100

C2137

SC1U6D3V2KX-GP

12

3D3V_S0

R2104

1 2

+V3.3A_1.5A_HDA3D3V_S5_PCH

R2106

1 2

0R0402-PAD-2-GP

4

C2105

12

DY

C2116

12

+V1.05DX_MODPHY_PCH

SC1U6D3V2KX-GP

TP2102TP2102

+V1.05S_APLLOPI

TP2107TP2107

SC1U6D3V2KX-GP

TP2108TP2108

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

TP2103TP2103 TP2104TP2104 TP2101TP2101

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP_VCCAPLLOPI_VAL

1

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

12

C2123

C2123 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

AA21

AH14

AH13

AH10

AE20 AE21

W21

M20

AC9 AA9

K19 A20

R21

K9

L10

M9 N8

P9 B18 B11

Y20

J13

V8 W9

J18

J17

T21 K18

V21

CPU1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD#Y20 VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

3

HSW_ULT_DDR3L

OPI

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20

VCCASW VCCASW VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

A00 0618

0R0402-PAD-2-GP

+3.

3A_DSW_PRTCSUS

AH11 AG10

+VCCRTCEXT

AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22

+PCH_VCCDSW PCH_VCCDSW_R

AG19 AG20 AE9

+1.05M_ASW

AF9 AG8

+V1.05A_SUS_PCH

AD10 AD8

J15

1D5V_S0

K14 K16

U8

+V3.3S_1.8S_LPSS_SDIO

T9

+V1.05A_AOSCSUS

AB8

TP_V1.05S_APLLOPI

AC20 AG16 AG17

12

C2109

C2109 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

RTC_AUX_S5

C2110

SCD1U10V2KX-5GP

1D05V_S0

R2110

R2110 5D1R2F-GP

5D1R2F-GP

1 2

1

0R0402-PAD-2-GP

1 2

TP2106TP2106

1

2

R21

02

1 2

3D3V_S0

TP2109TP2109

TP2105TP2105

C2135

SC1U6D3V2KX-GP

12

C2147

C2147 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2114

C2114 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2128

SC1U6D3V2KX-GP

12

3D3

3D3V_S5

V_S5_PCH

1 2

1D05V_S0

X02 remove C2103

+V3.3S_1.8S_LPSS_SDIO

0R0402-PAD-2-GP

12

C2104

SC1U6D3V2KX-GP

1

R2103

1 2

3D3V_S0

HASWELL-6-GP

1D05V_S0

B B

A A

R2118

1 2

0R0402-PAD-2-GP

5

+V1.05S_SSCFF

C2138

SC1U6D3V2KX-GP

12

HSIOPC[20]

4

1D05V_S0 1D05V_HSIO

1 2

5V_S5

1D05V_S0

HSIO

Non-HSIO

R2123

HSIO

0R2J-2-GP

12

C2102

SC4D7U6D3V3KX-GP

3

R2122

R2122 0R5J-5-GP

0R5J-5-GP

1 2

HSIOPC_R

U2101

1

VDD

2

D#2

3

D#3 D#44S#5

SLG59M1470VTR-GP

74.59147.093

9

HSIO

1D05V_HSIO

0R5J-5-GP

0R5J-5-GP R2114

ON

8

GND

S#7 S#6

HSIO_OUT

7 6 5

R2114

1 2

HSIO

12

HSIO

C2101

SC10U6D3V3MX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (POWER2)

Hadley 15"

21 101Friday, June 28, 2013

1

X02

5

SSI

D = CPU

D D

DC_TEST _AY2_AW2

TP2201TP2201

TP2204TP2204

C C

TP_DC_T EST_AY60

1

DC_TEST _AY61_AW61 DC_TEST _AY62_AW62

1

DC_TEST _A3_B3 DC_TEST _A61_B61 DC_TEST _B62_B63

4

HSW_ULT_DDR3L

CPU1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASW ELL-6-GP

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HSW_ULT_DDR3L

3

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

18 OF 19

RSVD#N23 RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7 RSVD#AU10 RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST _A3_B3

A3

TP_DC_T EST_A4DC_TEST _AY3_AW3

A4

TP_DC_T EST_A60

A60

DC_TEST _A61_B61

A61

TP_DC_T EST_A62TP_DC_T EST_B2

A62

TP_DC_T EST_AV1

AV1

TP_DC_T EST_AW1

AW1

DC_TEST _AY2_AW2

AW2

DC_TEST _AY3_AW3

AW3

DC_TEST _AY61_AW61DC_TEST _C1_C2

AW61

DC_TEST _AY62_AW62

AW62

TP_DC_T EST_AW63

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

2

TP2202TP2202

1

TP2203TP2203

1

TP2205TP2205

1

TP2206TP2206

1

TP2207TP2207

1

TP2208TP2208

1

HASW ELL-6-GP

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

RSVD

Hadley 15"

22 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

HSW

_ULT_DDR3L

CPU

A

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5

AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

A A A A28 A32 A36 A40 A44 A48 A52 A56

11 14 18 24

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASW ELL-6-GP

D D

C C

B B

_ULT_DDR3L

1N

4

14

OF 19

A

J35

VSS

J39

A

VSS

A

J41

VSS

J43

A

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

3

_ULT_DDR3L

HSW

CPU

1O

A

P22

VSS

P23

A

VSS

A

P26

VSS

P29

A

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16

VSS

AU18

VSS

AU20

VSS

AU22

VSS

AU24

VSS

AU26

VSS

AU28

VSS

AU30

VSS

AU33

VSS

AU51

VSS

AU53

VSS

AU55

VSS

AU57

VSS

AU59

VSS

AV14

VSS

AV16

VSS

AV20

VSS

AV24

VSS

AV28

VSS

AV33

VSS

AV34

VSS

AV36

VSS

AV39

VSS

AV41

VSS

AV43

VSS

AV46

VSS

AV49

VSS

AV51

VSS

AV55

VSS

HASW ELL-6-GP

2

15

OF 19

A

V59

VSS

V8

A

VSS

A

W16

VSS

W24

A

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Hadley 15"

23 10 1Friday, June 28, 201 3

1

X02

5

D = KBC

SSI

1D0

D D

C C

B B

5V_S0

Layout Note:

Need very close to EC

C2412

SCD1U10V2KX- 5GP

LCD_TST_EN[52]

LCD_TST[52]

R24

1 2

0R0402-PAD-2- GP

3D3V_S0

C24

SC2D2U6D3V2MX-GP

12

13

DY

R2417 0R0402-PAD-2-GPR2417 0R0402-PAD-2-GP

01

1 2

EC_AGND

Don't PD

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

ALL_SYS_PWRGD assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

R2444

R2444 0R2J-2-GP

0R2J-2-GP

R2446

R2446 0R2J-2-GP

0R2J-2-GP

1 2

eDP

1 2

LVDS

L_BKLT_EN[15]

eDP backlight Control from PCH

LVDS_R2136_BKLT _EN[53]

Backlight Control from LVDS Converter

EC_

VTT

12

C2401

SCD1U10V2KX-5GP

EC_FB_CLAMP_T GL_REQ#[76]

VBA

T

VBA

12

C2404

SCD1U10V2KX-5GP

EC_AGND

AD_IA[44]

C2414 SCD1U10V2KX-5GP

1 2

DY

PSID_EC[42]

PM_SLP_SUS#[17,38] BOOST_MON[44]

USBCHARG ER_CB0[35]

FAN1_DAC_1[26]

AD_IA_HW[44]

IMVP_PWRGD[7,46]

BAT_SCL[43,44,53] BAT_SDA[43,44,53]

SML1_CLK[18,26,76]

SML1_DATA[18,26,76]

PM_LAN_ENABLE[30]

RTCRST_O N[19]

USBCHG_EN[35]

TPCLK[62]

TPDATA[62]

ALL_SYS_PWRG D[36]

PWR_CH G_AD_OFF[42]

AD_IA_HW2[44]

BLON_OUT[52]

FAN_TACH 1[26]

PM_PWRBT N#[17,96]

EC_FB_CLAMP[75,76,83]

PM_SLP_S3#[17,36,48,49, 51]

PWRLED #[61]

KBC_BEEP[27]

EC_BRIGHTN ESS[52]

AC_IN_KBC#[42]

KB_BL_CTRL[62]

LAN_WAKE#[30]

KBC_DPW ROK[17]

CHG_AMBER_ LED#[61]

PCH_PW ROK[17,26,3 6]

USB_PWR _EN#[35]

AC_PRESENT[17,76]

SYS_PWROK[17,96] AOAC_WLA N_EN[58]

WIFI_RF_EN[58]

PM_SUSWA RN#[17]

DGPU_PW ROK[15,82,83]

DIS_DTM[44] E51_TxD[58]

PM_CLKRUN #_EC[17]

AMP_MUTE#[27]

12

R2445

100KR2J-1-GP

T

C2405

SC2D2U6D3V2MX-GP

12

DY

PCB_VER_AD

AMB_TEMP

MODEL_ID_DET

PROCHOT _EC LCD_TST_EN

ECSWI#_KBC

L_BKLT_EN_EC

3D3

EC_VTT

V_AUX_KBC_VC C

12

C2406

SCD1U10V2KX-5GP

KBC24

19

VCC

46

VCC

76

VCC

88

VCC

115

VCC

102

AVCC

4

VDD

12

VTT

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/EXT_PURST#/AD6

94

GPIO7/AD7/VD_IN2

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

70

GPIO17/SCL1/N2TCK

69

GPIO22/SDA1/N2TMS

67

GPIO73/SCL2/N2TCK

68

GPIO74/SDA2/N2TMS

119

GPIO23/SCL3/N2TCK

120

GPIO31/SDA3/N2TMS

24

GPIO47/SCL4/N2TCK

28

GPIO53/SDA4/N2TMS

26

GPIO51/TA3/N2TCK

123

GPIO67/N2TMS

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27/PSDAT2

25

GPIO50/PSCLK3/TDO

27

GPIO52/PSDAT3/RDY#

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DIO

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM/1_WIRE

81

GPIO66/G_PWM

66

GPO33/H_PWM/VD1_EN#

104

GPIO80/VD_IN1

110

GPIO82/IOX_LDSH/VD_OUT1

112

GPIO84/IOX_SCLK/VD_OUT2

84

GPIO77/SPI_MISO

83

GPIO76/SPI_MOSI

82

GPIO75/SPI_SCK

79

GPIO2/SPI_CS#

124

GPIO10/LPCPD#

121

GPIO85/GA20

111

GPIO83/SOUT_CR

9

GPIO65/SMI#

8

GPIO11/CLKRUN#

30

GPIO55/CLKOUT/IOX_DIN_DIO

NPCE985PA0DX -1-GP

71.00985.C0G

AOAC Ambient temperature detect

VBAT

12

R2437

R2437 10KR2F-2-GP

R2441

EC_AGND

C2419

1 2

10KR2F-2-GP

1 2

0V2KX-5GP

SCD1U1

C2420

AMB_TEMP

12

0P50V2JN-3GP

SC10

5

A A

NTC-10K-26- GP

69.60037.011

EC_GPIO47 High Active

PROCHOT _EC

12

R2442

100KR2J-1-GP

DY

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

4

02

R24

12

0R0603-PAD-2- GP-U

12

C2407

C2408

DY

SCD1U10V2KX-5GP

KBSIN0/GPIOA0/N2TCK

KBSIN1/GPIOA1/N2TMS

KBSOUT0/GPOB0/SOUT_CR/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT10/P80_CLK/GPIOC2

KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GPI/O63/TRIST#

KBSOUT14/GPI/O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

GPIO81/F_WP#/F_SDIO2 GPIO0/EXTCLK/F_SDIO3

PSL_IN2#/GPI6/EXT_PURST#

GPIO46/CIRRXM/TRST#

GPIO87/CIRRXM/SIN_CR

H_PROCHO T#_EC

D

4

2D2R3-1-U- GP

12

C2409

DY

SCD1U10V2KX-5GP

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

GPIO60/KBSOUT16 GPIO57/KBSOUT17

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

LFRAME#/GPIOF6

LRESET#/GPIOF7

F_CS0#

GPIO30/F_WP# GPIO41/F_WP#

F_SDIO/F_SDIO0

F_SDI/F_SDIO1

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

VBKUP VCORF

SERIRQ/GPIOF0

GPIO24

GPIO36/TB3

GPIO44/TDI GPIO43/TMS GPIO42/TCK

GPIO34/CIRRXL

1 2

0R0402-PAD-2- GP

C2410

F_SCK

VSBY

PECI

GND GND GND GND GND GND

AGND

R2440

3D3

R24

12

V_AUX_KBC

03

54 55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

90 92 109 80 87 86 91 77

73 93 74

29 85 122

75 114 44 13 125 6 15

21 20 17 23

113 14

5 18 45 78 89 116

103

1 2

12

SCD1U10V2KX- 5GP

C2411

SC2D2U6D3V2MX-GP

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 USB_DET#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

PLT_RST#_EC

EC_SPI_CS#_C EC_SPI_CLK_C

EC_SPI_DI_C EC_SPI_DO_C

PSL_IN1# PSL_IN2# PSL_OUT#

ECSCI#_KBC ECRST#

EC_VBKUP KBC_VCORF PECI

ECSMI#_KBC

EC_AGND

12

C2421

C2421 SC47P50V2JN-3G P

SC47P50V2JN-3G P

T

VBA

A00 0618

12

R24

04

64K9R2F-1-GP

PCB

_VER_AD

12

R24

06

100KR2F-L1-GP

C24

ME_UNLOCK [19]

WIFI_WAKE# [5 8]

S5_ENABLE [36]

X01 0321

12

R2435

R2435 0R0402-PAD-2- GP

0R0402-PAD-2- GP

EC_AGND

100KR2F-L1-GP

02

DY

1 2

EC_

AGND

KROW[0..7] [62]

KCOL[0..16] [62]

LPC_AD[3..0] [18,65]

CLK_PCI_KBC [18] LPC_FRAME# [18,65]

R2419 0R0 402-PAD-2-GPR2419 0R0402-PAD -2-GP

1 2

R2412 33R 2J-2-GPR2412 33R 2J-2-GP

12

R2420 0R0 402-PAD-2-GPR2420 0R0402-PAD -2-GP

1 2

R2422 0R0 402-PAD-2-GPR2422 0R0402-PAD -2-GP

1 2

Layout Note:

Need very close to EC

H_RCIN# [20]

R2428 0R0 402-PAD-2-GPR2428 0R0402-PAD -2-GP

1 2

INT_SERIRQ [20]

OVER_CUR RENT_P8# [76]

PM_SLP_S4# [17,49] RSMRST#_KBC [17]

CH751H-40PT -GP

83.R0304.A8F

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

LID_CLOSE# [61]

D2402

21

3D3V_AUX_S5 RTC_AUX_S5

DY

3

VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

PCB

00

X

01

02

X

03

A

00

R

served

e

Res

erved

served

e

eserved 100.0K 215.0K 1.048V

R

SPI_CS0#_R [18,25] SPI_CLK_R [18,25] CAP_LED# [62] BAT_IN# [42,43,44] SPI_SI_R [18, 25] SPI_SO_R [18,25]

PM_SUSACK# [17]

PCH_SUSC LK_KBC [17]

C2416 SC1U6D3V2 KX-GPC2416 SC1U6D 3V2KX-GP

1 2

R2429

12

C2422

43R2J-GP

SC100P50V2JN-3 GP

TOUCH_PA NEL_INTR# [52]

10KR2J-3-GP

PURE_HW _SHUTDOW N#[26,36,76]H_PROCH OT# [4,42,44,46]

3

00.0K

1

100.0K

1

00.0K 1.358V

00.0K

1

A00 0618

0R0402-PAD-2- GP

R2416

1 2

12

SC220P50V2KX-3GP

SC220P50V2KX-3GP C2415

C2415

DY

H_PECI [4]

Layout Note:

Need very close to EC C2422 PDG is 47p

3D3V_AUX_S5

R2439

R2434

12

1 2

DY

0R2J-2-GP

Q2404

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

E

B

C

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

1

43.0K

74.0KR

1

PLT_RST# [17,30,58,65,73]

KBC_PWR BTN#[61]

AC_IN#[44]

USBDET_CO N#[34]

ECRST#

C2418

12

DY

SC1U6D3V2KX-GP

3.0V

2

.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

0R0402-PAD-2- GP

R2427

1 2

0R0402-PAD-2- GP

R2430

1 2

D2401

3

BAT54CPT-2- GP

75.00054.K7D

PSL_OUT#

2

MOD

1

2

1 2

2

3D3V_AUX_S5

1KR2J-1-GP

1KR2J-1-GP R2432

R2432

EL_ID_DET

C24

SCD1U10V2KX- 5GP

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

1 2

PSL_IN2#

PSL_IN1#

USB_DET#

KBC_ON#_GAT E_L

VBAT

MODEL_ID_DET(GPIO07)

(DOH70)UMA

R2405

49K9R2F-L-GP

12

03

DY

1 2

EC_

AGND

3D3V_AUX_S5 3D3V_AUX_S5

R24

100KR2F-L1-GP

07

1 2

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2433

R2433 20KR2J-L2-GP

20KR2J-L2-GP

(DOH50)UMA/eDP

TBD

(DO

H70)DIS

TBD TBD TBD TBD

(DOH50)UMA/LVDS

D

OH50)DIS/eDP

(

TBD TBD TBD TBD TBD TBD TBD TBD

(DOH50)DIS/LVDS

TBD

ECSCI#_KBC

ECSMI#_KBC

ECSWI#_KBC

KBC_ON#_GAT EKBC_ON#_GAT E_L

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

AC_IN_KBC#

USB_DET#

BAT_SCL BAT_SDA

ECRST#

AC_IN# BAT_IN# OVER_CUR RENT_P8#

FAN_TACH 1

LID_CLOSE#

C2417

C2417 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

1 2

G

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

G

S

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, June 28, 2013

Friday, June 28, 2013 Date: Sheet of

Date: Sheet of

1

00.0K

1

100.0K

10.0K 1

3.7K

1

7.8K

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

7.6K

5 6

4.9K

3.2K

7

82.5K(64.82525.6DL) 1.808V

3.1K

9 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 2

32K

X01 0321

R24080R0402- PAD-2-GP R24080R 0402-PAD-2-GP

1 2

R24090R0402- PAD-2-GP R24090R 0402-PAD-2-GP

1 2

R24100R0402- PAD-2-GP R24100R 0402-PAD-2-GP

1 2

R2426 100KR2J-1-GPR2426 100KR2J-1-GP

1 2

R2411 100KR2J-1-GPR2411 100KR2J-1-GP

1 2

RN2401

4

SRN4K7J-8-G P

R2418 10KR2J -3-GPR 2418 10KR2J-3- GP

1 2

R2413 100KR2 J-1-GP

1 2

DY

R2414 100KR2 J-1-GPR 2414 100KR2J-1- GP

1 2

R2424 100KR2 J-1-GP

1 2

DY

R2415 10KR2J -3-GPR 2415 10KR2J-3- GP

1 2

R2421 100KR2J-1-GPR2421 100KR2J-1-GP

1 2

S

G

D

3D3V_AUX_KBC

Q2403

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

KBC Nuvoton NPCE985

Hadley 15"

1

64.10025.6DL)

( (

64.13725.6DL)

(

64.17825.6DL)

64.57625.6DL)

( (

64.64925.6DL)

64.73225.6DL) 1.905V

(

64.93125.6DL)

(

64.23236.6DL)

EC_SCI# [20]

EC_SMI# [19]

EC_SWI# [20 ]

3D3V_AUX_KBC

23 1

3D3V_AUX_KBC

3D3V_S0

3D3V_S5

3D3V_AUX_KBC

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

24 101

.0V

3 2

.902V

2.801V

2.702V

2.598V

2.492V

2.402V 2

.304V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

X02

5

D = Flash.ROM

SSI

4

3

2

1

SPI Flash ROM(8M) for PCH

3D3

V_S5

D D

R25

01

4K7R2J-2 -GP

4

RN2

501

SRN4K7J -8-GP

DY

1 2

1

2 3

DY

3D3

V_S5

SC10U6D3V3MX-GP

C2501

12

C25

02

SCD1U10 V2KX-5GP

Single SPI shared flash connection (SPI Quad I/O mode)

SPI25

SPI_CS0#_ R[18,24]

SPI_SO_R[1 8,24]

SPI_WP #[18]

12

DY

EC2502

SC4D7P5 0V2CN-1GP

C C

EC2502

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25 Q64FVSSIQ-GP

72.25Q64.K01

VCC

HOLD#/IO3

CLK

DI/IO0

3D3V_S5

8 7 6 5

12

DY

12

EC2503

DY

SC10P50 V2JN-4GP

EC2501

SC4D7P5 0V2CN-1GP

QUAD/DUAL fast read DUAL fast readSource

72.25Q64.K01

72.25647.00A O O

SPI_HOLD# [18] SPI_CLK_R [18,2 4] SPI_SI_R [18,24]

O O

Re

er to "NCPE985x/ NPCE995x board design reference guide"

f

SSID = RBATT

3

RTC_AUX _S5+RTC_VC C 3D 3V_AUX_S5

1 2

C2503

SC1U6D3 V2KX-GP

A00 0619

D2501

2

1

BAS40CW -GP

83.00040.E81

1 2 NP1 NP2

+RTC_VC C

1

1KR2J-1-G P

R2502

12

RTC_PW R

B B

AFTP250 2AFTP2502

RTC1

PWR GND

NP1 NP2

BAT-AAA-B AT-054-P06-GP-U

62.70001.061

A A

5

4

AFTP250 1AFTP2501

1

Q2505

12

R2504

R2504 10MR2J-L -GP

10MR2J-L -GP

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

3

RTC_DET # [20]

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Flash/RTC

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

25 10 1

1

X02

SSI

D = Thermal

5

4

3

2

1

Fan controller1

5V_

FAN1

1

12

C2605

4

5

AFTP260 1AFTP2601

AFTP260 2AFTP2602

S0

12

C2611

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

FAN

R26

05

0R2J-2-GP

3D3

V_S0

D D

3D3V_S0

SC10U6D3V3MX-GP

C2601

12

C2602

SCD1U10V2KX-5GP

84.03904.L06

2ND = 84.03904.P11

C C

3

1

Q2603

PMBS390 4-1-GP

2

NCT7718 _DXP

12

C2606

C2606 SC470P5 0V3JN-2GP

SC470P5 0V3JN-2GP

DY

NCT7718 _DXN

12

C2607

C2607 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

2.System Sensor, Put on palm rest

A00 0618

12

R2601

R2601 0R0402-P AD-2-GP

Layout Note:

C2812 close U28 01

Layout Note:

Both DXN and DX P routing 10 m il trace width and 10 mil spa cing.

3D3V_S0

R2603 18K7R2F-GPR2603 18K7R2F-GP

B B

1 2

R2604 2KR2F-3-GPR2604 2KR2F-3-GP

1 2

ALERT#

T_CRIT#

0R0402-P AD-2-GP

SML1_DA TA[18,24,76]

SML1_CL K[18,2 4,76]

THM26

1

VDD

2

D+

3

D-

T_CRIT#

ALERT#

T_CRIT#4GND

NCT7718 W-GP

74.07718.0B9

1204 change to PCH_PWROK

PCH_PW ROK[17,24,36 ]

THERM_S YS_SHDN#

SCL

SDA

6

5

Q2601

Q2601 2N7002K DW-GP

2N7002K DW-GP

8 7

ALERT#

6 5

G

S

3D3

V_S0

1

2

34

Q2602

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

1

23

602

RN2

RN2 SRN2K2J -1-GP

SRN2K2J -1-GP

4

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

12

DY

C2608

SCD1U10V2KX-5GP

12

C2610

DY

SCD1U10 V2KX-5GP

THM_SML 1_DATA

THM_SML 1_CLK

THM_SML 1_CLK THM_SML 1_DATA

12

C2609

SCD1U10V2KX-5GP

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW _SHUTDOW N# [2 4,36,76]

FAN

Layout Note:

Need 10 mil tra ce width.

0R2J-2-GP

1 2

5V_

S0

1_DAC_1[24]

FAN_TAC H1[2 4]

SC4D7U6 D3V3KX-GP

DY

FAN

C2604

_VCC_1

DY

FON

12

FAN

261

#

1

FSM

#

2

VIN

3

VOU

T

4

VSE

T

APL5606 AKI-TRG-GP

74.05606.A71

2nd = 74.02113.0E1

0R0402-P AD-2-GP

R2606

1 2

21

D2601

DY

CH551H-3 0PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

GND GND GND GND

FAN_TAC H1_C

FAN_VCC _1

12

C2603

DY

SC2200P50V2KX-2GP

8 7 6 5

FAN_TAC H1

FAN_VCC _1

1

2 3

ETY-CON3-8-GP

20.F1841.003

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

26 10 1

1

X02

S

SID = AUDIO

5

4

3

2

1

AGND

EC2

2_VREFO [29]

C2702

C2702 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

25

26

AVSS1

AVDD1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

CPVREF

MIC_CAP

MIC2_R/SLEEVE

MIC2_L/RING2

MONO_OUT

JDREF

SENSE_B

SENSE_A

12

AUD_PC_BEEP

+3V_AVDD

MIC

AUD

_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

MIC_CAP

JDREF

R2707 20KR2F-L-GPR2707 20KR2F-L-GP

AUD_SENSE_A

Layout Note:

AGND

Place close to Pin 13

DGND

12

C2710

SCD1U10V2KX-5GP

LINE1_L [29]

LINE1_R [29]

1 2

SLEEVE [29]

RING2 [29]

1 2

R2709

39K2R2F-L-GP

C2711

AGND

1 2

0R0603-PAD-2-GP-U

12

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

AUD_SENSECOMBO-GPI

DGND

5V_S0+5V_AVDD

A00 0618

R2703

AUD_AGND

Layout Note:

Width>40mil, to improve Headpohone Crosstalk noise

AUD_AGND

AUD_SENSE [29]

LIN

E1_VREFO_R[29]

LIN

E1_VREFO_L[29]

D D

C C

B B

3D3

V_S0

5V_S0 +5V_PVDD

A00 0618

1D5V_S0

3D3V_S0

25mA

1 2

R2701

0R0402-PAD-2-GP

A00 0618

1.5A

0R0805-PAD-2-GP-U

R2702

12

0R0805-PAD-2-GP-U

R2704

12

Layout Note:

Close pin41

DGND

A00 0618

0R0402-PAD-2-GP

R2710 0R2J-2-GP

R2705

1 2

DY

AGND

Azalia I/F EMI

EC2701

SCD1U10V2KX-5GP

PCH_AZ_CODEC_SDOUT1 HDA_CODEC_SDOUT

12

DY

HDA_CODEC_BITCLK_C

12

DY

EC2702

SC22P50V2JN-4GP

+3V

_AVDD

12

C2701

SC4D7U6D3V3KX-GP

C2706

12

SC4D7U6D3V3KX-GP

+3V_1D5V_AVDD

AUD_AGND

Close pin36

C2707

12

SCD1U10V2KX-5GP

12

C2715

SC4D7U6D3V3KX-GP

ER2701

47R2J-2-GP

1 2

ER2702

47R2J-2-GP

C2709

C2708

12

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

Close pin40

12

DY

HDA_CODEC_BITCLK

DY

AUD_AGND

AMP_MUTE#[24]

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

0R0402-PAD-2-GP

R2708

1 2

remove D2702 R2710 R2711 Add R2708_0R(PDB pin)

TP2702TP2702

DMIC_CLK[52]

SC22P50V2JN-4GP

Close pin3

0109 Add Close pin2

C2723

DMIC_DATA[52]

DY

1 2

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_RST#[19,29]

SC22P50V2JN-4GP

C2724

1 2

DY

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

SC4D7U6D3V3KX-GP

AUD

_HP1_JACK_L[29]

AUD

_HP1_JACK_R[29]

12

C2703

C2703 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

CBP

LDO2_CAP

EAPD#

C2716

A00 0618

0R0402-PAD-2-GP

R2714

1 2

R2716

1 2

0R0402-PAD-2-GP

+3V_AVDD

HDA27

37

CBP

38

AVSS2

39

LDO2_CAP

40

AVDD2

41

PVDD1

42

SPK_L+

43

SPK_L-

44

SPK_R-

45

SPK_R+

46

PVDD2

47

PDB

48

SPDIFO/GPIO2

49

GND

ALC3223-CG-GP

+3V_AVDD

12

C2717

SCD1U10V2KX-5GP

DMIC_DATA_R

DMIC_CLK_R

0R0402-PAD-2-GP

R2718

1 2

HDA_CODEC_SYNC

HDA_CODEC_RST#

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP C2704

C2704

1 2

CPVEE

CBN

35

33

34

36

CPVDD

DVDD1GPIO0/DMIC_DATA2GPIO1/DMIC_CLK3DVSS4SDATA_OUT5BIT_CLK6LDO3_CAP7SDATA_IN8DVDD_IO9SYNC10RESET#11PCBEEP

CBN

CPVEE

HP_OUT_R

HDA_CODEC_SDIN0

32

HP_OUT_L

C2705

12

AUD_VREF

28

31

29

30

MIC2_VREFO

LINE1_VREFO_L

LINE1_VREFO_R

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

SC2D2U6D3V2MX-GP

LDO1_CAP

27

VREF

LDO1_CAP

C2719SCD1U10 V2KX-5GP C2719SCD1U10 V2KX-5GP

EC2

EC2703 SCD1U10V2KX-5GPEC2703 SCD1U10V2KX-5GP

AUD_AGND

DGND

708 SCD1U10V2KX-5GP

1 2

DY

707 SCD1U10V2KX-5GP

1 2

706 SCD1U10V2KX-5GP

1 2

705 SCD1U10V2KX-5GP

1 2

704 SCD1U10V2KX-5GP

1 2

DY

1 2

Layout Note:

Tied at point only under Codec or near the Codec

AGND

R2711 0R0603-PAD-2-GP-UR2711 0R0603-PAD-2-GP-U R2706 0R0603-PAD-2-GP-UR2706 0R0603-PAD-2-GP-U

DGND

1 2 1 2

Layout Note:

Tied at point only under Codec or near the Codec

RN

HDA_SPKR[20]

KBC_BEEP[24]

A A

5

4

1 2 3

0R4P2R-PAD

RN2701

HDA_SPKR_R

4

KBC_BEEP_R

D2701

1

2

BAT54CPT-2-GP

75.00054.K7D

2nd=75.00054.J7D

3

AUD_PC_BEEP_C

3

12

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

AUD_PC_BEEP

1 2

C2720

C2720 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Audio Codec ALC3223

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

of

27 101Friday, June 28, 2013

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

28 10 1Friday, June 28, 201 3

X02

D = AUDIO

SSI

5

4

3

2

1

A00 0618

AUD

R29

R29060R0603-P AD-2-GP-U R29060R0603-P AD-2-GP-U

12

R29070R0603-P AD-2-GP-U R29070R0603-P AD-2-GP-U

12

R29090R0603-P AD-2-GP-U R29090R0603-P AD-2-GP-U

12

R29110R0603-P AD-2-GP-U R29110R0603-P AD-2-GP-U

12

R29

12

R29

12

R29

12

AUD_POR TA_R_R_B

AUD_AGN D

D D

C C

RN2901

RN2901 SRN2K2J -1-GP

SRN2K2J -1-GP

1

MIC2_VREF O[27]

RING2[27 ]

AUD_HP1 _JACK_L[27]

LINE1_L[27]

LINE1_VRE FO_L[27]

AUD_SEN SE[2 7]

AUD_HP1 _JACK_R[27]

LINE1_R[27]

LINE1_VRE FO_R[27]

SLEEVE[2 7]

B B

C2907

C2907 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

C2908

C2908 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

1 2

LINE1_L_C

LINE1_R_C

4

2 3

R2908 10R2F-L -GPR2908 10R2F-L -GP

1 2

R2921 1KR2J-1 -GPR2921 1KR2J-1 -GP

1 2

R2912 2K2R2J -2-GPR2912 2K2R2J -2-GP

1 2

R2910 10R2F-L -GPR2910 10R2F-L -GP

1 2

R2922 1KR2J-1 -GPR2922 1KR2J-1 -GP

1 2

R2913 2K2R2J -2-GPR2913 2K2R2J -2-GP

1 2

AUD

_SPK_R+[27]

AUD

_SPK_R-[27] _SPK_L+[27]

AUD AUD_SPK _L-[27]

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

12

DY

EC2901

SC2K2P50V3KX-GP

DY

EC2902

EC2903

SC2K2P50V3KX-GP

12

DY

EC2904

SC2K2P50V3KX-GP

A00 0618

SC100P50V2JN-3GP

EC2907

EC2908

10KR2J-3-GP

R2919

12

SC100P50V2JN-3GP

EC2906

EC2905

10KR2J-3-GP

R2920

12

EC2905

12

DY

AUD_AGN DAUD_AGND

_SPK_R+ _C

040R0603-PAD-2 -GP-U

AUD

_SPK_R-_ C

030R0603-PAD-2 -GP-U

_SPK_L+ _C

020R0603-PAD-2 -GP-U

AUD AUD

_SPK_L-_ C

010R0603-PAD-2 -GP-U

RING2_R

AUD_POR TA_L_R_B

SLEEVE_ R

Speaker

1

2 3 4

ACES-CON 4-7-GP-U

20.F0772.004

AUD_SPK _L-_C AUD_SPK _L+_C AUD_SPK _R-_C AUD_SPK _R+_C

Universal jack

AUD_AGN D

AUD_POR TA_L_R_B AUD_POR TA_R_R_B

AUD_SEN SE

SPK

1

5

6

HPMIC1

3 1

5 6 2 4

MS

AUDIO-JK40 4-GP

22.10270.V01

1 1 1 1

AFTP290 6AFTP2906 AFTP290 7AFTP2907 AFTP290 8AFTP2908 AFTP290 9AFTP2909

AFTP290 1AFTP2901 AFTP290 2AFTP2902 AFTP290 3AFTP2903 AFTP290 4AFTP2904

CONN Pin

Pin1

Pin2

Pin3

Pin4

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L_

R2918

100KR2J -1-GP

D

34

GG

2

S

1

3

+3V_AVD D

POP_G2POP_G1

12

DY

12

C2901

DY

SC1U6D3 V2KX-GP

0R0402-P AD-2-GP

R2917

1 2

HDA_COD EC_RST# [19 ,27]

SLEEVE [27]

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Speaker/HPMIC CONN

Size Document N umber Rev

A3

Date: Sheet of

Speaker/HPMIC CONN

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

29 10 1Friday, June 28, 201 3

1

X02

AUD_POR TA_R_R_B

AUD_POR TA_L_R_B

RING2_R

AUD_SEN SE

SLEEVE_ R

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2904

75.02025.077

DY

AZ2025-01H-R7G-GP

ED2905

12

4

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2903

75.02025.077

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2902

75.02025.077

AZ2025-01H-R7G-GP

ED2

12

901

A A

DY

75.02025.077

5

5V_PW R_2

12

AUD_AGN D

R2915

R2915 220KR2J -L2-GP

220KR2J -L2-GP

U2901

S

5

D

6

2N7002K DW-GP

5

D = LOM

SSI

V_S5

3D3

12

SCD1U10V2KX-5GP

C3013

Q3001

G

S

2N7002K -2-GP

1 2

12

D D

PM_LAN_ ENABLE[2 4]

100KR2J -1-GP

3D3V_LA N_S5 VDDREG

C C

12

C3007

SCD

1U10V2KX-5GP

12

R3023

DY

R3006 0R0603-PAD -2-GP-UR3006 0R0603-PAD -2-GP-U

12

C3012

C3008

SCD

1U10V2KX-5GP

D

LAN_SW

R30

R30 10KR2J-3 -GP

10KR2J-3 -GP

LAN_ENABLE_R_C

12

C3009

SCD1U10V2KX-5GP

21

R30

22

20KR2F-L -GP

1 2

LAN_SW

12

C3010

PM_

LAN_ENA BLE_R

main: 84.00102.031 2nd: 84.03403.031

SC4D7U6D3V3KX-GP

X5R

A00 0618

R3034 0R0603-PAD -2-GP-UR3034 0R0603-PAD -2-GP-U

1 2

B B

12

DY

C3018

SCD

1U10V2KX-5GP

L3010

1 2

IND-4D7UH-2 42-GP

LAN_SW

68.4R71E.10G

LAN_SW

C3024

12

SC4D7U6D3V3KX-GP

C3014

12

LAN_SW

SCD1U10V2KX-5GP

A00 0618

0R0603-P AD-2-GP-U

R3007

1 2

X5R

A A

5

12

03

C30

C30 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

0311 modify power railA00 0618

12

4

PA102FM G-GP-U

PA102FM G-GP-U Q30

Q30

04

G

3D3V_LA N_S5

12

C3019

C3020

SCD1U10V2KX-5GP

4

DS

R3039

R3039 10KR2J-3 -GP

10KR2J-3 -GP

LAN_W AKE#

12

C3021

SCD1U10V2KX-5GP

EVDD10

12

C3016

SCD1U10V2KX-5GP

3D3

V_LAN_S 5

12

DY

05

C30

SCD1U10V2KX-5GP

Pin12 Pull VCC33 (3D3V_S0) Supported RTD3

12

C3022

SCD1U10V2KX-5GP

12

C3023

SC1U6D3V2KX-GP

ENSW REG

CLK_PCIE_ LAN_REQ4#[18]

LAN

LANXIN

LAN_W AKE#[24]

XOUT

3

41

2 3

C3001

1 2

SC15P50 V2JN-2-GP

3D3V_LA N_S5

12

LAN_SW

12

0110 add CAP need close to chip

3D3V_S0

12

LAN_TXP _C_PCH_RXP4 LAN_TXN _C_PCH_RXN4

PCIE_PTX_ LANRX_P4_C PCIE_PTX_ LANRX_N4_C

3

C30

11

1 2

SC15P50 V2JN-2-GP

X30

01

XTAL-25M HZ-155-GP

R3036

R3036 0R2J-2-GP

0R2J-2-GP

A00 0618

R3037

R3037 0R0402-P AD-2-GP

0R0402-P AD-2-GP

VDD10 VDD10 VDD10

VDD10

EVDD10

3D3V_LA N_S5 3D3V_LA N_S5

3D3V_LA N_S5

SCD1U10V2KX-5GP

C3028

LAN_W AKE# ISOLATE#

PLT_RST #_LAN

CLK_PCIE_ LAN_P4 CLK_PCIE_ LAN_N4

PCIE_PTX_ LANRX_P4_C PCIE_PTX_ LANRX_N4_C

LAN_TXP _C_PCH_RXP4 LAN_TXN _C_PCH_RXN4

CARD_3D 3V

VDDREGVDD10REGOUT

C3025 SCD1U10 V2KX-5GPC 3025 SCD1U10V2KX-5G P

1 2 1 2

C3026 SCD1U10 V2KX-5GPC 3026 SCD1U10V2KX-5G P

Close To Pin 27

VDD33/18

U3001

3

AVDD10

8

AVDD10

46

AVDD10

33

DVDD10

20

EVDD10

11

AVDD33

48

AVDD33

12

DVDD33

32

DVDD33

13

CARD_3V3

27

VDD33/18

35

VDDREG

39

LANWAKE#

31

ISOLATE#

29

CLKREQ#

30

PERST#

23

REFCLK_P

24

REFCLK_N

21

HSIP

22

HSIN

25

HSOP

26

HSON

RTL8411 B-CGT-GP

71.08411.D03

2

A00 0618

0R0603-P AD-2-GP-U

R30

08

1 2

12

C3017

C3027

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

DY

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

44

CKXTAL1

45

CKXTAL2

REGOUT

RSET

LED_CR

LED0

LED1/GPO

LED3

SD_D1

SD_CD#

MS_CD#

GND

2

34 36 47

40 41 38 37

15 14 19 18

16 17 28

42 43

49

ENSWREG_H

SD_D0/MS_D1

SD_D2/MS_CLK

SD_D3/MS_D3

SD_CLK/MS_D0

SD_SMD/MS_D2

SD_WP/MS_BS

PCIE_PRX_ LANTX_P4 [1 6] PCIE_PRX_ LANTX_N4 [16]

PCIE_PTX_ LANRX_P4_C [16] PCIE_PTX_ LANRX_N4_C [16]

CLK_PCIE_ LAN_P4 [18] CLK_PCIE_ LAN_N4 [18]

D_3D3V

CAR

LANXIN LANXOUT

ENSW REG REGOUT RSETVDD33/18

LED_CR LED0 LED1 LED3

SP2 SP1 SP6 SP5

SP3 SP4 SP7

1

V_S0

Clo

se To Pin 13

12

C30

15

SCD1U10V2KX-5GP

DY

PLT_RST #[17,24,58,6 5,73]

LAN_MDI0P [31] LAN_MDI0N [31 ] LAN_MDI1P [31] LAN_MDI1N [31 ] LAN_MDI2P [31] LAN_MDI2N [31 ] LAN_MDI3P [31] LAN_MDI3N [31 ]

TP3004 T PAD14-OP-GPTP3004 TPA D14-OP-GP

1

TP3003 T PAD14-OP-GPTP3003 TPA D14-OP-GP

1

TP3002 T PAD14-OP-GPTP3002 TPA D14-OP-GP

1

TP3001 T PAD14-OP-GPTP3001 TPA D14-OP-GP

1

A00 0618

R3017 0R0402-P AD-2-GPR3017 0R0 402-PAD-2-GP

12

R3018 0R0402-P AD-2-GPR3018 0R0 402-PAD-2-GP

12

R3019 0R0402-P AD-2-GPR3019 0R0 402-PAD-2-GP

12

R3020 0R0402-P AD-2-GPR3020 0R0 402-PAD-2-GP

12

R3032 0R0402-P AD-2-GPR3032 0R0 402-PAD-2-GP

12

R3033 0R0402-P AD-2-GPR3033 0R0 402-PAD-2-GP

12

R3035 0R0402-P AD-2-GPR3035 0R0 402-PAD-2-GP

12

Title

Size Document N umber Rev

A3

Date: Sheet of

LOM(RTL8411B)

3D3

R3038

2K49R2F -GP

Hadley 15"

12

ISO

14

R30

15KR2F-G P

1

4

3

12

30 10 1Friday, June 28, 201 3

LATE#

12

15

DY

PLT_RST #_LAN

A00 0618

1 2

R30

1KR2J-1-G P

3D3V_LA N_S5

23

RN3001

DY

SRN10KJ -5-GP

Q402_1

1

2

DY

Q3003

Q3003 PMBS390 4-1-GP

PMBS390 4-1-GP

R3016

0R0402-P AD-2-GP

SP2/SD_D 0/MS_D1 [33] SP1/SD1 [33] SP6/SD_D 2/MS_CLK [33] SP5/SD_D 3/MS_D3 [33]

SP3/SD_C LK/MS_D0 [33] SP4/SD_C MD/MS_D2 [33] SP7/SD_W P/MS_BS [33]

SD_CD# [33] MS_CD# [33]

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

X02

Dell 15-7537 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual