Dell 15-7537 Schematic

5

D D

4

3

2

1

Hadley15" Schematics Document

Haswell ULT

C C

2013-06-28

REV : A00

B B

DY : None Installed UMA: UMA only installed OPS: Optimus solution installed. eDP: Support eDP Panel installed. LVDS: Support LVDS Panel installed.

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Hadley 15"

1

1 101Friday, June 28, 201 3

X02

5

4

3

2

1

Project code : 91.47L01.001

Had

y15 Block Diagram

l

PCB P/N

: 12311-1

Revision : A00

eDP

/

eDP L

USB 2.0

VDS Option circuit

52, 53

eDP

S

Converter

Realtek

LVD

RTD2136R

USB PowerShare

PERICOM

PI5USB1457AZAE

PCI-E

USB 2.0

to LVDS

35

5

3

TMDS

USB 2.0

USB 3.0

USB 2.0

USB 3.0

eDP

Intel CPU

Haswell ULT

15W/25W

Lynx Point-LP

8 USB 2.0/1.1 ports

2-4 USB 3.0 ports

High Definition Audio

4 SATA ports

8-12 PCIE ports

LPC I/F

ACPI 4.0a

DDR

L Channel A

3

DDR3L Channel B

PCI-E x4

USB 2.0

SMBUS

INT1

N14P-GT

Touch Screen

2M 720P Camera

D D

15.6" LCD

FHD(1920 x 1080)

52

HDMI CONN

54

USB 3.0 / Power share

34

C C

USB 3.0 CONN

34

Mini-Card

802.11a/b/g/n BT

58

Daughter board

USB 2.0

SATA3

SATA repeater

TI

SN75LVCP601

USB 3.0 CONN

USB 3.0

B B

USB3.0 Redriver

TI

SN65LVPE502RGER

USB 3.0

USB 2.0

PCI-E

LAN+Card reader

(10/100/1000M)

Realtek

RTL8411B

USB 3.0 CONN

USB 3.0

mSATA

SATA3

USB3.0 Redriver

TI

SN65LVPE502RGER

SATA repeater

TI

USB 3.0

SATA3

LPC

LPC debug port

SN75LVCP601

Nuvoton

NPCE985PA0DX

PS2

Touch Pad

62

Flash ROM

3

SPI

8MB

25

Internal Digital MIC

A A

Universal jack

29

2CH SPEAKER

5

52

Audio Codec

Realtek

HDA

ALC3223

27

SMBus

29

4

GPU

25W

KBC

3

L

DDR 1600MHz

DDR3L 1600MHz

73~77

52

30

65

24

Backlight Int. KB

Slot A

Slot B

GDDR5 Ch A

GDDR5 Ch B

SATA3

SMBus

62

2

1

2

13

VRAM(GDDR5)

128M x 16 x4(1GB)

VRAM(GDDR5)

128M x 16 x 4(1GB)

FFS

ST

DE351DL

INT2

67

HDD

RJ45

31

MMI Card Connector (SD/SDHC/SDXC/ SD-UHS/MS/MS-Pro)

Thermal

Nuvoton

NCT7718W

DC Fan Contrroller

ANPEC

APL5606AKI

Title

Size Document Number Rev

Date: Sheet of

56

Custom

INP

DCBATOUT

INPUTS OUTPUTS

DCBATOUT

INPUTS

DCBATOUT

INPUTS

DCBATOUT

5V_S5 3D3V_S5

3D3V_S0 1D05V_S0

1D35V_S3 1D35V_VGA_S0

3D3V_S5

PCB LAYER

33

26

DC Fan

26

Module

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Hadley 15"

R

GER

CHA

BQ24717

AD+ B

OUTPUTSINPUTS

T

+ DCBATOUT

T

EM DC/DC

SYS

TPS

1225

5

TS OUTPUTS

U

5V_AUX_S5 3D3V_AUX_S5 5V_CHARGER 3D3V_PWR

CPU DC/DC TPS51622

VCC_CORE

SYSTEM DC/DC

TPS51363

OUTPUTSINPUTS

1D05V_S0

SYSTEM DC/DC

TPS51216

OUTPUTS

1D35V_S3 0D675V_S0

SYSTEM DC/DC

NCP81172

OUTPUTS

VGA_CORE

Switches

OUTPUTSINPUTS

5V_S0 3D3V_S0

3D3V_VGA_S0 1D05V_VGA_S0

LDO

TLV70215DBVR

OUTPUTSINPUTS

L1 : TOP

L2 : GND

L3 : Signal

L4 : Signal

L5 : VCC

L6 : Signal

L7 : GND

L8 : Bottom

26

2 101Friday, June 28, 2013

1

46~47

36, 83

44

45

48

49

82

51

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

(Reserved)

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

3 101Friday, June 28, 201 3

1

X02

D = CPU

SSI

5

4

3

2

1

D D

1D05S_V CCST

12

R401

62R2J-GP

H_PROCH OT#[24,42,44,4 6]

C C

R407 200R2F-L -GPR407 200R2F-L -GP

1 2

R408 120R2F-G PR40 8 120R2F-G P

1 2

R409 100R2F-L 1-GP-UR409 100R2F-L 1-GP-U

1 2

Layout Note:

Design Guidelin e: SM_RCOMP keep r outing length less than 500 m ils.

Layout Note:

Impedance contr ol:50 ohm

SM_RCOM P_0

SM_RCOM P_1

SM_RCOM P_2

TP401TP401 TP402TP402

H_PECI[24]

1 2

TP403TP403

DDR_PG_ CTRL[12]

R403

R403 56R2J-4-G P

56R2J-4-G P

SKTOCC#

1

H_CATER R#

1

H_PROCH OT#_R

H_CPUPW RGD

1

R405

12

10KR2J-3 -GP

SM_RCOM P_0 SM_RCOM P_1 SM_RCOM P_2 SM_DRAM RST# DDR_PG_ CTRL

B B

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

CPU1B

PROC_DETECT# CATERR# PECI

PROCHOT#

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST# SM_PG_CNTL1

HASW ELL-6-GP

SM_DRAM RST#

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1D35V_S 3

12

R410

R410 470R2J-2 -GP

470R2J-2 -GP

R404

1 2

0R0402-P AD-2-GP

JTAG

2 OF 19

XDP_PRD Y#

J62

PRDY#

PREQ# PROC_TCK PROC_TMS

PROC_TRST#

PROC_TDI

PROC_TDO

BPM#0

BPM#1

BPM#2

BPM#3

BPM#4

BPM#5

BPM#6

BPM#7

Layout Note:

Place close to DIMM

XDP_PRE Q#

K62

XDP_TCL K

E60

XDP_TMS

E61

XDP_TRS T#

E59

XDP_TDI

F63

XDP_TDO

F62

XDP_BPM 0

J60

XDP_BPM 1

H60

XDP_BPM 2

H61

XDP_BPM 3

H62

XDP_BPM 4

K59

XDP_BPM 5

H63

XDP_BPM 6

K60

XDP_BPM 7

J61

DDR3_DR AMRST# [12,13]

XDP_PRD Y# [96] XDP_PRE Q# [96]

XDP_BPM [7:0]

XDP_BPM [7:0] [96]

XDP_TDO XDP_TDI

XDP_TMS

R402 51R2J-2-G P

XDP_TRS T# XDP_TCL K

R406 51R2J-2-G PR406 51R2J-2-G P

RN401

1 2 3

XDP

4 5

SRN51J-1 -GP

XDP

1 2 1 2

1D05S_V CCST

8 7 6

X01 change to short pad

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (THERMAL/CLOCK)

Size Document N umber Rev

Date: Sheet of

CPU (THERMAL/CLOCK)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

4 101Friday, June 28, 201 3

X02

5

S

SID = CPU

HSW

_ULT_DDR3L

CPU

CPU1C

M_A

_DQ[63:0][12]

D D

C C

_DQ[63:0]

M_A

_DQ0

M_A

_DQ1 _DQ2

M_A M_A

_DQ3

M_A

_DQ4 _DQ5

M_A M_A

_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQS7 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AH63 AH62

AK63

AK62 AH61 AH60

AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58 AR58 AM57

AK57

AL58

AK58 AR57 AN57

AP55 AR55 AM54

AK54

AL55

AK55 AR54 AN54

AY58 AW58

AY56 AW56

AV58 AU58

AV56 AU56

AY54 AW54

AY52 AW52

AV54 AU54

AV52 AU52

AK40

AK42 AM43 AM45

AK45

AK43 AM40 AM42 AM46

AK46 AM49

AK49 AM48

AK48 AM51

AK51

1C

SA_

DQ0

SA_

DQ1 DQ2

SA_ SA_

DQ3

SA_

DQ4 DQ5

SA_ SA_

DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

_ULT_DDR3L

DDR CHANNEL A

4

3 O

3 OF 19

F 19

SA_

CLK#0

SA_

CLK0

CLK#1

SA_

CLK1

CKE0

SA_ SA_

CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS#

SA_WE#

SA_CAS#

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

+V_SM_VREF_CNT

_DIMA_CLK_DDR#0 [12]

M_A M_A

_DIMA_CLK_DDR0 [12]

M_A

_DIMA_CLK_DDR#1 [12] _DIMA_CLK_DDR1 [12]

M_A

_DIMA_CKE0 [12] _DIMA_CKE1 [12]

M_A

M_A_DIMA_CS#0 [12] M_A_DIMA_CS#1 [12]

TP_M_A_DIMA_ODT0

M_A_RAS# [12]

M_A_WE# [12]

M_A_CAS# [12]

M_A_BS0 [12] M_A_BS1 [12] M_A_BS2 [12]

3

TP501TP501

1

M_A_A[15:0] [12]

M_A_DQS#[7:0] [12]

M_A_DQS[7:0] [12]

+V_SM_VREF_CNT [37] DDR_WR_VREF01 [12] DDR_WR_VREF02 [13]

2

HSW

_ULT_DDR3L

CPU

1D

_DQ[63:0]

_DQ[63:0][13]

M_B

_DQ0 _DQ1

M_B M_B

_DQ2

M_B

_DQ3 _DQ4

M_B M_B

_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AY31

AW31

AY29

AW29

AV31

AU31

AV29

AU29

AY27

AW27

AY25

AW25

AV27

AU27

AV25 AU25 AM29

AK29

AL28

AK28 AR29 AN29 AR28

AP28 AN26 AR26 AR25

AP25

AK26 AM26

AK25

AL25

AY23 AW23

AY21 AW21

AV23 AU23

AV21 AU21

AY19 AW19

AY17 AW17

AV19 AU19

AV17 AU17 AR21 AR22

AL21 AM22 AN22

AP21

AK21

AK22 AN20 AR20

AK18

AL18

AK20 AM20 AR18

AP18

SB_

DQ0 DQ1

SB_ SB_

DQ2

SB_

DQ3 DQ4

SB_ SB_

DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

_ULT_DDR3L

DDR CHANNEL B

4 O

SB_

CK#0

SB_

CK#1

SB_

CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS#

SB_WE#

SB_CAS#

SB_BA0 SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

F 19

AM38 AN38

CK0

AK38 AL38

CK1

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

TP_M_B_DIMB_ODT0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

1

M_B M_B M_B M_B

M_B M_B_DIMB_CKE1 [13]

M_B_DIMB_CS#0 [13] M_B_DIMB_CS#1 [13]

M_B_RAS# [13]

M_B_WE# [13]

M_B_CAS# [13]

_DIMB_CLK_DDR#0 [13] _DIMB_CLK_DDR0 [13] _DIMB_CLK_DDR#1 [13] _DIMB_CLK_DDR1 [13]

_DIMB_CKE0 [13]

TP503TP503

1

M_B_BS0 [13] M_B_BS1 [13] M_B_BS2 [13]

M_B_A[15:0] [13]

M_B_DQS#[7:0] [13]

M_B_DQS[7:0] [13]

B B

HASWELL-6-GP

A A

5

4

3

HASWELL-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDR)

Hadley 15"

1

X02

5 101Friday, June 28, 2013

X02

5

4

3

2

1

SSI

D D

C C

= CPU

D

CFG

HSW_ULT_DDR3L

CPU

S

1

[

19:0]

[

19:0][96]

CFG

1 2

R601

R601 49D9R2F -GP

49D9R2F -GP

1 2

R603

R603 8K2R2F-1 -GP

8K2R2F-1 -GP

0

CFG CFG

1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCO MP

TD_IREF

CFG3

A

C60 AC62 AC63 AA63 AA60

Y62

Y61

Y60

V62

V61

V60

U60

T63

T62

T61

T60

AA62

U63 AA61

U62

V63

H18

B12

A5

E1 D1

J20

0

CFG CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

CFG_RCOMP

RSVD#A5

RSVD#E1 RSVD#D1 RSVD#J20 RSVD#H18 TD_IREF

12

DY

R604

R604 1KR2J-1-G P

1KR2J-1-G P

HSW_ULT_DDR3L

RESERVED

PHYSICAL_DEBUG_ ENABLED (DFX P RIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

19

D

_TP#AV63

RSV RSVD_TP#AU63

RSVD_TP#C63 RSVD_TP#C62

RSVD#B43

RSVD_TP#A51 RSVD_TP#B51

RSVD_TP#L60

RSVD#N60

RSVD#W23

RSVD#Y22

PROC_OPI_RCOMP

RSVD#AV62

RSVD#D58

VSS VSS

RSVD#P20 RSVD#R20

F 19

O

AV63 AU63

C63 C62

EDP_SPA RE

B43

A51 B51

L60

N60

W23

PROC_OP I_COMP3

Y22

PROC_OP I_COMP

AY15

AV62 D58

P22 N21

HVM_CLK #

P20

HVM_CLK

R20

1

TP605TP605

R606 49D9R2F -GP

1 2

DY

R602 49D9R2F -GPR602 49D9R2F -GP

1 2

1

TP619TP619

1

TP620TP620

Layout Note:

1.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3.Trace width: 12~15mil

4.Isolation Spacing: 12mil

5.Max length: 500mil

1 : DISABLED

CFG4

B B

A A

5

4

12

R605

R605 1KR2J-1-G P

1KR2J-1-G P

DISPLAY PORT PR ESENCE STRAP

0 : ENABLED AN EXTERNAL DIS PLAY PORT DEVI CE IS CONNECTED TO THE EMBEDD ED DISPLAY PORT

CFG[4]

1 : DISABLED

NO PHYSICAL DIS PLAY PORT ATTA CHED TO EMBEDDE D DISPLAY PORT

3

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (RESERVED)

Hadley 15"

6 101Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

1D05S_V CCST

R703 75R2F-2-G PR703 75R2F-2-G P

1 2

R704 130R2F-1 -GPR704 130R2F-1 -GP

1 2

C C

1D05V_V TT_PWRGD[36,48]

EC701

SCD1U25V2KX-GP

12

DY

B B

VR_SVID_A LERT#

H_CPU_S VIDDAT

SCD1U10 V2KX-5GP

U701

1

NC#1

2

A

DY

GND3Y

74LVC1G 07GW-GP

73.01G07.0HG

1 2

R707

R707 100KR2F -L1-GP

100KR2F -L1-GP

VCC

C702

DY

5

4

12

4

3D3V_S5

1D05S_V CCST

12

R709

R709 51KR2J-1 -GP

51KR2J-1 -GP

12

R706

R706 10KR2J-3 -GP

10KR2J-3 -GP

DY

H_VCCST _PWRGD

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

H_VR_EN ABLE[46]

C705

SCD1U25 V2KX-GP

1D05S_V CCST

VR_SVID_A LERT#[46] H_CPU_S VIDCLK[46] H_CPU_S VIDDAT[46]

1 2

3

100R2F-L 1-GP-U

VCC_SEN SE[46]

IMVP_PW RGD_R

DY

R705 150R2J-L 1-GP-UR 705 150 R2J-L1-GP-U

1 2

VCC_COR E

R702

1 2

12

TP701TP701

R701

43R2J-GP

1 2

H_CPU_S VIDCLK H_CPU_S VIDDAT H_VCCST _PWRGD

DY

1D35V_S 3

VCC_COR E

1

+VCCIOA_OU T

H_CPU_S VIDALRT#

10KR2J-3 -GP

10KR2J-3 -GP R710

R710

PWR_ DEBUG

1D05S_V CCST

VCC_COR E

TP_VCCIO_ OUT

L59

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

F59 N58

AC58

E63

AB23

A59

E20 AD23 AA23 AE59

L62

N63

L63

B59

F60

C59

D63

H59

P62

P60

P61

N59

N61

T59 AD60 AD59 AA59 AE60 AC59 AG58

U59

V59

AC22 AE22 AE23

AB57 AD57 AG57

C24

C28

C32

J58

2

CPU

1L

RSVD#L59 RSVD#J58

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD#N58 RSVD#AC58

VCC_SENSE RSVD#AB23 VCCIO_OUT VCCIOA_OUT RSVD#AD23 RSVD#AA23 RSVD#AE59

VIDALERT# VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG# VSS RSVD_TP#P60 RSVD_TP#P61 RSVD_TP#N59 RSVD_TP#N61 RSVD#T59 RSVD#AD60 RSVD#AD59 RSVD#AA59 RSVD#AE60 RSVD#AC59 RSVD#AG58 RSVD#U59 RSVD#V59

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

HASW ELL-6-GP

HSW

_ULT_DDR3L

HSW ULT POWER

1

_CORE

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

VCC

12

OF 19

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

A00 0619

H_VR_EN ABLE

PR714

1D05S_V CCST1D05V_S 0

1 2

R711

0R0805-P AD-2-GP-U

A A

5

DY

12

C701

C703

DY

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

4

IMVP_PW RGD[24,46]

1 2

R713

R713 100KR2F -L1-GP

100KR2F -L1-GP

47KR2F-G P

IMVP_PW RGD_L IMVP_PWR GD_R

C704

SCD1U25V2KX-GP

12

R712

DY

3

1 2

0R2J-2-GP

PD701

DY

BAT54LP S-7-GP

KA

12

PR715

DY

10KR2F-2 -GP

12

PC706

DY

SCD047U 10V2KX-2GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Hadley 15"

7 101Friday, June 28, 201 3

1

X02

D = CPU

SSI

5

4

3

2

1

D D

HSW_ULT_DDR3L

X01 remove

CPU1A

HSW_ULT_DDR3L

1 OF 19

HDMI_DATA 2#[54]

HDMI_DATA 2[54]

HDMI

HDMI_DATA 1#[54]

HDMI_DATA 1[54]

HDMI_DATA 0#[54]

HDMI_DATA 0[54]

HDMI_CLK#[54]

HDMI_CLK[54]

C C

C54 C55

B58

C58

B55 A55 A57 B57

C51 C50 C53

B54

C49

B50 A53 B53

HASW ELL-6-GP

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

EDPDDI

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_TX0 _DN [53] EDP_TX0 _DP [53] EDP_TX1 _DN [53] EDP_TX1 _DP [53]

EDP_AUX _DN [5 3] EDP_AUX _DP [53]

EDP_COM P EDP_BRIGHT NESS

R801

24D9R2F -L-GP

1

TP801TP801

+VCCIOA_OU T

Design Guidelin e:

12

EDP_COMP keep r outing length max 100 mils. Trace Width:20 mils.

B B

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (DDI/EDP)

Hadley 15"

8 101Friday, June 28, 201 3

X02

5

SSI

D = CPU

D D

C C

B B

4

CPU1P

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61

G18 G22

G3

G5

G6

G8 H13

HASW ELL-6-GP

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HSW_ULT_DDR3L

16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS_SENSE

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

3

VSS_SEN SE

2

VSS_SEN SE [46]

12

R901

100R2F-L1-GP-U

Layout Note:

1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE impedance=50 ohm

3. Lwngth match<25mil

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)

Size Document N umber Rev

A3

Date: Sheet of

CPU (VSS)

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

9 101Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

1D3

5V_S3

D D

SC10U6D3V3MX-GP

C10

12

01

17

12

C10

SC2D2U6D3V2MX-GP

C C

C1003

C1002

C1018

DY

SC2D2U6D3V2MX-GP

12

C1019

DY

SC2D2U6D3V2MX-GP

C1005

C1004

12

C1020

SC2D2U6D3V2MX-GP

C1006

12

DY

Layout Note:

Direct tie to CPU VccIn/Vss balls

4

SC10U6D3V3MX-GP

Layout Note:

As close to CPU as possible

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP1)

Hadley 15"

10 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

4

3

2

1

MAX: 1.92A

1.838A 41mA 42mA

1D05V_H SIO +V1.05DX _MODPHY_PCH

1 2

R1101

0R0805-P AD-2-GP-U

12

SC1U6D3V2KX-GP

C1101

C1102

12

L1101 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

C1103

12

+V1.05S_ AUSB3PLL

SC1U6D3V2KX-GP

SC10U6D3V3MX-GP

C1104

12

+V1.05S_ AUSB3PLL1D05V_H SIO

SC10U6D3V3MX-GP

C1123

12

DY

1D05V_H SIO +V1.05S_ ASATA3PLL

L1102 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

SC1U6D3V2KX-GP

C1105

12

+V1.05S_ ASATA3PLL

SC10U6D3V3MX-GP

C1106

C1107

DY

C1107

12

SC10U6D3V3MX-GP

CAP need close to pin K9 L10

C C

1 2

R1102

0R0603-P AD-2-GP-U

+V1.05S_ APLLOPI

SC1U6D3V2KX-GP

C1109

12

SC10U6D3V3MX-GP

C1110

CAP need close to pin AA21 CAP need close to pin AC9 CAP need close to pin J18

CAP need close to pin B18 CAP need close to pin B11

+V1.05S_ APLLOPI1D05V_S 0

SC10U6D3V3MX-GP

C1124

12

DY

3D3V_S5 _PCH +V3.3A_P SUS

1 2

R1103

0R0603-P AD-2-GP-U

1205 Add

SC10U6D3V3MX-GP

C1108

12

1D05V_S 0 +V1.05S_ AXCK_DCB

L1103 IND-2 D2UH-196-GP

1 2

68.2R21D.10R

1205 Add

200mA62mA57mA

+V1.05S_ AXCK_DCB

SC10U6D3V3MX-GP

SC1U6D3V2KX-GP

C1112

C1111

12

DY

SC10U6D3V3MX-GP

C1125

12

1205 Add

31mA 658mA 1.632A 1mA

IND-2D2UH-1 96-GP

IND-2D2UH-1 96-GP L1104

L1104

1 2

68.2R21D.10R

B B

+V1.05S_ AXCK_LCPLL1D05V_S 0

SC1U6D3V2KX-GP

C1113

C1114

12

DY

CAP need close to pin A20 CAP need close to pin AE9 CAP need close to pin AE8 J11

1D05V_S 0 +1.05M_A SW 1D05V_S0

1 2

R1104

0R0603-P AD-2-GP-U

SC10U6D3V3MX-GP

0R0603-P AD-2-GP-U

SC22U6D3V5MX-2GP

C1115

12

DY

RTC_AUX _S5

SC1U6D3V2KX-GP

C1116

12

SC1U6D3V2KX-GP

C1117

C1118

12

SC10U6D3V3MX-GP

C1119

12

DY

SCD1U10V2KX-5GP

C1120

12

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C1122

C1121

12

CAP need close to pin AG10

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU(Power CAP2)

Hadley 15"

11 10 1Friday, June 28, 201 3

1

X02

5

S

SID = MEMORY

M_A

_A[15:0][5]

D D

M_A_BS2[5]

M_A_BS0[5] M_A_BS1[5]

M_A_DQ[63:0][5]

12

DY

C1202

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

12

DY

C1206

SCD1U10V2KX-5GP

16

C12

SC1U6D3V2KX-GP

M_A_DQS#[7:0][5]

M_A_DQS[7:0][5]

DDR3_DRAMRST#[4,13]

Layout Note:

Place these caps close to VREF_CA

Layout Note:

Place these caps close to VTT1 and VTT2.

M_VREF_CA_DIMMA M_VREF_DQ_DIMMA

C1217

SCD1U10V2KX-5GP

DY

M_VREF_CA_DIMMA

12

DY

01

18

C12

SCD1U10V2KX-5GP

C C

M_VREF_DQ_DIMMA

12

04

C12

0D675V_S0

14

12

C12

B B

A A

SC1U6D3V2KX-GP

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

SCD1U10V2KX-5GP

05

12

C12

DY

SC2D2U6D3V2MX-GP

SCD1U10V2KX-5GP

15

12

C12

DY

SC1U6D3V2KX-GP

M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A M_A_A13 M_A_A14 M_A_A15

M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ15 M_A_DQ11 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ31 M_A_DQ25 M_A_DQ24 M_A_DQ27 M_A_DQ26 M_A_DQ44 M_A_DQ41 M_A_DQ43 M_A_DQ47 M_A_DQ45 M_A_DQ40 M_A_DQ42 M_A_DQ46 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ7 M_A_DQ21 M_A_DQ20 M_A_DQ17 M_A_DQ16 M_A_DQ18 M_A_DQ19 M_A_DQ22 M_A_DQ23 M_A_DQ36 M_A_DQ33 M_A_DQ34 M_A_DQ38 M_A_DQ37 M_A_DQ32 M_A_DQ35 M_A_DQ39 M_A_DQ62 M_A_DQ58 M_A_DQ60 M_A_DQ61 M_A_DQ63 M_A_DQ59 M_A_DQ56 M_A_DQ57

M_A_DQS#1 M_A_DQS#3 M_A_DQS#5 M_A_DQS#6 M_A_DQS#0 M_A_DQS#2 M_A_DQS#4 M_A_DQS#7

M_A_DQS1 M_A_DQS3 M_A_DQS5 M_A_DQS6 M_A_DQS0 M_A_DQS2 M_A_DQS4 M_A_DQS7

M_A_DIMA_ODT0 M_A_DIMA_ODT1

0D675V_S0

12

_A0 _A1 _A2 _A3 _A4 _A5 _A6 _A7 _A8 _A9 _A10 _A11 _A12

close to dimm

5

4

DM1

8

9

A

0

9

7

1

A

6

9

A

2

5

9

A

3

9

2

4

A

9

1

5

A

0

9

A

6

8

A

7

8

9

8

A

5

8

A

9

107

A10

/AP

4

8

A11

8

3

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

D

DR3-204P-122-GP-U1

62.10017.Z51

4

RAS

WE#

CAS

CS0 CS1

CKE CKE

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

N

P1

NP1

P2

N

NP2

110

#

13

1 115

#

114

#

121

#

73

0

74

1

101

CK0

103

102

CK1

104

11 28 46 63 136 153 170 187

200

SDA

202

SCL

198

199

SA0_DIMA

197

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SA1_DIMA

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D35V_S3

M_A

_RAS# [5] _WE# [5]

M_A M_A

_CAS# [5]

M_A

_DIMA_CS#0 [5]

M_A

_DIMA_CS#1 [5]

M_A

_DIMA_CKE0 [5]

M_A

_DIMA_CKE1 [5]

M_A_DIMA_CLK_DDR0 [5] M_A_DIMA_CLK_DDR#0 [5]

M_A_DIMA_CLK_DDR1 [5] M_A_DIMA_CLK_DDR#1 [5]

PCH_SMBDATA [13,18,58,62,67] PCH_SMBCLK [13,18,58,62,67]

C1203

SCD1U10V2KX-5GP

1D35V_S3

Layout Note:

Place these Caps near SO-DIMMA.

X01 change to short pad

DDR_PG_CTRL[4]

1 2

Q1201 Need check Vth=1V

3

3D3V_S0

12

DY

12

0R0402-PAD-2-GP

R1205

0R0402-PAD-2-GP

C1207

12

DY

12

C1211

C1210

SCD1U10V2KX-5GP

DDR_PG_CTRL_R

SA0

_DIMA

SA1

_DIMA

12

02

R12

C1208

SC10U6D3V3MX-GP

12

C1212

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1D35V_S3

Q1201

Q1201 DMN5L06K-7-GP

DMN5L06K-7-GP

84.05067.031

C1209

SC10U6D3V3MX-GP

C1213

SC1U6D3V2KX-GP

G

01

R12

R12 0R0402-PAD-2-GP

0R0402-PAD-2-GP

12

C1220

SCD1U10V2KX-5GP

DS

12

C1221

5V_S5

DY

12

C1222

SCD1U10V2KX-5GP

12

R1208

R1208 220KR2J-L2-GP

220KR2J-L2-GP

DDR_VTT_PG_CTRL

12

R1204

R1204 2MR2-GP

2MR2-GP

2

e:

Not SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF01[5]

SCD1U10V2KX-5GP

1D35V_S3

D

Q1202

Q1202 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

2

M_A_B_DIMM_ODT

1

1D35V_S30D675V_VTTREF

12

R1215

0R2J-2-GP

DY

2R2F-GP

2R2F-GP R1210

R1210

1 2

12

C1219

C1219 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH1

12

R1212

R1212 24D9R2F-L-GP

24D9R2F-L-GP

DDR_VTT_PG_CTRL [49]

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

R1211

R1211 1K8R2F-GP

1K8R2F-GP

12

R1213

R1213 1K8R2F-GP

1K8R2F-GP

R1206 66D5R2F-GPR1206 66D5R2F-GP

1 2

R1207 66D5R2F-GPR1207 66D5R2F-GP

1 2

R1203 66D5R2F-GPR1203 66D5R2F-GP

1 2

R1209 66D5R2F-GPR1209 66D5R2F-GP

1 2

DDR3L-SODIMM1

Hadley 15"

Friday, June 28, 2013

Hadley 15"

M_A_DIMA_ODT0

M_A_DIMA_ODT1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

M_VREF_DQ_DIMMA

M_B_DIMB_ODT0 [13]

M_B_DIMB_ODT1 [13]

12 101

X02

5

S

SID = MEMORY

M_B

_A[15:0] [5]

D D

M_B_BS2[5]

M_B_BS0[5] M_B_BS1[5]

12

DY

12

DY

12

C1318

M_B_DQ[63:0][5]

Layout Note:

Place these caps close to VREF_CA

C1302

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VREF_DQ

C1306

SCD1U10V2KX-5GP

Layout Note:

Place these caps close to VTT1 and VTT2.

SC1U6D3V2KX-GP

M_B_DQS#[7:0] [5]

M_B_DQS[7:0] [5]

M_B_DIMB_ODT0[12] M_B_DIMB_ODT1[12]

M_VREF_CA_DIMMB M_VREF_DQ_DIMMB

DDR3_DRAMRST#[4,12]

C1319

SCD1U10V2KX-5GP

12

DY

M_VREF_CA_DIMMB

12

01

DY

C C

M_VREF_DQ_DIMMB

12

0D675V_S0

B B

A A

12

DY

Layout Note:

All VREF traces should have width=20mil; spacing=20 mil

302

C13

EC1

SCD1U10V2KX-5GP

05

12

C13

04

DY

C13

SC2D2U6D3V2MX-GP

SCD1U10V2KX-5GP

17

16

12

C13

SC1U6D3V2KX-GP

close to dimm

5

_A0

M_B

_A1

M_B M_B

_A2

M_B

_A3 _A4

M_B M_B

_A5

M_B

_A6 _A7

M_B M_B

_A8

M_B

_A9 _A10

M_B M_B

_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ8 M_B_DQ14 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ9 M_B_DQ13 M_B_DQ15 M_B_DQ28 M_B_DQ29 M_B_DQ26 M_B_DQ27 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ40 M_B_DQ41 M_B_DQ46 M_B_DQ42 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ43 M_B_DQ56 M_B_DQ57 M_B_DQ59 M_B_DQ58 M_B_DQ61 M_B_DQ60 M_B_DQ63 M_B_DQ62 M_B_DQ4 M_B_DQ1 M_B_DQ3 M_B_DQ7 M_B_DQ5 M_B_DQ0 M_B_DQ2 M_B_DQ6 M_B_DQ21 M_B_DQ20 M_B_DQ22 M_B_DQ23 M_B_DQ16 M_B_DQ17 M_B_DQ19 M_B_DQ18 M_B_DQ36 M_B_DQ33 M_B_DQ35 M_B_DQ39 M_B_DQ37 M_B_DQ32 M_B_DQ34 M_B_DQ38 M_B_DQ52 M_B_DQ49 M_B_DQ48 M_B_DQ53 M_B_DQ51 M_B_DQ55 M_B_DQ54 M_B_DQ50

M_B_DQS#1 M_B_DQS#3 M_B_DQS#5 M_B_DQS#7 M_B_DQS#0 M_B_DQS#2 M_B_DQS#4 M_B_DQS#6

M_B_DQS1 M_B_DQS3 M_B_DQS5 M_B_DQS7 M_B_DQS0 M_B_DQS2 M_B_DQS4 M_B_DQS6

0D675V_S0

4

DM2

9

8

0

A

7

9

A

1

6

9

A

2

9

5

3

A

9

2

4

A

1

9

A

5

0

9

A

6

8

6

7

A

9

8

A

8

5

8

A

9

107

/AP

A10

8

4

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

SKT_DDR 204P SMD

D

DR3-204P-122-GP-U1

62.10017.Z51

4

RAS

WE#

CAS

CS0 CS1

CKE CKE

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

P1

N

NP1

N

P2

NP2

110

#

13

1 115

#

114

#

121

#

73

0

74

1

101

CK0

103

102

CK1

104

11 28 46 63 136 153 170 187

200

SDA

202

SCL

198

199

197

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SA1_DIMB

201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

1D35V_S3

3

_RAS# [5]

M_B M_B

_WE# [5]

M_B

_CAS# [5]

M_B

_DIMB_CS#0 [5]

M_B

_DIMB_CS#1 [5]

M_B

_DIMB_CKE0 [5] _DIMB_CKE1 [5]

M_B

M_B_DIMB_CLK_DDR0 [ 5] M_B_DIMB_CLK_DDR#0 [5]

M_B_DIMB_CLK_DDR1 [ 5] M_B_DIMB_CLK_DDR#1 [5]

PCH_SMBDATA [12,18,58,62,67] PCH_SMBCLK [12,18,58,62,67]

DY

C1303

SCD1U10V2KX-5GP

1D35V_S3

12

DY

12

Layout Note:

Place these Caps near SO-DIMMA.

3

3D3V_S0

12

C1312

C1311

SC10U6D3V3MX-GP

12

DY

12

C1314

C1313

SCD1U10V2KX-5GP

2

Not

e: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

3D3V_S0

12

R1301

R1301 10KR2J-3-GP

10KR2J-3-GP

SA1_DIMB

SA0_DIMBSA0_DIMB

12

R1302

R1302 0R0402-PAD-2-GP

0R0402-PAD-2-GP

Layout Note:

Place Close SO-DIMMA.

DDR_WR_VREF02[5]

C1307

C1308

C1310

SC10U6D3V3MX-GP

12

DY

12

C1315

DY

SCD1U10V2KX-5GP

C1308

C1309

SC10U6D3V3MX-GP

12

EC1301

SCD1U10V2KX-5GP

SC10U6D3V3MX-GP

12

2

0D675V_VTTREF

R1308

0R2J-2-GP

2R2F-GP

2R2F-GP R1304

R1304

1 2

12

C1320

C1320 SCD022U16V2JX-GP

SCD022U16V2JX-GP

+V_VREF_PATH2

12

R1307

R1307 24D9R2F-L-GP

24D9R2F-L-GP

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

1D35V_S3

12

DY

Friday, June 28, 2013

1

12

R1306

R1306 1K8R2F-GP

1K8R2F-GP

12

DDR3L-SODIMM2

Hadley 15"

M_VREF_DQ_DIMMB

R1303

R1303 1K8R2F-GP

1K8R2F-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

13 101

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

M1&M3

Hadley 15"

14 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

C C

RN1504

4

OPS

SRN10KJ -5-GP

100KR2J -1-GP

100KR2J -1-GP R1509

R1509

DGPU_PW R_EN DGPU_HO LD_RST#

DGPU_PW ROK

1 2 3

1 2

4

0R0402-P AD-2-GP

L_BKLT_ CTRL_R

R1501

L_BKLT_ CTRL[53 ] L_BKLT_ EN[24]

EDP_VDD _EN[52]

A00 change to PIRQB#

HDD_FAL L_INT[67]

DGPU_PW R_EN[82,83] DGPU_HO LD_RST#[73]

DGPU_PW ROK[24,82,83]

1 2

0R0402-P AD-2-GP

0R0402-P AD-2-GP R1503

R1503

1 2

TP1501TP1501

TP1503TP1503

TP1502TP1502

1

MCP_GPIO55

1

DGPU_PW R_EN DGPU_HO LD_RST# DGPU_PW ROK

PCH_SD_ CD#

1

PIRQA# PIRQB# PIRQC# PIRQD# PCI_PME#

3

AD4

CPU1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA#/GPIO77

P4

PIRQB#/GPIO78

N4

PIRQC#/GPIO79

N2

PIRQD#/GPIO80 PME#

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

DISPLAY

2

9 OF 19

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD

DDPC_HPD

EDP_HPD

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

3D3V_S0

1

23

4

RN1501

RN1501 SRN2K2J -1-GP

SRN2K2J -1-GP

PCH_HDM I_CLK [54] PCH_HDM I_DATA [54]

HDMI_PCH_D ET [54]

EDP_HPD [52,53 ]

1

3D3V_S0

B B

A A

5

RN1505

8 7 6

SRN10KJ -6-GP

PIRQD#

1

PIRQC#

2

PIRQB#

3

PIRQA#

45

4

3

HASW ELL-6-GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU ( EDP SIDEBAND/GPIO/DDI )

Size Document N umber Rev

A3

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

X02

15 10 1Friday, June 28, 201 3

1

X02

SSI

D = CPU

5

4

3

2

1

D D

PCIE Table

Port

1

2

3

4

5(4lane)

6(4lane)

C C

B B

Device

N/A

WLAN

LAN+ Card reader

GPU

N/A

Share BUS

USB3.0_3

USB3.0_4

SATA0~3

CPU_RXN _C_dGPU_TXN0[73] CPU_RXP _C_dGPU_TXP0[73]

dGPU_RX N_C_CPU_TXN0[73] dGPU_RX P_C_CPU_TXP0[73]

CPU_RXN _C_dGPU_TXN1[73] CPU_RXP _C_dGPU_TXP1[73]

dGPU_RX N_C_CPU_TXN1[73] dGPU_RX P_C_CPU_TXP1[73]

CPU_RXN _C_dGPU_TXN2[73] CPU_RXP _C_dGPU_TXP2[73]

dGPU_RX N_C_CPU_TXN2[73] dGPU_RX P_C_CPU_TXP2[73]

CPU_RXN _C_dGPU_TXN3[73] CPU_RXP _C_dGPU_TXP3[73]

dGPU_RX N_C_CPU_TXN3[73] dGPU_RX P_C_CPU_TXP3[73]

PCIE_PRX_ WLANTX_N3[58] PCIE_PRX_ WLANTX_P3[58 ]

PCIE_PTX_ WLANRX_N3 _C[58] PCIE_PTX_ WLANRX_P3 _C[58]

PCIE_PRX_ LANTX_N4[30] PCIE_PRX_ LANTX_P4[30]

PCIE_PTX_ LANRX_N4_C[30] PCIE_PTX_ LANRX_P4_C[30]

USB3_PR X_DTX_N2[63] USB3_PR X_DTX_P2[63]

USB3_PT X_DRX_N2[63] USB3_PT X_DRX_P2[63]

USB3_PR X_DTX_N3[63] USB3_PR X_DTX_P3[63]

USB3_PT X_DRX_N3[63] USB3_PT X_DRX_P3[63]

+V1.05S_ AUSB3PLL

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1606

C1606

1 2

OPS

1 2

OPS

C1605

C1605 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1608

C1608

1 2

OPS

1 2

OPS

C1607

C1607 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1610

C1610

1 2

OPS

1 2

OPS

C1609

C1609 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1612

C1612

1 2

OPS

1 2

OPS

C1611

C1611 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1601

C1601

1 2 1 2

C1602

C1602 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP C1603

C1603

1 2 1 2

C1604

C1604 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

R1601

3KR2F-GP

1 2

Layout Note:

1. PCIE_RCOMP/ PCIE_IREF trac e width=12~15mi l

2. Isolation Sp acing: 12mil

3. Total trace length<500mil

dGPU_RX N_CPU_TXN0

dGPU_RX P_CPU_TXP0

dGPU_RX N_CPU_TXN1

dGPU_RX P_CPU_TXP1

dGPU_RX N_CPU_TXN2

dGPU_RX P_CPU_TXP2

dGPU_RX N_CPU_TXN3

dGPU_RX P_CPU_TXP3

PCIE_PTX_ WLANRX_N3 PCIE_PTX_ WLANRX_P3

PCIE_PTX_ LANRX_N4 PCIE_PTX_ LANRX_P4

PCIE_RCOM P

CPU

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD#E15

E13

RSVD#E13

A27

PCIE_RCOMP

B27

PCIE_IREF

1K

WLAN

LAN+Card reader

HASW ELL-6-GP

HSW

_ULT_DDR3L

PCIE USB

11

OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7 USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS#

USBRBIAS RSVD#AN10 RSVD#AM10

OC0/GPIO40# OC1/GPIO41# OC2/GPIO42# OC3/GPIO43#

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USB_PN7 USB_PP7

USB_COM P

USB_OC# 0_1 USB_OC# 2_3 USB_OC# 4_5 USB_OC# 6_7

1 1

USB_PN0 [34] USB_PP0 [34 ]

USB_PN1 [35] USB_PP1 [35 ]

USB_PN2 [63] USB_PP2 [63 ]

USB_PN3 [63] USB_PP3 [63 ]

USB_PN4 [52] USB_PP4 [52 ]

USB_PN5 [58] USB_PP5 [58 ]

USB_PN6 [52] USB_PP6 [52 ]

TP1602TP1602 TP1601TP1601

1 2

R1602

R1602 22D6R2F -L1-GP

22D6R2F -L1-GP

USB_OC# 0_1 [3 5] USB_OC# 2_3 [3 5]

USB 2.0 Table

Pai

0

1

2

3

4

5

6

7

USB3_PR X_CTX_N0 [34] USB3_PR X_CTX_P0 [34]

USB3_PT X_CRX_N0 [34] USB3_PT X_CRX_P0 [34]

USB3_PR X_CTX_N1 [34] USB3_PR X_CTX_P1 [34]

USB3_PT X_CRX_N1 [34] USB3_PT X_CRX_P1 [34]

1. USB_COMP usi ng 50 ohm

2. Isolation Sp acing :15mil

3. Total trace length<500mil

USB_OC# 0_1 USB_OC# 2_3 USB_OC# 4_5 USB_OC# 6_7

Dev

r

ice

USB3.0 Port2

USB3.0 port1 (with Power Share)

USB3.0 Port3

USB3.0 Port4

CAMERA

WL

N

A

Touch Panel

N/A

Layout Note:

single-ended i mpedance

3D3V_S5 _PCH

RN1601

1

8

2

7

3

6

4 5

SRN10KJ -6-GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PCIE/USB)

Hadley 15"

16 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

RN1

703

1

4

2 3

SRN10KJ -5-GP

1 2

DY

R1717 10KR2J -3-GP

3D3V_S0

RN1704

1 2 3

SRN8K2J -3-GP

C C

B B

XDP_DBR ESET#

4

PM_CLKR UN#

SYS_PW ROK[24,96] PCH_PW ROK[24,26,36]

PM_PW RBTN#[24,96] AC_PRES ENT[24,76 ]

PCH_SLP _S0#[48] PM_SLP_ SUS# [24,38]

3D3V_S5

3D3V_S5 _PCH

PM_

RSMRST#

PM_PCH_ PWROK

SYS_PW ROK

R1706 0R0402-PAD -2-GPR1706 0R0402-PAD -2-GP

1 2

PLT_RST #[24,30,58,6 5,73]

100KR2J -1-GP

RN1701

1

4

2 3

SRN10KJ -5-GP

1 2

DY

R1724 10KR2J-3 -GP

1 2

R1727 10KR2J-3 -GPR1727 10KR2J-3-GP

0R0402-P AD-2-GP

TP1705TP1705

R1715

DY

BATLOW # AC_PRES ENT

PM_SUS_ STAT#

PM_SUSW ARN#

R1707

1 2

12

DY

4

PM_SUSA CK#_R

XDP_DBR ESET# SYS_PW ROK PM_PCH_ PWROK MPWR OK PCI_PLTRS T#

PM_RSMR ST#

PM_SUSW ARN#_R

PM_PW RBTN# AC_PRES ENT BATLOW # PCH_SLP _S0#

R1713

PCH_SLP _WLAN#

PCI_PLTRS T#

PM_SUSA CK#[2 4]

PM_SUSW ARN#[24 ]

1

0R0402-P AD-2-GP

1 2

C1701

C1701 SC220P5 0V2KX-3GP

SC220P5 0V2KX-3GP

CPU1H

AK2

SUSACK#

AC3

SYS_RESET#

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST#

AW6

RSMRST#

AV4

SUSWARN#/SUSPWRDNACK#/GPIO30

AL7

PWRBTN#

AJ8

ACPRESENT/GPIO31

AN4

BATLOW#/GPIO72

AF3

SLP_S0#

AM5

SLP_WLAN#/GPIO29

HASW ELL-6-GP

RN

A00 0618

1

4

2 3

0R4P2R-P AD

RN1702

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

PM_SUSA CK#_R PM_SUSW ARN#_R

3D3V_AU X_S5

R1726

R1726 10KR2J-3 -GP

10KR2J-3 -GP

1 2

3

8 OF 19

DPWROK

WAKE#

SLP_S4# SLP_S3#

SLP_A#

SLP_SUS#

SLP_LAN#

AW7 AV5 AJ5

V5 AG4 AE6 AP5

AJ6 AT4 AL5 AP4 AJ7

PCH_DPW ROK

PM_RSMR ST#

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

NON DS3

1 2

R1708

R1708 100KR2J -1-GP

100KR2J -1-GP

Q1701

5

6

2N7002K DW-GP

34

2

1

3V_5V_P OK# 3V_5V_P OK_C

2

Die DSW VR Enable

On

= Disable

DSW

ODVREN

DSWO DVREN PCH_DPW ROK PM_RS MRST#

PCH_W AKE#

PM_CLKR UN# PM_SUS_ STAT# SUS_CLK PM_SLP_ S5#

PM_SLP_ S4# PM_SLP_ S3# PM_SLP_ A# PM_SLP_ SUS# PM_SLP_ LAN#

R1703 1KR2J-1-GPR1 703 1KR2J-1-G P

1

Low High = Enable (default)

*

NON DS3

0R2J-2-GP

0R2J-2-GP R1704

R1704

1 2 1 2

0R0402-P AD-2-GP

R1709

1 2

TP1702TP1702 R1710

R1710

1 2

TP1703TP1703

0R0402-P AD-2-GP

TP1704TP1704

TP1707TP1707

A00 0618

PM_SLP_ S4# [24,49]

PM_SLP_ S3# [24,36,48,49,5 1]

A00 0618

R1718

1 2

0R0402-P AD-2-GP

R1725

100KR2F -L1-GP

1KR2J-1-G P

1KR2J-1-G P R1702

R1702

1 2

R1728

1 2

0R2J-2-GP

NON DS3

1 2

R1729

0R0402-P AD-2-GP

12

DS3

RSMRST# _KBC [2 4]

3V_5V_P OK [45]

PM_SLP_ SUS#

3D3V_S5

0311 PCH WAKE# pin PH 1K

PM_CLKR UN#_EC [24]

PCH_SUS CLK_KBC [24 ]

KBC_DPW ROK [2 4]

PCH_SUS CLK_KBC

DSW

ODVREN

1

20

R17

330KR2J -L1-GP

1 2

DY

R17

21

330KR2J -L1-GP

EC1701

SC4D7P5 0V2CN-1GP

EC1701

RTC

DY

_AUX_S5

1 2

A00 0618

A A

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (PM)

Hadley 15"

X02

17 10 1Friday, June 28, 201 3

1

X02

5

S

ID = CPU

S

3

3V_S0

D

D D

C C

SRN10KJ -6-GP

CLK_PCIE_ WLAN_N3[5 8] CLK_PCIE_ WLAN_P3[58]

CLK_PCIE_ WLAN_REQ3 #[58]

CLK_PCIE_ LAN_N4[30] CLK_PCIE_ LAN_P4[30 ]

CLK_PCIE_ LAN_REQ4#[30]

R

1801

N

1 2 3 4 5

CLK_PCIE_ VGA#[73] CLK_PCIE_ VGA[73 ]

PEG_CLK REQ#[73]

C

K_PCIE_RE Q#

L

8

C

K_PCIE_W LAN_REQ3#

L

7

P

G_CLKRE Q#

E

6

C

K_PCIE_LA N_REQ4#

L

X01 0321

RN1806

LPC_AD[3 ..0][24,65]

B B

LPC_AD[3 ..0]

LPC_FRA ME#[24,65]

SPI_CLK_R[24,25] SPI_CS0#_ R[24,25]

SPI_SI_R[24,25]

SPI_SO_R[24,25]

SPI_WP #[25] SPI_HOLD#[25]

RN1802

SRN1KJ-1 1-GP-U

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

3D3V_S5

1

23

4

RN1806 0R8P4R-P AD-1-GP

0R8P4R-P AD-1-GP

8 7 6

X01 0321

PCH_SPI_D Q3 PCH_SPI_D Q2

RN

1 2 1 2 1 2 1 2

1 2 3 45

R18010R 0402-PAD-2-GP R18010R 0402-PAD-2-GP

1 2

R18070R 0402-PAD-2-GP R18070R 0402-PAD-2-GP

1 2

R18080R 0402-PAD-2-GP R18080R 0402-PAD-2-GP R18090R 0402-PAD-2-GP R18090R 0402-PAD-2-GP R18110R 0402-PAD-2-GP R18110R 0402-PAD-2-GP R18120R 0402-PAD-2-GP R18120R 0402-PAD-2-GP

4

CLK_PCIE_ REQ#

LPC_LAD 0_PCH LPC_LAD 1_PCH LPC_LAD 2_PCH LPC_LAD 3_PCH LPC_LFR AME#_PCH

PCH_SPI_C LK

R180633R2 J-2-GP R1 80633R2J-2-GP

PCH_SPI_C S0#

PCH_SPI_S I PCH_SPI_S O PCH_SPI_D Q2 PCH_SPI_D Q3

P

C

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0#/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1#/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2#/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3#/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4#/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5#/GPIO23

HASW ELL-6-GP

CPU1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME#

AA3

SPI_CLK

Y7

SPI_CS0#

Y4

SPI_CS1#

AC2

SPI_CS2#

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASW ELL-6-GP

U1F

HSW_ULT_DDR3L

CLOCK

WLAN

SIGNALS

LAN/ Card reader

GPU

HSW_ULT_DDR3L

LPC

SMBUS

SML1ALERT#/PCHHOT#/GPIO73

C-LINKSPI

3

XTAL24_IN

XTAL24_OUT

RSVD#K21 RSVD#M21

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0ALERT#/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK CL_DATA CL_RST#

OF 19

6

7 OF 19

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

XTAL24_ IN XTAL24_ OUT

XCLK_BIAS REF

MCP_TES TLOW1 MCP_TES TLOW2 MCP_TES TLOW3 MCP_TES TLOW4

CLK_PCI_L PC_R CLK_PCI_K BC_R

MCP_GPIO11 SMB_CLK SMB_DAT A CARD_PW R_EN SML0_CL K SML0_DA TA MCP_GPIO73 SML1_CL K SML1_DA TA

TP_CL_C LK

1

TP_CL_D ATA

1

TP_CL_R ST#

1

2

A00 0618

0R0402-P AD-2-GP

www.qdzbwx.com

+V1.05S_ AXCK_LCPLL

3KR2F-GP

R1803

1 2

RN1803

RN1803 SRN10KJ -5-GP

SRN10KJ -5-GP

2 3 1

4

RN1808

RN1808 SRN10KJ -5-GP

SRN10KJ -5-GP

1

4

2 3

R1804 0R2J-2-GP

1 2

LPC

R1805

1 2

0R0402-P AD-2-GP

A00 0618

12

DY

SML0_CL K [53] SML0_DA TA [53]

SML1_CL K [24,26,76] SML1_DA TA [24,26,76]

TP1803TP1803 TP1804TP1804 TP1805TP1805

SMB_DAT A

SMB_CLK

SC10P50V2JN-4GP

EC1801

3D3V_S0

6

5

DY

T

AL24_IN

X

AL24_OU T

T

SC10P50V2JN-4GP

EC1802

12

Q1801

1

2

34

2N7002K DW-GP

0R0402-P AD-2-GP

R

1 2

12

R

802

1

1M1R2J-G P

CLK_PCI_L PC [65]

CLK_PCI_K BC [24 ]

PCIE_CLK_ XDP_N [9 6] PCIE_CLK_ XDP_P [96]

SML0_DA TA SML0_CL K SML1_CL K SML1_DA TA

MCP_GPIO73 MCP_GPIO11 CARD_PW R_EN

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

1

810

SMB_DAT A SMB_CLK

T

AL24_IN_R

X

23

4 1

2 3 1

82.30004.891

RN1807

4 5 3 2 1

SRN2K2J -4-GP

SRN2K2J -4-GP RN1809

RN1809 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2 3 4 5

RN1804

2 3 1

SRN2K2J -1-GP

RN1805

4

SRN2K2J -1-GP

PCH_SMB DATA [12 ,13,58,62,67]

PCH_SMB CLK [12,13,58,6 2,67]

1

801

C

1 2

SC15P50 V2JN-2-GP

XTAL-24M HZ-86-GP

XTAL-24M HZ-86-GP X

X

801

1

802

C

1 2

SC15P50 V2JN-2-GP

6 7 8

8 7 6

4

3D3V_S0

3D3V_S5 _PCH

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (CLK/SMB/LPC/SPI)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

18 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

D D

Q1901

RTCRST_ ON[24]

R1902

10KR2J-3 -GP

C C

Flash Descriptor Security Overide/ Intel ME Debug Mode

HDA_SDOUT

The internal pull-down is disabled a fter PLTRST# deasserts

B B

Low = Default High = Enable

R1913

1 2

DY

330KR2J -L1-GP

*

PCH_INTVR MEN

Integrated SUS 1V VRM Enable

INTVRMEN

Low = External VRs High = Internal VRs

*

G

12

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

HDA_COD EC_BITCLK[27]

HDA_COD EC_SYNC[27] HDA_COD EC_RST#[27,29 ] HDA_COD EC_SDOUT[27]

ME_UNLO CK[24]

D

R1907 33R2J-2-GPR1907 33R2J-2-GP

R1905 0R0402-PAD -2-GPR1905 0R0402-PAD -2-GP R1908 0R0402-PAD -2-GPR1908 0R0402-PAD -2-GP R1910 0R0402-PAD -2-GPR1910 0R0402-PAD -2-GP

R1909 1KR2J-1-GPR1 909 1KR2J-1-G P

1D05S_V CCST

R1916 51R2J-2-G P

R1917 51R2J-2-G P

R1918 51R2J-2-G P

R1919 1KR2J-1-G P

C1901

SC1U6D3V2KX-GP

1 2

1 2 1 2 1 2

1 2

4

RN1901

SRN20KJ -1-GP

21

12

G1901

GAP-OPEN

DY

12

DY

12

DY

12

DY

RTC_AUX _S5

1

23

4

12

C1902

C1902 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_TMS

XDP_TCK _JTAGX

330KR2J -L1-GP

HDA_SDIN0[27]

HDA_BITCL K

HDA_SYNC HDA_RST # HDA_SDO UT

R1903

TP1902TP1902

TP1901TP1901

RTC

_AUX_S5

12

R1901

R1901 1M1R2J-G P

1M1R2J-G P

RTC_X1 RTC_X2

SM_INTRUD ER#

PCH_INTVR MEN SRTC_RS T# RTC_RST #

HDA_BITCL K HDA_SYNC HDA_RST # HDA_SDIN0

HDA_SDO UT TP_HDA_ DOCK_EN#

1

PCH_JTA G_TRST#

1

PCH_JTA G_TCK PCH_JTA G_TDI PCH_JTA G_TDO PCH_JTA G_TMS

XDP_TCK _JTAGX

3

CPU1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER#

AV7

INTVRMEN

AV6

SRTCRST#

AU7

RTCRST#

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST#/I2S_MCLK#

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN#/I2S1_TXD#

AV10

HDA_DOCK_RST#/I2S1_SFRM#

AY8

I2S1_SCLK

AU62

PCH_TRST#

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD#AL11

AC4

RSVD#AC4

AE63

JTAGX

AV2

RSVD#AV2

HASW ELL-6-GP

12

C19

SC15P50V2JN-2-GP

1 2

R19

15 10MR2J-L -GP

X19

01

41

2 3

03

X-32D768 KHZ-65-GP

82.30001.A41

2nd = 82.30001.841

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

2

_X1

RTC

_X2

RTC

02 0502 change C1903 C1904 from 18pF to 15 pF

X

12

C19

04

SC15P50V2JN-2-GP

5 OF 19

RSVD#L11 RSVD#K10

SATALED#

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1 U1 V6 AC1

A12 L11 K10 C12 U3

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

SATA_RCOMP

EC_SMI#

MCP_GPIO35

SATA_OD D_PRSNT#

SATA_IREF

SATA_RC OMP SATA_LE D#

EC_SMI#

MCP_GPIO35

MSATA_D ET#

SATA_OD D_PRSNT#

1

SATA3_P RX_DTX_N0 [56] SATA3_P RX_DTX_P0 [56] SATA3_P TX_DRX_N0 [56] SATA3_P TX_DRX_P0 [56]

SATA3_P RX_DTX_N1 [63] SATA3_P RX_DTX_P1 [63] SATA3_P TX_DRX_N1 [63] SATA3_P TX_DRX_P1 [63]

EC_SMI# [24]

MSATA_D ET# [63]

SATA_LE D# [61]

Layout Note:

4mil trace at b reak-out and 3 12-15mil trace with <0.2 ohms and length tota l <= 500mils.

RN1902

1 2 3 4 5

SRN10KJ -6-GP

HDD1

mSATA

+V1.05S_ ASATA3PLL

0R0402-P AD-2-GP

R1904

1 2

R1906

R1906 3KR2F-GP

3KR2F-GP

3D3V_S0

8 7 6

1 2

DY

R1920 51R2J-2-G P

A A

5

4

PCH_JTA G_TCK

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RTC/SATA/HDA/JTAG)

Size Document N umber Rev

A3

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

X02

19 10 1Friday, June 28, 201 3

1

X02

SSI

= CPU

D

5

4

HSW

CPU

J

1

HSW

ULT_DDR3L

_

3

10

F 19

O

2

1D05S_VCCST

12

R20

R20 1KR2J-1-G P

1KR2J-1-G P

8

1

FFS

INT2

04

3D3V_S0

OPS

UMA

_

MCP

GPIO8

_

MCP

GPIO12

_

MCP

GPIO15

_

MCP

GPIO16

_

1

A

_ODD_DA #

SAT RTC

DET#

_

GPIO27

MCP MCP

GPIO28

_

MCP_GPIO2 6

MCP_GPIO5 6 MCP_GPIO5 7 MCP_GPIO5 8 WLAN _PLT_RST#

DRAM_SE L0 DRAM_SE L3

BOARD_ID1 BOARD_ID2 MCP_GPIO5 0

1

MCP_GPIO1 3 MCP_GPIO1 4 CAMERA_ PWR_EN

1

DRAM_SE L1 DRAM_SE L2

EC_SW I# EC_SCI#

MCP_GPIO7 0

1

MCP_GPIO3 9

1

12

R2005

R2005 10KR2J-3 -GP

10KR2J-3 -GP

12

R2008

R2008 10KR2J-3 -GP

10KR2J-3 -GP

4

FFS

INT2[6 7]

RTC

_

0

TP2

_

DET#[2 5]

3D3

_S5

V

RN2

06

0

MCP

GPIO12

D D

1 2 3

SRN10KJ -5-GP

_

4

_

GPIO27

MCP

GPIO[47:44]=[1,1,1,1] for SODIMM configuration

RN2005

RN2005 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2

DY

1 2

DY

TP2002TP2002

TP2020TP2020

TP2009TP2009

TP2003TP2003

FFS_INT2

8

BOARD_ID1 I2C0_SCL

7

SATA_OD D_DA#

6

BLUETOO TH_EN

HDD_DEV SLP

MSATA_D EVSLP

HSIOPC[21]

3D3V_S5 _PCH

12

R2013

R2013 10KR2J-3 -GP

10KR2J-3 -GP

MCP_GPIO_ PH

C C

3D3V_S5 _PCH

3D3V_S0

B B

A00 0618

R20010R0402 -PAD-2-GP R20010R0402 -PAD-2-GP

1 2

R20020R0402 -PAD-2-GP R20020R0402 -PAD-2-GP

1 2

R20040R0402 -PAD-2-GP R20040R0402 -PAD-2-GP

1 2

R20070R0402 -PAD-2-GP R20070R0402 -PAD-2-GP

1 2

R20150R0402 -PAD-2-GP R20150R0402 -PAD-2-GP

1 2

R20160R0402 -PAD-2-GP R20160R0402 -PAD-2-GP

1 2

R20170R0402 -PAD-2-GP R20170R0402 -PAD-2-GP

1 2

R20190R0402 -PAD-2-GP R20190R0402 -PAD-2-GP

1 2

R20200R0402 -PAD-2-GP R20200R0402 -PAD-2-GP

1 2

R20210R0402 -PAD-2-GP R20210R0402 -PAD-2-GP

1 2

R20220R0402 -PAD-2-GP R20220R0402 -PAD-2-GP

1 2

R20230R0402 -PAD-2-GP R20230R0402 -PAD-2-GP

1 2

RN2012

RN2012 SRN10KJ -6-GP

SRN10KJ -6-GP

1 2 3 4 5

R2024

1 2

100KR2J -1-GP

8 7 6

MCP_GPIO5 8

DRAM_SE L0 DRAM_SE L2

MCP_GPIO2 6 MCP_GPIO5 6

DRAM_SE L1

MCP_GPIO1 4 MCP_GPIO2 8 MCP_GPIO8 MCP_GPIO1 3

DRAM_SE L3

MCP_GPIO5 7

EC_SCI#

EC_SW I# RTC_DET #

WLAN _PLT_RST#

HSIOPC

3D3V_S0

10KR2J-3 -GP

EC_SW I#[24] EC_SCI#[24]

HDD_DEV SLP[56]

MSATA_D EVSLP[63]

HDA_SPK R[27]

1 2 3 4 5

R2009

R2010

BIOS strap pin:

BIOS UMA/DIS Strap pin

BOARD_ID2BOARD_ID1

PX(AMD)

DIS

UMA

Optimus(NV)

A A

0 0

0

1

5

1

BOARD_ID2

0

1

P1

BMB

SY#/GPIO76

U

AU2

GPI

8

O

AM7

LAN

PHY_PWR_CTRL/GPIO12

_

AD6

GPI

15

O

Y1

GPI

16

O

T3

O

17

GPI

AD5

GPI

24

O

AN5

O

27

GPI

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASW ELL-6-GP

PCH strap pin:

The internal pull-down is disabled a fter PLTRST# deasserts

The internal pull-down is disabled a fter RSMRST# deasserts.

The internal pull-down is disabled a fter PLTRST# deasserts

GPIO

NO REBOOT

Low = Disable (Default)

HDA_SPKR

*

High = Enable

Top-Block Swap Override mode

SDIO_D0 / GPIO66

High = Enable "Top-Block swap"

Low = Disable "Top-Block swap" mode

*

TLS Confidentiality

Low = Disable Intel ME Crypto TLS

GPIO15

*

High = Enable Intel ME Crypto TLS

Boot BIOS Strap Bit BBS

Boot BIOS Destination

Low = SPI

*

High = LPC

CPU/

CPU/ MISC

MISC

SERIAL IO

mode (Default)

3

THR

TRIP#

M

RCI

#/GPIO82

N

SER

PCH

GSPI0_CS#/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS#/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92 UART0_RTS#/GPIO93 UART0_CTS#/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1 UART1_RST#/GPIO2 UART1_CTS#/GPIO3

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

I

OPI_RCOMP

_

RSV

#AF20

D D

#AB21

RSV

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

RQ

PCH

D60

H_R

V4

INT

T4

PCH

AW15 AF20 AB21

MCP_GPIO83

R6

MCP_GPIO84

L6

SATA_OD D_PWRGT

N6

LPSS_GS PI0_MOSI_BBS0_R

L8

MCP_GPIO87

R7

MCP_GPIO88

L5

TOUCH_P WR_EN

N7 K2 J1 K3

MCP_GPIO93

J2

MCP_GPIO94

G1

MCP_GPIO0

K4

MCP_GPIO1

G2

MCP_GPIO2

J3 J4

I2C0_SDA

F2

I2C0_SCL

F3

I2C1_SDA

G4

I2C1_SCL

F1

COLOR_E NGINE

E3

MCP_GPIO65

F4

LPSS_SD IO_D0_CM NHDR

D3

MCP_GPIO67

E4

MCP_GPIO68

C3

MCP_GPIO69

E2

3D3V_S0

1KR2J-1-G P

1KR2J-1-G P R2006

R2006

1 2

3D3V_S0

12

R2011

DY

1KR2J-1-G P

LPSS_SD IO_D0_CM NHDR

3D3V_S5 _PCH

12

R2014

DY

1KR2J-1-G P

3D3V_S0

12

R2012

DY

1KR2J-1-G P

LPSS_GS PI0_MOSI_BBS0_R

THERMTR IP

_

IN#

C SERIRQ

_

OPIRCOMP

_

DY

KB_DET# [62] KB_LED_ BL_DET [6 2] DBC_EN [52 ]

HDA_SPK R

MCP_GPIO15

1 1 1

1 1 1 1 1

1

1 1 1

2

1 2

R20

R20 49D9R2F -GP

49D9R2F -GP

TP2010TP2010 TP2011TP2011 TP2021TP2021

TP2012TP2012 TP2013TP2013 TP2014TP2014

TP2015TP2015 TP2016TP2016 TP2017TP2017 TP2018TP2018 TP2019TP2019

TP2005TP2005

TP2006TP2006 TP2007TP2007 TP2008TP2008

0

3

COLOR_E NGINE [52]

H_R

IN# [24]

C

INT

SERIRQ [2 4]

_

Layout Note:

1

.Referenced "continuous" VSS plane only.

2.Avoid routing next to clock pins or noisy signals.

3. Trace width: 12~15mil

4. Isolation Spacing: 12mil

5. Max length: 500mil

BLUETOO TH_EN [58]

RN2014

SRN10KJ -6-GP

INT_SERIRQ KB_DET#

H_RCIN# DBC_EN

I2C0_SDA

I2C1_SCL I2C1_SDA

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (GPIO)

Size Document N umber Rev

A3

Date: Sheet of

CPU (GPIO)

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

SRN10KJ -6-GP

1 2 3 4 5

RN2007

SRN10KJ -6-GP

8 7 6

20 10 1Friday, June 28, 201 3

1

3D3V_S0

8 7 6

3D3V_S0

1 2 3 45

X02

5

S

SID = CPU

D D

1D05V_S0

0R0402-PAD-2-GP

A00 0618

1 2

R2105

0R0402-PAD-2-GP

3D3V_S5

C C

1D05V_S0

R2101

1 2

0R0402-PAD-2-GP

R2117

1 2

0R0402-PAD-2-GP

12

DY

+V3.3A_DSW_P

C2136

SCD1U10V2KX-5GP

+V1.05S_SSCF100

C2137

SC1U6D3V2KX-GP

12

3D3V_S0

R2104

1 2

+V3.3A_1.5A_HDA3D3V_S5_PCH

R2106

1 2

0R0402-PAD-2-GP

4

C2105

12

DY

C2116

12

+V1.05DX_MODPHY_PCH

SC1U6D3V2KX-GP

TP2102TP2102

+V1.05S_APLLOPI

TP2107TP2107

SC1U6D3V2KX-GP

TP2108TP2108

+V1.05S_AXCK_DCB

+V1.05S_AXCK_LCPLL

TP2103TP2103 TP2104TP2104 TP2101TP2101

+V1.05DX_MODPHY_PCH

+V1.05S_AIDLE

+V1.05S_AUSB3PLL

+V1.05S_ASATA3PLL

TP_VCCAPLLOPI_VAL

1

+V1.05A_VCCUSB3SUS

1

+V3.3A_1.5A_HDA

+V1.05A_USB2SUS

1

+V3.3A_PSUS

+V3.3A_DSW_P

12

C2123

C2123 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

+V1.05S_SSCF100

+V1.05S_SSCFF

TP_V1.05S_SSCF100

1

TP_V1.05S_AXCK_DCB

1

TP_V1.05S_SSCFF

1

+V3.3A_PSUS

+V3.3S_PCORE

AA21

AH14

AH13

AH10

AE20 AE21

W21

M20

AC9 AA9

K19 A20

R21

K9

L10

M9 N8

P9 B18 B11

Y20

J13

V8 W9

J18

J17

T21 K18

V21

CPU1M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD#Y20 VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD#K18 RSVD#M20 RSVD#V21 VCCSUS3_3 VCCSUS3_3

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

3

HSW_ULT_DDR3L

OPI

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

13 OF 19

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP#AG19 DCPSUSBYP#AG20

VCCASW VCCASW VCCASW

DCPSUS1#AD10

DCPSUS1#AD8

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD#AC20

VCC1_05

A00 0618

0R0402-PAD-2-GP

+3.

3A_DSW_PRTCSUS

AH11 AG10

+VCCRTCEXT

AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22

+PCH_VCCDSW PCH_VCCDSW_R

AG19 AG20 AE9

+1.05M_ASW

AF9 AG8

+V1.05A_SUS_PCH

AD10 AD8

J15

1D5V_S0

K14 K16

U8

+V3.3S_1.8S_LPSS_SDIO

T9

+V1.05A_AOSCSUS

AB8

TP_V1.05S_APLLOPI

AC20 AG16 AG17

12

C2109

C2109 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

RTC_AUX_S5

C2110

SCD1U10V2KX-5GP

1D05V_S0

R2110

R2110 5D1R2F-GP

5D1R2F-GP

1 2

1

0R0402-PAD-2-GP

1 2

TP2106TP2106

1

2

R21

02

1 2

3D3V_S0

TP2109TP2109

TP2105TP2105

C2135

SC1U6D3V2KX-GP

12

C2147

C2147 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2114

C2114 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2128

SC1U6D3V2KX-GP

12

3D3

3D3V_S5

V_S5_PCH

1 2

1D05V_S0

X02 remove C2103

+V3.3S_1.8S_LPSS_SDIO

0R0402-PAD-2-GP

12

C2104

SC1U6D3V2KX-GP

1

R2103

1 2

3D3V_S0

HASWELL-6-GP

1D05V_S0

B B

A A

R2118

1 2

0R0402-PAD-2-GP

5

+V1.05S_SSCFF

C2138

SC1U6D3V2KX-GP

12

HSIOPC[20]

4

1D05V_S0 1D05V_HSIO

1 2

5V_S5

1D05V_S0

HSIO

Non-HSIO

R2123

HSIO

0R2J-2-GP

12

C2102

SC4D7U6D3V3KX-GP

3

R2122

R2122 0R5J-5-GP

0R5J-5-GP

1 2

HSIOPC_R

U2101

1

VDD

2

D#2

3

D#3 D#44S#5

SLG59M1470VTR-GP

74.59147.093

9

HSIO

1D05V_HSIO

0R5J-5-GP

0R5J-5-GP R2114

ON

8

GND

S#7 S#6

HSIO_OUT

7 6 5

R2114

1 2

HSIO

12

HSIO

C2101

SC10U6D3V3MX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (POWER2)

Hadley 15"

21 101Friday, June 28, 2013

1

X02

5

SSI

D = CPU

D D

DC_TEST _AY2_AW2

TP2201TP2201

TP2204TP2204

C C

TP_DC_T EST_AY60

1

DC_TEST _AY61_AW61 DC_TEST _AY62_AW62

1

DC_TEST _A3_B3 DC_TEST _A61_B61 DC_TEST _B62_B63

4

HSW_ULT_DDR3L

CPU1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASW ELL-6-GP

CPU1R

AT2

RSVD#AT2

AU44

RSVD#AU44

AV44

RSVD#AV44

D15

RSVD#D15

F22

RSVD#F22

H22

RSVD#H22

J21

RSVD#J21

HSW_ULT_DDR3L

3

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

18 OF 19

RSVD#N23 RSVD#R23

RSVD#T23

RSVD#U10

RSVD#AL1

RSVD#AM11

RSVD#AP7 RSVD#AU10 RSVD#AU15

RSVD#AW14

RSVD#AY14

DC_TEST _A3_B3

A3

TP_DC_T EST_A4DC_TEST _AY3_AW3

A4

TP_DC_T EST_A60

A60

DC_TEST _A61_B61

A61

TP_DC_T EST_A62TP_DC_T EST_B2

A62

TP_DC_T EST_AV1

AV1

TP_DC_T EST_AW1

AW1

DC_TEST _AY2_AW2

AW2

DC_TEST _AY3_AW3

AW3

DC_TEST _AY61_AW61DC_TEST _C1_C2

AW61

DC_TEST _AY62_AW62

AW62

TP_DC_T EST_AW63

AW63

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

2

TP2202TP2202

1

TP2203TP2203

1

TP2205TP2205

1

TP2206TP2206

1

TP2207TP2207

1

TP2208TP2208

1

HASW ELL-6-GP

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

RSVD

Hadley 15"

22 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = CPU

HSW

_ULT_DDR3L

CPU

A

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5

AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

A A A A28 A32 A36 A40 A44 A48 A52 A56

11 14 18 24

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

HASW ELL-6-GP

D D

C C

B B

_ULT_DDR3L

1N

4

14

OF 19

A

J35

VSS

J39

A

VSS

A

J41

VSS

J43

A

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

3

_ULT_DDR3L

HSW

CPU

1O

A

P22

VSS

P23

A

VSS

A

P26

VSS

P29

A

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16

VSS

AU18

VSS

AU20

VSS

AU22

VSS

AU24

VSS

AU26

VSS

AU28

VSS

AU30

VSS

AU33

VSS

AU51

VSS

AU53

VSS

AU55

VSS

AU57

VSS

AU59

VSS

AV14

VSS

AV16

VSS

AV20

VSS

AV24

VSS

AV28

VSS

AV33

VSS

AV34

VSS

AV36

VSS

AV39

VSS

AV41

VSS

AV43

VSS

AV46

VSS

AV49

VSS

AV51

VSS

AV55

VSS

HASW ELL-6-GP

2

15

OF 19

A

V59

VSS

V8

A

VSS

A

W16

VSS

W24

A

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

Hadley 15"

23 10 1Friday, June 28, 201 3

1

X02

5

D = KBC

SSI

1D0

D D

C C

B B

5V_S0

Layout Note:

Need very close to EC

C2412

SCD1U10V2KX- 5GP

LCD_TST_EN[52]

LCD_TST[52]

R24

1 2

0R0402-PAD-2- GP

3D3V_S0

C24

SC2D2U6D3V2MX-GP

12

13

DY

R2417 0R0402-PAD-2-GPR2417 0R0402-PAD-2-GP

01

1 2

EC_AGND

Don't PD

ALL_SYS_PWRGD assert, delay 10ms; PCH_PWROK assert.

ALL_SYS_PWRGD assert, delay 100ms; SYS_PWROK assert.

LVDS backlight Control from PS8625

R2444

R2444 0R2J-2-GP

0R2J-2-GP

R2446

R2446 0R2J-2-GP

0R2J-2-GP

1 2

eDP

1 2

LVDS

L_BKLT_EN[15]

eDP backlight Control from PCH

LVDS_R2136_BKLT _EN[53]

Backlight Control from LVDS Converter

EC_

VTT

12

C2401

SCD1U10V2KX-5GP

EC_FB_CLAMP_T GL_REQ#[76]

VBA

T

VBA

12

C2404

SCD1U10V2KX-5GP

EC_AGND

AD_IA[44]

C2414 SCD1U10V2KX-5GP

1 2

DY

PSID_EC[42]

PM_SLP_SUS#[17,38] BOOST_MON[44]

USBCHARG ER_CB0[35]

FAN1_DAC_1[26]

AD_IA_HW[44]

IMVP_PWRGD[7,46]

BAT_SCL[43,44,53] BAT_SDA[43,44,53]

SML1_CLK[18,26,76]

SML1_DATA[18,26,76]

PM_LAN_ENABLE[30]

RTCRST_O N[19]

USBCHG_EN[35]

TPCLK[62]

TPDATA[62]

ALL_SYS_PWRG D[36]

PWR_CH G_AD_OFF[42]

AD_IA_HW2[44]

BLON_OUT[52]

FAN_TACH 1[26]

PM_PWRBT N#[17,96]

EC_FB_CLAMP[75,76,83]

PM_SLP_S3#[17,36,48,49, 51]

PWRLED #[61]

KBC_BEEP[27]

EC_BRIGHTN ESS[52]

AC_IN_KBC#[42]

KB_BL_CTRL[62]

LAN_WAKE#[30]

KBC_DPW ROK[17]

CHG_AMBER_ LED#[61]

PCH_PW ROK[17,26,3 6]

USB_PWR _EN#[35]

AC_PRESENT[17,76]

SYS_PWROK[17,96] AOAC_WLA N_EN[58]

WIFI_RF_EN[58]

PM_SUSWA RN#[17]

DGPU_PW ROK[15,82,83]

DIS_DTM[44] E51_TxD[58]

PM_CLKRUN #_EC[17]

AMP_MUTE#[27]

12

R2445

100KR2J-1-GP

T

C2405

SC2D2U6D3V2MX-GP

12

DY

PCB_VER_AD

AMB_TEMP

MODEL_ID_DET

PROCHOT _EC LCD_TST_EN

ECSWI#_KBC

L_BKLT_EN_EC

3D3

EC_VTT

V_AUX_KBC_VC C

12

C2406

SCD1U10V2KX-5GP

KBC24

19

VCC

46

VCC

76

VCC

88

VCC

115

VCC

102

AVCC

4

VDD

12

VTT

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

108

GPIO5/AD4

96

GPIO4/AD5

95

GPIO3/EXT_PURST#/AD6

94

GPIO7/AD7/VD_IN2

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

70

GPIO17/SCL1/N2TCK

69

GPIO22/SDA1/N2TMS

67

GPIO73/SCL2/N2TCK

68

GPIO74/SDA2/N2TMS

119

GPIO23/SCL3/N2TCK

120

GPIO31/SDA3/N2TMS

24

GPIO47/SCL4/N2TCK

28

GPIO53/SDA4/N2TMS

26

GPIO51/TA3/N2TCK

123

GPIO67/N2TMS

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27/PSDAT2

25

GPIO50/PSCLK3/TDO

27

GPIO52/PSDAT3/RDY#

31

GPIO56/TA1

117

GPIO20/TA2/IOX_DIN_DIO

63

GPIO14/TB1

64

GPIO1/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM/1_WIRE

81

GPIO66/G_PWM

66

GPO33/H_PWM/VD1_EN#

104

GPIO80/VD_IN1

110

GPIO82/IOX_LDSH/VD_OUT1

112

GPIO84/IOX_SCLK/VD_OUT2

84

GPIO77/SPI_MISO

83

GPIO76/SPI_MOSI

82

GPIO75/SPI_SCK

79

GPIO2/SPI_CS#

124

GPIO10/LPCPD#

121

GPIO85/GA20

111

GPIO83/SOUT_CR

9

GPIO65/SMI#

8

GPIO11/CLKRUN#

30

GPIO55/CLKOUT/IOX_DIN_DIO

NPCE985PA0DX -1-GP

71.00985.C0G

AOAC Ambient temperature detect

VBAT

12

R2437

R2437 10KR2F-2-GP

R2441

EC_AGND

C2419

1 2

10KR2F-2-GP

1 2

0V2KX-5GP

SCD1U1

C2420

AMB_TEMP

12

0P50V2JN-3GP

SC10

5

A A

NTC-10K-26- GP

69.60037.011

EC_GPIO47 High Active

PROCHOT _EC

12

R2442

100KR2J-1-GP

DY

R2438

R2438 0R2J-2-GP

0R2J-2-GP

1 2

DY

Q2401

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

4

02

R24

12

0R0603-PAD-2- GP-U

12

C2407

C2408

DY

SCD1U10V2KX-5GP

KBSIN0/GPIOA0/N2TCK

KBSIN1/GPIOA1/N2TMS

KBSOUT0/GPOB0/SOUT_CR/JENK#

KBSOUT1/GPIOB1/TCK KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT9/GPOC1/SDP_VIS#

KBSOUT10/P80_CLK/GPIOC2

KBSOUT11/P80_DAT/GPIOC3

KBSOUT12/GPO64/TEST#

KBSOUT13/GPI/O63/TRIST#

KBSOUT14/GPI/O62/XORTR#

KBSOUT15/GPIO61/XOR_OUT

GPIO81/F_WP#/F_SDIO2 GPIO0/EXTCLK/F_SDIO3

PSL_IN2#/GPI6/EXT_PURST#

GPIO46/CIRRXM/TRST#

GPIO87/CIRRXM/SIN_CR

H_PROCHO T#_EC

D

4

2D2R3-1-U- GP

12

C2409

DY

SCD1U10V2KX-5GP

KBSIN2/GPIOA2 KBSIN3/GPIOA3 KBSIN4/GPIOA4 KBSIN5/GPIOA5 KBSIN6/GPIOA6 KBSIN7/GPIOA7

KBSOUT7/GPIOB7 KBSOUT8/GPIOC0

GPIO60/KBSOUT16 GPIO57/KBSOUT17

LAD0/GPIOF1 LAD1/GPIOF2 LAD2/GPIOF3 LAD3/GPIOF4 LCLK/GPIOF5

LFRAME#/GPIOF6

LRESET#/GPIOF7

F_CS0#

GPIO30/F_WP# GPIO41/F_WP#

F_SDIO/F_SDIO0

F_SDI/F_SDIO1

PSL_IN1#/GPI70

PSL_OUT#/GPIO71

ECSCI#/GPIO54

EXT_RST#

KBRST#/GPIO86

VBKUP VCORF

SERIRQ/GPIOF0

GPIO24

GPIO36/TB3

GPIO44/TDI GPIO43/TMS GPIO42/TCK

GPIO34/CIRRXL

1 2

0R0402-PAD-2- GP

C2410

F_SCK

VSBY

PECI

GND GND GND GND GND GND

AGND

R2440

3D3

R24

12

V_AUX_KBC

03

54 55 56 57 58 59 60 61

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

126 127 128 1 2 3 7

90 92 109 80 87 86 91 77

73 93 74

29 85 122

75 114 44 13 125 6 15

21 20 17 23

113 14

5 18 45 78 89 116

103

1 2

12

SCD1U10V2KX- 5GP

C2411

SC2D2U6D3V2MX-GP

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 USB_DET#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

PLT_RST#_EC

EC_SPI_CS#_C EC_SPI_CLK_C

EC_SPI_DI_C EC_SPI_DO_C

PSL_IN1# PSL_IN2# PSL_OUT#

ECSCI#_KBC ECRST#

EC_VBKUP KBC_VCORF PECI

ECSMI#_KBC

EC_AGND

12

C2421

C2421 SC47P50V2JN-3G P

SC47P50V2JN-3G P

T

VBA

A00 0618

12

R24

04

64K9R2F-1-GP

PCB

_VER_AD

12

R24

06

100KR2F-L1-GP

C24

ME_UNLOCK [19]

WIFI_WAKE# [5 8]

S5_ENABLE [36]

X01 0321

12

R2435

R2435 0R0402-PAD-2- GP

0R0402-PAD-2- GP

EC_AGND

100KR2F-L1-GP

02

DY

1 2

EC_

AGND

KROW[0..7] [62]

KCOL[0..16] [62]

LPC_AD[3..0] [18,65]

CLK_PCI_KBC [18] LPC_FRAME# [18,65]

R2419 0R0 402-PAD-2-GPR2419 0R0402-PAD -2-GP

1 2

R2412 33R 2J-2-GPR2412 33R 2J-2-GP

12

R2420 0R0 402-PAD-2-GPR2420 0R0402-PAD -2-GP

1 2

R2422 0R0 402-PAD-2-GPR2422 0R0402-PAD -2-GP

1 2

Layout Note:

Need very close to EC

H_RCIN# [20]

R2428 0R0 402-PAD-2-GPR2428 0R0402-PAD -2-GP

1 2

INT_SERIRQ [20]

OVER_CUR RENT_P8# [76]

PM_SLP_S4# [17,49] RSMRST#_KBC [17]

CH751H-40PT -GP

83.R0304.A8F

Layout Note:

Connect GND and AGND planes via either 0R resistor or connect directly.

LID_CLOSE# [61]

D2402

21

3D3V_AUX_S5 RTC_AUX_S5

DY

3

VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

PCB

00

X

01

02

X

03

A

00

R

served

e

Res

erved

served

e

eserved 100.0K 215.0K 1.048V

R

SPI_CS0#_R [18,25] SPI_CLK_R [18,25] CAP_LED# [62] BAT_IN# [42,43,44] SPI_SI_R [18, 25] SPI_SO_R [18,25]

PM_SUSACK# [17]

PCH_SUSC LK_KBC [17]

C2416 SC1U6D3V2 KX-GPC2416 SC1U6D 3V2KX-GP

1 2

R2429

12

C2422

43R2J-GP

SC100P50V2JN-3 GP

TOUCH_PA NEL_INTR# [52]

10KR2J-3-GP

PURE_HW _SHUTDOW N#[26,36,76]H_PROCH OT# [4,42,44,46]

3

00.0K

1

100.0K

1

00.0K 1.358V

00.0K

1

A00 0618

0R0402-PAD-2- GP

R2416

1 2

12

SC220P50V2KX-3GP

SC220P50V2KX-3GP C2415

C2415

DY

H_PECI [4]

Layout Note:

Need very close to EC C2422 PDG is 47p

3D3V_AUX_S5

R2439

R2434

12

1 2

DY

0R2J-2-GP

Q2404

MMBT3906-4-GP

84.T3906.A11

2nd = 84.03906.F11

E

B

C

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

1

43.0K

74.0KR

1

PLT_RST# [17,30,58,65,73]

KBC_PWR BTN#[61]

AC_IN#[44]

USBDET_CO N#[34]

ECRST#

C2418

12

DY

SC1U6D3V2KX-GP

3.0V

2

.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

1.204V

0R0402-PAD-2- GP

R2427

1 2

0R0402-PAD-2- GP

R2430

1 2

D2401

3

BAT54CPT-2- GP

75.00054.K7D

PSL_OUT#

2

MOD

1

2

1 2

2

3D3V_AUX_S5

1KR2J-1-GP

1KR2J-1-GP R2432

R2432

EL_ID_DET

C24

SCD1U10V2KX- 5GP

R2425

R2425 330KR2J-L1-GP

330KR2J-L1-GP

1 2

PSL_IN2#

PSL_IN1#

USB_DET#

KBC_ON#_GAT E_L

VBAT

MODEL_ID_DET(GPIO07)

(DOH70)UMA

R2405

49K9R2F-L-GP

12

03

DY

1 2

EC_

AGND

3D3V_AUX_S5 3D3V_AUX_S5

R24

100KR2F-L1-GP

07

1 2

R2431

R2431 330KR2J-L1-GP

330KR2J-L1-GP

1 2

R2433

R2433 20KR2J-L2-GP

20KR2J-L2-GP

(DOH50)UMA/eDP

TBD

(DO

H70)DIS

TBD TBD TBD TBD

(DOH50)UMA/LVDS

D

OH50)DIS/eDP

(

TBD TBD TBD TBD TBD TBD TBD TBD

(DOH50)DIS/LVDS

TBD

ECSCI#_KBC

ECSMI#_KBC

ECSWI#_KBC

KBC_ON#_GAT EKBC_ON#_GAT E_L

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

AC_IN_KBC#

USB_DET#

BAT_SCL BAT_SDA

ECRST#

AC_IN# BAT_IN# OVER_CUR RENT_P8#

FAN_TACH 1

LID_CLOSE#

C2417

C2417 SCD1U10V2KX- 5GP

SCD1U10V2KX- 5GP

1 2

G

Q2402

Q2402 DMP2130L-7-GP

DMP2130L-7-GP

84.02130.031

2ND = 84.03413.A31

G

S

Title

Size Document Num ber Rev

Size Document Num ber Rev A2

A2

Friday, June 28, 2013

Friday, June 28, 2013 Date: Sheet of

Date: Sheet of

1

00.0K

1

100.0K

10.0K 1

3.7K

1

7.8K

22.1K(64.22125.6DL)

27.0K(64.27025.6DL)

32.4K(64.32425.6DL)

37.4K(64.37425.6DL)

43.2K(64.43225.6DL)

7.6K

5 6

4.9K

3.2K

7

82.5K(64.82525.6DL) 1.808V

3.1K

9 107K(64.10735.6DL) 120K(64.12035.6DL) 137K(64.13735.6DL) 154K(64.15435.6DL) 200K(64.20035.6DL) 1.099V 2

32K

X01 0321

R24080R0402- PAD-2-GP R24080R 0402-PAD-2-GP

1 2

R24090R0402- PAD-2-GP R24090R 0402-PAD-2-GP

1 2

R24100R0402- PAD-2-GP R24100R 0402-PAD-2-GP

1 2

R2426 100KR2J-1-GPR2426 100KR2J-1-GP

1 2

R2411 100KR2J-1-GPR2411 100KR2J-1-GP

1 2

RN2401

4

SRN4K7J-8-G P

R2418 10KR2J -3-GPR 2418 10KR2J-3- GP

1 2

R2413 100KR2 J-1-GP

1 2

DY

R2414 100KR2 J-1-GPR 2414 100KR2J-1- GP

1 2

R2424 100KR2 J-1-GP

1 2

DY

R2415 10KR2J -3-GPR 2415 10KR2J-3- GP

1 2

R2421 100KR2J-1-GPR2421 100KR2J-1-GP

1 2

S

G

D

3D3V_AUX_KBC

Q2403

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

KBC Nuvoton NPCE985

Hadley 15"

1

64.10025.6DL)

( (

64.13725.6DL)

(

64.17825.6DL)

64.57625.6DL)

( (

64.64925.6DL)

64.73225.6DL) 1.905V

(

64.93125.6DL)

(

64.23236.6DL)

EC_SCI# [20]

EC_SMI# [19]

EC_SWI# [20 ]

3D3V_AUX_KBC

23 1

3D3V_AUX_KBC

3D3V_S0

3D3V_S5

3D3V_AUX_KBC

12

R2436

R2436 10KR2J-3-GP

10KR2J-3-GP

S5_ENABLE

24 101

.0V

3 2

.902V

2.801V

2.702V

2.598V

2.492V

2.402V 2

.304V

2.201V49.9K(64.49925.6DL)

2.093V

2.001V

1.709V

1.594V

1.499V

1.392V

1.299V

0.994V

X02

5

D = Flash.ROM

SSI

4

3

2

1

SPI Flash ROM(8M) for PCH

3D3

V_S5

D D

R25

01

4K7R2J-2 -GP

4

RN2

501

SRN4K7J -8-GP

DY

1 2

1

2 3

DY

3D3

V_S5

SC10U6D3V3MX-GP

C2501

12

C25

02

SCD1U10 V2KX-5GP

Single SPI shared flash connection (SPI Quad I/O mode)

SPI25

SPI_CS0#_ R[18,24]

SPI_SO_R[1 8,24]

SPI_WP #[18]

12

DY

EC2502

SC4D7P5 0V2CN-1GP

C C

EC2502

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

W25 Q64FVSSIQ-GP

72.25Q64.K01

VCC

HOLD#/IO3

CLK

DI/IO0

3D3V_S5

8 7 6 5

12

DY

12

EC2503

DY

SC10P50 V2JN-4GP

EC2501

SC4D7P5 0V2CN-1GP

QUAD/DUAL fast read DUAL fast readSource

72.25Q64.K01

72.25647.00A O O

SPI_HOLD# [18] SPI_CLK_R [18,2 4] SPI_SI_R [18,24]

O O

Re

er to "NCPE985x/ NPCE995x board design reference guide"

f

SSID = RBATT

3

RTC_AUX _S5+RTC_VC C 3D 3V_AUX_S5

1 2

C2503

SC1U6D3 V2KX-GP

A00 0619

D2501

2

1

BAS40CW -GP

83.00040.E81

1 2 NP1 NP2

+RTC_VC C

1

1KR2J-1-G P

R2502

12

RTC_PW R

B B

AFTP250 2AFTP2502

RTC1

PWR GND

NP1 NP2

BAT-AAA-B AT-054-P06-GP-U

62.70001.061

A A

5

4

AFTP250 1AFTP2501

1

Q2505

12

R2504

R2504 10MR2J-L -GP

10MR2J-L -GP

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

D

3

RTC_DET # [20]

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Flash/RTC

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

25 10 1

1

X02

SSI

D = Thermal

5

4

3

2

1

Fan controller1

5V_

FAN1

1

12

C2605

4

5

AFTP260 1AFTP2601

AFTP260 2AFTP2602

S0

12

C2611

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

FAN

R26

05

0R2J-2-GP

3D3

V_S0

D D

3D3V_S0

SC10U6D3V3MX-GP

C2601

12

C2602

SCD1U10V2KX-5GP

84.03904.L06

2ND = 84.03904.P11

C C

3

1

Q2603

PMBS390 4-1-GP

2

NCT7718 _DXP

12

C2606

C2606 SC470P5 0V3JN-2GP

SC470P5 0V3JN-2GP

DY

NCT7718 _DXN

12

C2607

C2607 SC2200P 50V2KX-2GP

SC2200P 50V2KX-2GP

2.System Sensor, Put on palm rest

A00 0618

12

R2601

R2601 0R0402-P AD-2-GP

Layout Note:

C2812 close U28 01

Layout Note:

Both DXN and DX P routing 10 m il trace width and 10 mil spa cing.

3D3V_S0

R2603 18K7R2F-GPR2603 18K7R2F-GP

B B

1 2

R2604 2KR2F-3-GPR2604 2KR2F-3-GP

1 2

ALERT#

T_CRIT#

0R0402-P AD-2-GP

SML1_DA TA[18,24,76]

SML1_CL K[18,2 4,76]

THM26

1

VDD

2

D+

3

D-

T_CRIT#

ALERT#

T_CRIT#4GND

NCT7718 W-GP

74.07718.0B9

1204 change to PCH_PWROK

PCH_PW ROK[17,24,36 ]

THERM_S YS_SHDN#

SCL

SDA

6

5

Q2601

Q2601 2N7002K DW-GP

2N7002K DW-GP

8 7

ALERT#

6 5

G

S

3D3

V_S0

1

2

34

Q2602

D

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

3rd = 84.07002.I31

4th = 84.2N702.W31

1

23

602

RN2

RN2 SRN2K2J -1-GP

SRN2K2J -1-GP

4

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

12

DY

C2608

SCD1U10V2KX-5GP

12

C2610

DY

SCD1U10 V2KX-5GP

THM_SML 1_DATA

THM_SML 1_CLK

THM_SML 1_CLK THM_SML 1_DATA

12

C2609

SCD1U10V2KX-5GP

Layout Note:

Signal Routing Guideline: Trace width = 15mil

PURE_HW _SHUTDOW N# [2 4,36,76]

FAN

Layout Note:

Need 10 mil tra ce width.

0R2J-2-GP

1 2

5V_

S0

1_DAC_1[24]

FAN_TAC H1[2 4]

SC4D7U6 D3V3KX-GP

DY

FAN

C2604

_VCC_1

DY

FON

12

FAN

261

#

1

FSM

#

2

VIN

3

VOU

T

4

VSE

T

APL5606 AKI-TRG-GP

74.05606.A71

2nd = 74.02113.0E1

0R0402-P AD-2-GP

R2606

1 2

21

D2601

DY

CH551H-3 0PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

GND GND GND GND

FAN_TAC H1_C

FAN_VCC _1

12

C2603

DY

SC2200P50V2KX-2GP

8 7 6 5

FAN_TAC H1

FAN_VCC _1

1

2 3

ETY-CON3-8-GP

20.F1841.003

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal NCT7718W/Fan

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

26 10 1

1

X02

S

SID = AUDIO

5

4

3

2

1

AGND

EC2

2_VREFO [29]

C2702

C2702 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

25

26

AVSS1

AVDD1

LINE2_L

LINE2_R

LINE1_L

LINE1_R

CPVREF

MIC_CAP

MIC2_R/SLEEVE

MIC2_L/RING2

MONO_OUT

JDREF

SENSE_B

SENSE_A

12

AUD_PC_BEEP

+3V_AVDD

MIC

AUD

_AGND

+5V_AVDD

AUD_AGND

24

23

22

21

20

19

18

17

16

15

14

13

C2713 SC10U6D3V3MX-GPC2713 SC10U6D3V3MX-GP

MIC_CAP

JDREF

R2707 20KR2F-L-GPR2707 20KR2F-L-GP

AUD_SENSE_A

Layout Note:

AGND

Place close to Pin 13

DGND

12

C2710

SCD1U10V2KX-5GP

LINE1_L [29]

LINE1_R [29]

1 2

SLEEVE [29]

RING2 [29]

1 2

R2709

39K2R2F-L-GP

C2711

AGND

1 2

0R0603-PAD-2-GP-U

12

Layout Note:

Place close to Pin 26

AUD_AGND

SC4D7U6D3V3KX-GP

AUD_SENSECOMBO-GPI

DGND

5V_S0+5V_AVDD

A00 0618

R2703

AUD_AGND

Layout Note:

Width>40mil, to improve Headpohone Crosstalk noise

AUD_AGND

AUD_SENSE [29]

LIN

E1_VREFO_R[29]

LIN

E1_VREFO_L[29]

D D

C C

B B

3D3

V_S0

5V_S0 +5V_PVDD

A00 0618

1D5V_S0

3D3V_S0

25mA

1 2

R2701

0R0402-PAD-2-GP

A00 0618

1.5A

0R0805-PAD-2-GP-U

R2702

12

0R0805-PAD-2-GP-U

R2704

12

Layout Note:

Close pin41

DGND

A00 0618

0R0402-PAD-2-GP

R2710 0R2J-2-GP

R2705

1 2

DY

AGND

Azalia I/F EMI

EC2701

SCD1U10V2KX-5GP

PCH_AZ_CODEC_SDOUT1 HDA_CODEC_SDOUT

12

DY

HDA_CODEC_BITCLK_C

12

DY

EC2702

SC22P50V2JN-4GP

+3V

_AVDD

12

C2701

SC4D7U6D3V3KX-GP

C2706

12

SC4D7U6D3V3KX-GP

+3V_1D5V_AVDD

AUD_AGND

Close pin36

C2707

12

SCD1U10V2KX-5GP

12

C2715

SC4D7U6D3V3KX-GP

ER2701

47R2J-2-GP

1 2

ER2702

47R2J-2-GP

C2709

C2708

12

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

Layout Note:

Close pin46

Close pin40

12

DY

HDA_CODEC_BITCLK

DY

AUD_AGND

AMP_MUTE#[24]

C2712 SC10U6D3V3MX-GPC2712 SC10U6D3V3MX-GP

1 2

AUD_SPK_L+[29]

AUD_SPK_L-[29]

AUD_SPK_R-[29]

AUD_SPK_R+[29]

0R0402-PAD-2-GP

R2708

1 2

remove D2702 R2710 R2711 Add R2708_0R(PDB pin)

TP2702TP2702

DMIC_CLK[52]

SC22P50V2JN-4GP

Close pin3

0109 Add Close pin2

C2723

DMIC_DATA[52]

DY

1 2

HDA_CODEC_SDOUT[19]

HDA_CODEC_BITCLK[19]

HDA_SDIN0[19]

HDA_CODEC_SYNC[19]

HDA_CODEC_RST#[19,29]

SC22P50V2JN-4GP

C2724

1 2

DY

+3V_1D5V_AVDD

+5V_PVDD

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

+5V_PVDD

1

SC4D7U6D3V3KX-GP

AUD

_HP1_JACK_L[29]

AUD

_HP1_JACK_R[29]

12

C2703

C2703 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

CBP

LDO2_CAP

EAPD#

C2716

A00 0618

0R0402-PAD-2-GP

R2714

1 2

R2716

1 2

0R0402-PAD-2-GP

+3V_AVDD

HDA27

37

CBP

38

AVSS2

39

LDO2_CAP

40

AVDD2

41

PVDD1

42

SPK_L+

43

SPK_L-

44

SPK_R-

45

SPK_R+

46

PVDD2

47

PDB

48

SPDIFO/GPIO2

49

GND

ALC3223-CG-GP

+3V_AVDD

12

C2717

SCD1U10V2KX-5GP

DMIC_DATA_R

DMIC_CLK_R

0R0402-PAD-2-GP

R2718

1 2

HDA_CODEC_SYNC

HDA_CODEC_RST#

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP C2704

C2704

1 2

CPVEE

CBN

35

33

34

36

CPVDD

DVDD1GPIO0/DMIC_DATA2GPIO1/DMIC_CLK3DVSS4SDATA_OUT5BIT_CLK6LDO3_CAP7SDATA_IN8DVDD_IO9SYNC10RESET#11PCBEEP

CBN

CPVEE

HP_OUT_R

HDA_CODEC_SDIN0

32

HP_OUT_L

C2705

12

AUD_VREF

28

31

29

30

MIC2_VREFO

LINE1_VREFO_L

LINE1_VREFO_R

LDO3_CAP

C2718SC4D7U6D3V3KX-GP C2718SC4D7U6D3V3KX-GP

12

SC2D2U6D3V2MX-GP

LDO1_CAP

27

VREF

LDO1_CAP

C2719SCD1U10 V2KX-5GP C2719SCD1U10 V2KX-5GP

EC2

EC2703 SCD1U10V2KX-5GPEC2703 SCD1U10V2KX-5GP

AUD_AGND

DGND

708 SCD1U10V2KX-5GP

1 2

DY

707 SCD1U10V2KX-5GP

1 2

706 SCD1U10V2KX-5GP

1 2

705 SCD1U10V2KX-5GP

1 2

704 SCD1U10V2KX-5GP

1 2

DY

1 2

Layout Note:

Tied at point only under Codec or near the Codec

AGND

R2711 0R0603-PAD-2-GP-UR2711 0R0603-PAD-2-GP-U R2706 0R0603-PAD-2-GP-UR2706 0R0603-PAD-2-GP-U

DGND

1 2 1 2

Layout Note:

Tied at point only under Codec or near the Codec

RN

HDA_SPKR[20]

KBC_BEEP[24]

A A

5

4

1 2 3

0R4P2R-PAD

RN2701

HDA_SPKR_R

4

KBC_BEEP_R

D2701

1

2

BAT54CPT-2-GP

75.00054.K7D

2nd=75.00054.J7D

3

AUD_PC_BEEP_C

3

12

R2717

R2717 1KR2J-1-GP

1KR2J-1-GP

AUD_PC_BEEP

1 2

C2720

C2720 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Audio Codec ALC3223

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

of

27 101Friday, June 28, 2013

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

28 10 1Friday, June 28, 201 3

X02

D = AUDIO

SSI

5

4

3

2

1

A00 0618

AUD

R29

R29060R0603-P AD-2-GP-U R29060R0603-P AD-2-GP-U

12

R29070R0603-P AD-2-GP-U R29070R0603-P AD-2-GP-U

12

R29090R0603-P AD-2-GP-U R29090R0603-P AD-2-GP-U

12

R29110R0603-P AD-2-GP-U R29110R0603-P AD-2-GP-U

12

R29

12

R29

12

R29

12

AUD_POR TA_R_R_B

AUD_AGN D

D D

C C

RN2901

RN2901 SRN2K2J -1-GP

SRN2K2J -1-GP

1

MIC2_VREF O[27]

RING2[27 ]

AUD_HP1 _JACK_L[27]

LINE1_L[27]

LINE1_VRE FO_L[27]

AUD_SEN SE[2 7]

AUD_HP1 _JACK_R[27]

LINE1_R[27]

LINE1_VRE FO_R[27]

SLEEVE[2 7]

B B

C2907

C2907 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

C2908

C2908 SC4D7U6 D3V3KX-GP

SC4D7U6 D3V3KX-GP

1 2

LINE1_L_C

LINE1_R_C

4

2 3

R2908 10R2F-L -GPR2908 10R2F-L -GP

1 2

R2921 1KR2J-1 -GPR2921 1KR2J-1 -GP

1 2

R2912 2K2R2J -2-GPR2912 2K2R2J -2-GP

1 2

R2910 10R2F-L -GPR2910 10R2F-L -GP

1 2

R2922 1KR2J-1 -GPR2922 1KR2J-1 -GP

1 2

R2913 2K2R2J -2-GPR2913 2K2R2J -2-GP

1 2

AUD

_SPK_R+[27]

AUD

_SPK_R-[27] _SPK_L+[27]

AUD AUD_SPK _L-[27]

AUD_HP1 _JACK_L1

AUD_HP1 _JACK_R1

12

DY

EC2901

SC2K2P50V3KX-GP

DY

EC2902

EC2903

SC2K2P50V3KX-GP

12

DY

EC2904

SC2K2P50V3KX-GP

A00 0618

SC100P50V2JN-3GP

EC2907

EC2908

10KR2J-3-GP

R2919

12

SC100P50V2JN-3GP

EC2906

EC2905

10KR2J-3-GP

R2920

12

EC2905

12

DY

AUD_AGN DAUD_AGND

_SPK_R+ _C

040R0603-PAD-2 -GP-U

AUD

_SPK_R-_ C

030R0603-PAD-2 -GP-U

_SPK_L+ _C

020R0603-PAD-2 -GP-U

AUD AUD

_SPK_L-_ C

010R0603-PAD-2 -GP-U

RING2_R

AUD_POR TA_L_R_B

SLEEVE_ R

Speaker

1

2 3 4

ACES-CON 4-7-GP-U

20.F0772.004

AUD_SPK _L-_C AUD_SPK _L+_C AUD_SPK _R-_C AUD_SPK _R+_C

Universal jack

AUD_AGN D

AUD_POR TA_L_R_B AUD_POR TA_R_R_B

AUD_SEN SE

SPK

1

5

6

HPMIC1

3 1

5 6 2 4

MS

AUDIO-JK40 4-GP

22.10270.V01

1 1 1 1

AFTP290 6AFTP2906 AFTP290 7AFTP2907 AFTP290 8AFTP2908 AFTP290 9AFTP2909

AFTP290 1AFTP2901 AFTP290 2AFTP2902 AFTP290 3AFTP2903 AFTP290 4AFTP2904

CONN Pin

Pin1

Pin2

Pin3

Pin4

Net name

SPK_R+

SPK_R-

SPK_L+

SPK_L_

R2918

100KR2J -1-GP

D

34

GG

2

S

1

3

+3V_AVD D

POP_G2POP_G1

12

DY

12

C2901

DY

SC1U6D3 V2KX-GP

0R0402-P AD-2-GP

R2917

1 2

HDA_COD EC_RST# [19 ,27]

SLEEVE [27]

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Speaker/HPMIC CONN

Size Document N umber Rev

A3

Date: Sheet of

Speaker/HPMIC CONN

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

29 10 1Friday, June 28, 201 3

1

X02

AUD_POR TA_R_R_B

AUD_POR TA_L_R_B

RING2_R

AUD_SEN SE

SLEEVE_ R

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2904

75.02025.077

DY

AZ2025-01H-R7G-GP

ED2905

12

4

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2903

75.02025.077

AZ2025-01H-R7G-GP

DY

12

AZ2025-01H-R7G-GP

ED2902

75.02025.077

AZ2025-01H-R7G-GP

ED2

12

901

A A

DY

75.02025.077

5

5V_PW R_2

12

AUD_AGN D

R2915

R2915 220KR2J -L2-GP

220KR2J -L2-GP

U2901

S

5

D

6

2N7002K DW-GP

5

D = LOM

SSI

V_S5

3D3

12

SCD1U10V2KX-5GP

C3013

Q3001

G

S

2N7002K -2-GP

1 2

12

D D

PM_LAN_ ENABLE[2 4]

100KR2J -1-GP

3D3V_LA N_S5 VDDREG

C C

12

C3007

SCD

1U10V2KX-5GP

12

R3023

DY

R3006 0R0603-PAD -2-GP-UR3006 0R0603-PAD -2-GP-U

12

C3012

C3008

SCD

1U10V2KX-5GP

D

LAN_SW

R30

R30 10KR2J-3 -GP

10KR2J-3 -GP

LAN_ENABLE_R_C

12

C3009

SCD1U10V2KX-5GP

21

R30

22

20KR2F-L -GP

1 2

LAN_SW

12

C3010

PM_

LAN_ENA BLE_R

main: 84.00102.031 2nd: 84.03403.031

SC4D7U6D3V3KX-GP

X5R

A00 0618

R3034 0R0603-PAD -2-GP-UR3034 0R0603-PAD -2-GP-U

1 2

B B

12

DY

C3018

SCD

1U10V2KX-5GP

L3010

1 2

IND-4D7UH-2 42-GP

LAN_SW

68.4R71E.10G

LAN_SW

C3024

12

SC4D7U6D3V3KX-GP

C3014

12

LAN_SW

SCD1U10V2KX-5GP

A00 0618

0R0603-P AD-2-GP-U

R3007

1 2

X5R

A A

5

12

03

C30

C30 SC1U6D3 V2KX-GP

SC1U6D3 V2KX-GP

0311 modify power railA00 0618

12

4

PA102FM G-GP-U

PA102FM G-GP-U Q30

Q30

04

G

3D3V_LA N_S5

12

C3019

C3020

SCD1U10V2KX-5GP

4

DS

R3039

R3039 10KR2J-3 -GP

10KR2J-3 -GP

LAN_W AKE#

12

C3021

SCD1U10V2KX-5GP

EVDD10

12

C3016

SCD1U10V2KX-5GP

3D3

V_LAN_S 5

12

DY

05

C30

SCD1U10V2KX-5GP

Pin12 Pull VCC33 (3D3V_S0) Supported RTD3

12

C3022

SCD1U10V2KX-5GP

12

C3023

SC1U6D3V2KX-GP

ENSW REG

CLK_PCIE_ LAN_REQ4#[18]

LAN

LANXIN

LAN_W AKE#[24]

XOUT

3

41

2 3

C3001

1 2

SC15P50 V2JN-2-GP

3D3V_LA N_S5

12

LAN_SW

12

0110 add CAP need close to chip

3D3V_S0

12

LAN_TXP _C_PCH_RXP4 LAN_TXN _C_PCH_RXN4

PCIE_PTX_ LANRX_P4_C PCIE_PTX_ LANRX_N4_C

3

C30

11

1 2

SC15P50 V2JN-2-GP

X30

01

XTAL-25M HZ-155-GP

R3036

R3036 0R2J-2-GP

0R2J-2-GP

A00 0618

R3037

R3037 0R0402-P AD-2-GP

0R0402-P AD-2-GP

VDD10 VDD10 VDD10

VDD10

EVDD10

3D3V_LA N_S5 3D3V_LA N_S5

3D3V_LA N_S5

SCD1U10V2KX-5GP

C3028

LAN_W AKE# ISOLATE#

PLT_RST #_LAN

CLK_PCIE_ LAN_P4 CLK_PCIE_ LAN_N4

PCIE_PTX_ LANRX_P4_C PCIE_PTX_ LANRX_N4_C

LAN_TXP _C_PCH_RXP4 LAN_TXN _C_PCH_RXN4

CARD_3D 3V

VDDREGVDD10REGOUT

C3025 SCD1U10 V2KX-5GPC 3025 SCD1U10V2KX-5G P

1 2 1 2

C3026 SCD1U10 V2KX-5GPC 3026 SCD1U10V2KX-5G P

Close To Pin 27

VDD33/18

U3001

3

AVDD10

8

AVDD10

46

AVDD10

33

DVDD10

20

EVDD10

11

AVDD33

48

AVDD33

12

DVDD33

32

DVDD33

13

CARD_3V3

27

VDD33/18

35

VDDREG

39

LANWAKE#

31

ISOLATE#

29

CLKREQ#

30

PERST#

23

REFCLK_P

24

REFCLK_N

21

HSIP

22

HSIN

25

HSOP

26

HSON

RTL8411 B-CGT-GP

71.08411.D03

2

A00 0618

0R0603-P AD-2-GP-U

R30

08

1 2

12

C3017

C3027

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

DY

1

MDIP0

2

MDIN0

4

MDIP1

5

MDIN1

6

MDIP2

7

MDIN2

9

MDIP3

10

MDIN3

44

CKXTAL1

45

CKXTAL2

REGOUT

RSET

LED_CR

LED0

LED1/GPO

LED3

SD_D1

SD_CD#

MS_CD#

GND

2

34 36 47

40 41 38 37

15 14 19 18

16 17 28

42 43

49

ENSWREG_H

SD_D0/MS_D1

SD_D2/MS_CLK

SD_D3/MS_D3

SD_CLK/MS_D0

SD_SMD/MS_D2

SD_WP/MS_BS

PCIE_PRX_ LANTX_P4 [1 6] PCIE_PRX_ LANTX_N4 [16]

PCIE_PTX_ LANRX_P4_C [16] PCIE_PTX_ LANRX_N4_C [16]

CLK_PCIE_ LAN_P4 [18] CLK_PCIE_ LAN_N4 [18]

D_3D3V

CAR

LANXIN LANXOUT

ENSW REG REGOUT RSETVDD33/18

LED_CR LED0 LED1 LED3

SP2 SP1 SP6 SP5

SP3 SP4 SP7

1

V_S0

Clo

se To Pin 13

12

C30

15

SCD1U10V2KX-5GP

DY

PLT_RST #[17,24,58,6 5,73]

LAN_MDI0P [31] LAN_MDI0N [31 ] LAN_MDI1P [31] LAN_MDI1N [31 ] LAN_MDI2P [31] LAN_MDI2N [31 ] LAN_MDI3P [31] LAN_MDI3N [31 ]

TP3004 T PAD14-OP-GPTP3004 TPA D14-OP-GP

1

TP3003 T PAD14-OP-GPTP3003 TPA D14-OP-GP

1

TP3002 T PAD14-OP-GPTP3002 TPA D14-OP-GP

1

TP3001 T PAD14-OP-GPTP3001 TPA D14-OP-GP

1

A00 0618

R3017 0R0402-P AD-2-GPR3017 0R0 402-PAD-2-GP

12

R3018 0R0402-P AD-2-GPR3018 0R0 402-PAD-2-GP

12

R3019 0R0402-P AD-2-GPR3019 0R0 402-PAD-2-GP

12

R3020 0R0402-P AD-2-GPR3020 0R0 402-PAD-2-GP

12

R3032 0R0402-P AD-2-GPR3032 0R0 402-PAD-2-GP

12

R3033 0R0402-P AD-2-GPR3033 0R0 402-PAD-2-GP

12

R3035 0R0402-P AD-2-GPR3035 0R0 402-PAD-2-GP

12

Title

Size Document N umber Rev

A3

Date: Sheet of

LOM(RTL8411B)

3D3

R3038

2K49R2F -GP

Hadley 15"

12

ISO

14

R30

15KR2F-G P

1

4

3

12

30 10 1Friday, June 28, 201 3

LATE#

12

15

DY

PLT_RST #_LAN

A00 0618

1 2

R30

1KR2J-1-G P

3D3V_LA N_S5

23

RN3001

DY

SRN10KJ -5-GP

Q402_1

1

2

DY

Q3003

Q3003 PMBS390 4-1-GP

PMBS390 4-1-GP

R3016

0R0402-P AD-2-GP

SP2/SD_D 0/MS_D1 [33] SP1/SD1 [33] SP6/SD_D 2/MS_CLK [33] SP5/SD_D 3/MS_D3 [33]

SP3/SD_C LK/MS_D0 [33] SP4/SD_C MD/MS_D2 [33] SP7/SD_W P/MS_BS [33]

SD_CD# [33] MS_CD# [33]

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

X02

5

D = LOM

SSI

GIG

D D

LAN_MDI3N[30]

LAN_MDI3P[30]

LAN_MDI2N[30]

LAN_MDI2P[30]

LAN_MDI1N[30]

LAN_MDI1P[30]

_TCT

LOM

C C

12

C3106

C3106 SCD01U1 6V2KX-3GP

SCD01U1 6V2KX-3GP

LAN_MDI0N[30]

LAN_MDI0P[30]

1 2

DY

EC3108 SC 10P50V2JN-4GP

1 2

DY

EC3107 SC 10P50V2JN-4GP

1 2

DY

EC3106 SC 10P50V2JN-4GP

1 2

DY

EC3105 SC 10P50V2JN-4GP

1 2

DY

EC3104 SC 10P50V2JN-4GP

1 2

DY

EC3103 SC 10P50V2JN-4GP

1 2

DY

EC3102 SC 10P50V2JN-4GP

1 2

DY

EC3101 SC 10P50V2JN-4GP

A LAN TransFormer

Follow Reference Schematic 0.01uF~0.4uF

4

101

XF3

2

1

3

1:1

5

4

6

1:1

8

7

9

1:1

11

10

12 13

1:1

XFORM-24 P-63-GP

68.89240.30D

3

1

MDO

23

MCT0

24

22

20

MCT1

21

19

17

MCT2

18

16

14

MCT3

15

3-

MDO3+

MDO2-

MDO2+

MDO1-

MDO1+

MDO0-

MDO0+

MCT

MCT0

MCT3

MCT2

45

678

MCT

12

Layout: Place near RJ45

AFTP310 7AFTP3107 AFTP310 2AFTP3102 AFTP310 1AFTP3101 AFTP310 3AFTP3103 AFTP310 4AFTP3104 AFTP310 6AFTP3106 AFTP310 5AFTP3105 AFTP310 8AFTP3108

123

RN3101

RN3101 SRN75J-1 -GP

SRN75J-1 -GP

C3101

C3101 SC100P3 KV8JN-2-GP

SC100P3 KV8JN-2-GP

78.1013N.1AL

1 1 1 1 1 1 1 1

MDO0+ MDO0MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

2

U3101

LAN_MDI0P LAN_MDI0P LAN_MDI0N LAN_MDI0N

LAN_MDI1P LAN_MDI1P LAN_MDI1N LAN_MDI1N

LAN_MDI2P LAN_MDI2N

LAN_MDI3P LAN_MDI3N

91 8

2

3

DY

7

4

6

5

ESD3V3U 4ULC-GP

83.3V3U4.0A0

U3102

91 8

2

3

DY

7

4

6

5

ESD3V3U 4ULC-GP

83.3V3U4.0A0

MDO0+

MDO0MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3-

LAN_MDI2P LAN_MDI2N

LAN_MDI3P LAN_MDI3N

RJ45

9 1

2 3 4 5 6 7 8

10

RJ45-8P-1 18-GP-U

22.10019.141

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RJ45+Transformer

Size Document N umber Rev

A3

Date: Sheet of

RJ45+Transformer

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

31 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

1

32 10 1Friday, June 28, 201 3

X02

SSI

D = SDIO

5

4

3

2

1

D_3D3V_ S0

D D

C C

CAR

12

C3303

SCD1U10V2KX-5GP

Close To Pin11 SD_VCC

AFT

P3308

Close To Pin 4 MS_VCC

12

C3302

C3304

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

P3308

SD_CD#[30] SP5/SD_D 3/MS_D3[30]

SP3/SD_C LK/MS_D0[30] SP4/SD_C MD/MS_D2[30]

SP2/SD_D 0/MS_D1[30] SP1/SD1[30] SP6/SD_D 2/MS_CLK[30]

SP7/SD_W P/MS_BS[30]

Reserve EMI Cap, 0107 CLK Cap DY

SP1/SD1 SP2/SD_D 0/MS_D1 SP3/SD_C LK/MS_D0 SP4/SD_C MD/MS_D2 SP5/SD_D 3/MS_D3 SP6/SD_D 2/MS_CLK SP7/SD_W P/MS_BS

SC4D7P50V2BN-GP

EC3301

EC3302

EC3303

DY

EC3303

12

B B

DY

12

DY

SC4D7P50V2BN-GP

EC3304

12

DY

D_3D3V_ S0

CAR

D1

1

SC4D7P50V2BN-GP

DY

SC4D7P50V2BN-GP

EC3307

12

EC3305

EC3306

12

DY

SD_VDD/MMC_VDD11MS_DATA0

4

MS_VCC

20

SD_CD

3

SD_CD/DAT3/MMC_RSV

14

SD_SLK/MMC_CLK

6

SD_CMD/MMC_CMD

18

SD_DAT0/MMC_DAT

19

SD_DAT1

1

SD_DAT2

22

SD_WP/SW

NP1

NP2

CARDBUS 22P-SKT-2-GP-U

62.10051.H21

AFTP330 1AFTP3301 AFTP330 2AFTP3302 AFTP330 3AFTP3303 AFTP330 4AFTP3304 AFTP330 5AFTP3305 AFTP330 6AFTP3306 AFTP330 7AFTP3307

SD_VSS/MMC_VSS1 SD_VSS/MMC_VSS2

1 1 1 1 1 1 1

SP1/SD1 SP2/SD_D 0/MS_D1 SP3/SD_C LK/MS_D0 SP4/SD_C MD/MS_D2 SP5/SD_D 3/MS_D3 SP6/SD_D 2/MS_CLK SP7/SD_W P/MS_BS

MS_DATA1 MS_DATA2 MS_DATA3

MS_INS

MS_BS

MS_SCLK

GND GND

SD_GND

MS_VSS MS_VSS

12 13 10 7

8 15 5

23 24

21

16 2

9 17

1

AFTP330 9AFTP3309

SP3/SD_C LK/MS_D0 [30] SP2/SD_D 0/MS_D1 [30] SP4/SD_C MD/MS_D2 [30] SP5/SD_D 3/MS_D3 [30]

MS_CD# [30] SP7/SD_W P/MS_BS [30] SP6/SD_D 2/MS_CLK [30]

layout note: EC3305 need colse to chip

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Card Reader CONN

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

33 10 1Friday, June 28, 201 3

1

X02

5

SSI

D D

AFTP340 3AFTP3403 AFTP340 2AFTP3402

= USB

D

AFT

USB20_D N1_C

1

USB20_D P1_C

1

P

3407

USB

0_VCCA

3

1

USB20_D N1_C USB20_D P1_C

USB3.0 Port1 with power share

USB

1

VBU

S

STD

2

D-

3

D+

10 11 12 13

STDA_SSTX+

10 11 12 13

KT-USB13 -144-GP

S

22.10339.W31

STD

STDA_SSTX-

GND_DRAIN

_SSRX-

A

_SSRX+

GND

5 6

8 9

4 7

A00 0618

USB30_T XDN0_R

USB3_PT X_CRX_N0[16]

C C

1 2

C3401

SCD1U10 V2KX-5GP

R3404

1 2

0R0402-P AD-2-GP

USB30_T XDN0_C

A00 0618

USB30_T XDP0_R

USB3_PT X_CRX_P0[16]

1 2

C3402

SCD1U10 V2KX-5GP

R3406

1 2

0R0402-P AD-2-GP

USB30_T XDP0_C

A00 0618

R3405

USB3_PR X_CTX_N0[16]

B B

1 2

0R0402-P AD-2-GP

USB30_R XDN0_C

A00 0618

R3407

USB3_PR X_CTX_P0[16]

1 2

0R0402-P AD-2-GP

USB30_R XDP0_C

4

USB

0_RXDN0 _C

3

0_RXDP0 _C

USB

USB30_T XDN0_C

USB30_T XDP0_C

USBDET1 #

1

USB_PP1 _R[35]

USB_PN1 _R[35]

USB30_T XDP0_C

USB30_T XDN0_C

USB30_R XDP0_C

USB30_R XDN0_C

1 2

R3402

R3402 0R0402-P AD-2-GP

0R0402-P AD-2-GP

AFTP340 1AFTP3401

X02 stuff TR3403

1 2

FILTER-4P-6 2-GP

69.10080.021

2nd = 69.10103.061

U3401

1

2

3

4 5

AZ1065-0 6Q-GP

83.01065.0AJ

X01 0321

USBDET_ CON# [24]

A00 0618

TR3403

34

A00 0618

USB30_V CCA

8

7

USB20_D P1_C

6

USB20_D N1_C

USB20_D P1_C

USB20_D N1_C

3

2

1

USB3.0 Port2

USB

0_VCCB

3

USB

0_TXDP1 _C

USB USB

USB

3

0_TXDN1 _C

3

0_DN0_C

2

0_DP0_C

2 3

0_RXDP1 _C

3

0_RXDN1 _C

AFT

AFT AFT

AFT

3408

P

USB

3405

P

P P

P

3406

0_DN0_C

2

1

2

0_DP0_C

USB

1

A00 0618

USB30_T XDN1_R

USB3_PT X_CRX_N1[16]

1 2

C3407

SCD1U10 V2KX-5GP

R3441

1 2

0R0402-P AD-2-GP

USB30_T XDN1_C

A00 0618

USB30_T XDP1_R

USB3_PT X_CRX_P1[16]

1 2

C3409

SCD1U10 V2KX-5GP

R3415

1 2

0R0402-P AD-2-GP

USB30_T XDP1_C

A00 0618

R3424

USB3_PR X_CTX_N1[16]

1 2

0R0402-P AD-2-GP

USB30_R XDN1_C

A00 0618

R3423

USB3_PR X_CTX_P1[16]

1 2

0R0402-P AD-2-GP

USB30_R XDP1_C

2

USB

CHASSIS

1

0 9 1

8 2 7 3 6 4 5

11 12

CHASSISCHASSIS

S

KT-USB13 -32-GP-U

22.10341.531

USB_PP0[16]

USB_PN0[16]

USB20_D N0_C

USB20_D P0_C

USB30_R XDP1_C

USB30_R XDN1_C

1

3

1

2

3

4 5

AFTP340 4AFTP3404

1

X02 stuff TR3412

A00 0618

TR3412

1 2

FILTER-4P-6 2-GP

69.10080.021

2nd = 69.10103.061

A00 0618

8

7

USB30_T XDN1_C

6

USB30_T XDP1_C

USB30_V CCB

U3403

AZ1065-0 6Q-GP

83.01065.0AJ

USB20_D P0_C

34

USB20_D N0_C

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

USB3.0(1)

1

34 10 1Friday, June 28, 201 3

X02

SSI

D = USB

5

4

3

2

1

5V_

S5

C35

01

SC1U6D3V2KX-GP

D D

USB_PW R_EN#[24]

C C

12

5V_S5

SC1U6D3V2KX-GP

C3505

12

USB_PW R_EN#[24]

U35

02

1

GND

2

VIN

3

VIN EN#4OC#

UP7534Q RA8-15-GP

74.07534.C79

2nd = 74.06288.A79

3rd = 74.02000.B71

U3503

1

GND

2

IN

3

EN1# EN2#4FLG2

AP2182S G-13-GP

74.02182.071

VOU VOU VOU

FLG1 OUT1 OUT2

8

T#8

7

T#7

6

T#6

5

8 7 6 5

USB

_OC#0_1 [16]

USB30_V CCC USB30_V CCD

USB_OC# 2_3 [1 6]

0319 modify USB Charger circuit

C35

12

02

SCD1U10V2KX-5GP

USB

30_VCCB

C35

07

SC1U6D3V2KX-GP

12

C35

04

SC100U6 D3V6MX-GP

78.10710.52L

If MLCC is used as Main Source. Inform Layout team to remark Pin 1 as positive. In case MLCC shortage and other type of Cap With Polarity Is Used.

A00 0618

R3505

USBCHG_ EN[24]

U3501

SB#

U3501

9 8 7 6 5

INT

GND

D-

SB/

D+

Y-

SEL

Y+ VDD

PI5USB145 8AZAEX-GP

74.51458.073

1 2 3 4

A00 0618

0R0402-P AD-2-GP

R3502

1 2

USB_PN1[16] USB_PP1[1 6]

5V_S5

12

C3510

SCD1U10V2KX-5GP

B B

1 2

0R0402-P AD-2-GP

USBCHG_ EN_R

SEL

USB_PN1 _R [34]USBCHAR GER_CB0[24] USB_PP1 _R [34 ]

5V_S5

12

R3503

R3503 100KR2J -1-GP

100KR2J -1-GP

Q3502

G

S

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

5V_S5

12

R3501

R3501 100KR2J -1-GP

100KR2J -1-GP

D

USBCHG_ EN#

12

R3504

10KR2J-3 -GP

DY

5V_S5 USB30_V CCA

C3503

SC1U6D3V2KX-GP

12

A A

USB Power SW (U3504)

Vendor Vendor P/N Wistron P/N

Silergy

DII (Diodes)

GMT

5

SY6288DCAC

AP2301MPG-13

G547I2P81U

74.06288.A79

74.02301.071

74.00547.F79

Priority

1ST

2ND

3RD

USBCHG_ EN#

4

U3504

1

GND

VOUT#8

2

VIN

VOUT#7

3

VIN

VOUT#6

EN#4OC#

UP7534Q RA8-15-GP

74.07534.C79

2nd = 74.06288.A79

3rd = 74.02000.B71

8 7 6 5

USB_OC# 0_1 [1 6]

3

C3511

C3512

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

12

C3506

C3506 SC100U6 D3V6MX-GP

SC100U6 D3V6MX-GP

78.10710.52L

If MLCC is used as Main Source. Inform Layout team to remark Pin 1 as positive. In case MLCC shortage and other type of Cap With Polarity Is Used.

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

2

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

USB Power SW

1

X02

35 10 1Friday, June 28, 2013

X02

12

5

SSI

D = Reset.Suspend

Pow

D D

er Good

A00 0618

R3610 0R0402-P AD-2-GPR3610 0R0 402-PAD-2-GP

1D35V_V TT_PWRGD[49]

1D05V_V TT_PWRGD[7,48]

12

R3611 0R0402-P AD-2-GPR3611 0R0 402-PAD-2-GP

12

4

V_S0

3D3

12

R3601

R3601 1KR2J-1-G P

1KR2J-1-G P

ALL_SYS_PW RGD [24]

3

2

1

ROSA Run Power

C C

B B

3D3V_AU X_S5

3V_5V_E N[45 ]

1 2

DY

R3607

100KR2J -1-GP

PM_SLP_ S3#[1 7,24,48,49,51]

PCH_PW ROK[17,24,26 ]

200KR2J -L1-GP

R3602

PS_S3CN TRL

D G

S

12

DY

S

5

6

DY

123 4

G

D

Q3603

Q3603 2N7002K DW-GP

2N7002K DW-GP

84.2N702.A3F

0R0402-P AD-2-GP

D3602

D3602 BAS16-6-G P

BAS16-6-G P

2

1

1 2

R3603

1KR2J-1-G P

A00 0618

R3609

12

3

83.00016.K11

2ND = 83.00016.F11

5V_S5

3V_5V_S 0_EN

3D3V_S5

PURE_HW _SHUTDOW N# [2 4,26,76]

S5_ENAB LE [24]

U3601

1

VIN1#1

2

VIN1#2

3

ON1

4

VBIAS

5

ON2

6

VIN2#6

7

VIN2#7

TPS2296 6DPUR-GP

74.22966.093

GND VOUT1#14 VOUT1#13

CT1

GND

CT2 VOUT2#9 VOUT2#8

5V_S0

15 14 13 12 11 10 9 8

CT2

CT1

SC470P50V2KX-3GP

C3601

C3602

12

3D3V_S0

SC470P50V2KX-3GP

12

SC10U6D3V3MX-GP

C3604

5V_S0

SC10U6D3V3MX-GP

C3603

5V_S0 Comsumption Peak current 4.033A

3D3V_S0

3D3V_S0 Comsumption Peak current 3A

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Power Plane Enable

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

36 10 1

1

X02

5

D = Reset.Suspend

SSI

D D

4

3

2

1

12

+V_SM_V REF_CNT[5]

R3706

R3706 1K8R2F-G P

1K8R2F-G P

R3703

R3703 1K8R2F-G P

1K8R2F-G P

2R2F-GP

2R2F-GP R3708

R3708

1 2

12

C3701

C3701 SCD022U 16V2JX-GP

SCD022U 16V2JX-GP

+V_VREF _PATH3

12

R3707

R3707 24D9R2F -L-GP

24D9R2F -L-GP

Close to DIMM S3 Power Reduction Circuit PM_DRAM_PWRGD

Layout Note:

Place Close SO-DIMMA.

C C

B B

SA_DIMM_VREFDQ

SODIMM1

M_VREF_ CA_DIMMA

0D675V_ VTTREF 1D35V_S 3

0R2J-2-GP

0R2J-2-GP R3704

R3704

1 2

DY

12

R3705

R3705 0R0402-P AD-2-GP

0R0402-P AD-2-GP

SB_DIMM_VREFDQ

SODIMM2

M_VREF_ CA_DIMMB

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

S3 Power Reduction

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

37 10 1

1

X02

5

D = Reset.Suspend

SSI

D D

4

3

2

1

3D3V_S5 3D3V_S5 _PCH

3D3V_S5

SCD47U16V2ZY-GP

C3801

12

DS3

C C

DS3_PW RCTL

R3802

PM_SLP_ SUS#[17,24]

1 2

0R0402-P AD-2-GP

A00 0618

B B

0R3J-0-U-G P

0R3J-0-U-G P R3801

R3801

1 2

Non DS3

U3801

DS3

1

GND

OUT#8

2

IN#2

OUT#7

3

IN#3

OUT#6

EN/EN#4OCB

SY6288CCA C-GP

74.06288.079

3D3V_S5 _PCH

8 7 6 5

SCD47U16V2ZY-GP

C3802

12

DS3

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

DSW

1

38 10 1Friday, June 28, 201 3

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

39 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

40 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

41 10 1

1

X02

5

SSI

D = PWR.Support

D D

0103 Add EC4203

ndde close to EL4202

JGND

SCD1U50 V5JX-1-GP

SCD1U50 V5JX-1-GP EC4203

EC4203

1 2

DY

EL4202

EL4202 PAD-2P-45 16-GP-U

PAD-2P-45 16-GP-U

DCIN1

6 NP1 1

2 3

C C

ACES-CON 5-27-GP

20.F2182.005

B B

4 5 NP2 7

1

AFTP420 5AFTP4205

AC_IN_KBC #[24]

1

+DC_IN_C

DY

JGND

1

2

AFTP420 3AFTP4203

SC10U25V5KX-GP

12

EC4201

JGND

Lay

out Note:

PSID Layout width > 25mil

1

A00 0619

SCD1U25V2KX-GP

EC4202

12

1

2

EL4201

PAD-2P-45 16-GP-U

1

2

EL4203

EL4203 PAD-2P-45 16-GP-U

PAD-2P-45 16-GP-U

PR4215

PR4215 100KR2J -1-GP

100KR2J -1-GP

AFTP420 4AFTP4204

12

PS_ID_R

PR4214

PR4214 100KR2J -1-GP

100KR2J -1-GP

AC_IN#_G

4

A00 0618

0R0603-P AD-2-GP-U

PR4219

1 2

PQ4206

3 4

2

1

2N7002K DW-GP

PS_ID_R2

1

2

DY

3

12

PR4216

3K3R6J-G P

PQ4206_ 3

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

5

6

15KR2F-G P

100KR2J -1-GP

PD4204

PD4204 PESD24V S2UT-GP

PESD24V S2UT-GP

1 2

PR4212

1KR2J-1-G P

PR4

202

211

3

1 2

PQ3

802_1

1

1 2

PQ4201

FDV301N -NL-GP

D

1 2

33R2J-2-G P

PQ4204

R1

B

R2

PDTC124 EU-1-GP

84.00124.H1K

2nd = 84.05124.011

PWR_ CHG_AD_OFF_R

84.03904.L06

2nd = 84.03904.P11

2

PMBS390 4-1-GP

PMBS390 4-1-GP PQ4

PQ4

3

PSI

G

84.00301.A31

2nd = 84.3K329.031

PR4208

DY

KA

PD4201

PD4201 1SMB22A T3G-GP-U1

1SMB22A T3G-GP-U1

83.22R03.03G

C

E

202

D_DISABLE #_R_C

SD

AD_OFF_ L

DT MODE

5V_

S5

12

PR4

PR4 10KR2J-3 -GP

10KR2J-3 -GP

PS_ID

12

B

203

PC4202

PC4202 SCD1U25 V3KX-GP

SCD1U25 V3KX-GP

PQ4205

R2

E

R1

C

PDTA124 EU-1-GP

84.00124.K1K

2nd = 84.05124.A11

PR4207

1 2

33R2J-2-G P

AD_OFF_ R

3D3V_S5

DY

2

1 2

12

PC4201

PR4210

47KR3J-L -GP

PR4213

PR4213 10KR2J-3 -GP

10KR2J-3 -GP

1

3D3

V_S5

3D3

1

2

203

PD4

PD4 BAV99-12 -GP

BAV99-12 -GP

3

75.00099.E7D

2nd = 75.03101.07D

PU4201

S

D

S

1

240KR3-GP

2 3 4 5

SI7121DN-T 1-GE3-GP

DY

PC4208

SC1U25V3KX-1-GP

12

PR4209

SC1U25V5KX-1GP

12

D

S

S S

S G D

G D

Id=-9.6A Qg=-25nC Rdson=18~30mohm

12

PQ3808D

8

D

7

D

6

PQ4208

DY

D

2N7002K -2-GP

84.2N702.J31

V_S5

12

206

PR4

PR4 2K2R2J-2 -GP

2K2R2J-2 -GP

PSID_EC [24]

AD++DC_IN

12

PC4205

PC4206

SC10U25V5KX-GP

SCD01U50V2KX-1GP

PR4217

PQ3808G

DY

12

1 2

DY

1KR2J-1-G P

PC4209

G

S

SCD01U50V2KX-1GP

PWR_ CHG_AD_OFF[24]

PR4218

12

DY

100KR2J -1-GP

PQ3807D

1 2

DY

H_PROCH OT#[4,24,44,4 6]

A A

5

4

3

DY

PC4207

PC4207 SC1U6D3 V2ZY-GP

SC1U6D3 V2ZY-GP

PQ4203

1

6

2

5

DY

3 4

DMN66D0 LDW-7-GP

2

Title

Size Document N umber Rev

A3

Date: Sheet of

BAT_IN#

BAT_IN# [24,43 ,44]

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DCIN

Hadley 15"

1

SCD01U50V2KX-1GP

X02

42 10 1Friday, June 28, 201 3

X02

5

SSI

D = PWR.Support

4

3

2

1

D D

SRN100J -4-GP

SRN100J -4-GP RN4301

RN4301

1

BAT_SCL[24,44,53] BAT_SDA[24,44,5 3] BAT_IN#[24,42 ,44]

SC10P50V2JN-4GP

EC4303

C C

DY

12

DY

1 2

SC10P50V2JN-4GP

EC4301

EC4302

12

DY

2 3 4 5

8 7 6

BT+

C4301

SCD1U50 V3KX-GP

C4301

DY

12

EC4304

DY

SC2200P 50V2KX-2GP

1 2

R4303

R4303 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PBAT_SM BCLK1 PBAT_SM BDAT1 PBAT_PR ES1# SYS_PRES1#

Battery CONN

BATT1

10

8 7 6 5 4 3 2

1 9

SYN-CON8-28-G P

20.82045.008

AFTP430 1AFTP4301 AFTP430 2AFTP4302 AFTP430 3AFTP4303 AFTP430 4AFTP4304 AFTP430 5AFTP4305

PBAT_PR ES1#

1

PBAT_SM BDAT1

1

PBAT_SM BCLK1

1

BT+

1

SYS_PRES1#

1

0109 DY PD4301~4303

BAT_SCLBAT_ IN# BAT_SDA

3

PD4303

PD4303 BAV99-12 -GP

BAV99-12 -GP

1

2

75.00099.E7D

2nd = 75.03101.07D

B B

3

1

2

75.00099.E7D

2nd = 75.03101.07D

PD4302

PD4302 BAV99-12 -GP

BAV99-12 -GP

3

1

2

75.00099.E7D

2nd = 75.03101.07D

PD4301

PD4301 BAV99-12 -GP

BAV99-12 -GP

3D3V_AU X_KBC

Layout Note:

Place near Batt ery CONN

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

BATT CONN

1

43 10 1Friday, June 28, 201 3

X02

5

SSI

D = Charger

D D

AD+

12

DY

12

PR4452

100KR2J-1-GP

DY

3D3V_S5

12

PR4431

DY

12

DY

PQ4406_G

G

DY

A00 0618

PR4462

0R0402-PAD-2-GP

PR4463

0R2J-2-GP

DY

BQ24715_AGND

3K3R2J-3-GP

BAT_SDA[24,43,53]

BAT_SCL[24,43,53]

PQ4412_2

100KR2F-L1-GP

PC4414

PC4414 SCD47U6D3V2KX-1- GP

SCD47U6D3V2KX-1- GP

12

DY

1 2

PQ4405_3

PQ4405_2

12

DY

PWR_CHG_ACOK

KBC FOR DT MODE CHECK EE PULL HIGH

3D3V_AUX_S5

150KR2F-L-GP

PWR_CHG_REG N

PR4

434

12

C C

PR4

100KR2F-L1-GP

DY

419

DY

12

PR4

33KR2F-GP

415

DY

DIS_DTM: H= cell is plus to GND. (reset charger ic) L=nornal

12

PR4449

PR4449 100KR2J-1-GP

100KR2J-1-GP

Follow custormer circuits

1 2

DIS_DTM[24]

DY

PC4409

SC1U25V3KX-1-GP

B B

CHECK EE

PQ4406

PQ4406 2N7002K-1-GP

2N7002K-1-GP

84.2N702.031

PR4433

PD4403_A

PMBS3906-GP

84.03906.F11

680KR2F-GP

PQ4406_D

12

DY

1

PR4451

AD+

12

408_E

PQ4

2

3

12

5

84.2N702.031

D S

416

PR4

100KR2J-1-GP

PQ4408

PQ4408_C

H_PROCHOT#[4,24,42,46]

0R2J-2-GP

A A

A00 0618

CHECK EE follow custormer circuits.

PR4459

15V_S5

DY

1 2

1N4148WS-7- F-GP

PD4403_K

1 2

DCBATOUT

DY

1 2

PR4456

PR4456 0R2J-2-GP

0R2J-2-GP

1MR2J-1-GP

PD4403

K A

PR4458

PR4458 0R0402-PAD-2-GP

0R0402-PAD-2-GP

309KR2F-GP

PC4402

SCD01U50V2KX-1GP

PR4432

DY

ACAV_IN H=ACIN L=UNAC

CHARGER_CELL_PIN

DY

PR4454

1 2

0R2J-2-GP

BAT_IN# [24,42,43 ]

PR4429

PR4429 100KR2J-1-GP

100KR2J-1-GP

PR4455

PR4455 0R0402-PAD-2-GP

0R0402-PAD-2-GP

PQ4405

3 4

2

1

2N7002KDW-G P

PD4

405

A K

PAD-2P-330056-GP

AD+

12

VacDET=2.4V

PR4444

Acok setting=2.4*((PR4444+PR4411)/PR4411) Setting=18.178v

12

PR4411

PR4411 47KR2F-GP

47KR2F-GP

BQ24715_AGND

3D3V_AUX_S53D3V_S5

12

PR4414

PR4414 3K3R2J-3-GP

3K3R2J-3-GP

DY

PG4401 GAP-CLOSE-PW R-3-GPPG4401 GAP-CLOSE-PW R-3-GP

PG4408 GAP-CLOSE-PW R-3-GPPG4408 GAP-CLOSE-PW R-3-GP

ACAV_IN

PR4430 0R0402-PAD-2-GPPR4430 0R0402-PAD-2-GP

Follow custormer circuits

PQ4412

3 4

2

5

DY

CHARGER_CELL_PIN

1

6

2N7002KDW-G P

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PWR_CHG_ACOK: PWR_CHG_REGN=6V V+=6*(PR4404/(PR4410+PR4404))=3.27V

BATTERY MON

BOOST_MON[24]

H_PROCHOT# [4,24,42,46]

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PQ4405_5

5

PC4404

SC1U25V3KX-1-GP

12

6

PQ4405_6

PR4405

PR4405 100KR2F-L1-GP

100KR2F-L1-GP

12

PR4450

10KR2F-2-GP

1 2

3D3V_S5

_CHG_1

PWR

12

AD_IA[24]

0R0402-PAD-2-GP

1 2

12

100KR2F-L1-GP

DY

A00 0618

1 2

PR4445

4

SC1U25V3KX-1-GP

PR4413

0R0402-PAD-2-GP

DIS_DTM_CELLPQ4413_2

DY

PC4431

PC4431 SC1U25V3KX-1-GP

SC1U25V3KX-1-GP

PR4464

4

+SDC_IN

12

PC4432

BQ24715_AGND

PR4439

PR4439 4K02R2F-GP

4K02R2F-GP

PWR_CHG_CMSR C

PWR_CHG_ACD ET

CHARGER_CELL_PIN

PWR_CHG_ACO K

BQ24715_IOUT_1

12

PC4417

SC1U25V3KX-1-GP

12

1 2

PR4403 10R5J-GPPR4403 10 R5J-GP

12

PWR_CHG_ACP

PWR_CHG_ACN

DY

1

2

3

4

6

10

PWR_SDA

8

PWR_SCL

9

5

7

SC100P50V2JN-3GP

12

PR4424

PU4401_6BOOST_MON_1

1 2

20KR2F-L-GP

PU4404

BQ24717RGRR-GP

ACN

BATDRV#

ACP

CMSRC

ACDRV

ACDET

CELL

SDA

SCL

ACOK

IOUT

21

PC4423

BQ24715_AGND

Close PR4443

DCBATOUT

PG4404

GAP-CLOSE-PWR-3-GP

1 2

DCBATOUT_R

12

PR4446

PR4446 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

PR4407

6D8R2F-GP

1 2

PU4401_5

PC4415

SCD1U25V2KX-GP

PU4401_4

5

6

PU4401

-

+

-

+

INA199A1-GP

123 4

PC4408

SC1U25V3KX-1-GP

12

GND

PR4

418

3KR5J-GP

_CHG_VCC

PWR

12

PC4433

SCD1U25V2KX-GP

BQ24715_AGND

20

VCC

11

16

REGN

17

BTST

18

HIDRV

19

PHASE

15

LODRV

14

GND

13

SRP

12

SRN

PR4406 0R0402-PAD-2-GPPR4406 0R0402-PAD-2-GP

1 2

BQ24715_AGND

PWR_CHG_BATDR V

PWR_CHG_REG N

PWR_CHG_BTST

PWR_CHG_HID RV

PWR_CHG_PHASE

PWR_CHG_LO DRV

PWR_CHG_SRP

PWR_CHG_SRN

PC4410

12

SC1U25V3KX-1-GP

PR4409

4K02R2F-GP

12

PR4425

1 2

0R3J-0-U-GP

PR4438 0R0402-PAD-2-GPPR4438 0R0402-PAD-2-GP

PR4417 0R0402-PAD-2-GPPR4417 0R0402-PAD-2-GP

BQ24715_AGND

PG4405

GAP-CLOSE-PWR-3-GP

1 2

CHECK PM BATTERY TYPE CHECK CELL for DT mode

+VCHGR_R +VCHGR

12

PR4448

PR4448 10R2F-L-GP

10R2F-L-GP

DCBATOUT

DIS_DTM_HW: PWR_CHG_REGN=6V V+=6*(PR4440/(PR4441+PR4440))=3.27V Setting=3.27*((PR4442+PR4447)/PR4447)=9V

AD+

1 2

3

PU4

405

S

D

S

D

1

8

S

D

S

D

2

7

SGDD

3

6

45

SI7121DN-T1-GE3-G P

84.06675.030

2nd = 84.07121.037

12

DC_IN_D

407

PQ4

3 4

V_IN

ACA

2

5

1

6

2N7002KDW-G P

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PU4406 and PU4407: main source: 84.03660.037

FDMS3600-02-RJ K0215-COLAY-GP

1 2

PC4421

1 2

12

PR4422

PR4422 1M8R2J-L-GP

1M8R2J-L-GP

12

PR4441

PU4402_1IN+

12

3

100KR2F-L1-GP

DCBATOUT

12

DY

1 2

PR4465

PR4402

PR4402 316KR2F-GP

316KR2F-GP

BQ24715_IOUT_1

316KR2F-GP

FDMS3600-02-RJ K0215-COLAY-GP

3D3V_AUX_S5

LM393PWR-GP

PU4402

BT+

12

DY

12

DY

BATDRV

PWR_CHG_REG N

PC4422

SC1U25V3KX-1-GP

PD4401

PD4401 1PS76SB40-GP-U

1PS76SB40-GP-U

83.1PS76.01F

K A

PWR_CHG_BTST1

SCD047U25V3KX-3-G P

PWR_CHG_CMPIN: V-=3.3*(PR4402/(PR4428+PR4402))=1.1099V

PWR_CHG_REG N

5V_S5

100KR2F-L1-GP

12

PR4461

DY

PR4440

120KR2J-GP

DY

AD+

_G_2

PU4406

1

9

DY

8

ZZ.00215.037

150KR2F-L-GP

PR4428

12

PWR_CHG_CMPIN

5V_S5

7

5

8

6

2IN-

VCC

2IN+

2OUT

1OUT11IN-21IN+3GND

4

DIS_DTM_CELL

PR4442

412KR2F-GP

PU4402_1IN-

PR4447

PR4447 180KR2F-GP

180KR2F-GP

12

PR4435

100KR2J-1-GP

PR4423

AD+_G_1

1 2

10KR2F-2-GP

BQ24715_AGND

2 3 4 10

7 6 5

PWR_CHG_SRP_ R

PWR_CHG_SRN _R

PWR_CHG_CM POUT

12

PWR_CHG_REG N

12

PR4453

DY

+SD

C_IN

426

PR4

1 2

D01R3721F-GP-U

12

PG4

406

GAP-CLOSE-PWR-3- GP

PR4

421 0R2J-2-GP

D

Y

PWR_CHG_ACP

SCD1U25V2KX-GP

1 2

PC4418

PU4407

FDMS3600-02-RJ K0215-COLAY-GP

PC4426

SC100P50V2JN-3GP

100KR2F-L1-GP

DY

1

9

8

ZZ.00215.037

DY

12

PC4419

SCD01U25V2KX-3GP

5V_S5

100KR2F-L1-GP

12

PR4460

2 3 4 10

7 6 5

PR4427

2D2R5F-2-GP

12

DY

DCBATOUT_SNUB

12

PC4406

SC330P50V3KX-GP

(AD_IA_HW)

2

CHARGER_SRC

12

PG4

402

GAP-CLOSE-PWR-3- GP

12

428

PC4

12

SCD1U25V2KX-GP

D

Y

1 2

PC4416

PWR_CHG_ACN

BQ24715_AGND

PC4425

PC4411

SC10U25V5KX-GP

12

DCBATOUT

PC4403

SC10U25V5KX-GP

12

PL4401

PL4401 COIL-2D2UH-11 -GP

COIL-2D2UH-11 -GP

1 2

68.2R210.20C

SCD1U25V2KX-GP

PC4401

1 2

PR4443

D01R2512F-3-G P

GAP-CLOSE-PWR-3-GP

PG4407

1 2

PC4429

1 2

12

SCD1U25V2KX-GP

1 2

12

BQ24715_AGND BQ24715_AGND

5V_S5

12

PR4437

PR4437 100KR2J-1-GP

100KR2J-1-GP

PR4436

PWR_CHG_CM POUT PQ 4413_5

CHECK PM ADAPTER TYPE And setting adapter type

PR4436

1 2

220KR2F-GP

SCD01U50V3JX-1G P

357KR2F-GP

PR4401

1 2

PC4405

AC_IN#[24]

PQ4411_D1PW R_CHG_CMPIN

ADAPTER TYPE

90W

65W

45W

2

CHARGER_SRC

PC4407

PC4427

SC10U25V5KX-GP

12

PC4430

SC10U25V5KX-GP

12

PC4420

GAP-CLOSE-PWR-3-GP

DY

PG4403

SC1U25V3KX-1-GP

1 2

BATDRV

PC4412

PC4412 SCD1U25V2KX-GP

SCD1U25V2KX-GP

12

3D3V_AUX_S5

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PQ4411

3 4

2

5

1

6

2N7002KDW-G P

AD_IA_HW AD_IA_HW_2

L

H L

L

SC10U25V5KX-GP

PC4413

SCD1U25V2KX-GP

12

+VCHGR

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

PQ4413

PQ4413 2N7002KDW-G P

2N7002KDW-G P

6

12

PR4412

PR4412 100KR2F-L1-GP

100KR2F-L1-GP

84.2N702.A3F

L

H

PC4434

SC10U25V5KX-GP

12

PD4402

3

V10P10-GP-U

PU4403

S

1

S

2

S

3

G D

4 5

FDMC6675BZ-GP-U

84.06675.030

2nd = 84.07121.037

2345

1

AD_IA_HW [24]AD_IA_HW2[24]

1 2

147KR2F-GP

147KR2F-GP PR4420

PR4420

1.099V

0.862329V

0.659648V

1

2

D

8

D

7

D

6

DY

PR4457

1 2

H_PROCHOT# [4,24,42,46]

0R0402-PAD-2-GP

PQ4413_3

PWR_CHG_REG N

12

PWR_CHG_CM PINPQ4411 _D2

(AD_IA_HW_2)

SETTING

1

BT+

12

PC4424

SCD01U25V2KX-3GP

PR4410

PR4410 100KR2J-1-GP

100KR2J-1-GP

PWR_CHG_ACO K

PR4404

PR4404 120KR2J-GP

120KR2J-GP

Wistron Co rporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CHARGE(BQ24715)

44 101Friday, June 28, 2013

1

44 101Friday, June 28, 2013

X02

A

S

SID = PWR.Plane.Regulator_5v3p3v

3D3

503

PR4

0R2J-2-GP

PC4508

0R2J-2-GP

SCD1U25V2KX-GP

12

0R2J-2-GP

506

PR4

12

D

Y

PWR_DCBATOUT_3D3V

PC4509

SC10U25V5KX-GP

12

4 4

ATOUT

DCB

3 3

_DCBATOUT_3D3V

PWR

PG4504

1 2

GAP-CLOSE-PWR-3-GP

PG4501

1 2

GAP-CLOSE-PWR-3-GP

PG4507

1 2

GAP-CLOSE-PWR-3-GP

PG4511

1 2

GAP-CLOSE-PWR-3-GP

3V_5V_EN[36]

PC4507

SC10U25V5KX-GP

12

D

Design Current= 3.34A

5.28A<OCP<5.72A A

3D3V_PWR3D3V_S5

PG4514

12

GAP-CLOSE-PWR-3-GP

PG4516

GAP-CLOSE-PWR-3-GP

PG4518

GAP-CLOSE-PWR-3-GP

PG4519

GAP-CLOSE-PWR-3-GP

PG4524

GAP-CLOSE-PWR-3-GP

PG4531

GAP-CLOSE-PWR-3-GP

2 2

3D3V_PWR

12

PC4517

SCD1U10V2KX-5GP

12

DY

2nd = 68.3R31B.10U

12

PT4502

SE220U6D3VM-28-GP-U

PR4513

6K65R2F-GP

PR4517

10KR2F-2-GP

68.3R310.20A

PL4503

1 2

IND-3D3UH-57GP

PG4520

2D2R5F-2-GP

12

GAP-CLOSE-PWR-3-GP

SC330P50V3KX-GP

3V_FEEDBACK

12

PR4514

PR4514 0R2J-2-GP

0R2J-2-GP

DY

12

PC4521

PC4521 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

DY

12

PR4509

PC4519

Close to VFB Pi n (pin5)

SSS

123

S G

12

D

8

DY

D

SSS

123

S

PWR_3D3V_SNUB

12

DY

3V_5V_POK[17]

V_AUX_S5

12

D

Y

PWR

PR4504

PR4504 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

678

DDD

PU4502

PU4502 SIS412DN-T1-GE3-GP

SIS412DN-T1-GE3-GP

G D

4 5

PU4504

567

DDD

SIS780DN-T1-GE3-GP

G

0R0402-PAD-2-GP

B

_5V_EN1_R

84.00412.037

PC4515

SCD1U25V3KX-GP

4

PR4520

502

PR4

1 2

0R0402-PAD-2-GP

PR4505

1 2

0R0402-PAD-2-GP

PWR_3D3V_VBST2_1

12

3D3V_S5

12

PR4519

DY

100KR2J-1-GP

12

PWR

PWR_3D3V_EN2

PR4507

1 2

1D5R3F-GP

PWR_3D3V_DRVH2

PWR_3D3V_DRVL2

PR4511

PR4511 57K6R2F-GP

57K6R2F-GP

PWR_5V3D3V_PGOOD

3D3V_AUX_S5

GAP-CLOSE-PWR-3-GP

_5V_EN1

PWR_3D3V_VBST2

PWR_3D3V_LL2

PWR_3D3V_FB2

PWR_3D3V_EN2

PWR_3D3V_CS2

PG4529

1 2

SC4D7U6D3V3KX-GP

PU4501

TPS51225RUKR-GP

9

VBST2

10

DRVH2

8

SW2

11

DRVL2

4

VFB2

6

EN2

5

CS2

7

PGOOD

3D3V_PWR_2

PC4523

DCBATOUT

VREG3

3

12

PC4510

SC10U25V5KX-GP

12

DY

12

VIN

VBST1

DRVH1

SW1

DRVL1

VO1

VFB1

EN1

CS1

VCLK

GND

VREG5

13

12

PC4524

PC4524 SC1U6D3V3KX-2GP

SC1U6D3V3KX-2GP

PC4511

12

17

16

18

15

14

2

20

1

19

21

5V_PWR_2

C

SCD01U50V2KX-1GP

PWR_5V_VBST1

PWR_5V_DRVH1

PWR_5V_LL1

PWR_5V_DRVL1

PWR_5V_VO1

PWR_5V_FB1

PWR_5V_EN1

PWR_5V_CS1

PWR_5V_VCLK

PR4508

1 2

1D5R3F-GP

DCB

ATOUT

GAP-CLOSE-PWR-3-GP

PWR_5V_VBST1_1

12

PR4512

PR4512 143KR2F-GP

143KR2F-GP

PWR

_DCBATOUT_5V

PG4

502

12

503

PG4

12

505

PG4

12

PG4506

12

PG4508

12

PG4510

12

84.00412.037

SIS412DN-T1-GE3-GP

PC4516

12

SCD1U25V3KX-GP

PU4503

D

_5V_VCLK

PWR

PC4

525

SC1KP50V2KX-1GP

75.00054.B7D

2nd = 75.00054.C7D

3rd = 75.00054.M7D

PC4527

SCD1U25V3KX-GP

PWR_DCBATOUT_5V

PC4512

PC4513

SC10U25V5KX-GP

12

678

DDD

D

SSS

GD

SSS

GD

123

4 5

G

S

D

567

8

DDD

D

DDD

D

G

4

SSS

123

SG

PU4505

SIS780DN-T1-GE3-GP

SC18P50V2JN-1-GP

12

IND-2D2UH-46-GP-U

12

PR4510

PR4510 2D2R5F-2-GP

2D2R5F-2-GP

DY

PWR_5V_SNUB

12

PC4520

DY

SC560P50V-GP

0R2J-2-GP

PC4

526

526 SCD1U25V3KX-GP

SCD1U25V3KX-GP

12

D

Y

BAT54S-7-F-GP

5V_PWR 15V_S5

12

DY

SCD1U25V3KX-GP

PC4514

SC10U25V5KX-GP

12

PL4502

1 2

PR4515

PC4522

12

Y

D

BST15V_1

PD4

503

3

D

Y

1

2

BOOST_10V

12

DY

SC1U25V3KX-1-GP

PC4534

SCD1U25V2KX-GP

12

DY

PWR_5V_FB1_RPWR_3D3V_FB2_R

12

DY

SC1U25V3KX-1-GP

Design Current= 8.48A

13.33A<OCP<15.7 6A

PG4521

GAP-CLOSE-PWR-3-GP

12

PR4516

PR4516 15KR2F-GP

15KR2F-GP

12

PR4518

PR4518 9K76R2F-1-GP

9K76R2F-1-GP

12

Y

D

PC4

PC4 SCD1U25V3KX-GP

SCD1U25V3KX-GP

BST15V_2

3

D

Y

1

2

15V_PWR

12

PC4533

DY

5V_PWR

PC4518

SCD1U10V2KX-5GP

12

DY

X01 change PR4120 to 9.76K to solve 5V voltage fall issue while on heavy loading

E

532

PD4

502

BAT54S-7-F-GP

75.00054.B7D

2nd = 75.00054.C7D

3rd = 75.00054.M7D

PG4530

GAP-CLOSE-PWR-3-GP

PD4501

BZT52C15S-GP

DY

A K

5V_PWR

GAP-CLOSE-PWR-3-GP

A00 0618A00 0618

PT4501

GAP-CLOSE-PWR-3-GP

SE220U6D3VM-28-GP-U

GAP-CLOSE-PWR-3-GP

12

PG4512

PG4513

PG4515

PG4517

PG4522

PG4523

PG4525

PG4526

PG4527

PG4528

5V_S5

12

Close to VFB Pi n (pin2)

1 1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

A

B

C D

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

3V/5V TPS51225

E

X02

45 101Friday, June 28, 2013

X02

5

D = CPU.Regulator

SSI

4

PWR

_VCC_VR EF

3

2

1

12

PR4

603

12

PR4

602

16

VBAT

DROOP

25

SCD33U6D3V2KX-1-GP

602

NTC-100K -10-GP

PC4

602

1 2

SC4700P 50V2KX-1GP

1 2

PR4610

422KR3F -GP

PWR_VCC_THERM

PWR_VCC_IMON

PWR_VCC_OCP-1

15

14

SLEWA

COMP

27

26

PC4606

1 2

11

13

12

IMON

OCP-I

THERM

VREF

GND

V5A

30

29

28

PWR_VCC_V5A

PR4624 1 0R3J-3-GPPR 4624 10R3J-3-GP

SC10U6D3V2MX-GP-U

PC4607

12

1 2

PR4609

PR4609 56KR2F-G P

56KR2F-G P

PWR_ VCC_B-RAMP

PWR_ VCC_F-Imax

PWR_ VCC_O-USR

10

9

O-USR

F-IMAX

B-RAMP

VR_ON

SKIP#

PWM1

PWM2

MODE

PGOOD

VDD

VDIO

ALERT#

GND

VR_HOT#

VCLK

32

31

33

1 2

IMVP_VRON

8

7

6

5

4

PWR_ PG

3

PWR_ VCC_VDD

2

1

NC#4

D D

PR4606 15 KR2F-GPPR4606 15 KR2F-GP

1 2

PC4603

1 2

SC1KP50 V2KX-1GP

PR4611 7 5R2F-2-GP

1 2

DY

PR4612

PWR_ VCC_SLEW A

1 2

39KR2F-G P

PR4613

DCBATOU T

C C

PWR_ VCC_CSP1[47]

PWR_ VCC_CSN1[47]

3D3V_S5

PR4616

VSS_SEN SE[9]

VCC_SEN SE[7]

B B

1 2

0R0402-P AD-2-GP

0R0402-P AD-2-GP PR4617

PR4617

1 2

0R0402-P AD-2-GP

PR4627

1 2

5K76R2F -2-GP

PC4604

PC4604 SC470P5 0V2JN-GP

SC470P5 0V2JN-GP

PC4608

SC1500P 50V2KX-2GP

PR4613

10R3J-3-G P

PWR_ VCC_GFB

PWR_ VCC_VFB

PWR_ VCC_DROOP

12

DY

1 2

PR4619

PR4619 10KR2F-2 -GP

10KR2F-2 -GP

1 2

PWR_ VCC_VBAT

1 2

TPS5162 2RSMR-1-GP

PR4620

1 2

3KR2F-GP

PU4601

17

CSP1

18

CSN1

19

CSN2

20

CSP2

21

NC#21

22

NC#22

23

GFB

24

VFB

PWR_ VCC_COMP

PWR_ VCC_VREF

603

75R2F-2-G P

D

Y

12

PR4601

PR4601 150KR2F -L-GP

150KR2F -L-GP

PR4615

PR4615 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PR4626

1 2

0R2J-2-GP

0R2J-2-GP PR4625

PR4625

1 2

0R0402-P AD-2-GP

PR4618 1 0R3J-3-GPPR 4618 10R3J-3-GP

SC1U6D3V2KX-GP

PC4601

12

5V_S5

1 2

DY

1 2

12

PR4

604

1MR2F-GP

12

PR4607

PR4607 150KR2F -L-GP

150KR2F -L-GP

H_CPU_S VIDDAT [7]

VR_SVID_A LERT# [7 ]

H_CPU_S VIDCLK [7 ]

H_PROCH OT# [4,24,42 ,44]

12

PR4

605

8K87R2F -2-GP

12

PR4608

PR4608 150KR2F -L-GP

150KR2F -L-GP

H_VR_EN ABLE [7]

PWR_ VCC_SKIP# [47]

PWR_ VCC_PWM1 [47]

IMVP_PW RGD [7,24]

3D3V_S5

Fsw

OCP

IMON

Load line

IMVP_PW RGD

H_CPU_S VIDDAT

H_CPU_S VIDCLK

VR_SVID_A LERT#

28W 15W

392K

PR4604

75K

PR4607

150k

PR4609

680K

PR4610

2.8K

PR4620

PR4614 2K R2F-3-GPPR 4614 2KR2F-3-GP

EC4602

SCD1U25V2KX-GP

12

DY

1M

150K

75K

422K

3K

3D3V_S0

12

0117 Add EC4602

1D05S_V CCST

PC4605SCD1U10 V2KX-5GP

12

DY

1 2

PR4621130R2F-1-GP PR4621130R2F-1-GP

PR462254D9R2F-L1-GP PR462254D9R2F -L1-GP

PR4623130R2F-1-GP

DY

PWR_VCC_COMP_1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51622_CPUCORE(1/2)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

46 10 1Friday, June 28, 201 3

1

X02

5

D = CPU.Regulator

SSI

PWR

PG4

1 2

PG4

1 2

PG4704

1 2

PG4701

1 2

PG4705

1 2

PG4706

1 2

PC4729

SC22U6D3V3MX-1-GP

PC4719

SC22U6D3V3MX-1-GP

PC4714

DY

PWR

_DCBATO UT_VCCCORE1

702

703

12

PC4730

SC22U6D3V3MX-1-GP

12

PC4720

SC22U6D3V3MX-1-GP

12

PC4727

DY

PC4733

PC4726

PC4739

DY

12

PC4734

SC22U6D3V5MX-2GP

12

PC4709

SC22U6D3V3MX-1-GP

12

PC4740

DY

12

PC4732

PC4731

SC22U6D3V3MX-1-GP

PC4721

SC22U6D3V3MX-1-GP

PC4728

DY

SC22U6D3V3MX-1-GP

12

PC4722

SC22U6D3V5MX-2GP

SC22U6D3V3MX-1-GP

12

PC4715

DY

DCB

ATOUT

GAP-CLOS E-PWR-3-GP

D D

C C

B B

GAP-CLOS E-PWR-3-GP

VCC_COR E

4

_DCBATO UT_VCCCORE1

12

PC4725

PC4710

PC4716

DY

12

PWR_ VCC_SKIP#[46]

PWR_ VCC_PWM1[46]

12

PC4

702

SC10U25V5KX-GP

12

PC4737

PC4736

SC22U6D3V5MX-2GP

12

PC4711

SC22U6D3V5MX-2GP

SC22U6D3V3MX-1-GP

12

PC4741

PC4742

DY

12

PC4

703

SC10U25V5KX-GP

PR4702

PR4702 0R0402-P AD-2-GP

0R0402-P AD-2-GP

12

PC4738

SC22U6D3V5MX-2GP

12

PC4724

DY

SC22U6D3V5MX-2GP

12

PC4743

DY

3

For

12

EC4

704

SCD1U50V3KX-GP

DY

12

PC4708

PC4708 SC1000P 100V3KX-GP

SC1000P 100V3KX-GP

1 2

12

PC4735

DY

12

PT4

701

SE68U25VM-7-GP-U

DY

PWR_ DCBATOUT_VCC CORE1

PWR_ VCC_SKIP#1

acoustic noice

702

PU4701

PU4701 CSD9737 4Q4M-GP-U1

CSD9737 4Q4M-GP-U1

5

VIN

1

SKIP#

8

PWM

3

PGND

VDD

BOOT_R

BOOT

VSW

PGND

9

5V_S5

2

PWR_ VCC_BOOTR1

6

PWR_ VCC_BOOT1

7

4

PC4705 SC2D2 U10V3KX-1GPPC4705 S C2D2U10V3KX-1 GP

1 2

PR4703 2D2 R3F-L-GPPR 4703 2D2R3F-L-GP

PWR_ VCC_VSW1

12

PR4701

PR4701 2D2R5F-2 -GP

2D2R5F-2 -GP

VCC_VSW 1_R

12

PC4701

PC4701 SC820P5 0V2KX-1GP

SC820P5 0V2KX-1GP

A00 0621

0318 Add EC4702, need close to PC4741

SCD1U10V2KX-4GP

12

EC4702

1 2

PC4706

VCC_BOO TR1_R

PC4706

1

2

SCD22U2 5V3KX-GP

PL4701 IND-D2 2UH-9-GP-UPL4701 IND-D2 2UH-9-GP-U

1 2

GAP-CLOSE-PWR-3-GP

PG4707

1 2

VCC_VSW1_GP

12

PR4704

PR4704 2K21R2F -GP

2K21R2F -GP

1 2

PR4706

2K94R2F -GP

1 2

VCC_CSN 1_R

2

PR4705

29K4R2F -GP

PR4707

1 2

NTC-10K-2 6-GP

PC4707

1 2

SCD15U1 0V3KX-4-GP

1

VCC_COR E

A00 0621

GAP-CLOSE-PWR-3-GP

PG4708

1 2

12

PT4701

DY

SE330U2 D5VM-14-GP

79.3371V.6CL

28W 15W

PR4704

2.21K

2.94K

60.4K

2.21K

2.94K

29.4K

DCR sensing

PWR_ VCC_CSN1 [4 6]

PWR_ VCC_CSP1 [46]

PR4706

PR4705

SC22U6D3V5MX-2GP

28W CPU need stuff PC4743, PC4728, PC4739, PC4724, PC4735, PC4738

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51622_CPUCORE(2/2)

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

47 10 1Friday, June 28, 201 3

1

X02

5

D

= PWR.Plane.Regulator_1p05v

SSI

PR4

01 0R040 2-PAD-2-GP

8

D D

Ref

r Intel CRB to use SLP_S3# control

e

SCD22U6D3V2KX-1GP

PC48

12

26

C C

TRIP

GND

5V

B B

PWR_ 1D05_VRF_L

12

PR4826

PR4826 95K3R2F -GP

95K3R2F -GP

PWR_ 1D05_REFIN_1

12

PR4833

PR4833 105KR2F -1-GP

105KR2F -1-GP

OCL(A)

8A

12A

PM_

S

LP_S3#[17,24,36,49,5 1]

8

PR4823

PR4823 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PR4832

PR4832 0R0402-P AD-2-GP

0R0402-P AD-2-GP

PR4828

1 2

0R0402-P AD-2-GP

Reserve PR4821 for OCP setting

1 2

DY

1 2

5V_S5

12

SCD1U10 V2KX-4GP

PR4821

PR4821 0R2J-2-GP

0R2J-2-GP

PC4821 S C10P50V2JN-4GP

PC4833

Pin19 direct connect to thermal pad

4

PWR

1D05_EN

_

12

PC4818

DY

PWR_ 1D05_VREF

PWR_ 1D05_REFIN

DY

SC10P50 V2JN-4GP

5V_S5

PWR_ 1D05V_GSNS

PWR_ 1D05V_VSNS

PWR_ 1D05_SLEW

PWR_ 1D05_TRIP

PC4819

12

1 2

PC4834 SC 2700P50V2KX-1-G PPC483 4 SC2700P50V2KX -1-GP

3

M

ode

GND

Float

PU4801

28

EN

27

NU#27

26

VREF

25

REFIN

24

REFIN2

23

GSNS

22

VSNS

21

SLEW

20

TRIP

19

GND

18

V5

17

VIN

TPS5136 3RVER-GP

16

SC2D2U10V3KX-1GP

VIN

15

VIN

PGOOD

NU#2

MODE

NC#4

BST

SW#6

SW#7

SW#8

SW#9

PGND

GND

29

PWR_ 1D05_PGOOD

1

PWR_ 1D05_LP#

2

PWR_ 1D05_MODE

3

4

PWR_ 1D05_BOOT

5

6

7

8

9

10

11

12

13

14

PR4834 0 R0402-PAD-2-GPPR4834 0 R0402-PAD-2-GP

PR4835 1 0KR2F-2-GP

1 2

DY

PR4819 1 0KR2F-2-GP

1 2

DY

PR4824 0R 2J-2-GP

PR4830

PR4830 5D1R3F-G P

5D1R3F-G P

1 2

PWR_ 1D05_SW

PR4825

2D2R5F-2 -GP

PC4820

SC330P5 0V3KX-GP

1 2

12

DY

PWR_ 1D05_RC

12

SCD1U25 V3KX-GP

SCD1U25 V3KX-GP PC4823

PC4823

12

DY

PWR_1D05_SUNB

12

DY

PCH_SLP _S0# [17]

PL4801

1 2

COIL-1UH-61 -GP

PWR_ 1D05V_VSNS

PWR_1D05V _GSNS

2

Fsw(KHz)

400KHz

800KHz

1D05V_V TT_PWRGD [7,3 6]

Panasonic ETQP3W1R0WFN 7 x 7 x 3 . Isat : 13 A , DCR 6.9+-15%mOhm

GAP-CLOSE-PWR-3-GP

12

PG4820

PG4821

12

GAP-CLOSE-PWR-3-GP

12

PC4829

SC22U6D3V5MX-2GP

1D05V_PWR 1D05V_S0

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

1 2

GAP-CLOS E-PWR-3-GP

12

PC4822

PC4831

SC22U6D3V5MX-2GP

1

PG4

02

8

PG4

03

8

PG4

04

8

PG4805

PG4806

PG4807

PG4808

Design Current = 6.1A

9.57A<OCP<11.31A

12

DY

12

PC4830

SC22U6D3V5MX-2GP

DY

PC4825

SC22U6D3V5MX-2GP

DY

PC4832

1D05V_P WR

12

SC22U6D3V5MX-2GP

PC4828

SCD1U10V2KX-5GP

+PWR _SRC_1D05VDCBATOU T

PG4813

1 2

GAP-CLOS E-PWR-3-GP

PG4812

1 2

GAP-CLOS E-PWR-3-GP

PG4814

1 2

GAP-CLOS E-PWR-3-GP

PG4815

1 2

GAP-CLOS E-PWR-3-GP

A A

5

+PWR _SRC_1D05V

PC4817

12

PC4835

PC4827

SC10U25V5KX-GP

12

I/P cap: CHIP CAP C 10U 25V K0805 X5R/ 78.10622.51L Inductor:CHIP CHOKE 1.0UH ETQP3W1R0WFN / Panasonic/ 6.9mOhm / Isat =13Arms/ 68.1R01D.20H O/P cap:CHIP CAP C 22U 6.3V M0805 X5R /78.22610.51L

4

PC4835

PC4824

SC10U25V5KX-GP

12

DY

SCD1U25V2KX-GP

12

REFIN Voltage (V)

GND

FLOAT

Resistor Divider

Output Voltage (V)

1.05V

1.2V

Adjustable between 0.6V to 2.0V

3

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

2

Date: Sheet of

TPS51363 1D05V

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

48 10 1

1

X02

5

4

3

2

1

C

BATOUT

S

ID = PWR.Plane.Regulator_1p35v0p675v

S

P

4907

R

P

_SLP_S4 #[17,24]

M

D D

DDR_VTT _PG_CTRL[12]

PM_SLP_ S3#[17 ,24,36,48,51]

1D35V_V TT_PWRGD[36]

C C

12

4903

4903 PC

PC

SCD1U10V2KX-4GP

B B

0117 Add EC4901

12

PR4903

PR4903 10KR2F-2 -GP

10KR2F-2 -GP

12

4902

4902 PC

PC

12

SCD01U16V2KX-3GP

4906

4906 PR

PR

29K4R2F-GP

1 2

0R0402-P AD-2-GP

PR4909

1 2

0R0402-P AD-2-GP

PR4910 0 R2J-2-GP

1 2

EC4901

SCD1U25V2KX-GP

12

DY

0D675V_ EN

PWR_ 1D35V_EN

PWR_ 1D35V_VREF

PWR_ 1D35V_REFIN

PWR_ 1D35V_MODE

PWR_ 1D35V_TRIP

12

PWR_ 1D35V_VTTREF

200KR2F-L-GP

PR4908

1 2

12

PC4918

PC4918 SCD22U1 0V2KX-1GP

SCD22U1 0V2KX-1GP

68K1R2F-1-GP

PR4902

DY

P

R_1D35V _EN

W

12

P

4906

C

SCD1U10 V2KX-5GP

DY

0D675V_ EN

PU4901

20

PGOOD

17

VTTEN

16

EN/PSV

6

VREF

8

REFIN

19

MODE

18

TRIP

5

VTTREF

21

GND

7

GND

TPS5121 6RUKR-GP

74.51216.073

+0D675V _DDR_P 0D 675V_S0

VDDQS

VTTGND

PG4901

1 2

GAP-CLOS E-PWR-3-GP

PG4902

1 2

GAP-CLOS E-PWR-3-GP

V5IN

VBST

DRVH

DRVL

PGND

VTTIN

VTT

VTTS

SW

12

PWR_ 1D35V_VBST

15

PWR_ 1D35V_DRVH

14

PWR_ 1D35V_SW

13

PWR_ 1D35V_DRVL

11

10

PWR_ 1D35V_VDDQS

9

2

3

1

4

PWR_ 1D35V_VTTREF

5V_S5

PC4915

12

PC4901

SC1U10V2KX-1GP

PR4905

1 2

2D2R3-1-U -GP

PC4916

SCD1U10V2KX-5GP

PC4919

PC4919 SCD1U25 V3KX-GP

SCD1U25 V3KX-GP

PR4605_2

1 2

+0D675V _DDR_P

12

DY

PC4917

SC10U6D3V5KX-1GP

A00 0618

PR4911

1 2

0R0603-P AD-2-GP-U

SC10U6D3V5KX-1GP

0D675V_ VTTREF

12

PC4909

PC4911

SIR172ADP-T1-GE3-GP

567

8

DDD

D

DDD

D

PU4902

G

4

SSS

123

567

8

DDD

D

DDD

D

PU4903

G

4

SSS

123

1D35V_P WR

SC1U6D3V2KX-GP

PC4904

12

SC10U25V5KX-GP

PL4902

1 2

IND-D68UH-5 1-GP-U

SIRA12DP-T1-GE3-GP

IND-D68UH-5 1-GP-U

12

PR4912

DY

2D2R5F-2 -GP

TPS5121 6_PHS_SET

12

DY

PC4922

PC4922 SC330P5 0V2KX-3GP

SC330P5 0V2KX-3GP

www.qdzbwx.com

+PWR _SRC_1D35V

12

PC4912

SC10U25V5KX-GP

12

PC4913

SCD1U25V2KX-GP

1 2

PWR_1D35V_VDDQS

D

PC4914

SC4D7U25V5KX-GP

12

PC4920

PG4907

GAP-CLOSE-PWR-3-GP

PC4920

P

WR_ SRC_1D35V

+

G

4903

P

1 2

GAP-CLOS E-PWR-3-GP

P

4904

G

1 2

GAP-CLOS E-PWR-3-GP

P

4905

G

1 2

GAP-CLOS E-PWR-3-GP

P

4906

G

1 2

GAP-CLOS E-PWR-3-GP

PG4921

1 2

GAP-CLOS E-PWR-3-GP

PG4920

1 2

GAP-CLOS E-PWR-3-GP

Design Current=13.52A

21.25A<OCP>25.11A

1D35V_P WR

A00 0621

PT4903

12

PC4921

SCD1U10V2KX-5GP

SC4D7U6D3V5KX-3GP

79.3371V.6CL

1

35V_PW R

D

GAP-CLOS E-PWR-3-GP

SE330U2D5VM-14-GP

DY

12

EC4601

SCD1U50V3KX-GP

GAP-CLOS E-PWR-3-GP

P

4908

G

1 2

P

4909

G

1 2

PG4910

1 2

PG4911

1 2

PG4912

1 2

PG4913

1 2

PG4914

1 2

PG4915

1 2

PG4916

1 2

PG4917

1 2

PG4919

1 2

PG4918

1 2

PG4922

1 2

PG4923

1 2

1

D

35V_S3

State S3 S5 VDDR VTTREF VTT

S0

S3

S4/S5

MODE

A A

PR4608

200k ohm

100k ohm

68k ohm

47k ohm

Hi

Lo

HiLoOn

Hi

On

Lo

Frequency

400kHz

300kHz

400kHz

5

On

OffOff

On

Off(Hi-Z)

Off

Discharge Mode

Tracking Discharge

Non-tracking Discharge

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: CHIP CHOKE 1.0UH PCMB104T-1R0M/ 3.3mohm/ Isat =28A rms /68.1R01C.10Q O/P cap: CHIP CAP POL 330U 2.5V M 6.3*4.5 2.3Arms Matsuti/77.53371.18L H/S: SIR172ADP-T1-GE3 / 8.5mohm/[email protected]/ 84.00172.A37 L/S: SIRA12DP-T1-GE3 / 4.4mohm/[email protected]/ 84.SRA12.037

4

3

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

2

Date: Sheet of

TPS51216_+1.35V_SUS

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

49 10 1

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

(Reserved)TPS51312 1D8V

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

50 10 1

1

X02

5

SSI

D = PWR.Plane.Regulator_1p5v

D D

3D3

V_S5

4

TLV

70215DBVR for 1D5V_S0

SC1U6D3V2KX-GP

PC5103

12

3

2

1

Design Current = 15mA

PU5101

1

IN

OUT

2

PWR_ 1D5V_EN

C C

PR5108

PM_SLP_ S3#[1 7,24,36,48,49]

12

0R0402-P AD-2-GP

GND EN3NC#4

TLV7021 5DBVR-GP

PWR_ 1D5V_EN

12

PC5101

PC5101 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

1D5V_PW R 1D5 V_S0

5

4

12

SC1U6D3V2KX-GP

PC5104

1 2

GAP-CLOS E-PWR

PG5101

0108 Reserve PC5101

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

RT9198-15PU5R_1D5V

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

51 10 1

1

X02

5

S

SID = VIDEO

LCD

12

C52

03

01

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

DY

LVDS_DATA2#_R [53]

LVDS_DATA2_R [53]

LVDS_CLK#_R [53]

LVDS_CLK_R [53]

VDD

12

EC5

201

SCD1U25V2KX-GP

DBC_EN [20]

COLOR_ENGINE [20]

LCD_TST_C LCD_BRIGHTNESS BLON_OUT_C

LCD

1

3

1

2 3 4 5 6

32

STAR-CON30-4-GP

7 8 9 1

0

1

2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

D D

C C

BKLT_CTRL

_HP/LVDS_3D3V_ROM

EDP LCD

_TST_C

EDP

_AUX/LVDS_DDC_CLK _AUX#/LVDS_DDC_DAT

EDP

_TX0/LVDS_DATA0# _TX0/LVDS_DATA0

EDP

EDP_TX1/LVDS_DATA1# EDP_TX1/LVDS_DATA1

LVDS_DATA2#_R LVDS_DATA2_R

LVDS_CLK#_R LVDS_CLK_R

DBC_EN_R LCD_BRIGHTNESS BLON_OUT_C COLOR_ENGINE_CONN

A00 0618

0R0402-PAD-2-GP

R5222

1 2

D5202

21

CH751H-40PT-GP

83.R0304.A8F

DCBATOUT_LCD

12

A00 0618

0R0402-PAD-2-GP

R5224

1 2

DY

R5228

R5228 0R2J-2-GP

0R2J-2-GP

LVDS / EDP Colay Page 53 PL Page 53.

eDP_BKLT_CTRL [53]

EC_BRIGHTNESS [24]

EC (BIST MODE)

4

eDP eDPLVDS LVDS

1

LCDVDD

2

LCDVDD

3

LCDVDD

4

LCDVDD

EDP

5

6

LCD_TST_C

7

EDP_AUX LVDS_DDC_CLK

8

EDP_AUX# LVDS_DDC_DAT

9

GND GND

0

1

EDP_TX0N LVDS_DATA0#

1

EDP_TX0P LVDS_DATA0

2

1

GND GND

13

EDP_TX1N LVDS_DATA1#

14

EDP_TX1P LVDS_DATA1

15

GND GND

1 2 3 4 5

SRN100J-4-GP

LCDVDD LCDVDD

LCDVDD

_HP 3D3V_ROM

LCD_TST_C

RN5201

8

BKLT_CTRL

7 6

16 17

18

1920NC

2 22

23

2

26 27

28

29

30

LCD_TST [24]

BLON_OUT [24]

NC NC LVDS_DATA2

GND

1

GND

4

DBC_EN DBC_EN

5

BRIGHTNESS BRIGHTNESS

BLON_OUT BLON_OUT

Color_Engine Color_Engine

NC

DCBATOUT_LCD

BKLT_CTRL BLON_OUT_C EDP_HPD

3

LVDS_DATA2#

GND

LVDS_CLK#_R

LVDS_CLK_RNC

GND GND

GND

NC

DCBATOUT_LCD

RN5204

1 2 3 4 5

SRN100KJ-5-GP

2

1

X02 change CAM1 connector

CAM

1

5

1

2 3 4 5 6 7 8 9 1

0

1

2

1

3

14

16

ACES-CON14-9-GP

Camera Power

303mA

3D3V_S0

R5214 0R3J-0-U-GPR5214 0R3J-0-U-GP

1 2

F5204

1 2

DY

POLYSW-D5A6V-1-GP

69.50007.921

8 7 6

DMI

USB USB

C_CLK_C

USB USB

_CAMERA _CAMERA#

EL5

201

1 2

BLM15AG221SN-GP

68.00094.991

_PN6_TPNL _PP6_TPNL

TOUCH_PANEL_INTR# [24]

USB_CAMERA USB_CAMERA# DMIC_CLK DMIC_DATA 3D3V_CAMERA_S0

CAMERA

3D3V_CAMERA_S0

EC5202

SC1U6D3V2KX-GP

C5207

SC10U6D3V3MX-GP

12

DY

3D3

V_CAMERA_S0

C_CLK [27]

DMI

C_DATA [27]

TPA

N_VDD

SC10P50V2JN-4GP

AFTP5202AFTP 5202

1

AFTP5203AFTP 5203

1

AFTP5204AFTP 5204

1

AFTP5205AFTP 5205

1

AFTP5206AFTP 5206

1

EC5206

USB_CAMERA#

USB_CAMERA

DY

12

SC10P50V2JN-4GP

SC10P50V2JN-4GP EC5205

EC5205

A00 0618

0R0603-PAD-2-GP-U

R5225

12

R5221

0R0603-PAD-2-GP-U

USB_PN4 [16]

USB_PP4 [16]

need close to connector

eDP/ LVDS select circuit

eDP

C5215 SCD1U10V2KX-5GP

EDP_TX0_DN_CON_L[53] EDP_TX0_DP_CON_L[53]

LVDSA_DATA0#[ 53] LVDSA_DATA0[53]

EDP_TX1_DN_CON_L[53] EDP_TX1_DP_CON_L[53]

LVDSA_DATA1#[ 53] LVDSA_DATA1[53]

B B

EDP_AUX_DN_CON_L[53] EDP_AUX_DP_CON_L[53]

LVDS_DDC_DATA_R[53] LVDS_DDC_CLK_R[53]

1 2

C5216 SCD1U10V2KX-5GP

1 2

eDP

2 3

LVDS

1

eDP

1 2 1 2

eDP

2 3

LVDS

1

eDP

1 2 1 2

eDP

1 2 3

LVDS

4

RN5206 SRN0J-6-GP

C5218 SCD1U10V2KX-5GP

C5218 SCD1U10V2KX-5GP C5217 SCD1U10V2KX-5GP

C5217 SCD1U10V2KX-5GP

RN5207 SRN0J-6-GP

C5219 SCD1U10V2KX-5GP

C5219 SCD1U10V2KX-5GP C5220 SCD1U10V2KX-5GP

C5220 SCD1U10V2KX-5GP

RN5208 SRN0J-6-GP

Touch panel

X02 remove TPNL1

A A

EC5204

TPAN_VDD USB_PN6_TPNL USB_PP6_TPNL TOUCH_PANEL_INTR#

AFTP5210AFTP 5210

1

AFTP5208AFTP 5208

1

AFTP5209AFTP 5209

1

AFTP5207AFTP 5207

1

5

EC5204

SC10P50V2JN-4GP

EDP_TX0/LVDS_DATA0# EDP_TX0/LVDS_DATA0

EDP_TX1/LVDS_DATA1# EDP_TX1/LVDS_DATA1

EDP_AUX#/LVDS_DDC_DAT EDP_AUX/LVDS_DDC_CLK

USB_PN6_TPNL

USB_PP6_TPNL

12

DY

EC5203

SC10P50V2JN-4GP

need close to connector

INVERTER POWER

3D3V_S0

R5201 0R3J-0-U-GP

F5202 FUSE-2A32V-16-GP

A00 0618

0R0603-PAD-2-GP-U

R5223

12

A00 0618

12

R5220

0R0603-PAD-2-GP-U

A00 0618

4

POLYSW-1D1A24V-GP-U

69.50007.A31

2nd = 69.50007.D31

3rd = 69.50007.A41

1 2

LVDS

1 2

DY

EDP_HPD[15,53]

F5201

1 2

R5203 100R2J-2-GP

eDP

0307 modify

USB_PN6 [16]

USB_PP6 [16]

800mA

C5205

SCD1U50V3KX-GP

12

DCBATOUT_LCDDCBATOUT

12

DY

1 2

EDP_HP/LVDS_3D3V_ROM

0R3J-0-U-GP

0R3J-0-U-GP R5229

R5229

1 2

F5203

1 2

DY

POLYSW-D5A6V-1-GP

69.50007.921

C5202

3

SC1KP50V2KX-1GP

TPAN_VDD5V_S0

LCDVDD

EDP_VDD_EN[15]

LVDS_VDD_EN[53]

LCD_TST_EN[24]

R5207

1 2

eDP

0R2J-2-GP

R5208

1 2

DY

0R2J-2-GP

Layout Note:

Trace width = 80mil

LCDPWR_EN

2

D5201

1

eDP

2

BAT54CPT-2-GP

75.00054.K7D

LVDS_VDD_EN

LCD Power

3

12

R5209

eDP

100KR2J-1-GP

LCDVDD

R5211

1 2

0R3J-0-U-GP

2136_LCDVDD

R5212

1 2

0R3J-0-U-GP

2136_LCDVDD

EN_LCDPWR

600mA

3D3V_S0

U5201

1

EN

2

GND

3

VOUT

RT9724GB-GP

74.09724.09F

Layout Note:

Trace width = 80mil

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Friday, June 28, 2013

Date: Sheet of

74.09724.09F

LCDVDD

2136_LCDVDD

LCD Connector

Hadley 15"

5

VIN#5

eDP

4

VIN#4

eDP

12

R5202

100KR2J-1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

52 101

1

12

C5204

C5204 SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

X02

5

SID = VIDEO

S

LVDS & EDP Colay

_TX1_DN[8]

EDP EDP

_TX1_DP[8]

D D

EDP

_TX0_DN[8]

EDP

_TX0_DP[8]

EDP_AUX_DN[8] EDP_AUX_DP[8]

RN5304 SRN0J-6-GP

Brightness

L_BKLT_CTRL[ 15]

EDP_HPD[15,52]

4

LVDS

LVDS LVDS

LVDS

C52

09 SCD1U10V2KX-5GP

1 2

C52

10 SCD1U10V2KX-5GP

1 2

2 3

e

DP

1

RN5

303 SRN0J-6-GP

C52

C52 C52

C52

RN5302 SRN0J-6-GP

LVDS

LVDS LVDS

LVDS

C5213 SCD1U10V2KX-5GP

C5213 SCD1U10V2KX-5GP C5214 SCD1U10V2KX-5GP

C5214 SCD1U10V2KX-5GP

R5319 0R2J-2-GP

R5320 0R2J-2-GP

4

LVDS

LVDS LVDS

LVDS

11 SCD1U10V2KX-5GP

1 2

12 SCD1U10V2KX-5GP

1 2

2 3

eDP

1

4

1 2 1 2

1

4

2 3

eDP

1 2

LVDS

1 2

eDP

R5302

1KR2J-1-GP

1 2

LVDS

Lay

out Note:

Pla

ce near U5301

_TX1_DN_RTS2136

EDP EDP

_TX1_DP_RTS2136

EDP

_TX1_DN_CON_L

EDP

_TX1_DP_CON_L

_TX0_DN_RTS2136

EDP EDP

_TX0_DP_RTS2136

EDP_TX0_DN_CON_L EDP_TX0_DP_CON_L

EDP_AUX_DN_RTS2136 EDP_AUX_DP_RTS2136

EDP_AUX_DN_CON_L EDP_AUX_DP_CON_L

2136_PWM_IN

eDP_BKLT_CTRL

EDP_HPD_RTS2136

_TX1_DN_CON_L [52]

EDP EDP

_TX1_DP_CON_L [52]

EDP_TX0_DN_CON_L [52] EDP_TX0_DP_CON_L [52]

EDP_AUX_DN_CON_L [52] EDP_AUX_DP_CON_L [52]

3

eDP_BKLT_CTRL [52]

2

1

3D3V_S0

12

C5312

LVDS

3D3V_S0

12

LVDS

C5317

SCD

1U10V2KX-5GP

SWR_LX

RN5301

1 2 3

LVDS

4 5

SRN4K7J-10-GP

CIICSDA1

CIICSCL1

L5301

1 2

LVDS

MPZ1608S600AT-GP

68.00212.011

SCD

1U10V2KX-5GP

L5302

LVDS

1 2

MPZ1608S600AT-GP

68.00212.011

L5303

IND-4D7UH-300-GP

1 2

2136_SW

A00 0618

0R0603-PAD-2-GP-U

R5314

1 2

LVDS_DDC_DATA_R

8

LVDS_DDC_CLK_R

7 6

5

LVDS

C C

B B

A A

DP_AVCC33

C5301

SC10U6D3V3MX-GP

12

LVDS

DY

DP_DVCC33

C5302

SC10U6D3V3MX-GP

12

DY

SWR_V12

C5305

SC10U6D3V3MX-GP

12

C5306

LVDS

3D3V_S0

Q5301

1

LVDS

2

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

C5303

SCD1U10V2KX-5GP

C5313

SCD1U10V2KX-5GP

6

5

CIICSDA

CIICSCL

RN5307

1 2 3

DY

SRN0J-6-GP

RN5305

1 2 3

LVDS

SRN0J-6-GP

4

X02 change to 4 P2R

RN5306

1 2 3

LVDS

SRN100KJ-6-GP

EDP_AUX_DN_RTS2136 EDP_AUX_DP_RTS2136

EDP_TX0_DP_RTS2136 EDP_TX0_DN_RTS2136 EDP_TX1_DP_RTS2136 EDP_TX1_DN_RTS2136

Close to PIN5

DP_AVCC33

12

C5316

LVDS

SCD1U10V2KX-5GP

SML0_DATA [18] SML0_CLK [18]

BAT_SDA [24,43,44] BAT_SCL [24,43,44]

4

LVDS_R2136_BKLT_EN[24]

LVDS_DDC_DATA_R[52] LVDS_DDC_CLK_R[52]

TEST_MODE 2136_PWM_IN

C5310

SCD1U10V2KX-5GP

12

LVDS

PCH PCH

KBC KBC

EDP_HPD_RTS2136 TEST_MODE

DP_AVCC33

SWR_V12 DP_REXT

12

R5301

R5301 12KR2F-L-GP

12KR2F-L-GP

LVDS

eDP_BKLT_CTRL[52] LVDS_VDD_EN[52]

2136_PWM_IN

LVDS_DDC_DATA_R LVDS_DDC_CLK_R EEPROM_SDA0 EEPROM_SCL0

U5301

1

HPD

2

TEST

3

AUX_N

4

AUX_P

5

DP_V33

6

DP_GND

7

LANE0_P

8

LANE0_N

9

LANE1_P

10

LANE1_N

11

DP_V12

12

DP_REXT

CIICSCL1 CIICSDA1

3

48

49

46

GND

MIICSCL

MODE_CFG047MODE_CFG1

LVDS

CIICSCL13CIICSDA14SWR_VCCK15SWR_GND16SWR_LX17SWR_VDD18PWM_OUT19PANEL_VCC20PWM_IN21PVCC22TXE3+23TXE3-

SWR_V12

DP_DVCC33

12

C5308

SCD1U10V2KX-5GP

LVDS

SWR_V12

44

45

BL_EN

MIICSDA

SWR_LX

LVDS

43

12

SCD1U10V2KX-5GP

C5311

1 2

DY

38

39

40

41

42

VCCK

TXO1-

TXO0-

TXO1+

TXO0+

C5307

SC10U6D3V3MX-GP

Close to PIN13

37

TXO2-

TXO2+

TXOC-

TXOC+

TXO3-

TXO3+

TXE0-

TXE0+

TXE1-

TXE1+

TXE2TXE2+ TXEC-

TXEC+

RTD2136R-CGT-GP

24

71.02136.B03

DP_DVCC33

12

C5309

LVDS

SCD1U10V2KX-5GP

36 35 34 33 32 31 30 29 28 27 26 25

LVDSA_DATA0# [52] LVDSA_DATA0 [52] LVDSA_DATA1# [52] LVDSA_DATA1 [52] LVDS_DATA2#_R [52] LVDS_DATA2_R [52]

LVDS_CLK#_R [52] LVDS_CLK_R [52]

2

PIN48

3D3V_S0

R5306

R5317

12

4K7R2J-2-GP

DY

12

R5307

R5318

4K7R2J-2-GP

LVDS

DY

EEPROM_SCL0 EEPROM_SDA0

LVDS

Operation Mode Table

PIN47

0

1

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

X

ROM EEPOOM

LVDS_Switch

Hadley 15"

Friday, June 28, 2013

Hadley 15"

1

EP Mode

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

53 101

1

X02

5

S

ID = VIDEO

S

5

_S0

V

5

_HDMI_S0

5

_S0

V

5

401

F

D D

C C

B B

1 2

POLYSW -1D1A8V-5-GP

V

HDMI_CLK#[8] HDMI_CLK[8]

HDMI_DATA 0#[8] HDMI_DATA 0[8]

HDMI_DATA 1#[8] HDMI_DATA 1[8]

HDMI_DATA 2#[8] HDMI_DATA 2[8]

PCH_HDM I_CLK[1 5]

PCH_HDM I_DATA[15]

U

401

5

G

S

2N7002K -2-GP

8

.2N702.J31

4

C5401 SCD1U1 0V2KX-5GPC5401 SCD1U1 0V2KX-5GP

1 2

C5402 SCD1U1 0V2KX-5GPC5402 SCD1U1 0V2KX-5GP

1 2

C5403 SCD1U1 0V2KX-5GPC5403 SCD1U1 0V2KX-5GP

1 2

C5404 SCD1U1 0V2KX-5GPC5404 SCD1U1 0V2KX-5GP

1 2

C5405 SCD1U1 0V2KX-5GPC5405 SCD1U1 0V2KX-5GP

1 2

C5406 SCD1U1 0V2KX-5GPC5406 SCD1U1 0V2KX-5GP

1 2

C5407 SCD1U1 0V2KX-5GPC5407 SCD1U1 0V2KX-5GP

1 2

C5408 SCD1U1 0V2KX-5GPC5408 SCD1U1 0V2KX-5GP

1 2

H

D

SRN470J -5-GP

3D3V_S0

5

6

Q5401

Q5401 2N7002K DW-GP

2N7002K DW-GP

84.2N702.A3F

D

MI_PLL_GN D

RN5402

34

2

1

4

307 change RN5401 RN5402 form

0 680 ohm to 470 ohm

123

45

123

45

RN5401

RN5401 SRN470J -5-GP

SRN470J -5-GP

678

5V_HDMI_S 0

3

2

D5102_2

4

RN5203

RN5203 SRN2K2J -1-GP

SRN2K2J -1-GP

1

2 3

DDC_CLK _HDMI

DDC_DAT A_HDMI

678

HDMI_CLK_ R_C# HDMI_CLK_ R_C

HDMI_DATA 0_R_C# HDMI_DATA 0_R_C

HDMI_DATA 1_R_C# HDMI_DATA 1_R_C

HDMI_DATA 2_R_C# HDMI_DATA 2_R_C

D5401

D5401 BAW5 6-11-GP

BAW5 6-11-GP

75.00056.B7D

1

2nd = 75.00056.A7D

D5102_1

3

D

MI_CLK_R_ C

H

HDMI_CLK_ R_C#

HDMI_DATA 0_R_C

HDMI_DATA 0_R_C#

0R3J-0-U-G P

5

401

R

1 2

A

0 0618

0

1 2

R5402

R5402 0R3J-0-U-G P

0R3J-0-U-G P

0R3J-0-U-G P R5403

R5403

1 2

A00 0618

1 2

R5404

R5404 0R3J-0-U-G P

0R3J-0-U-G P

www.qdzbwx.com

D

MI_CLK_R_ C_CON

H

A00 0619

12

E

5401

R

150R2J-L 1-GP-U

HDMI_CLK_ R_C#_CON

ER5401~04 change to 180R

HDMI_DATA 0_R_C_CON

A00 0619

12

ER5402

ER5402 150R2J-L 1-GP-U

150R2J-L 1-GP-U

HDMI_DATA 0_R_C#_CON

HDMI_DATA 2_R_C_CON

HDMI_DATA 2_R_C#_CON HDMI_DATA 1_R_C_CON

HDMI_DATA 1_R_C#_CON HDMI_DATA 0_R_C_CON

HDMI_DATA 0_R_C#_CON HDMI_CLK_ R_C_CON

HDMI_CLK_ R_C#_CON

1

12

TP5411TP5411

DDC_CLK _HDMI DDC_DAT A_HDMI

1

5V_HDMI_S 0

AFTP540 1AFTP5401

C5417

SCD1U10 V2KX-5GP

3D3V_S0

2

H

HDMI_DATA 2_R_C#

HDMI_DATA 1_R_C

HDMI_DATA 1_R_C#

HPD_HDM I_CON

D

MI_DATA2_ R_C

0R3J-0-U-G P

5

405

R

1 2

A

0 0618

0

1 2

R5406

R5406 0R3J-0-U-G P

0R3J-0-U-G P

0R3J-0-U-G P R5407

R5407

1 2

A00 0618

1 2

R5408

R5408 0R3J-0-U-G P

0R3J-0-U-G P

HDMI CONN

HDMI1

22 20

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

21 23

SKT-HDMI23 -97-GP

22.10296.A31

D

MI_DATA2_ R_C_CON

H

HDMI_DATA2 _R_C#_CON

HDMI_DATA1 _R_C_CON

HDMI_DATA1 _R_C#_CON

1

A00 0619

12

E

5403

R

150R2J-L 1-GP-U

A00 0619

12

ER5404

ER5404 150R2J-L 1-GP-U

150R2J-L 1-GP-U

3

PMBS390 4-1-GP

PMBS390 4-1-GP Q5402

Q5402

R5413

HDMI_HPD_ E

A A

5

4

HDMI_PCH_ DET[15]

1 2

0R0402-P AD-2-GP

3

1

84.03904.L06

2

12

R5414

R5414 10KR2J-3 -GP

10KR2J-3 -GP

HDMI_HPD_ B

R5411

1 2

150KR2J -L1-GP

DY

12

R5412

R5412 20KR2J-L 2-GP

20KR2J-L 2-GP

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Repeater/Connector

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

54 10 1

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

55 10 1Friday, June 28, 201 3

1

X02

SSI

D = SATA

SATA3_P TX_DRX_P0[19 ]

SATA3_P TX_DRX_N0[19]

3D3V_S0

R5601

10KR2J-3 -GP

R5605

10KR2J-3 -GP

5V_

SC10U6D3V3MX-GP

C5602

Layout Note:

AC coupling Cap; place near CONN(<100mils)

3D3V_S0

C5609 SCD0 1U16V2KX-3GPC56 09 SCD 01U16V2KX-3GP

1 2 1 2

C5610 SCD0 1U16V2KX-3GPC56 10 SCD 01U16V2KX-3GP

12

DY

12

R5606

10KR2J-3 -GP

R5609

10KR2J-3 -GP

3D3V_S0

DY

12

R5611

4K7R2J-2 -GP

R5610

4K7R2J-2 -GP

DY

S0

12

C56

C56 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

DY

SATA3_D RX_CTX_P0 SATA3_D RX_CTX_N0

SC1U6D3V2KX-GP

C5613

3D3V_S0

12

DY

12

4K7R2J-2 -GP

03

Need to check conn pin define

C5601 SCD01U1 6V2KX-3GPC560 1 SCD 01U16V2KX-3GP C5604 SCD01U1 6V2KX-3GPC560 4 SCD 01U16V2KX-3GP

C5606 SCD01U1 6V2KX-3GPC560 6 SCD 01U16V2KX-3GP C5605 SCD01U1 6V2KX-3GPC560 5 SCD 01U16V2KX-3GP

SC1U6D3V2KX-GP

C5611

C5612

12

SATA3_P TX_DRX_P0_R SATA3_P TX_DRX_N0_R SATA3_D RX_CTX_P0 SATA3_D RX_CTX_N0

SATA3_D E1_HDD SATA3_D E2_HDD

HDD_DEW 1 HDD_DEW 2

3D3V_S0

12

R5613

DY

HDD CONN

20.F2036.020

A00 0618

0R0402-P AD-2-GP

HDD_DEV SLP[20]

FFS_INT2_ Q[67]

1 2 1 2

12 12

12

1 2

HDD

R56

02

5V_S0

0R0402-P AD-2-GP

R5614

1 2

SATA3_D RX_CTX_P0_C SATA3_D RX_CTX_N0_C

SATA3_D TX_CRX_N0_CSATA3_D TX_CRX_N0 SATA3_D TX_CRX_P0_CSATA3 _DTX_CRX_P0

_DEVSLP _R

FFS_INT2_ Q_R

20.F2036.020

ACES-CON 20-28-GP

20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2

1

HDD1

2

4

23

22

21

HDD Re-driver

C5607 SCD0 1U16V2KX-3GPC56 07 SCD 01U16V2KX-3GP

U5601

10 20

1

2 11 12

9

8

16

6

SN75LVC P601RTJR-GP

TX1P

VCC

TX1N

VCC

TX2P

TX2N RX1P RX1N RX2P RX2N

DE1 DE2

DEW1 DEW2

71.75601.003

EQ1 EQ2

GND GND GND GND

15 14 5 4

17 19

7

EN

3 13 18 21

SATA3_D TX_CRX_P0 SATA3_D TX_CRX_N0 SATA3_P RX_DTX_P0_L SATA3_P RX_DTX_N0_L

SATA3_E Q1_HDD SATA3_E Q2_HDD

3D3V_S0

1 2 1 2

C5608 SCD0 1U16V2KX-3GPC56 08 SCD 01U16V2KX-3GP

3D3V_S0

12

DY

12

DY

R5604

R5604 10KR2J-3 -GP

10KR2J-3 -GP

R5608

R5608 10KR2J-3 -GP

10KR2J-3 -GP

SATA3_P RX_DTX_P0 [19]

SATA3_P RX_DTX_N0 [19]

3D3V_S0

12

R5603

R5603 10KR2J-3 -GP

10KR2J-3 -GP

DY

12

R5607

R5607 10KR2J-3 -GP

10KR2J-3 -GP

DY

R5612

4K7R2J-2 -GP

12

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

HDD

56 10 1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

57 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = Wireless

D D

3D3V_S0 3D3V_W LAN_AOAC

3D3V_S5

C5804

SC1U6D3V2KX-GP

AOAC

C C

1210 Low Active change to High Active (Need to confirm with the SW)

B B

AOAC

AOAC_W LAN_EN[24]

USB_PN5 _R

SC1U6D3V2KX-GP

1 2

12

100KR2J-1-GP

R5808

DY

A00 0618

R5801 0R0603-PAD -2-GP-UR5801 0R0603-PAD -2-GP-U

1 2

R5806

0R3J-0-U-G P

1 2

NON AOAC

U5801

AOAC

1

GND

2

IN#2

3

IN#3 EN/EN#4OCB

SY6288CCA C-GP

74.06288.079

A00 0618

USB_PP5 _R

A00 0618

R5805 0R0603-PAD -2-GP-UR5805 0R0603-PAD -2-GP-U

1 2

OUT#8 OUT#7 OUT#6

4

8 7 6 5

USB_PN5 [16]

USB_PP5 [16 ]

1.1A

3D3V_W LAN_AOAC

SC10U6D3V3MX-GP

C5801

12

3

1 modify power rail

031

3D3V_W LAN_AOAC

12

R5809

R5809 10KR2J-3 -GP

10KR2J-3 -GP

WIFI_W AKE#[2 4]

TP5802TP5802

1

TP5803TP5803

1

CLK_PCIE_ WLAN_REQ3 #[18]

CLK_PCIE_ WLAN_N3[1 8]

CLK_PCIE_ WLAN_P3[18]

TP5801TP5801

1

R5803 0R2J-2-GP

E51_TxD[24]

WIFI_RF_ EN[24]

PCIE_PRX_ WLANTX_N3[16]

PCIE_PRX_ WLANTX_P3[16]

PCH_SMB CLK[12,13,18,62 ,67]

PCIE_PTX_ WLANRX_N3 _C[16]

PCH_SMB DATA[12,13,18,6 2,67]

PCIE_PTX_ WLANRX_P3 _C[16]

12

C5806

SCD1U10V2KX-5GP

C5805

C5805 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

A00 0618

PLT_RST #[17,24,30,6 5,73]

BLUETOO TH_EN[20]

1 2

DY

0R0402-P AD-2-GP

R5804

1 2

5V_S5

10KR2J-3 -GP

10KR2J-3 -GP R5807

R5807

1 2

DY

2

WLAN _ACT

BT_ACT

E51_RxD_R

E51_TxD_R

WLAN _22

USB_PN5 _R

USB_PP5 _R

WLAN CONN

WLAN 1

54

NP1

1 2

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

NP2

53

MINIPCI52P-8-GP-U 1

62.10043.B91

1

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

WLAN/BT

58 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

59 10 1Friday, June 28, 201 3

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

60 10 1Friday, June 28, 201 3

X02

5

D = User.Interface

SSI

4

3

2

1

PWRBTN CONN

PWB

T1

AFTP610 1AFTP6101 AFTP610 2AFTP6102 AFTP610 7AFTP6107

5

1

2 3 4

6

ACES-CON 4-50-GP

20.K0722.004

D D

Battery LED1(Amber_LED)

LOW

actived from KBC GPIO

CHG_AMB ER_LED#_R

2nd = 84.DT144.A11

Q6104

B

R1

PDTA144 VT-GP

84.00144.P11

3D3

RN6

101

KBC

_PW RBTN#[24]

LID_CLOSE #[24]

R2

5V_S5

E

C

LED_BAT

EC6104

DY

SC220P50V2KX-3GP

1 2

R6107

12

680R2J-3 -GP

BAT_AMB ER_LED_A

1 2 3

4

SRN100J -3-GP

V_S5

_PW RBTN#_C

KBC LID

_CLOSE# _C

3D3V_S5 KBC_PW RBTN#_C LID_CLOSE #_C

1 1 1

Power & Battery LED2(White_LED)

LOW actived from KBC GPIO

C C

Q6103

R2

RN6102

RN6102 0R8P4R-P AD-1-GP

0R8P4R-P AD-1-GP

RN

CHG_AMB ER_LED#[24]

PWRL ED#[24 ] SATA_LE D#[19]

1 2 3 4 5

CHG_AMB ER_LED#_R

8

PWRL ED#_R

7

SATA_LE D#_R

6

PWRL ED#_R

2nd = 84.DT144.A11

B

R1

PDTA144 VT-GP

84.00144.P11

R2

SATA HDD LED

B B

Q6105

R2

SATA_LE D#_R

2nd = 84.DT144.A11

R2

B

R1

PDTA144 VT-GP

84.00144.P11

5V_S5

E

C

E

C

5V_S0

SATA_LE D_R

LED_BAT CHG

EC6103

DY

SC220P50V2KX-3GP

DY

12

1 2

R6106

12

680R2J-3 -GP

BAT_W HITE_LED_A

LED board CONN

LEDBD1

5

1

2 3 4

6

ACES-CON 4-50-GP

20.K0722.004

AFTP610 3AFTP6103 AFTP610 4AFTP6104 AFTP610 5AFTP6105 AFTP610 6AFTP6106

EC6105

1 2

R6108

680R2J-3 -GP

HDD_LED _A

BAT_W HITE_LED_A

BAT_AMB ER_LED_A HDD_LED _A

BAT_W HITE_LED_A BAT_AMB ER_LED_A GND HDD_LED _A

1 1 1 1

SC220P50V2KX-3GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

LED Bar/Power Button

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

61 10 1

1

X02

5

4

3

2

1

D = KBC

SSI

D = Touch.Pad

SSI

Internal Keyboard Connector

0R0603-P AD-2-GP-U

TP_VDD

1

23

RN6201

SRN10KJ -5-GP

4

12

DY

X01 0321

09

R62

1 2

SRN33J-5 -GP-U

1 2 3

SC33P50V2JN-3GP

EC6202

RN6202

12

DY

TP_

VDD

Touch Pad Connector

TP_VDD

12

C6201

20.K0721.006

ACES-CON 6-52-GP

1

ACES-CON 6-52-GP

8

6 5 4 3 2

1

7

TP1

SCD1U10V2KX-5GP

AFTP621 4AFTP6214

TPCLK_C TPDATA_ C

4

PCH_SMB CLK[12,13,18,58 ,67]

PCH_SMB DATA[12,13,18,5 8,67]

3D3

V_S0

KB1

AFT

P6201

D D

KROW [0..7][24 ]

KCOL[0..16 ][24]

C C

DET#[20]

KB_

AFTP623 8AFTP6238

AFT

AFT AFT

AFT AFTP620 4AFTP6204 AFTP620 5AFTP6205 AFTP620 6AFTP6206 AFTP620 7AFTP6207 AFTP620 8AFTP6208 AFTP620 9AFTP6209 AFTP621 0AFTP6210 AFTP621 1AFTP6211 AFTP621 2AFTP6212 AFTP621 3AFTP6213 AFTP621 5AFTP6215 AFTP621 6AFTP6216 AFTP621 7AFTP6217 AFTP621 8AFTP6218 AFTP621 9AFTP6219 AFTP622 0AFTP6220 AFTP622 1AFTP6221 AFTP622 2AFTP6222 AFTP622 3AFTP6223 AFTP622 5AFTP6225 AFTP622 4AFTP6224 AFTP622 6AFTP6226 AFTP622 7AFTP6227

CAP_LED

1

P6202

P6202 P6203

P6203

AFTP622 8AFTP6228

1

W7

KRO

1

KRO

W6

1

KROW 4

1

KROW 2

1

KROW 5

1

KROW 1

1

KROW 3

1

KROW 0

1

KCOL5

1

KCOL4

1

KCOL7

1

KCOL6

1

KCOL8

1

KCOL3

1

KCOL1

1

KCOL2

1

KCOL0

1

KCOL12

1

KCOL16

1

KCOL15

1

KCOL13

1

KCOL14

1

KCOL9

1

KCOL11

1

KCOL10

1

CAP_LED

1

CAP LED Control

KB1

1

3

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32

A

CES-CON3 0-10-GP

20.K0592.030

TPCLK[24]

TPDATA[24]

EC6201

SC33P50 V2JN-3GP

LOW actived from KBC GPIO

Q6201

A0

0618

0

CAP_LED #[24]

1 2

0R0402-P AD-2-GP

R6202

CAP_LED _R#

Q6201

B

R1

PDTA144 VT-GP

84.00144.P11

2nd = 84.DT144.A11

5V_S0 CAP_LED

R2

E

C

R6201

1 2

1KR2J-1-G P

TP_VDD TPCLK_C

CAP_LEDCAP_LE D_Q

TPDATA_ C PCH_SMB CLK PCH_SMB DATA

AFTP622 9AFTP6229

1

AFTP623 0AFTP6230

1

AFTP623 1AFTP6231

1

AFTP623 2AFTP6232

1

AFTP623 3AFTP6233

1

B B

F6201

1 2

DY

POLYSW -D5A6V-1-GP

69.50007.921

1 2

R6205 0R3J-0-U-G PR6205 0R3J-0-U -GP

KB_LED_ BL_DET[20]

A A

5

KB_BL_C TRL[24]

12

C6202

C6202 SCD1U10 V2KX-5GP

SCD1U10 V2KX-5GP

R6206

1 2

12

51KR2J-1 -GP

R6207

R6207 100KR2J -1-GP

100KR2J -1-GP

DY

12

+5V_KB_ BL5V_S0

KB_LED_ DET_C

12

C6203

DY

R6208

R6208 100KR2J -1-GP

100KR2J -1-GP

SCD1U10V2KX-5GP

G

KB_BL_CTRL#

DS

Q6202

Q6202 P8503BM G-GP

P8503BM G-GP

84.P8503.031

2nd = 84.03404.C31

4

KBLIT1

5

1

2 3 4

6

ACES-CON 4-50-GP

20.K0722.004

+5V_KB_ BL KB_LED_ DET_C KB_BL_C TRL#

1

AFTP623 4AFTP6234

1 1 1

AFTP623 5AFTP6235 AFTP623 6AFTP6236 AFTP623 7AFTP6237

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

3

2

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

62 10 1

1

X02

5

SSI

D = User.Interface

D D

4

3

2

1

A00 0618

IOBD1

41

1

2 3 4 5 6 7 8

C C

B B

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

42

ACES-CON 40-18-GP

20.K0678.040

USB30_V CCC

USB30_V CCD

3D3V_S0

USB20_D N3_C USB20_D P3_C

USB20_D N2_C USB20_D P2_C

SATA3_P TX_DRX_N1_R SATA3_P TX_DRX_P1_R

SATA3_P RX_DTX_N1_R SATA3_P RX_DTX_P1_R

USB30_V CCC USB3 0_VCCD 3D3V _S0

SCD1U10V2KX-5GP

EC6301

12

DY

USB3_PR X_DTX_N3 [16] USB3_PR X_DTX_P3 [16]

USB3_PT X_DRX_N3 [16 ] USB3_PT X_DRX_P3 [16]

USB3_PR X_DTX_N2 [16] USB3_PR X_DTX_P2 [16]

USB3_PT X_DRX_N2 [16 ] USB3_PT X_DRX_P2 [16]

DY

C6002 SCD0 1U16V2KX-3GP

1 2 1 2

DY

C6013 SCD0 1U16V2KX-3GP

C6013 SCD0 1U16V2KX-3GP C6012 SCD0 1U16V2KX-3GP

C6012 SCD0 1U16V2KX-3GP

1 2

DY

1 2

DY

C6001 SCD0 1U16V2KX-3GP

MSATA_D ET# [19]

DY

A00 0628

SCD1U10V2KX-5GP

EC6302

DY

SCD1U10V2KX-5GP

EC6303

12

USB20_D N2_C

USB20_D P2_C

1 2

TR6301

FILTER-4P-6 2-GP

34

USB_PN2 [16]

69.10080.021

2nd = 69.10103.061

USB_PP2 [16 ]

A00 0618

SATA3_P TX_DRX_N1 [19] SATA3_P TX_DRX_P1 [19]

SATA3_P RX_DTX_N1 [19] SATA3_P RX_DTX_P1 [19]

MSATA_D EVSLP [20]

USB20_D N3_C

USB20_D P3_C

1 2

TR6302

FILTER-4P-6 2-GP

34

USB_PN3 [16]

69.10080.021

2nd = 69.10103.061

USB_PP3 [16 ]

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector

Size Document N umber Rev

A3

Date: Sheet of

IO Board Connector

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

63 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

64 10 1

1

X02

5

D = DEBUG PORT

SSI

4

3

2

1

Debug Connector

DB1

LPC

A00 0625

D D

LPC_AD[3 ..0][18,24]

C C

LPC_AD[3 ..0]

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRA ME#[18,24] PLT_RST #[17,24,30,5 8,73]

0R8P4R-P AD-1-GP

lace near trace separated point

P

RN6501

RN

1 2 3 4 5

R65010R 0402-PAD-2-GP R65010R 0402-PAD-2-GP

1 2

R65020R 0402-PAD-2-GP R65020R 0402-PAD-2-GP

1 2

8 7 6

LPC_LAD 0_R LPC_LAD 1_R LPC_LAD 2_R LPC_LAD 3_R LPC_FRA ME#_DEBUG PLT_RST #_DEBUG

CLK_PCI_L PC[18]

3D3

V_S0

11

1

2 3 4 5 6 7 8

9 10 12

P

AD-10P-17 7042-GP

ZZ.00PAD.Y41

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Dubug connector

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

65 10 1

1

X02

5

D D

C C

4

3

2

1

B B

A A

5

4

(Blanking)

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document Number Rev

Size Document Number Rev A4

A4

Friday, June 28, 2013

Date: Sheet of

2

Reserved

Hadley 15"

66 101

1

X02

5

D = User.Interface

SSI

D D

4

3

2

1

Note:

- no via, trace, under the sensor (keep out area around 2mm)

- stay away from the screw hole or metal shield soldering joints

- design PCB pad based on our sensor LGA pad size (add 0.1mm)

Free Fall Sensor

C C

10

RES#10

13

RES#13

15

RES#15

16

RES#16

PCH_SMB CLK[12,13,18,58 ,62] PCH_SMB DATA[12,13,18,5 8,62]

3D3V_RU N_FFS

4

SCL/SPC

6

SDA/SDI/SDO

SDO/SA07CS

5

GND

12

GND

LNG3DMT R-GP

74.LNG3D.0BZ

FFS

U6701

VDD_IO

VDD

INT1 INT2

NC#2 NC#3

1

14

11 9

8

2 3

3D3V_RU N_FFS

SCD1U16V2KX-3GP

C6703

12

FFS

SCD1U16V2KX-3GP

C6702

C6701

12

DY

3D3V_S0

A00 0618

0R0603-P AD-2-GP-U

R6701

1 2

SC10U6D3V3MX-GP

- solder stencil opening to 90% of the PCB pad size

- mount the sensor near the center of mass of the NB as possible as you can

3D3V_S0

HDD_FAL L_INT

HDD_FAL L_INT [15]

Need to check GPIO

2N7002K DW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

4th = 84.2N702.F3F

Q6701

FFS

12

34

R6703

R6703 100KR2J -1-GP

100KR2J -1-GP

FALL_INT2

1

2

FFS

5

6

B B

Note:

(1) Keep all signals are the same trace width. (included VDD, GND). (2) No VIA under IC bottom.

FFS_INT2

FFS_INT2 [20]

FFS_INT2_ Q [56]

Need to check conn pin define

Need to check GPIO

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

FFS

1

67 10 1Friday, June 28, 201 3

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

68 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

69 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

70 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

71 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

72 10 1Friday, June 28, 201 3

1

X02

5

S

SID = VIDEO

D73

K A

O

PLT

_RST#[17,24,30,58,65]

U_HOLD_RST#[15]

D D

PEG_CLKREQ#[ 18]

C C

B B

A A

DGP

3D3

Q7301

D

OPS

2N7002K-2-GP

84.2N702.J31

1 2

DY

R7305

0R2J-2-GP

5

O

1SS400GPT-GP

83.00400.C1F

2

ND = 83.27101.01F

3RD = 83.01426.01F

0R0402-PAD-2-GP

A00

0618

1 2

V_VGA_S0

R7308

G

10KR2J-3-GP

OPS

1 2

S

PS

R73

01

CPU_RXP_C_dGPU_TXP0[16] CPU_RXN_C_dGPU_TXN0[16]

dGPU_RXP_C_CPU_TXP0[16] dGPU_RXN_C_CPU_TXN0[16]

CPU_RXP_C_dGPU_TXP1[16] CPU_RXN_C_dGPU_TXN1[16]

dGPU_RXP_C_CPU_TXP1[16] dGPU_RXN_C_CPU_TXN1[16]

CPU_RXP_C_dGPU_TXP2[16] CPU_RXN_C_dGPU_TXN2[16]

dGPU_RXP_C_CPU_TXP2[16] dGPU_RXN_C_CPU_TXN2[16]

CPU_RXP_C_dGPU_TXP3[16] CPU_RXN_C_dGPU_TXN3[16]

dGPU_RXP_C_CPU_TXP3[16] dGPU_RXN_C_CPU_TXN3[16]

04

dGPU Reset

4

CLK_PCIE_VGA[18] CLK_PCIE_VGA#[18]

C7301 SCD22U10V2KX-1GP

1 2

OPS

C7302 SCD22U10V2KX-1GP

1 2

OPS

C7303 SCD22U10V2KX-1GP

1 2

OPS

C7304 SCD22U10V2KX-1GP

1 2

OPS

C7305 SCD22U10V2KX-1GP

1 2

OPS

C7306 SCD22U10V2KX-1GP

1 2

OPS

C7307 SCD22U10V2KX-1GP

1 2

OPS

C7308 SCD22U10V2KX-1GP

1 2

OPS

4

VGA

_RST# [76]

VGA_RST#

GPU_CLKREQ#

dGPU_TXP_CPU_RXP0 dGPU_TXN_CPU_RXN0

dGPU_TXP_CPU_RXP1 dGPU_TXN_CPU_RXN1

dGPU_TXP_CPU_RXP2 dGPU_TXN_CPU_RXN2

dGPU_TXP_CPU_RXP3 dGPU_TXN_CPU_RXN3

GPU

AJ11

AJ12

AK12

AL13

AK13

AK14

AJ14

AN12

AM12

AH14 AG14

AN14

AM14

AK15

AJ15

AP14 AP15

AL16

AK16

AN15

AM15

AK17

AJ17

AN17

AM17

AH17 AG17

AP17 AP18

AK18

AJ18

AN18

AM18

AL19

AK19

AN20

AM20

AK20

AJ20

AP20 AP21

AH20 AG20

AN21

AM21

AK21

AJ21

AN23

AM23

AL22

AK22

AP23 AP24

AK23

AJ23

AN24

AM24

AH23 AG23

AN26

AM26

AK24

AJ24

AP26 AP27

AL25

AK25

AN27

AM27

N14P-GS-A1-GP

71.0N14P.00U

1A

1/17 PCI_EXPRESS

PEX_WAKE#

PEX_RST#

PEX_CLKREQ#

PEX_REFCLK PEX_REFCLK#

PEX_TX0 PEX_TX0#

PEX_RX0 PEX_RX0#

PEX_TX1 PEX_TX1#

PEX_RX1 PEX_RX1#

PEX_TX2 PEX_TX2#

PEX_RX2 PEX_RX2#

PEX_TX3 PEX_TX3#

PEX_RX3 PEX_RX3#

PEX_TX4 PEX_TX4#

PEX_RX4 PEX_RX4#

PEX_TX5 PEX_TX5#

PEX_RX5 PEX_RX5#

PEX_TX6 PEX_TX6#

PEX_RX6 PEX_RX6#

PEX_TX7 PEX_TX7#

PEX_RX7 PEX_RX7#

PEX_TX8 PEX_TX8#

PEX_RX8 PEX_RX8#

PEX_TX9 PEX_TX9#

PEX_RX9 PEX_RX9#

PEX_TX10 PEX_TX10#

PEX_RX10 PEX_RX10#

PEX_TX11 PEX_TX11#

PEX_RX11 PEX_RX11#

PEX_TX12 PEX_TX12#

PEX_RX12 PEX_RX12#

PEX_TX13 PEX_TX13#

PEX_RX13 PEX_RX13#

PEX_TX14 PEX_TX14#

PEX_RX14 PEX_RX14#

PEX_TX15 PEX_TX15#

PEX_RX15 PEX_RX15#

3

GK107/GF108

GK208/GF117

GF108

PEX LANES 8 TO 15 NC FOR GF117/ GK208

3

NC

GK208/GK107/GF117

OPS

1 OF 17

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

NC_3V3AUX

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

PEX_PLLVDD

TESTMODE

PEX_TERMP

12

OPS

23

C73

SC10U6D3V3MX-GP

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

C7320

SC10U6D3V3MX-GP

12

OPS

X7R, Under GPU.

L4

L5

P8

PEXTSTCLK_OUT

AJ26

PEXTSTCLK_OUT#

AK26

AG26

R7302

TESTMODE

PEX_TERMP

1 2

OPS

10KR2J-3-GP

R7301

1 2

OPS

2K49R2F-GP

AK11

AP29

OPS

10

C73

SC10U6D3V3MX-GP

OPS

C7321

SC10U6D3V3MX-GP

R7303

200R2F-L-GP

1 2

DY

12

C7316

SCD1U10V2KX-5GP

C73

C7309

OPS

12

22

SC10U6D3V3MX-GP

SC4D7U6D3V3KX-GP

OPS

12

C7315

2

C73

C7311

SC4D7U6D3V3KX-GP

OPS

C7318

SCD1U10V2KX-5GP

2

12

OPS

12

C73

SC1U6D3V2KX-GP

12

OPS

C7314

SC1U6D3V2KX-GP

12

C7324

SC4D7U6D3V3KX-GP

OPS

VGA_SENSE [82]

GND_SENSE [82]

12

OPS

12

OPS

13

SC1U6D3V2KX-GP

12

OPS

SC1U6D3V2KX-GP

12

C7317

SC4D7U6D3V3KX-GP

12

OPS

25

C73

SC10U6D3V3MX-GP

12

OPS

C7327

SC10U6D3V3MX-GP

3D3V_VGA_S0

POWER IC

12

C7319

OPS

1

1D0

5V_VGA_S0

12

OPS

26

C73

SC10U6D3V3MX-GP

1.05V +/- 30mV

3.3A

1D05V_VGA_S0

12

OPS

C7328

SC4D7U6D3V3KX-GP

3.3V +/- 5% 210mA

1.05V +/- 30mV 150mA

1D05V_VGA_S0

0102 remove R7307

12

SC1U6D3V2KX-GP

OPS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

GPU_PCIE/STRAPPING(1/5)

Hadley 15"

1

X02

of

73 101Friday, June 28, 2013

5

SID = VIDEO

S

GPU

1J

5/1

7 IFPAB

ALL

PINS NC FOR GF117

DP(GK208)

DPA_L3

DPA_L3 DPA_L3

IFPD

DPA_L3

DPA_L2

DPA_L2 DPA_L2

DPA_L2

DPA_L1

DPA_L1 DPA_L1

DPA_L1

DPA_L0

DPA_L0 DPA_L0

DPA_L0

DPB_L3

DPB_L3 DPB_L3

DPB_L3

DPB_L2

DPB_L2 DPB_L2

DPB_L2

DPB_L1

DPB_L1 DPB_L1

DPB_L1

DPB_L0

DPB_L0 DPB_L0

DPB_L0

I2CX_SDA

I2CX_SDA I2CX_SCL

I2CX_SCL

DVI/HDMI

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

D D

IFPAB_PLLVDD

TP7401TP7401

1

TP7402TP7402

TP7403TP7403

C C

B B

TP7404TP7404

TP7405TP7405

A A

IFPA_IOVDD IFPC_IOVDD

1

IFPB_IOVDD

1

IFPD_PLLVDD

1

IFPD_IOVDD

1

5

AJ8

IFP

AH8

IFPAB_PLLVDD

AG8

IFPA_IOVDD

AG9

IFPB_IOVDD

IFPAB

N14P-GS-A1-GP

71.0N14P.00U

OPS

GPU1L

7/17 IFPD

AN2

IFPD_RSET

AG7

IFPD_PLLVDD

AG6

IFPD_IOVDD

N14P-GS-A1-GP

71.0N14P.00U

OPS

AB_RSET

ALL PINS NC FOR GF117

LVDS

IFP

IFPA_TXD1#

IFPA_TXD1

IFPA_TXD2#

IFPA_TXD2

IFPA_TXD3#

IFPA_TXD3

IFPB_TXC#

IFPB_TXC

IFPB_TXD4#

IFPB_TXD4

IFPB_TXD5#

IFPB_TXD5

IFPB_TXD6#

IFPB_TXD6

IFPB_TXD7#

IFPB_TXD7

IFPD_AUX_I2CX_SDA#

IFPD_AUX_I2CX_SCL

10 OF 17

A_TXC#

A_TXC

A_TXD0#

A_TXD0

GPIO14

DP

12 OF 17

IFPD_L3#

IFPD_L3

IFPD_L2#

IFPD_L2

IFPD_L1#

IFPD_L1

IFPD_L0#

IFPD_L0

GPIO17

4

AN6 AM6

AN3 AP3

AM5 AN5

AK6 AL6

AH6 AJ6

AH9 AJ9

AP5 AP6

AL7 AM7

AM8 AN8

AL8 AK8

TP7

406

TP7407TP7407

N4

TP7408TP7408

AK2 AK3

AK5 AK4

AL4 AL3

AM4 AM3

AM2 AM1

TP7409TP7409

TP7410TP7410

M6

4

1

IFPEF_PLLVDD

1

IFPE_IOVDD

1

IFPF_IOVDD

1

C_PLLVDD

IFP

3

1K

GPU

6/17 IFPC

ALL

PINS NC FOR GF117

AF8

IFP

C_RSET

AF7

C_PLLVDD

IFP

AF6

IFPC_IOVDD

N14P-GS-A1-GP

71.0N14P.00U

OPS

GPU1M

8/17 IFPEF

AB8

IFPEF_PLLVDD

AD6

IFPEF_RSET

NC FOR GK208

IFPE

AC7

IFPE_IOVDD

AC8

IFPF_IOVDD

NC FOR GK208

IFPF

N14P-GS-A1-GP

71.0N14P.00U

OPS

3

DVI/HDMI DP

I2CW_SDA

I2CW_SDA I2CW_SCL

I2CW_SCL

TXC

TXC TXC

TXC

TXD0

IFPC

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

ALL PINS NC FOR GF117

I2CY_SDA

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

HPD_E

TXD3

TXD3 TXD3

TXD3

TXD4

TXD4 TXD4

TXD4

TXD5

TXD5 TXD5

TXD5

C_AUX_I2CW_SDA#

IFP

C_AUX_I2CW_SCL

I2CY_SDA

I2CY_SDA I2CY_SCLI2CY_SCL

I2CY_SCLI2CY_SCL

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

NC FOR GK208

HPD_E

I2CZ_SDA

I2CZ_SDA I2CZ_SCL

I2CZ_SCL

TXC

TXC TXC

TXC

TXD0

TXD0 TXD0

TXD0

TXD1

TXD1 TXD1

TXD1

TXD2

TXD2 TXD2

TXD2

NC FOR GK208

HPD_F

11 OF 17

AG2 AG3

AG4

IFPC_L3#

AG5

IFPC_L3

AH4

IFPC_L2#

AH3

IFPC_L2

AJ2

IFPC_L1#

AJ3

IFPC_L1

AJ1

IFPC_L0#

AK1

IFPC_L0

P2

GPIO15

IFPE_AUX_I2CY_SDA#

IFPE_AUX_I2CY_SCL

IFPF_AUX_I2CZ_SDA#

IFPF_AUX_I2CZ_SCL

2

13 OF 17

DPDVI-SL/HDMIDVI-DL

IFPE_L3#

IFPE_L3

IFPE_L2#

IFPE_L2

IFPE_L1#

IFPE_L1

IFPE_L0#

IFPE_L0

GPIO18

IFPF_L3#

IFPF_L3

IFPF_L2#

IFPF_L2

IFPF_L1#

IFPF_L1

IFPF_L0#

IFPF_L0

GPIO19

2

1

AB4 AB3

AC5 AC4

AC3 AC2

AC1 AD1

AD3 AD2

R1

AF2 AF3

AF1 AG1

AD5 AD4

AF5 AF4

AE4 AE3

P3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

GPU Memory(2/5)

74 101Friday, June 28, 2013

1

X02

5

SID = VIDEO

S

FBA

_D[0..31][78]

D D

FBA_D[32..63][79]

C C

FBA_DQM[0..3][78]

FBA_DQM[4..7][79]

FBA_EDC[0..3][78]

FBA_EDC[4..7][79]

B B

TP7503TP7503

A A

FBA

_D0

FBA

_D1 _D2

FBA FBA

_D3

FBA

_D4

FBA

_D5

FBA

_D6

FBA

_D7 _D8

FBA FBA

_D9 _D10

FBA FBA

_D11

FBA

_D12 _D13

FBA FBA

_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

1

5

AM29 AM31

AM30

AM33

AM32

AM34

AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28

AK29

AK28

AN29

AN31 AN32 AP30 AP32

AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33

AD31

AF34

AE31 AK30 AN33 AF33

AF30 AK31

AF32

L28

M29

L29 M28 N31 P29 R29 P28

J28 H29

J29 H28 G29 E31 E32

F30 C34 D32 B33 C33

F33

F32 H33 H32 P34 P32 P31 P33

L31

L34

L32

L33

AJ29

AJ30

AL31

P30

F31

F34 M32

AL29

M31 G31 E33 M33

M30 H30 E34 M34

H26

1B

GPU

2/17 FBA

FBA

_D0

FBA

_D1

FBA

_D2

FBA

_D3

FBA

_D4 _D5

FBA FBA

_D6

FBA

_D7 _D8

FBA FBA

_D9 _D10

FBA FBA

_D11

FBA

_D12 _D13

FBA FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

THE FBA_WCKBxx

THE FBA_WCKBxx PINS ARE USED

PINS ARE USED ONLY ON GK107

ONLY ON GK107 THEY ARE NC

THEY ARE NC FOR GK208/GF108

FOR GK208/GF108 /GF117

/GF117

FB_VREF

N14P-GS-A1-G P

71.0N14P.00U

OPS

FBA_CMD14 FBA_CMD30

FBA_CMD29 FBA_CMD13

NC

NC NC

NC

GF117/GK208

GF117/GK208 GK107/GF108

GK107/GF108

1D35V_VGA_S0 1D35V_VGA_S0

OPS

1 2

OPS

1 2

R7516

R7520

10KR2J-3-GP

FB_

DLL_AVDD

FB_

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CMD_RFU0 FBA_CMD_RFU1

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0

FBA_CLK0#

FBA_CLK1

FBA_CLK1#

FBA_WCK1 FBA_WCK1# FBA_WCK23

FBA_WCK23#

FBA_WCK45

FBA_WCK45#

FBA_WCK67

FBA_WCK67#

FBA_WCKB1 FBA_WCKB1# FBA_WCKB23

FBA_WCKB23#

FBA_WCKB45

FBA_WCKB45#

FBA_WCKB67

FBA_WCKB67#

FBA_PLL_AVDD

R7524

10KR2J-3-GP

OPS

1 2

R7521

OPS

1 2

10KR2J-3-GP

2 OF 17

CLAMP

E1

K27

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31

R32 AC32

R28 AC28

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

U27

C75

4

0618

A00

0R0402-PAD-2- GP

06

R75

1 2

FB_

CLAM

R75

18 10KR2J-3-GP

1 2

OPS

FBA

_PLL_AVDD

09

X7R

12

Layout note:FBA_PLL_AVDD=16mil

OPS

ce close to Ball

Pla

SCD1U10V2KX-5GP

0102 remove L7502 change K27 pin net name

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0P FBA_CLK0N FBA_CLK1P FBA_CLK1N

FBA_WCK 01 FBA_WCK 01# FBA_WCK 23 FBA_WCK 23# FBA_WCK 45 FBA_WCK 45# FBA_WCK 67 FBA_WCK 67#

FBA_CMD0 [78] FBA_CMD1 [78] FBA_CMD2 [78] FBA_CMD3 [78] FBA_CMD4 [78] FBA_CMD5 [78] FBA_CMD6 [78] FBA_CMD7 [78] FBA_CMD8 [78] FBA_CMD9 [78] FBA_CMD10 [78] FBA_CMD11 [78] FBA_CMD12 [78] FBA_CMD13 [78] FBA_CMD14 [78] FBA_CMD15 [78] FBA_CMD16 [79] FBA_CMD17 [79] FBA_CMD18 [79] FBA_CMD19 [79] FBA_CMD20 [79] FBA_CMD21 [79] FBA_CMD22 [79] FBA_CMD23 [79] FBA_CMD24 [79] FBA_CMD25 [79] FBA_CMD26 [79] FBA_CMD27 [79] FBA_CMD28 [79] FBA_CMD29 [79] FBA_CMD30 [79] FBA_CMD31 [79]

DY

1 2

R7501 60D4R2F- GP

DY

1 2

R7503 60D4R2F- GP

FBA_CLK0P [78] FBA_CLK0N [78] FBA_CLK1P [79] FBA_CLK1N [79]

FBA_WCK 01 [78] FBA_WCK 01# [78] FBA_WCK 23 [78] FBA_WCK 23# [78] FBA_WCK 45 [79] FBA_WCK 45# [79] FBA_WCK 67 [79] FBA_WCK 67# [79]

DA-05691-001_V05 P7

FBA_PLL_AVDD

12

OPS

C7505

C7506

SC10U6D3V3MX-GP

SCD1U10V2KX-5GP

Place under GPU near

4

3

3 OF 17

OPS

1 2

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_DEBUG0 FBB_DEBUG1

FBB_CLK0#

FBB_CLK1#

FBB_WCK1 FBB_WCK1# FBB_WCK23

FBB_WCK23#

FBB_WCK45

FBB_WCK45#

FBB_WCK67

FBB_WCK67#

FBB_WCKB1 FBB_WCKB1# FBB_WCKB23

FBB_WCKB23#

FBB_WCKB45

FBB_WCKB45#

FBB_WCKB67

FBB_WCKB67#

FBB_PLL_AVDD

GK107GF108

R7525

10KR2J-3-GP

1 2

R7523

10KR2J-3-GP

3 OF 17

FBB_CLK0

FBB_CLK1

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17

C12 C20

G14 G20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_DEBUG0 FBB_DEBUG1

FBB_CLK0P FBB_CLK0N FBB_CLK1P FBB_CLK1N

FBB_WCK 01 FBB_WCK 01# FBB_WCK 23 FBB_WCK 23# FBB_WCK 45 FBB_WCK 45# FBB_WCK 67 FBB_WCK 67#

C7510

1C

GPU

7 FBB

3/1

EC_

FB_CLAMP [24,76,83]

1D35V_VGA_S0 1D35V_VGA_S0

1D05V_VGA_S0

L7501

MHC1608S300QBP- GP

1 2

OPS

68.00335.051

12

0102 remove L7503 change C7506 to 0603 package

FBB

_D[0..31][80]

FBB_D[32..63][81]

FBB_DQM[0..3][80]

FBB_DQM[4..7][81]

FBB_EDC[0..3][80]

FBB_EDC[4..7][81]

30ohm@100MHz ESR=0.2

FBB

_D0

FBB

_D1 _D2

FBB FBB

_D3

FBB

_D4

FBB

_D5

FBB

_D6

FBB

_D7 _D8

FBB FBB

_D9 _D10

FBB FBB

_D11

FBB

_D12 _D13

FBB FBB

_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_EDC0 FBB_EDC1 FBB_EDC2 FBB_EDC3 FBB_EDC4 FBB_EDC5 FBB_EDC6 FBB_EDC7

3/1

ALL

PINS NC FOR GF117/GK208

G9

FBB

_D0

E9

FBB

_D1

G8

FBB

_D2

F9

FBB

_D3

F11

FBB

_D4

G11

_D5

FBB

F12

FBB

_D6

G12

FBB

_D7

G6

_D8

FBB

F5

FBB

_D9

E6

_D10

FBB

F6

FBB

_D11

F4

FBB

_D12

G4

_D13

FBB

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

THE FBB_WCKBxx

THE FBB_WCKBxx PINS ARE USED

PINS ARE USED ONLY ON GK107

ONLY ON GK107 THEY ARE NC

THEY ARE NC FOR GF108

FOR GF108

NC

N14P-GS-A1-G P

71.0N14P.00U

OPS

FBB_CMD14 FBB_CMD30

FBB_CMD29 FBB_CMD13

3

NC

R7517

10KR2J-3-GP

OPS

1 2

R7522

OPS

1 2

10KR2J-3-GP

OPS

SCD1U10V2KX-5GP

X7R

12

FBA_PLL_AVDDFB_VREF

2

FBB_CMD0 [80] FBB_CMD1 [80] FBB_CMD2 [80] FBB_CMD3 [80] FBB_CMD4 [80] FBB_CMD5 [80] FBB_CMD6 [80] FBB_CMD7 [80] FBB_CMD8 [80] FBB_CMD9 [80] FBB_CMD10 [80] FBB_CMD11 [80] FBB_CMD12 [80] FBB_CMD13 [80] FBB_CMD14 [80] FBB_CMD15 [80] FBB_CMD16 [81] FBB_CMD17 [81] FBB_CMD18 [81] FBB_CMD19 [81] FBB_CMD20 [81] FBB_CMD21 [81] FBB_CMD22 [81] FBB_CMD23 [81] FBB_CMD24 [81] FBB_CMD25 [81] FBB_CMD26 [81] FBB_CMD27 [81] FBB_CMD28 [81] FBB_CMD29 [81] FBB_CMD30 [81] FBB_CMD31 [81]

DY

1 2

R7502 60D4R2F- GP

DY

1 2

R7504 60D4R2F- GP

FBB_CLK0P [80 ] FBB_CLK0N [80] FBB_CLK1P [81 ] FBB_CLK1N [81]

FBB_WCK 01 [80] FBB_WCK 01# [80] FBB_WCK 23 [80] FBB_WCK 23# [80] FBB_WCK 45 [81] FBB_WCK 45# [81] FBB_WCK 67 [81] FBB_WCK 67# [81]

2

1D35V_VGA_S0

12

C7502

C7501

OPS

SC1U6D3V2KX-GP

1D35V_VGA_S0

12

C7503

C7504

OPS

SC1U6D3V2KX-GP

1D35V_VGA_S0

OPS

12

C7525

OPS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

12

C7526

OPS

SCD1U10V2KX-5GP

TP7501TP7501

TP7502TP7502

R7505

OPS

40D2R2F-GP

12

R7507

OPS

1 2

42D2R2F-GP

1.35V +/- 3%

4.88A

12

C7507

OPS

SC1U6D3V2KX-GP

12

C7511

OPS

DY

SCD1U10V2KX-5GP

1

4 OF 17

1D

GPU

14/

17 FBVDDQ

AA27

FBV

DDQ_1

AA30

FBV

DDQ_2

AB27

FBV

DDQ_3

AB33

FBV

DDQ_4

AC27

FBV

DDQ_5

AD27

FBV

DDQ_6

AE27

DDQ_7

FBV

AF27

FBV

DDQ_8

AG27

FBV

DDQ_9

B13

DDQ_10

FBV

B16

FBV

DDQ_11

B19

DDQ_12

FBV

E13

FBV

DDQ_13

E16

FBV

DDQ_14

E19

DDQ_15

FBV

H10

FBVDDQ_16

H11

FBVDDQ_17

H12

FBVDDQ_18

H13

FBVDDQ_19

H14

FBVDDQ_20

H15

FBVDDQ_21

H16

FBVDDQ_22

H18

FBVDDQ_23

H19

FBVDDQ_24

H20

FBVDDQ_25

H21

FBVDDQ_26

H22

FBVDDQ_27

H23

FBVDDQ_28

H24

FBVDDQ_29

H8

FBVDDQ_30

H9

FBVDDQ_31

L27

FBVDDQ_32

M27

FBVDDQ_33

N27

FBVDDQ_34

P27

FBVDDQ_35

R27

FBVDDQ_36

T27

FBVDDQ_37

T30

FBVDDQ_38

T33

FBVDDQ_39

V27

FBVDDQ_40

W27

FBVDDQ_41

W30

FBVDDQ_42

W33

FBVDDQ_43

Y27

FBVDDQ_SEN SE

1

FB_GND_SEN SE

1

FB_CAL_PD_VD DQ

12

FB_CAL_PU_GN D

FB_CAL_TERM _GND

R7508

60D4R2F-GP

12

C7508

C7524

SC1U6D3V2KX-GP

DY

H27

H25

12

C7522

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

DY

FBVDDQ_44

F1

FB_VDDQ_SENSE

F2

FB_GND_SENSE

J27

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

N14P-GS-A1-G P

71.0N14P.00U

OPS

GPU FBVDDQ Decoupling

PLACE CLOSE TO GPU BALLS

12

C7513

12

SC4D7U6D3V3KX-GP

DY

C7514

C7520

C7517

SC4D7U6D3V3KX-GP

SC10U6D3V3MX-GP

OPS

DY

12

SC10U6D3V3MX-GP

DY

PLACE CLOSE TO GPU BALLS

C7512

12

SC1U6D3V2KX-GP

OPS

C7515

C7516

C7523

C7527

SC1U6D3V2KX-GP

DY

OPS

DY

SC4D7U6D3V3KX-GP

Title

GPU_DP/LVDS/CRT/GPIO(3/5)

Size Document Num ber Rev

A2

Hadley 15"

Date: Sheet of

Hadley 15"

12

C7518

C7519

SC10U6D3V3MX-GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

1

C7521

C7529

75 101Friday, June 28, 2013

1D3

SC10U6D3V3MX-GP

DY

SC10U6D3V3MX-GP

DY

5V_VGA_S0

12

C7528

12

C7530

12

SC10U6D3V3MX-GP

DY

12

SC10U6D3V3MX-GP

DY

X02

5

D = VIDEO

SSI

4 OF 17

1

GPU

1N

4/1

7 DACA

GF108/GK107

AG10

DAC

AP9

DAC

AP8

DAC

D D

N14P-GS-A1-GP

71.0N14P.00U

OPS

GK2

A_VDD

A_VREF

A_RSET

7

GF11

08

N

C

TSEN_VREF

NC

0102 remove 0R

3D3V_VGA_S0

SML1_DATA[18,24,26]

R7607

TP7602TP7602 TP7605TP7605 TP7601TP7601

SML1_CLK[18,24,26]

TP7603TP7603

TP7604TP7604

1 1 1

STRAP_REF0_GND_N9

12

OPS

STRAP0 STRAP1

STRAP3 STRAP4

1

OPS

RN7602

SRN10KJ-5-GP

P2800_VGA_DXN

P2800_VGA_DXP

N12P_JTAG_TCK N12P_JTAG_TMS N12P_JTAG_TDI N12P_JTAG_TDO N12P_JTAG_TRST

4

1

2 3

GPU1P

12/17 MISC2

J2

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

GK107/GF117

J1

MULTI_STRAP_REF

N14P-GS-A1-GP

71.0N14P.00U

OPS

5

GK208

C C

B B

A A

40K2R2F-GP

GF1

17

N

C

NC

NC NC

NC

N

C

N

Q7601

3 4

2

1

OPS

K4

K3

AM10

AP11

AM11

AP12 AN11

NC

NC NC

NC

GF108

CEC IS NC FOR

CEC IS NC FOR GK107/GK208/GF117

GK107/GK208/GF117

1

GF108/GK107

GK208

I2C

A_SCL

I2C

A_SDA

DAC

A_HSYNC A_VSYNC

DAC

A_RED

DAC

A_GREEN

DAC

A_BLUE

5

2N7002KDW-GP

6

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

GPU1Q

10/19 MISC1

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#

GPIO16

GPIO16 GPIO20

GPIO20

GPIO8

GK208 GF117

N14P-GS-A1-GP

71.0N14P.00U

OPS

ROM_CS#

ROM_SCLK

BUFRST#

16 OF 17

ROM_SI

ROM_SO

R4 R5

AM9 AN9

AK9

AL10

AL9

NC

CEC

I2C

A_SCL

I2C

A_SDA

SMBD_THERM_NV

SMBC_THERM_NV

NC

NC NC

NC

GF117

GK208

GK208 OVERT

OVERT

GPIO16

NCNC

NCNC NC

NC

GK107

ROM_CS#

H6

ROM_SI

H5

ROM_SO

H7

ROM_SCLK

H4

BUFRST#

L2

L3

RN7

603

1

4

OPS

SRN2K2J-1-GP

23

3D3V_VGA_S0

4

RN7601

RN7601 SRN4K7J-8-GP

SRN4K7J-8-GP

OPS

1

2 3

17 OF 17

SMBC_THERM_NV

T4

I2CS_SCL

SMBD_THERM_NV

T3

I2CS_SDA

I2CC_SCL

R2

I2CC_SCL

I2CC_SDA

R3

I2CC_SDA

I2CB_SCL

R7

I2CB_SCL

I2CB_SDA

R6

I2CB_SDA

GK107/GF108

GK208

FB_CLAMP_MON

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

FB_CLAMP_TGL_REQ#

M7

GPIO6

N8

GPIO7

GPIO8_OVERT#

M1

GPIO8

GPIO9_ALERT

M2

GPIO9

GPIO10_FBVREF

L1

GPIO10

M5

GPIO11

PWR_LEVEL

N3

GPIO12

M4

GPIO13

R8

GPIO16

P4

GPIO20

P1

GPIO21

GF108

DA-05691-001_V05 P6 NC : N13P-GS

3D3V_VGA_S0

R7628

OPS

10KR2J-3-GP

DA-05691-001_V05 P15 GPIO20/21 NC : for ALL

R7626

R7626 10KR2J-3-GP

10KR2J-3-GP

DY

1 2

12

3D3

V_VGA_S0

180ohm@100MHz DCR=0.3 ohm Max current = 300mA

23

SRN2K2J-1-GP

1

4

RN7604

OPS

RN7604

OPS

RN7605

1

4

OPS

SRN2K2J-1-GP

23

4

5V_VGA_S0

1D0

MHC1608S300QBP-GP

1 2

6

8

MCB1608S181FBP-GP

1 2

8.00909.261

6

3D3V_VGA_S0

GPIO10_FBVREF [78,79,80,81]

VGA_CORE_VID [82 ]

VGA_CORE_PSI [82]

EA40-HW SC

EC_FB_CLAMP[24,75,83]

4

0ohm@100MHz

3 DCR=0.04 ohm Max current = 3000mA

L76

01

OPS

.00335.051

05

C76

SCD1U10V2KX-5GP

02

L76

OPS

C76

FB_CLAMP_MON

12

OPS

01

C76

12

OPS

SCD1U10V2KX-5GP

GPIO9_ALERT GPIO8_OVERT#

GPIO10_FBVREF

3D3V_VGA_S0

12

OPS

3D3V_VGA_S0

12

C76

06

SC2D2U6D3V2MX-GP

OPS

04

03

C76

12

OPS

SC4D7U6D3V3KX-GP

2 3

OPS

1

OPS

R7605

R7605 10KR2J-3-GP

10KR2J-3-GP

DY

83.00400.C1F

2ND = 83.27101.01F

3RD = 83.01426.01F

OPS

83.00400.C1F

2ND = 83.27101.01F

3RD = 83.01426.01F

R7647

R7647 10KR2J-L-GP

10KR2J-L-GP

OPS_GC6

1 2

N14P-GT

52m

112mA

02

12

OPS

SCD1U10V2KX-5GP

RN7606

4

SRN10KJ-5-GP

12

R7610

R7610 100KR2J-1-GP

100KR2J-1-GP

D7601

KA

1SS400GPT-GP

D7602

KA

1SS400GPT-GP

Q7603

Q7603 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.F3F

1

2

3 4

OPS_GC6

A

3D3V_VGA_S0

AC_PRESENT [17,24]

OVER_CURRENT_P8# [24]

6

5

GPU SP_

VID

EO_CLK_XTAL_SS

12

R7601

OPS

10KR2J-3-GP

SC15P50V2JN-2-GP

3D3V_S0

FB_CLAMP_MON_S

3

NV

request to need to be keeped

GPU

1O

11/

17 XTAL_PLL

_PLL_VDD

PLLVDD

C7607

R7650

R7650 10KR2J-L-GP

10KR2J-L-GP

OPS_GC6

1 2

17 XTAL_PLL

AD8

PLL

VDD

AE8

SP_

PLLVDD

AD7

VID

_PLLVDD

H1

XTA

L_SSIN

H3

XTAL_IN

N14P-GS-A1-GP

71.0N14P.00U

27MHZ_IN 27MHZ_OUT

12

OPS

3D3V_VGA_S0

GPIO9_ALERT

GPIO8_OVERT#

FB_CLAMP_TGL_REQ#STRAP2

3

GK208

R7603

1MR2J-1-GP

1 2

DY

X7601

2 3

OPS

XTAL-27MHZ-85-GP-U

82.30034.641

2ND = 82.30034.651

3RD = 82.30034.681

G

S

VGA_RST#_R

OPS_GC6

1 2

NC

GF117GF108/GK107

XTA

OPS

20PF 5% 50V +/-0.25PF 0402

41

27MHZ_OUT_R

Q7604

OPS

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00 0618

1 2

R7604

0R0402-PAD-2-GP

Q7602

G

OPS

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

R7649

R7649 10KR2J-L-GP

10KR2J-L-GP

G

S

Q7606

OPS_GC6

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

1

5 OF 17

J4

L_OUTBUFF

H2

XTAL_OUT

A00 0618

R7629

R7629 0R0402-PAD-2-GP

0R0402-PAD-2-GP

1 2

12

C7608

C7608 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

OPS

VIDEO_THERM_OVERT# [82]

VGA_RST# [73]

PURE_HW_SHUTDOWN# [24 ,26,36]

D

3D3V_S03D3V_VGA_ S03D3V_VGA_S0

N12

P_XTAL_OUTBUFF

R7648

R7648 10KR2J-L-GP

10KR2J-L-GP

OPS_GC6

1 2

12

R7602

R7602 10KR2J-3-GP

10KR2J-3-GP

OPS

EC_FB_CLAMP_TGL_REQ# [24]

2

3D3V_VGA_S0

R7608

4K99R2F-L-GP

ROM_SO

3D3V_VGA_S0 3D3V_VGA_S0 3D3V_VGA_S0

R7613

10KR2J-3-GP

STRAP4

2

OPS

DY

OPS

12

10KR2J-3-GP

ROM_SI

R7621

R7621 15KR2F-GP

15KR2F-GP

10KR2J-3-GP

R7609

R7609 45K3R2F-L-GP

45K3R2F-L-GP

R7611

R7614

STRAP3

3D3V_VGA_S0

12

DY

12

R7618

R7618 45K3R2F-L-GP

45K3R2F-L-GP

Samsung

12

DY

12

R7625

R7625 4K99R2F-L-GP

4K99R2F-L-GP

OPS

3D3V_VGA_S0

12

R7612

10KR2J-3-GP

DY

ROM_SCLK

12

R7617

R7617 15KR2F-GP

15KR2F-GP

OPS

12

R7615

10KR2J-3-GP

DY

STRAP2

12

R7619

R7619 24K9R2F-L-GP

24K9R2F-L-GP

OPS

Title

Size Document Number Rev

Custom

Date: Sheet of

1

3D3V_VGA_S0

12

R7620

45K3R2F-L-GP

DY

STRAP1 STRAP0

12

R7627

R7627 4K99R2F-L-GP

4K99R2F-L-GP

OPS

1

3D3V_VGA_S0

12

R7616

45K3R2F-L-GP

OPS

12

R7622

R7622 15KR2F-GP

15KR2F-GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

X02

76 101Friday, June 28, 2013

X02

5

SID = VIDEO

S

Under GPU

C77

09

OPS

U6D3V2KX-GP

SC1

OPS

09

OPS

D7U6D3V3KX-GP

SC4

C7722

12

OPS

D7U6D3V3KX-GP

SC4

C7718

12

OPS

U6D3V2KX-GP

SC1

D D

C7725

SC1

0U6D3V3MX-GP

C7715

C7716

12

OPS

C C

U6D3V2KX-GP

SC1

C77

12

07

C77

SC1

OPS

0U6D3V3MX-GP

C7723

C7724

12

SC10U6D3V3MX-GP

OPS

D7U6D3V3KX-GP

SC4

C7714

C7717

12

OPS

U6D3V2KX-GP

SC1

08

SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

12

OPS

12

OPS

12

OPS

C77

SC10U6D3V3MX-GP

C7721

C7713

OPS

06

OPS

SC4D7U6D3V3KX-GP

OPS

SC1U6D3V2KX-GP

N14

12

P-GT : 45A

C77

01

02

12

OPS

SC4D7U6D3V3KX-GP

C7719

C7720

12

OPS

SC4D7U6D3V3KX-GP

C7711

C7712

12

OPS

SC1U6D3V2KX-GP

OPS

SC4D7U6D3V3KX-GP

OPS

SC4D7U6D3V3KX-GP

OPS

SC1U6D3V2KX-GP

VGA

_CORE

12

NEAR TO GPU

12

C7703

C7705

SC10U6D3V3MX-GP

OPS

B B

12

OPS

12

UMA

R7701

0R3J-0-U-GP

12

C7710

SC10U6D3V3MX-GP

4

GPU

AA12

VDD

AA14

VDD

AA16

VDD

AA19

VDD

AA21

VDD

AA23

VDD

AB13

VDD

AB15

VDD

AB17

VDD

AB18

VDD_10

AB20

VDD_11

AB22

VDD_12

AC12

VDD_13

AC14

VDD_14

AC16

VDD_15

AC19

VDD_16

AC21

VDD_17

AC23

VDD_18

M12

VDD_19

M14

VDD_20

M16

VDD_21

M19

VDD_22

M21

VDD_23

M23

VDD_24

N13

VDD_25

N15

VDD_26

N17

VDD_27

N18

VDD_28

N20

VDD_29

N22

VDD_30

P12

VDD_31

P14

VDD_32

P16

VDD_33

P19

VDD_34

P21

VDD_35

P23

VDD_36

R13

VDD_37

R15

VDD_38

R17

VDD_39

R18

VDD_40

R20

VDD_41

R22

VDD_42

T12

VDD_43

T14

VDD_44

T16

VDD_45

T19

VDD_46

T21

VDD_47

T23

VDD_48

U13

VDD_49

U15

VDD_50

U17

VDD_51

U18

VDD_52

U20

VDD_53

U22

VDD_54

V13

VDD_55

V15

VDD_56

V17

VDD_57

V18

VDD_58

V20

VDD_59

V22

VDD_60

W12

VDD_61

W14

VDD_62

W16

VDD_63

W19

VDD_64

W21

VDD_65

W23

VDD_66

Y13

VDD_67

Y15

VDD_68

Y17

VDD_69

Y18

VDD_70

Y20

VDD_71

Y22

VDD_72

N14P-GS-A1-GP

71.0N14P.00U

OPS

3

6 OF 17

15/

17 GND_1/2

6 OF 17

GND GND GND GND GND GND GND GND GND GND GND GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140

GPU

AM25

_71

AN1

_72

AN10

_73

AN13

_74

AN16

_75

AN19

_76

AN22

_77

AN25

_78

AN30

_79

AN34

_80

AN4

_81

AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16

GPU

N19

N2 N21 N23 N28 N30 N32 N33

N5

N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23

T13 T15 T17 T18

T2

T20 T22

AG11

N14P-GS-A1-GP

71.0N14P.00U

OPS

GPU

1F

8 OF 17

1H

13/

17 NVVDD

_1 _2 _3 _4 _5 _6 _7 _8 _9

A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19

AB2

AB21

A33 AB23 AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AA15 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AJ7

AK10

AK7

AL12 AL14 AL15 AL17 AL18

AL2

AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AL5

AM13 AM16 AM19 AM22

N14P-GS-A1-GP

71.0N14P.00U

OPS

1F

GND GND GND GND GND GND GND GND GND GND GND GND_2 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_3 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_4 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70

_1 _5 _6 _7 _8 _9 _10 _11 _12 _13 _14

1G

16/

17 GND_2/2

GND

_141 _142

GND

_143

GND GND

_144

GND

_145 _146

GND GND

_147

GND

_148 _149

GND GND

_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169

GND_F

Optional CMD GNDs (2)

NC for 4-Lyr cards

2

7 OF 17

GND GND GND GND GND GND GND GND GND GND GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_OPT_1 GND_OPT_2

_170 _171 _172 _173 _174 _175 _176 _177 _178 _179

GND_H

T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23

AH11

C16 W32

1I

GPU

9/1

7 XVDD

CONFIGURABLE

CONFIGURABLE POWER

POWER CHANNELS

CHANNELS

N14P-GS-A1-GP

71.0N14P.00U

OPS

9 OF 17

XVD XVD XVD XVD XVD XVD XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30

XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38

1

U1

D_1

U2

D_2

U3

D_3

U4

D_4

U5

D_5

U6

D_6

U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

C7729

OPS

SCD1U10V2KX-5GP

3.3V +/- 5% 85mA

X7R

12

C7727

OPS

SCD1U10V2KX-5GP

3D3V_VGA_S0

X7R

C7728

OPS

SC1U6D3V2KX-GP

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

3

2

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

GPU_POWER(4/5)

77 101Friday, June 28, 2013

1

X02

12

5 OF 17

GK107

3V3MISC

3V3MISC 3V3MISC

3V3MISC

DO NOT

CONNECT

THESE

PINS

5

5 OF 17

GK208

GK208 GF117

GF117

3V3MISC_1 3V3MISC_2

VDD33_1 VDD33_2

DA-05691-001_V05 P20 3V3MISC : N13P-GS

J8 K8

L8 M8

12

C7704

OPS

SC1U6D3V2KX-GP

0.1U Under GPU

4.7U NEAR TO GPU

1U NEAR TO GPU

4

GPU1E

17/17 NC/VDD33

AJ28

NC#AJ28

C15

NC#C15

D19

NC#D19

D20

NC#D20

D23

NC#D23

D26

NC#D26

H31

NC#H31

V32

NC#V32

AC6

DNU#AC6

AJ4

DNU#AJ4

AJ5

DNU#AJ5

AL11

DNU#AL11

T8

DNU#T8

N14P-GS-A1-GP

71.0N14P.00U

A A

71.0N14P.00U

OPS

SID = VIDEO

S

5

4

3

2

1

1D3

1D35V_V GA_S0

FBA_VREF C0

FBA_VREF D_L

5V_VGA_ S0

C

5

C

10

D

11

1

G

4

G

11

G

14 L

1 4

L

11 14

L

P11

R5

R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2

G13

H3

H12

K3

K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10 U10

1D3

5V_VGA_ S0

VRA

C

5

C

10 11

D

1

G G

D D

1D35V_V GA_S0

C C

FBA_VREF C0

FBA_VREF D_L

SC820P50V2KX-1GP

12

OPS

4

G

11

G

14

1

L L

4

11

L L14 P11

R5

R10

B1

B3 B12 B14

D1

D3 D12 D14

E5

E10

F1

F3 F12 F14

G2

G13

H3

H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10

U10

C78

26

H5GQ2H24 AFR-T2C-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VREFD VREFD

1

OF 2

M1A

OPS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

B

5

VSS

B

10

VSS

10

D

VSS

5

G

VSS

G

10

VSS

H

1

VSS

H

14

VSS

1

K

VSS

K

14

VSS

5

L

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

VPP1 VPP2

TP7801 TPAD1 4-OP-GPTP7801 TPAD14-OP-G P

1

TP7802 TPAD1 4-OP-GPTP7802 TPAD14-OP-G P

1

Frame Buffer Patition A-Lower Half

1D3

5V_VGA_ S0

12

R78

06

OPS

R7807

12

FBA_VREF _FET_L

OPS

FBVREF%

70%Termination

R78 549R2F-GP

549R2F-GP

OPS

R7804

931R2F-1-GP

12

OPS

D

G

Voltage

0.749V50%

1.0617V

05

FBA_VREF D_L

R7809

R7803

1K33R2F-GP

931R2F-1-GP

12

OPS

Q7801

Q7801 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

S

Description

GPU_GPIO10

High

Low

FBA_VREF C0

SC820P50V2KX-1GP

12

OPS

GPIO10_ FBVREF[76,79,80,8 1]

FBVREF Termination

Type

Un-termination

549R2F-GP

C7803

R78

1K33R2F-GP

12

OPS

C7802

SC820P50V2KX-1GP

VRA

M2A

VDD

OPS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VPP/NC#A5

VPP/NC#U5 VREFD VREFD

H5GQ2H24 AFR-T2C-GP

1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

OF 2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B

5

B

10

D

10 5

G

10

G H

1

H

14

K

1 14

K L

5 10

L P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC3

1

TP_VPPNC4

1

C7827

ST330U2VDM-4-GP

12

DY

OPS

C7813

SC10U6D3V3MX-GP

OPS

Place close VDD ball

OPS

TP7803 TPAD1 4-OP-GPTP7803 TPAD14-OP-G P TP7804 TPAD1 4-OP-GPTP7804 TPAD14-OP-G P

12

Place close VDD ball

1D3

5V_VGA_ S0

OPS

C7805

C7804

SC1U6D3V3KX-2GP

SC10U6D3V3MX-GP

12

OPS

Place close VDD ball

1D35V_V GA_S0

OPS

C7820

C7821

SCD1U10V2KX-4GP

12

OPS

Place close VDDQ ball

1D35V_V GA_S0

C7814

SC1U6D3V3KX-2GP

OPS

12

OPS

12

OPS

C7807

C7809

C7806

SC1U6D3V3KX-2GP

OPS

C7822

SCD1U10V2KX-4GP

C7810

SC1U6D3V3KX-2GP

OPS

C7809

SC1U6D3V3KX-2GP

12

OPS

C7823

C7824

SCD1U10V2KX-4GP

12

DY

C7811

C7812

SC1U6D3V3KX-2GP

OPS

12

Place close VDDQ ball

1D35V_V GA_S0 1D35V_V GA_S0

C7817

C7815

C7808

SCD1U10V2KX-4GP

OPS

12

C7817

C7816

SCD1U10V2KX-4GP

OPS

12

OPS

12

C7825

SCD1U10V2KX-4GP

12

C7819

C7818

SCD1U10V2KX-4GP

12

OPS

R7810

1KR2J-1-GP

FBA_CLK0 P FBA_CLK0 N

OPS

FBA_CMD10[75] FBA_CMD7[75] FBA_CMD6[75] FBA_CMD11[75] FBA_CMD9[75]

FBA_CMD3[75] FBA_CMD1[75] FBA_CMD2[75] FBA_CMD4[75]

FBA_CMD8[75] FBA_CMD15[75] FBA_CMD5[75] FBA_CMD12[75] FBA_CMD0[75]

FBA_CMD14[75]

FBA_CMD13[75]

1D35V_V GA_S0

R7813

121R2F-GP

12

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3

R7812 1KR2J-1-G P

FBA_EDC0 FBA_EDC1 FBA_EDC2

B B

Normal(MF=0)

VRAM1B

FBA_CMD6[75] FBA_CMD11[75] FBA_CMD10[75] FBA_CMD7[75] FBA_CMD9[75]

FBA_CMD2[75] FBA_CMD4[75] FBA_CMD3[75] FBA_CMD1[75]

FBA_CMD8[75] FBA_CMD12[75] FBA_CMD0[75] FBA_CMD15[75] FBA_CMD5[75]

FBA_CLK0 P[75] FBA_CLK0 N[75] FBA_CMD14[75]

OPS

FBA_CMD13[75]

R78

121R2F-GP

12

08

OPS

A A

FBA_CMD6 FBA_CMD11 FBA_CMD10 FBA_CMD7 FBA_CMD9

FBA_CMD2 FBA_CMD4 FBA_CMD3 FBA_CMD1

FBA_CMD8 FBA_CMD12 FBA_CMD0 FBA_CMD15 FBA_CMD5

FBA_CLK0 P FBA_CLK0 N FBA_CMD14

FBA_DQM0

FBA_DQM2

FBA_CMD13

FBA_SEN0 FBA_ZQ0 FBA_MF1

R78

1KR2J-1-GP

FBA_WC K01

11

FBA_WC K01#

FBA_WC K23 FBA_WC K23#

1 2

5

VRAM1B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBA_D0

A4

FBA_D1

A2

FBA_D2

B4

FBA_D3

B2

FBA_D4

E4

FBA_D5

E2

FBA_D6

F4

FBA_D7

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D16

U11

FBA_D17

U13

FBA_D18

T11

FBA_D19

T13

FBA_D20

N11

FBA_D21

N13

FBA_D22

M11

FBA_D23

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBA_EDC0

C2 C13

FBA_EDC2

R13 R2

FBA_EDC3

FBA_D[0.. 31] [75]

4

R7802

40D2R2F-G P

OPS

C7801

SCD01U16 V2KX-3GP

12

R7801

R7801 40D2R2F-G P

40D2R2F-G P

OPS

FBA_CLK0 _MIDPT

OPS

1 2

OPS

FBA_W CK23[75] FBA_W CK23#[ 75] FBA_W CK01[75] FBA_W CK01#[ 75]

1 2

3

OPS

12

FBA_DQM[0 ..3] [75]FBA_EDC[0 ..3][75]

FBA_CMD10 FBA_CMD7 FBA_CMD6 FBA_CMD11 FBA_CMD9

FBA_CMD3 FBA_CMD1 FBA_CMD2 FBA_CMD4

FBA_CMD8 FBA_CMD15 FBA_CMD5 FBA_CMD12 FBA_CMD0

FBA_CMD14

FBA_DQM3

FBA_DQM1

FBA_CMD13

FBA_SEN0 FBA_ZQ1 FBA_MF2

FBA_W CK23 FBA_W CK23#

FBA_W CK01 FBA_W CK01#

Mirrored(MF=1)

VRAM2B

K4

A8/A7

OPS

A9/A1 A10/A0 A11/A6

J5

A12/RFU#J5/NC#J5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

J4

ABI# RAS# CS#

L3

CAS# WE#

CK CK#

J3

CKE#

DBI0# DBI1# DBI2# DBI3#

J2

RESET#

SEN ZQ

J1

MF

WCK01 WCK01#

WCK23 WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

H5 H4 K5

H11 K10 K11 H10

G3

G12

L12

J12 J11

D2 D13 P13

P2

J10 J13

D4

D5

P4

P5

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBA_D24

A4

FBA_D25

A2

FBA_D26

B4

FBA_D27

B2

FBA_D28

E4

FBA_D29

E2

FBA_D30

F4

FBA_D31

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D8

U11

FBA_D9

U13

FBA_D10

T11

FBA_D11

T13

FBA_D12

N11

FBA_D13

N13

FBA_D14

M11

FBA_D15

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBA_EDC3

C2 C13

FBA_EDC1

R13 R2

2

FBA_D[0.. 31] [75]

Title

Size Docum ent Number Rev

Size Docum ent Number Rev Custom

Custom

Date: Sheet of

Friday, June 28 , 2013

GPU-VRAM1,2 (1/4)

Hadley 15"

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

78 101

X02

5

S

SID = VIDEO

4

3

2

1

1D35V_V GA_S0

FBA_VREF C1

FBA_VREF D_H

1D3

5V_VGA_ S0

M4A

VRA

5

C

VDD

10

C

VDD

D

11

VDD

G

1

VDD

G

4

VDD

11

G

VDD

G

14

VDD

1

L

VDD

L4

VDD

L11

VDD

L14

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

H5GQ2H24 AFR-T2C-GP

OPS

1

OF 2

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

1D3

5V_VGA_ S0

5

B

VSS

10

B

VSS

D

10

VSS

G

5

VSS

G

10

VSS

1

H

VSS

H

14

VSS

1

K

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC7 TP_VPPNC8

TP7903 TPAD14 -OP-GPTP7903 TPA D14-OP-GP

1

TP7904 TPAD14 -OP-GPTP7904 TPA D14-OP-GP

1

C7907

SC10U6D3V3MX-GP

12

OPS

12

OPS

C7918

SC10U6D3V3MX-GP

12

OPS

Place close VDD ball

12

OPS

Place close VDD ball

C7905

12

OPS

C7905

C7904

SC1U6D3V3KX-2GP

12

OPS

C7913

C7914

SCD1U10V2KX-4GP

12

OPS

C7916

C7915

SC1U6D3V3KX-2GP

12

OPS

Place close VDDQ ball

C7921

SCD1U10V2KX-4GP

12

OPS

12

C7922

OPS

C7906

SC1U6D3V3KX-2GP

C7920

SCD1U10V2KX-4GP

OPS

C7917

SC1U6D3V3KX-2GP

12

C7924

SC1U6D3V3KX-2GP

12

OPS

1D35V_V GA_S0

Place close VDD ball

C7911

C7912

SCD1U10V2KX-4GP

12

OPS

1D35V_V GA_S0

Place close VDDQ ball

C7919

SC1U6D3V3KX-2GP

12

OPS

1D35V_V GA_S0 1D35V_V GA_S0

C7910

C7909

SCD1U10V2KX-4GP

12

OPS

C7926

SCD1U10V2KX-4GP

12

C7925

C7923

SCD1U10V2KX-4GP

12

DY

1D3

5V_VGA_ S0

VRA

5

C

10

C D

D D

1D35V_V GA_S0

C C

FBA_VREF C1

FBA_VREF D_H

12

OPS

11

G

1

G

4

11

G G

14

1

L

L4 L11 L14 P11

R5

R10

B1

B3 B12 B14

D1

D3

D12 D14

E5 E10

F1

F3 F12 F14

G2

G13

H3

H12

K3 K12

L2

L13

M1

M3

M12 M14

N5

N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10

C7908

SC820P50V2KX-1GP

U10

H5GQ2H24 AFR-T2C-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VREFD VREFD

1

OF 2

M3A

OPS

5

B

VSS

10

B

VSS

D

10

VSS

G

5

VSS

G

10

VSS

1

H

VSS

H

14

VSS

1

K

VSS

K14

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1

VSSQ

A3

VSSQ

A12

VSSQ

A14

VSSQ

C1

VSSQ

C3

VSSQ

C4

VSSQ

C11

VSSQ

C12

VSSQ

C14

VSSQ

E1

VSSQ

E3

VSSQ

E12

VSSQ

E14

VSSQ

F5

VSSQ

F10

VSSQ

H2

VSSQ

H13

VSSQ

K2

VSSQ

K13

VSSQ

M5

VSSQ

M10

VSSQ

N1

VSSQ

N3

VSSQ

N12

VSSQ

N14

VSSQ

R1

VSSQ

R3

VSSQ

R4

VSSQ

R11

VSSQ

R12

VSSQ

R14

VSSQ

U1

VSSQ

U3

VSSQ

U12

VSSQ

U14

VSSQ

A5

VPP/NC#A5

U5

VPP/NC#U5

TP_VPPNC5 TP_VPPNC6

FBA_EDC[4 ..7][75] FBA_DQM[4 ..7] [75]

TP7901 TPAD14 -OP-GPTP7901 TPA D14-OP-GP

1

TP7902 TPAD14 -OP-GPTP7902 TPA D14-OP-GP

1

FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

Frame Buffer Patition A-Upper Half

5V_VGA_ S0

1D3

12

R79

549R2F-GP

FBA_VREF C1

C7902

SC820P50V2KX-1GP

12

OPS

GPIO10_ FBVREF[76,78,80,8 1]

FBVREF Termination

Type

Un-termination

R79

OPS

1K33R2F-GP

12

03

R7904

931R2F-1-GP

12

OPS

FBA_VREF _FET_H

OPS

FBVREF%

70%Termination

R79

R79 549R2F-GP

549R2F-GP

OPS

R7902

931R2F-1-GP

12

OPS

D

G

Voltage

0.749V50%

1.0617V

07

FBA_VREF D_H

R7905

R7901

1K33R2F-GP

12

OPS

Q7901

Q7901 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

S

GPU_GPIO10

12

High

Low

C7903

SC820P50V2KX-1GP

FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

B B

FBA_CMD22[75] FBA_CMD27[75] FBA_CMD26[75] FBA_CMD23[75] FBA_CMD25[75]

FBA_CMD18[75] FBA_CMD20[75] FBA_CMD19[75] FBA_CMD17[75]

FBA_CMD24[75] FBA_CMD28[75] FBA_CMD16[75] FBA_CMD31[75] FBA_CMD21[75]

FBA_CLK1 P[75] FBA_CLK1 N[75] FBA_CMD30[75]

FBA_CMD29[75]

R79

121R2F-GP

12

OPS

12

OPS

1 2

A A

FBA_CMD22 FBA_CMD27 FBA_CMD26 FBA_CMD23 FBA_CMD25

FBA_CMD18 FBA_CMD20 FBA_CMD19 FBA_CMD17

FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21

FBA_CLK1 P FBA_CLK1 N FBA_CMD30

FBA_DQM4

FBA_DQM6

FBA_CMD29

FBA_SEN2 FBA_ZQ2 FBA_MF3

R79

1KR2J-1-GP

FBA_WC K45

11

FBA_WC K45#

FBA_WC K67 FBA_WC K67#

5

Normal(MF=0) Mirrored(MF=1)

VRAM3B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

VRAM4B

FBA_D32

A4

FBA_D33

A2

FBA_D34

B4

FBA_D35

B2

FBA_D36

E4

FBA_D37

E2

FBA_D38

F4

FBA_D39

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D48

U11

FBA_D49

U13

FBA_D50

T11

FBA_D51

T13

FBA_D52

N11

FBA_D53

N13

FBA_D54

M11

FBA_D55

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBA_EDC4

C2 C13

FBA_EDC6

R13 R2

FBA_D[32 ..63] [75]

4

R7906

40D2R2F-G P

OPS

C7901

SCD01U16 V2KX-3GP

12

FBA_CLK1 _MIDPT

OPS

1 2

OPS

FBA_W CK67[75] FBA_W CK67#[ 75] FBA_W CK45[75] FBA_W CK45#[ 75]

R7908

R7908 40D2R2F-G P

40D2R2F-G P

OPS

1D35V_V GA_S0

R7909

1KR2J-1-GP

OPS

1 2

FBA_CMD26[75] FBA_CMD23[75] FBA_CMD22[75] FBA_CMD27[75] FBA_CMD25[75]

FBA_CMD19[75] FBA_CMD17[75] FBA_CMD18[75] FBA_CMD20[75]

FBA_CMD24[75] FBA_CMD31[75] FBA_CMD21[75] FBA_CMD28[75] FBA_CMD16[75]

FBA_CMD30[75]

FBA_CMD29[75]

121R2F-GP

12

3

R7910 1K R2J-1-GP

R7910 1K R2J-1-GP R7913

R7913

OPS

12

FBA_CMD26 FBA_CMD23 FBA_CMD22 FBA_CMD27 FBA_CMD25

FBA_CMD19 FBA_CMD17 FBA_CMD18 FBA_CMD20

FBA_CMD24 FBA_CMD31 FBA_CMD21 FBA_CMD28 FBA_CMD16

FBA_CLK1 P FBA_CLK1 N FBA_CMD30

FBA_DQM7

FBA_DQM5

FBA_CMD29

FBA_SEN2 FBA_ZQ3 FBA_MF4

FBA_W CK67 FBA_W CK67#

FBA_W CK45 FBA_W CK45#

VRAM4B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBA_D56

A4

FBA_D57

A2

FBA_D58

B4

FBA_D59

B2

FBA_D60

E4

FBA_D61

E2

FBA_D62

F4

FBA_D63

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D40

U11

FBA_D41

U13

FBA_D42

T11

FBA_D43

T13

FBA_D44

N11

FBA_D45

N13

FBA_D46

M11

FBA_D47

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBA_EDC7

C2 C13

FBA_EDC5

R13 R2

2

FBA_D[32 ..63] [75]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Docum ent Number Rev

Size Docum ent Number Rev Custom

Custom

Friday, June 28 , 2013

Friday, June 28 , 2013 Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM3,4 (2/4)

Hadley 15"

1

79 101

X02

5

SID = VIDEO

S

1D3

5V_VGA_ S0

D D

1D35V_V GA_S0

C C

FBB_VREF D_L

SC820P50V2KX-1GP

12

OPS

C8026

VRA

C

5

10

C

11

D

G

1

G

4

G

11 14

G

L

1 4

L L11 L14 P11

R5

R10

B1

B3 B12 B14

D1

D3

D12 D14

E5 E10

F1

F3 F12 F14

G2

G13

H3

H12

K3 K12

L2

L13

M1

M3

M12 M14

N5

N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10

U10

H5GQ2H24 AFR-T2C-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VREFD VREFD

1

OF 2

M5A

OPS

VPP/NC#A5 VPP/NC#U5

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B

5

VSS

10

B

VSS

10

D

VSS

G

5

VSS

G

10

VSS

H

1

VSS

14

H

VSS

K

1

VSS

14

K

VSS

L5

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC9 TP_VPPNC1 0

TP8001 TPAD14 -OP-GPTP8001 TPA D14-OP-GP

1

TP8002 TPAD14 -OP-GPTP8002 TPA D14-OP-GP

1

4

Frame Buffer Patition B-Lower Half

SC820P50V2KX-1GP

12

OPS

GPIO10_ FBVREF[76,78,79,8 1]

549R2F-GP

C8022

OPS

R80

1K33R2F-GP

12

1D3

12

05

OPS

R8007

931R2F-1-GP

12

OPS

FBB_VREF _FET_L

OPS

5V_VGA_ S0

12

OPS

R8003

12

OPS

D

G

R80

R80 549R2F-GP

549R2F-GP

931R2F-1-GP

S

04

FBB_VREF D_LFBB_VREF C0

R8009

1K33R2F-GP

12

OPS

Q8001

Q8001 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

FBVREF Termination

Type

Un-termination

FBVREF%

70%Termination

Voltage

0.749V50%

1.0617V

R8006

OPS

3

C8020

SC820P50V2KX-1GP

12

GPU_GPIO10

High

Low

1D3

5V_VGA_ S0

1D35V_V GA_S0

FBB_VREF C0

FBB_VREF D_LFBB_VREF C0

VRA

M6A

C

5

VDD

C

10

VDD

D

11

VDD

1

G

VDD

4

G

VDD

G

11

VDD

G

14

VDD

L

1

VDD

4

L

VDD

L

11

VDD

14

L

VDD

P11

VDD

R5

VDD

R10

VDD

B1

VDDQ

B3

VDDQ

B12

VDDQ

B14

VDDQ

D1

VDDQ

D3

VDDQ

D12

VDDQ

D14

VDDQ

E5

VDDQ

E10

VDDQ

F1

VDDQ

F3

VDDQ

F12

VDDQ

F14

VDDQ

G2

VDDQ

G13

VDDQ

H3

VDDQ

H12

VDDQ

K3

VDDQ

K12

VDDQ

L2

VDDQ

L13

VDDQ

M1

VDDQ

M3

VDDQ

M12

VDDQ

M14

VDDQ

N5

VDDQ

N10

VDDQ

P1

VDDQ

P3

VDDQ

P12

VDDQ

P14

VDDQ

T1

VDDQ

T3

VDDQ

T12

VDDQ

T14

VDDQ

J14

VREFC

A10

VREFD

U10

VREFD

H5GQ2H24 AFR-T2C-GP

OPS

1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

OF 2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

2

1D3

5V_VGA_ S0

B

5

B

10

D

10 5

G

10

G H

1

H

14

K

1 14

K L

5 10

L P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC1 1 TP_VPPNC1 2

C8023

SC10U6D3V3MX-GP

OPS

C8007

SC10U6D3V3MX-GP

OPS

Place close VDD ball

TP8003 TPAD14 -OP-GPTP8003 TPA D14-OP-GP

1

TP8004 TPAD14 -OP-GPTP8004 TPA D14-OP-GP

1

12

OPS

12

OPS

1D35V_V GA_S0

C8014

SCD1U10V2KX-4GP

12

OPS

1D35V_V GA_S0

12

OPS

1D35V_V GA_S0

SCD1U10V2KX-4GP

12

C8021

SC1U6D3V3KX-2GP

C8015

SCD1U10V2KX-4GP

C8008

SC1U6D3V3KX-2GP

C8001

12

OPS

Place close VDD ball

C8024

SC1U6D3V3KX-2GP

12

OPS

Place close VDD ball

C8016

SCD1U10V2KX-4GP

12

OPS

Place close VDDQ ball

C8004

SC1U6D3V3KX-2GP

12

OPS

C8009

SCD1U10V2KX-4GP

1

C8003

C8002

SC1U6D3V3KX-2GP

12

OPS

C8017

C8018

SCD1U10V2KX-4GP

OPS

C8010

12

SC1U6D3V3KX-2GP

OPS

C8006

12

SCD1U10V2KX-4GP

12

OPS

1D35V_V GA_S0

C8011

SCD1U10V2KX-4GP

OPS

12

C8005

SC1U6D3V3KX-2GP

12

Place close VDDQ ball

SCD1U10V2KX-4GP

12

OPS

C8019

C8013

C8012

SCD1U10V2KX-4GP

12

OPS

Normal(MF=0)

FBB_EDC[0 ..3][75]

B B

FBB_CMD6[75] FBB_CMD11[75] FBB_CMD10[75] FBB_CMD7[75] FBB_CMD9[75]

FBB_CMD2[75] FBB_CMD4[75] FBB_CMD3[75] FBB_CMD1[75]

FBB_CMD8[75] FBB_CMD12[75] FBB_CMD0[75] FBB_CMD15[75] FBB_CMD5[75]

FBB_CLK0 P[75] FBB_CLK0 N[75] FBB_CMD14[75]

FBB_CMD13[75]

R80

121R2F-GP

12

08

OPS

A A

OPS

1 2

FBB_CMD6 FBB_CMD11 FBB_CMD10 FBB_CMD7 FBB_CMD9

FBB_CMD2 FBB_CMD4 FBB_CMD3 FBB_CMD1

FBB_CMD8 FBB_CMD12 FBB_CMD0 FBB_CMD15 FBB_CMD5

FBB_CLK0 P FBB_CLK0 N FBB_CLK0 N FBB_CMD14

FBB_DQM0

FBB_DQM2

FBB_CMD13

FBB_SEN0 FBB_ZQ0 FBB_MFB

R80

1KR2J-1-GP

FBB_WC K01

11

FBB_WC K01#

FBB_WC K23 FBB_WC K23#

5

VRAM5B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBB_D0

A4

FBB_D1

A2

FBB_D2

B4

FBB_D3

B2

FBB_D4

E4

FBB_D5

E2

FBB_D6

F4

FBB_D7

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBB_D16

U11

FBB_D17

U13

FBB_D18

T11

FBB_D19

T13

FBB_D20

N11

FBB_D21

N13

FBB_D22

M11

FBB_D23

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBB_EDC0

C2 C13

FBB_EDC2

R13 R2

FBB_EDC0 FBB_EDC1 FBB_EDC2 FBB_EDC3

4

FBB_D[0.. 31] [ 75]

R8002

40D2R2F-G P

C8025

SCD01U16 V2KX-3GP

12

OPS

FBB_CLK0 _MIDPT

OPS

1 2

FBB_W CK23[75] FBB_W CK23#[ 75] FBB_W CK01[75] FBB_W CK01#[ 75]

3

R8001

R8001 40D2R2F-G P

40D2R2F-G P

OPS

1 2

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3

1D35V_V GA_S0

R8010

121R2F-GP

1KR2J-1-GP

12

OPS

FBB_CMD10[75] FBB_CMD7[75] FBB_CMD6[75] FBB_CMD11[75] FBB_CMD9[75]

FBB_CMD3[75] FBB_CMD1[75] FBB_CMD2[75] FBB_CMD4[75]

FBB_CMD8[75] FBB_CMD15[75] FBB_CMD5[75] FBB_CMD12[75] FBB_CMD0[75]

FBB_CMD14[75]

FBB_CMD13[75]

R8013

OPS

12

R8012 1K R2J-1-GP

FBB_DQM[0 ..3] [75]

FBB_CMD10 FBB_CMD7 FBB_CMD6 FBB_CMD11 FBB_CMD9

FBB_CMD3 FBB_CMD1 FBB_CMD2 FBB_CMD4

FBB_CMD8 FBB_CMD15 FBB_CMD5 FBB_CMD12 FBB_CMD0

FBB_CLK0 P

FBB_CMD14

FBB_DQM3

FBB_DQM1

FBB_CMD13

FBB_SEN0 FBB_ZQ1 FBB_MF2

FBB_W CK23 FBB_W CK23#

FBB_W CK01 FBB_W CK01#

Mirrored(MF=1)

VRAM6B

K4

A8/A7

OPS

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

2

FBB_D24

A4

FBB_D25

A2

FBB_D26

B4

FBB_D27

B2

FBB_D28

E4

FBB_D29

E2

FBB_D30

F4

FBB_D31

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBB_D8

U11

FBB_D9

U13

FBB_D10

T11

FBB_D11

T13

FBB_D12

N11

FBB_D13

N13

FBB_D14

M11

FBB_D15

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBB_EDC3

C2 C13

FBB_EDC1

R13 R2

FBB_D[0. .31] [75]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Docum ent Number Rev

Size Docum ent Number Rev Custom

Custom

Friday, June 28 , 2013

Friday, June 28 , 2013 Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM5,6 (3/4)

Hadley 15"

1

80 101

X02

SID = VIDEO

S

5

4

3

2

1

1D3

5V_VGA_ S0

VRA

1D3

5V_VGA_ S0

VRA

C

5

C

10 11

D

1

G G

D D

1D35V_V GA_S0

C C

FBB_VREF C1

FBB_VREF D_H

SC820P50V2KX-1GP

12

OPS

4

G

11

G

14

1

L L

4

11

L L14 P11

R5

R10

B1

B3 B12 B14

D1

D3

D12 D14

E5 E10

F1

F3 F12 F14

G2

G13

H3

H12

K3 K12

L2 L13

M1

M3 M12 M14

N5

N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10

U10

C81

26

H5GQ2H24 AFR-T2C-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VREFD VREFD

1

OF 2

M7A

OPS

VPP/NC#A5

VPP/NC#U5

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

B

5

VSS

B

10

VSS

10

D

VSS

5

G

VSS

G

10

VSS

H

1

VSS

H

14

VSS

1

K

VSS

K

14

VSS

5

L

VSS

L10

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC1 3

TP8101 TPAD1 4-OP-GPTP8101 TPAD14-OP-G P

1

TP_VPPNC1 4

TP8102 TPAD1 4-OP-GPTP8102 TPAD14-OP-G P

1

Frame Buffer Patition B-Upper Half

1D3

5V_VGA_ S0

12

R81

03

OPS

R8104

931R2F-1-GP

12

OPS

FBB_VREF _FET_H

OPS

FBVREF%

70%Termination

R81 549R2F-GP

549R2F-GP

OPS

R8102

931R2F-1-GP

12

OPS

D

G

09

FBB_VREF D_H

R8101

R8105

1K33R2F-GP

12

OPS

Q8101

Q8101 2N7002K -2-GP

2N7002K -2-GP

84.2N702.J31

2ND = 84.2N702.031

S

GPU_GPIO10

Voltage

0.749V50%

1.0617V

FBB_VREF C1

SC820P50V2KX-1GP

12

OPS

GPIO10_ FBVREF[76,78,79,8 0]

FBVREF Termination

Type

Un-termination

549R2F-GP

C8102

OPS

R81

1K33R2F-GP

12

High

Low

C8103

SC820P50V2KX-1GP

1D35V_V GA_S0

FBB_VREF C1

FBB_VREF D_H

Normal(MF=0)

VRA

C

5

C

10

D

11

1

G

4

G

11

G

14 L

1 4

L

11 14

L P11

R5

R10

B1

B3 B12 B14

D1

D3 D12 D14

E5 E10

F1

F3 F12 F14

G2 G13

H3 H12

K3 K12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3 P12 P14

T1

T3 T12 T14

J14

A10 U10

H5GQ2H24 AFR-T2C-GP

Mirrored(MF=1)

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VREFC

VREFD VREFD

1

OF 2

M8A

OPS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VPP/NC#A5 VPP/NC#U5

B

5

VSS

B

10

VSS

D

10

VSS

5

G

VSS

10

G

VSS

H

1

VSS

H

14

VSS

K

1

VSS

14

K

VSS

L

5

VSS

10

L

VSS

P10

VSS

T5

VSS

T10

VSS

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

A5 U5

TP_VPPNC1 5

TP8103 TPAD1 4-OP-GPTP8103 TPAD14-OP-G P

1

TP_VPPNC1 6

TP8104 TPAD1 4-OP-GPTP8104 TPAD14-OP-G P

1

1D3

5V_VGA_ S0

C8107

SC10U6D3V3MX-GP

12

OPS

1D35V_V GA_S0

SCD1U10V2KX-4GP

12

OPS

1D35V_V GA_S0

C8117

SC10U6D3V3MX-GP

12

OPS

Place close VDD ball

1D35V_V GA_S0 1D35V_VG A_S0

SCD1U10V2KX-4GP

12

DY

C8124

SC1U6D3V3KX-2GP

12

OPS

C8110

C8111

SCD1U10V2KX-4GP

12

OPS

C8118

SC1U6D3V3KX-2GP

12

OPS

C8108

C8109

SCD1U10V2KX-4GP

12

OPS

Place close VDD ball

C8104

SC1U6D3V3KX-2GP

12

Place close VDD ball

C8112

SCD1U10V2KX-4GP

12

Place close VDDQ ball

C8114

SC1U6D3V3KX-2GP

12

OPS

C8105

SC1U6D3V3KX-2GP

12

OPS

C8113

SCD1U10V2KX-4GP

12

OPS

C8115

SC1U6D3V3KX-2GP

12

OPS

Place close VDDQ ball

C8120

C8122

SCD1U10V2KX-4GP

12

OPS

C8106

C8119

C8121

SCD1U10V2KX-4GP

12

OPS

C8116

C8123

C8125

SCD1U10V2KX-4GP

12

OPS

FBB_DQM[4 ..7] [75]

FBB_CMD26 FBB_CMD23 FBB_CMD22 FBB_CMD27 FBB_CMD25

FBB_CMD19 FBB_CMD17 FBB_CMD18 FBB_CMD20

FBB_CMD24 FBB_CMD31 FBB_CMD21 FBB_CMD28 FBB_CMD16

FBB_CLK1 P FBB_CLK1 N FBB_CMD30

FBB_DQM7

FBB_DQM5

FBB_CMD29

FBB_SEN2 FBB_ZQ3 FBB_MF4

12

FBB_W CK67 FBB_W CK67#

FBB_W CK45 FBB_W CK45#

VRAM8B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBB_D56

A4

FBB_D57

A2

FBB_D58

B4

FBB_D59

B2

FBB_D60

E4

FBB_D61

E2

FBB_D62

F4

FBB_D63

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBB_D40

U11

FBB_D41

U13

FBB_D42

T11

FBB_D43

T13

FBB_D44

N11

FBB_D45

N13

FBB_D46

M11

FBB_D47

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBB_EDC7

C2 C13

FBB_EDC5

R13 R2

2

FBB_D[32 ..63] [75]

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Docum ent Number Rev

Size Docum ent Number Rev Custom

Custom

Friday, June 28 , 2013

Friday, June 28 , 2013 Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM7,8 (4/4)

Hadley 15"

1

81 101

X02

R8110

R8110 40D2R2F-G P

40D2R2F-G P

OPS

R8111

1KR2J-1-GP

OPS

1 2

3

FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_CMD26[75] FBB_CMD23[75] FBB_CMD22[75] FBB_CMD27[75] FBB_CMD25[75]

FBB_CMD19[75] FBB_CMD17[75] FBB_CMD18[75] FBB_CMD20[75]

FBB_CMD24[75] FBB_CMD31[75] FBB_CMD21[75] FBB_CMD28[75] FBB_CMD16[75]

FBB_CMD30[75]

FBB_CMD29[75]

1D35V_V GA_S0

R8114

121R2F-GP

12

R8112 1K R2J-1-GP

FBB_EDC[4 ..7][75]

B B

2 OF 2

OPS

2 OF 2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

EDC0 EDC1 EDC2 EDC3

FBB_D32

A4

FBB_D33

A2

FBB_D34

B4

FBB_D35

B2

FBB_D36

E4

FBB_D37

E2

FBB_D38

F4

FBB_D39

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBB_D48

U11

FBB_D49

U13

FBB_D50

T11

FBB_D51

T13

FBB_D52

N11

FBB_D53

N13

FBB_D54

M11

FBB_D55

M13 U4 U2 T4 T2 N4 N2 M4 M2

FBB_EDC4

C2 C13

FBB_EDC6

R13 R2

VRAM7B

5

VRAM7B

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J5

A12/RFU#J5/NC#J5

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

J4

ABI#

G3

RAS#

G12

CS#

L3

CAS#

L12

WE#

J12

CK

J11

CK#

J3

CKE#

D2

DBI0#

D13

DBI1#

P13

DBI2#

P2

DBI3#

J2

RESET#

J10

SEN

J13

ZQ

J1

MF

D4

WCK01

D5

WCK01#

P4

WCK23

P5

WCK23#

H5GQ2H24 AFR-T2C-GP

FBB_CMD22[75] FBB_CMD27[75] FBB_CMD26[75] FBB_CMD23[75] FBB_CMD25[75]

FBB_CMD18[75] FBB_CMD20[75] FBB_CMD19[75] FBB_CMD17[75]

FBB_CMD24[75] FBB_CMD28[75] FBB_CMD16[75] FBB_CMD31[75] FBB_CMD21[75]

FBB_CLK1 P[75] FBB_CLK1 N[75] FBB_CMD30[75]

FBB_CMD29[75]

A A

OPS

R81

121R2F-GP

12

06

OPS

1 2

FBB_CMD22 FBB_CMD27 FBB_CMD26 FBB_CMD23 FBB_CMD25

FBB_CMD18 FBB_CMD20 FBB_CMD19 FBB_CMD17

FBB_CMD24 FBB_CMD28 FBB_CMD16 FBB_CMD31 FBB_CMD21

FBB_CLK1 P FBB_CLK1 N FBB_CMD30

FBB_DQM4

FBB_DQM6

FBB_CMD29

FBB_SEN2 FBB_ZQ2 FBB_MF3

R81

1KR2J-1-GP

FBB_WC K45

13

FBB_WC K45#

FBB_WC K67 FBB_WC K67#

FBB_EDC4 FBB_EDC5 FBB_EDC6 FBB_EDC7

FBB_D[32 ..63] [75]

4

R8108

40D2R2F-G P

C8101

SCD01U16 V2KX-3GP

OPS

12

FBB_W CK67[75] FBB_W CK67#[ 75] FBB_W CK45[75] FBB_W CK45#[ 75]

12

FBB_CLK1 _MIDPT

OPS

1 2

OPS

5

D = PWR.Plane.Regulator_vga_core

SSI

E

N

D D

0

307 DY PR8263, POP PR8265

0521 change resistor value from 12K ohm to 10K

S

I

P

VGA_CORE_PS I[76]

C C

B B

3D3

V_VGA_S0

PWR

PR8

263 10KR2J-3-GP

1 2

DY

PR8

265

PR8257

1 2

OPS

0R0402-PAD-2- GP

PC8214

1 2

10KR2J-3-GP

OPS

0V2KX-4GP

SCD1U1

3D3V_VGA_S0

12

PR8258

PR8258 10KR2J-3-GP

10KR2J-3-GP

OPS

12

PR8259

DY

0R2J-2-GP

DGP

U_PWR_E N[15,83]

PC8

238

12

SCD1U10V2KX-4GP

OPS

PWR_VGA _CORE_PSI

_VGA_CORE_EN

3D3

V_VGA_S0

PWR_VGA _CORE_HG2 PWR_VGA _CORE_SW2 PWR_VGA _CORE_LG2

Phase1

DCBATOUT

OPS

PC8220

SIRA

567

8

DDD

D

DDD

D

PU8202

PWR_VGA _CORE_HG1 PWR_VGA _CORE_SW1 PWR_VGA _CORE_LG1

A A

PU8206

OPS

4

G

OPS

G

567

DDD

14DP-T1-GE3-GP

SSS

123

SIRA

8

D

PU8208

12DP-T1-GE3-GP

SSS

123

5

OPS

12

567

DDD

12

PC8229

SC10U25V5KX-GP

SIRA12DP-T1-GE3-GP

8

D

SSS

123

12

PC8221

SC10U25V5KX-GP

OPS

G

4

PC8228

OPS

SC10U25V5KX-GP

12

OPS

12

PC8227

PC8227 SCD1U25V3KX- GP

SCD1U25V3KX- GP

1 2

COIL-D15UH- 2-GP

PR8226

PR8226 2D2R5F-2-G P

2D2R5F-2-G P

DY

1 2

VGA_SNB1

12

PC8231

PC8231 SC330P50V2KX-3GP

SC330P50V2KX-3GP

DY

OPS

PL8201

OPS

12

4

DGP

U_PWRO K[15,24,83]

OPS

213 10KR2J-3-GP

PR8

1 2

EO_THERM_OV ERT#[76]

VID

VGA

_CORE_VID[76]

NTC-100K-10- GP

B=4250K

NTC close Phase1 MOSFET

DCBATOUT

567

8

DDD

PU8205

OPS

G

4

123

567

8

DDD

PU8207

OPS

G

4

123

VGA_CORE

PT8210

SE330U2D5VM-14-GP

A00 0621

PT8211

SE330U2D5VM-14-GP

12

OPS

I/P cap: 10U 25V K0805 X5R/ 78 .10622.51L Inductor: CHIP IND 0.22UH M PC MC063T-R22MN/ 2.8mohm/ Isat =4 0A rms /68.R2210.10V O/P cap: CHIP CAP POL 330U 2.5 V M 6.3*4.5 2.3Arms Matsuti/77 .53371.18L H/S: SIRA14DP-T1-GE3 / 6.8mohm /[email protected]/ 84.A14DP.037 L/S: SIRA12DP-T1-GE3 / 4.4mohm /[email protected]/ 84.SRA12.037

4

1 2

DY

PR8

214 0R0402-PAD-2-GP

1 2

OPS

12

PC8216

12

SCD1U10V2KX- 4GP

OPS

PC8224

OPS

81172_AGND

SC10U25V5KX-GP

12

PU8209

SCD1U10V2KX- 4GP

OPS

PC8223

SC10U25V5KX-GP

OPS

G

4

PR8268

SIRA14DP-T1-GE3-GP

D

SSS

SIRA12DP-T1-GE3-GP

D

SSS

PR8

2150R2J-2-GP

3K92R2F-GP

OPS

12

PC8235

567

DDD

12

PR8202

OPS

81172_AGND

Phase2

OPS

12

SC10U25V5KX-GP

PC8234

SIRA12DP-T1-GE3-GP

8

D

SSS

123

12

OPS

R2

12

PC8222

SCD01U50V2KX- 1GP

12

SC10U25V5KX-GP

DY

1 2

VGA_SNB2

12

DY

5V_

S5

12

OPS

12

PC8

PC8 SC1U6D3V2KX- GP

SC1U6D3V2KX- GP

OPS

811

72_AGND

PWR

PWR_VGA _CORE_REFIN

R3

PR8204

PR8204 2KR2F-3-GP

2KR2F-3-GP

VGA_R1R3

PR8211

1 2

OPS

20KR2F-L-GP

R4

18KR2F-GP

R5

0R0402-PAD-2- GP

OPS

12

PC8236

PC8236 SCD1U25V3KX- GP

SCD1U25V3KX- GP

PL8202

1 2

OPS

COIL-D15UH- 2-GP

PR8229

PR8229 2D2R5F-2-G P

2D2R5F-2-G P

PC8233

PC8233 SC330P50V2KX-3GP

SC330P50V2KX-3GP

3

PR8

264

2D2R2J-GP

_VGA_CORE_VC C

PWR

211

811

PWR

_VGA_CORE_EN _VGA_CORE_PS I

PWR

_VGA_CORE_T ALERT#

PWR

_VGA_CORE_VID

_VGA_CORE_T SENSE

PWR_VGA _CORE_VREF

PWR_VGA _CORE_VIDBUF

12

PR8207

PR8207 20KR2F-L-GP

20KR2F-L-GP

OPS

R1

PWR_VGA _CORE_REFIN

12

PR8203

OPS

VGA_R4R5

12

PR8201

OPS

81172_AGND

VGA_CORE

OPS

3

72_AGND

PWR_VGA _CORE_FS

12

PR8208

PR8208 34KR2F-GP

34KR2F-GP

OPS

81172_AGND

PT8212

12

SE470UF2VDM- GP

ESR=6mohm

PU8

201

1

5

VCC

2

5

GND

OPS

3

E

N

4

PSI

16

PGO

OD

14

ERT#

TAL

5

VID

13

S

TSN

8

VREF

7

REFIN

6

VIDBUF

9

FS

NCP81172MNTX G-1-GP-U

74.81172.A73

C

12

PC8219

PC8219 SC2700P50V2KX-1- GP

SC2700P50V2KX-1- GP

OPS

81172_AGND

5V_

S5

PC8

212

1 2

21

PVC

C

OPS

SC4D7U6D3V 2MX-GP-U

22

PGN

D

PWR

_VGA_CORE_H G1

2

HG1

PWR

_VGA_CORE_BS T1

1

BST

1

PWR

_VGA_CORE_SW 1

2

4

PH1

_VGA_CORE_LG 1

PWR

3

2

LG1

1

7

HG2

18

BST

2

9

1

PH2

20

LG2

10

FBRTN

11

FB

12

COMP

VGA type Config Design

N14P-LP

N14P-GE

N14P-GS

N14P-GT

N14P-GV

N14P-GV2

N14M-GS

N14M-LP

N14M-GL

N14M-GE

N14E-GTX

N14E-GS

N14E-GE-B

N14E-GE

N14E-GL

1 2

OPS

PR8

216 21KR2F-GP

PWR

_VGA_CORE_H G2

PWR

_VGA_CORE_BS T2 _VGA_CORE_SW 2

PWR PWR

_VGA_CORE_LG 2

PWR_VGA _CORE_FBRTN PWR_VGA _CORE_FB

PWR_VGA _CORE_COMP

PR8212 0R0402-PAD-2-GP

OPS

1 2

PR8267

82KR2F-1-GP

1 2

PC8218

SC100P50V2JN-L -GP

OPS

81172_AGND

Current

B

25A

B

27A

B

38A

B

45A

24A 35A

B 20K 20K 2K 18K 0 2.7nF

32A 55A

B

26A 45A

B

22A 35A

B

24.33A 35.42A

C

35A 40.89A

C

95A 125A

A

65.16A 87.87A

B

65.37A 98.6A

B

65.37A 98.6A

B

46.35A 71.83A

B

2

PR8

225

0R3J-0-U-G P

OPS

PR8

230

0R3J-0-U-G P

1 2

OPS

PC8217

12

SC10P50V2JN-4G P

OPS

PWR

_VGA_CORE_BS T1_R

12

PWR

_VGA_CORE_BS T2_R

12

PR8206

1 2

49D9R2F-GP

OPS

PC8

230

PWR

1 2

SCD1U25V3KX- GP

OPS

PC8

237

PWR

1 2

SCD1U25V3KX- GP

OPS

1 2

SC47P50V2JN-3G P

1 2

PR8209

10KR2F-2-GP

OPS

_VGA_CORE_SW 1

_VGA_CORE_SW 2

PC8215

OPS

12

C8232

C8232 SC1KP25V2JX-G P

SC1KP25V2JX-G P

N14P-GT iis ConfigB

EDP-peak OCP R1/ PR8207 R2/PR8211 R3/PR8204

35A

40A

60A

75A

38.5A<OCP<45.5A

44A<OCP<52A

66A<OCP<78A

82.5A<OCP<97.5A

20K

38.5A<OCP<45.5A

60.5A<OCP<71.5A

49.5A<OCP<58.5A

38.5A<OCP<45.5A

38.96A<OCP<46.04A

44.98A<OCP<53.16A

137.5A<OCP<162.5A

96.66A<OCP<114.2A

108.5A<OCP<128.2A

79.01A<OCP<93.98A

2

20K 20K 2K 18K 0 2.7nF

39K

20K

1

PR8

228

0R0402-PAD-2- GP

PR8210

1 2

OPS

228

1 2

OPS

10R2J-2-GP

GND_SENSE [73]

1225 change P/N

1 2

OPS

PR8205

0R0402-PAD-2- GP

1 2

10R2J-2-GP

PR8227

OPS

VGA_SENSE [73]

VGA_CORE

R4/PR8203 R5/PR8201 C/PC8219

20K

30K

39K

20K

2K

3K

1.5K

2K

Title

Size Document Num ber Rev

A2

Date: Sheet of

Date: Sheet

18K

24K

30K

18K

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

NCP81172_VGA_CORE

Hadley 15"

1

0

3K

1.5K

0

2.7nF

1.8nF

1.5nF

2.7nF

X02

of

82 101Friday, June 28, 2013

5

SID = PWR.Plane.Regulator_3p3v_vga, 1p35v_vga, 1p05v_vga

S

4

3

2

1

3D3V_VGA_S0

D D

1D35V_VGA_S0 should ramp-up before 1D05V_VGA_S0

C C

5V_VGA_S0

1D0

3

D3V_VGA_S0 should ramp-up before VGA_Core

VGA_Core should ramp-up before 1D5V_VGA_S0

R8314

DGPU_PWROK[15,24,82]

1 2

10KR2J-3-GP

OPS

1D05V_VGA_EN

C8310

SCD1U10V2KX-L1-GP

1 2

OPS

1D05V_S0

3D3V_S0

1D05V_VGA_EN

5V_S0

DGPU_PWR_EN[15,82]

C8304

SC1U6D3V2KX-GP

C8302

SC1U6D3V2KX-GP

12

DY

SC1U6D3V2KX-GP

12

DY

3D3

V_S0 to 3D3V_VGA_S0

1D05V_S0 to 1D05V_VGA_S0

U8301

1

VIN1#1

2

VIN1#2

3

ON1

4

VBIAS

5

ON2

6

VIN2#6

OPS

VIN2#77VOUT2#8

TPS22966DPUR-GP

74.22966.093

GND VOUT1#14 VOUT1#13

GND

VOUT2#9

15 14 13 12

CT1

11 10

CT2

9 8

VTT_CT_105VC_2

VTT_CT_3VC_1

X01 0322

OPS

12

1D05V_VGA_OUT2

3D3V_VGA_OUT1

C8305

SC220P50V2KX-3GP

OPS

C8309

12

PG8312

1 2

GAP-CLOSE-PWR

SC1KP25V2JX-GP

0

307 Add Discharge Circuit

PR8317

10R2J-2-GP

PQ8307

PQ8307 2N7002K-2-GP

2N7002K-2-GP

DGPU_PWR_EN#

VGA_CORE

OPS

G

12

D

OPS

S

1D05V_VGA_S0

PG8313

1 2

GAP-CLOSE-PWR

C8308

SCD1U10V2KX-L1-GP

C8307

SC10U6D3V3MX-GP

GAP-CLOSE-PWR

PG8314

1 2

GAP-CLOSE-PWR

PG8315

1 2

GAP-CLOSE-PWR

12

DY

3D3V_VGA_S0

C8301

SC10U6D3V3MX-GP

12

DY

1 2

OPS

3D3V_AUX_S5

C8306

SCD1U10V2KX-L1-GP

1 2

DGPU_PWR_EN#

1 2

OPS

PR8313

PR8313 100KR2J-1-GP

100KR2J-1-GP

PQ8305

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

3rd = 84.2N702.E3F

DGPU_PWR_EN[15,82]

6

123 4

S D

GD S

5

1D05V_VGA_S0

12

10R2J-2-GP

OPS

10R2J-2-GP PR8316

PR8316

84.2N702.J31

OPS

G

1D35V_S3

D

1D35V_VGA_S0

B B

EC_FB_CLAMP[24,75,76]

DGPU_PWROK[15,24,82]

A A

5

4

3D3V_AUX_S5

OPS GC6

D8301

1

2

BAT54CPT-2-GP

75.00054.K7D

R8312

1 2

0R2J-2-GP

Non-GC6

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

1 2

PR8311

PR8311 100KR2J-1-GP

100KR2J-1-GP

2nd = 84.DM601.03F

3

PC8303

SC10U6D3V3MX-GP

1D5V_VGA_EN#

OPS

PQ8304

2N7002KDW-GP

84.2N702.A3F

3rd = 84.2N702.E3F

1D5V_VGA_EN

12

OPS

SCD01U50V2KX-1GP

GD S

5

6

123 4

G

S D

OPS

D

8

D

7

D

6

D

5

SIRA06DP-T1-GE3-GP

84.SRA06.037

PC8302

OPS

PR8312

330KR2J-L1-GP

OPS

1D5V_ENABLE

DY

12

PQ8308

S

1

OPS

S

2

S

3

G

4

1D5V_ENABLE_RC

A00 0618

1 2

R8313

0R0402-PAD-2-GP

15V_S5DCBATOUT

12

DY

PR8301

PR8301 10MR2J-L-GP

10MR2J-L-GP

3

3.3V +/- 5%

4.88A

100KR2J-1-GP

PR8310

1D35V_VGA_S0

12

PC8307

PC8307 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

OPS

0319 modify Discharge Circuit

1D35V_VGA_S0

12

10R2J-2-GP

OPS

PR8315

DIS_1D5V_VGA_S0

PQ8306

2N7002K-2-GP

84.2N702.J31

1D5V_VGA_EN#

D

OPS

S

G

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

DISCRETE VGA POWER

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

83 101Friday, June 28, 2013

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

84 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

85 10 1Friday, June 28, 201 3

1

X02

5

SSI

D = User.Interface

SO1

OPS

D D

1

S

TF217R1 28H83-2-GP

34.4Y702.301

SO2

OPS

1

S

TF217R1 28H83-2-GP

34.4Y702.301

SO3

OPS

1

S

TF217R1 28H83-2-GP

34.4Y702.301

34.4T025.001

S

P

RING-52-GP

S

1

4

S

34.4T025.001

S

2

1

P

RING-52-GP

S

3

1

P

RING-52-GP

S

34.4T025.001

S

4

1

P

RING-52-GP

S

34.4T025.001

3

2

1

0116 Add RF CAP

C3

C1

C1 HOLE197 R166-1-GP

H2

H3

H4

DCBATOU T

HOLE197 R166-1-GP

C2

C2 HOLE197 R166-1-GP

HOLE197 R166-1-GP

C3 HOLE197 R166-1-GP

HOLE197 R166-1-GP

1

C C

HOLET25 6B315R111-GP

ZZ.00PAD.M01

1

HT85BE8 5R29-U-5-GP

ZZ.00PAD.D41

1

HOLET25 6B315R111-GP

ZZ.00PAD.M01

12

EC8602

EC8601

DY

SCD1U25V2KX-GP

12

EC8604

EC8603

EC8605

DY

SCD1U25V2KX-GP

1

ZZ.00PAD.V71

1

ZZ.00PAD.V71

1

ZZ.00PAD.V71

0528 Add NPTH hole

0117 Add EMC CAP

PAD1

1

PAD-3P-GP

B B

3

2

DCBATOU T

12

EC8606

EC8607

DY

SCD1U25V2KX-GP

5V_S0 3D3V_S 0 VGA_CORE 1 D05V_S0

12

DY

12

EC8614

EC8615

DY

EC8613

12

EC8608

SCD1U25V2KX-GP

12

EC8616

DY

12

EC8610

EC8612

EC8611

SCD1U25V2KX-GP

DY

SCD1U25V2KX-GP

DY

EC8611

DY

SCD1U25V2KX-GP

12

EC8620

DY

12

EC8609

12

EC8621

EC8622

DY

SCD1U25V2KX-GP

A A

5

4

SCD1U25V2KX-GP

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

3

2

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

86 10 1

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

87 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Reserved

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Taipei Hsien 221, Taiwan, R.O.C.

Hadley 15"

88 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

89 10 1

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

90 10 1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

91 10 1

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

92 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Reserved

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

93 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

Hadley 15"

94 10 1Friday, June 28, 201 3

1

X02

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

95 10 1Friday, June 28, 2013

95 10 1Friday, June 28, 201 3

1

X02

5

D = XDP

SSI

D D

4

3

2

1

CPU XDP

3D3V_S5

XDP_BPM 0 XDP_BPM 1 XDP_BPM 2 XDP_BPM 3 XDP_BPM 4 XDP_BPM 5 XDP_BPM 6 XDP_BPM 7

CFG[19:0]

XDP_BPM [7:0]

XDP_PRE Q#

XDP_PRD Y#

TP9601TP9601

1

TP9602TP9602

1

TP9612TP9612

1

TP9613TP9613

1

TP9614TP9614

1

TP9615TP9615

1

TP9616TP9616

1

TP9617TP9617

1

TP9618TP9618

1

TP9619TP9619

1

CFG[19:0][6]

1

23

RN9602

SRN1KJ-1 1-GP-U

C C

XDP

4

SYS_PW ROK [17,2 4]

PM_PW RBTN# [17,24 ]

CFG0 CFG12 CFG1

CFG2 CFG3 CFG15

CFG4 CFG5

CFG6 CFG7

CFG8 CFG9

CFG10 CFG11

TP9624TP9624

1

TP9623TP9623

1

TP9622TP9622

1

TP9621TP9621

1

TP9609TP9609

1

TP9608TP9608

1

TP9607TP9607

1

TP9606TP9606

1

TP9629TP9629

1

TP9630TP9630

1

TP9631TP9631

1

TP9632TP9632

1

TP9639TP9639 TP9640TP9640

CFG13

CFG14

CFG17 CFG16

CFG19 CFG18

1 1

TP9635TP9635

1

TP9636TP9636

1

TP9637TP9637

1

TP9638TP9638

1

TP9627TP9627

1

TP9628TP9628

1

TP9633TP9633

1

TP9634TP9634

1

PCIE_CLK_ XDP_P PCIE_CLK_ XDP_N

PCIE_CLK_ XDP_P [18] PCIE_CLK_ XDP_N [1 8]

XDP_BPM [7:0][4]

XDP_PRE Q#[4]

XDP_PRD Y#[4]

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

Size Document N umber Rev A3

A3

Friday, June 28, 201 3

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

CPU XDP

96 10 1

1

X02

A

e S

Nam

chematics Notes

B

Pro

Name

c

C

essor StrappingPCH Strapping

a

p Description

Str

1 unless specified otherwise)

D

(Default value for each bit is

Default Value

E

C

4 4

POWER PLANE

VOLTAGE DESCRIPTION

Voltage Rails

ACTIVE IN

3 3

2 2

SMBus ADDRESSES

2

PCIE Routing

LANE1 X

LANE2

LANE3

LANE4

1 1

LANE5

LANE6

LANE7

LANE8

X

Mini Card1(WLAN)

X

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

mSATA

USB Table

Pair

0

1

2

3

4

5

6

7

Device

USB port 1,with Power Share

USB 2.0 HDMI

USB port2 (usb redriver)

X

Touch Panel

Card Reader

BLUETOOTH

CAMERA

I C / SMBus Addresses

Device EC SMBus 1 Battery 0 CHARGER PS8122(HDMI Switch) (Bottom Dock) USB3.0 redriver PS8710 (Bottom Dock)

EC SMBus 2 Battery 1 PCH Discrete VGA Thermal SML1_CLK/SML1_DATA PS8321 HDMI level shifter NCT7718W

EC SMBus 3 NCT5605Y-0 NCT5605Y-1

PCH SMBus SO-DIMMA SO-DIMMB Intel LAN 82579 G-Sensor MINI WWAN INTEL LAN82579

0x96 & 0x94 0x9C or 0x9E 0x96 & 0X97 0x98 or 0x99

CHIEF RIVER ORB

Address Bus

0x16 0x12 0x9E 0x40

0x16

0x30 0x32 SMB2_CLK/SMB2_DATA

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

SMB2_CLK/SMB2_DATA SMB2_CLK/SMB2_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document N umber Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Hadley 15"

97 10 1Friday, June 28, 201 3

X02

5

D D

C C

4

3

2

1

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1 , Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Change History

Size Document N umber Rev

Date: Sheet of

Hadley 15"

Taipei Hsien 221, Taiwan, R.O.C.

98 10 1Friday, June 28, 2013

98 10 1Friday, June 28, 201 3

1

X02

5

4

ntel-Power Up Sequence

I

3

2

1

(AC

D D

C C

mode)

1

C_VCC

+RT

T

RTC_RST#

DCBATOUT

3D3V_AUX_S5

S5_ENABLE

5V_S5

3D3V_S5

PM_RSMRST#

PCH_SUSCLK_KBC

AC_PRESENT

KBC_PWRBTN#

PM_PWRBTN#

PM_SLP_S4#

1D35V_S3

1.35V_VTT_PWRGD

PM_SLP_S3#

1D5V_S0

1D05V_S0

1.05VTT_PWRGD / RUNPWROK

5V_S0

3D3V_S0

DDR_VTT_PG_CTRL

0D675V_S0

>9m

T10

s

T11

printings:KBC GPIO involved

Red

T2

T

3

T4

T5

6

T

T12

T13

KBC GPIO34 control

T7

>5msT8

<90ms

0ms<

T9

T15T14

T16

T17

T18

T19

T20

T21

KBC GPIO43 to PCH

KBC GPIO84 control

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T22

(DC

mode)

+RT

C_VCC

RTC_RST#

DCBATOUT

3D3V_AUX_S5

KBC_PWRBTN#

S5_ENABLE

3D3V_S5

5V_S5

PM_PWRBTN#

C

H_RSMRST#

P

PCH_SUSCLK_KBC

PM_SLP_S4#

1D35V_S3

1.35V_VTT_PWRGD

PM_SLP_S3#

1D5V_S0

1D05V_S0

1.05VTT_PWRGD / RUNPWROK

5V_S0

3D3V_S0

printings:KBC GPIO involved

Red

T

1

T

2

T3

T4

T5

T6

T7

T8

T9 T10 >5ms

T11

T12

T13

T15T14

T16

T17

T18

T19

T21

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T20

B B

A A

43

RUNPWROK

H_VCCST_PWRGD

PM_SLP_S3#

PCH_PWROK

H_VR_ENABLE

VCC_CORE

IMVP_PWRGD

SYS_PWROK

H_CPU_SVIDDAT

PLT_RST#

5

T23

T24

T25

T26

T27

T28

4

3

DDR_VTT_PG_CTRL

0D675V_S0

RUNPWROK

H_VCCST_PWRGD

PM_SLP_S3#

PCH_PWROK

H_VR_ENABLE

VCC_CORE

IMVP_PWRGD

SYS_PWROK

H_CPU_SVIDDAT

PLT_RST#

T23

T24

T25

T26

T27

T28

2

T22

Title

Power Sequence

Size Document Number Rev

Date: Sheet of

1

Hadley 15"

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

99 101Friday, June 28, 2013

X02

5

istron SHARK BAY POWER UP SEQUENCE DIAGRAM

W

4

3

2

1

D D

C C

B B

D

C

a

ttery

B

age43

7

-

P

AC

Adapter in

Page42

+DC_IN

SLP_S3# de-assert, delay 20ms; PCH_PWROK assert.

BT+

SWITCH

age44

P

SWITCH

Page44

Charger

BQ24715

ACOK

AD+

Page44

7

-6

AC_IN

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

6

PCH_PWROK

11

H_CPU_SVIDDAT

H_VR_ENABLE

DCBATOUT

-5

DCBATOUT

1

VDIO

VR_ON

3

-

S5_ENABLE

EN1

EN2

TPS51225CRUKR

VIN

DC/DC

(3.3V/5V)

3D3V_AUX_S5

SWITCH

-4

Page24

3D3V_AUX_KBC

PSL_IN1#

KBC

PSL_IN2#

NPCE985

GPIO8

GPIO01

GPIO80

S0_PWR_GOOD

10

SLP_S3# de-assert, delay 200ms; S0_PWR_GOOD assert.

TPS51622

CSD97374

PGOOD

Page46

PWR_VCC_PWM1

VSW

Page47

VCC_CORE

Page41

GPIO34

GPIO43

GPIO20

Page24

9

8

3D3V_S5

-2

5V_S5

-3

S5_ENABLE

-1

RSMRST#_KBC

PM_PWRBTN#

2

DPWROK

Haswell ULT CPU

RSMRST#

PWRBTN#

Lynx Point PCH

APWROK

PCH_PWROK

5

H_VCCST_PWRGD

SYS_PWROK be asserted after S0_ PWR_GOOD assertion and CPU core VR powe r good assertion.

S0_PWR_GOOD

IMVP_PWRGD

4

PM_SLP_S3#

DDR_VTT_PG_CTRL

DDR_PG_CTL

with

VCCST_PWRGD

EN PGOOD

4

SYS_PWROK

P

M_SLP_S4#

DCBATOUT

VIN

TPS51367

1D35V_S3

TPS51206

3

Page48

VIDSOUT

PLTRST#

VR_READY

SW

VR_EN

Page46

4a

1D05V_S0

RUNPWROK

4b

0D675V_S0

H_VR_ENABLE

H_CPU_SVIDDAT

11

12

PCI_PLTRST#

DCB

ATOUT

3a

TPS51367

EN

VIN

PGOOD

Page48

1D35V_S3

SW

RUNPWROK

4b

RUNPWROK

4b

7

RUNPWROK

3D3V_S5

SWITCH

Page36

SWITCH

Page36

Level Shifter

Page7

5V_S0

3D3V_S0

H_VCCST_PWRGD

5

4a

PM_SLP_S3#

TPS51312

EN

VIN

4

VOUT

PGOOD

Page51

1D5V_S0

RUNPWROK

4b

A A

4b 5 6 7 8 9 10 11 121 2 3a 4 4a

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., H sichih, Taipei Hsie n 221, Taiwan, R.O.C.

Taipei Hsie n 221, Taiwan, R.O.C.

Hadley 15"

1

Taipei Hsie n 221, Taiwan, R.O.C.

100 101Friday, June 28, 2013

X02

Title

Power Block Diagram

Size Document Num ber Rev

Date: Sheet of

5

4

3

2

Date: Sheet of