Dell 14 N4050 Schematics

5

4

3

2

1

Enrico Caruso 14

D D

Muxless/UMA Schematics Document

Sandy Bridge

Intel PCH

2011-04-07

C C

REV : A00

DY : None Installed UMA: UMA ONLY installed PSL: KBC795 PSL circuit for 10mW solution installed.

B B

10mW: External circuit for 10mW solution installed. DIS: MUXLESS solution installed. Surge: For GO Rural config stuff. GIGA: For GIGA LAN config stuff. HDMI: For HDMI config stuff. DIS_CRT: Pure DIS install

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Cover Page

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

A00

5

##OnMainBoard

VRAM

D D

1GB (128Mx16x4)

512MB (64Mx16x4)

gDDR3 900NHz

88,89,90,91

gDDR3 900MHz

Seymou-XT S3

83.84,85,86,87

C C

CRT

LCD

HDMI

B B

50

49

51

SD/MMC/MS/ MS Pro

CardReader

74

Audio board

Internal Analog MIC

HP1

58

82

MIC IN

2CH SPEAKER

A A

5

58

CRT

LVDS

HDMI

Realtek RTS5138

Azalia CODEC

IDT 92HD87

4

3

Block Diagram (Discrete/UMA co-lay)

4

(Discrete only)

32

29

4

PCIe x 8

FDIx4x2

USB2.0

AZALIA

24MHz

Intel CPU

Sandy Bridge

4,5,6,7,8,9,10

DMIx4 1GB/s

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

17,18,19,20,21,22,23,24,25

SATA

3Gbps

ODDHDD

Flash ROM

5656

SPI

4MB

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

PCIE

100MHz

2.5Gbps

USB 2.0

480Mbps

LPC Bus

33MHz

60

3

Project code: 91.4IU01.001 PCB P/N : 48.4IU16.0SC Revision : 10315-SC

PCIE x 1

Touch PAD

DDRIII 1066/1333

10/100 /1000 LOM

Realtek RTL8111E (Giga LAN)

Realtek RTL8105E (10M/100M)

KBC

NUVOTON

NPCE795BA0DX

PS/2 PS/2

Int. KB

6969

2

USB 2.0 x 1

USB 2.0 x 2

27

2

Slot 0

15

Slot 1

14

31

USB 2.0 x 1

Thermal

ENE P2800

ENE P2793 Fan

28

1

SYSTEM DC/DC

APL5916

INPUTS

DCBATOUT

OUTPUTS

0D85V_S0

48

CPU DC/DC

VT1316+1314

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE

SYSTEM DC/DC

TPS51218

INPUTS

DCBATOUT

OUTPUTS

1D05V_VTT

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT 5V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

SYSTEM DC/DC

RJ45 CONN

Mini-Card

802.11a/b/g

WLAN+BT3.0

TPS51216R

INPUTS

DCBATOUT

59

GFX DC/DC

VT1316+1317

INPUTS

64

DCBATOUT

INPUTS

DCBATOUT

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

VGA

RT8208B

OUTPUTS

VGA_CORE

TI CHARGER

BQ24707

CAMERA

M/B USB x1 (Left)

I/O board USB x2 (Right)

28

Title

Size Document Number Rev

A3

Date: Sheet of

49

61

82

Block Diagram

Enrico Caruso 14

INPUTS

+DC_IN_S5

SYSTEM DC/DC

INPUTS

3D3V_S5

SYSTEM DC/DC

INPUTS OUTPUTS

1D5V_S3 1V_VGA_S0

3D3V_S0

INPUTS OUTPUTS

1D5V_S3 5V_S5

PCB LAYER

L1:Top L2:GND L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

OUTPUTS

APW7153B

OUTPUTS

G9731

Switches

L4:Signal L5:VCC L6:Bottom

2 105Wednesday, April 13, 2011

42~44

40

DCBATOUT+PBATT

1D8V_S0

1D8V_VGA_S0

1D5V_S0 5V_S0 3D3V_S03D3V_S5

A00

45

41

46

44

92

47

93

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-k

No Reboot Mode with TCO Disabled:

- 10-k weak pull-up resistor.



GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B



C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort.

Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

N/A

USB Table

Pair

0

1

2

3

4

5

6

7

1 1

8

9

10

11

12

13

Device

X

USB Ext. port 2 (MB)

X

CARD READER

X

USB Ext. port 3

USB Ext. port 1

X

Mini Card1 (WLAN+BT)

CAMERA

X

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

HURON RIVER ORB

Address Hex Bus Ref Des

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

PCIE Routing

LANE1 X

LANE2

LANE3 X

LANE5

LANE6

LANE7

LANE8 X

LAN

WirelessLANE4

X

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Table of Content

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

3 105

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19

FDI_LSYNC019 FDI_LSYNC119

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403

1 2

10KR2J-3-GP

DY

Stuff to disable internal graphics function for power saving.

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

eDP_HPD

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-k pull-Up resistor on the motherboard.

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

SANDY

62.10055.421

2nd = 62.10040.771

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SKT-BGA989C470395-1H180

DMI

Intel(R) FDI

eDP



CPU1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN7 83 PEG_RXN6 83 PEG_RXN5 83 PEG_RXN4 83 PEG_RXN3 83 PEG_RXN2 83 PEG_RXN1 83 PEG_RXN0 83

PEG_RXP7 83 PEG_RXP6 83 PEG_RXP5 83 PEG_RXP4 83 PEG_RXP3 83 PEG_RXP2 83 PEG_RXP1 83 PEG_RXP0 83

C409 SCD22U10V2KX-1GP

1 2

DIS

C410 SCD22U10V2KX-1GP

1 2

DIS

C411 SCD22U10V2KX-1GP

1 2

DIS

C412 SCD22U10V2KX-1GP

1 2

DIS

C413 SCD22U10V2KX-1GP

1 2

DIS

C414 SCD22U10V2KX-1GP

1 2

DIS

C415 SCD22U10V2KX-1GP

1 2

DIS

C416 SCD22U10V2KX-1GP

1 2

DIS

C425 SCD22U10V2KX-1GP

1 2

DIS

C426 SCD22U10V2KX-1GP

1 2

DIS

C427 SCD22U10V2KX-1GP

1 2

DIS

C428 SCD22U10V2KX-1GP

1 2

DIS

C429 SCD22U10V2KX-1GP

1 2

DIS

C430 SCD22U10V2KX-1GP

1 2

DIS

C431 SCD22U10V2KX-1GP

1 2

DIS

C432 SCD22U10V2KX-1GP

1 2

DIS

A A

1D05V_VTT

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG Static Lane Reversal

PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

PEG_TXN7 83 PEG_TXN6 83 PEG_TXN5 83 PEG_TXN4 83 PEG_TXN3 83 PEG_TXN2 83 PEG_TXN1 83 PEG_TXN0 83

PEG_TXP7 83 PEG_TXP6 83 PEG_TXP5 83 PEG_TXP4 83 PEG_TXP3 83 PEG_TXP2 83 PEG_TXP1 83 PEG_TXP0 83

CPU (PCIE/DMI/FDI)

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

4 105

A00

SSID = CPU

5

H_THERMTRIP#22,36,85

H_CPUPWRGD22,36

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

1 2

1K5R2F-2-GP

H_SNB_IVB#18

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

H_PECI22,27

R513

10KR2J-3-GP

R509

R509 750R2F-GP

750R2F-GP

1 2

56R2J-4-GP

R504

1 2

C504

R505

1 2

DY

H_CPUPWRGD_R

1 2

0R2J-2-GP

12

H_PROCHOT#27,40,42

H_PM_SYNC19

R503

1 2

12

1D05V_VTT

R501

1 2

62R2J-GP

D D

62R2J-GP

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

CRB : 47pf CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

X01-0127 Add C504 for noise couple.

C C

R510

PLT_RST#18,27,31,65,71,83

R510

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

0R0402-PAD

SCD1U10V2KX-5GP

VDDPWRGOOD

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

CPU1B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

62.10055.421

2nd = 62.10040.771

SANDY

MISCTHERMALPWR MANAGEMENT

CPU1

SKT-BGA989C470395-1H180

3

2 OF 9

A28

BCLK

A27

BCLK#

PRDY# PREQ#

TCK TMS

TRST#

TDI

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3

MISC

DDR3

MISC

JTAG & BPM

2

CLK_EXP_P 20 CLK_EXP_N 20

RN502

CLK_DP_P_R CLK_DP_N_RH_PROCHOT#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

RN502

4

R502

1 2

1 23

SRN1KJ-7-GP

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1

TP511 TPAD14-GPTP511 TPAD14-GP

1

TP512 TPAD14-GPTP512 TPAD14-GP

1 1 1 1 1 1 1 1

1D05V_VTT

X01-0210 MergeR512 R514

SM_DRAMRST# 37

11/16 remove TP for layout space

TP503 TPAD14-GPTP503 TPAD14-GP TP504 TPAD14-GPTP504 TPAD14-GP TP505 TPAD14-GPTP505 TPAD14-GP TP506 TPAD14-GPTP506 TPAD14-GP TP507 TPAD14-GPTP507 TPAD14-GP TP508 TPAD14-GPTP508 TPAD14-GP TP509 TPAD14-GPTP509 TPAD14-GP TP510 TPAD14-GPTP510 TPAD14-GP

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

12/6 swap net for layout

RN501

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

1D05V_VTT

3D3V_S0

XDP_DBRESET#19

XDP_DBRESET#

1 2

R516

R516 10KR2J-3-GP

10KR2J-3-GP

B B

1D05V_VTT

12

R518

DY

75R2J-1-GP

Buffered reset to CPU

PLT_RST#18,27,31,65,71,83

U501

1

IN B

VCC

2

IN A

DY

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

75R2J-1-GP

5

4

A A

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

DY

12

R515

R515 0R2J-2-GP

0R2J-2-GP

BUF_CPU_RST#BUFO_CPU_RST#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

CPU (THERMAL/CLOCK/PM )

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

5 105

A00

5

4

3

2

1

SSID = CPU

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0]15 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ[63:0]

M_A_BS015 M_A_BS115 M_A_BS215

M_A_CAS#15 M_A_RAS#15 M_A_WE#15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5

AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

CPU1

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 15 M_A_DIM0_CLK_DDR#0 15 M_A_DIM0_CKE0 15

M_A_DIM0_CLK_DDR1 15 M_A_DIM0_CLK_DDR#1 15 M_A_DIM0_CKE1 15

M_A_DIM0_CS#0 15 M_A_DIM0_CS#1 15

M_A_DIM0_ODT0 15 M_A_DIM0_ODT1 15

M_A_DQS#[7:0] 15

M_A_DQS[7:0] 15

M_A_A[15:0] 15

M_B_DQ[63:0]

M_B_BS014 M_B_BS114 M_B_BS214

M_B_CAS#14 M_B_RAS#14 M_B_WE#14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

CPU1

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 14 M_B_DIM0_CLK_DDR#0 14 M_B_DIM0_CKE0 14

M_B_DIM0_CLK_DDR1 14 M_B_DIM0_CLK_DDR#1 14 M_B_DIM0_CKE1 14

M_B_DIM0_CS#0 14 M_B_DIM0_CS#1 14

M_B_DIM0_ODT0 14 M_B_DIM0_ODT1 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

SANDY

62.10055.421

2nd = 62.10040.771

A A

5

4

3

SANDY

62.10055.421

2nd = 62.10040.771

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (DDR)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

6 105

1

A00

5

4

3

2

1

SSID = CPU

5 OF 9

CPU1E

11/17 remove TP715

AK28

CFG0

AK29

D D

CFG2

CFG4 CFG5 CFG6 CFG7

AL26 AL27

AK26

AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

SANDY

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

CFG2

CFG4

DIS

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

PEG Static Lane Reversal

CFG2

11/17 change R703 to 1K but dummy

Display Port Presence Strap

CFG4

DY

12

R703

R703 1KR2F-3-GP

1KR2F-3-GP

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AT2 RSVD#AT1 RSVD#AR1

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

0702 Modify

TP713

AN35

TP714

AM35

AT2 AT1 AR1

CFG5

CFG6

CFG7

1

TP713 TPAD14-GPTP713 TPAD14-GP

1

TP714 TPAD14-GPTP714 TPAD14-GP

DY

12

R701

1KR2J-1-GP

DY

12

R704

1KR2J-1-GP

R705

R705 1KR2J-1-GP

1KR2J-1-GP

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

AJ31

RSVD#AJ31

AH31

RSVD#AH31

AJ33

RSVD#AJ33

AH33

RSVD#AH33

AJ26

M3 - Processor Generated SO-DIMM VREF_DQ

DY

C C

M_VREF_DQ_DIMM0 M_VREF_DQ_DIMM1

M_VREF_CA_DIMM0

M_VREF_CA_DIMM1

R707 0R2J-2-GP

R706 0R2J-2-GP

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

1KR2F-3-GP

20 mils

R710 0R2J-2-GP

1 2

DY

B B

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

1KR2F-3-GP

H_VCCP_SEL

RSVD#AJ26

B4

RSVD#B4

D1

RSVD#D1

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

A19

RSVD#A19

J15

RSVD#J15

SANDY

SKT-BGA989C470395-1H180

62.10055.421

2nd = 62.10040.771

CPU1

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RESERVED

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (RESERVED)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

7 105

1

A00

5

SSID = CPU

D D

PROCESSOR CORE POWER

VCC_CORE

C C

B B

A A

DY

12

C820

53A

C801

SC4D7U6D3V3KX-GP

11/15 change Caps to 78.22610.51L

12

SC22U4V3MX-GP

DY

12

C804

C803

C802

SC10U6D3V5KX-1GP

12

C819

C818

SC22U6D3V5MX-2GP

SC4D7U6D3V3KX-GP

12

C807

C806

SC22U6D3V5MX-2GP

12

C812

C817

SC22U4V3MX-GP

12/23 stuff the capacities

SC22U6D3V5MX-2GP

12

C811

SC22U6D3V5MX-2GP

12/28 Yellow mark for OPI change

12

C816

C821

SC22U6D3V5MX-2GP

12

C837

C836

SC22U6D3V5MX-L2GP

12

C822

SC22U6D3V5MX-2GP

12

C835

SC22U6D3V5MX-2GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

12

C823

C824

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

C833

C834

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C825

SC22U6D3V5MX-2GP

12

C831

C832

SC22U6D3V5MX-2GP

11/4 add Caps to 28 location as vendor recommand.

X01-0127 Stuff C812, C822, C831, C834 for VCC core noise issue.

X01-0217 Stuff C801=22uF change C817 to 22uF

5

C826

SC22U6D3V5MX-L2GP

SC22U6D3V5MX-2GP

4

POWER

CPU1F

VCC_CORE

AG35

VCC

AG34

VCC

AG33

VCC

AG32

VCC

AG31

VCC

AG30

VCC

AG29

VCC

AG28

VCC

AG27

VCC

AG26

VCC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

AC31

VCC

AC30

VCC

AC29

VCC

AC28

VCC

AC27

VCC

AC26

VCC

AA35

VCC

AA34

VCC

AA33

VCC

AA32

VCC

AA31

VCC

AA30

VCC

AA29

VCC

AA28

VCC

AA27

VCC

12

C827

SC22U6D3V5MX-2GP

12

C828

SC22U6D3V5MX-2GP

4

AA26

VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

62.10055.421

2nd = 62.10040.771

POWER

SANDY

CORE SUPPLY

CPU1

3

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

VCC_SENSE

VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

SENSE LINES SVID

3

2

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12/28 Yellow mark for OPI change

PROCESSOR VCCIO: 8.5A

12

C805

SC4D7U6D3V3KX-GP

DY

12

C809

C808

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

12/23 stuff the capacities

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

12

C829

SC10U6D3V5KX-1GP

12

C842

C830

SC22U6D3V5MX-2GP

11/16 follow DN13 to meet schematic check list

These resistors need to close to power IC

11/17 change part refernce R807 to R805

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R803 43R2J-GPR803 43R2J-GP

1 2

VCCIO_SENSE 45 VSSIO_SENSE 45

2

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

VCC_CORE

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

1

1D05V_VTT

12

DY

12

SC10U6D3V5KX-1GP

VR_SVID_ALERT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

C839

C838

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

R805 75R2J-1-GPR805 75R2J-1-GP

R806 54D9R2F-L1-GP

R804 130R2F-1-GPR804 130R2F-1-GP

VCCSENSE 42 VSSSENSE 42

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

12

1 2

C841

C840

SC10U6D3V5KX-1GP

C845

SC22U6D3V5MX-2GP

1D05V_VTT

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Enrico Caruso 14

1

8 105

A00

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

D D

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

12

C902

C901

SC4D7U6D3V5KX-3GP

SC10U6D3V5KX-1GP

12/28 Yellow mark for OPI

12

C908

SC4D7U6D3V3KX-GP

C C

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

1D8V_S0

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

4

PROCESSOR VAXG: 33A

12

C904

SC10U6D3V5KX-1GP

DY

12

C922

SC1U10V2KX-1GP

12

C906

C905

DY

SC10U6D3V5KX-1GP

12

C920

C921

SC4D7U6D3V3KX-GP

C924

SC1U10V2KX-1GP

3

POWER

CPU1G

AT24

VAXG

AT23

VAXG

AT21

VAXG

AT20

VAXG

AT18

VAXG

AT17

VAXG

AR24

VAXG

AR23

VAXG

AR21

VAXG

AR20

SC10U6D3V5KX-1GP

SC4D7U6D3V3KX-GP

AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24 AL23 AL21 AL20 AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

POWER

SANDY

GRAPHICS

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

PROCESSOR VDDQ: 10A

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

12

C909

DY

12/28 Yellow mark for OPI

PROCESSOR VCCSA: 6A

12

C916

M27 M26 L26 J26 J25 J24 H26 H25

2

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

12

C910

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C915

SC10U6D3V5KX-1GP

VCC_AXG_SENSE VSS_AXG_SENSE

+V_SM_VREF_CNT 37

1D5V_S0

12

C911

SC10U6D3V3MX-GP

12

C917

SC10U6D3V5KX-1GP

12

C912

SC4D7U6D3V5KX-3GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

12

DY

EC902

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

C914

C913

2nd = 77.C3371.13L

SCD1U50V3KX-GP

TC901

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

79.33719.20L

VCC_GFXCORE

12

DY

C907

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

12

DY

C918

SCD1U10V2KX-5GP

1

12

DY

C919

SCD1U10V2KX-5GP

1D5V_S3

12

DY

C925

SCD1U10V2KX-5GP

11/16 Follow Annie team's schematic by power solution

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

62.10055.421

2nd = 62.10040.771

VCCSA_SENSE

CPU1

1.8V RAIL

FC_C22

VCCSA_VID1

H23

C22 C24

VCCSA_SENSE

H_FC_C22 VCCSA_SEL

R910

1 2

10R2J-2-GP

4

RN901

DY

SRN1KJ-7-GP

1

2 3

0D85V_S0

R910 close to pin H23.

VCCSA_SEL 48

11/ 17 dummy RN901

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (VCC_GFXCORE)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

9 105

1

A00

5

4

3

2

1

SSID = CPU

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

CPU1

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31

F34 F31 F29

CPU1I

SANDY

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

CPU1

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

62.10055.421

2nd = 62.10040.771

A A

5

4

3

SANDY

62.10055.421

2nd = 62.10040.771

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

CPU (VSS)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

10 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

XDP

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

11 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

12 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

13 105Wednesday, April 13, 2011

A00

5

SSID = MEMORY

M_B_A[15:0] 6

DDR_VREF_S3

R1405

R1405 0R0402-PAD

D D

C C

X02-0303 change 0R to short pad

B B

A A

0R0402-PAD

1 2

12

C1423

DDR_VREF_S3

R1404

R1404 0R0402-PAD

0R0402-PAD

1 2

12

C1411

0D75V_S0

12

DY

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

C1419

DY

SC1U6D3V2KX-GP

M_VREF_CA_DIMM1

12

C1425

C1424

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM1

12

C1412

C1413

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1421

C1420

SC1U6D3V2KX-GP

5

DY

12

C1422

DY

SC1U6D3V2KX-GP

M_B_BS26

M_B_BS06 M_B_BS16

M_B_DQ[63:0]6

12

C1418

SC10U6D3V5KX-1GP

M_B_DIM0_ODT06 M_B_DIM0_ODT16

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#15,37

M_B_DQS#[7:0] 6

M_B_DQS[7:0] 6

0D75V_S0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H =5.2mm

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-135-GP

62.10024.E21

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198

199

197 201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM1 SA1_DIM1

3

1D5V_S3

Layout Note: Place these Caps near SO-DIMMA.

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20,65 PCH_SMBCLK 15,20,65

TS#_DIMM0_1 15

1D5V_S3

SWAP SA0_DM1 and SA1_DIM1 each other for DM2 can't boot up issue(only DN15/DQ15)

12

C1401

SCD1U10V2KX-5GP

DY

ST330U2VDM-4-GP

12

TC1401

12

C1402

DY

SC2D2U10V3KX-1GP

12

DY

12

C1414

SC1U6D3V2KX-GP

12/28 Yellow mark for OPI change

12/3 Change DM2 to 62.10024.E21

12/9 Change DM2 to 62.10017.K01

12/21 Change DM2 to 62.10017.P61

12/22 Change DM2 to 62.10024.E21

SA1_DIM1

SA0_DIM1

3D3V_S0

Thermal EVENT

TS#_DIMM0_1

SODIMM A DECOUPLING

12

C1404

C1405

C1403

SC10U6D3V5KX-1GP

12

C1415

SCD1U10V2KX-5GP

C1405

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1416

C1417

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

2

12

2

3D3V_S0

12

R1403

1 2

C1406

SC10U6D3V5KX-1GP

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

12

C1407

DY

11/ 17 Change SMbus adress note

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4 SO-DIMMA TS Address is 0x34

3D3V_S0

12

DY

SC10U6D3V5KX-1GP

C1409

C1408

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

12

C1410

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM2

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

14 105

1

A00

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_BS26

M_A_BS06 M_A_BS16

M_A_DQ[63:0]6

DDR_VREF_S3

R1504

R1504 0R0402-PAD

0R0402-PAD

1 2

12

C C

DDR_VREF_S3

1 2

12

B B

X02-0303 change 0R to short pad

0D75V_S0

12

C1518

DY

SC1U6D3V2KX-GP

A A

M_VREF_CA_DIMM0

12

C1523

C1524

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

R1503

R1503 0R0402-PAD

0R0402-PAD

M_VREF_DQ_DIMM0

12

C1515

C1516

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1519

DY

SC1U6D3V2KX-GP

5

12

C1522

SCD1U10V2KX-5GP

12

C1517

SCD1U10V2KX-5GP

12

C1520

C1521

SC1U6D3V2KX-GP

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#14,37

0D75V_S0

4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

H =9.2mm

4

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-128-GP

62.10024.D51

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1 NP2

CK0

CK1

SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198

199

197 201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM0 SA1_DIM0

3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,65 PCH_SMBCLK 14,20,65

TS#_DIMM0_1 14

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

C1501

1D5V_S3

12

SCD1U10V2KX-5GP

12

C1502

DY

SC2D2U10V3KX-1GP

SODIMM B DECOUPLING

12

C1503

DY

SC10U10V5ZY-1GP

12

C1511

SC1U6D3V2KX-GP

12/7 Change DM1 to 62.10024.D51

12/9 Change DM1 to 62.10017.K11

12/17 Change DM1 to 62.10017.N11

12/21 Change DM1 to 62.10017.Q41

12/22 Change DM1 to 62.10024.D91

12/22 Change DM1 to 62.10024.D51

Note: The symbol DM1 is change value and PN only.

3

2

M_A_DQS#[7:0] 6

M_A_DQS[7:0] 6

SA1_DIM0

SA0_DIM0

12

R1502

R1502 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

12/28 Yellow mark for OPI change

12

C1504

C1505

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1512

C1513

SCD1U10V2KX-5GP

12

DY

12

SCD1U10V2KX-5GP

C1507

C1506

C1514

2

DY

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

11/ 17 Change SMbus adress note

Note: SO-DIMMB SPD Address is 0xA0 SO-DIMMB TS Address is 0x30

SO-DIMMB is placed farther from the Processor than SO-DIMMA

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

1 2

12

C1508

SC10U10V5ZY-1GP

12

C1509

C1510

DY

SC10U6D3V5KX-1GP

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

DDR3-SODIMM1

Enrico Caruso 14

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

15 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 105Wednesday, April 13, 2011

A00

5

D D

4

3

2

1

RN1706

3D3V_S0

1

23

HDMI

4

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

HDMI_PCH_DET 51

HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

4 OF 10

PCH1D

L_BKLT_EN27

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

C C

SRN100KJ-6-GP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

12

R1701

2K37R2F-GP

Place near PCH

X02-0303 change 0R to short pad

LVDS_VDD_EN49

L_BKLT_CTRL49

LVDS_DDC_CLK_R49 LVDS_DDC_DATA_R49

TP1701TPAD14-GP TP1701TPAD14-GP

RN1704

2 3 1

0R4P2R-PAD

RN

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

RN

4

LVDS_VREFH LVDS_VREFL

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

Close to PCH side

PCH_CRT_BLUE PCH_CRT_GREEN PCH_CRT_RED

B B

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

4 5

PCH_CRT_BLUE50 PCH_CRT_GREEN50 PCH_CRT_RED50

11/20 Add C1722~C1724

PCH_CRT_BLUE

C1722

12

SC10P50V2JN-4GP

DY

PCH_CRT_GREEN

C1723

12

SC10P50V2JN-4GP

PCH_CRT_RED

C1724

12

SC10P50V2JN-4GP

11/19 Del R1703~R1705

PCH_CRT_DDCCLK50 PCH_CRT_DDCDATA50

PCH_CRT_HSYNC50 PCH_CRT_VSYNC50

12

R1702

1KR2D-1-GP

Notes: 1K 0.5% 0402.

CHIP RES 1K D 1/16W 0402

DAC_IREF_R

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

PCH1

Digital Display Interface

P/N: ND27V

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J-1-GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (LVDS/CRT/DDI)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

17 105

1

A00

5

4

3

2

1

SSID = PCH

12/2 Net swap for layout

RN1801

D D

3D3V_S0

INT_PIRQB#

INT_PIRQC# INT_PIRQF#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

B B

A A

PLT_RST#5,27,31,65,71,83

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

1 2

DY

1 2

DY

R1802

1KR2J-1-GP

R1803

1KR2J-1-GP

10

INT_PIRQE#INT_PIRQD#

9

INT_PIRQA#

8

INT_PIRQH#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

3D3V_S0

BOOT BIOS Strap

Reserved 01

11

SPI(Default)

CLK_PCI_LPC71

CLK_PCI_KBC27

X02-0303 change 0R to short pad

R1807

1 2

0R0402-PAD

12

R1816

DY

C1801

100KR2J-1-GP

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

5

PCI_PLTRST#

BBS_BIT0 21

DGPU_HOLD_RST# DGPU_PWR_EN#

SRN10KJ-5-GP

DGPU_HOLD_RST#83

DGPU_PWR_EN#93

TP1806TPAD14-GP TP1806TPAD14-GP

SATA_ODD_DA#56

TP1807TPAD14-GP TP1807TPAD14-GP

1

X02-0311 dummy R1804

R1804 22R2J-2-GP

R1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 22R2J-2-GPR1806 22R2J-2-GP

12

EC1801

EC1802

DY

1 2

SC33P50V2JN-3GP

SC4D7P50V2CN-1GP

4

RN1803

1 2 3

3D3V_S0

1

PCH_GPIO53

R1813

1 2

0R0402-PAD

DY

1 2 1 2 1 2

12

EC1803

DY

SC33P50V2JN-3GP

4

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

1 2

DGPU_SELECT#

DGPU_PWR_EN#

TP1801TPAD14-GP TP1801TPAD14-GP

1

TP1802TPAD14-GP TP1802TPAD14-GP

1

KBC CLK EMI

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

BBS_BIT1

PCI_GNT3#

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME#

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

H49 H43

K42 H40

L24

K40 K38

J48

H3

C6

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

RSVD

PCI

PCH1

NVRAM

USB

P/N: ND27V

12/1 Swap net for layout

11/11 change to RN1802 to meet schematic check result.

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

3D3V_S5

PCH_GPIO14 USB_OC#6_7

USB_OC#4_5

3

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

10 9 8 7

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10

AT8

AY5 BA2

AT12 BF3

USB Ext. port 1 (HS) External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14

PCH_GPIO14

C14

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

USB_OC#0_1 USB_OC#12_13USB_OC#10_11 USB_OC#8_9 USB_OC#2_3

3D3V_S5

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

2

USB_PN1 61 USB_PP1 61

USB_PN5 32 USB_PP5 32

USB_PN8 82 USB_PP8 82 USB_PN9 82 USB_PP9 82

USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49

USB_OC#0_1 61

USB_OC#8_9 61CLK_PCI_FB20

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

DMI & FDI Termination Voltage

USB Table

Pair

Wednesday, April 13, 2011

NV_CLE

Danbury Technology: Disabled when Low. Enable when High.

X

0

USB Ext. port 2 (MB)

1

X

2

X

3

X

4

CARD READER

5

X

6

X

7

USB Ext. port 3

8

USB Ext. port 1

9

X

10

Mini Card1 (WLAN+BT)

11

CAMERA

12

X

13

PCH (PCI/USB/NVRAM)

Enrico Caruso 14

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# 5

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

NV_ALE

Device

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 105

1

A00

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500

D D

mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

DY

R1926

12

10KR2J-3-GP

10KR2J-3-GP R1904

R1904

12

100KR2J-1-GP

AC_PRESENT27

XDP_DBRESET#5

SYS_PWROK36

S0_PWR_GOOD27,36

RUNPWROK45,46,47

PM_PWRBTN#27

100KR2J-1-GP

3D3V_S0

C C

PM_DRAM_PWRGD5,37

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

SUS_PWR_ACK27

B B

SYS_PWROK

PWROK

R1924

1 2

0R0402-PAD

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

1 2

X02-0303 change 0R to short pad

R1903

1 2

0R0402-PAD

R1905

1 2

PWROK

MEPWROK

DY

1 2

SYS_RESET#

R1923

0R0402-PAD

R1907

1 2

DY

R1925

1 2

10KR2J-3-GP

0R2J-2-GP

DMI_COMP_R

RBIAS_CPY

0R2J-2-GP

DY

R1906

12

0R0402-PAD

PM_RSMRST#

BATLOW#

PM_RI#

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

SUSACK#SUS_PWR_ACK

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18 BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

DMI

System Power Management

PCH1

P/N: ND27V

3D3V_S5

RN1901

8 7 6

SRN10KJ-6-GP

DY

A A

DY

5

12/2 Swap net for layout

BATLOW#

1

PCH_WAKE#

2

PM_RI#

3

SUS_PWR_ACK

45

R1909

12

10KR2J-3-GP

R1922

12

10KR2J-3-GP

R1920

12

10KR2J-3-GP

R1908

12

10KR2J-3-GP

AC_PRESENT

PM_PWRBTN#

PM_SLP_LAN#

PM_RSMRST#

PCIE_WAKE# CRB : 1K CEKLT: 10K

4

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] 4

FDI_TXP[7:0] 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

R1913

1 2

0R0402-PAD

PM_RSMRST#

R1910

1 2

0R0402-PAD

1 2

R1911 10KR2J-3-GP

DY

TP1901 TPAD14-GPTP1901 TPAD14-GP

1

TP1902 TPAD14-GPTP1902 TPAD14-GP

1

TP1903 TPAD14-GPTP1903 TPAD14-GP

1

TP1904 TPAD14-GPTP1904 TPAD14-GP

H_PM_SYNC 5

1

TP1905 TPAD14-GPTP1905 TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ˉno connectˇ

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RTC_AUX_S5

PCH_WAKE# 27

PM_CLKRUN# 27

PCH_SUSCLK_KBC 27

RSMRST#_KBC 27

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

PM_SLP_S4# 27,46

PM_SLP_S3# 27,36,37,47

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

Enrico Caruso 14

1

RTC_AUX_S5

3D3V_S0

19 105

A00

5

SSID = PCH

D D

PCIE_RXN231

PCIE_RXP231 PCIE_TXN231 PCIE_TXP231

PCIE_RXN465

PCIE_RXP465 PCIE_TXN465 PCIE_TXP465

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

CLK_PCH_48M

EC2001

1 2

DY

SC4D7P50V2CN-1GP

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

12/2 Swap net for layout

RN2001

C C

PCIE_CLK_REQ0#

3D3V_S5

1 2 3 4 5 6

SRN10KJ-L3-GP

CLK_PCIE_WLAN#65 CLK_PCIE_WLAN65

CLK_PCIE_WLAN_REQ#65

12/6 swap net for layout

CLK_PCIE_LAN#31

B B

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2#

CLK_PCIE_LAN31

PCIE_CLK_LAN_REQ#31

RN2018

1 2 3

SRN10KJ-5-GP

PCIE_CLK_REQ2#

4

CLK_PCIE_WLAN_REQ#

Support S0 power only

10

PEG_B_CLKRQ#

9

PCIE_CLK_REQ4#PCIE_CLK_LAN_REQ#

8

CLK_PCIE_REQ7#PCIE_CLK_REQ5#

7

EC_SWI#

PCIE_CLK_REQ0#

RN2012

2 3 1

0R4P2R-PAD

RN

RN2014

1 2 3

0R4P2R-PAD

3D3V_S5

CLK_PCH_SRC1_N

4

PCIE_CLK_REQ2#

RN

4

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

A00-0413 SWAP RN2014 net for layout

PCIE_CLK_REQ4#

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

11/1 Add EC2002~EC2007 for EMI request

A A

CLK_PCIE_WLAN#

SC22P50V2JN-4GP

CLK_PCIE_WLAN

SC22P50V2JN-4GP

CLK_PCIE_LAN

SC22P50V2JN-4GP

CLK_PCIE_LAN#

SC22P50V2JN-4GP

JTAG_TCK_VGA

SC22P50V2JN-4GP

DY

EC2002

12

EC2003

12

EC2004

12

EC2005

12

EC2007

12

5

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

CLK_PCIE_REQ7#

ITPXDP_N

1

ITPXDP_P

1

4

PCH1B

BG34

BJ34 AV32 AU32

BE34

BF34 BB32 AY32

BG36

BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40

BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13

V38 V37

K12

AK14 AK13

COUGAR-GP-U2-NF

Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3



Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2



if more than 2 PCI clocks + PCI loopback are routed.

4

Cougar

PERN1 PERP1

Point

PETN1

W-WAN

PETP1

PERN2 PERP2

LAN

PETN2 PETP2

PERN3 PERP3

Card Reader

PETN3 PETP3

PERN4

WLAN

PERP4 PETN4 PETP4

PERN5 PERP5

USB3.0

PETN5 PETP5

PERN6 PERP6

Intel GBE LAN

PETN6 PETP6

PERN7 PERP7

Dock

PETN7 PETP7

PERN8

NEW CARD

PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

WWAN CLK

WLAN CLK

LAN CLK

USB3.0 CLK

NEWCARD CLK

PCI-E*

CLOCKS

P/N: ND27V

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_PCILOOPBACK

PCH1

FLEX CLOCKS

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

REFCLK14IN

XTAL25_IN

XTAL25_OUT

3

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

PEG_CLKREQ#_R

XCLK_RCOMP

DGPU_PRSNT#

EC_SWI#

SMB_CLK

SMB_DATA

DRAMRST_CNTRL_PCH

SML0_CLK

SML0_DATA

PCH_GPIO74

SML1_CLK

SML1_DATA

CL_CLK

1

CL_DATA

1

CL_RST#

1

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

1 2

90D9R2F-1-GP

JTAG_TCK

CLK_48_USB30

CLK_27M_VGA_R

11/18 Del VGA 27M and change to TP2007

EC_SWI# 27

DRAMRST_CNTRL_PCH 37

SML1_CLK 27,85

SML1_DATA 27,85

TP2001 TPAD14-GPTP2001 TPAD14-GP

TP2002 TPAD14-GPTP2002 TPAD14-GP

TP2003 TPAD14-GPTP2003 TPAD14-GP

R2003

RN

1 2

DY

0R2J-2-GP

RN2016

1 2 3

0R4P2R-PAD

RN2010

2 3 1

0R4P2R-PAD

SRN10KJ-5-GP

12/6 swap net for layout

4

RN

RN2008

2 3 1

4

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N

CLK_PCI_FB 18

CLK_BUF_CKSSCD_P

12/6 swap net for layout

CLK_BUF_EXP_N CLK_BUF_EXP_P

R2007

R2001

R2016

+VCCDIFFCLKN

1 2

22R2J-2-GP

1 2

22R2J-2-GP

1

TP2007 TPAD14-GPTP2007 TPAD14-GP

DY

CLK_BUF_REF14

2

UMA

PEG_CLKREQ#_R

PEG_CLKREQ# 85

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

CLK_EXP_N 5 CLK_EXP_P 5

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

2 3 1

RN2021 SRN10KJ-5-GPRN2021 SRN10KJ-5-GP

2 3 1

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

2 3 1

R2008

1 2

JTAG_TCK_VGA 83,85

CLK_PCH_48M 32

2

3D3V_S5

DIS

SMB_DATA

SMB_CLK

4

10KR2J-3-GP

1

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

2 3 1

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

RN2007

4

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

1

6

2

5

34

Q2001

XTAL25_IN

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

XTAL25_OUT

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

CRB : 1K CEKLT: 10K

PCH_SMBDATA 14,15,65

PCH_SMBCLK 14,15,65

41

X2001

2 3

11/29 change X2001 to 82.30020.D41

X01-0217 change C2008 , C2007 to 15pF

3D3V_S0 3D3V_S0

12

R2012

R2013

UMA

10KR2J-3-GP

12

R2011

R2010

DY

10KR2J-3-GP

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Enrico Caruso 14

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# DGPU_PRSNT#

DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

1

SRN2K2J-1-GP

23

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

SC15P50V2JN-2-GP

XTAL-25MHZ-155-GP

C2007

12

SC15P50V2JN-2-GP

UMA_DIS# 22

20 105

3D3V_S5

A00

5

RTC_AUX_S5

SSID = PCH

2 3

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

12

C2101

SC15P50V2JN-2-GP

HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

C C

X2101

1 4

32

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

RN2102

1 2 3

SRN33J-5-GP-U

R212333R2J-2-GP R212333R2J-2-GP

12

4

HDA_SDOUT

HDA_RST# HDA_BITCLK

Flash Descriptor Security Overide

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

HDA_SDOUT

HDA_SPKR

HDA_SDOUT

HDA_SPKR

+3VS_+1.5VS_HDA_IO

DY

R2102

1 2

1KR2J-1-GP

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106

1 2

1KR2J-1-GP

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

PLL ODVR VOLTAGE

HDA_SYNC

Low = 1.8V (Default) High = 1.5V

11/2 Merge R2122 into Q2101

A A

HDA_CODEC_SYNC29

RUN_ENABLE

HDA_CODEC_SYNC

R2117

100KR2J-1-GP

5

1 2

Q2101

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

1

SRN20KJ-1-GP

SC1U6D3V2KX-GP

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_SYNC_R

R212233R2J-2-GP

12

4

3

X01-0210 Merge R2115 R2116

RN2106

4

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

C2104

GAP-OPEN

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

ME_UNLOCK27

SPI_SI_R27,60

SPI_SO_R27,60

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

1 2

SPI_CLK_R27,60

SPI_CS0#_R27,60

RTC_X1

RTC_X2

RTC_RST#

12

HDA_SDOUT

PCH_GPIO33

1

SRTC_RST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK

HDA_SYNC

HDA_RST#

PCH_JTAG_TCK_BUF

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

12

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

TP2105TPAD14-GP TP2105TPAD14-GP

TP2101TPAD14-GP TP2101TPAD14-GP

TP2102TPAD14-GP TP2102TPAD14-GP

TP2103TPAD14-GP TP2103TPAD14-GP

TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

ER2111 0R0402-PADER2111 0R0402-PAD

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

11/1 Add R2111 for EMI request

11/ 17 change R2111 from 33ohm to 0ohm and change to ER2111

EC2103

R2124

33R2J-2-GP

HDA_SYNC

12

4

DY

1 2

EC2102

SC4D7P50V2CN-1GP

DY

1 2

EC2103

SC4D7P50V2CN-1GP

DY

3

PCH1A

Cougar

RTCX1

Point

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

COUGAR-GP-U2-NF

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2101

1 2

SC4D7P50V2CN-1GP

1 OF 10

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

RTCIHDA

JTAG

PCH1

SPI

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP/GPIO21

SATA1GP/GPIO19

P/N: ND27V

INT_SERIRQ SATA_DET#0

S_GPIO22

PSW_CLR#22

12/6 Separate RN2103 to R2125 and R2126

11/11Remove RN2104 and FP_DET#

1 2 3

2

X01-0208 Add RN2101, R2127 for LPC EA result X01-0210 change RN2101 to RN2104 RN2105

LPC_AD[0..3]

LPC_FRAME# 27,71

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LPC_AD0_R LPC_AD1_R LPC_AD2_R LPC_AD3_R

LPC_FRAME#_R

SATA_TXN0_C SATA_TXP0_C

SATA_TXN4_C SATA_TXP4_C

SATA_DET#0

BBS_BIT0

RN2103

SRN10KJ-5-GP

R2125

1 2

10KR2J-3-GP

R2126

1 2

10KR2J-3-GP

2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

3D3V_S0

4

RN2104 SRN33J-5-GP-URN2104 SRN33J-5-GP-U

2 3 1

RN2105 SRN33J-5-GP-URN2105 SRN33J-5-GP-U

1 2 3

KB_DET# 69

INT_SERIRQ 27

C2111 SCD01U16V2KX-3GPC2111 SCD01U16V2KX-3GP

1 2

C2112 SCD01U16V2KX-3GPC2112 SCD01U16V2KX-3GP

1 2

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

BBS_BIT0 18

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

LPC_AD0 LPC_AD1

4

LPC_AD2

4

LPC_AD3

R2127

12

33R2J-2-GP

C2114SCD01U16V2KX-3GP C2114SCD01U16V2KX-3GP

12

C2113SCD01U16V2KX-3GP C2113SCD01U16V2KX-3GP

12

1 2

SATA_LED# 68

PCH (SPI/RTC/LPC/SATA/IHDA)

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

1

LPC_AD[0..3] 27,71

21 105

1

HDD1

ODD

A00

5

4

3

2

1

SSID = PCH

D D

3D3V_S0

R2202

1 2

100KR2J-1-GP

3D3V_S0

RN2203

2 3 1

4

SRN10KJ-5-GP

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

11/11 Remove R2220 for GPIO48 set to GPO

C C

PCH_TEMP_ALERT#

MFG_MODE

DGPU_HPD_INTR# EC_SCI# EC_SMI#

11/11Remove DBC_EN X01-0211 swap DGPU_HPD_INTR#, EC_SMI# for layout.

B B

12/1 Add R2224 pull high

RTC_SENSE#

PCH_GPIO15

1 2

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

RN2201

1 2 3 4 5

SRN10KJ-6-GP

1 2

R2224 10KR2J-3-GPR2224 10KR2J-3-GP

R2201

1 2

DY

11/ 17 Dummy R2201 because GPIO15 internal PH

H_A20GATE H_RCIN#

8 7 6

1KR2J-1-GP

SATA_ODD_PRSNT#

X02-0303 change 0R to short pad

3D3V_S0

3D3V_S5

11/15 Remove Rn2204

Note: For PCH debug with XDP, need to DUMMY R2218

S_GPIO21

TP2219TPAD14-GP TP2219TPAD14-GP

RTC_SENSE#60

SATA_ODD_PRSNT#56

TPAD14-GP

PSW_CLR#21

TPAD14-GP

GAP-OPEN

21

G2201

S_GPIO PCH_GPIO0

EC_SMI#27

EC_SCI#27

1

DGPU_PWROK86,92,93

TP2214TPAD14-GP TP2214TPAD14-GP

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP

TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

TP2210

TP2212TPAD14-GP TP2212TPAD14-GP

TP2203

TP2213

TP2211TPAD14-GP TP2211TPAD14-GP

RTC_SENSE#

R2213

R2213 0R0402-PAD

0R0402-PAD

1

R2218

1 2

100R2J-2-GP

EC_SMI#

DGPU_HPD_INTR#

EC_SCI#

ICC_EN#

PCH_GPIO15

PCH_GPIO16

12

DGPU_PWROK

PCH_GPIO22

1

PCH_GPIO24

1

PCH_GPIO27

1

PLL_ODVR_EN

PSW_CLR#

PCH_GPIO35

1

DMI_OVRVLTG

FDI_OVRVLTG

MFG_MODE

GFX_CRB_DET

1

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_NCTF_1

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_4

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

UMA_DIS#

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

P4

H_PECI_R

AU16

P5

AY11

PCH_THERMTRIP_R

AY10

INIT3_3V#

T14

AH8

AK11

AH10

TS_VSS

AK10

P37

BG2

3D3V_S0

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

3D3V_S0

C48

D1

D49

E1

E49

F1

F49

R2219

1 2

0R0402-PAD

12

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

GPIO

PCH1

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

P/N: ND27V

ICC_EN#

1

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

DMI_OVRVLTG

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

SATA_ODD_PWRGT 56

UMA_DIS# 20

TP2204

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE 27

H_RCIN# 27

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

DY

R2203

1 2

0R2J-2-GP

H_CPUPWRGD 5,36

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

1KR2J-1-GP

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

H_PECI 5,27

H_THERMTRIP# 5,36,85

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

A A

5

4

PLL ON DIE VR ENABLE

NOTE:This signa l has a weak in ternal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (GPIO/CPU)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

22 105

1

A00

5

1D05V_VTT

(1uFx3)

6A

1.3A(Total current of VCCCORE)

12

C2301

SC10U6D3V3MX-GP

12

C2303

C2302

C2303

SC1U6D3V2KX-GP

SSID = PCH

D D

(10uFx1_0603)

11/18 change capacity to 0603 package

1D05V_VTT

TP2301TPAD14-GP TP2301TPAD14-GP

1D05V_VTT

C C

(1uF x4)

12

C2306

C2305

C2306

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

1

2.925A(Total current of VCCIO)

12

C2307

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

12/28 Yellow mark for OPI change X02-0303

0.266A (Totally VCC3_3 current)

(0.1uF x1)

3D3V_S0

0.159A(Totally current of VCCVRM)

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

1D5V_S0

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

1

0.042A (Totally current of VCCDMI)

4

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

DY

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

3

11/ 17 Add R2301 but dummy it and change L2301 source to 3D3V_DAC_S0

7 OF 10

POWER

Cougar

Cougar Point

Point

CRTLVDS

7 OF 10

VCCADAC

VSSADAC

U48

U47

0.001A

+VCCA_DAC_1_2

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

0.001A

+3VS_VCCA_LVDS

VCC CORE

VCCALVDS

VCCTX_LVDS

VSSALVDS

VCC3_3

VCCVRM

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

0.16A

0.042A

+1.05VS_VCC_DMI

AT20

VCCIO

PCH1

FDI

DMI

NAND / SPI HVCMOS

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

12

0.19A

12

0.02A

12

P/N: ND27V

12

C2314

SCD01U16V2KX-3GP

12

(0.1uFx1)

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2306

1 2

0R0402-PAD

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

R2307

1 2

0R0402-PAD

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2

3D3V_S0

DY

R2301

R2301 0R2J-2-GP

0R2J-2-GP

1 2

L2301

1 2

HCB1608KF-181-GP

12

C2315

SCD1U10V2KX-5GP

12

C2316

SCD01U16V2KX-3GP

3D3V_S0

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

SC10U6D3V3MX-GP

C2318

12

C2317

SCD01U16V2KX-3GP

11/18 change capacity to 0603 package

1D5V_S0

1D05V_VTT

SC10U6D3V3MX-GP

(1uF x1)

1D05V_VTT

(1uFx1) (10uFx1)

1D8V_S0

3D3V_DAC_S0

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

11/2 change R2304, R2305 to 0ohm

X02-0303 change 0R to short pad

change 0R to short pad

(0.1uFx1)

3D3V_S5

(1uFx1)

3D3V_S0

1D8V_S0

(0.01uF x2) (22uF x1)

1

Refer to NPCE795 shared SPI flash architecture

11/3 Add LDO for CRT DAC power

A A

5

4

11/ 17change U2301 Vout power rail and stuff the circuit

5

4

3D3V_DAC_S0

12

C2312

SC1U6D3V2KX-GP

5V_S0

C2311

U2301

1

VIN

12

SC1U10V2KX-1GP

3

2

2nd = 74.09198.G7F

VOUT GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

PCH (POWER1)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

23 105

1

A00

5

4

3

2

1

SSID = PCH

1

DCPSUSBYP

1

(10uFx1)

1

12

DY

C2407

1D5V_S0

(1uFx1)

0.095A

C2415

12

TP2406TPAD14-GP TP2406TPAD14-GP

12

C2418

12

C2421

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

VCCACLK

+VCCPDSW

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2408

SC1U6D3V2KX-GP

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

(1uFx1)

+VCCSST

DCPSUS

1

12

C2422

SCD1U10V2KX-5GP

TP2401TPAD14-GP TP2401TPAD14-GP

0.002A

3D3V_S0

(10uFx1)

D D

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

+V3.3S_VCC_CLKF33

(1uFx1)

12

C2401

SC10U6D3V3MX-GP

C2402

SC1U10V2KX-1GP

3D3V_S5

R2403

1 2

0R0603-PAD

TP2405TPAD14-GP TP2405TPAD14-GP

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

11/18 change capacity to 0603 package

1D05V_VTT

(22uFx2_0603) (1uFx3)

C C

1D05V_VTT

0.08A

L2402

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

0.08A

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

B B

1D05V_VTT

R2404

12

0R0402-PAD

1D05V_VTT

R2405

12

0R0402-PAD

(1uFx1) (220uFx1)

+1.05VS_VCCA_A_DPL

12

C2443

C2443 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

+1.05VS_VCCA_B_DPL

12

C2444

C2444 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

+VCCDIFFCLK

12

C2412

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

C2413

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

12

11/ 17 Change R2406 from close gap to 0ohm

X02-0303 change 0R to short pad

A A

5

12

12/28 Yellow mark for OPI change

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2411

1D05V_VTT

C2411

1D05V_VTT

(0.1uFx2) (4.7uFx1_0603)

RTC_AUX_S5

(0.1uFx2) (1uFx1)

SCD1U10V2KX-5GP

(1uFx1)

C2403

SC4D7U6D3V3KX-GP

1 2

0R0402-PAD

SC1U6D3V2KX-GP

(0.1uFx1)

0.001A

SC4D7U6D3V3KX-GP

1.01A (Total current of VCCASW)

12

R2406

(1uFx1)

C2404

(0.1uFx1)

12

C2406

SC10U6D3V3MX-GP

+VCCRTCEXT

+VCCDIFFCLKN

C2414

C2417

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

0.055A

12

SCD1U10V2KX-5GP

12

6uA

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

CPURTC

PCH1

3

PCI/GPIO/LPCMISC

SATA USB

HDA

P/N: ND27V

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

0.097A (Totally current of VCCSUS3_3)

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

1D05V_VTT

0.01A

C2433

SCD1U10V2KX-5GP

C2433

3D3V_S5

C2428

C2430

C2429

C2432

DY

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

DY

12

C2434

SC10U6D3V5KX-1GP

12

2

C2423

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

C2435

(1uFx1)

SC1U6D3V2KX-GP

(0.1uFx1)

TP2403 TPAD14-GPTP2403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

SC1U6D3V2KX-GP

1D05V_VTT

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

5V_S5

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

83.R0304.A8F

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

10R2J-2-GP

(0.1uFx2)

3D3V_S0

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

+3VS_+1.5VS_HDA_IO

R2409

0R0402-PAD

11/ 17 Change R2409 from close gap to 0ohm

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (POWER2)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

R2407

12

5V_S0

(1uFx1)

24 105

1

3D3V_S5

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

PCH1

P/N: ND27V

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

PCH1

P/N: ND27V

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

25 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Reserved

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

A00

11/17 change R2724 to meet X00 PCB ver

SSID = KBC

3D3V_AUX_KBC

DY

D D

11/16 Add R2728 R2729 for SERIES_ID

3D3V_AUX_KBC

Vostro

C C

11/22 add RTC_AUX_S5 to KBC_GPIO72

X01-0127 Del R2757 to follow standard 10mw circuit

11/1 Add R2777, C2777 for EMI

B B

ROSA Multi GPIO setting

L_BKLT_EN17

X02-0303 change 0R to short pad

R2771

R2771 2D2R3-1-U-GP

2D2R3-1-U-GP

1 2

12

C2701

C2704

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

R2728

R2728 100KR2J-1-GP

100KR2J-1-GP

Ins

SERIES_ID

12

R2729

R2729 100KR2J-1-GP

100KR2J-1-GP

CLK_PCI_KBC

R2777

C2777

VGA_THRM

C2719 SCD1U10V2KX-5GP

1 2

DY

SYS_THRM

C2720

1 2

DY

CPU_THRM

C2721

1 2

DY

KBC_PWRBTN#68

A A

5

11/ 17 change R2702 from close gap to 0ohm

R2702

1 2

0R0603-PAD

SCD1U10V2KX-5GP

12

C2705

DY

EC_AGND

12

DY

22R2J-2-GP

CLK_PCI_KBC_EMI

DY

1 2

SC4D7P50V2CN-1GP

SCD1U10V2KX-5GP

1 2

R2761 0R0402-PADR2761 0R0402-PAD

BAT54CPT-GP

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

12

C2706

C2707

SCD1U10V2KX-5GP

AD_IA40

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

1 2

PSID_EC38

CPU_THRM28

FAN1_DAC28

LCD_TST49

SUS_PWR_ACK19

VGA_THRM28 SYS_THRM28

BATT_WHITE_LED#68

CAP_LED#69

S5_ENABLE36

BAT_IN#39

LID_CLOSE#82

RSMRST#_KBC19

PM_SLP_S4#19,46

ME_UNLOCK21

WIFI_RF_EN65 BLUETOOTH_EN65 S0_PWR_GOOD19,36

USB_PWR_EN#61

AC_PRESENT19

IMVP_PWRGD36,42

11/ 17 add R2774 pull high for LID_CLOSE#

LID_CLOSE#

EC_AGND

PANEL_BLEN

PSL_IN2

1

1 2

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

D2703

2

10mW

1

BAT54CPT-GP

12

C2708

C2709

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

EC_AGND

PCB_VER_AD

SERIES_ID

VGA_THRM

PSL_IN2

MODEL_ID_DET

ECSMI#_KBC

CAP_LED#

RCID38

PSL_IN1 PSL_OUT EC_GPIO72

KBC_VCORF

12

C2712

SC1U10V3ZY-6GP

Very close to EC

3D3V_S5

12

R2774

100KR2J-1-GP

KBC_ON#_R

R2704

330KR2J-L1-GP

3

AC_IN# 40

12

C2710

EC_GPIO72

SCD1U10V2KX-5GP

4

NPCE795PA0DX-GP-U

EC_SWI#20

EC_SCI#22

RN2706

SRN10KJ-5-GP

5

X01-0210 change R2724 to meet X01 PCB ver X02-0314 change R2724 to meet X02 PCB ver

Reserved 0.1uF on all of ADC input pins

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3

96

GPIO4

108

GPIO5

93

GPIO6

94

GPIO7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/TRST#

26

GPIO51

73

GPIO70

74

GPIO71

75

GPIO72

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/TEST#

112

GPO84/XORTR#

107

GPIO97

44

VCORF

EC_SWI#20

EC_SCI#22

3D3V_AUX_S5

1

KBC_ON#_GATE

23

base on NUVOTON feedback list.(C2717~C2721)

VBAT

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

C2722

1 2

SCD1U10V2KX-5GP

12

DY

C2713

SCD1U10V2KX-5GP

Q2706

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00-0413 change R2724 to 47K for PCB ver

115

102

4

VDD

AVCC

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

GND

5

116

R2711

1 2

0R0402-PAD

EC_AGND

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

R2758

1 2

0R0402-PAD

ECSCI#_KBC

R2759

1 2

0R0402-PAD

3D3V_AUX_S5

S

Q2703

G

DMP2130L-7-GP

D

2ND = 84.03413.A31

D

84.02130.031

3D3V_AUX_KBC

S5_ENABLE

D

4

3D3V_S0

12

C2703

DY

C2702

A00-0328

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

change R2735 to 10R and C2711 to 220p

1 OF 2

PLT_RST#_EC

7

LRESET#

2

LCLK

3

LFRAME#

SERIRQ

AGND

103

EC_AGND

F_CS0#

F_SCK

LPC_AD3

1

LAD3

LPC_AD2

128

LAD2

LPC_AD1

127

LAD1

LPC_AD0

126

LAD0

125 8

PANEL_BLEN

9

ECSCI#_KBC

29

KBC_GPIO10

124

ECSWI#_KBC

123 121 122

27

AD_IA_HW2

25 11 10 71 72

70 69 67 68 119

EC_ENABLE#_1

120

PROCHOT_EC

24 28

EC_SPI_CS#_C

90

EC_SPI_CLK_C

92

EC_SPI_DI_C

86

EC_SPI_DO_C

87

NOTE: Locate resistors R2736,R2719 and R2722 close to the NPCE795P.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

PCB_VER_AD

C2717

C2711

1 2

SC220P50V2KX-3GP

R2735

1 2

10R2J-2-GP

LPC_AD[0..3] 21,71

INT_SERIRQ 21 PM_CLKRUN# 19

TP2701 TPAD14-GPTP2701 TPAD14-GP

1

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

AD_IA_HW2 40

PCH_WAKE# 19

TPDATA 69 TPCLK 69

<------ TP

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,85 SML1_DATA 20,85

PM_LAN_ENABLE 31

LCD_TST_EN 49

X02-0309 change 0R to short pad

33R2J-2-GPR2736 33R2J-2-GPR2736

12

33R2J-2-GPR2719 33R2J-2-GPR2719

12

R2737 0R0402-PADR2737 0R0402-PAD

12

R2722 33R2J-2-GPR2722 33R2J-2-GP

12

3D3V_AUX_KBC

12

R2724

R2724 47KR2F-GP

47KR2F-GP

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

DY

SCD1U16V2KX-3GP

EC_AGND

PLT_RST# 5,18,31,65,71,83

CLK_PCI_KBC 18

LPC_FRAME# 21,71

11/19 add TP2701 for KBC_GPIO10

Follow DQ15 change PCIE_RST# to AD_IA_HW2

<------ BATTERY / CHARGER

<------PCH / eDP

SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60

SPI_SI_R 21,60

EC_SPI_DI_C

12

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01

X02

A00

Reserved

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

11/22 change WLAN LED control to KBC

H_PECI5,22

1D05V_VTT

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

12/10 Add R2762 and dummy R2732, Q2702

EC_GPIO47 High Active

Q2702

100KR2J-1-GP

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PROCHOT_EC

12

R2732

DY

R2762

1 2

0R0402-PAD

H_PROCHOT#_EC

D

DY

1 2

R2733 0R0402-PADR2733 0R0402-PAD

PSL SOLUTION 10mW SOLUTION

11/ 17 DY R2734 and stuff R2756 to keep KBC data

EC_GPIO72

R2756

1 2

0R0402-PAD

PSL_IN1AC_OK

R2768

R8909

PWR_CHG_ACOK40

1 2

0R0402-PAD

X01-0208 dummy R2769

1 2

PSL_OUT

G

S

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

R2768

1 2

PSL

0R2J-2-GP

DY

R2767

Q2705

Q2705 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PSL

0R2J-2-GP

D

KBC_ON#_R

DY

4

12

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

AC_IN#_KBC

EC_ENABLE#_1

3

R2734

1 2

DY

R2763

1 2

10mW

1 2

10mW

2N7002K-2-GP

G

S

Q2704

84.2N702.J31

2ND = 84.2N702.031

R2766

CHG_AMBER_LED#68

KBC_WLAN_OUT#68

PCH_SUSCLK_KBC19

H_PROCHOT# 5,40,42

VBACKUP

EC_GPIO72

0R2J-2-GP

PSL_IN1

0R2J-2-GP

10mW

KBC_ON#_RKBC_ON#

0R2J-2-GP

100.0KX00

100.0K

FAN_TACH128

PM_PWRBTN#19

PCIE_WAKE#31 PM_SLP_S3#19,36,37,47

KBC_BEEP29

AD_IA_HW40

PWRLED#68

E51_RxD65

E51_TxD65

AMP_MUTE#29

R2721 43R2J-GPR2721 43R2J-GP

1 2 1 2

R2720 0R0402-PADR2720 0R0402-PAD

Very close to EC

PSL_IN1

PSL_OUT

KBC_ON#

D

C2716

SCD1U10V2KX-5GP

PURE_HW_SHUTDOWN#28,36

31

117

63 64

32

118

62 65 81 66 22 16

85

113 111

30 77

13 12

12

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

U2701B

GPIO56/TA1 GPIO20/TA2 GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO45/E_PWM GPIO40/F_PWM

VCC_POR#

GPIO87/SIN_CR GPO83/SOUT_CR/TRIST#

GPIO55/CLKOUT GPIO00/EXTCLK

PECI VTT

NPCE795PA0DX-GP-U

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K 1.204V

ECRST#

PECI EC_VTT

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

12/22 swap net for layout

AC_IN#_KBC BAT_IN#

S5_ENABLE

EC_ENABLE#_1

ECRST#

12/6 swap net for layout

FAN_TACH128

FAN_TACH1

E51_RxD

BLUETOOTH_EN

11/2 Add MODEL_ID_DET pin for Vostro & Inspron select

KBSOUT15/GPIO61/XOR_OUT

3D3V_AUX_S5

12

2

MODELID

MODEL_ID_DET

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK

KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

2nd = 84.03906.F11

RN2701

4

SRN4K7J-8-GP

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J-3-GPR2712 10KR2J-3-GP

R2708

1 2

R2709

1 2

DY

2

3D3V_AUX_KBC

C2718

1 2

SCD1U10V2KX-5GP

EC_AGND

2 OF 2

KBSOUT3/TDI

KBSOUT7 KBSOUT8

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

Q2701

MMBT3906-7F-GP

B

84.03906.P11

23 1

1 23

1 2 3 45

DY

10KR2J-3-GP

12

R2710

R2710 47KR2F-GP

47KR2F-GP

12

R2739

100KR2F-L1-GP

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

E

C

3D3V_AUX_KBC

3D3V_S0

MODEL_ID_DET(GPIO07)

Reserved

DV15_UMA with HDMI

DV15_UMA without HDMI

DV14_UMA with HDMI

DV14_UMA without HDMI

DV14_DIS(512M) with HDMI

DV14_DIS(512M) without HDMI

DV14_DIS(1G) with HDMI

DV14_DIS(1G) without HDMI

1

100.0K

100.0K 143.0K(64.14335.L0L)

100.0K

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K(64.76825.6DL)

100.0K(64.10035.6DL)

174.0K(74.17435.6DL)

215.0K(64.21535.6DL)100.0K

Notes: The total SPI interface signal between EC and PCH canˇt not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

ECRST#

12

C2715

C2715 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

KCOL[0..16] 69

11/16 Add R2776 for aviod kbc code error

3D3V_AUX_KBC

R2776

PCIE_WAKE#

KROW[0..7] 69

12

DY

100KR2J-1-GP

11/ 17 DY D2705 to meet DN13 result

D2705

EC_SMI#22

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Wednesday, April 13, 2011

Wednesday, April 13, 2011 Date: Sheet of

Date: Sheet of

1

2

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

R2760

EC_SMI#22

1 2

0R0402-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC Nuvoton NPCE795

Enrico Caruso 14

1

DY

ECSMI#_KBC

3

ECSMI#_KBC

27 105

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTOR

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V

1.358V

1.204V

1.048V

A00

5

4

3

2

1

SSID = Thermal

D D

3D3V_S0

12

C2802

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

2ND = 84.03904.P11

3

84.03904.L06

Q2801

DY

PMBS3904-1-GP

R2808

R2808 NTC-100K-8-GP

NTC-100K-8-GP

C C

1

2

THERM_SYS_SHDN#

2.System Sensor, Put on palm rest

SCD1U10V2KX-5GP

P2800_DXP

12

C2806

P2800_DXN

SC470P50V3JN-2GP

1 2

R2811 0R2J-2-GPR2811 0R2J-2-GP

Thermal sensor P2800

3D3V_S0

12

R2803

R2803 107KR2F-GP

107KR2F-GP

DY

87.1 Degree

ADJ

12

R2804

12

C2807

SC2200P50V2KX-2GP

T8_P2800

12

C2805

DY

C2805

SCD1U10V2KX-5GP

DY

226KR2F-GP

Very Close to CPU1

U2801

5

VCC

6

DXP

7

DXN

8

OTZ

P2800EB0-GP

74.02800.B71

1.H/W T8 Shutdown

TDR

TDL

GND

ADJ

12/14 dummy R2803, R2804 and C2805 12/15 Remove 3rd source

Very close to CPU1

11/4 Vendor recommand

X01-0209 dummy U2805 circuit

4 3 2

ADJ

1

SYS_THRM 27 CPU_THRM 27

T8_G709 HYST_PHTHERM_SYS_SHDN#

1 2

DY

R2810 0R2J-2-GP

DY



DY

R2812

24K3R2F-1-GP

R2807

1 2

0R0402-PAD

86.9

R(K )= 0.0012*T^2- 0.9308T+ 96.147



FAN_TACH127

AFTP2801AFTP2801 AFTP2802AFTP2802 AFTP2803AFTP2803

FAN_VCC

1

FAN_TACH1_C

1

GND

1

X02-0309 change AFTP to followDV14 AMD

12/13 change P2800 to ver B

B B

Fan controller P2793

U2802

R2802

1 2

DY

0R2J-2-GP

5V_S0

FAN1_DAC27

0R2J-2-GP

FAN_VCC

*Layout* 10 mil

For linear FAN

3D3V_S0

R2813

1 2

470KR2J-2-GP

DY

U2805

1

SET

2

GND

12

OUT#3HYST

G709T1UF-GP

C2809

SC4D7U6D3V3KX-GP

VCC

DY

FAN_TACH1_C

*Layout* 15 mil

12

21

D2802

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

FON#

5

4

G709_VCCADJ_G709

U2802

1

FON#

2

VIN

3

VO

4

VSET

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

FAN_VCC

12

DY

12

DY

R2805

150R2F-1-GP

12

C2808

C2808 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

C2810

SC2200P50V2KX-2GP

GND GND GND GND

DY

8 7 6 5

R2828

1 2

0R2J-2-GP

FAN1

5 3 2

1 4

FOX-CON3-6-GP-U

20.D0210.103

5V_S0

3D3V_S0

R2809

12

C2803

SC4D7U6D3V3KX-GP

12

C2804

SCD1U10V2KX-5GP

Q2802

PURE_HW_SHUTDOWN#27,36

VGA Thermal sensor P2800

P2800_VGA_DXP85

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

P2800_VGA_DXN85

A A

3D3V_S0

P2800_VGA_DXP

12

DY

P2800_VGA_DXN FAN_VCC

1 2

R2814 0R0402-PADR2814 0R0402-PAD

5

3D3V_S0_thermal

C2812

C2812 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

3D3V_S0_thermal

DY

12

C2814

SCD1U10V2KX-5GP

U2804

5

VCC

6

DXP

7

DY

DXN

8

OTZ

P2800EB0-GP

74.02800.B71

DY

VGA_THRM_TDR

4

TDR

VGA_THRM_TDL

3

TDL

2

GND

1

ADJ

X02-0311 Add R2816& R2817 to option VGA_THRM and DY the circuit

4

DY

R2816 0R2J-2-GP

1 2

R2817 0R2J-2-GP

1 2

DY

11/18 remove R2817, R2818, C2816 and NC U2804 OTZ pin

VGA_THRM 27

12

R2815

R2815 100KR2J-1-GP

100KR2J-1-GP

DY

3

EMI/ESD

12

EC2801

DY

SCD1U16V2KX-3GP

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

2

Date: Sheet of

D

12

C2811

2N7002K-2-GP

DY

84.2N702.J31

2ND = 84.2N702.031

SCD1U10V2KX-5GP

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

THERM_SYS_SHDN#

S

G

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

100KR2J-1-GP

3D3V_S0

28 105

A00

5

SSID = AUDIO

D D

11/ 17 change R2930 to 0ohm and part reference change to ER2930

3D3V_S0

Close to codec

12

C2903

C2904

C2902

1 2

SC1U6D3V2KX-GP

C C

SC1U10V2KX-1GP

B B

C2923

3D3V_S0

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

DY

C2902

1 2

SCD1U10V2KX-5GP

AMP_MUTE#

AUD_VREFOUT_B

HDA_CODEC_BITCLK

12

C2907

C2907 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

HDA_CODEC_SDOUT21 HDA_CODEC_BITCLK21

HDA_SDIN021

HDA_CODEC_SYNC21 HDA_CODEC_RST#21

SCD1U10V2KX-5GP

11/1 Add R2930 for EMI

HDA_CODEC_SDOUT

ER2930 0R0402-PADER2930 0R0402-PAD

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

1 2 1 2

4

AMP_MUTE#27

AMP_MUTE#

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

HDA_CODEC_BITCLK_R

33R2J-2-GPR2901 33R2J-2-GPR2901

HDA_CODEC_SDIN0

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

+PVDD

36

37

38

39

40

41

EAPD

PVDD

PORTD_-R

PORTD_+R

THERMAL_PAD

71.92H87.A03

3

35

PVSS

PORTD_-L

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

+AVDD

AUD_VREG

32

33

34

PVDD

AVDD2

PORTD_+L

31

VREG/+2_5V

CAP+

CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

AUD_AGND

30 29 28

V-

27 26 25 24 23 22 21

AUD_SPK_R+ 58

AUD_SPK_R- 58

AUD_SPK_L- 58

AUD_SPK_L+ 58

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

2

+AVDD

12

C2905

1 2

SC2D2U10V3KX-1GP

1 2

C2906

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

C2914

R2906 60D4R2F-GPR2906 60D4R2F-GP R2905 60D4R2F-GPR2905 60D4R2F-GP

SC1U10V2KX-1GP

AUD_AGND

CLOSE TO CODEC

1 2 1 2

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

Close to codec

5V_S0 +PVDD

R2902

12

0R0603-PAD

AUD_HP1_JACK_R2 82

AUD_HP1_JACK_L2 82

12 12

AUD_AGND

MIC_IN_R 82 MIC_IN_L 82

12

C2908

C2909

1 2

C2909

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

AUD_AGND

1

R2903

12

C2910

R2904

SC10U6D3V5KX-1GP

12

0R0603-PAD

12

0R0603-PAD

5V_S0

11/ 17 Del C2925

AUD_CAP2

AUD_VREFFLT

AUD_V_B

AUD_VREG

12

C2917

AUD_AGND AUD_AGND AUD_AGND AUD_AGND

C2918

SC4D7U6D3V3KX-GP

Close to codec

12

SC10U6D3V5MX-3GP

12

C2915

C2916

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

92HD87B1A5NDGXTBX8-GP

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

AUD_SENSE_B

AUD_SENSE_A

AUD_PC_BEEP

AUD_CAP2

AUD_VREFFLT

INT_MIC

C2924

SC1U10V3KX-3GP

20

AUD_VREFOUT_O

AUD_VREFOUT_B

12

R2920

1 2

2K2R2J-2-GP

INT_MIC_L_R 58,82

Vendor recommand

INT_MIC_L_R

X02-0314 change 0R to short pad

R2911

12

0R0603-PAD

R2914

12

0R0603-PAD

R2917

12

0R0603-PAD

AUD_AGND

MIC IN

120KR2J-L-GP

AUD_PC_BEEP Trace width>15 mils

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

12

SB_SPKR_RAUD_PC_BEEP

KBC_BEEP_R

120KR2J-L-GP

R2909

1 2

R2910 470KR2J-2-GPR2910 470KR2J-2-GP

From PCH

HDA_SPKR 21

KBC_BEEP 27

From EC

Close to Codec

AUD_VREFOUT_B

RN2901

SRN4K7J-8-GP

1

23

4

MIC_IN_R82

MIC_IN_L82

Azalia I/F EMI

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

11/16 Change C2919 to 0402 package

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

AUD_SENSE_A

12

C2919

C2919 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

AUD_AGND

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

+AVDD

AUD_HP1_JD# 82

AUD_SENSE_B

12

EXT_MIC_JD# 82

Close to Pin14

3

12

AUD_AGND

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

1

A00

29 105Wednesday, April 13, 2011

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 105Wednesday, April 13, 2011

A00