Dell 14 N4050 Schematics

5

4

3

2

1

Enrico Caruso 14

D D

Muxless/UMA Schematics Document

Sandy Bridge

Intel PCH

2011-04-07

C C

REV : A00

DY : None Installed UMA: UMA ONLY installed PSL: KBC795 PSL circuit for 10mW solution installed.

B B

10mW: External circuit for 10mW solution installed. DIS: MUXLESS solution installed. Surge: For GO Rural config stuff. GIGA: For GIGA LAN config stuff. HDMI: For HDMI config stuff. DIS_CRT: Pure DIS install

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Cover Page

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

1 105

1

A00

5

##OnMainBoard

VRAM

D D

1GB (128Mx16x4)

512MB (64Mx16x4)

gDDR3 900NHz

88,89,90,91

gDDR3 900MHz

Seymou-XT S3

83.84,85,86,87

C C

CRT

LCD

HDMI

B B

50

49

51

SD/MMC/MS/ MS Pro

CardReader

74

Audio board

Internal Analog MIC

HP1

58

82

MIC IN

2CH SPEAKER

A A

5

58

CRT

LVDS

HDMI

Realtek RTS5138

Azalia CODEC

IDT 92HD87

4

3

Block Diagram (Discrete/UMA co-lay)

4

(Discrete only)

32

29

4

PCIe x 8

FDIx4x2

USB2.0

AZALIA

24MHz

Intel CPU

Sandy Bridge

4,5,6,7,8,9,10

DMIx4 1GB/s

Intel

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

LPC I/F

ACPI 1.1

17,18,19,20,21,22,23,24,25

SATA

3Gbps

ODDHDD

Flash ROM

5656

SPI

4MB

DDRIII 1066/1333 Channel A

DDRIII 1066/1333 Channel B

PCIE

100MHz

2.5Gbps

USB 2.0

480Mbps

LPC Bus

33MHz

60

3

Project code: 91.4IU01.001 PCB P/N : 48.4IU16.0SC Revision : 10315-SC

PCIE x 1

Touch PAD

DDRIII 1066/1333

10/100 /1000 LOM

Realtek RTL8111E (Giga LAN)

Realtek RTL8105E (10M/100M)

KBC

NUVOTON

NPCE795BA0DX

PS/2 PS/2

Int. KB

6969

2

USB 2.0 x 1

USB 2.0 x 2

27

2

Slot 0

15

Slot 1

14

31

USB 2.0 x 1

Thermal

ENE P2800

ENE P2793 Fan

28

1

SYSTEM DC/DC

APL5916

INPUTS

DCBATOUT

OUTPUTS

0D85V_S0

48

CPU DC/DC

VT1316+1314

INPUTS

DCBATOUT

OUTPUTS

VCC_CORE

SYSTEM DC/DC

TPS51218

INPUTS

DCBATOUT

OUTPUTS

1D05V_VTT

SYSTEM DC/DC

TPS51125

INPUTS

DCBATOUT 5V_S5

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

SYSTEM DC/DC

RJ45 CONN

Mini-Card

802.11a/b/g

WLAN+BT3.0

TPS51216R

INPUTS

DCBATOUT

59

GFX DC/DC

VT1316+1317

INPUTS

64

DCBATOUT

INPUTS

DCBATOUT

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

VCC_GFXCORE

VGA

RT8208B

OUTPUTS

VGA_CORE

TI CHARGER

BQ24707

CAMERA

M/B USB x1 (Left)

I/O board USB x2 (Right)

28

Title

Size Document Number Rev

A3

Date: Sheet of

49

61

82

Block Diagram

Enrico Caruso 14

INPUTS

+DC_IN_S5

SYSTEM DC/DC

INPUTS

3D3V_S5

SYSTEM DC/DC

INPUTS OUTPUTS

1D5V_S3 1V_VGA_S0

3D3V_S0

INPUTS OUTPUTS

1D5V_S3 5V_S5

PCB LAYER

L1:Top L2:GND L3:Signal

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

OUTPUTS

APW7153B

OUTPUTS

G9731

Switches

L4:Signal L5:VCC L6:Bottom

2 105Wednesday, April 13, 2011

42~44

40

DCBATOUT+PBATT

1D8V_S0

1D8V_VGA_S0

1D5V_S0 5V_S0 3D3V_S03D3V_S5

A00

45

41

46

44

92

47

93

A

PCH Strapping

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55

4 4

GNT2#/GPIO53 GNT1#/GPIO51

SPI_MOSI

NV_ALE

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Connect to Vcc3_3 with 8.2-k

No Reboot Mode with TCO Disabled:

- 10-k weak pull-up resistor.



GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Enable Danbury:

Disable Danbury:

Huron River Schematic Checklist Rev.0_7

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

B



C

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

PCI-Express Static Lane Reversal

CFG[4]

CFG[6:5]

CFG[7]

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded DisplayPort.

Enabled - An external Display Port device is

0:

connectd to the EMBEDDED display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

D

Huron River Schematic Checklist Rev.0_7

Default Value

1

0

11

1

E

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.

HAD_DOCK_EN# /GPIO[33]

3 3

High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

GPIO15

GPIO8

2 2

GPIO27

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality

Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE 1D8V_VGA_S0 3D3V_VGA_S0 1V_VGA_S0

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

1.8V

3.3V 1V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

Voltage Rails

ACTIVE IN

S0

CPU Core Rail Graphics Core Rail

S3

AC Brick Mode only

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

N/A

USB Table

Pair

0

1

2

3

4

5

6

7

1 1

8

9

10

11

12

13

Device

X

USB Ext. port 2 (MB)

X

CARD READER

X

USB Ext. port 3

USB Ext. port 1

X

Mini Card1 (WLAN+BT)

CAMERA

X

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery CHARGER

EC SMBus 2 PCH eDP

PCH SMBus SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot G-Sensor MINI

HURON RIVER ORB

Address Hex Bus Ref Des

BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA BAT_SCL/BAT_SDA

SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

PCIE Routing

LANE1 X

LANE2

LANE3 X

LANE5

LANE6

LANE7

LANE8 X

LAN

WirelessLANE4

X

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Table of Content

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

3 105

A00

5

4

3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN[3:0]19

DMI_TXP[3:0]19

DMI_RXN[3:0]19

DMI_RXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019 FDI_FSYNC119

FDI_INT19

FDI_LSYNC019 FDI_LSYNC119

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

R403

1 2

10KR2J-3-GP

DY

Stuff to disable internal graphics function for power saving.

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

eDP_HPD

NOTE: Select a Fast FET similar to 2N7002E whose rise/ fall time is less than 6 ns. If HPD on eDP interface is disabled, connect it to CPU VCCIO via a 10-k pull-Up resistor on the motherboard.

B27 B25 A25 B24

B28 B26 A24 B23

G21 E22 F21 D21

G22 D22 F20 C21

A21 H19 E19 F18 B21 C20 D18 E17

A22 G19 E20 G18 B20 C19 D19 F17

J18 J17

H20

J19

H17

A18 A17 B16

C15 D15

C17 F16 C16 G15

C18 E16 D16 F15

SANDY

62.10055.421

2nd = 62.10040.771

SANDY

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX#0 FDI0_TX#1 FDI0_TX#2 FDI0_TX#3 FDI1_TX#0 FDI1_TX#1 FDI1_TX#2 FDI1_TX#3

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3 FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI0_LSYNC FDI1_LSYNC

EDP_COMPIO EDP_ICOMPO EDP_HPD

EDP_AUX EDP_AUX#

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_TX#0 EDP_TX#1 EDP_TX#2 EDP_TX#3

SKT-BGA989C470395-1H180

DMI

Intel(R) FDI

eDP



CPU1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11

PCI EXPRESS* - GRAPHICS

PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

1 OF 9

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_IRCOMP_R

PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN7 83 PEG_RXN6 83 PEG_RXN5 83 PEG_RXN4 83 PEG_RXN3 83 PEG_RXN2 83 PEG_RXN1 83 PEG_RXN0 83

PEG_RXP7 83 PEG_RXP6 83 PEG_RXP5 83 PEG_RXP4 83 PEG_RXP3 83 PEG_RXP2 83 PEG_RXP1 83 PEG_RXP0 83

C409 SCD22U10V2KX-1GP

1 2

DIS

C410 SCD22U10V2KX-1GP

1 2

DIS

C411 SCD22U10V2KX-1GP

1 2

DIS

C412 SCD22U10V2KX-1GP

1 2

DIS

C413 SCD22U10V2KX-1GP

1 2

DIS

C414 SCD22U10V2KX-1GP

1 2

DIS

C415 SCD22U10V2KX-1GP

1 2

DIS

C416 SCD22U10V2KX-1GP

1 2

DIS

C425 SCD22U10V2KX-1GP

1 2

DIS

C426 SCD22U10V2KX-1GP

1 2

DIS

C427 SCD22U10V2KX-1GP

1 2

DIS

C428 SCD22U10V2KX-1GP

1 2

DIS

C429 SCD22U10V2KX-1GP

1 2

DIS

C430 SCD22U10V2KX-1GP

1 2

DIS

C431 SCD22U10V2KX-1GP

1 2

DIS

C432 SCD22U10V2KX-1GP

1 2

DIS

A A

1D05V_VTT

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG Static Lane Reversal

PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

PEG_TXN7 83 PEG_TXN6 83 PEG_TXN5 83 PEG_TXN4 83 PEG_TXN3 83 PEG_TXN2 83 PEG_TXN1 83 PEG_TXN0 83

PEG_TXP7 83 PEG_TXP6 83 PEG_TXP5 83 PEG_TXP4 83 PEG_TXP3 83 PEG_TXP2 83 PEG_TXP1 83 PEG_TXP0 83

CPU (PCIE/DMI/FDI)

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

4 105

A00

SSID = CPU

5

H_THERMTRIP#22,36,85

H_CPUPWRGD22,36

PM_DRAM_PWRGD19,37

VDDPWRGOOD37

1 2

1K5R2F-2-GP

H_SNB_IVB#18

1

TP501TPAD14-GP TP501TPAD14-GP

1

TP502TPAD14-GP TP502TPAD14-GP

H_PECI22,27

R513

10KR2J-3-GP

R509

R509 750R2F-GP

750R2F-GP

1 2

56R2J-4-GP

R504

1 2

C504

R505

1 2

DY

H_CPUPWRGD_R

1 2

0R2J-2-GP

12

H_PROCHOT#27,40,42

H_PM_SYNC19

R503

1 2

12

1D05V_VTT

R501

1 2

62R2J-GP

D D

62R2J-GP

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

CRB : 47pf CEKLT:43pf

Connect EC to PROCHOT# through inverting OD buffer.

X01-0127 Add C504 for noise couple.

C C

R510

PLT_RST#18,27,31,65,71,83

R510

4

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

0R0402-PAD

SCD1U10V2KX-5GP

VDDPWRGOOD

BUF_CPU_RST#

C501

C501 SC220P50V2KX-3GP

SC220P50V2KX-3GP

CPU1B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

SANDY

62.10055.421

2nd = 62.10040.771

SANDY

MISCTHERMALPWR MANAGEMENT

CPU1

SKT-BGA989C470395-1H180

3

2 OF 9

A28

BCLK

A27

BCLK#

PRDY# PREQ#

TCK TMS

TRST#

TDI

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

A16 A15

R8

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

DDR3

MISC

DDR3

MISC

JTAG & BPM

2

CLK_EXP_P 20 CLK_EXP_N 20

RN502

CLK_DP_P_R CLK_DP_N_RH_PROCHOT#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

RN502

4

R502

1 2

1 23

SRN1KJ-7-GP

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1

TP511 TPAD14-GPTP511 TPAD14-GP

1

TP512 TPAD14-GPTP512 TPAD14-GP

1 1 1 1 1 1 1 1

1D05V_VTT

X01-0210 MergeR512 R514

SM_DRAMRST# 37

11/16 remove TP for layout space

TP503 TPAD14-GPTP503 TPAD14-GP TP504 TPAD14-GPTP504 TPAD14-GP TP505 TPAD14-GPTP505 TPAD14-GP TP506 TPAD14-GPTP506 TPAD14-GP TP507 TPAD14-GPTP507 TPAD14-GP TP508 TPAD14-GPTP508 TPAD14-GP TP509 TPAD14-GPTP509 TPAD14-GP TP510 TPAD14-GPTP510 TPAD14-GP

1

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

12/6 swap net for layout

RN501

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

1D05V_VTT

3D3V_S0

XDP_DBRESET#19

XDP_DBRESET#

1 2

R516

R516 10KR2J-3-GP

10KR2J-3-GP

B B

1D05V_VTT

12

R518

DY

75R2J-1-GP

Buffered reset to CPU

PLT_RST#18,27,31,65,71,83

U501

1

IN B

VCC

2

IN A

DY

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

75R2J-1-GP

5

4

A A

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

DY

12

R515

R515 0R2J-2-GP

0R2J-2-GP

BUF_CPU_RST#BUFO_CPU_RST#

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

CPU (THERMAL/CLOCK/PM )

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

5 105

A00

5

4

3

2

1

SSID = CPU

3 OF 9

CPU1C

SANDY

M_A_DQ[63:0]15 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ[63:0]

M_A_BS015 M_A_BS115 M_A_BS215

M_A_CAS#15 M_A_RAS#15 M_A_WE#15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5

AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

C5

SA_DQ0

D5

SA_DQ1

D3

SA_DQ2

D2

SA_DQ3

D6

SA_DQ4

C6

SA_DQ5

C2

SA_DQ6

C3

SA_DQ7

F10

SA_DQ8

F8

SA_DQ9 SA_DQ10

G9

SA_DQ11

F9

SA_DQ12

F7

SA_DQ13

G8

SA_DQ14

G7

SA_DQ15

K4

SA_DQ16

K5

SA_DQ17

K1

SA_DQ18

J1

SA_DQ19

J5

SA_DQ20

J4

SA_DQ21

J2

SA_DQ22

K2

SA_DQ23

M8

SA_DQ24 SA_DQ25

N8

SA_DQ26

N7

SA_DQ27 SA_DQ28

M9

SA_DQ29

N9

SA_DQ30

M7

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37

AJ5

SA_DQ38

AJ6

SA_DQ39

AJ8

SA_DQ40 SA_DQ41

AJ9

SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55

V6

SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

CPU1

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CLK2

SA_CLK#2

SA_CKE2

SA_CLK3

SA_CLK#3

SA_CKE3

SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3

SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 15 M_A_DIM0_CLK_DDR#0 15 M_A_DIM0_CKE0 15

M_A_DIM0_CLK_DDR1 15 M_A_DIM0_CLK_DDR#1 15 M_A_DIM0_CKE1 15

M_A_DIM0_CS#0 15 M_A_DIM0_CS#1 15

M_A_DIM0_ODT0 15 M_A_DIM0_ODT1 15

M_A_DQS#[7:0] 15

M_A_DQS[7:0] 15

M_A_A[15:0] 15

M_B_DQ[63:0]

M_B_BS014 M_B_BS114 M_B_BS214

M_B_CAS#14 M_B_RAS#14 M_B_WE#14

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12

AH12

AT11 AN14 AR14

AT14

AT12 AN15 AR15

AT15

AA9 AA7

AA10

AB8 AB9

CPU1D

SANDY

C9

SB_DQ0

A7

SB_DQ1 SB_DQ2

C8

SB_DQ3

A9

SB_DQ4

A8

SB_DQ5

D9

SB_DQ6

D8

SB_DQ7

G4

SB_DQ8

F4

SB_DQ9

F1

SB_DQ10

G1

SB_DQ11

G5

SB_DQ12

F5

SB_DQ13

F2

SB_DQ14

G2

SB_DQ15

J7

SB_DQ16

J8

SB_DQ17 SB_DQ18

K9

SB_DQ19

J9

SB_DQ20

J10

SB_DQ21

K8

SB_DQ22

K7

SB_DQ23

M5

SB_DQ24

N4

SB_DQ25

N2

SB_DQ26

N1

SB_DQ27

M4

SB_DQ28

N5

SB_DQ29

M2

SB_DQ30

M1

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54

R6

SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

CPU1

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CLK2

SB_CLK#2

SB_CKE2

SB_CLK3

SB_CLK#3

SB_CKE3

SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3

SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 14 M_B_DIM0_CLK_DDR#0 14 M_B_DIM0_CKE0 14

M_B_DIM0_CLK_DDR1 14 M_B_DIM0_CLK_DDR#1 14 M_B_DIM0_CKE1 14

M_B_DIM0_CS#0 14 M_B_DIM0_CS#1 14

M_B_DIM0_ODT0 14 M_B_DIM0_ODT1 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

SANDY

62.10055.421

2nd = 62.10040.771

A A

5

4

3

SANDY

62.10055.421

2nd = 62.10040.771

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (DDR)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

6 105

1

A00

5

4

3

2

1

SSID = CPU

5 OF 9

CPU1E

11/17 remove TP715

AK28

CFG0

AK29

D D

CFG2

CFG4 CFG5 CFG6 CFG7

AL26 AL27

AK26

AL29

AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

SANDY

5 OF 9

RSVD#L7 RSVD#AG7 RSVD#AE7 RSVD#AK2

RSVD#W8

RSVD#AT26

RSVD#AM33

RSVD#AJ27

RSVD#T8

RSVD#J16 RSVD#H16

RSVD#G16

L7 AG7 AE7 AK2 W8

AT26 AM33 AJ27

T8 J16 H16 G16

CFG2

CFG4

DIS

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

PEG Static Lane Reversal

CFG2

11/17 change R703 to 1K but dummy

Display Port Presence Strap

CFG4

DY

12

R703

R703 1KR2F-3-GP

1KR2F-3-GP

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

RSVD#B34 RSVD#A33 RSVD#A34 RSVD#B35 RSVD#C35

RSVD#AT2 RSVD#AT1 RSVD#AR1

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AH27

0702 Modify

TP713

AN35

TP714

AM35

AT2 AT1 AR1

CFG5

CFG6

CFG7

1

TP713 TPAD14-GPTP713 TPAD14-GP

1

TP714 TPAD14-GPTP714 TPAD14-GP

DY

12

R701

1KR2J-1-GP

DY

12

R704

1KR2J-1-GP

R705

R705 1KR2J-1-GP

1KR2J-1-GP

PCIE Port Bifurcation Straps

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

AJ31

RSVD#AJ31

AH31

RSVD#AH31

AJ33

RSVD#AJ33

AH33

RSVD#AH33

AJ26

M3 - Processor Generated SO-DIMM VREF_DQ

DY

C C

M_VREF_DQ_DIMM0 M_VREF_DQ_DIMM1

M_VREF_CA_DIMM0

M_VREF_CA_DIMM1

R707 0R2J-2-GP

R706 0R2J-2-GP

DY

R708 0R2J-2-GP

1 2

DY

R709 0R2J-2-GP

1 2

DY

1 2

DY

M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C

R711

1KR2F-3-GP

20 mils

R710 0R2J-2-GP

1 2

DY

B B

B4:VREF_DQ CHA

D1:VREF_DQ CHB

12

R712

1KR2F-3-GP

H_VCCP_SEL

RSVD#AJ26

B4

RSVD#B4

D1

RSVD#D1

F25

RSVD#F25

F24

RSVD#F24

F23

RSVD#F23

D24

RSVD#D24

G25

RSVD#G25

G24

RSVD#G24

E23

RSVD#E23

D23

RSVD#D23

C30

RSVD#C30

A31

RSVD#A31

B30

RSVD#B30

B29

RSVD#B29

D30

RSVD#D30

B31

RSVD#B31

A30

RSVD#A30

C29

RSVD#C29

J20

RSVD#J20

B18

RSVD#B18

A19

RSVD#A19

J15

RSVD#J15

SANDY

SKT-BGA989C470395-1H180

62.10055.421

2nd = 62.10040.771

CPU1

RSVD#AR35

RSVD#AT34 RSVD#AT33

RSVD#AP35

RSVD#AR34

RESERVED

RSVD#AJ32

RSVD#AK32

RSVD#AH27

RSVD#AN35 RSVD#AM35

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (RESERVED)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

7 105

1

A00

5

SSID = CPU

D D

PROCESSOR CORE POWER

VCC_CORE

C C

B B

A A

DY

12

C820

53A

C801

SC4D7U6D3V3KX-GP

11/15 change Caps to 78.22610.51L

12

SC22U4V3MX-GP

DY

12

C804

C803

C802

SC10U6D3V5KX-1GP

12

C819

C818

SC22U6D3V5MX-2GP

SC4D7U6D3V3KX-GP

12

C807

C806

SC22U6D3V5MX-2GP

12

C812

C817

SC22U4V3MX-GP

12/23 stuff the capacities

SC22U6D3V5MX-2GP

12

C811

SC22U6D3V5MX-2GP

12/28 Yellow mark for OPI change

12

C816

C821

SC22U6D3V5MX-2GP

12

C837

C836

SC22U6D3V5MX-L2GP

12

C822

SC22U6D3V5MX-2GP

12

C835

SC22U6D3V5MX-2GP

VCC Output Decoupling Recommendation: 4 x 470 uF at Bottom Socket Edge 8 x 22 uF at Top Socket Cavity 8 x 22 uF at Top Socket Edge 8 x 22 uF at Bottom Socket Cavity

12

C823

C824

SC22U6D3V5MX-2GP

12

SC22U6D3V5MX-2GP

C833

C834

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

12

C825

SC22U6D3V5MX-2GP

12

C831

C832

SC22U6D3V5MX-2GP

11/4 add Caps to 28 location as vendor recommand.

X01-0127 Stuff C812, C822, C831, C834 for VCC core noise issue.

X01-0217 Stuff C801=22uF change C817 to 22uF

5

C826

SC22U6D3V5MX-L2GP

SC22U6D3V5MX-2GP

4

POWER

CPU1F

VCC_CORE

AG35

VCC

AG34

VCC

AG33

VCC

AG32

VCC

AG31

VCC

AG30

VCC

AG29

VCC

AG28

VCC

AG27

VCC

AG26

VCC

AF35

VCC

AF34

VCC

AF33

VCC

AF32

VCC

AF31

VCC

AF30

VCC

AF29

VCC

AF28

VCC

AF27

VCC

AF26

VCC

AD35

VCC

AD34

VCC

AD33

VCC

AD32

VCC

AD31

VCC

AD30

VCC

AD29

VCC

AD28

VCC

AD27

VCC

AD26

VCC

AC35

VCC

AC34

VCC

AC33

VCC

AC32

VCC

AC31

VCC

AC30

VCC

AC29

VCC

AC28

VCC

AC27

VCC

AC26

VCC

AA35

VCC

AA34

VCC

AA33

VCC

AA32

VCC

AA31

VCC

AA30

VCC

AA29

VCC

AA28

VCC

AA27

VCC

12

C827

SC22U6D3V5MX-2GP

12

C828

SC22U6D3V5MX-2GP

4

AA26

VCC

Y35

VCC

Y34

VCC

Y33

VCC

Y32

VCC

Y31

VCC

Y30

VCC

Y29

VCC

Y28

VCC

Y27

VCC

Y26

VCC

V35

VCC

V34

VCC

V33

VCC

V32

VCC

V31

VCC

V30

VCC

V29

VCC

V28

VCC

V27

VCC

V26

VCC

U35

VCC

U34

VCC

U33

VCC

U32

VCC

U31

VCC

U30

VCC

U29

VCC

U28

VCC

U27

VCC

U26

VCC

R35

VCC

R34

VCC

R33

VCC

R32

VCC

R31

VCC

R30

VCC

R29

VCC

R28

VCC

R27

VCC

R26

VCC

P35

VCC

P34

VCC

P33

VCC

P32

VCC

P31

VCC

P30

VCC

P29

VCC

P28

VCC

P27

VCC

P26

VCC

SANDY

62.10055.421

2nd = 62.10040.771

POWER

SANDY

CORE SUPPLY

CPU1

3

6 OF 9

AH13

VCCIO

AH10

VCCIO

AG10

VCCIO

AC10

VCCIO

Y10

VCCIO

U10

VCCIO

P10

VCCIO

L10

VCCIO

J14

VCCIO

J13

VCCIO

J12

VCCIO

J11

VCCIO

H14

VCCIO

H12

VCCIO

H11

VCCIO

G14

VCCIO

G13

VCCIO

G12

VCCIO

F14

VCCIO

F13

VCCIO

F12

VCCIO

F11

VCCIO

E14

VCCIO

E12

VCCIO

E11

VCCIO

D14

VCCIO

D13

VCCIO

D12

VCCIO

D11

VCCIO

C14

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO

VIDALERT#

VIDSCLK

VIDSOUT

C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

PEG AND DDR

VCC_SENSE

VSS_SENSE

VCCIO_SENSE VSSIO_SENSE

SENSE LINES SVID

3

2

VCCIO Output Decoupling Recommendation: 2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12/28 Yellow mark for OPI change

PROCESSOR VCCIO: 8.5A

12

C805

SC4D7U6D3V3KX-GP

DY

12

C809

C808

SC10U6D3V5KX-1GP

SC10U6D3V3MX-GP

12/23 stuff the capacities

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

12

C829

SC10U6D3V5KX-1GP

12

C842

C830

SC22U6D3V5MX-2GP

11/16 follow DN13 to meet schematic check list

These resistors need to close to power IC

11/17 change part refernce R807 to R805

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R803 43R2J-GPR803 43R2J-GP

1 2

VCCIO_SENSE 45 VSSIO_SENSE 45

2

VR_SVID_ALERT# 42

H_CPU_SVIDCLK 42

H_CPU_SVIDDAT 42

VCC_CORE

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

1

1D05V_VTT

12

DY

12

SC10U6D3V5KX-1GP

VR_SVID_ALERT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

C839

C838

SC10U6D3V5KX-1GP

1D05V_VTT

12

C844

C843

SC10U6D3V5KX-1GP

R805 75R2J-1-GPR805 75R2J-1-GP

R806 54D9R2F-L1-GP

R804 130R2F-1-GPR804 130R2F-1-GP

VCCSENSE 42 VSSSENSE 42

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

12

1 2

C841

C840

SC10U6D3V5KX-1GP

C845

SC22U6D3V5MX-2GP

1D05V_VTT

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VCC_CORE)

Enrico Caruso 14

1

8 105

A00

5

VAXG Output Decoupling Recommendation:

SSID = CPU

VCC_GFXCORE

D D

2 x 470 uF at Bottom Socket Edge 2 x 22 uF at Top Socket Cavity 4 x 22 uF at Top Socket Edge 2 x 22 uF at Bottom Socket Cavity 4 x 22 uF at Bottom Socket Edge

12

C902

C901

SC4D7U6D3V5KX-3GP

SC10U6D3V5KX-1GP

12/28 Yellow mark for OPI

12

C908

SC4D7U6D3V3KX-GP

C C

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating)

B B

if the VR is stuffed

1D8V_S0

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

4

PROCESSOR VAXG: 33A

12

C904

SC10U6D3V5KX-1GP

DY

12

C922

SC1U10V2KX-1GP

12

C906

C905

DY

SC10U6D3V5KX-1GP

12

C920

C921

SC4D7U6D3V3KX-GP

C924

SC1U10V2KX-1GP

3

POWER

CPU1G

AT24

VAXG

AT23

VAXG

AT21

VAXG

AT20

VAXG

AT18

VAXG

AT17

VAXG

AR24

VAXG

AR23

VAXG

AR21

VAXG

AR20

SC10U6D3V5KX-1GP

SC4D7U6D3V3KX-GP

AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AL24 AL23 AL21 AL20 AL18

AL17 AK24 AK23 AK21 AK20 AK18 AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17 AH24 AH23 AH21 AH20 AH18 AH17

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

POWER

SANDY

GRAPHICS

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

7 OF 9

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK35 AK34

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power reduction implementation.

+V_SM_VREF_CNT should have 10 mil trace width

+V_SM_VREF_CNT

AL1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

PROCESSOR VDDQ: 10A

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

12

C909

DY

12/28 Yellow mark for OPI

PROCESSOR VCCSA: 6A

12

C916

M27 M26 L26 J26 J25 J24 H26 H25

2

VCC_AXG_SENSE 42 VSS_AXG_SENSE 42

12

C910

DY

SC10U6D3V3MX-GP

0D85V_S0

12

C915

SC10U6D3V5KX-1GP

VCC_AXG_SENSE VSS_AXG_SENSE

+V_SM_VREF_CNT 37

1D5V_S0

12

C911

SC10U6D3V3MX-GP

12

C917

SC10U6D3V5KX-1GP

12

C912

SC4D7U6D3V5KX-3GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

12

DY

EC902

VCCSA Output Decoupling Recommendation: 1 x 330 uF 2 x 10 uF at Bottom Socket Cavity 1 x 10 uF at Bottom Socket Edge

C914

C913

2nd = 77.C3371.13L

SCD1U50V3KX-GP

TC901

ST330U2VDM-4-GP

SC10U6D3V5KX-1GP

79.33719.20L

VCC_GFXCORE

12

DY

C907

12

R906

R906 100R2F-L1-GP-U

100R2F-L1-GP-U

12

R907

R907 100R2F-L1-GP-U

100R2F-L1-GP-U

12

DY

C918

SCD1U10V2KX-5GP

1

12

DY

C919

SCD1U10V2KX-5GP

1D5V_S3

12

DY

C925

SCD1U10V2KX-5GP

11/16 Follow Annie team's schematic by power solution

B6

VCCPLL

A6

VCCPLL

A2

VCCPLL

SANDY

62.10055.421

2nd = 62.10040.771

VCCSA_SENSE

CPU1

1.8V RAIL

FC_C22

VCCSA_VID1

H23

C22 C24

VCCSA_SENSE

H_FC_C22 VCCSA_SEL

R910

1 2

10R2J-2-GP

4

RN901

DY

SRN1KJ-7-GP

1

2 3

0D85V_S0

R910 close to pin H23.

VCCSA_SEL 48

11/ 17 dummy RN901

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CPU (VCC_GFXCORE)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

9 105

1

A00

5

4

3

2

1

SSID = CPU

8 OF 9

CPU1H

AT35

VSS

AT32

VSS

AT29

VSS

AT27

VSS

AT25

VSS

AT22

VSS

D D

C C

B B

AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

CPU1

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31

F34 F31 F29

CPU1I

SANDY

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

P9

VSS

P8

VSS

P6

VSS

P5

VSS

P3

VSS

P2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L9

VSS

L8

VSS

L6

VSS

L5

VSS

L4

VSS

L3

VSS

L2

VSS

L1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H9

VSS

H8

VSS

H7

VSS

H6

VSS

H5

VSS

H4

VSS

H3

VSS

H2

VSS

H1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SANDY

VSS

CPU1

9 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SANDY

62.10055.421

2nd = 62.10040.771

A A

5

4

3

SANDY

62.10055.421

2nd = 62.10040.771

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

CPU (VSS)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

10 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

XDP

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

11 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

12 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

13 105Wednesday, April 13, 2011

A00

5

SSID = MEMORY

M_B_A[15:0] 6

DDR_VREF_S3

R1405

R1405 0R0402-PAD

D D

C C

X02-0303 change 0R to short pad

B B

A A

0R0402-PAD

1 2

12

C1423

DDR_VREF_S3

R1404

R1404 0R0402-PAD

0R0402-PAD

1 2

12

C1411

0D75V_S0

12

DY

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

C1419

DY

SC1U6D3V2KX-GP

M_VREF_CA_DIMM1

12

C1425

C1424

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

M_VREF_DQ_DIMM1

12

C1412

C1413

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1421

C1420

SC1U6D3V2KX-GP

5

DY

12

C1422

DY

SC1U6D3V2KX-GP

M_B_BS26

M_B_BS06 M_B_BS16

M_B_DQ[63:0]6

12

C1418

SC10U6D3V5KX-1GP

M_B_DIM0_ODT06 M_B_DIM0_ODT16

M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1

DDR3_DRAMRST#15,37

M_B_DQS#[7:0] 6

M_B_DQS[7:0] 6

0D75V_S0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H =5.2mm

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-135-GP

62.10024.E21

NP1 NP2

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0

CK0#

CK1

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

SCL

EVENT#

VDDSPD

SA0 SA1

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198

199

197 201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM1 SA1_DIM1

3

1D5V_S3

Layout Note: Place these Caps near SO-DIMMA.

3

M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6

M_B_DIM0_CS#0 6 M_B_DIM0_CS#1 6

M_B_DIM0_CKE0 6 M_B_DIM0_CKE1 6

M_B_DIM0_CLK_DDR0 6 M_B_DIM0_CLK_DDR#0 6

M_B_DIM0_CLK_DDR1 6 M_B_DIM0_CLK_DDR#1 6

PCH_SMBDATA 15,20,65 PCH_SMBCLK 15,20,65

TS#_DIMM0_1 15

1D5V_S3

SWAP SA0_DM1 and SA1_DIM1 each other for DM2 can't boot up issue(only DN15/DQ15)

12

C1401

SCD1U10V2KX-5GP

DY

ST330U2VDM-4-GP

12

TC1401

12

C1402

DY

SC2D2U10V3KX-1GP

12

DY

12

C1414

SC1U6D3V2KX-GP

12/28 Yellow mark for OPI change

12/3 Change DM2 to 62.10024.E21

12/9 Change DM2 to 62.10017.K01

12/21 Change DM2 to 62.10017.P61

12/22 Change DM2 to 62.10024.E21

SA1_DIM1

SA0_DIM1

3D3V_S0

Thermal EVENT

TS#_DIMM0_1

SODIMM A DECOUPLING

12

C1404

C1405

C1403

SC10U6D3V5KX-1GP

12

C1415

SCD1U10V2KX-5GP

C1405

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1416

C1417

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

2

12

2

3D3V_S0

12

R1403

1 2

C1406

SC10U6D3V5KX-1GP

R1402

R1402 10KR2J-3-GP

10KR2J-3-GP

R1401

R1401 10KR2J-3-GP

10KR2J-3-GP

12

C1407

DY

11/ 17 Change SMbus adress note

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 0, SA1_DIM0 = 1 SO-DIMMA SPD Address is 0xA4 SO-DIMMA TS Address is 0x34

3D3V_S0

12

DY

SC10U6D3V5KX-1GP

C1409

C1408

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

12

C1410

DY

SC10U6D3V5KX-1GP

DDR3-SODIMM2

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

14 105

1

A00

5

SSID = MEMORY

M_A_A[15:0] 6

D D

M_A_BS26

M_A_BS06 M_A_BS16

M_A_DQ[63:0]6

DDR_VREF_S3

R1504

R1504 0R0402-PAD

0R0402-PAD

1 2

12

C C

DDR_VREF_S3

1 2

12

B B

X02-0303 change 0R to short pad

0D75V_S0

12

C1518

DY

SC1U6D3V2KX-GP

A A

M_VREF_CA_DIMM0

12

C1523

C1524

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

R1503

R1503 0R0402-PAD

0R0402-PAD

M_VREF_DQ_DIMM0

12

C1515

C1516

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1519

DY

SC1U6D3V2KX-GP

5

12

C1522

SCD1U10V2KX-5GP

12

C1517

SCD1U10V2KX-5GP

12

C1520

C1521

SC1U6D3V2KX-GP

M_A_DIM0_ODT06 M_A_DIM0_ODT16

M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0

DDR3_DRAMRST#14,37

0D75V_S0

4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

H =9.2mm

4

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-128-GP

62.10024.D51

RAS#

WE#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7

SDA

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1 NP2

CK0

CK1

SCL

SA0 SA1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2

110 113 115

114 121

73 74

101 103

102 104

11 28 46 63 136 153 170 187

200 202

198

199

197 201

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

SA0_DIM0 SA1_DIM0

3

M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6

M_A_DIM0_CS#0 6 M_A_DIM0_CS#1 6

M_A_DIM0_CKE0 6 M_A_DIM0_CKE1 6

M_A_DIM0_CLK_DDR0 6 M_A_DIM0_CLK_DDR#0 6

M_A_DIM0_CLK_DDR1 6 M_A_DIM0_CLK_DDR#1 6

PCH_SMBDATA 14,20,65 PCH_SMBCLK 14,20,65

TS#_DIMM0_1 14

1D5V_S3

Layout Note: Place these Caps near SO-DIMMB.

C1501

1D5V_S3

12

SCD1U10V2KX-5GP

12

C1502

DY

SC2D2U10V3KX-1GP

SODIMM B DECOUPLING

12

C1503

DY

SC10U10V5ZY-1GP

12

C1511

SC1U6D3V2KX-GP

12/7 Change DM1 to 62.10024.D51

12/9 Change DM1 to 62.10017.K11

12/17 Change DM1 to 62.10017.N11

12/21 Change DM1 to 62.10017.Q41

12/22 Change DM1 to 62.10024.D91

12/22 Change DM1 to 62.10024.D51

Note: The symbol DM1 is change value and PN only.

3

2

M_A_DQS#[7:0] 6

M_A_DQS[7:0] 6

SA1_DIM0

SA0_DIM0

12

R1502

R1502 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

12/28 Yellow mark for OPI change

12

C1504

C1505

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1512

C1513

SCD1U10V2KX-5GP

12

DY

12

SCD1U10V2KX-5GP

C1507

C1506

C1514

2

DY

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

11/ 17 Change SMbus adress note

Note: SO-DIMMB SPD Address is 0xA0 SO-DIMMB TS Address is 0x30

SO-DIMMB is placed farther from the Processor than SO-DIMMA

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

1 2

12

C1508

SC10U10V5ZY-1GP

12

C1509

C1510

DY

SC10U6D3V5KX-1GP

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

DDR3-SODIMM1

Enrico Caruso 14

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

15 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 105Wednesday, April 13, 2011

A00

5

D D

4

3

2

1

RN1706

3D3V_S0

1

23

HDMI

4

DDI Port B Detect:(SDVO_CTRL_ DATA) 1: Port B detected 0: Port B not detected

PCH_HDMI_CLK 51 PCH_HDMI_DATA 51

HDMI_PCH_DET 51

HDMI_DATA2_R# 51 HDMI_DATA2_R 51 HDMI_DATA1_R# 51 HDMI_DATA1_R 51 HDMI_DATA0_R# 51 HDMI_DATA0_R 51 HDMI_CLK_R# 51 HDMI_CLK_R 51

4 OF 10

PCH1D

L_BKLT_EN27

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

RN1702

2 3 1

SRN100KJ-6-GP

C C

SRN100KJ-6-GP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN LVDS_VDD_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

12

R1701

2K37R2F-GP

Place near PCH

X02-0303 change 0R to short pad

LVDS_VDD_EN49

L_BKLT_CTRL49

LVDS_DDC_CLK_R49 LVDS_DDC_DATA_R49

TP1701TPAD14-GP TP1701TPAD14-GP

RN1704

2 3 1

0R4P2R-PAD

RN

LVDSA_CLK#49 LVDSA_CLK49

LVDSA_DATA0#49 LVDSA_DATA1#49 LVDSA_DATA2#49

LVDSA_DATA049 LVDSA_DATA149 LVDSA_DATA249

RN

4

LVDS_VREFH LVDS_VREFL

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

Close to PCH side

PCH_CRT_BLUE PCH_CRT_GREEN PCH_CRT_RED

B B

678

RN1705

RN1705 SRN150F-1-GP

SRN150F-1-GP

123

4 5

PCH_CRT_BLUE50 PCH_CRT_GREEN50 PCH_CRT_RED50

11/20 Add C1722~C1724

PCH_CRT_BLUE

C1722

12

SC10P50V2JN-4GP

DY

PCH_CRT_GREEN

C1723

12

SC10P50V2JN-4GP

PCH_CRT_RED

C1724

12

SC10P50V2JN-4GP

11/19 Del R1703~R1705

PCH_CRT_DDCCLK50 PCH_CRT_DDCDATA50

PCH_CRT_HSYNC50 PCH_CRT_VSYNC50

12

R1702

1KR2D-1-GP

Notes: 1K 0.5% 0402.

CHIP RES 1K D 1/16W 0402

DAC_IREF_R

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

LVDS

CRT

PCH1

Digital Display Interface

P/N: ND27V

4 OF 10

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SRN2K2J-1-GP

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (LVDS/CRT/DDI)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

17 105

1

A00

5

4

3

2

1

SSID = PCH

12/2 Net swap for layout

RN1801

D D

3D3V_S0

INT_PIRQB#

INT_PIRQC# INT_PIRQF#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

B B

A A

PLT_RST#5,27,31,65,71,83

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

1 2

DY

1 2

DY

R1802

1KR2J-1-GP

R1803

1KR2J-1-GP

10

INT_PIRQE#INT_PIRQD#

9

INT_PIRQA#

8

INT_PIRQH#

7

INT_PIRQG#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

3D3V_S0

BOOT BIOS Strap

Reserved 01

11

SPI(Default)

CLK_PCI_LPC71

CLK_PCI_KBC27

X02-0303 change 0R to short pad

R1807

1 2

0R0402-PAD

12

R1816

DY

C1801

100KR2J-1-GP

C1801 SC220P50V2KX-3GP

SC220P50V2KX-3GP

DY

5

PCI_PLTRST#

BBS_BIT0 21

DGPU_HOLD_RST# DGPU_PWR_EN#

SRN10KJ-5-GP

DGPU_HOLD_RST#83

DGPU_PWR_EN#93

TP1806TPAD14-GP TP1806TPAD14-GP

SATA_ODD_DA#56

TP1807TPAD14-GP TP1807TPAD14-GP

1

X02-0311 dummy R1804

R1804 22R2J-2-GP

R1804 22R2J-2-GP R1805 22R2J-2-GPR1805 22R2J-2-GP R1806 22R2J-2-GPR1806 22R2J-2-GP

12

EC1801

EC1802

DY

1 2

SC33P50V2JN-3GP

SC4D7P50V2CN-1GP

4

RN1803

1 2 3

3D3V_S0

1

PCH_GPIO53

R1813

1 2

0R0402-PAD

DY

1 2 1 2 1 2

12

EC1803

DY

SC33P50V2JN-3GP

4

R1814

R1814 8K2R2J-3-GP

8K2R2J-3-GP

1 2

DGPU_SELECT#

DGPU_PWR_EN#

TP1801TPAD14-GP TP1801TPAD14-GP

1

TP1802TPAD14-GP TP1802TPAD14-GP

1

KBC CLK EMI

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

BBS_BIT1

PCI_GNT3#

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME#

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

Y13 K24

AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

H38

G38

C46 C44 E40

D47 E42 F46

G42 G40

C42 D44

K10

H49 H43

K42 H40

L24

K40 K38

J48

H3

C6

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

RSVD

PCI

PCH1

NVRAM

USB

P/N: ND27V

12/1 Swap net for layout

11/11 change to RN1802 to meet schematic check result.

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

3D3V_S5

PCH_GPIO14 USB_OC#6_7

USB_OC#4_5

3

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

10 9 8 7

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10

AT8

AY5 BA2

AT12 BF3

USB Ext. port 1 (HS) External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14

PCH_GPIO14

C14

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

USB_OC#0_1 USB_OC#12_13USB_OC#10_11 USB_OC#8_9 USB_OC#2_3

3D3V_S5

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

2

USB_PN1 61 USB_PP1 61

USB_PN5 32 USB_PP5 32

USB_PN8 82 USB_PP8 82 USB_PN9 82 USB_PP9 82

USB_PN11 65 USB_PP11 65 USB_PN12 49 USB_PP12 49

USB_OC#0_1 61

USB_OC#8_9 61CLK_PCI_FB20

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

DMI & FDI Termination Voltage

USB Table

Pair

Wednesday, April 13, 2011

NV_CLE

Danbury Technology: Disabled when Low. Enable when High.

X

0

USB Ext. port 2 (MB)

1

X

2

X

3

X

4

CARD READER

5

X

6

X

7

USB Ext. port 3

8

USB Ext. port 1

9

X

10

Mini Card1 (WLAN+BT)

11

CAMERA

12

X

13

PCH (PCI/USB/NVRAM)

Enrico Caruso 14

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# 5

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

NV_ALE

Device

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

18 105

1

A00

5

4

3

2

1

SSID = PCH

3 OF 10

PCH1C

Signal Routing Guideline: DMI_ZCOMP keep W=4 mils and routing length less than 500

D D

mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

DY

R1926

12

10KR2J-3-GP

10KR2J-3-GP R1904

R1904

12

100KR2J-1-GP

AC_PRESENT27

XDP_DBRESET#5

SYS_PWROK36

S0_PWR_GOOD27,36

RUNPWROK45,46,47

PM_PWRBTN#27

100KR2J-1-GP

3D3V_S0

C C

PM_DRAM_PWRGD5,37

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

SUS_PWR_ACK27

B B

SYS_PWROK

PWROK

R1924

1 2

0R0402-PAD

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

1 2

X02-0303 change 0R to short pad

R1903

1 2

0R0402-PAD

R1905

1 2

PWROK

MEPWROK

DY

1 2

SYS_RESET#

R1923

0R0402-PAD

R1907

1 2

DY

R1925

1 2

10KR2J-3-GP

0R2J-2-GP

DMI_COMP_R

RBIAS_CPY

0R2J-2-GP

DY

R1906

12

0R0402-PAD

PM_RSMRST#

BATLOW#

PM_RI#

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

SUSACK#SUS_PWR_ACK

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18 BJ20

AW24 AW20

BB18

AV18

AY24

AY20

AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPWRDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPIO72

RI#

DMI

System Power Management

PCH1

P/N: ND27V

3D3V_S5

RN1901

8 7 6

SRN10KJ-6-GP

DY

A A

DY

5

12/2 Swap net for layout

BATLOW#

1

PCH_WAKE#

2

PM_RI#

3

SUS_PWR_ACK

45

R1909

12

10KR2J-3-GP

R1922

12

10KR2J-3-GP

R1920

12

10KR2J-3-GP

R1908

12

10KR2J-3-GP

AC_PRESENT

PM_PWRBTN#

PM_SLP_LAN#

PM_RSMRST#

PCIE_WAKE# CRB : 1K CEKLT: 10K

4

3 OF 10

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DSWODVREN

PCH_DPWROK

PM_SUS_STAT#

SUS_CLK

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] 4

FDI_TXP[7:0] 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

R1913

1 2

0R0402-PAD

PM_RSMRST#

R1910

1 2

0R0402-PAD

1 2

R1911 10KR2J-3-GP

DY

TP1901 TPAD14-GPTP1901 TPAD14-GP

1

TP1902 TPAD14-GPTP1902 TPAD14-GP

1

TP1903 TPAD14-GPTP1903 TPAD14-GP

1

TP1904 TPAD14-GPTP1904 TPAD14-GP

H_PM_SYNC 5

1

TP1905 TPAD14-GPTP1905 TPAD14-GP

R1912

1 2

0R0402-PAD

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ˉno connectˇ

4.SUSWARN# used as SUSPWRDNACK/GPIO30

PM_RSMRST#

RTC_AUX_S5

PCH_WAKE# 27

PM_CLKRUN# 27

PCH_SUSCLK_KBC 27

RSMRST#_KBC 27

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

PM_SLP_S4# 27,46

PM_SLP_S3# 27,36,37,47

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH (DM I/FDI/PM)

Enrico Caruso 14

1

RTC_AUX_S5

3D3V_S0

19 105

A00

5

SSID = PCH

D D

PCIE_RXN231

PCIE_RXP231 PCIE_TXN231 PCIE_TXP231

PCIE_RXN465

PCIE_RXP465 PCIE_TXN465 PCIE_TXP465

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

CLK_PCH_48M

EC2001

1 2

DY

SC4D7P50V2CN-1GP

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN4_C PCIE_TXP4_C

12/2 Swap net for layout

RN2001

C C

PCIE_CLK_REQ0#

3D3V_S5

1 2 3 4 5 6

SRN10KJ-L3-GP

CLK_PCIE_WLAN#65 CLK_PCIE_WLAN65

CLK_PCIE_WLAN_REQ#65

12/6 swap net for layout

CLK_PCIE_LAN#31

B B

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2#

CLK_PCIE_LAN31

PCIE_CLK_LAN_REQ#31

RN2018

1 2 3

SRN10KJ-5-GP

PCIE_CLK_REQ2#

4

CLK_PCIE_WLAN_REQ#

Support S0 power only

10

PEG_B_CLKRQ#

9

PCIE_CLK_REQ4#PCIE_CLK_LAN_REQ#

8

CLK_PCIE_REQ7#PCIE_CLK_REQ5#

7

EC_SWI#

PCIE_CLK_REQ0#

RN2012

2 3 1

0R4P2R-PAD

RN

RN2014

1 2 3

0R4P2R-PAD

3D3V_S5

CLK_PCH_SRC1_N

4

PCIE_CLK_REQ2#

RN

4

CLK_PCH_SRC3_N CLK_PCH_SRC3_P

A00-0413 SWAP RN2014 net for layout

PCIE_CLK_REQ4#

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

11/1 Add EC2002~EC2007 for EMI request

A A

CLK_PCIE_WLAN#

SC22P50V2JN-4GP

CLK_PCIE_WLAN

SC22P50V2JN-4GP

CLK_PCIE_LAN

SC22P50V2JN-4GP

CLK_PCIE_LAN#

SC22P50V2JN-4GP

JTAG_TCK_VGA

SC22P50V2JN-4GP

DY

EC2002

12

EC2003

12

EC2004

12

EC2005

12

EC2007

12

5

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

CLK_PCIE_REQ7#

ITPXDP_N

1

ITPXDP_P

1

4

PCH1B

BG34

BJ34 AV32 AU32

BE34

BF34 BB32 AY32

BG36

BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40

BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13

V38 V37

K12

AK14 AK13

COUGAR-GP-U2-NF

Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3



Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2



if more than 2 PCI clocks + PCI loopback are routed.

4

Cougar

PERN1 PERP1

Point

PETN1

W-WAN

PETP1

PERN2 PERP2

LAN

PETN2 PETP2

PERN3 PERP3

Card Reader

PETN3 PETP3

PERN4

WLAN

PERP4 PETN4 PETP4

PERN5 PERP5

USB3.0

PETN5 PETP5

PERN6 PERP6

Intel GBE LAN

PETN6 PETP6

PERN7 PERP7

Dock

PETN7 PETP7

PERN8

NEW CARD

PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2#/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3#/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4#/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ#/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6#/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

WWAN CLK

WLAN CLK

LAN CLK

USB3.0 CLK

NEWCARD CLK

PCI-E*

CLOCKS

P/N: ND27V

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_PCILOOPBACK

PCH1

FLEX CLOCKS

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

2 OF 10

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

REFCLK14IN

XTAL25_IN

XTAL25_OUT

3

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

PEG_CLKREQ#_R

XCLK_RCOMP

DGPU_PRSNT#

EC_SWI#

SMB_CLK

SMB_DATA

DRAMRST_CNTRL_PCH

SML0_CLK

SML0_DATA

PCH_GPIO74

SML1_CLK

SML1_DATA

CL_CLK

1

CL_DATA

1

CL_RST#

1

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_PCLK_PCH_SRC1_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

1 2

90D9R2F-1-GP

JTAG_TCK

CLK_48_USB30

CLK_27M_VGA_R

11/18 Del VGA 27M and change to TP2007

EC_SWI# 27

DRAMRST_CNTRL_PCH 37

SML1_CLK 27,85

SML1_DATA 27,85

TP2001 TPAD14-GPTP2001 TPAD14-GP

TP2002 TPAD14-GPTP2002 TPAD14-GP

TP2003 TPAD14-GPTP2003 TPAD14-GP

R2003

RN

1 2

DY

0R2J-2-GP

RN2016

1 2 3

0R4P2R-PAD

RN2010

2 3 1

0R4P2R-PAD

SRN10KJ-5-GP

12/6 swap net for layout

4

RN

RN2008

2 3 1

4

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N

CLK_PCI_FB 18

CLK_BUF_CKSSCD_P

12/6 swap net for layout

CLK_BUF_EXP_N CLK_BUF_EXP_P

R2007

R2001

R2016

+VCCDIFFCLKN

1 2

22R2J-2-GP

1 2

22R2J-2-GP

1

TP2007 TPAD14-GPTP2007 TPAD14-GP

DY

CLK_BUF_REF14

2

UMA

PEG_CLKREQ#_R

PEG_CLKREQ# 85

CLK_PCIE_VGA# 83 CLK_PCIE_VGA 83

CLK_EXP_N 5 CLK_EXP_P 5

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

2 3 1

RN2021 SRN10KJ-5-GPRN2021 SRN10KJ-5-GP

2 3 1

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

2 3 1

R2008

1 2

JTAG_TCK_VGA 83,85

CLK_PCH_48M 32

2

3D3V_S5

DIS

SMB_DATA

SMB_CLK

4

10KR2J-3-GP

1

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

2 3 1

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

RN2007

4

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

1

6

2

5

34

Q2001

XTAL25_IN

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

XTAL25_OUT

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

CRB : 1K CEKLT: 10K

PCH_SMBDATA 14,15,65

PCH_SMBCLK 14,15,65

41

X2001

2 3

11/29 change X2001 to 82.30020.D41

X01-0217 change C2008 , C2007 to 15pF

3D3V_S0 3D3V_S0

12

R2012

R2013

UMA

10KR2J-3-GP

12

R2011

R2010

DY

10KR2J-3-GP

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Enrico Caruso 14

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 Optimus(Muxless) : 1 0

UMA_DIS# DGPU_PRSNT#

DIS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RN2003

1

SRN2K2J-1-GP

23

RN2004

1

SRN2K2J-1-GP

23

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

SC15P50V2JN-2-GP

XTAL-25MHZ-155-GP

C2007

12

SC15P50V2JN-2-GP

UMA_DIS# 22

20 105

3D3V_S5

A00

5

RTC_AUX_S5

SSID = PCH

2 3

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

12

C2101

SC15P50V2JN-2-GP

HDA_CODEC_SDOUT29

HDA_CODEC_RST#29 HDA_CODEC_BITCLK29

C C

X2101

1 4

32

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

RN2102

1 2 3

SRN33J-5-GP-U

R212333R2J-2-GP R212333R2J-2-GP

12

4

HDA_SDOUT

HDA_RST# HDA_BITCLK

Flash Descriptor Security Overide

Low = Default High = Enable

No Reboot Strap

Low = Default High = No Reboot

HDA_SYNC

HDA_SDOUT

HDA_SPKR

HDA_SDOUT

HDA_SPKR

+3VS_+1.5VS_HDA_IO

DY

R2102

1 2

1KR2J-1-GP

3D3V_S0

B B

NO REBOOT STRAP

DY

R2106

1 2

1KR2J-1-GP

+3VS_+1.5VS_HDA_IO

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

1 2

PLL ODVR VOLTAGE

HDA_SYNC

Low = 1.8V (Default) High = 1.5V

11/2 Merge R2122 into Q2101

A A

HDA_CODEC_SYNC29

RUN_ENABLE

HDA_CODEC_SYNC

R2117

100KR2J-1-GP

5

1 2

Q2101

G

D

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

DY

1

SRN20KJ-1-GP

SC1U6D3V2KX-GP

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_SYNC_R

R212233R2J-2-GP

12

4

3

X01-0210 Merge R2115 R2116

RN2106

4

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

C2104

GAP-OPEN

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

ME_UNLOCK27

SPI_SI_R27,60

SPI_SO_R27,60

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR29

HDA_SDIN029

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

1 2

SPI_CLK_R27,60

SPI_CS0#_R27,60

RTC_X1

RTC_X2

RTC_RST#

12

HDA_SDOUT

PCH_GPIO33

1

SRTC_RST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK

HDA_SYNC

HDA_RST#

PCH_JTAG_TCK_BUF

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

12

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

TP2105TPAD14-GP TP2105TPAD14-GP

TP2101TPAD14-GP TP2101TPAD14-GP

TP2102TPAD14-GP TP2102TPAD14-GP

TP2103TPAD14-GP TP2103TPAD14-GP

TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

ER2111 0R0402-PADER2111 0R0402-PAD

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

11/1 Add R2111 for EMI request

11/ 17 change R2111 from 33ohm to 0ohm and change to ER2111

EC2103

R2124

33R2J-2-GP

HDA_SYNC

12

4

DY

1 2

EC2102

SC4D7P50V2CN-1GP

DY

1 2

EC2103

SC4D7P50V2CN-1GP

DY

3

PCH1A

Cougar

RTCX1

Point

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

COUGAR-GP-U2-NF

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

EC2101

1 2

SC4D7P50V2CN-1GP

1 OF 10

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATALED#

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

RTCIHDA

JTAG

PCH1

SPI

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP/GPIO21

SATA1GP/GPIO19

P/N: ND27V

INT_SERIRQ SATA_DET#0

S_GPIO22

PSW_CLR#22

12/6 Separate RN2103 to R2125 and R2126

11/11Remove RN2104 and FP_DET#

1 2 3

2

X01-0208 Add RN2101, R2127 for LPC EA result X01-0210 change RN2101 to RN2104 RN2105

LPC_AD[0..3]

LPC_FRAME# 27,71

SATA_RXN0 56 SATA_RXP0 56 SATA_TXN0 56 SATA_TXP0 56

SATA_RXN4 56 SATA_RXP4 56 SATA_TXN4 56 SATA_TXP4 56

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LPC_AD0_R LPC_AD1_R LPC_AD2_R LPC_AD3_R

LPC_FRAME#_R

SATA_TXN0_C SATA_TXP0_C

SATA_TXN4_C SATA_TXP4_C

SATA_DET#0

BBS_BIT0

RN2103

SRN10KJ-5-GP

R2125

1 2

10KR2J-3-GP

R2126

1 2

10KR2J-3-GP

2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

3D3V_S0

4

RN2104 SRN33J-5-GP-URN2104 SRN33J-5-GP-U

2 3 1

RN2105 SRN33J-5-GP-URN2105 SRN33J-5-GP-U

1 2 3

KB_DET# 69

INT_SERIRQ 27

C2111 SCD01U16V2KX-3GPC2111 SCD01U16V2KX-3GP

1 2

C2112 SCD01U16V2KX-3GPC2112 SCD01U16V2KX-3GP

1 2

R2112 37D4R2F-GPR2112 37D4R2F-GP

R2113 49D9R2F-GPR2113 49D9R2F-GP

R2114 750R2F-GPR2114 750R2F-GP

BBS_BIT0 18

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

LPC_AD0 LPC_AD1

4

LPC_AD2

4

LPC_AD3

R2127

12

33R2J-2-GP

C2114SCD01U16V2KX-3GP C2114SCD01U16V2KX-3GP

12

C2113SCD01U16V2KX-3GP C2113SCD01U16V2KX-3GP

12

1 2

SATA_LED# 68

PCH (SPI/RTC/LPC/SATA/IHDA)

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

1

LPC_AD[0..3] 27,71

21 105

1

HDD1

ODD

A00

5

4

3

2

1

SSID = PCH

D D

3D3V_S0

R2202

1 2

100KR2J-1-GP

3D3V_S0

RN2203

2 3 1

4

SRN10KJ-5-GP

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

11/11 Remove R2220 for GPIO48 set to GPO

C C

PCH_TEMP_ALERT#

MFG_MODE

DGPU_HPD_INTR# EC_SCI# EC_SMI#

11/11Remove DBC_EN X01-0211 swap DGPU_HPD_INTR#, EC_SMI# for layout.

B B

12/1 Add R2224 pull high

RTC_SENSE#

PCH_GPIO15

1 2

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

RN2201

1 2 3 4 5

SRN10KJ-6-GP

1 2

R2224 10KR2J-3-GPR2224 10KR2J-3-GP

R2201

1 2

DY

11/ 17 Dummy R2201 because GPIO15 internal PH

H_A20GATE H_RCIN#

8 7 6

1KR2J-1-GP

SATA_ODD_PRSNT#

X02-0303 change 0R to short pad

3D3V_S0

3D3V_S5

11/15 Remove Rn2204

Note: For PCH debug with XDP, need to DUMMY R2218

S_GPIO21

TP2219TPAD14-GP TP2219TPAD14-GP

RTC_SENSE#60

SATA_ODD_PRSNT#56

TPAD14-GP

PSW_CLR#21

TPAD14-GP

GAP-OPEN

21

G2201

S_GPIO PCH_GPIO0

EC_SMI#27

EC_SCI#27

1

DGPU_PWROK86,92,93

TP2214TPAD14-GP TP2214TPAD14-GP

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP

TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

TP2210

TP2212TPAD14-GP TP2212TPAD14-GP

TP2203

TP2213

TP2211TPAD14-GP TP2211TPAD14-GP

RTC_SENSE#

R2213

R2213 0R0402-PAD

0R0402-PAD

1

R2218

1 2

100R2J-2-GP

EC_SMI#

DGPU_HPD_INTR#

EC_SCI#

ICC_EN#

PCH_GPIO15

PCH_GPIO16

12

DGPU_PWROK

PCH_GPIO22

1

PCH_GPIO24

1

PCH_GPIO27

1

PLL_ODVR_EN

PSW_CLR#

PCH_GPIO35

1

DMI_OVRVLTG

FDI_OVRVLTG

MFG_MODE

GFX_CRB_DET

1

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_NCTF_1

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_4

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

6 OF 10

A20GATE

PECI

RCIN#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

UMA_DIS#

B41

PCH_GPIO70

C41

PCH_GPIO71

A40

P4

H_PECI_R

AU16

P5

AY11

PCH_THERMTRIP_R

AY10

INIT3_3V#

T14

AH8

AK11

AH10

TS_VSS

AK10

P37

BG2

3D3V_S0

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

3D3V_S0

C48

D1

D49

E1

E49

F1

F49

R2219

1 2

0R0402-PAD

12

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

GPIO

PCH1

THRMTRIP#

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

P/N: ND27V

ICC_EN#

1

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

DY

FDI_OVRVLTG

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DY

DMI_OVRVLTG

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

1 2

SATA_ODD_PWRGT 56

UMA_DIS# 20

TP2204

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE 27

H_RCIN# 27

R2204 390R2J-1-GPR2204 390R2J-1-GP

TP2201

1

DY

R2203

1 2

0R2J-2-GP

H_CPUPWRGD 5,36

1 2

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboard. They should be tied to GND directly.

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Integrated Clock Chip Enable

ICC_EN#

1KR2J-1-GP

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

H_PECI 5,27

H_THERMTRIP# 5,36,85

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

A A

5

4

PLL ON DIE VR ENABLE

NOTE:This signa l has a weak in ternal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

3

1 2

DY

R2212

1KR2J-1-GP

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (GPIO/CPU)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

22 105

1

A00

5

1D05V_VTT

(1uFx3)

6A

1.3A(Total current of VCCCORE)

12

C2301

SC10U6D3V3MX-GP

12

C2303

C2302

C2303

SC1U6D3V2KX-GP

SSID = PCH

D D

(10uFx1_0603)

11/18 change capacity to 0603 package

1D05V_VTT

TP2301TPAD14-GP TP2301TPAD14-GP

1D05V_VTT

C C

(1uF x4)

12

C2306

C2305

C2306

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

1

2.925A(Total current of VCCIO)

12

C2307

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

12/28 Yellow mark for OPI change X02-0303

0.266A (Totally VCC3_3 current)

(0.1uF x1)

3D3V_S0

0.159A(Totally current of VCCVRM)

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

1D5V_S0

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

1

0.042A (Totally current of VCCDMI)

4

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

DY

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

3

11/ 17 Add R2301 but dummy it and change L2301 source to 3D3V_DAC_S0

7 OF 10

POWER

Cougar

Cougar Point

Point

CRTLVDS

7 OF 10

VCCADAC

VSSADAC

U48

U47

0.001A

+VCCA_DAC_1_2

(0.1uF/0.01uF x1) (10uF x1_0603)

12

C2313

0.001A

+3VS_VCCA_LVDS

VCC CORE

VCCALVDS

VCCTX_LVDS

VSSALVDS

VCC3_3

VCCVRM

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

0.16A

0.042A

+1.05VS_VCC_DMI

AT20

VCCIO

PCH1

FDI

DMI

NAND / SPI HVCMOS

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

12

0.19A

12

0.02A

12

P/N: ND27V

12

C2314

SCD01U16V2KX-3GP

12

(0.1uFx1)

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2306

1 2

0R0402-PAD

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

R2307

1 2

0R0402-PAD

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2

3D3V_S0

DY

R2301

R2301 0R2J-2-GP

0R2J-2-GP

1 2

L2301

1 2

HCB1608KF-181-GP

12

C2315

SCD1U10V2KX-5GP

12

C2316

SCD01U16V2KX-3GP

3D3V_S0

HCB1608KF-181-GP

68.00214.051

2nd = 68.00206.041

3rd = 68.00335.081

SC10U6D3V3MX-GP

C2318

12

C2317

SCD01U16V2KX-3GP

11/18 change capacity to 0603 package

1D5V_S0

1D05V_VTT

SC10U6D3V3MX-GP

(1uF x1)

1D05V_VTT

(1uFx1) (10uFx1)

1D8V_S0

3D3V_DAC_S0

R2304

1 2

0R0603-PAD

R2305

1 2

0R0805-PAD

11/2 change R2304, R2305 to 0ohm

X02-0303 change 0R to short pad

change 0R to short pad

(0.1uFx1)

3D3V_S5

(1uFx1)

3D3V_S0

1D8V_S0

(0.01uF x2) (22uF x1)

1

Refer to NPCE795 shared SPI flash architecture

11/3 Add LDO for CRT DAC power

A A

5

4

11/ 17change U2301 Vout power rail and stuff the circuit

5

4

3D3V_DAC_S0

12

C2312

SC1U6D3V2KX-GP

5V_S0

C2311

U2301

1

VIN

12

SC1U10V2KX-1GP

3

2

2nd = 74.09198.G7F

VOUT GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

PCH (POWER1)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

23 105

1

A00

5

4

3

2

1

SSID = PCH

1

DCPSUSBYP

1

(10uFx1)

1

12

DY

C2407

1D5V_S0

(1uFx1)

0.095A

C2415

12

TP2406TPAD14-GP TP2406TPAD14-GP

12

C2418

12

C2421

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

VCCACLK

+VCCPDSW

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2408

SC1U6D3V2KX-GP

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+V1.05S_SSCVCC

(1uFx1)

+VCCSST

DCPSUS

1

12

C2422

SCD1U10V2KX-5GP

TP2401TPAD14-GP TP2401TPAD14-GP

0.002A

3D3V_S0

(10uFx1)

D D

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

+V3.3S_VCC_CLKF33

(1uFx1)

12

C2401

SC10U6D3V3MX-GP

C2402

SC1U10V2KX-1GP

3D3V_S5

R2403

1 2

0R0603-PAD

TP2405TPAD14-GP TP2405TPAD14-GP

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

11/18 change capacity to 0603 package

1D05V_VTT

(22uFx2_0603) (1uFx3)

C C

1D05V_VTT

0.08A

L2402

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

0.08A

L2403

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

B B

1D05V_VTT

R2404

12

0R0402-PAD

1D05V_VTT

R2405

12

0R0402-PAD

(1uFx1) (220uFx1)

+1.05VS_VCCA_A_DPL

12

C2443

C2443 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

+1.05VS_VCCA_B_DPL

12

C2444

C2444 SC10U6D3V3MX-GP

SC10U6D3V3MX-GP

DY

+VCCDIFFCLK

12

C2412

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

C2413

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

12

11/ 17 Change R2406 from close gap to 0ohm

X02-0303 change 0R to short pad

A A

5

12

12/28 Yellow mark for OPI change

12

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2411

1D05V_VTT

C2411

1D05V_VTT

(0.1uFx2) (4.7uFx1_0603)

RTC_AUX_S5

(0.1uFx2) (1uFx1)

SCD1U10V2KX-5GP

(1uFx1)

C2403

SC4D7U6D3V3KX-GP

1 2

0R0402-PAD

SC1U6D3V2KX-GP

(0.1uFx1)

0.001A

SC4D7U6D3V3KX-GP

1.01A (Total current of VCCASW)

12

R2406

(1uFx1)

C2404

(0.1uFx1)

12

C2406

SC10U6D3V3MX-GP

+VCCRTCEXT

+VCCDIFFCLKN

C2414

C2417

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

0.055A

12

SCD1U10V2KX-5GP

12

6uA

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

CPURTC

PCH1

3

PCI/GPIO/LPCMISC

SATA USB

HDA

P/N: ND27V

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

0.097A (Totally current of VCCSUS3_3)

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

1D05V_VTT

0.01A

C2433

SCD1U10V2KX-5GP

C2433

3D3V_S5

C2428

C2430

C2429

C2432

DY

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

DY

12

C2434

SC10U6D3V5KX-1GP

12

2

C2423

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

C2435

(1uFx1)

SC1U6D3V2KX-GP

(0.1uFx1)

TP2403 TPAD14-GPTP2403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

SC1U6D3V2KX-GP

1D05V_VTT

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

5V_S5

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

83.R0304.A8F

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

1 2

10R2J-2-GP

(0.1uFx2)

3D3V_S0

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

+3VS_+1.5VS_HDA_IO

R2409

0R0402-PAD

11/ 17 Change R2409 from close gap to 0ohm

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PCH (POWER2)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

R2407

12

5V_S0

(1uFx1)

24 105

1

3D3V_S5

A00

5

4

3

2

1

SSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

PCH1

P/N: ND27V

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

PCH1

P/N: ND27V

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

PCH (VSS)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

25 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Reserved

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

26 105

1

A00

11/17 change R2724 to meet X00 PCB ver

SSID = KBC

3D3V_AUX_KBC

DY

D D

11/16 Add R2728 R2729 for SERIES_ID

3D3V_AUX_KBC

Vostro

C C

11/22 add RTC_AUX_S5 to KBC_GPIO72

X01-0127 Del R2757 to follow standard 10mw circuit

11/1 Add R2777, C2777 for EMI

B B

ROSA Multi GPIO setting

L_BKLT_EN17

X02-0303 change 0R to short pad

R2771

R2771 2D2R3-1-U-GP

2D2R3-1-U-GP

1 2

12

C2701

C2704

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

12

R2728

R2728 100KR2J-1-GP

100KR2J-1-GP

Ins

SERIES_ID

12

R2729

R2729 100KR2J-1-GP

100KR2J-1-GP

CLK_PCI_KBC

R2777

C2777

VGA_THRM

C2719 SCD1U10V2KX-5GP

1 2

DY

SYS_THRM

C2720

1 2

DY

CPU_THRM

C2721

1 2

DY

KBC_PWRBTN#68

A A

5

11/ 17 change R2702 from close gap to 0ohm

R2702

1 2

0R0603-PAD

SCD1U10V2KX-5GP

12

C2705

DY

EC_AGND

12

DY

22R2J-2-GP

CLK_PCI_KBC_EMI

DY

1 2

SC4D7P50V2CN-1GP

SCD1U10V2KX-5GP

1 2

R2761 0R0402-PADR2761 0R0402-PAD

BAT54CPT-GP

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

12

C2706

C2707

SCD1U10V2KX-5GP

AD_IA40

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

1 2

PSID_EC38

CPU_THRM28

FAN1_DAC28

LCD_TST49

SUS_PWR_ACK19

VGA_THRM28 SYS_THRM28

BATT_WHITE_LED#68

CAP_LED#69

S5_ENABLE36

BAT_IN#39

LID_CLOSE#82

RSMRST#_KBC19

PM_SLP_S4#19,46

ME_UNLOCK21

WIFI_RF_EN65 BLUETOOTH_EN65 S0_PWR_GOOD19,36

USB_PWR_EN#61

AC_PRESENT19

IMVP_PWRGD36,42

11/ 17 add R2774 pull high for LID_CLOSE#

LID_CLOSE#

EC_AGND

PANEL_BLEN

PSL_IN2

1

1 2

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

D2703

2

10mW

1

BAT54CPT-GP

12

C2708

C2709

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

EC_AGND

PCB_VER_AD

SERIES_ID

VGA_THRM

PSL_IN2

MODEL_ID_DET

ECSMI#_KBC

CAP_LED#

RCID38

PSL_IN1 PSL_OUT EC_GPIO72

KBC_VCORF

12

C2712

SC1U10V3ZY-6GP

Very close to EC

3D3V_S5

12

R2774

100KR2J-1-GP

KBC_ON#_R

R2704

330KR2J-L1-GP

3

AC_IN# 40

12

C2710

EC_GPIO72

SCD1U10V2KX-5GP

4

NPCE795PA0DX-GP-U

EC_SWI#20

EC_SCI#22

RN2706

SRN10KJ-5-GP

5

X01-0210 change R2724 to meet X01 PCB ver X02-0314 change R2724 to meet X02 PCB ver

Reserved 0.1uF on all of ADC input pins

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3

96

GPIO4

108

GPIO5

93

GPIO6

94

GPIO7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/TRST#

26

GPIO51

73

GPIO70

74

GPIO71

75

GPIO72

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/TEST#

112

GPO84/XORTR#

107

GPIO97

44

VCORF

EC_SWI#20

EC_SCI#22

3D3V_AUX_S5

1

KBC_ON#_GATE

23

base on NUVOTON feedback list.(C2717~C2721)

VBAT

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

D2701

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

D2704

1

DY

BAS16-6-GP

2

83.00016.K11

2ND = 83.00016.F11

C2722

1 2

SCD1U10V2KX-5GP

12

DY

C2713

SCD1U10V2KX-5GP

Q2706

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

A00-0413 change R2724 to 47K for PCB ver

115

102

4

VDD

AVCC

GPIO11/CLKRUN#

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO67/PWUREQ#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1

GPIO22/SDA1

GPIO73/SCL2

GPIO74/SDA2

GPIO23/SCL3

GPIO31/SDA3

GPIO47/SCL4

GPIO53/SDA4

F_SDI/F_SDIO1

F_SDIO/F_SDIO0

GND

5

116

R2711

1 2

0R0402-PAD

EC_AGND

ECSWI#_KBC

3

ECSCI#_KBC

3

ECSWI#_KBC

R2758

1 2

0R0402-PAD

ECSCI#_KBC

R2759

1 2

0R0402-PAD

3D3V_AUX_S5

S

Q2703

G

DMP2130L-7-GP

D

2ND = 84.03413.A31

D

84.02130.031

3D3V_AUX_KBC

S5_ENABLE

D

4

3D3V_S0

12

C2703

DY

C2702

A00-0328

SC2D2U10V3KX-1GP

SCD1U10V2KX-5GP

change R2735 to 10R and C2711 to 220p

1 OF 2

PLT_RST#_EC

7

LRESET#

2

LCLK

3

LFRAME#

SERIRQ

AGND

103

EC_AGND

F_CS0#

F_SCK

LPC_AD3

1

LAD3

LPC_AD2

128

LAD2

LPC_AD1

127

LAD1

LPC_AD0

126

LAD0

125 8

PANEL_BLEN

9

ECSCI#_KBC

29

KBC_GPIO10

124

ECSWI#_KBC

123 121 122

27

AD_IA_HW2

25 11 10 71 72

70 69 67 68 119

EC_ENABLE#_1

120

PROCHOT_EC

24 28

EC_SPI_CS#_C

90

EC_SPI_CLK_C

92

EC_SPI_DI_C

86

EC_SPI_DO_C

87

NOTE: Locate resistors R2736,R2719 and R2722 close to the NPCE795P.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connection.

PCB_VER_AD

C2717

C2711

1 2

SC220P50V2KX-3GP

R2735

1 2

10R2J-2-GP

LPC_AD[0..3] 21,71

INT_SERIRQ 21 PM_CLKRUN# 19

TP2701 TPAD14-GPTP2701 TPAD14-GP

1

H_A20GATE 22 H_RCIN# 22

BLON_OUT 49

AD_IA_HW2 40

PCH_WAKE# 19

TPDATA 69 TPCLK 69

<------ TP

BAT_SCL 39,40 BAT_SDA 39,40 SML1_CLK 20,85 SML1_DATA 20,85

PM_LAN_ENABLE 31

LCD_TST_EN 49

X02-0309 change 0R to short pad

33R2J-2-GPR2736 33R2J-2-GPR2736

12

33R2J-2-GPR2719 33R2J-2-GPR2719

12

R2737 0R0402-PADR2737 0R0402-PAD

12

R2722 33R2J-2-GPR2722 33R2J-2-GP

12

3D3V_AUX_KBC

12

R2724

R2724 47KR2F-GP

47KR2F-GP

12

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

DY

SCD1U16V2KX-3GP

EC_AGND

PLT_RST# 5,18,31,65,71,83

CLK_PCI_KBC 18

LPC_FRAME# 21,71

11/19 add TP2701 for KBC_GPIO10

Follow DQ15 change PCIE_RST# to AD_IA_HW2

<------ BATTERY / CHARGER

<------PCH / eDP

SPI_CS0#_R 21,60 SPI_CLK_R 21,60 SPI_SO_R 21,60

SPI_SI_R 21,60

EC_SPI_DI_C

12

3

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

X01

X02

A00

Reserved

Reserved 100.0K 215.0K 1.048V

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

11/22 change WLAN LED control to KBC

H_PECI5,22

1D05V_VTT

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

12/10 Add R2762 and dummy R2732, Q2702

EC_GPIO47 High Active

Q2702

100KR2J-1-GP

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PROCHOT_EC

12

R2732

DY

R2762

1 2

0R0402-PAD

H_PROCHOT#_EC

D

DY

1 2

R2733 0R0402-PADR2733 0R0402-PAD

PSL SOLUTION 10mW SOLUTION

11/ 17 DY R2734 and stuff R2756 to keep KBC data

EC_GPIO72

R2756

1 2

0R0402-PAD

PSL_IN1AC_OK

R2768

R8909

PWR_CHG_ACOK40

1 2

0R0402-PAD

X01-0208 dummy R2769

1 2

PSL_OUT

G

S

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

R2768

1 2

PSL

0R2J-2-GP

DY

R2767

Q2705

Q2705 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

PSL

0R2J-2-GP

D

KBC_ON#_R

DY

4

12

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AUX_S5

AC_IN#_KBC

EC_ENABLE#_1

3

R2734

1 2

DY

R2763

1 2

10mW

1 2

10mW

2N7002K-2-GP

G

S

Q2704

84.2N702.J31

2ND = 84.2N702.031

R2766

CHG_AMBER_LED#68

KBC_WLAN_OUT#68

PCH_SUSCLK_KBC19

H_PROCHOT# 5,40,42

VBACKUP

EC_GPIO72

0R2J-2-GP

PSL_IN1

0R2J-2-GP

10mW

KBC_ON#_RKBC_ON#

0R2J-2-GP

100.0KX00

100.0K

FAN_TACH128

PM_PWRBTN#19

PCIE_WAKE#31 PM_SLP_S3#19,36,37,47

KBC_BEEP29

AD_IA_HW40

PWRLED#68

E51_RxD65

E51_TxD65

AMP_MUTE#29

R2721 43R2J-GPR2721 43R2J-GP

1 2 1 2

R2720 0R0402-PADR2720 0R0402-PAD

Very close to EC

PSL_IN1

PSL_OUT

KBC_ON#

D

C2716

SCD1U10V2KX-5GP

PURE_HW_SHUTDOWN#28,36

31

117

63 64

32

118

62 65 81 66 22 16

85

113 111

30 77

13 12

12

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65VReserved

U2701B

GPIO56/TA1 GPIO20/TA2 GPIO14/TB1 GPIO01/TB2

GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM GPIO32/D_PWM GPIO66/G_PWM GPIO33/H_PWM GPIO45/E_PWM GPIO40/F_PWM

VCC_POR#

GPIO87/SIN_CR GPO83/SOUT_CR/TRIST#

GPIO55/CLKOUT GPIO00/EXTCLK

PECI VTT

NPCE795PA0DX-GP-U

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K 1.204V

ECRST#

PECI EC_VTT

EC GPIO standard PH/PL

BAT_SCL BAT_SDA

12/22 swap net for layout

AC_IN#_KBC BAT_IN#

S5_ENABLE

EC_ENABLE#_1

ECRST#

12/6 swap net for layout

FAN_TACH128

FAN_TACH1

E51_RxD

BLUETOOTH_EN

11/2 Add MODEL_ID_DET pin for Vostro & Inspron select

KBSOUT15/GPIO61/XOR_OUT

3D3V_AUX_S5

12

2

MODELID

MODEL_ID_DET

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK

KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

2nd = 84.03906.F11

RN2701

4

SRN4K7J-8-GP

RN2703

4

SRN100KJ-6-GP

RN2705

8 7 6

SRN10KJ-6-GP

1 2

R2712 10KR2J-3-GPR2712 10KR2J-3-GP

R2708

1 2

R2709

1 2

DY

2

3D3V_AUX_KBC

C2718

1 2

SCD1U10V2KX-5GP

EC_AGND

2 OF 2

KBSOUT3/TDI

KBSOUT7 KBSOUT8

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

Q2701

MMBT3906-7F-GP

B

84.03906.P11

23 1

1 23

1 2 3 45

DY

10KR2J-3-GP

12

R2710

R2710 47KR2F-GP

47KR2F-GP

12

R2739

100KR2F-L1-GP

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

E

C

3D3V_AUX_KBC

3D3V_S0

MODEL_ID_DET(GPIO07)

Reserved

DV15_UMA with HDMI

DV15_UMA without HDMI

DV14_UMA with HDMI

DV14_UMA without HDMI

DV14_DIS(512M) with HDMI

DV14_DIS(512M) without HDMI

DV14_DIS(1G) with HDMI

DV14_DIS(1G) without HDMI

1

100.0K

100.0K 143.0K(64.14335.L0L)

100.0K

10.0K(64.10025.6DL)

20.0K(64.20025.6DL)

33.0K

47.0K(64.47025.6DL)

64.9K(64.64925.6DL)

76.8K(64.76825.6DL)

100.0K(64.10035.6DL)

174.0K(74.17435.6DL)

215.0K(64.21535.6DL)100.0K

Notes: The total SPI interface signal between EC and PCH canˇt not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

ECRST#

12

C2715

C2715 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DY

KCOL[0..16] 69

11/16 Add R2776 for aviod kbc code error

3D3V_AUX_KBC

R2776

PCIE_WAKE#

KROW[0..7] 69

12

DY

100KR2J-1-GP

11/ 17 DY D2705 to meet DN13 result

D2705

EC_SMI#22

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Wednesday, April 13, 2011

Wednesday, April 13, 2011 Date: Sheet of

Date: Sheet of

1

2

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

R2760

EC_SMI#22

1 2

0R0402-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

KBC Nuvoton NPCE795

Enrico Caruso 14

1

DY

ECSMI#_KBC

3

ECSMI#_KBC

27 105

VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTOR

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.65V

1.358V

1.204V

1.048V

A00

5

4

3

2

1

SSID = Thermal

D D

3D3V_S0

12

C2802

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

12

2ND = 84.03904.P11

3

84.03904.L06

Q2801

DY

PMBS3904-1-GP

R2808

R2808 NTC-100K-8-GP

NTC-100K-8-GP

C C

1

2

THERM_SYS_SHDN#

2.System Sensor, Put on palm rest

SCD1U10V2KX-5GP

P2800_DXP

12

C2806

P2800_DXN

SC470P50V3JN-2GP

1 2

R2811 0R2J-2-GPR2811 0R2J-2-GP

Thermal sensor P2800

3D3V_S0

12

R2803

R2803 107KR2F-GP

107KR2F-GP

DY

87.1 Degree

ADJ

12

R2804

12

C2807

SC2200P50V2KX-2GP

T8_P2800

12

C2805

DY

C2805

SCD1U10V2KX-5GP

DY

226KR2F-GP

Very Close to CPU1

U2801

5

VCC

6

DXP

7

DXN

8

OTZ

P2800EB0-GP

74.02800.B71

1.H/W T8 Shutdown

TDR

TDL

GND

ADJ

12/14 dummy R2803, R2804 and C2805 12/15 Remove 3rd source

Very close to CPU1

11/4 Vendor recommand

X01-0209 dummy U2805 circuit

4 3 2

ADJ

1

SYS_THRM 27 CPU_THRM 27

T8_G709 HYST_PHTHERM_SYS_SHDN#

1 2

DY

R2810 0R2J-2-GP

DY



DY

R2812

24K3R2F-1-GP

R2807

1 2

0R0402-PAD

86.9

R(K )= 0.0012*T^2- 0.9308T+ 96.147



FAN_TACH127

AFTP2801AFTP2801 AFTP2802AFTP2802 AFTP2803AFTP2803

FAN_VCC

1

FAN_TACH1_C

1

GND

1

X02-0309 change AFTP to followDV14 AMD

12/13 change P2800 to ver B

B B

Fan controller P2793

U2802

R2802

1 2

DY

0R2J-2-GP

5V_S0

FAN1_DAC27

0R2J-2-GP

FAN_VCC

*Layout* 10 mil

For linear FAN

3D3V_S0

R2813

1 2

470KR2J-2-GP

DY

U2805

1

SET

2

GND

12

OUT#3HYST

G709T1UF-GP

C2809

SC4D7U6D3V3KX-GP

VCC

DY

FAN_TACH1_C

*Layout* 15 mil

12

21

D2802

CH551H-30PT-GP

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

FON#

5

4

G709_VCCADJ_G709

U2802

1

FON#

2

VIN

3

VO

4

VSET

G991P11U-GP

74.00991.031

2nd = 74.02793.A31

FAN_VCC

12

DY

12

DY

R2805

150R2F-1-GP

12

C2808

C2808 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

C2810

SC2200P50V2KX-2GP

GND GND GND GND

DY

8 7 6 5

R2828

1 2

0R2J-2-GP

FAN1

5 3 2

1 4

FOX-CON3-6-GP-U

20.D0210.103

5V_S0

3D3V_S0

R2809

12

C2803

SC4D7U6D3V3KX-GP

12

C2804

SCD1U10V2KX-5GP

Q2802

PURE_HW_SHUTDOWN#27,36

VGA Thermal sensor P2800

P2800_VGA_DXP85

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

P2800_VGA_DXN85

A A

3D3V_S0

P2800_VGA_DXP

12

DY

P2800_VGA_DXN FAN_VCC

1 2

R2814 0R0402-PADR2814 0R0402-PAD

5

3D3V_S0_thermal

C2812

C2812 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

3D3V_S0_thermal

DY

12

C2814

SCD1U10V2KX-5GP

U2804

5

VCC

6

DXP

7

DY

DXN

8

OTZ

P2800EB0-GP

74.02800.B71

DY

VGA_THRM_TDR

4

TDR

VGA_THRM_TDL

3

TDL

2

GND

1

ADJ

X02-0311 Add R2816& R2817 to option VGA_THRM and DY the circuit

4

DY

R2816 0R2J-2-GP

1 2

R2817 0R2J-2-GP

1 2

DY

11/18 remove R2817, R2818, C2816 and NC U2804 OTZ pin

VGA_THRM 27

12

R2815

R2815 100KR2J-1-GP

100KR2J-1-GP

DY

3

EMI/ESD

12

EC2801

DY

SCD1U16V2KX-3GP

Title

Thermal P2800/Fan Controllor P2793

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

2

Date: Sheet of

D

12

C2811

2N7002K-2-GP

DY

84.2N702.J31

2ND = 84.2N702.031

SCD1U10V2KX-5GP

Enrico Caruso 14

Wednesday, April 13, 2011

Enrico Caruso 14

THERM_SYS_SHDN#

S

G

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

100KR2J-1-GP

3D3V_S0

28 105

A00

5

SSID = AUDIO

D D

11/ 17 change R2930 to 0ohm and part reference change to ER2930

3D3V_S0

Close to codec

12

C2903

C2904

C2902

1 2

SC1U6D3V2KX-GP

C C

SC1U10V2KX-1GP

B B

C2923

3D3V_S0

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

DY

C2902

1 2

SCD1U10V2KX-5GP

AMP_MUTE#

AUD_VREFOUT_B

HDA_CODEC_BITCLK

12

C2907

C2907 SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

HDA_CODEC_SDOUT21 HDA_CODEC_BITCLK21

HDA_SDIN021

HDA_CODEC_SYNC21 HDA_CODEC_RST#21

SCD1U10V2KX-5GP

11/1 Add R2930 for EMI

HDA_CODEC_SDOUT

ER2930 0R0402-PADER2930 0R0402-PAD

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

1 2 1 2

4

AMP_MUTE#27

AMP_MUTE#

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

HDA_CODEC_BITCLK_R

33R2J-2-GPR2901 33R2J-2-GPR2901

HDA_CODEC_SDIN0

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

+PVDD

36

37

38

39

40

41

EAPD

PVDD

PORTD_-R

PORTD_+R

THERMAL_PAD

71.92H87.A03

3

35

PVSS

PORTD_-L

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

+AVDD

AUD_VREG

32

33

34

PVDD

AVDD2

PORTD_+L

31

VREG/+2_5V

CAP+

CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

AUD_AGND

30 29 28

V-

27 26 25 24 23 22 21

AUD_SPK_R+ 58

AUD_SPK_R- 58

AUD_SPK_L- 58

AUD_SPK_L+ 58

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_R AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

2

+AVDD

12

C2905

1 2

SC2D2U10V3KX-1GP

1 2

C2906

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

C2914

R2906 60D4R2F-GPR2906 60D4R2F-GP R2905 60D4R2F-GPR2905 60D4R2F-GP

SC1U10V2KX-1GP

AUD_AGND

CLOSE TO CODEC

1 2 1 2

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

Close to codec

5V_S0 +PVDD

R2902

12

0R0603-PAD

AUD_HP1_JACK_R2 82

AUD_HP1_JACK_L2 82

12 12

AUD_AGND

MIC_IN_R 82 MIC_IN_L 82

12

C2908

C2909

1 2

C2909

SC1U10V2KX-1GP

SCD1U10V2KX-5GP

AUD_AGND

1

R2903

12

C2910

R2904

SC10U6D3V5KX-1GP

12

0R0603-PAD

12

0R0603-PAD

5V_S0

11/ 17 Del C2925

AUD_CAP2

AUD_VREFFLT

AUD_V_B

AUD_VREG

12

C2917

AUD_AGND AUD_AGND AUD_AGND AUD_AGND

C2918

SC4D7U6D3V3KX-GP

Close to codec

12

SC10U6D3V5MX-3GP

12

C2915

C2916

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

92HD87B1A5NDGXTBX8-GP

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

AUD_SENSE_B

AUD_SENSE_A

AUD_PC_BEEP

AUD_CAP2

AUD_VREFFLT

INT_MIC

C2924

SC1U10V3KX-3GP

20

AUD_VREFOUT_O

AUD_VREFOUT_B

12

R2920

1 2

2K2R2J-2-GP

INT_MIC_L_R 58,82

Vendor recommand

INT_MIC_L_R

X02-0314 change 0R to short pad

R2911

12

0R0603-PAD

R2914

12

0R0603-PAD

R2917

12

0R0603-PAD

AUD_AGND

MIC IN

120KR2J-L-GP

AUD_PC_BEEP Trace width>15 mils

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

12

SB_SPKR_RAUD_PC_BEEP

KBC_BEEP_R

120KR2J-L-GP

R2909

1 2

R2910 470KR2J-2-GPR2910 470KR2J-2-GP

From PCH

HDA_SPKR 21

KBC_BEEP 27

From EC

Close to Codec

AUD_VREFOUT_B

RN2901

SRN4K7J-8-GP

1

23

4

MIC_IN_R82

MIC_IN_L82

Azalia I/F EMI

HDA_CODEC_SDOUT

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

PCH_AZ_CODEC_SDOUT1

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

11/16 Change C2919 to 0402 package

+AVDD

12

R2915

R2915 2K49R2F-GP

2K49R2F-GP

AUD_SENSE_A

12

C2919

C2919 SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

AUD_AGND

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

+AVDD

AUD_HP1_JD# 82

AUD_SENSE_B

12

EXT_MIC_JD# 82

Close to Pin14

3

12

AUD_AGND

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

1

A00

29 105Wednesday, April 13, 2011

A00

5

D D

4

3

2

1

(Blanking)

C C

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 105Wednesday, April 13, 2011

A00

5

11/18 change L3101 to slime type

D D

R3117

1 2

0R0603-PAD

60 mils

L3101

1 2

IND-4D7UH-192-GP

C3115

12

C3120

SCD1U16V2ZY-2GP

R3115

1 2

0R0603-PAD

SC4D7U6D3V3KX-GP

EVDD10

C3106

12

SC1U10V3ZY-6GP

12

C3113

SCD1U16V2ZY-2GP

X5R

3D3V_LAN_S5

40 mils

12

C3121

SCD1U16V2ZY-2GP

X5R

12

C3119

SCD1U16V2ZY-2GP

12

3D3V_S5

5

C3101

SC4D7U6D3V3KX-GP

12

C3130

C3130 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

R3131

1 2

0R2J-2-GP

Q3102

G

S

2N7002K-2-GP

AVDD33_REG

3D3V_LAN_S5

C3111

12

SCD1U16V2ZY-2GP

LAN_RST#

X02-0311 add circuit to provent leakage. X02-0314 SWAP net

3D3V_S0

12

R3121

R3121 10KR2J-3-GP

10KR2J-3-GP

R3118

1 2

20KR2F-L-GP

DY

D

A00-0320 Change R3118 for LOM power sequence

LAN_ENABLE_R_C

4

RN3103

RN3103 SRN10KJ-5-GP

SRN10KJ-5-GP

1

2 3

Q3104_B

Q3104

Q3104 PMBS3904-1-GP

PMBS3904-1-GP

312

1 2

DY

R3130 0R2J-2-GP

DY

R3119

1 2

0R3J-0-U-GP

DY

R3120

1 2

0R3J-0-U-GP

12

C3122

C3122 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

PM_LAN_ENABLE_R

X01-0211 add C3122 for soft-sart

12

C3118

SCD1U16V2ZY-2GP

C C

R3104

1 2

0R0603-PAD

X02-0303 change 0R to short pad

B B

11/19 add R3131 for KBC code test

A A

PM_LAN_ENABLE27

12

C3109

SCD1U16V2ZY-2GP

4

12

C3117

C3114

GIGA

SCD1U16V2ZY-2GP

PLT_RST# 5,18,27,65,71,83

PA102FMG-GP-U

PA102FMG-GP-U Q3103

Q3103

DS

G

12

DY

C3125

SC1U10V2KX-1GP

4

DVDD10LANOUP_1.05S CTRL10A_R

12

C3112

12

C3123

SCD1U16V2ZY-2GP

GIGA

3D3V_LAN_S5

main: 84.00102.031 2nd: 84.03403.031

12

C3126

C3129

C3126

SCD1U10V2KX-5GP

LAN CHIP

DVDD10

12

C3116

SCD1U16V2ZY-2GP

R3113

R3113 2K49R2F-GP

2K49R2F-GP

1 2

DVDD10

LAN_MDI0P59 LAN_MDI0N59

LAN_MDI1P59 LAN_MDI1N59

LAN_MDI2P59 LAN_MDI2N59

LAN_MDI3P59 LAN_MDI3N59

3D3V_LAN_S5

12

GIGA

SCD1U10V2KX-4GP

C3128

12

SCD1U10V2KX-5GP

DVDD10

3D3V_LAN_S5

TP3101TPAD14-GP TP3101TPAD14-GP

EVDD10

3

3D3V_LAN_S5

LAN_RSET

U3101

49

GND

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

AVDD10

7

MDIP2

8

MDIN2

9

AVDD10

10

MDIP3

11

MDIN3

12

AVDD33

RTL8111E-VB-GR-GP

DVDD10

1

SMBDATA_LAN CLK_LAN_REQ#_R PCIE_TXP2 PCIE_TXN2 CLK_PCIE_LAN CLK_PCIE_LAN#

PCIE_RXP2_C PCIE_RXN2_C

C3131

1 2

SCD1U10V2KX-5GP

3

EVDD10

R3101

R3101 10KR2J-3-GP

10KR2J-3-GP

1 2

DY

CLK_LAN_REQ#_R

REGOUT VDDREG VDDREG

EEDI/SDA

DVDD10

DVDD33

ISOLATE#

PERST#

DY

36 35 34 33 32 31 30 29 28 27 26 25

LANOUP_1.05S

AVDD3348AVDD33

DVDD10

13

47

SMBCLK14SMBDATA15CLKREQ#

46

RSET

LANXOUT

LANXIN

45

43

42

AVDD10

AVDD33

CKXTAL244CKXTAL1

LAN

HSIP17HSIN18REFCLK_P19REFCLK_N20EVDD1021HSOP22HSON

16

3D3V_LAN_S5

GPO

41

40

39

38

37

LED0

DVDD10

DVDD33

GPO/SMBALERT

24

23

DVDD10

LED1/EESK

GND

ENSWREG

LED3/EEDO

EECS/SCL

LANWAKE#

11/29 change X3101 to 82.30020.D41

X01-0217 change C3102, C3103 to 15pF

R3116 10KR2J-3-GP

3D3V_LAN_S5

R3103 1KR2J-1-GP

1 2

GIGA

1 2

GIGA

R3114

1 2

10KR2J-3-GP

SMBDATA_LAN

GPO

EEDI/SDA

2

ENSWREG EEDI/SDA

LAN_EECS DVDD10

ISOLATE#

LAN_RST#

2

1

3D3V_LAN_S5

DY

1 2

1

DY

2

PMBS3904-1-GP

1 2

DY

R3108 0R2J-2-GP

X02-0302 Dummy PCIE_CLK_LAN_REQ# circuit

AVDD33_REG

R3107 10KR2J-3-GPR3107 10KR2J-3-GP

1 2

X01-0127 change Q3101 base power rail for leakage issue.

R3102

R3102 10KR2J-3-GP

10KR2J-3-GP

Q3101_B

3

Q3101

DY

11/2 change LAN_REQ# circuit to prevent leakage.

For Switch Regulator enable

3D3V_LAN_S5

R3105

R3105 0R0402-PAD

0R0402-PAD

1 2

DVDD10

PCIE_WAKE# 27

3D3V_LAN_S5

12

R3109

15KR2F-GP

LANXOUT

LANXIN

PCIE_RXP2_C PCIE_RXN2_C

PCIE_TXP2 PCIE_TXN2

DN15ATI Whistler

Title

Size Document Number Rev

A3

Date: Sheet of

R3110

12

1KR2J-1-GP

PCIE_WAKE#

SC15P50V2JN-2-GP

41

C3105

C3104 SCD1U10V2KX-5GPC3104 SCD1U10V2KX-5GP

X3101

X3101 XTAL-25MHZ-155-GP

XTAL-25MHZ-155-GP

2 3

82.30020.D41

SC15P50V2JN-2-GP

SCD1U10V2KX-5GP

1 2 1 2

Reserved

Enrico Caruso 14

PCIE_CLK_LAN_REQ# 20

R3123

12

10KR2J-3-GP

R3106

R3106 0R2J-2-GP

0R2J-2-GP

DY

3D3V_S0

DY

C3102

1 2

C3103

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_LAN_S5

R312210KR2J-3-GP

12

PCIE_RXP2 20 PCIE_RXN2 20

PCIE_TXP2 20 PCIE_TXN2 20

CLK_PCIE_LAN 20 CLK_PCIE_LAN# 20

31 105Wednesday, April 13, 2011

A00

5

SSID = SDIO

4

3

2

1

XD_D7

XD_D6/MS_BS

22

23

XD_D7

CLK_IN

XD_CD#7SP18SP29SP310SP411SP5

XD_D5/SD_D2/MS_D5

XD_D4/SD_D3/MS_D1

XD_D3/SD_D4/MS_D4

SP1119SP1220SP1321SP14

18

SP10

17

GPIO0

16

SP9

15

SP8

14

SP7

13

SP6

12

71.05138.003

XD_ALE/SD_D7/MS_D3

XD_CLE/SD_D0/MS_D7

XD_CE#/SD_D1

XD_RE#/MS_INS#

XD_RDY/SD_WP/MS_CLK_R

XD_CD#

D D

11/ 17 dummy C3204 and C3209

3D3V_S0

43mA

12

C3203

C3204

DY

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

C C

Close to chip

3D3V_CARD_S0

12

C3206

SCD1U10V2KX-5GP

CLK_PCH_48M20

3D3V_CARD_S0

250mA

Vendor recommand

C3207

SC4D7U6D3V3KX-GP

C3209

DY

RREF

1 2

SC100P50V2JN-3GP

R3201

1 2

6K2R2F-GP

USB_PN5_R USB_PP5_R

12

C3208

12

1 2 3 4 5

V18

6

25

SC1U6D3V2KX-GP

24

U3201

RREF DM DP 3V3_IN CARD_3V3 V18

GND

RTS5138-GR-GP

1

TP3204 TPAD14-GPTP3204 TPAD14-GP

XD_D6/MS_BS 74

XD_D5/SD_D2/MS_D5 74

XD_D4/SD_D3/MS_D1 74

1

TP3205 TPAD14-GPTP3205 TPAD14-GP

XD_D2/SD_CMD CR_GPIO0 XD_D1/SD_D5/MS_D0 XD_D0/SD_CLK/MS_D2 XD_WP/SD_D6/MS_D6 XD_WE#/SD_CD#

1

XD_D2/SD_CMD 74

TP3201 TPAD14-GPTP3201 TPAD14-GP

1

XD_D1/SD_D5/MS_D0 74 XD_D0/SD_CLK/MS_D2 74

1

TP3206 TPAD14-GPTP3206 TPAD14-GP

XD_WE#/SD_CD# 74

XD_ALE/SD_D7/MS_D3 74

XD_CLE/SD_D0/MS_D7 74

XD_CE#/SD_D1 74

XD_RE#/MS_INS# 74

TP3203 TPAD14-GPTP3203 TPAD14-GP

R3208

1 2

0R2J-2-GP

XD_RDY/SD_WP/MS_CLK 74

11/22 vendor recommand

11/1 Add R3210, C3210 for EMI

Close U3201

B B

A A

5

CLK_PCH_48M

R3210

C3210

12

DY

10R2J-2-GP

CLK_PCH_48M_R

12

DY

SC10P50V2JN-4GP

4

USB_PN5_R

USB_PP5_R

4

1

3

TR3201

DLW21HN900SQ2LGP-U

68.00201.141

2

USB_PN5 18

USB_PP5 18

X02-0311 stuff TR3201 and change symbol to 68.00201.141

A00-0324 change TR6102 to TR3201

A00-0406 remove R3206, R3207 PAD

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Card Reader-RTS5138

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Card Reader-RTS5138

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

1

A00

32 105Wednesday, April 13, 2011

A00

A

4 4

3 3

B

C

D

E

(Blanking)

2 2

1 1

A

B

C

D

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

E

33 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

34 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

35 105Wednesday, April 13, 2011

A00

5

IMVP_PWRGD27,42

SSID = Reset.Suspend

20101206 X02:

D D

Add Q3603 for RTC power sequence.

PS_S3CNTRL

S0_PWR_GOOD19,27

G

S

Q3603

2N7002K-2-GP

3

4

D

12/16 Add Q3603 to meet RTC sequence as DN13

2

DY

1

D3602

BAS16-6-GP

83.00016.K11

2ND = 83.00016.F11

R3614

1 2

0R0402-PAD

SCD01U50V2KX-1GP

SYS_PWROK

C3612

DY

12

X02-0303 change 0R to short pad

Power Sequence

SYS_PWROK 19

3

1D05V_VTT

H_CPUPWRGD5,22

3V_5V_EN41

DY

12

2

1 2

R3602

200KR2J-L1-GP

R3601

DY

H_PWRGD_R

1KR2J-1-GP

R3603 1KR2J-1-GPR3603 1KR2J-1-GP

R3622

56R2J-4-GP

C3602

2ND = 83.00016.F11

83.00016.K11

BAS16-6-GP

2

3

1

D3601

1 2

1

12

E

B

DY

Q3601

12

CHT2222APT-GP

C

DY

SCD1U10V2KX-5GP

H_THERMTRIP# 5,22,85

PURE_HW_SHUTDOWN# 27,28

S5_ENABLE 27

ROSA Run Power

C C

3D3V_AUX_S5

R3606

1 2

2nd = 84.DM601.03F

B B

1.5V_RUN for VGA Comsumption Peak current 7.39A

+1.5V_RUN_CPU Comsumption Peak current 3A

+1.5V_RUN for Mini-Card Comsumption Peak current 1A

A A

PM_SLP_S3#19,27,37,47

RUN_ENABLE

PS_S3CNTRL

100KR2J-1-GP

Q3602

2N7002KDW-GP

84.2N702.A3F

5

6

123 4

GGDD

S

PS_S3CNTRL 37

S

15V_S5

R3604

R3604 100KR2J-1-GP

100KR2J-1-GP

1 2

R3605

1 2

R3607

1 2

10KR2J-3-GP

R3630

1 2

10KR2J-3-GP

SCD01U50V2KX-1GP

4

5V_RUN_ENABLE

10KR2J-3-GP

12

3D3V_S5

3.3V_RUN_ENABLE

12

C3605

C3605 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1D5V_S3 1D5V_S0

1.5V_RUN_ENABLE

12

C3610

AO4468 MAX 9A

Rds(on) = 18.5mOhm

2nd = 84.08882.037

5V_S5 5V_S0

84.04468.037

AO4468-GP

6

D

7

D

8

D

C3608

C3608 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

Rds(on) = 18.5mOhm AO4468 MAX 11.6A

2nd = 84.08882.037

84.04468.037

AO4468-GP

6

D

7

D

8

D

TPCA8062-H-GP MAX 28A Rds(on) = 4.1~5.4m OHM

D S

8

D

7

D

6

POWERPAK-8P-GP

U3602

U3606

U3601

G D

G D S

S S

S

S S

S GD

GD

45

G D

3

S

2

S

1

S

3D3V_S0

45 3 2 1

12

1 2 3 45

X02-0314 Change U3606 footprint.

3

5V_S0

+5V_RUN Comsumption Peak current 7.73A

12

C3603

C3603 SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

3D3V_S0

+3.3V_RUN Comsumption Peak current 8.14A

C3604

C3604 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D5V_S0

MAX Current ? mA Design Current ? mA

Total= 11.39A

12

C3609

C3609 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

Power Plane Enable

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

36 105

1

A00

5

Close to CPU S3 Power Reduction Circuit Processor VREF_DQ Implementation

D D

M_VREF_DQ_DIMM0

C C

PS_S3CNTRL36

1 2

R3708 0R0402-PADR3708 0R0402-PAD

2N7002K-2-GP

G

S

Q3704

84.2N702.J31

2ND = 84.2N702.031

D

+V_SM_VREF

0D75V_EN

PM_SLP_S3#19,27,36,47

R3707

R3707 0R2J-2-GP

0R2J-2-GP

1 2

Q3708

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

R3716 22R2J-2-GP

DY

RUN_ENABLE

1 2

DY

4

S

G

1 2

1.05VTT_PWRGD 45,48

12

R3710

R3710 0R0402-PAD

0R0402-PAD

12

C3705

C3705 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

+V_SM_VREF_CNT 9

R3705

R3705 100KR2J-1-GP

100KR2J-1-GP

X02-0303 change 0R to short pad

0D75V_EN 46

3

PS_S3CNTRL36

SM_DRAMRST#5

2

Close to DIMM S3 Power Reduction Circuit SM_DRAMPWROK

0D75V_S0

12

R3703

R3703 22R2J-2-GP

22R2J-2-GP

Q3701_D

D

Q3701

Q3701 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

G

Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK

DY

2ND = 84.2N702.031

84.2N702.J31

Q3703

S

G

2N7002K-2-GP

R3709

1 2

PS_S3CNTRL

0R2J-2-GP

D

1D5V_S3

1D5V_S0

12

R3704

2

12

SM_DRAMRST#_D

12

R3704 220R2J-L2-GP

220R2J-L2-GP

DY

Q3702_D

D

Q3702

Q3702 2N7002K-2-GP

2N7002K-2-GP

84.2N702.J31

DY

2ND = 84.2N702.031

S

G

R3706

R3706 1KR2J-1-GP

1KR2J-1-GP

S3 Power Reduction Circuit SM_DRAMRST#

R3718

1 2

1KR2J-1-GP

C3702

C3702 SC100P50V2JN-3GP

SC100P50V2JN-3GP

DRAMRST_CNTRL_PCH 20

1

DDR3_DRAMRST# 14,15

B B

C3703

DRAMRST_CNTRL_PCH

Close to CPU

3D3V_S0

12

R3713

200R2F-L-GP

PM_DRAM_PWRGD5,19

A A

R3717

1 2

DY

PM_DRAM_PWRGD5,19

SM_DRAMPWROK must have a maximum of 15ns rise or fall time over VDDQ * 0.55

∮∮∮∮

200mV and the edge must be monotonic

5

DY

0R2J-2-GP

0D75V_EN

VDDPWRGOOD_R

U3701

1

B

2

A

3

GND

74LVC1G08GW-1-GP

73.01G08.L04

2nd = 73.7SZ08.DAH

S3 Power Reduction Circuit SM_DRAMPWROK

1D5V_S03D3V_S0

CEKLT V1.0: PCH to 1K,CUP to 200R

12

R3702

200R2F-L-GP

DY

VCC

5

4

Y

4

DY

VDDPWRGOOD_R

R3721

39R2J-L-GP

PS_S3CNTRL

DY

12

Q3707_D

D

G

R3719

1 2

910R2F-GP

Q3707

DY

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

S

12

R3720

R3720 750R2F-GP

750R2F-GP

3

VDDPWRGOOD 5

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

2

Date: Sheet of

12

SCD047U16V2KX-1-GP

Wednesday, April 13, 2011

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

S3 Reduction Circuit

Enrico Caruso 14

37 105

1

A00

5

4

3

5V_S5

2

1

SSID = PWR.Support

1

2

DY

PD3802

PD3802 BAV99-4-GP

BAV99-4-GP

PR3804

DY

3

PSID_DISABLE#_R

DEL PR4305, PSID_DISABLE# 08/13

PR3807

PS_ID

This cap should be used only as last resort for EMI suppression.

12

PC3801

PC3801 SCD1U50V3KX-GP

SCD1U50V3KX-GP

PQ3805

B

R1

DY

PDTA124EU-1-GP

PR3807

1 2

33R2J-2-GP

RCID27

R2

E

C

AD_OFF_R

PR3812

PR3812 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

12

3D3V_S5

PQ3803

G

S

2N7002K-2-GP

DY

Change 09/09

1

2

PD3803

3

BAV99-5-GP-U

D

3D3V_S5

12

PR3806

PR3806 2K2R2J-2-GP

2K2R2J-2-GP

PSID_EC 27

X01-0217 change PU3801 to 84.04407.G37

PU3801

S

1

S

12

PC3804

PR3810

SC1U25V5KX-1GP

PR3811

PR3811 47KR3J-L-GP

47KR3J-L-GP

1 2

2

S

3

G D

4 5

AO4407AL-GP

240KR3-GP

AO4407AL-GP

Id= -10A Qg= -22nC Rdson=14~30mohm

AD++DC_IN

D

8

D

7

D

6

12

PC3805

DY

SCD01U50V2KX-1GP

12

PC3802

DY

SCD01U50V2KX-1GP

12

PC3803

PC3806

SC10U25V6KX-1GP

SCD01U50V2KX-1GP

20100107

1

PQ3801

PR3808

1 2

DY

33R2J-2-GP

20100107

2

PMBS3904-1-GP

PMBS3904-1-GP PQ3802

PQ3802

3

PSID_DISABLE#_R_C

G

SD

12

PR3802

PR3802 10KR2J-3-GP

10KR2J-3-GP

1 2

10KR2J-3-GP

DCin CONN

D D

PR3801

15KR2J-1-GP

PSID_PROTECT

PR3803

100KR2J-1-GP

1 2

FDV301N-NL-GP

D

Modify 0923

X02-0314 Del short pad PAD1 to prevent system burn.

+DC_IN

DCIN1

1

C C

8

2

9

3

10

4

11

5

12

6

13

7

14

ACES-CONN14G-GP

PS_ID_R

PR3809 0R0603-PADPR3809 0R0603-PAD

1 2

PS_ID_R2

When PQ3801 is stuffed, the PR3806 need change to 2.2K 1% resistor

DY

A00

PD3801

11/25

AFTP3812AFTP3812 AFTP3813AFTP3813 AFTP3814AFTP3814

1 1 1

PS_ID_R +DC_IN GND

X02-0309 Change AFTP to follow DV14 AMD

PD3801 P6SBMJ27APT-GP

P6SBMJ27APT-GP

11/25

A K

12/2 change PD3801 to 83.P6SBM.DAG(CHENMKO)

DY

2 1

PD3804

PD3804 B240A-13-GP

B240A-13-GP

PWR_CHG_AD_OFF40

PQ3804

R1

B

DY

R2

PDTC124EU-1-GP

AD_OFF_L

C

E

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

DCIN Jack

1

38 105Wednesday, April 13, 2011

A00

5

SSID = PWR.Support

4

3

2

1

D D

X02-0309 Change AFTP to follow DV14 AMD

BT+

SCD1U50V3KX-GP

merge PR3902~3904 11/18

BAT_SCL27,40 BAT_SDA27,40 BAT_IN#27

C C

DELETE PR3901 11/8

SRN33J-7-GP

4 5 3 2 1

PN3901

EC3904

6 7 8

12

EC3901

DY

12

EC3902

12

DY

SC10P50V2JN-4GP

EC3903

EC3903 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

SC10P50V2JN-4GP

PD3902

DY

SMF18AT1G-GP

A K

11/25

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

AFTP3901AFTP3901

Batt Connecter

BATT1

10

1

BAT_ALERT

1

2 3 4 5 6 7 8 9

11

ALP-CON9-4-GP

1

20.81507.009

AFTP3906AFTP3906

12/2

12/6 swap net for layout

AFTP3902AFTP3902 AFTP3903AFTP3903 AFTP3904AFTP3904 AFTP3905AFTP3905

11/25

B B

For actual location, need to be swap all pin

X02-0309 change AFTP to follow DV14 AMD

PBAT_PRES1#

1

PBAT_SMBDAT1

1

PBAT_SMBCLK1

1

BT+

1

Placement: Close to Batt Connector

BAT_IN#

3

D3902

D3902 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

A A

5

4

2nd = 83.00099.K11

3rd = 83.BAV99.D11

BAT_SDA

3

D3903

D3903 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

3

BAT_SCL

3

D3901

D3901 BAV99-5-GP-U

BAV99-5-GP-U

1

2

83.00099.T11

2nd = 83.00099.K11

3rd = 83.BAV99.D11

3D3V_AUX_KBC

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

BATT CONN

39 105Wednesday, April 13, 2011

1

A00

5

SSID = Charger

4

3

2

1

D D

EE need pull high and net name

AD+

0802 Rename H_PROCHOT#

3D3V_AUX_S5

H_PROCHOT#5,27,42

PWR_CHG_CMPIN

12

PR4029

PR4029 54K9R2F-L-GP

54K9R2F-L-GP

C C

B B

A00-0412 Change PR4029 to 54.9K

PR4029_2

D

PQ4004

PQ4004 2N7002K-2-GP

2N7002K-2-GP

S

G

AD_IA_HW 27

CHG_AGND

PWR_CHG_CMPIN

12

PR4027

PR4027 19K6R2F-GP

19K6R2F-GP

PWR_CHG_CMPIN_R

A00-0412 Change PR4027 to 19.6K

D

PQ4003

PQ4003 2N7002K-2-GP

2N7002K-2-GP

S

G

CHG_AGND

PQ4005

PQ4005 2N7002A-7-GP

2N7002A-7-GP

G

A00-0412 stuff PQ4005

S D

AD_IA_HW2 27

11/15

12

PR4037

DY

100KR2J-1-GP

A00-0412 dummy PR4037

PWR_CHG_CMPOUT

AD+

PR4007

316KR2F-GP

PR403149K9R2F-L-GP PR40 3149 K9R2F-L-GP

3D3V_AUX_S5

12

PR4017

PR4017 100KR2J-1-GP

100KR2J-1-GP

12

PR4023

PR4023 59KR2F-GP

59KR2F-GP

CHG_AGND

ROSA

Adapter Type

12

CHG_AGND

65W

90W

A A

EC code only BQ24707

H_PROCHOT# AD_IA_HW2

65W

90W

130W

AD_IA_HW

0 0

1 0

0 1

5

130W

X01-0217 change PU4002, PU4003 to 84.04407.G37

PU4002

S

D

S

D D

D

AO4407AL-GP

PQ4002

3 4

2

1

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12

PR4011

PR4011 19K1R2F-GP

19K1R2F-GP

12

R4013

R4013 49K9R2F-L-GP

49K9R2F-L-GP

CHG_AGND

1

S

2

S

3

GD

45

5

6

BAT_SCL27,39

BAT_SDA27,39

AD+_G_2

PR4008

20R5J-GP

1 2

PR4010 20R5J-GPPR4010 20R5J-GP

PWR_CHG_REGN

120KR2F-L-GP

PG4007 GAP-CLOSE-PWR-3-GPPG4007 GAP-CLOSE-PWR-3-GP

PG4008 GAP-CLOSE-PWR-3-GPPG4008 GAP-CLOSE-PWR-3-GP

8 7 6

Id= -10A Qg= -22nC

PR4004

Rdson=14~13mohm

1 2

10KR2J-3-GP

DC_IN_D

PWR_CHG_ACOK

PWR_CHG_IOUT

12

PC4012

SCD01U50V2KX-1GP

A00-0412 Change PR4013 to 49.9K

A00-0412 stuff PR4030& PR4032

PWR_CHG_AD_OFF38

3D3V_AUX_S5

PWR_CHG_REGN

12

PR4026

PQ4001

PQ4001 2N7002A-7-GP

2N7002A-7-GP

DY

G

S D

EE need check pull high

CHG_AGND

PR4023

24K

33.2K

59K

PR4026

DY

100KR2J-1-GP

PWR_CHG_CMPOUT

AC_IN#27

PWR_CHG_REGN

12

PR4025

PR4025 100KR2J-1-GP

100KR2J-1-GP

DY

12

DY

PC4001

SCD1U25V3KX-GP

PR4034 can dummy if you use external 10mW

X01-0127 DY PQ4007, PR4038, PR4039 for new version BQ24707

4

12

PR4003

100KR2J-1-GP

PR4001

1 2

10KR2F-2-GP

AD+_G_1

PR4030

100KR2J-1-GP

PR4032

DY

1 2

3D3V_AUX_S5

12

PWR_CHG_CMPOUT

12

0R2J-2-GP

PR4035

10KR2F-2-GP

12

PR4034

PR4034 100KR2J-1-GP

100KR2J-1-GP

12

PR4033

120KR2F-L-GP

DY

CHG_AGND

PWR_CHG_VCC

12

PC4010

CHG_AGND

SCD47U25V3KX-2GP

PWR_CHG_ACDET

12

PR4014

3D3MR2J-GP

PWR_CHG_CMPIN

PWR_CHG_BAT_SCL

PWR_CHG_BAT_SDA

PWR_CHG_ILIM

PWR_CHG_IFAULT

12

DY

PR4018

11/29

BOM merge 12/15

D

DY

2N7002K-2-GP

PC4003

PQ4007

PG4002

12

DY

SC1U25V3KX-1-GP

20

10

11

AD+_TO_SYS

CHG_AGND

6

3

4

9

8

5

G

S

1 2

PR4002

PR4002 D01R2512F-4-GP

D01R2512F-4-GP

12

PR4006

0R2J-2-GP

12

DY

GAP-CLOSE-PWR-3-GP

1 2

PC4002

SCD1U25V2KX-GP

12

PC4004

SC1U25V3KX-1-GP

PWR_CHG_ACP

2

PU4005

ACP

VCC

ACDET

CMPOUT

CMPIN

SCL

BQ24707ARGRR-GP

SDA

ILIM

IFAULT#

ACOK#

GND

21

CHG_AGND

AD+

12

PR4038

316KR2F-GP

DY

12

PR4039

49K9R2F-L-GP

DY

DCBATOUT

12

PG4003

GAP-CLOSE-PWR-3-GP

12

PC4024

SC1U25V3KX-1-GP

PWR_CHG_ACN

CHG_AGND

1

ACN

17

BTST

16

REGN

18

HIDRV

19

PHASE

15

LODRV

13

SRP

12

SRN

7

IOUT

GND

14

PG4011

1 2

GAP-CLOSE-PWR

CHG_AGND

PWR_CHG_ACOK27

3

PR4009

0R3J-0-U-GP

1 2

PWR_CHG_BTST

PWR_CHG_HIDRV

PWR_CHG_LODRV

PWR_CHG_SRP

PWR_CHG_SRN

PWR_CHG_IOUT

PR4024

DY

PD4001

SD103AWS-1-GP

K A

PC4011_1

12

PC4011

delete net name 11/10

delete net name 11/15

PR4022

PR4022 0R2J-2-GP

0R2J-2-GP

1 2

12

8K45R2F-2-GP

12

PC4022

SC220P50V2JN-3GP

CHG_AGND

3D3V_AUX_S5

12

PR4019

PR4019 100KR2J-1-GP

100KR2J-1-GP

PWR_CHG_REGN

11/18

SCD047U25V2KX-GP

PR4021

1 2

10R2F-L-GP

PR4020

1 2

7D5R2F-GP

PWR_CHG_REGN

12

PR4028

DY

100KR2J-1-GP

12

PR4036

DY

120KR2F-L-GP

11/10

1 2

PC4007

SC1U25V3KX-1-GP

AD_IA 27

1 2

PG4004

DY

1 2

PC4013

PC4013 SC3300P50V3KX-1GP

SC3300P50V3KX-1GP

12

PC4020

SCD1U25V2KX-GP

DY

CHG_AGND

PC4021

SCD1U25V2KX-GP

12

PC4023

SCD1U25V2KX-GP

CHG_AGND

D

S

G

2

AD+

12

PR4005

PR4005 470KR2J-2-GP

1 2

PG4005

GAP-CLOSE-PWR-3-GP

1 2

PG4001

PG4006

GAP-CLOSE-PWR-3-GP

678

DDD

PU4004

AO4496-GP

SSS

GD

SSS

GD

123

4 5

470KR2J-2-GP

PWR_DCBATOUT_CHG

12

PC4008

PC4006

SC10U25V5KX-GP

Charger Current=1.4~3.6A

PL4001

PL4001 IND-5D6UH-52-GP

IND-5D6UH-52-GP

BT+_RPWR_CHG_PHASE

1 2

678

DDD

PU4001

AO4496-GP

SSS

GD

SSS

GD

123

4 5

PWR_CHG_CSOP_1

X01-0217 change PU4001, PU4004 to 84.04496.037

12

PWR_CHG_CSON_1

Add net name 11/10

PQ4006

PQ4006 2N7002K-2-GP

2N7002K-2-GP

AC_IN#

1 2

PR4016

PR4016 D01R2512F-4-GP

D01R2512F-4-GP

1 2

PG4009

GAP-CLOSE-PWR-3-GP

Title

Size Document Number Rev

Custom

Date: Sheet of

PU4003

S

1

S

2

S

3

G D

4 5

AO4407AL-GP

Id= -10A Qg= -22nC Rdson=14~13mohm

12

DY

PC4026

PC4014

SC10U25V5KX-GP

1 2

PG4010

GAP-CLOSE-PWR-3-GP

CHARGER BQ24707

Enrico Caruso 14

BT+

D

8

D

7

D

6

12

PC4009

DY

PC4025

SC10U25V5KX-GP

12

PC4015

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

EC4001

DY

SCD1U50V3KX-GP

SC2200P50V2KX-2GP

BT+

12

DY

PC4016

PC4017

SC10U25V5KX-GP

40 105Wednesday, April 13, 2011

EC4002

SCD1U25V2ZY-1GP

12

PC4019

PC4018

SCD1U50V3KX-GP

SC10U25V5KX-GP

A00

A

SSID = PWR.Plane.Regulator_3p3v5v

4 4

3D3V_S5

1 2

3 3

2 2

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: 2.2U PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =10Arms 68.2R210.20B O/P cap: 330U6.3V M6.3*5.7 15mOhm 3.16Arms Matsuki/77.53371.04L H/S: SIS412DN / 24mohm/30mOhm@4.5Vgs/ 84.00412.037 L/S: SI7716ADN / 13.5mohm/16.5mOhm@4.5Vgs/ 84.07716.037

1 1

DCBATOUT

GAP-CLOSE-PWR-3-GP

3D3V_PWR

GAP-CLOSE-PWR-3-GP

PG4102

GAP-CLOSE-PWR-3-GP

PG4105

GAP-CLOSE-PWR-3-GP

PG4107

GAP-CLOSE-PWR-3-GP

PG4108

GAP-CLOSE-PWR-3-GP

PG4110

GAP-CLOSE-PWR-3-GP

PG4113

GAP-CLOSE-PWR-3-GP

Design Current = 4.5A 7A<OCP< 8.4A

3D3V_PWR 5V_PWR

12

PC4119

SCD1U10V2KX-5GP

Close to VFB Pin (pin5)

DCBATOUT

12

PR4126

PR4126 40K2R2F-GP

40K2R2F-GP

DY

PU4101_5

0629 Modify

12

PR4127

DY

750KR2F-GP

12

PG4103

1 2

PG4104

1 2

PG4106

1 2

PG4109

1 2

PT4103

SE330U6D3VM-15-GP

PT4103

SE330U6D3VM-15-GP

PR4113

6K65R2F-GP

PR4117

10KR2F-2-GP

PU4105

DY

6

2N7002KDW-GP

84.2N702.A3F

A

PWR_3D3V_DCBATOUT

PC4109

SCD01U50V2KX-1GP

12

12/15

PL4102

COIL-2D2UH-27-GP

12

PG4121

2D2R5F-2-GP

GAP-CLOSE-PWR-3-GP

SC330P50V2KX-3GP

12

PR4114

PR4114 0R2J-2-GP

0R2J-2-GP

DY

51125_FB2_R

12

PC4125

PC4125 SC18P50V2JN-1-GP

SC18P50V2JN-1-GP

DY

12

Vz=5.1V

PWR_5V3D3V_EN0

PU4101_2

2345

0629 Modify

1

PC4110

SC10U25V5KX-GP

PC4110

SC10U25V5KX-GP

PR4111

11/18

PC4121

DCBATOUT

DY

PC4130

SC10U25V5KX-GP

PC4130

SC10U25V5KX-GP

12

DY

PD4105

PD4105 MMPZ5231BPT-GP

MMPZ5231BPT-GP

1 2

12

PR4105

PR4105 100KR2F-L1-GP

100KR2F-L1-GP

3V_5V_EN36

12

12/15

678

DDD

PU4102

PU4102 FDMC8884-GP

FDMC8884-GP

SSS

G D

SSS

G D

123

4 5

12

PR4111_2

12

8

D

SSS

123

3D3V_PWR_2

PU4103

567

FDMC7696-GP

DDD

G

4

12/15

51125_VREF

3D3V_PWR_2

1 2

PR4104 10KR2J-3-GPPR4104 10KR2J-3-GP

PR4108

PWR_5V3D3V_EN0

PR4109

PC4113

SCD1U25V3KX-GP

PWR_3D3V_VBST2_1

12

DY

PR4121 0R0402-PADPR4121 0R0402-PAD

PR4122 0R0402-PADPR4122 0R0402-PAD

TPS51125:

TONSEL

GND

VREF

VREG3

VREG5

RT8205B:

TONSEL

GND

VREF

VREG3

VREG5

B

PQ4101

2N7002K-2-GP

ALW_ON_1

TPS51125 RT8205B

DY ASM

TPS51125 RT8205B

0R3J 4R7

0826

PR4109

PWR_3D3V_VBST2

1 2

2D2R3J-2-GP

PWR_3D3V_DRH2

PWR_3D3V_LL2

PWR_3D3V_DRVL2

PWR_3D3V_VO2

PWR_3D3V_FB2

PWR_5V3D3V_EN0

1 2

DY

PR4101 820KR2F-GP

PWR_3D3V_ENTRIP2

51125_VREF

PC4123

SCD22U10V2KX-1GP

PC4123

SCD22U10V2KX-1GP

12

PWR_5V3V_TONSEL

PWR_5V3V_SKIPSEL

3D3V_PWR_2

PR4118

12

0R2J-2-GP

12

PR4123

12

DY

0R2J-2-GP

PR4124

12

DY

0R2J-2-GP

TPS51125 RT8205B

DYPR4118

PR4121 ASM

200kHz

245kHz

300kHz

365kHz

CH1 CH2

200kHz

300kHz

365kHz 460kHz

365kHz

B

X01-0217 change PR4103 to 100K(F)

PWR_3D3V5V_ENTRIP

G

12

PR4106

PR4106 200KR2J-L1-GP

200KR2J-L1-GP

DY

PR4108

1 2

DY

820KR3J-GP

10

11

12

13

14

PG4127

1 2

GAP-CLOSE-PWR-3-GP

ASM DY

CH2CH1

265kHz

305kHz

375kHz

460kHz

250kHz

375kHz

D

PU4101

9

7

5

6

3

4

PC4126

12

PC4105

DY

S

VBST2

DRVH2

LL2

DRVL2

TPS51125ARGER-GP

VO2

VFB2

EN0

ENTRIP2

VREF

TONSEL

SKIPSEL

PWR_5V_DCBATOUT

16

VIN

VBST1

DRVH1

DRVL1

PGOOD

ENTRIP1

VREG3

VREG5

8

17

3D3V_AUX_S5_5_51125

12

PC4127

SC4D7U6D3V5KX-3GP

12/13

PC4114

12

LL1

VO1

VFB1

GND

VCLK

SC10U10V5KX-2GP

SC18P50V2JN-1-GP

SC10U25V5KX-GP

12

22

21

20

19

24

2

23

1

15

25

18

5V_AUX_S5

12/20 changePC4126 to 78.47520.51L

SKIPSEL GNDVREG3 or VREG5

Operating

OOA Auto Skip Auto Skip

Mode

Operating

enable both

Mode

LDOs, VCLK on and ready to turn on switcher channels

460kHz

3D3V_PWR_2

12

PR4102

PR4102 100KR2J-1-GP

100KR2J-1-GP

PWR_5V_ENTRIP1

12

PR4103

PR4103 100KR2F-L1-GP

100KR2F-L1-GP

11/18

PC4115

SCD01U50V2KX-1GP

PWR_5V_VBST1

PWR_5V_DRVH1

PWR_5V_LL1

PWR_5V_DRVL1

PWR_5V_VO1

PWR_5V_FB1

3V_5V_POK

PWR_5V_ENTRIP1

PWR_5V3D3V_VLK

6

123 4

TPS51125 RT8205B

PR4110

1 2

0R3J-0-U-GP

5

PWR_3D3V_ENTRIP2

PC4108

SC18P50V2JN-1-GP

0R3J 4R7

PWR_5V_VBST1_1

PR4125

PR4125 0R0402-PAD

0R0402-PAD

VREF(2V)

OpenEN0 820k to GND



enable both LDOs, VCLK off and ready to turn on switcher channels

C

12/10 EE change for BOM merge

PQ4102

PQ4102 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12

PR4107

PR4107 91KR2F-GP

DY

91KR2F-GP

11/18

SCD1U25V3KX-GP

SCD1U25V3KX-GP PC4118

PC4118

1 2

3D3V_PWR_2

12

PR4119

PR4119 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_S53D3V_PWR_2

12

PWM only

GND

disable all circuit

C

D

PWR_5V3D3V_VLK

PWR_5V_DCBATOUT

PC4112

SCD1U50V3KX-GP

PC4112

PC4116

SC10U25V5KX-GP

PC4116

SC10U25V5KX-GP

PC4117

SC10U25V5KX-GP

PC4117

SC10U25V5KX-GP

12

123

45

D1D1D1

G1

D1D1D1

G1

PU4104

Q1

S1/D2

9

PU4104 FDMS3604S-GP

FDMS3604S-GP

PHASE

Q2

S2S2S2

G2

S2S2S2

G2

678

PL4103

1 2

IND-1D5UH-34-GP

68.1R510.10J

12

DY

PR4112

11/10

2D2R5F-2-GP

11/18

PR4112_2

12

PC4122

DY

SC560P50V-GP

SCD1U50V3KX-GP

PC4132

SC10U25V5KX-GP

PC4132

SC10U25V5KX-GP

PC4131

SC10U25V5KX-GP

PC4131

SC10U25V5KX-GP

12

Design Current = 16A

25.1A<OCP< 29.3A

GAP-CLOSE-PWR-3-GP

12

PG4122

GAP-CLOSE-PWR-3-GP

PT4101

12

ST220U6D3VDM-15GP

ST220U6D3VDM-15GP PC4120

PC4120

SCD1U10V2KX-4GP

12

SC1KP50V2KX-1GP

PD4101

BAT54S-5-GP

15V_PWR

PG4112

GAP-CLOSE-PWR-3-GP

1 2

PD4103

BZT52C15S-GP

DY

11/18

PT4104

12

ST220U6D3VDM-15GP

PC4102

A K

X02-0310 stuff PC4120

12

PR4115

0R2J-2-GP

DY

12

PR4116

PR4116 33KR2F-GP

33KR2F-GP

PWR_5V_FB1_R

12

PC4124

DY

SC18P50V2JN-1-GP

DY

12

PR4120

PR4120 21K5R2F-GP

21K5R2F-GP

Close to VFB Pin (pin2)

I/P cap:10U 25V K0805 X5R/ 78.10622.51L Inductor: 1.50UH PCMC104T-1R5 Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J O/P cap: 220U 6.3V PSLV0J227M 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037

D

E

12

SCD1U25V3KX-GP

PC4103_2

3

2

12

PC4106

SC1U25V3KX-1-GP

DCBATOUT

GAP-CLOSE-PWR-3-GP

Title

Size Document Number Rev

A2

Date: Sheet of

12

PC4103

1

1 2

SCD1U25V3KX-GP

11/1811/18

PC4104_2

3

1

2

PC4101_1

11/18

12

PC4101

SCD1U25V3KX-GP

PWR_5V_DCBATOUT

PG4111

PG4114

PG4116

PG4130

PG4131

PG4132

PG4133

PG4134

PG4135

PG4136

PG4137

TPS51125_5V/3D3V

Enrico Caruso 14

E

PC4104

PD4102

PD4102 BAT54S-5-GP

BAT54S-5-GP

5V_PWR15V_S5

12

PC4107

PC4107 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

5V_PWR

PG4119

41 105Wednesday, April 13, 2011

1 2

PG4118

1 2

PG4101

1 2

PG4120

1 2

PG4123

1 2

PG4124

1 2

PG4125

1 2

PG4126

1 2

PG4138

1 2

PG4139

1 2

PG4140

1 2

PG4141

1 2

PG4142

1 2

PG4143

1 2

PG4144

1 2

PG4145

1 2

PG4146

1 2

GAP-CLOSE-PWR-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5V_S5

A00

5

SSID = CPU.Regulator

4

3

2

1

12

PR4204

PR4204 1R2F-GP

1R2F-GP

SCD1U25V3KX-GP

GND_1316

PWR_VCORE_DB043 PWR_VCORE_DB143 PWR_VCORE_DB243

1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

5V_S5

12

PR4205

PR4205 1R2F-GP

1R2F-GP

12

PC4213

SCD1U25V3KX-GP

GND_1316

PWR_VCORE_VDD5

PWR_VCORE_VDD3 PWR_VCORE_VDD3

PWR_VCORE_IMON1 PWR_VCORE_IMON2

DB0_GFX44 DB1_GFX44 DB2_GFX44

PWR_VCORE_R_OSC PWR_VCORE_R_REF1 PWR_VCORE_R_REF2

PWR_VCORE_R_SEL0 PWR_VCORE_R_SEL1 PWR_VCORE_R_SEL2 PWR_VCORE_R_SEL3 PWR_VCORE_R_SEL4 PWR_VCORE_R_SEL5 PWR_VCORE_R_SEL6

3D3V_S01D05V_VTT

PR421210KR2F-2-GP PR421210KR2F-2-GP

PR420910KR2F-2-GP PR420910KR2F-2-GP

PR420854D9R2F-L1-GP PR420854D9R2F-L1-GP

PR4210130R2F-1-GP PR4210130R2F-1-GP

12

PC4201

PU4201

12

VDD5

43

VDD3

42

VDD3

21

IMON1

25

IMON2

37

DB10

36

DB11

35

DB12

33

DB20

32

DB21

31

DB22

24

IDES1_N

23

IDES1_P

27

IDES2_N

28

IDES2_P

41

R_OSC

22

R_REF1

26

R_REF2

2

R_SEL0

1

R_SEL1

48

R_SEL2

47

R_SEL3

46

R_SEL4

45

R_SEL5

44

R_SEL6

VT1316MAFQX-041-GP

11/18

TEMP_SENSE1 TEMP_SENSE2

SPHASE1_0 SPHASE1_1 SPHASE1_2

VR_ENABLE

VR1_READY VR2_READY

DCMDRP1 DCMDRP2

SENSE1-

SENSE1+

SENSE2-

SENSE2+

SPHASE2

VCLK VDIO

VR_TT#

ALERT#

NC#17 NC#20

GND GND GND

18 19

PWR_VCORE_SENSE1-

14

PWR_VCORE_SENSE1+

13

PWR_VCORE_SENSE2-

15

PWR_VCORE_SENSE2+

16

PWR_VCORE_TEMP_SENSE1

29 30

40 39 38 34

5 4

6 10 8

PWR_VCORE_VR2_DELAY

9

7

17 20

49 11 3

GND_1316

12

PC4218

SCD047U25V2KX-GP

12

SCD047U25V2KX-GP

12

PR4233

1 2

5K76R2F-2-GP

PC4219

12

Delete PR4212 Pull-up 200 R of ALL_SYS_PWRGD

PWR_VCORE_DCMDRP1 PWR_VCORE_DCMDRP2

PR4217 0R0402-PADPR4217 0R0402-PAD

1 2

PR4218 0R0402-PADPR4218 0R0402-PAD

1 2

PR4219 0R0402-PADPR4219 0R0402-PAD

1 2

PR4220 0R0402-PADPR4220 0R0402-PAD

1 2

TEMP_SENSE_GFX

PWR_VCORE_TEMP_SENSE1_R

12

PR4238

43K2R2F-L-GP

1 2

PR4223 100KR2F-L1-GPPR4223 100KR2F-L1-GP

12

PR4239

PR4239 NTC-220K-2-GP

NTC-220K-2-GP

NTCG104QH224HT

VSSSENSE 8 VCCSENSE 8 VSS_AXG_SENSE 9 VCC_AXG_SENSE 9

PR4254

1 2

0R0402-PAD

PWR_VCORE_SPHASE_0 43 PWR_VCORE_SPHASE_1 43

SPHASE_GFX 44

D85V_PWRGD 48

IMVP_PWRGD 27,36

VR_SVID_ALERT# 8

1D05V_VTT

12

PR4243

PR4243 48K7R3F-1-GP

48K7R3F-1-GP

0R0402-PAD

H_CPU_SVIDCLK 8

H_CPU_SVIDDAT 8

H_PROCHOT# 5,27,40

H_PROCHOT#

12/2

TEMP_SENSE_GFX_R

12

PR4255

61K9R2F-GP

12/17 change PR4246 to 475K(1%) as DN13

1D05V_VTT

PWR_VCORE_DB1

12

PR4244

PR4244 221KR2F-GP

221KR2F-GP

1 2

PR4224 100KR2F-L1-GPPR4224 100KR2F-L1-GP

12

PR4256

PR4256 NTC-220K-2-GP

NTC-220K-2-GP

NTCG104QH224HT

12/2

20101012

12

PR4245

PR4245 158KR2F-GP

158KR2F-GP

H_PROCHOT#

DB1_GFX

12

PR4246

PR4246 475KR3F-GP

475KR3F-GP

3D3V_PWR

D D

1D05V_VTT

12

PR4215

DY

100R2F-L1-GP-U

20101012

12

C C

B B

PR4221

PR4221 7K87R2F-GP

7K87R2F-GP

PC4214

GND_1316

PC4231

12

SCD022U16V2KX-3GP

1 2

PG4203

PG4203 GAP-CLOSE-PWR

GAP-CLOSE-PWR

DY

SCD022U16V2KX-3GP

12

PR4216

PR4216 100R2F-L1-GP-U

100R2F-L1-GP-U

12

GND_1316

12/2

12

PR4222

PR4222 8K87R2F-2-GP

8K87R2F-2-GP

20101012

GND_1316

PWR_VCORE_IDES1_N PWR_VCORE_IDES1_P

PR4225130KR2F-GP PR4225130KR2F-GP PR422644K2R2D-GP PR422644K2R2D-GP PR422944K2R2D-GP PR422944K2R2D-GP

PR423123K7R2F-GP PR423123K7R2F-GP PR423249K9R2F-L-GP PR423249K9R2F-L-GP PR423439K2R2F-L-GP PR423439K2R2F-L-GP PR423532K4R2F-1-GP PR423532K4R2F-1-GP PR423627K4R2F-GP PR423627K4R2F-GP PR423739K2R2F-L-GP PR423739K2R2F-L-GP PR42013K74R2F-GP PR42013K74R2F-GP

PWR_VCORE_IDES1_N43 PWR_VCORE_IDES1_P43

IDES_N_GFX44 IDES_P_GFX44

1

PWR_VCORE_DCMDRP2

12

PC4229

PC4229 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

42 105Wednesday, April 13, 2011

A00

PWR_VCORE_DCMDRP1

12

PR4249

PR4249 1K54R2F-GP

1K54R2F-GP

GND_1316

A A

12

DELETE 11/8

Title

Size Document Number Rev

A3

Date: Sheet of

5

4

3

2

Date: Sheet of

20101012

PC4228

PC4228 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

VT1316+1314_CPU_CORE(1/3)

Enrico Caruso 14

12

PR4250

PR4250 5K11R2F-L1-GP

5K11R2F-L1-GP

GND_1316

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5

X01-0217 change PR4202, PR4213, PR4230 PR4247 to 7.5K(F)

20101012

D D

20101012

C C

PWR_VCORE_IDES1_N42

PWR_VCORE_IDES1_P42

B B

A A

PWR_VCORE_IDES1_N

PWR_VCORE_IDES1_P

5

PR4202

1 2

7K5R2F-1-GP

PWR_VCORE_IDES1_N_2

1 2

PC4202 SC1KP50V2KX-1GPPC4202 SC1KP50V2KX-1GP

PR4213

1 2

7K5R2F-1-GP

PC4212

1 2

SC1KP50V2KX-1GP

PR4230

20101012

SC1KP50V2KX-1GP

1 2

7K5R2F-1-GP

PC4216 SC1KP50V2KX-1GPPC4216 SC1KP50V2KX-1GP

PR4247

1 2

7K5R2F-1-GP

PC4227

1 2

4

PR4203

1 2

9K31R2F-GP

PWR_VCORE0_IDES_P_1

PR4206

3K09R2F-1-GP

PR4214

1 2

9K31R2F-GP

PWR_VCORE_IDES0_P_1

1 2

PWR_VCORE_IDES1_N_1

1 2

PWR_VCORE1_IDES_P_1

3K09R2F-1-GP

1 2

PWR_VCORE_IDES1_P_1

5V_S5

4

12

PR4227

9K31R2F-GP

PR4241

PR4248

9K31R2F-GP

PR4242

1 2

10R2J-2-GP

SCD1U25V3KX-GP

PC4203

PC4203 SC4700P50V2KX-1GP

SC4700P50V2KX-1GP

PWR_VCORE0_IDES_N

PWR_VCORE0_IDES_P

PWR_VCORE_DB042 PWR_VCORE_DB142 PWR_VCORE_DB242

PWR_VCORE_SPHASE_042

5V_S5

1 2

12

PC4217

PC4217 SC4700P50V2KX-1GP

SC4700P50V2KX-1GP

12

PWR_VCORE1_IDES_N PWR_VCORE1_IDES_P

PWR_VCORE_DB042 PWR_VCORE_DB142 PWR_VCORE_DB242

PWR_VCORE_SPHASE_142

12

PC4230

GND_1317S_2

PR4211

10R2J-2-GP

SCD1U25V3KX-GP

PU4203_AVDD

PU4202_AVDD

PC4215

GND_1317S_2

PU4202_AVDD

12

GND_1317S_1

A5 A4

A6 A1 B1

B6

A3

B3 B4 B5

3

GND_1317S_1

PU4203

IDES_N IDES_P

DB0 DB1 DB2

SPHASE

AVDD

AGND AGND AGND

AGND

A2

GND_1317S_2

3

PU4202

A5

IDES_N

A4

IDES_P

A6

DB0

A1

DB1

B1

DB2

B6

SPHASE

A3

AVDD

B3

AGND

B4

AGND

B5

AGND

A2

GND_1317S_1

5V_S5

G4

VDDHG6VDDHG5VDDH

VT1314SFCX-001-GP-U

AGND

B2

G3

G4

VDDHG6VDDHG5VDDH

VT1314SFCX-001-GP-U

AGND

B2

G3

E4

C4

VDDHE6VDDHE5VDDH

VDDHC6VDDHC5VDDH

GNDE1GNDE2GND

GNDG1GNDG2GND

E3

C3

2

400mils or Copper Shape

5V_S5

12

PC4209

PC4205

SC10U6D3V3MX-GP

2120mils or Copper Shape

PWR_VCORE_VX0

PG4201

1 2

VDDHE6VDDHE5VDDH

GNDG1GNDG2GND

E3

E4

C4

VDDHC6VDDHC5VDDH

GNDE1GNDE2GND

C3

12

PC4208

SC10U6D3V3MX-GP

VX#D1 VX#D2 VX#D3 VX#D4 VX#D5 VX#D6 VX#F1 VX#F2 VX#F3 VX#F4 VX#F5 VX#F6

GNDC1GNDC2GND

GND_1317S_1

PC4204

SC10U6D3V3MX-GP

D1 D2 D3 D4 D5 D6 F1 F2 F3 F4 F5 F6

GAP-CLOSE-PWR

400mils or Copper Shape

PC4221

PC4220

SC10U6D3V3MX-GP

PC4223

SC10U6D3V3MX-GP

12

PC4222

PC4221

12

PC4225

PC4224

SC1U10V2KX-1GP

SC10U6D3V3MX-GP

53A=2120mils or Copper Shape

PWR_VCORE_VX1

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F1

VX#F1

F2

VX#F2

F3

VX#F3

F4

VX#F4

F5

VX#F5

F6

VX#F6

GNDC1GNDC2GND

1 2

PG4202

PG4202 GAP-CLOSE-PWR

GND_1317S_2

GAP-CLOSE-PWR

2

1

12

SC10U6D3V3MX-GP

PC4210

PC4206

SC1U10V2KX-1GP

3

2

4

PL4201

PL4201 IND-240NH-GP

IND-240NH-GP

1

12

PC4207

SCD1U10V2KX-4GP

VCC_CORE

12/29 change PL4201 to HF part

12

PC4226

SCD1U10V2KX-4GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

VT1316+1314_CPU_CORE(2/3)

Size Document Number Rev

A3

Date: Sheet of

VT1316+1314_CPU_CORE(2/3)

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

1

A00

43 105Wednesday, April 13, 2011

A00

5

4

3

2

1

X01-0217 change PR4402& PR4406 to 4.12K(F)

D D

PR4403

20101012

PR4402

IDES_N_GFX42

C C

IDES_P_GFX42

1 2

4K12R2F-GP

PC4413

1 2

SC2700P50V2KX-1-GP

PC4422

1 2

SC2700P50V2KX-1-GP

PR4406

1 2

20101012

4K12R2F-GP

PR4403

1 2

11KR2F-L-GP

IDES_N_GFX_1

IDES_P_GFX_1

PR4405

1 2

11KR2F-L-GP

SPHASE_GFX42

PC4414

12

SC4700P50V2KX-1GP

PWR_AXG_IDES_P_1

12

PR4404

3K09R2F-1-GP

DB0_GFX42 DB1_GFX42 DB2_GFX42

SCD1U25V3KX-GP

5V_S5

12

PWR_AXG_IDES_P

PWR_AXG_AVDD

12

PC4427

PR4401

PR4401 10R2J-2-GP

10R2J-2-GP

A5 A4

A6 A1 B1

B6

A3 B3 B4 B5

PU4401

IDES_N IDES_P

DB0 DB1 DB2

SPHASE

AVDD AGND AGND AGND

C6

VT1317SFCX-001-GP

AGND

A2

B2

E3

VDDHC4VDDHC5VDDH

GNDE1GNDE2GND

VDDHE4VDDHE5VDDH

GNDC1GNDC2GND

320mils or Copper Shape

5V_S5

12

PC4415

SC10U6D3V3MX-GP

E6

G6

J6

H1

VX#H1

VDDHG4VDDHG5VDDH

VDDHJ4VDDHJ5VDDH

GNDJ1GNDJ2GND

J3

C3

G3

H2

VX#H2

H3

VX#H3

H4

VX#H4

H5

VX#H5

H6

VX#H6

D1

VX#D1

D2

VX#D2

D3

VX#D3

D4

VX#D4

D5

VX#D5

D6

VX#D6

F6

VX#F6

F5

VX#F5

F4

VX#F4

F3

VX#F3

F2

VX#F2

F1

VX#F1

GNDG1GNDG2GND

PC4417

PC4416

SC10U6D3V3MX-GP

PWR_AXG_VXPWR_AXG_IDES_N

20100802 Power: Change PL4401 to 68.R1010.10T.

12

PC4418

SC10U6D3V3MX-GP

PL4401

1 2

IND-D1UH-26-GP

68.R1010.10T

PC4419

SC1U10V2KX-1GP

0.12UH~0.15UH

PC4402

12

DY

12

PC4420

SC1U10V2KX-1GP

12

PC4421

11/18

SCD1U10V2KX-5GP

2120mils or Copper Shape

12

PC4423

PC4401

SC22U6D3V5MX-2GP

12

PC4424

PC4425

SC22U6D3V5MX-2GP

12

PC4426

SC22U6D3V5MX-2GP

2120mils or Copper Shape

12

PC4403

PC4404

DY

12

PC4405

PC4406

12

PC4408

PC4407

12

PC4409

PC4410

12

VCC_GFXCORE

12

PC4411

12

PC4412

1 2

PG4401

B B

A A

5

4

PG4401 GAP-CLOSE-PWR

GAP-CLOSE-PWR

GND_1317S_3

3

SC22U6D3V5MX-2GP

2

SC22U6D3V5MX-2GP

Title

Size Document Number Rev

A3

Date: Sheet of

SC22U6D3V5MX-2GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

VT1316+1317_AXG_CORE(3/3)

Enrico Caruso 14

44 105Wednesday, April 13, 2011

1

A00

5

DCBATOUT PWR_1D05V_DCBATOUT

PG4501

GAP-CLOSE-PWR-3-GP

D D

GAP-CLOSE-PWR-3-GP

X01-0217 Change PR4501 to 78.7K(F)

C C

B B

1 2

RUNPWROK19,46,47

PG4502

PG4503

PG4504

11/18

1 2

PR4502

0R0402-PAD

1.05VTT_PWRGD37,48

3D3V_S0

PR4501

1 2

78K7R2F-GP

12

SC1KP50V2KX-1GP

TPS51218 for 1D05V

PR4516

12

10KR2J-3-GP

PC4501

10KR2J-3-GP

PWR_1D05V_TRIP

PWR_1D05V_EN

PWR_1D05V_CCM

12

PR4503

PR4503 470KR2F-GP

470KR2F-GP

PU4501

1

PGOOD

2

TRIP

3

EN

4

VFB

5

CCM

TPS51218DSCR-GP-U1

4

GND

VBST

DRVH

SW

V5IN

DRVL

11

PWR_1D05V_VBST

10

PWR_1D05V_DRVH

9

PWR_1D05V_SWPWR_1D05V_VFB

8 7

PWR_1D05V_DRVL

6

84.00172.037 BSZ115N03MSC Id=20A, Qg=9.8nC, Rdson=8.9 mohm

PR4504

PWR_1D05V_VBST_R

1 2

2D2R3-1-U-GP

12

84.00460.037 SiR460DP-T1-GE3 Id=40A, Qg=16.8nC, Rdson=4.7~6.1 mohm

PU4502

5V_S5

SC1U10V2KX-1GP

PU4502

PC4502

PC4502 SCD1U25V3KX-GP

SCD1U25V3KX-GP

12

PU4503

RJK03B9DPA-00-J5A-GP

PC4503

RJK03D4DPA-00-J5A-GP

3

PWR_1D05V_DCBATOUT

567

8

DDD

D

DDD

D

G

4

SSS

123

567

8

DDD

D

DDD

D

G

4

SSS

123

VTT_SENSE_L

VSS_SENSE_L

11/10

12/15

12

PC4504

SC10U25V5KX-GP

PR4509

1 2

0R0402-PAD

12

PC4510

DY

SC1000P50V3JN-GP-U

PR4510

1 2

0R0402-PAD

DY

12

PWR_1D05V_SNUB

12

PC4505

12

PC4507

SC10U25V5KX-GP

PL4501

1 2

IND-1D5UH-34-GP

PR4514

PR4514 2D2R5F-2-GP

2D2R5F-2-GP

PC4509

PC4509 SC560P50V-GP

SC560P50V-GP

2

X02-0310 stuff EC4501

12

EC4501

SCD1U50V3KX-GP

SCD1U25V3KX-GP

Design Current = 14.375A

22.6A<OCP< 26.7A

1D05V_PWR

BOM merge 11/18

11/10

VTT_SENSE_L

PR4506

9K76R2F-1-GP

PWR_1D05V_VFB

PR4507

20KR2F-L-GP

VSS_SENSE_L

VCCIO_SENSE 8

12

PR4505

100R2F-L1-GP-U

12

PC4511

12

SCD1U10V2KX-4GP

DY

PR4508

PR4508 100R2F-L1-GP-U

100R2F-L1-GP-U

PC4508

SCD1U10V2KX-5GP

11/10

79.33719.L01

12

Vout=0.704V*(R1+R2)/R2

VSSIO_SENSE 8

PT4501

SE330U2VDM-L-GP

GAP-CLOSE-PWR-3-GP

12

PT4509

SE330U2VDM-L-GP

DY

GAP-CLOSE-PWR-3-GP

11/10

GAP-CLOSE-PWR-3-GP

1

PG4505

1 2

PG4506

1 2

PG4507

1 2

PG4508

1 2

PG4509

1 2

PG4510

1 2

PG4511

1 2

PG4512

1 2

PG4513

1 2

GAP-CLOSE-PWR-3-GP

PG4514

1 2

GAP-CLOSE-PWR-3-GP

PG4515

1 2

GAP-CLOSE-PWR-3-GP

PG4516

1 2

PG4517

1 2

PG4518

1 2

PG4519

1 2

PG4520

1 2

1D05V_VTT1D05V_PWR

12

DY

EC4502

SCD1U50V3KX-GP

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: 1.50UH PCMC104T Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J O/P cap: 330U2V EEFSX0D331ER 9mOhm 3Arms Panasonic/79.33719.L01 H/S: SIR172DP / 10.3mohm/12.4mOhm@4.5Vgs/ 84.00172.037 L/S: SiR460DP / 0.49mohm/0.61mOhm@4.5Vgs/ 84.00460.037

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

TPS51218_+1.05V_VTT

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

45 105

1

A00

5

SSID = PWR.Plane.Regulator_1p5v0p75v

D D

RUNPWROK19,45,47

12

PR4603

PR4603 10KR2F-2-GP

10KR2F-2-GP

12

1 2

PC4603

C C

PC4603

PC4602

SCD1U25V3KX-GP

SCD01U16V2KX-3GP

X01-0217 change PR4601 to 52.3K(F)

State S3 S5 VDDR VTTREF VTT

B B

S4/S5

MODE

11/10

3D3V_S0

12

PR4604

PR4604 20KR2J-L2-GP

20KR2J-L2-GP

0D75V_EN37

PWR_1D5V_EN

PWR_1D5V_VREF

PWR_1D5V_REFIN

PWR_1D5V_MODE

PWR_1D5V_TRIP

PR4601_1

52K3R2F-L-GP

PR4608

240R2F-1-GP

11/18

1 2

11/18

BOM merge 11/18

PWR_1D5V_VTTREF

200KR2F-L-GP

12

PC4610

PR4602

SC10U6D3V3MX-GP

1 2

51KR2F-L-GP

PR4601

1 2

12

PR4606

X01-0210 change PC4610 from 0.22uF to 10uF

S0

S3

Hi Hi

HiLo

Lo Lo

PR4608

200k ohm

100k ohm

68k ohm

Frequency Discharge Mode

400kHz

300kHz

47k ohm 400kHz

PU4601

20

PGOOD

17

VTTEN

16

EN/PSV

6

VREF

8

REFIN

19

MODE

18

TRIP

5

VTTREF

21

GND

7

GND

TPS51216RUKR-GP

74.51216.073

On

Off(Hi-Z)

Off Off Off

Tracking Discharge

Non-tracking Discharge

On

4

12

V5IN

15

VBST

14

DRVH

13

SW

11

DRVL

10

PGND

9

VDDQS

2

VTTIN

3

VTT

1

VTTS

4

VTTGND

BOM merge 11/18

5V_S5

12

PC4601

PWR_1D5V_VBST

PWR_1D5V_DRVH

PWR_1D5V_SW

PWR_1D5V_DRVL

PWR_1D5V_VDDQS

12

PC4615

SCD1U10V2KX-5GP

+0D75V_DDR_P 0D75V_S0

PWR_1D5V_VTTREF

84.00172.037 BSZ115N03MSC Id=20A, Qg=9.8nC,

SC1U10V3KX-3GP

Rdson=8.9 mohm

PR4605

1 2

2D2R3J-2-GP

11/18

+0D75V_DDR_P

12

DY

PC4616

PC4617

SC10U6D3V5KX-1GP

PG4601

1 2

GAP-CLOSE-PWR-3-GP

PG4602

1 2

GAP-CLOSE-PWR-3-GP

PC4619

PC4619 SCD1U25V3KX-GP

SCD1U25V3KX-GP

PR4605_2

1 2

SC10U6D3V5MX-3GP

DDR_VREF_S3

PR4611

1 2

0R0603-PAD

3

+PWR_SRC_1D5V

11/10

PC4609

SC10U25V5KX-GP

12/15

12

PC4611

PC4612

SC10U25V5KX-GP

9

S1/D2

123

G1

Q1

G2

8

12

45

D1

S2

7

PU4602

PU4602 FDMS3604S-GP

FDMS3604S-GP

PHASE

Q2

S2

6

12/20

PL4601

1 2

COIL-1UH-51-GP-U

12

PR4612

DY

2D2R5F-2-GP

TPS51216_PHS_SET

12

PC4622

DY

SC330P50V2KX-3GP

1D5V_PWR

12

PC4604

SC1U10V3KX-3GP

PM_SLP_S4#19,27

I/P cap:10U 25V K0805 X5R/ 78.10622.51L Inductor: 0.68UH PCMC104T-R68MN Cyntec 2.4mohm/2.7mohm Isat =39Arms 68.R6810.20G O/P cap: 220U2V EEFCX0D221R 15mOhm 2.7Arm/Panasonic/79.22719.20L H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037

COIL-1UH-51-GP-U

68.R6810.20G Id=22~39A DCR=2.4~2.7mohm Size=10X11.5X4

PR4607

PR4607 0R0402-PAD

0R0402-PAD

1 2

2

DCBATOUT

PG4603

12

PC4614

PC4613

1 2

Design Current = 16.34A

25.7A<OCP< 30.3A

PC4614

SCD1U50V3KX-GP

SC4D7U25V5KX-GP

PG4603

PG4604

PG4605

PG4606

BOM merge 11/18

12

1 2

PG4607

GAP-CLOSE-PWR-3-GP

X01-0210 del PT4602

PWR_1D5V_VDDQS

PWR_1D5V_EN

12

PC4606

PC4606 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

PC4621

PC4620

SCD1U10V2KX-5GP

SC4D7U6D3V5KX-3GP

Change part refernce name 11/26

+PWR_SRC_1D5V

12

GAP-CLOSE-PWR-3-GP

12

GAP-CLOSE-PWR-3-GP

12

GAP-CLOSE-PWR-3-GP

12

GAP-CLOSE-PWR-3-GP

1D5V_PWR

PT4603

12

SE220U2VDM-8GP

1D5V

X01-0209 PT4603 UMA-->220uF DIS-->470uF

GAP-CLOSE-PWR-3-GP

12

DY

EC4601

SCD1U50V3KX-GP

GAP-CLOSE-PWR-3-GP

1

1D5V_PWR 1D5V_S3

PG4608

1 2

PG4609

1 2

PG4610

1 2

PG4611

1 2

PG4612

1 2

PG4613

1 2

PG4614

1 2

GAP-CLOSE-PWR-3-GP

PG4615

1 2

GAP-CLOSE-PWR-3-GP

PG4616

1 2

GAP-CLOSE-PWR-3-GP

PG4617

1 2

PG4618

1 2

PG4619

1 2

PG4620

1 2

PG4621

1 2

PG4622

1 2

PG4623

1 2

PG4624

1 2

PG4625

1 2

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

TPS51216_+1.5V_SUS

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

46 105

1

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p8v

+1.8V_RUN Design current = 1.015A

APW7153B for 1D8V_S0 DIS

PR4709

PR4705

2D2R2F-GP

PC4708

SCD1U10V2KX-5GP

1 2

10KR2F-2-GP

12

DIS

12

DIS

DY

PC4709

1 2

DIS

SC1KP50V2KX-1GP

PWR_1D8V_FB

PWR_1D8V_COMP

PWR_1D8V_COMP_R

PC4712

1 2

DY

SC47P50V2JN-3GP

PU4702

PU4702 APW7153BQBI-TRG-GP

APW7153BQBI-TRG-GP

6

PVDD

7

VDD

8

POK

9

FB

10

COMP

74.07153.A73

PR4710

1 2

DIS

20KR2F-L-GP

DIS

GND

11

PGND

LX#4

LX#3

GND

SHDN/RT

5

4

3

2

1

PWR_1D8V_LX

PWR_1D8V_RT

12

PR4706

820KR2F-GP

DIS

PL4702

1 2

COIL-1D5UH-28-GP

PC4707

SCD1U10V2KX-4GPDYPC4707

SCD1U10V2KX-4GP

12

DY

12/15

DIS

12

PR4708

DIS

20KR2F-L-GP

PWR_1D8V_FB

12

PR4707

16KR2F-GP

DIS

Vo=0.8*(1+(R1/R2))

DIS

12

PC4713

SC100P50V2JN-3GP

12

PC4714

SC22U6D3V5MX-2GP

1D8V_PWR

12

PC4716

SC22U6D3V5MX-2GP

3D3V_S0

D D

C C

3D3V_S5

12

PC4715

SC10U6D3V3MX-GP

12

PC4711

SC10U6D3V3MX-GP

1MR2J-1-GP

PR4704

DIS

RUNPWROK19,45,46

12

1D8V_PWR

GAP-CLOSE-PWR-3-GP

1 2

BOM merge 12/15

2N7002K-2-GP

PR4711

PM_SLP_S3#19,27,36,37

B B

RUNPWROK19,45,46

PR4712

PM_SLP_S3#19,27,36,37

1 2

0R0402-PAD

47KR2J-2-GP

PR4713

1 2

0R0402-PAD

PC4717

SC1U10V3KX-3GP

1D8V_RUN_EN

12

DY

PWR_1D8V_RT_R

PC4710

SCD1U10V2KX-5GP

5V_S5

12

UMA

12

DY

PC4718

DY

12

2N7002K-2-GP

G

S

MOS_N-FET

PU4703

6

VCNTL

7

POK

8

UMA

EN

9

VIN#9

APL5930KAI-TRG-GP

74.05930.03D

DIS

PQ4702

VIN#5 VOUT#4 VOUT#3

GND

D

3D3V_S5

5 4 3 2

FB

1

12/9 EE change to

APL5930 for 1D8V_S0 UMA

1D8V_PWR

12

PR4714

PR4714 16K5R2F-2-GP

16K5R2F-2-GP

UMA

12

PC4719

PC4719 SC68P50V2JN-1GP

SC68P50V2JN-1GP

UMA

PG4704

PG4706

PG4707

1D8V_S0

11/4

SC4700P50V2KX-1GP

A A

I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L O/P cap: 22U 25V M0805 X5R/ 78.22610.51L Inductor: 1.5U PCMC063T Cyntec 14mohm/15mohm Isat =18Arms 68.1R510.10K

5

4

5912_1.8V_RUN_FB

12

PR4715

PR4715 13K3R2F-L1-GP

13K3R2F-L1-GP

UMA

Vout=0.8V*(R1+R2)/R2

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

APW7153B_ +1.8V_RUN

Size Document Number Rev

A3

Date: Sheet of

APW7153B_ +1.8V_RUN

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

1

47 105Wednesday, April 13, 2011

A00

5

4

3

2

1

APL5916 for VCCSA

11/18

D D

D85V_PWRGD42

1.05VTT_PWRGD37,45

11/18

PR4802

1KR2F-L-GP

3D3V_S0

12

SC1U6D3V2KX-GP

PR4803

1 2

0R0402-PAD

11/18

C C

X01-0209 dummy PC4809 for BBU result

5V_S5

PC4801

D85V_PWRGD

PWR_VCCSA_EN

DY

12

PR4801

PR4801 0R0402-PAD

0R0402-PAD

PWR_VCCSA_VCNTL

12

PC4809

PC4809 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

APL5916KAI-TRL-GP

7

8

PU4801

POK

EN

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

PWR_VCCSA_VIN

GAP-CLOSE-PWR-3-GP

PC4802

12

SC10U6D3V5MX-3GP

R1

PR4804

10KR2F-2-GP

PWR_VCCSA_FB

R2

PR4805

80K6R2F-GP

1 2

12

Vout=0.8*(1+R1/R2)

2N7002K-2-GP

B B

PG4801

PG4802

PC4803

SC10U6D3V5MX-3GP

PR4806

160KR2F-GP

PQ4801

1D05V_VTT

12

PC4804

12

DY

PWR_VCCSA_SEL1

D

DY

S

SC100P50V2JN-3GP

11/25

G

PWR_VCCSA_SEL0

VCCSA_PWR

12

PC4805

SC10U6D3V5MX-3GP

12

DY

12

PC4806

SC10U6D3V5MX-3GP

DY

PR4807

1 2

10KR2J-3-GP

PC4807

PC4807 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Iomax=6A OCP>9A VCCSA=0.9V

GAP-CLOSE-PWR-3-GP

12

PT4801

GAP-CLOSE-PWR-3-GP

DY

GAP-CLOSE-PWR-3-GP

ST150U10VDM-4GP

VCCSA_SEL 9

PG4803

1 2

PG4804

1 2

PG4805

1 2

PG4806

1 2

PG4807

1 2

PG4808

1 2

0D85V_S0

A A

5

4

3

2

JV10-CS

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

APL5916_VCCSA

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

48 105Wednesday, April 13, 2011

1

A00

SSID = VIDEO

DCBATOUT_LCD

A00-0408 Add RN4903 for ESD issue.

LVDS_DDC_DATA_R17 LVDS_DDC_CLK_R17

AFTP4906AFTP4906 AFTP4907AFTP4907

USB_CAMERA#

1

USB_CAMERA

1

RN4903

RN4903 SRN33J-5-GP-U

SRN33J-5-GP-U

1 2 3

LVDSA_CLK17 LVDSA_CLK#17 LVDSA_DATA217 LVDSA_DATA2#17 LVDSA_DATA117 LVDSA_DATA1#17 LVDSA_DATA017 LVDSA_DATA0#17

4

BLON_OUT_C

LCD_BRIGHTNESS LVDS_DDC_DATA LVDS_DDC_CLK

X02-0309 change AFTP to follow DV14 AMD

USB_CAMERA

USB_CAMERA#

3 4

2

WCM2012F2S-GP-U2

WCM2012F2S-GP-U2 TR4901

TR4901

1

Close to LVDS connector

A00-0320 Change TR4901 to 120ohm. A00-0406 remove R4903, R4904

A00-0408 SWAP TR4901 net

Close to LVDS connector

LCD1

NP1

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15

NP2

ETY-CONN30E-2-GP-U2

20.F0891.030

USB_PP12 18

USB_PN12 18

SSID = Inverter

INVERTER POWER

R4907

1 2

100KR2J-1-GP

BLON_OUT_C

31

30

29 28 27 26 25 24 23

USB_CAMERA#

22

USB_CAMERA

21

LCD_TST_C

20 19 18 17 16

32

LCD_TST_C

LCD_BRIGHTNESS

3D3V_CAMERA_S0

3D3V_S0

12

C4901

SCD1U10V2KX-5GP

RN4901

1 2 3 4 5

SRN100J-4-GP

LCDVDD

1 2

8 7 6

BLON_OUT 27 LCD_TST 27

L_BKLT_CTRL 17

F4901 POLYSW-1D1A24V-GP-U

1 2

69.50007.A31

2nd = 69.50007.A41

SCD1U50V3KX-GP

11/ 17 dummy C4905

C4904

SC1U6D3V2KX-GP

3D3V_CAMERA_S03D3V_S0

LCD_BRIGHTNESS

LCD_TST

0818

R4908 0R3J-0-U-GPR4908 0R3J-0-U-GP

1 2

SSID = VIDEO

LCD POWER

15V_S5

11/15 change LCDVDD source from S0 to S5

3D3V_S5

R4912

330KR2J-L1-GP

1 2

R4906

330KR2J-L1-GP

12

DY

100KR2J-1-GP

1 2

C4909 SCD1U25V2KX-GPC4909 SCD1U25V2KX-GP

11/17 move RN1703 from P17 to P49 and change part refernce

3D3V_S0

RN4902

1 2 3

SRN2K2J-1-GP

LVDS_DDC_DATA_R

4

LVDS_DDC_CLK_R

EC4903

12

DY

SC33P50V2JN-3GP

C4903

C4903 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12/22 swap net for layout

DCBATOUT_LCDDCBATOUT

12

C4906

EC4906

SC33P50V2JN-3GP

C4906

SC1KP50V2KX-1GP

12

DY

C4905

DY

1 2

12

EC4905

SC33P50V2JN-3GP

For EMI request

12/2 modify +LCDVDD to LCDVDD

Q4901

D

D G

G

AO6402A-GP

5

6

D

6

D

5

S

Q4902

34

2

1

2N7002KDW-GP

150R3J-L-GP

LCDVDD_1

1 2 3 4

FPVCC_CTL1

R4916

LCDVDD

12

LVDSA_CLK

LVDSA_CLK#

EC4907

LCD_BRIGHTNESS

LCD_TST_C

DY

12

EC4901

12

EC4902

DY

SC33P50V2JN-3GP

12

EC4908

DY

SC5D6P50V2CN-1GP

LVDS_VDD_EN17

LCD_TST_EN27

12/9 BOM merge

D4901

1

2

3

BAT54CPT-GP

For EMI request

5V_S5

Q4903

R1

LCDVCC_EN

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

R1

1

R2

PDTC144EU-1-GP

Wednesday, April 13, 2011

1 2

R4917 100KR2J-1-GPR4917 100KR2J-1-GP

3

2

LCD Connector

Enrico Caruso 14

FPVCC_CTL3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

49 105

A00

5

4

3

2

1

SSID = VIDEO

3D3V_S0

11/ 17 Add RN5012 for SMbus pull high

4

RN5012

RN5012 SRN2K2J-1-GP

SRN2K2J-1-GP

D D

11/3 Add RN5010 for CRT SMBus

1

2 3

X02-0303 change 0R to short pad

DDCDATA DDC_DATA_CON

RN5010

PCH_CRT_DDCDATA17 PCH_CRT_DDCCLK17

5V Tolerance

CRT_GFX_DDCDAT85 CRT_GFX_DDCCLK85

2 3 1

0R4P2R-PAD

RN5006

2 3 1

DIS_CRT

SRN0J-6-GP

4

RN

DDC_DATA_CON DDC_CLK_CON

DDCCLK

Layout Note:

C C

*Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. * RGB signal will hit 75 Ohm first, then pi-filter, finally

X01: change RN5012 from 0R to 2.2KR

3D3V_S0

Q5001

34

2

5

1

6

2N7002KDW-GP

DDC_CLK_CON

RN

RN5007

1

8

2

PCH_CRT_BLUE17 PCH_CRT_GREEN17 PCH_CRT_RED17

CRT_GFX_R85 CRT_GFX_G85 CRT_GFX_B85

3 4 5

0R8P4R-PAD

RN5005

1 2 3

DIS_CRT

4 5

SRN0J-7-GP

7 6

8 7 6

SC22P50V2JN-4GP

CRT_BLUE CRT_GREEN CRT_RED

CRT CONN.

CRT_RED

CRT_GREEN

CRT_BLUE

B B

45

678

123

RN5003

RN5003 SRN150F-1-GP

SRN150F-1-GP

DY

12

DY

C5005

C5004

C5005

SC8P250V2CC-GP

L5001 BLM15BA330SS1D-GPL5001 BLM15BA330SS1D-GP

1 2

L5002 BLM15BA330SS1D-GPL5002 BLM15BA330SS1D-GP

1 2

L5003 BLM15BA330SS1D-GPL5003 BLM15BA330SS1D-GP

1 2

12

DY

C5006

SC8P250V2CC-GP

12

C5007

SC10P50V2JN-4GP

CRT_R

CRT_G

CRT_B

12

C5008

C5009

SC10P50V2JN-4GP

5V_CRT_S0

1

23

12

C5017

DY

SC18P50V2JN-1-GP

C5013

DY

4

12

RN5001

RN5001 SRN2K2J-1-GP

SRN2K2J-1-GP

DDC_DATA_CON

DDC_CLK_CON

12

DY

C5014

SC22P50V2JN-4GP

11/18 change Fuse for CRT and HDMI share

5V_CRT_S0_R

F5101

1 2

FUSE-1D1A6V-4GP-U

69.50007.691

2nd = 69.50007.771

5V_CRT_S0

D5001

2 1

CH551H-30PT-GP

JVGA_VS

JVGA_HS

12

DY

C5018

SC18P50V2JN-1-GP

11/29 change CRT1 to 20.20927.015

5V_CRT_S0_R

CRT1

9

VCC_CRT

DDC_DATA_CON DDC_CLK_CON

CRT_R CRT_G CRT_B

JVGA_VS JVGA_HS

12

DDCDATA_ID1

15

DDCCLK_ID3

1

CRT_RED

2

CRT_GREEN

3

CRT_BLUE

14

VSYNC

13

HSYNC

D-SUB-15-111-GP

20.20927.015

11/15 remove F5501 base on brazos result.

11/ 17 Remove R5001

5V_S0

AFTP501AFTP501 AFTP502AFTP502 AFTP503AFTP503 AFTP504AFTP504 AFTP505AFTP505 AFTP506AFTP506 AFTP507AFTP507 AFTP508AFTP508

X02-0309 change AFTP to follow DV14 AMD

5V_CRT_S0

1

DDC_DATA_CON

1

DDC_CLK_CON

1

CRT_R

1

CRT_G

1

CRT_B

1

JVGA_HS

1

JVGA_VS

1

4

NC#4

11

NC#11

5

GND

6

GND

7

GND

8

GND

10

GND

16

GND

17

GND

AFTP509AFTP509

1

5V_CRT_S0

D5002

5V_CRT_S0

12

DY

Hsync & Vsync level shift

CRT_HSYNC

14

A A

CRT_VSYNC

5 6

DY

TC74VHCT125AFTQK2M-GP

7

4

U5001B

2 3

DY

C5012

SCD01U16V2KX-3GP

14

1

U5001A

DY

TC74VHCT125AFTQK2M-GP

7

HSYNC_5

VSYNC_5 JVGA_VS

RN5011

2 3 1

DY

SRN0J-6-GP

JVGA_HS

4

X00 9/23

R5002 33R2J-2-GPR5002 33R2J-2-GP

1 2

R5003 33R2J-2-GPR5003 33R2J-2-GP

1 2

CRT_R

CRT_G

CRT_B

D5002

3

DY

BAV99PT-GP-U

D5003

3

DY

BAV99PT-GP-U

D5004

3

DY

BAV99PT-GP-U

2

1

2

1

2

1

X01-0208 change R5002, R5003 to 33R

5

4

3

5V_CRT_S0

14

10

9 8

DY

U5001C

7

TC74VHCT125AFTQK2M-GP

5V_CRT_S0

14

13

12 11

DY

U5001D

7

TC74VHCT125AFTQK2M-GP

4

50 105

1

CRT_HSYNC CRT_VSYNC

A00

RN5008

PCH_CRT_HSYNC17 PCH_CRT_VSYNC17

VGA_CRT_HSYNC83,85 VGA_CRT_VSYNC83,85

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

2

Date: Sheet of

2 3 1

0R4P2R-PAD

RN

RN5009

2 3 1

DIS_CRT

SRN0J-6-GP

CLOSE TO TRANSFORMER

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CRT Connector

Enrico Caruso 14

5

4

3

2

1

SSID = VIDEO

R5101

HDMI_CLK_R_C

D D

A00-0407 remove TR5101, TR5102, TR5103, TR5104 PAD and remove 0R PAD.

HDMI_DATA0_R_C

C C

B B

1 2

HDMI_CLK_R#17 HDMI_CLK_R17

HDMI_DATA0_R#17 HDMI_DATA0_R17

HDMI_DATA1_R#17 HDMI_DATA1_R17

HDMI_DATA2_R#17 HDMI_DATA2_R17

R5101 0R0402-PAD

0R0402-PAD

RR5102

RR5102 0R0402-PAD

0R0402-PAD

RR5104

RR5104 0R0402-PAD

0R0402-PAD

RR5103

RR5103 0R0402-PAD

0R0402-PAD

C5103 SCD1U10V2KX-5GP

C5103 SCD1U10V2KX-5GP C5104 SCD1U10V2KX-5GP

C5104 SCD1U10V2KX-5GP

C5105 SCD1U10V2KX-5GP

C5105 SCD1U10V2KX-5GP C5106 SCD1U10V2KX-5GP

C5106 SCD1U10V2KX-5GP

C5110 SCD1U10V2KX-5GP

C5110 SCD1U10V2KX-5GP C5107 SCD1U10V2KX-5GP

C5107 SCD1U10V2KX-5GP

C5108 SCD1U10V2KX-5GP

C5108 SCD1U10V2KX-5GP C5109 SCD1U10V2KX-5GP

C5109 SCD1U10V2KX-5GP

HDMI Level Shifter & CONNECTOR

RR5106

HDMI

123

RR5106 0R0402-PAD

0R0402-PAD

1 2

RR5105

RR5105 0R0402-PAD

0R0402-PAD

1 2

RR5108

RR5108 0R0402-PAD

0R0402-PAD

1 2

RR5107

RR5107 0R0402-PAD

0R0402-PAD

1 2

678

RN5106

RN5106 SRN680J-GP

SRN680J-GP

4 5

HDMI_DATA1_R_C_CON

HDMI_DATA1_R_C#_CONHDMI_DATA1_R_C#

HDMI_DATA2_R_C_CON

HDMI_DATA2_R_C#_CON

HDMI_CLK_R_C# HDMI_CLK_R_C

HDMI_DATA0_R_C# HDMI_DATA0_R_C

HDMI_DATA1_R_C# HDMI_DATA1_R_C

HDMI_DATA2_R_C# HDMI_DATA2_R_C

678

RN5107

RN5107 SRN680J-GP

SRN680J-GP

HDMI

123

4 5

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

5V_S0

12

DY

11/19 change net Q5103_G to 5V_S0

HDMI_CLK_R_C_CON

HDMI_CLK_R_C#_CONHDMI_CLK_R_C#

HDMI_DATA0_R_C_CON

HDMI_DATA0_R_C#_CONHDMI_DATA0_R_C#

1 2

HDMI

1 2

HDMI

1 2

HDMI

1 2

HDMI

1 2

HDMI

1 2

HDMI

1 2

HDMI

1 2

HDMI

HDMI_PLL_GND

HDMI_DATA1_R_C

HDMI_DATA2_R_C

HDMI_DATA2_R_C#

HDMI DISCRETE/ UMA Co-lay

66.68136.08L=>680ohm for UMA

66.47136.A8L=>470ohm for GPU

Q5103

R5113

R5113 100KR2J-1-GP

100KR2J-1-GP

HDMI_PLL_GND

D

HDMI

G

HDMI CONN

HDMI1

2021

R5123

0R2J-2-GP

DY

1 2

S

HDMI

SKT-HDMI19P-63-GP-U

22.10296.171

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2223

200KR2J-L1-GP

HDMI_DATA2_R_C_CON

HDMI_DATA2_R_C#_CON HDMI_DATA1_R_C_CON

HDMI_DATA1_R_C#_CON HDMI_DATA0_R_C_CON

HDMI_DATA0_R_C#_CON HDMI_CLK_R_C_CON

HDMI_CLK_R_C#_CON

DDC_CLK_HDMI DDC_DATA_HDMI

HPD_HDMI_CON

12

R5110

DY

5V_CRT_S0_R

12

HDMI

C5102

SCD1U10V2KX-5GP

HDMI

HDMI_HPD_B

1 2

R5111 150KR2J-L1-GP

11/18 change Fuse for CRT and HDMI share

5V_CRT_S0_R

X02-0309 Del AFTP test point to follow DV14 AMD

12/9 BOM merge

3D3V_S0

12/23 BOM merge

HDMI

3

Q5102

Q5102 PMBS3904-1-GP

1

HDMI

PMBS3904-1-GP

84.03904.L06

2ND = 84.03904.P11

2

HDMI_HPD_E

R5112

R5112 10KR2J-3-GP

10KR2J-3-GP

R5125 0R0402-PADR5125 0R0402-PAD

12

1 2

HDMI_PCH_DET 17

12/1 Modify 5V_HDMI to 5V_CRT_S0_R

3D3V_S0

11/18 change RN5117 BOM control property to HDMI

RN5117

PCH_HDMI_CLK17

PCH_HDMI_DATA17

11/16 Del RN5112~5115 for no need to reserve for VGA

A A

X02-0303 change 0R to short pad

2 3 1

0R4P2R-PAD

RN

4

DDC_DATA_Q

Q5104

34

2

5

HDMI

1

6

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

DDC_CLK_HDMIDDC_CLK_Q

DDC_DATA_HDMI

Routing Guidelines: CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm). The total delay on CTRLDATA should be longer than CTRLCLK.

5

4

3

HDMI

4

RN5101

RN5101 SRN2K2J-1-GP

SRN2K2J-1-GP

1

2 3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

51 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

52 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

LVDS_Switch

53 105Wednesday, April 13, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

54 105Wednesday, April 13, 2011

A00

5

4

3

2

1

SSID = User.Interface

D D

C C

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

ITP/Fan Connector

Size Document Number Rev

A3

Date: Sheet of

ITP/Fan Connector

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

55 105Wednesday, April 13, 2011

1

A00

SSID = SATA

SATA HDD Connector

11/10 Change HDD1 CONN to 62.10065.031

12/22 Change HDD1 CONN to62.10065.H71

12

Close to HDD1

ODD Connector

ODD1

S1

GND

S4

GND

S7

GND

P5

GND

P6

GND

8

GND

9

GND

SKT-SATA7P+6P-26-GP-U

22.10300.201

+5V +5V

P2 P3

P1

DP

P4

MD

S3

A-

S2

A+

S5

B-

S6

B+

12/21 ODD1 to 22.10300.201

ODD_PWR_5V

SATA_ODD_PRSNT# SATA_ODD_DA#_C

SATA_RXN4_C SATA_RXP4_C

C5607 SCD01U16V2KX-3GPC5607 SCD01U16V2KX-3GP C5608 SCD01U16V2KX-3GPC5608 SCD01U16V2KX-3GP

SATA_ODD_PWRGT SATA_ODD_DA#

SUPPORT ZERO SATA ODD

C5605

SC10U10V5ZY-1GP

1 2 1 2

12

C5606

SCD1U10V2KX-5GP

R5602

1 2

0R2J-2-GP

DY

3D3V_S05V_S0

12

DY

RN5601

4

SRN10KJ-5-GP

12

C5604

C5601

DY

SC10U6D3V5KX-1GP

SATA_ODD_PRSNT# 22 SATA_ODD_DA# 18

SATA_TXN4 21 SATA_TXP4 21

SATA_RXN4 21 SATA_RXP4 21

12

R5604

R5604 10KR2J-3-GP

10KR2J-3-GP

DY

1 23

SCD1U10V2KX-5GP

3D3V_S0

5V_S0

AFTP5607AFTP5607 AFTP5608AFTP5608 AFTP5609AFTP5609

SATA_TXP021

SATA_TXN021

SATA_RXP021

SATA_RXN021

C5615 SCD01U16V2KX-3GPC5615 SCD01U16V2KX-3GP

1 2

C5616 SCD01U16V2KX-3GPC5616 SCD01U16V2KX-3GP

1 2

When the drive is powered on, the FET to the MD/DA pin drive is OFF. When the drive is powered off, the FET to the MD/DA pin is ON

3D3V_S0

R5605

100KR2J-1-GP

1 2

ODD_PWRGT#

3D3V_S0

R5606

R5606 10KR2J-3-GP

10KR2J-3-GP

1 2

SATA_ODD_DA#_C

A00-0408 Add R5606 to pull high 3.3V_S0 Change pull high to 3.3V_S0

HDD1_20

1

HDD1_21

1

HDD1_22

1

SATA_RXP0_C SATA_RXN0_C

SATA_ODD_PWRGT22

P1

V33

P2

V33

P3

V33

P7

V5

P8

V5

P9

V5

P13

V12

P14

V12

P15

V12

S2

A+

S3

A-

S6

B+

S5

B-

SKT-SATA7P-15P-80-GP

62.10065.H71

5V_S0

12

C5609

C5609 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

HDD1

16

17

NP1

NP2

S1

GND

S4

GND

S7

GND

P4

GND

P5

GND

P6

GND

P10

GND

P12

GND

P11

DAS/DSS

SATA Zero Power ODD

U5601

U5601 G547F1P81U-GP

G547F1P81U-GP

EN/EN#4OC#

3

IN#3

2

IN#2

1

GND

74.00547.C79

2ND = 74.02191.079

Current limit Active High typ =>2A

OUT#6 OUT#7 OUT#8

5

ODD_PWR_5V

6 7 8

SC10U6D3V5KX-1GP

ODD_PWR_5V

C5610

100 mil

12

Q5601

SATA_ODD_PWRGT SATA_ODD_DA#

123 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

5

6

Q5601

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

HDD/ODD

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

56 105

A00

5

4

3

2

1

SSID = ESATA

D D

C C

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

ESATA

Enrico Caruso 14

57 105Wednesday, April 13, 2011

1

A00

5

SSID = AUDIO

4

3

2

1

D D

Speaker Connector

AUD_SPK_L-29

AUD_SPK_L+29 AUD_SPK_R-29 AUD_SPK_R+29

12

EC5801

DY

12

EC5802

DY

EC5803

DY

12

EC5804

DY

56

SPK1

SPK1 ACES-CON4-4-GP

ACES-CON4-4-GP

1

2 3 4

12

AFTP5805AFTP5805

1

20.F0765.004

C C

MLVG0402220NV05BP-GP-U

AFTP5801AFTP5801 AFTP5802AFTP5802 AFTP5803AFTP5803 AFTP5804AFTP5804

11/10 remove MIC1

B B

11/26 reserve MIC2

12/7 change MIC2 to 20.F1050.002

AFTP5808AFTP5808

MIC2

3

1

INT_MIC_L_R29,82

AFTP5809AFTP5809

1

MIC2

2 4

ACES-CON2-19-GP

20.F1889.002

AUD_SPK_L-

1

AUD_SPK_L+

1

AUD_SPK_R-

1

AUD_SPK_R+

1

12/7 Change to digital GND

X02-0315 Change MIC2 to 20.F1889.002

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

SPEAKER CONN

58 105Wednesday, April 13, 2011

1

A00

5

SSID = LOM

D D

Giga Main: 68.IH601.301

Giga 2nd: 68.05009.30A

10/100 Main: 68.HH035.301

10/100 Main: 68.01284.30A

C C

LOM_TCT

12

C5902

C5902 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

4

LAN TransFormer

XF5901

1CT:1CT

LAN_MDI3P31

LAN_MDI3N31

LAN_MDI2P31

LAN_MDI2N31

LAN_MDI1P31

LAN_MDI1N31

LAN_MDI0P31

LAN_MDI0N31

2

1

3

1CT:1CT

5

4

6

1CT:1CT

8

7

9

XFOM

1CT:1CT

11

10

12 13

XFORM-24P-19-GP

2nd = 68.89240.30B

GD5901

MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+ MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-

1 2

GT1206150ASMD-GP

GT1206150ASMD-GP GD5902

GD5902

MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+

1 2

GT1206150ASMD-GP

3

X01-0211 Add EMI solution for Surge

11/30 swap net

23

MCT3

24

22

20

MCT2

21

19

17

MCT1

18

16

14

MCT0

15

MDO3+MDO3+MDO3+MDO3+MDO3+MDO3+

MDO3-MDO3-MDO3-MDO3-MDO3-MDO3-MDO3-MDO3-MDO3-MDO3-

MDO2+MDO2+MDO2+MDO2+MDO2+MDO2+

MDO2-MDO2-MDO2-MDO2-MDO2-MDO2-MDO2-MDO2-MDO2-MDO2-

MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+MDO1+

MDO1-MDO1-MDO1-MDO1-MDO1-MDO1-

MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+MDO0+

MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-MDO0-

12/6 change resistor package.

Surge

MDO1-MDO1-MDO1-

MDO2+ MDO2-

ER5910

ER5910 75R2J-1-GP

75R2J-1-GP

10/100

MDO3+ MDO3-

ER5913

75R2J-1-GP

10/100

1 2

12

10/100

12

GIGA

ER5911

ER5911 75R2J-1-GP

75R2J-1-GP

MCT

12

ER5912

ER5912 75R2J-1-GP

75R2J-1-GP

10/100

MCT

MCT2

MCT3

4

RN5901

RN5901 SRN75J-2-GP-U

SRN75J-2-GP-U

1

2 3

2

MCT

Surge

12

C5901

C5901 SC1KP3KV8KX-GP-U

SC1KP3KV8KX-GP-U

MCT1

12

Surge

MCT1_C

12

LAN_MDI0P

LAN_MDI0N

LAN_MDI1P

LAN_MDI1N

C5906SC1KP3KV8KX-GP-U

Non-Surge

R5902

R5902 75R5F-1-GP

75R5F-1-GP

12

R59060R3J-0-U-GP

12

Non-Surge

2

U5901

1

3

4

6

12

Surge

MCT0_C MCT0

12

C5911

SC1KP2KV6KX-GP

5

Surge

TVLST2304AD0-GP

C5905SC1KP3KV8KX-GP-U

12

R59050R3J-0-U-GP

Non-Surge

R5901

R5901 75R5F-1-GP

75R5F-1-GP

1

11/27 Del U5902

11/27 Del GDT5903, GDT5904

B B

X02-0311 Change GDT5901& GDT5902 to GD5901& GD5902

11/25 modify to CRC circuit and divided resistor as EMI suggest 11/29 Change C5911 to 78.1022S.22L

0722 : change to gas tube

RJ45

9

MDO0+

MDO0MDO1+ MDO2+ MDO2MDO1-

A A

MDO3+ MDO3-

11/29 change RJ45 to 22.10277.D01

5

NP1

1

2 3 4 5 6 7 8

NP2

10

RJ45-12P-4-GP-U

22.10277.D01

DN15ATI Whistler

MDO1+ MDO2+ MDO2MDO1MDO3+ MDO3MDO0+ MDO0-

4

AFTP5901AFTP5901

1

AFTP5902AFTP5902

1

AFTP5903AFTP5903

1

AFTP5904AFTP5904

1

AFTP5905AFTP5905

1

AFTP5906AFTP5906

1

AFTP5907AFTP5907

1

AFTP5908AFTP5908

1

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

XFOM&RJ45

59 105Wednesday, April 13, 2011

1

A00

5

SSID = Flash.ROM

SPI FLASH ROM (4M byte) for PCH

11/18 Merge R6003, R6004, R6005 to RN6001

D D

12/6 swap net for layout X01-0211 swap CS#, WP# for layout

X01: modify CS#, WP#

SPI_CS0#_R21,27

SPI_SO_R21,27

C C

11/18 reserve R6002 for WP# and change change DO pin pull down to capacity

1 2

R6001 33R2J-2-GPR6001 33R2J-2-GP

EC6004

SC4D7P50V2CN-1GP

EC6004

DY

12

3D3V_S5

123

DY

1 2

4

678

RN6001

RN6001 SRN4K7J-10-GP

SRN4K7J-10-GP

4 5

SPI_SO

SPI_WP#

R6002

R6002 10KR2J-3-GP

10KR2J-3-GP

SPI_HOLD_0#

U6001

1

CS#

2

DO WP# VSS

HOLD#

3 4

W25Q32BVSSIG-1-GP

72.25Q32.A01

2nd = 72.25320.C01

2nd = 72.25320.C01 3rd = 72.25032.D01

3rd = 72.25032.D01

VCC

CLK

3

2

1

Notes: The total SPI interface signal between EC and PCH

3D3V_S5

canˇt not exceed 6500mil. The mismatch between SPI signal must be within 500mil

SC10U6D3V5KX-1GP

12

C6002

SCD1U10V2KX-5GP

SPI_CLK_R 21,27 SPI_SI_R 21,27

12

C6001

DY

3D3V_S5

8 7

SPI_CLK

6

SPI_SI

5

DI

EC6003

SC4D7P50V2CN-1GP

DY

12

R6026 0R0402-PADR6026 0R0402-PAD

1 2

R6025 0R0402-PADR6025 0R0402-PAD

1 2

11/1 Add R6026, R6025 for EMI X02-0309 Change 0R to short pad

12

DY

EC6001

SC4D7P50V2CN-1GP

SSID = RBATT

3D3V_AUX_S5

B B

A A

RTC_AUX_S5

C6003

SC1U6D3V2KX-GP

X02-0310 Del RTC AFTP to follow DV14 AMD

RTC_PWR

12

3

CH715FPT-GP

1 2

R6007 100R2J-2-GP

G

R6008

R6008 10MR2J-L-GP

10MR2J-L-GP

S

5

Q6001

2

RTC_PWR

1

83.R0304.B81

2nd = 83.00040.E81

Width=20mils

1 2

DY

2N7002K-2-GP

D

Q6002

84.2N702.J31

2ND = 84.2N702.031

1 2

RTC_SENSE# 22

+RTC_VCC

R6006

R6006 1KR2J-1-GP

1KR2J-1-GP

RTC1

3 1 2

4

ACES-CON2-31-GP

20.F1606.002

11/29 change RTC1 to 20.F1606.002

11/23 add RTC DET circuit

4

VccRTC is now connected to VccDSW3_3 through the Schottky diode instead of the 3.3V Sus well.

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Flash/RTC

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

60 105

1

A00

5

SSID = USB

4

3

2

1

USB20_VCCA

USB_PN1_R USB_PP1_R

AFTP6102AFTP6102

USB2

5 1

2 3

1

4 6

SKT-USB6-16-GP

22.10321.S01

11/29 change USB2 to 22.10321.S01

12

C6103

USB20_VCCA

SCD1U16V2KX-3GP

12

C6104

12

TC6101

SCD1U10V2KX-5GP

12

TC6103

DY

ST100U6D3VBML1GP

11/30 Add TC6103

ST220U6D3VDM-15GP

5V_S5

D D

SC1U10V3ZY-6GP

C6102

12

U6102

1

GND

2

IN#2

3

IN#3

4

EN/EN#

G547F2P81U-GP

74.00547.A79

OUT#8 OUT#7 OUT#6

OC#

8 7 6 5

100 mil

USB_OC#0_1 18

LOW ACTIVE TYPE!!

USB_PWR_EN#27

12/22 change TC6101 to 100uF

AFTP6101AFTP6101

11/18 remove R6101, R6104

5V_S5

C C

12

C6107

SC1U10V3ZY-6GP

USB_PWR_EN#27

C6107

11/10 Move USB power SW to Mainboard

U6103

1

GND

2

IN#2

3

IN#3

4

EN/EN#

G547F2P81U-GP

74.00547.A79

OUT#8 OUT#7 OUT#6

OC#

8 7 6 5

100 mil

USB_OC#8_9 18

LOW ACTIVE TYPE!!

USB20_VCCB

12

C6105

12

C6106

DY

SCD1U16V2KX-3GP

SCD1U10V2KX-5GP

11/18 dummy C6106

X02-0314 stuff C6106

12

TC6102

ST220U6D3VDM-15GP

AFTP6103AFTP6103 AFTP6104AFTP6104

1 1 1

USB20_VCCA USB_PN1_R USB_PP1_R

B B

11/1 Stuff TR6101 for EMI

U6105

USB_PP1_R

USB_PN1_R

1

34

TR6101

TR6101 WCM2012F2S-GP-U2

WCM2012F2S-GP-U2

2

USB_PP1 18

USB_PN1 18

A00-0320 Change TR6101 120ohm.

A00-0406 remove R6102, R6103

A A

A00-0408 Swap TR6101 net for layout

5

4

USB_PN1_R USB_PP1_R

3

1

ESD I/O1

2

GND

3

ESD I/O2

IP4220CZ6-GP

DY

ESD I/O4

ESD I/O3

6 5

VP

4

5V_S5

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

USB Power SW

1

A00

61 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

62 105Wednesday, April 13, 2011

A00

5

4

3

2

1

SSID = User.Interface

D D

(Blanking)

C C

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Bluetooth

1

63 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RESERVED

Size Document Number Rev

A3

Date: Sheet of

RESERVED

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

64 105Wednesday, April 13, 2011

1

A00

5

4

3

2

1

SSID = Wireless

Mini Card Connector(802.11a/b/g)

11/10 Change WLAN1 to 62.10043.841

D D

C C

C6501

3D3V_S0

12

5V_S5

SCD1U25V2KX-GP

C6502

12

DY

USB_PP1118

1D5V_S0

C6503

C6508

12

C6504

SCD1U10V2KX-5GP

SCD1U25V2KX-GP

12

DY

SCD1U10V2KX-5GP

WLAN_ACT

R6506

1 2

0R0402-PAD

SC10U6D3V5KX-1GP

DY

12

C6505

SC10U6D3V5KX-1GP

12

C6506

SCD1U10V2KX-5GP

11/18 add R65008 R6509 for E51_TX,RX

11/23 add R6511 to connect BT_ACT

BT_ACT

R6511

1 2

BLUETOOTH_EN27

USB_PP11_R

11/18 change R6510 R6503 from 0603 to 0402

12

SCD1U10V2KX-5GP

X02-0309 change AFTP to follow DV14 AMD

CLK_PCIE_WLAN_REQ#20

CLK_PCIE_WLAN#20 CLK_PCIE_WLAN20

E51_RXD27 E51_TXD27

PCIE_RXN420 PCIE_RXP420

PCIE_TXN420 PCIE_TXP420

0R2J-2-GP

5V_S5

3D3V_S0

R6510

1 2

0R2J-2-GP

R6503

1 2

DY

0R2J-2-GP

+5V_MINI_DEBUG

AFTP6505AFTP6505

DY

R6509 0R2J-2-GP

1 2

R6508 0R2J-2-GP

1 2

DY

1

WLAN_ACT BT_ACT

E51_RX E51_TX

WLAN1

53

1

3 5 7

9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

54

SKT-MINI52P-41-GP

62.10043.841

NP1 2

4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 NP2

3D3V_S0

1D5V_S0

WIFI_RF_EN 27

3D3V_S0

1D5V_S0

USB_PN11_R USB_PP11_R

CARD_WLAN_OUT# CARD_WPAN_OUT#

PLT_RST# 5,18,27,31,71,83

PCH_SMBCLK 14,15,20

PCH_SMBDATA 14,15,20

CARD_WLAN_OUT# 68 CARD_WPAN_OUT# 68

1D5V_S0

3D3V_S0

11/18 change R6507 to close gap

11/22 change WLAN LED control to KBC

11/26 Add CARD_WLAN_OUT# and CARD_WPAN_OUT#

A00-0406 remove TR6501

R6505

USB_PN1118

B B

1 2

0R0402-PAD

USB_PN11_R

12/22 swap nets for layout

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

MINICARD(WLAN)/ITP CONN

Size Document Number Rev

Date: Sheet of

MINICARD(WLAN)/ITP CONN

A3

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

65 105Wednesday, April 13, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

66 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

67 105Wednesday, April 13, 2011

A00

5

SSID = User.Interface

FRONT POWER LED

R6813

PWRLED#27

11/26 reserve R6813 to aviod LED turn on

D D

when Q6801 install

1 2

0R0402-PAD

11/26 Add R6810 to avoid LED turn on

R6810

SATA_LED#21

1 2

15KR2J-1-GP

SATA HDD LED(White)

Need change to LOW actived from KBC GPIO

Battery LED2(WHITE_LED)

BATT_WHITE_LED#27

C C

11/16 Del RN6801 to follow DV15 AMD

CHG_AMBER_LED#27

Battery LED1(AMBER_LED)

4

PWRLED#_C

SATALED#_C

R6804

1 2

0R0402-PAD

Q6807

R1

B

DY

PDTC124EU-1-GP

84.00124.H1K

R6805

1 2

0R0402-PAD

Q6808

R1

B

DY

R2

PDTC124EU-1-GP

84.00124.H1K

R2

C

E

R6811

1 2

0R0402-PAD

Q6801

R2

B

R1

DY

PDTA143ET-GP

84.00143.M11

Q6805

R2

B

R1

PDTA143ET-GP

84.00143.M11

WHITE_LED_BAT#

C

E

AMBER_LED_BAT#

3

R6806

E

C

LED_PWR

R6806

330R2J-3-GP

A00-0320 Change resistor for LED brightness

5V_S0

E

SATA_LED_R

C

11/18 add R6804 R6805 0ohm and dummy Q6807, Q6808

R6812

330R2J-3-GP

12

X02-0303 change 0R to short pad

R6801

330R2J-3-GP

R6803

R6803 499R2F-2-GP

499R2F-2-GP

12

BAT_WHITE#

12

BAT_AMBER#

A00-0413 change R6806, R6812, R6801, R6808 to 330ohm

FPOWER_LED_A

12

HDD_LED_A

3

2

83.00326.G70

WHITE

CHLED1

LED-OW-3-GP

AMBER

PLED1

3

AK

12

LED-W-27-GP

83.01221.R70

HDLED1

3

A K

1 2

LED-W-27-GP

83.01221.R70

5V_S5

1

5V_S5

2

EC6801 SC220P50V2KX-3GP

LED_PWR

SATA_LED_R

AMBER_LED_BAT#

EC6801 SC220P50V2KX-3GP

EC6810 SC220P50V2KX-3GP

EC6807 SC220P50V2KX-3GP

WHITE_LED_BAT#

EC6809 SC220P50V2KX-3GP

1 2

DY

1 2

DY

1 2

DY

1 2

DY

1

12/3 Change LED part reference to follow standard

B B

A00-0328 change R6814 to 10KR

11/26 change WLANLED control circuit

D6801

CARD_WLAN_OUT#65

CARD_WPAN_OUT#65

KBC_WLAN_OUT#27

11/26 if WLAN LED control by KBC. remove D6801 and short R6814, R6807

1

2

BAT54A-7-F-1-GP

R6807

1 2

0R2J-2-GP

DY

WLAN_LED#

3

R6814

1 2

10KR2J-3-GP

11/26 remove R6835

Q6806

R2

WLANLED#_C

B

84.00143.M11

R1

PDTA143ET-GP

E

WLAN_LED_R WLAN_LED

C

X01-0217 Change R6814 to 0R

5V_S0

R6808

12

330R2J-3-GP

Place EC6806 near LED2

WHITE

X02-0315 Change R6808 to 499K

DY

1 2

EC6806

SCD1U25V2KX-GP

WLED1

3

A K

1 2

LED-W-27-GP

83.01221.R70

KBC_PWRBTN#27

A00-0316 modify WLED1 circuit for brightness

A A

5

4

3

Power button

1 2

R6802

R6802 100R2J-2-GP

100R2J-2-GP

AFTP6801AFTP6801

2

KBC_PWRBTN#_C

1

20.K0464.004

12/10 change PWRBT1 pin define

12/21 change PWRBT1 to 20.K0464.004

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

PWRBT1

6 4B

4A

3B

3A

2B

2A

1B

1A

5

ACES-CONN8G-GP

AFTP6802AFTP6802

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

LED Bard/Power Button

Enrico Caruso 14

68 105

1

A00

Wireless LED

5

4

3

2

1

SSID = Touch.PadSSID = KBC

KB1

D D

C C

KB1

31 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32

JAE-CON30-7-GP

20.K0565.030

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0 KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10 CAP_LED_R

KB_DET#

1

AFTP6901AFTP6901

KB_DET# 21

12/6 swap net for layout

SRN10KJ-5-GP

TPCLK27

TPDATA27

C6904

SC33P50V2JN-3GP

C6904

X01-0216 exchange C6903& C6904

RN6903

DY

5V_S0

12

1

23

4

AFTP6927AFTP6927

12

DY

C6903

SC33P50V2JN-3GP

5V_S0

1

TouchPad Connector

12

C6901

C6901 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

20.K0464.004

ACES-CONN8G-GP

6 4B

4A

3B

3A

2B

2A

1B

1A

5

TPAD1

11/23 change TPAD1 to 20.K0320.004

X01-0208 change TPAD1 to 20.K0464.004

X01-0216 Modify pin define error

AFTP6929AFTP6929 AFTP6931AFTP6931 AFTP6930AFTP6930

1 1 1

5V_S0 TPDATA TPCLK

X01-0216 Modify pin define error

11/26 change KB1 to 20.K0597.030

12/8 Change KB1 to 20.K0565.030

X02-0309 change AFTP to follow DV14 AMD

CAP_LED_R

B B

GND

AFTP6957AFTP6957

1

AFTP6972AFTP6972

1

12/8 Add Cap LED control circuit

CAP LED CONTROL

Q6902

R6905

KROW7 KROW6 KROW4 KROW2 KROW5 KROW1 KROW3 KROW0

1 2

15KR2J-1-GP

1 1 1 1 1 1 1 1

CAP_LED#27

A A

KROW[0..7] 27

KCOL[0..16] 27

5

Q6902

Q6902_B

B

R1

PDTA143ET-GP

84.00143.M11

2nd = 84.02143.011

3rd = 84.00143.N11

AFTP6902AFTP6902 AFTP6903AFTP6903 AFTP6904AFTP6904 AFTP6905AFTP6905 AFTP6906AFTP6906 AFTP6907AFTP6907 AFTP6908AFTP6908 AFTP6909AFTP6909

5V_S5

R2

E

C

1 2

DY

R6907 100R2J-2-GP

KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2

1 2

R6906 1KR2J-1-GPR6906 1KR2J-1-GP

AFTP6910AFTP6910

1

AFTP6911AFTP6911

1

AFTP6912AFTP6912

1

AFTP6913AFTP6913

1

AFTP6914AFTP6914

1

AFTP6915AFTP6915

1

AFTP6916AFTP6916

1

AFTP6917AFTP6917

1

4

CAP_LED_RCAP_LED_Q

KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10

Wistron Corporation

AFTP6918AFTP6918

1

AFTP6919AFTP6919

1

AFTP6920AFTP6920

1

AFTP6921AFTP6921

1

AFTP6922AFTP6922

1

AFTP6923AFTP6923

1

AFTP6924AFTP6924

1

AFTP6925AFTP6925

1

AFTP6926AFTP6926

1

3

2

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Key Board/Touch Pad

Enrico Caruso 14

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

69 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

Hall Sensor

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

70 105

1

A00

5

D D

4

3

2

1

11/18 remove RN7102, R7107

LPC_AD021,27 LPC_AD121,27 LPC_AD221,27 LPC_AD321,27 LPC_FRAME#21,27

PLT_RST#5,18,27,31,65,83

CLK_PCI_LPC18

3D3V_S0

DB1

1 2 3 4 5 6 7

DB1

8

9 10 11 12

MLX-CON10-7-GP

20.D0183.110

C C

B B

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Debug connector

71 105Wednesday, April 13, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

72 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

73 105Wednesday, April 13, 2011

A00

5

4

3

2

1

SSID = SDIO

3D3V_CARD_S0

D D

DY

12

DY

C7401

SCD1U10V2KX-5GP

12

DY

C7403

C7402

SCD1U10V2KX-5GP

12

C7404

C7405

SC2D2U6D3V3KX-GP

SCD1U10V2KX-5GP

XD_WE#/SD_CD#32

XD_D4/SD_D3/MS_D132

XD_D2/SD_CMD32

XD_CLE/SD_D0/MS_D732

XD_CE#/SD_D132

XD_D5/SD_D2/MS_D532

XD_RDY/SD_WP/MS_CLK32

XD_D0/SD_CLK/MS_D2_R

CARD1

SD_VDD/MMC_VDD11MS_DATA0

4

MS_VCC

20

SD_CD

3

SD_CD/DAT3/MMC_RSV

14

SD_CLK/MMC_CLK

6

SD_CMD/MMC_CMD

18

SD_DAT0/MMC_DAT

19

SD_DAT1

1

SD_DAT2

22

SD_WP/SW

NP1

NP2

CARD-PUSH-22P-GP

SD_VSS/MMC_VSS1 SD_VSS/MMC_VSS2

20.I0110.021

MS_DATA1 MS_DATA2 MS_DATA3

MS_INS

MS_BS

MS_SCLK

GND GND

SD_GND

MS_VSS MS_VSS

12 13

XD_D0/SD_CLK/MS_D2_R

10 7

8 15 5

23 24

21

2 16

9 17

XD_D1/SD_D5/MS_D0 32 XD_D4/SD_D3/MS_D1 32

XD_ALE/SD_D7/MS_D3 32

XD_RE#/MS_INS# 32 XD_D6/MS_BS 32

XD_RDY/SD_WP/MS_CLK 32

C C

XD_ALE/SD_D7/MS_D3 XD_D1/SD_D5/MS_D0 XD_CLE/SD_D0/MS_D7 XD_CE#/SD_D1 XD_D5/SD_D2/MS_D5 XD_D4/SD_D3/MS_D1 XD_D2/SD_CMD XD_D0/SD_CLK/MS_D2_R XD_WE#/SD_CD# XD_RDY/SD_WP/MS_CLK

For EMI

12

EC7401

SC6D8P50V2CN-GP

12

EC7402

SC6D8P50V2CN-GP

12

EC7403

EC7404

SC4D7P50V2BN-GP

SC6D8P50V2CN-GP

12

EC7406

EC7405

SC6D8P50V2CN-GP

12

EC7408

EC7407

SC6D8P50V2CN-GP

12

EC7410

EC7409

SC6D8P50V2CN-GP

11/18 Dummy EC7401, EC7403

0810 Vendor Recommand

B B

XD_D0/SD_CLK/MS_D232

R7407 33R2J-2-GPR7407 33R2J-2-GP

11/20 vendor recommand to reserve 5P

X01-0216 stuff EC7401~EC7410 for EMI

12

XD_D0/SD_CLK/MS_D2_R

For EMI

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

SD/XD/MS/MMC Card CONN

Size Document Number Rev

A3

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Enrico Caruso 14

74 105Wednesday, April 13, 2011

1

A00

5

4

3

2

1

SSID = ExpressCard

D D

C C

B B

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Express Card

75 105Wednesday, April 13, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

76 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

77 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

78 105Wednesday, April 13, 2011

A00

5

4

3

2

1

SSID = User.Interface

D D

C C

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Free Fall Sensor

79 105Wednesday, April 13, 2011

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

80 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

81 105Wednesday, April 13, 2011

A00

5

4

3

2

1

IOBD1 is for USB board

11/1 Stuff TR8201, TR8202 for EMI

D D

USB_PP9_R

USB_PN9_R

1

2

WCM2012F2S-GP-U2

WCM2012F2S-GP-U2 TR8202

TR8202

34

A00-0406 remove R8201, R8202, R8203, R8204 pad

USB_PP9 18

USB_PN9 18

USB_PN9_R USB_PP9_R

USB_PN8_R USB_PP8_R

A00-0320 Change TR8201, TR8202 to 120ohm.

A00-0408 Swap net for layout

12/6 swap net for layout

C C

USB_PP8_R

USB_PN8_R

1

2

WCM2012F2S-GP-U2

WCM2012F2S-GP-U2 TR8201

TR8201

34

USB_PP8 18

USB_PN8 18

USB20_VCCB

IOBD1

17

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

18

PTWO-CON16-1-GP

20.K0429.016

11/10 modify B2B CONN and pin define

X01-0214 add AFTP8201~8210

X02-0309 Del AFTP8201~8210

IOBD2 is for Audio board

IOBD2

17

INT_MIC_L_R29,58

AUD_HP1_JACK_L229 AUD_HP1_JACK_R229

MIC_IN_L29

11/1 Add EC2901~EC2904 for EMI request

B B

MIC_IN_L

MIC_IN_R

AUD_HP1_JACK_L2

AUD_HP1_JACK_R2

1 2

DY

EC8201SC10P50V2JN-4GP

EC8202SC10P50V2JN-4GP

EC8203SC10P50V2JN-4GP

EC8204SC10P50V2JN-4GP

EXT_MIC_JD#29

AUD_HP1_JD#29

MIC_IN_R29

LID_CLOSE#27

3D3V_S5

AUD_AGND

1

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

18

PTWO-CON16-1-GP

20.K0429.016

X02-0309 Del AFTP8201~8210

12/10 Change pin defien for audio board routing smooth.

A A

5

4

3

12/14 Change IOBD2 to 20.K0429.016 and change pin define.

Title

IO Board Connector

Size Document Number Rev

A3

Date: Sheet of

2

Date: Sheet of

IO Board Connector

Enrico Caruso 14

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

82 105Wednesday, April 13, 2011

1

A00

5

VGA1A

SSID = VIDEO

PEG_TXP04 PEG_TXN04

D D

C C

B B

PEG_TXP14 PEG_TXN14

PEG_TXP24 PEG_TXN24

PEG_TXP34 PEG_TXN34

PEG_TXP44 PEG_TXN44

PEG_TXP54 PEG_TXN54

PEG_TXP64 PEG_TXN64

PEG_TXP74 PEG_TXN74

ATI_RST# VGA_RST#

11/2 change to 1D5V_VGA_PWOK

1D5V_VGA_PWOK86

A A

1D8V_S0_VGA_PG93

PEG_TXP0 PEG_TXN0

PEG_TXP1 PEG_TXN1

PEG_TXP2 PEG_TXN2

PEG_TXP3 PEG_TXN3

PEG_TXP4 PEG_TXN4

PEG_TXP5 PEG_TXN5

PEG_TXP6 PEG_TXN6

PEG_TXP7 PEG_TXN7

CLK_PCIE_VGA20 CLK_PCIE_VGA#20

1 2

DIS

R8314 10KR2F-2-GP

R8316

12

0R0402-PAD

PLT_RST#5,18,27,31,65,71

5

PWRGOOD PCIE_CALRN

12

DY

R8330

12

DY

0R2J-2-GP

R8324

12

DY

0R2J-2-GP

VGA1A

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

PWRGOOD

AL27

PERST#

C8312

Seymour-S3-XT

SC47P50V2JN-3GP

1D8V_S0_VGA_PG_R

12

C8311

C8311 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

CLOCK

DY

VGA1

12

0R2J-2-GP

PCI EXPRESS INTERFACE

P/N: FJPJP

R8323

U8301

1

B

2

DY

A

3

GND

74LVC1G08GW-1-GP

2ND =

4

1 OF 7

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

ATI_RST#PLT_RST#

5

VCC

4

Y

73.01G08.L04

4

PEG_C_RXP0

AH30

PEG_C_RXN0

AG31

PEG_C_RXP1

AG29

PEG_C_RXN1

AF28

PEG_C_RXP2

AF27

PEG_C_RXN2

AF26

PEG_C_RXP3

AD27

PEG_C_RXN3

AD26

PEG_C_RXP4

AC25

PEG_C_RXN4

AB25

PEG_C_RXP5

Y23

PEG_C_RXN5

Y24

PEG_C_RXP6

AB27

PEG_C_RXN6

AB26

PEG_C_RXP7

Y27

PEG_C_RXN7

Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

PCIE_CALRP

Y22

AA22

11/18 Del R8322 and dummy R8324, U8301, U8302

C8306 SCD1U10V2KX-5GP

1 2

DIS

C8305 SCD1U10V2KX-5GP

1 2

DIS

C8303 SCD1U10V2KX-5GP

1 2

DIS

C8304 SCD1U10V2KX-5GP

1 2

DIS

C8310 SCD1U10V2KX-5GP

1 2

DIS

C8309 SCD1U10V2KX-5GP

1 2

DIS

C8308 SCD1U10V2KX-5GP

1 2

DIS

C8307 SCD1U10V2KX-5GP

1 2

DIS

C8315 SCD1U10V2KX-5GP

1 2

DIS

C8316 SCD1U10V2KX-5GP

1 2

DIS

C8318 SCD1U10V2KX-5GP

1 2

DIS

C8317 SCD1U10V2KX-5GP

1 2

DIS

C8314 SCD1U10V2KX-5GP

1 2

DIS

C8313 SCD1U10V2KX-5GP

1 2

DIS

C8319 SCD1U10V2KX-5GP

1 2

DIS

C8320 SCD1U10V2KX-5GP

1 2

DIS

11/18 Add R8311, R8312 and dummy R8319, R8310 to follow DN13

1 2

DIS

R8321 1K27R2F-L-GP

1 2

DIS

R8315 2KR2F-3-GP

X02-0311 Change R8316, R8331 to short pad

R8331

DGPU_HOLD_RST#18

3D3V_VGA_S0

U8301_Y

1

2

3

74LVC1G08GW-1-GP

0R0402-PAD

U8302

B

DY

A

GND

2ND =

12

VCC

Y

73.01G08.L04

1V_VGA_S0

5

ATI_RST#

4

3

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

PEG_RXP0 4 PEG_RXN0 4

PEG_RXP1 4 PEG_RXN1 4

PEG_RXP2 4 PEG_RXN2 4

PEG_RXP3 4 PEG_RXN3 4

PEG_RXP4 4 PEG_RXN4 4

PEG_RXP5 4 PEG_RXN5 4

PEG_RXP6 4 PEG_RXN6 4

PEG_RXP7 4 PEG_RXN7 4

STRAPS

TX_PWRS_ENB

GPIO8_ROMSO

VGA_DIS

GPIO21_BB_EN

BIOS_ROM_EN

VIP_DEVICE_STRAP_EN

RSVD

2010/06/11

A00-0322 Dummy R8302 for disable de-emphasis

3D3V_VGA_S0

ATI_RST# 85

3

Need to check

TX_PWRS_ENB85

TX_DEEMPH_EN85

BIF_GEN2_EN_A85

GPIO8_ROMSO85

VGA_DIS85

CONFIG085

CONFIG185

CONFIG285

VGA_CRT_VSYNC50,85

VGA_CRT_HSYNC50,85

VSYNC_DAC285

HSYNC_DAC285

BIOS_ROM_EN85

GPIO5_AC_BATT85

GPIO21_BB_EN85

2

CONFIGURATION STRAPS

GPIO0

GPIO1TX_DEEMPH_EN

GPIO2BIF_GEN2_EN_A 0

GPIO5GPIO5_AC_BATT

GPIO8 RESERVED 0

GPIO[13:11]ROMIDCFG[2:0]

GPIO21 RESERVED

GPIO_22_ROMCSB

V2SYNC

H2SYNC 0

GENERICC 0RSVD

HSYNC XAUD[1]

VSYNC XAUD[0]

DESCRIPTION OF DEFAULT SETTINGS

Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing

PCIE TRANSMITTER DE-EMPHASIS ENABLED 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

0:Advertises the PCIe device as 2.5GT/s capable at power on. 1:Advertises the PCIe device as 5.0GT/s capable at power on.

optional input allow the system to request a fast power reduction by setting GPIO5 to low.

0:VGA Controller capacity enabled 1:The device won't be recognized as the system's VGA controller

BIOS_ROM_EN=1, Config[2:0] defines the ROM type BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

0:Disable external BIOS ROM device

VIP Device Strap Enable indicates to the software driver that it sense whether or not a VIP device is connected on the VIP Host interface.

1:Enable external BIOS ROM device

RESERVED

AUD[1:0]:11-Audio for both DisplayPort and HDMI

2010/06/11

3D3V_VGA_S0

PIN STRAPS

R8301 3KR2J-2-GP

1 2

DIS

R8302 3KR2J-2-GP

1 2

DY

R8303 10KR2J-3-GP

1 2

DIS

R8304 10KR2J-3-GP

1 2

DY

R8305 10KR2J-3-GP

1 2

DY

R8306 10KR2J-3-GP

1 2

DIS

R8307 10KR2J-3-GP

1 2

DY

R8308 10KR2J-3-GP

1 2

DY

R8309 10KR2J-3-GP

1 2

DY

R8310 10KR2J-3-GP

1 2

DY

R8311 10KR2J-3-GP

1 2

DY

R8312 10KR2J-3-GP

1 2

DY

R8313 10KR2J-3-GP

1 2

DY

R8318 10KR2J-3-GP

1 2

DY

R8317 10KR2J-3-GP

1 2

DY

dGPU mode

IGPU

IGPU with BACO

2

2010/07/13 Stuff for 5.0GT/S

PE_GPIO0

H

Title

L

H

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Date: Sheet of

JTAG_TMS_VGA85

TESTEN84

JTAG_TRST#_VGA85

JTAG_TCK_VGA20,85

JTAG SIGNAL OPTION

Signal

JTAG_TCK

JTAG_TMS

Wednesday, April 13, 2011

Normal mode

"1"(PU)TESTEN "1"(PU)

"0"(PD) "1"(PU)JTAG_TRST#

CLK

GPU_PCIE/STRAPPING(1/5)

Enrico Caruso 14

R8326 10KR2J-3-GP

R8329 10KR2J-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 3K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

RECOMMEND

PLATFORM SETTING

X

1

0

?

0

0GPIO9

X XX

0

X

0

0 0 1 (256MB)

0

1

3D3V_VGA_S0

R8325

10KR2J-3-GP

DY

R8327

DY

Debug mode

10KR2J-3-GP

12

5K11R2F-L1-GP

pilot run mode

1 2

R8328

1 2

DIS

1 2

"0"(PD)

NC

"1"(PU)

"1"(PU)"1"(PU)

83 105

1

NC

A00

5

4

3

2

1

SSID = VIDEO

D D

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

1D5V_VGA_S0 1D5V_VGA_S0

12

R8410

Ra

40D2R2F-GP

DIS

R8414

R8414 100R2F-L1-GP-U

100R2F-L1-GP-U

MVREFDA

12

C8402

C8402 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DIS

12

Rb

DIS

DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3)

1 2

DIS

1 2

DIS

For SEYMOUR

10R

50R

5K

120pF

MVDDQ

Ra

Rb

MEM_CALRN0 MEM_CALRP0

For Robson

C C

1D5V_VGA_S0

R8403 243R2F-2-GP

R8408 243R2F-2-GP

This basic topology should be used for DRAM_RST for

**

DDR3/GDDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be

B B

calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec.

Designator

R_MEM_1

R_MEM_2

R_MEM_3

C_MEM

12

R8411

Ra

40D2R2F-GP

DIS

R8415

R8415 100R2F-L1-GP-U

100R2F-L1-GP-U

1.5V/1.8V

MVREFSA

12

C8403

C8403 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DDR3

40.2R

100R

DIS

R_MEM_2

R8405

1 2

DIS

51R2J-2-GP

C8401

SC120P50V2JN-1GP

12

Rb

DIS

DDR5

1.5V

40.2R

100R

DPC_CALR (Park/Robson-S3): Analog calibration. Connect DPxx_CALR to GND through a 150- (1%) resistor.

MEM_RST88,89

C_MEM R_MEM_3

Place all these components very close to GPU (Within 25mm) and keep all component close

10R

to each Other (within 5mm) except R_MEM_2

50R

5K

120pF

DRAM_RST_1

DIS

1 2

MDA[0..31]88

MDA[32..63]89



150R2F-1-GP

150R2F-1-GP R8407

R8407

R_MEM_1

R8402

1 2

DIS

10R2J-2-GP

1 2

DIS

R8409

5K1R2F-2-GP

TESTEN83

MEM_CALRP1/DPC_CALR

TP8401TPAD14 TP8401TPAD14 TP8402TPAD14 TP8402TPAD14

12

DIS

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17

MDA18

MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

MVREFDA MVREFSA

MEM_CALRN0 TESTEN

MEM_CALRP0

DRAM_RST

CLKTESTA

1

CLKTESTB

1

VGA1C

K27

DQA_0

J29

DQA_1

H30

DQA_2

H32

DQA_3

G29

DQA_4

F28

DQA_5

F32

DQA_6

F30

DQA_7

C30

DQA_8

F27

DQA_9

A28

DQA_10

C28

DQA_11

E27

DQA_12

G26

DQA_13

D26

DQA_14

F25

DQA_15

A25

DQA_16

C25

DQA_17

E25

DQA_18

D24

DQA_19

E23

DQA_20

F23

DQA_21

D22

DQA_22

F21

DQA_23

E21

DQA_24

D20

DQA_25

F19

DQA_26

A19

DQA_27

D18

DQA_28

F17

DQA_29

A17

DQA_30

C17

DQA_31

E17

DQA_32

D16

DQA_33

F15

DQA_34

A15

DQA_35

D14

DQA_36

F13

DQA_37

A13

DQA_38

C13

DQA_39

E11

DQA_40

A11

DQA_41

C11

DQA_42

F11

DQA_43

A9

DQA_44

C9

DQA_45

F9

DQA_46

D8

DQA_47

E7

DQA_48

A7

DQA_49

C7

DQA_50

F7

DQA_51

A5

DQA_52

E5

DQA_53

C3

DQA_54

E1

DQA_55

G7

DQA_56

G6

DQA_57

G1

DQA_58

G3

DQA_59

J6

DQA_60

J1

DQA_61

J3

DQA_62

J5

DQA_63

K26

MVREFDA

J26

MVREFSA

J25

MEM_CALRN0

K7

TESTEN

J8

MEM_CALRP1/DPC_CALR

K25

MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

Seymour-S3-XT

51R2J-2-GP

MEMORY INTERFACE

VGA1

P/N: FJPJP

CLKTESTA_C

12

R8419

DY

MAA_14/BA0 MAA_15/BA1

MAA_BA2

RDQSA_0 RDQSA_1 RDQSA_2 RDQSA_3 RDQSA_4 RDQSA_5 RDQSA_6 RDQSA_7

WDQSA_0 WDQSA_1 WDQSA_2 WDQSA_3 WDQSA_4 WDQSA_5 WDQSA_6 WDQSA_7

RSVD#G14

C8407

C8407 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CLKTESTB_C

12

DY

R8418

51R2J-2-GP

3 OF 7

MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8

MAA_9 MAA_10 MAA_11 MAA_12 MAA_13

DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6 DQMA_7

ODTA0

ODTA1

CLKA0

CLKA0#

CLKA1

CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0 CSA0#_1

CSA1#_0 CSA1#_1

CKEA0

CKEA1

WEA0#

WEA1#

PX_EN

1 2

DY

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G20 J16 L15 G11

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

AB16

G14

CLKTESTA

C8406

C8406 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

CLKTESTB

1 2

DY

MAA0 88,89 MAA1 88,89 MAA2 88,89 MAA3 88,89 MAA4 88,89 MAA5 88,89 MAA6 88,89 MAA7 88,89 MAA8 88,89 MAA9 88,89 MAA10 88,89 MAA11 88,89 MAA12 88,89 MAA13 88,89 A_BA0 88,89 A_BA1 88,89 A_BA2 88,89

DQMA0 88 DQMA1 88 DQMA2 88 DQMA3 88 DQMA4 89 DQMA5 89 DQMA6 89 DQMA7 89

QSAP_0 88 QSAP_1 88 QSAP_2 88 QSAP_3 88 QSAP_4 89 QSAP_5 89 QSAP_6 89 QSAP_7 89

QSAN_0 88 QSAN_1 88 QSAN_2 88 QSAN_3 88 QSAN_4 89 QSAN_5 89 QSAN_6 89 QSAN_7 89

ODTA0 88 ODTA1 89

CLKA0 88 CLKA0# 88

CLKA1 89 CLKA1# 89

RASA0# 88 RASA1# 89

CASA0# 88 CASA1# 89

CSA0#_0 88

CSA1#_0 89

CKEA0 88 CKEA1 89

WEA0# 88 WEA1# 89

PX_EN_R

R8440

1 2

0R0402-PAD

R8441

R8441 10KR2J-3-GP

10KR2J-3-GP

DIS

1 2

2010/07/06 Schematics check list: A pull-down resistor is required.

PX_EN 86

11/16 change part reference to R8441 and stuff

11/18 move R8441 before R8440

For normal GPU operation, these signals can be left

floating (do not populate the capacitors and resistors).

A A

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Wednesday, April 13, 2011 Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU Memory(2/5)

Enrico Caruso 14

1

84 105

A00

MEMORY ID Table

DVPDATA[3:0]

0000

0001

0010

0011

D D

For Seymour, DPC_PVDD is DPC_VDD18 DPC_PVSS and all DPC_VSSR are DP_VSSR

2010/07/15 Modify: Q8501 change to dual 2n7002. Add R8512,R8521,C8529 for Q8501 pin2 turn on timming control.

2nd =

H_THERMTRIP#5,22,36

ATI_RST#83

X01: dummy VGA thermal circuit base on DN15

3D3V_VGA_S0

C C

B B

A A

12

R8503

DIS

10KR2J-3-GP

GPIO17_VGA

GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1: Voltage control signals for the core (VDDC and VDDCI). At Reset, these signals will be inputs with weak internal pull-down resistors. VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state.

R8520 3KR2J-2-GP

1 2

DY

R8521 3KR2J-2-GP

1 2

DY

R8523 10KR2J-3-GP

1 2

DY

12/17 dummy R8523 for panel interface unused.

11/18 Del 27M CLK circuit from PCH

2010/07/06 Schematics check list: A 1-M ohm resistor must be connected between XTALIN and XTALOUT when a crystal is used.

DIS

XTALIN

C8524

1 2

SC12P50V2JN-3GP

5

Description

DDR3 SAMSUNG-K4W1G1646G-BC11(900MHz)64M*16

DDR3 Hynix-H5TQ1G63DFR-11C (900MHz) 64M*16

DDR3 SAMSUNG K4W2G1646C-HC11 (900MHz) 128M*16

DDR3 Hynix-H5TQ2G63BFR-11C (900MHz) 128M*16

DVPDATA[0:3] Default:Pull down

2010/06/11

MEM_ID Control

THERMTRIP_VGA

12

R8526

THERMTRIP_R

5

6

Q8501

DY

2N7002KDW-GP

84.2N702.A3F

123 4

R8525

Q5801_2

12

DY

12

0R2J-2-GP

DY

11/18 Del C8529 to follow DN13

PWRCNTL_0

PWRCNTL_1

VGA_BLEN

1D8V_VGA_S0

BLM18PG471SN1D-GP

SC4D7U6D3V3KX-GP

1V_VGA_S0

1 2

L8506 BLM18PG471SN1D-GP

R8502

1 2

DIS

1MR2F-GP

X8501

41

XTAL-27MHZ-85-GP

5

XTALOUT

2 3

R8526

10KR2J-3-GP

C8529

SCD1U10V2KX-5GP

2010/07/07 Change to RSVD based on DS v3.05

(1.8V@75mA DPLL_PVDD)

L8501

1 2

DIS

C8505

DIS

C8517

SC4D7U6D3V3KX-GP

1D8V_VGA_S0 TSVDD

C8525

DIS

1 2

SC12P50V2JN-3GP

1V_VGA_S0

DY

2010/07/07 Remove TP8517,TP8518,TP8506,TP8519,TP8512

TX_DEEMPH_EN83 BIF_GEN2_EN_A83

GPIO5_AC_BATT83

JTAG_TRST#_VGA83

PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC

12

C8515

12

DIS

SC1U6D3V2KX-GP

(1.0V@125mA DPLL_VDDC)

12

DY

DIS

C8518

SC1U6D3V2KX-GP

L8504

DIS

1 2

BLM15BD121SS1D-GP

SC4D7U6D3V3KX-GP

11/2 Stuff X8501, R8502 C8524, C8525

11/29 change X8501 to 82.30034.641

SSID = VIDEO

1D8V_VGA_S0

R8527 10KR2J-3-GP

1 2

R8522 10KR2J-3-GP

1 2

R8519 10KR2J-3-GP

1 2

R8518 10KR2J-3-GP

1 2

L8507

(1.0V@110mA DPC_VDD10)

DIS

1 2

BLM15BD121SS1D-GP

Vendor suggest to reserve test point 09/06

TX_PWRS_ENB83

GPIO8_ROMSO83

VGA_DIS83

CONFIG083 CONFIG183 CONFIG283

GPIO21_BB_EN83 BIOS_ROM_EN83 PEG_CLKREQ#20

JTAG_TCK_VGA20,83 JTAG_TMS_VGA83

DIS

SCD1U10V2KX-5GP

C8519

C8520

Clock Input Configuraiton -GDDR3/DDR3 a) 27MHz crystal connected to XTALIN or XTALOUT or b) 27MHz (1.8V) oscillator connected to XTALIN or c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)

TP8511TPAD14 TP8511TPAD14

DPLL_PVDD

C8516

12

DIS

SCD1U10V2KX-5GP

12

DY

PWRCNTL_092

PWRCNTL_192

1

1D8V_VGA_S0

R8516

249R2F-GP

DPLL_VDDC

12

DIS

12

C8526

DIS

(1.8V@20mA TSVDD)

C8521

SC1U6D3V2KX-GP

4

0923 Modify for DV14 Config

DY

DY DY

DY

1GVRAM

Hynix

DPB_VDD18

2010/06/11

DPC_VDD10

12

C8527

C8528

DIS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SMBUS

1

TP8503TPAD14 TP8503TPAD14

TP8504TPAD14 TP8504TPAD14 TP8508TPAD14 TP8508TPAD14

TP8509TPAD14 TP8509TPAD14

C8514

12

SCD1U10V2KX-5GP

DIS

1 2

DY

1 2

DY

SC2200P50V2KX-2GP

12

DIS

4

SCD1U10V2KX-5GP

TP8507TPAD14 TP8507TPAD14 TP8513TPAD14 TP8513TPAD14

GPIO_VGA_03_DATA GPIO_VGA_04_CLK

1

1 1

1

GPU_VREFG

C8523

TP8512TPAD14 TP8512TPAD14

C8522

SCD1U10V2KX-5GP

1 1

GPIO6_VGA

VGA_BLEN

GPIO16_SSIN GPIO17_VGA GPIO18_VGA THERMTRIP_VGA

JTAG_TDI

JTAG_TDO_VGA

RSVD

GEN_A GEN_B

GENERICE_HPD4

NC#AC22/XO_IN NC#AB22/XO_IN2

12

DY

1

SC10U6D3V5KX-1GP

TP8505TPAD14 TP8505TPAD14

TP8502TPAD14-GP TP8502TPAD14-GP

TP8506TPAD14-GP TP8506TPAD14-GP

TP8510TPAD14 TP8510TPAD14

12

R8515

R8515 499R2F-2-GP

499R2F-2-GP

12

DIS

R8510 0R2J-2-GP

R8510 0R2J-2-GP R8511 0R2J-2-GP

R8511 0R2J-2-GP

P2800_VGA_DXP28

P2800_VGA_DXN28

MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0

GPU_SCL GPU_SDA

XTALIN

AM28

XTALOUT

Change to DY 9/20

FAN_PWM_C

VGA1B

M93-S3/M92-S2

AE9

DVCNTL_0/DVPDATA_18

L9

DVCNTL_1/NC#L9

N9

DVCNTL_2/TESTEN#2

AE8

DVDATA_12/DVPDATA_16

AD9

DVDATA_11/DVPDATA_20

AC10

DVDATA_10/DVPDATA_22

AD7

DVDATA_9/DVPDATA_12

AC8

DVDATA_8/DVPDATA_14

AC7

DVDATA_7/DVPCNTL_0

AB9

DVDATA_6/DVPDATA_8

AB8

DVDATA_5/DVPDATA_6

AB7

DVDATA_4DVPDATA_4

AB4

DVDATA_3/DVPDATA_19

AB2

DVDATA_2/DVPDATA_21

Y8

DVDATA_1/DVPDATA_2

Y7

DVDATA_0/DVPDATA_0

M93-S3/M92-S2

W6

DPC_PVDD/DVPDATA_11

V6

DPC_PVSS/GND

AC6

DPC_VDD18#1/DVPDAT10

AC5

DPC_VDD18#2/DVPDAT23

AA5

DPC_VDD10#1/DVPDAT15

AA6

DPC_VDD10#2/DVPDAT17

U1

DPC_VSSR#1/DVPCLK

W1

DPC_VSSR#2/DVPDAT5

U3

DPC_VSSR#3/GND

Y6

DPC_VSSR#4/GND

AA1

DPC_VSSR#5/DVPCNTL_MV0

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

L6

JTAG_TRST#

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

AF24

RSVD#AF24

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AC16

VREFG

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

XTALIN

AK28

XTALOUT

AC22

NC#AC22/XO_IN

AB22

NC#AB22/XO_IN2

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

Seymour-S3-XT

DVO

I2C

PLL/CLOCK

THERMAL

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P

DPA

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P

TX3M_DPB2N

DPB

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

M92-S2/M93-S3

DVPDATA_3/TXCCP_DPC3P

DVPCNTL_2/TXCCM_DPC3N

DVPDATA_7/TX0P_DPC2P DVPDATA_1/TX0M_DPC2N

DVPCNTL_MV1/TX1P_DPC1P

DVPDATA_9/TX1M_DPC1N

DVPDATA_13/TX2P_DPC0P

DVPCNTL_1/TX2M_DPC0N

DPC

DAC1

M92-S2/M93-S3

R2/NC#AM12

R2#/NC#AK12

G2#/NC#AJ11

DAC2

COMP/NC#AJ9

VGA1

VDD2DI/NC#AD19 VSS2DI/NC#AC19

A2VDD/NC#AE20

A2VDDQ/NC#AE17

R2SET/NC#AG13

M92-S2/M93-S3M92-S2/M93-S3

DDC/AUX

DDCCLK_AUX5P

DDCDATA_AUX5N

NC#AD20/DDCCLK_AUX3P

NC#AC20/DDCDATA_AUX3N

P/N: FJPJP

NC#AA12

HSYNC

VSYNC

AVDD

AVSSQ

VDD1DI VSS1DI

G2/NC#AL11

B2/NC#AK10 B2#/NC#AL9

C/NC#AH12 Y/NC#AM10

H2SYNC V2SYNC

A2VSSQ

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDC6CLK

DDC6DATA

2 OF 7

RSET

3

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

AA12

AM26

R

AK26

R#

AL25

G

AJ25

G#

AH24

B

AG25

B#

AH26 AJ27

GPU_RSET

AD22

AG24 AE22

AE23 AD23

AM12 AK12

AL11 AJ11

AK10 AL9

AH12 AM10 AJ9

AL13 AJ13

AD19

AC19_GND

AC19

AE20

AE17

AE19

R2SET

AG13

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AE16 AD16

AC1 AC3

AD20 AC20

3

VGA_CRT_HSYNC 50,83 VGA_CRT_VSYNC 50,83

DIS

1 2

R8514 499R2F-2-GP

AVDD

12/20 NC R-,G-,B- on SSI and try to co-layout with Rosbson in PT stage

AVSSQ

HSYNC_DAC2 83 VSYNC_DAC2 83

R8504 0R2J-2-GP

1 2

ROB

R8501

1 2

ROB

715R2F-GP

VDD1DI

CRT_GFX_DDCCLK 50 CRT_GFX_DDCDAT 50

0723 Add SMBUS

3D3V_VGA_S0

RN8501

SRN4K7J-8-GP

GPIO_VGA_04_CLK

GPIO_VGA_03_DATA

RN8502

SRN150F-1-GP

AVSSQ

VDD2DI

12/20 Add R8504 for Robson.

A2VDD

A2VDDQ

12/9 chnage R8501 to ROB

0820

AUXP PD 100K AUXN PU 100K Draw on EDP circuit page

4

DIS

1

2 3

2nd =

Q8503

1

2

3 4

2N7002KDW-GP

84.2N702.A3F

DIS

6

5

2

CRT_GFX_R 50

CRT_GFX_G 50

CRT_GFX_B 50

678

DIS_CRT

123

4 5

Modified 9/1

R8517

0R0402-PAD

AVSSQ

12/16 change R8507, R8505 and R8513 to ROB

SML1_CLK 20,27

SML1_DATA 20,27

2

LVDS Interface

VGA1F

LVDS CONTROL

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_DPF0N

LVTMDP

TXCLK_LP_DPE3P

TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

Seymour-S3-XT

12

P/N: FJPJP

1D8V_VGA_S0

3D3V_VGA_S0

1

6 OF 7

AB11

VARY_BL

AB12

DIGON

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24

TXOUT_U3P

AJ23

TXOUT_U3N

VGA1

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19

TXOUT_L3P

AK18

TXOUT_L3N

DY

SC1U6D3V2KX-GP

12

C8503

DIS

SCD1U10V2KX-5GP

12

C8506

DIS

SC1U6D3V2KX-GP

12

C8512

DY

85 105

DIS

VDD2DI

DY

SC1U6D3V2KX-GP

DY

AVDD

12

VDD1DI

12

C8507

12

A2VDDQ

12

A2VDD

12

C8504

AVSSQ

C8509

SC1U6D3V2KX-GP

C8511

DY

C8513

C8513 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

L8502

DIS

1 2

BLM15BD121SS1D-GP

L8503

DIS

1 2

BLM15BD121SS1D-GP

R8507

1 2

0R2J-2-GP

L8505

1 2

BLM15BD121SS1D-GP

R8513

ROB

1 2

0R2J-2-GP

Title

GPU_DP/LVDS/CRT/GPIO(3/5)

Size Document Number Rev

Size Document Number Rev A2

A2

Wednesday, April 13, 2011

Wednesday, April 13, 2011 Date: Sheet of

Date: Sheet of

(1.8V@65mA AVDD)

12

C8501

DIS

SC4D7U6D3V3KX-GP

(1.8V@100mA VDD1DI)

SC4D7U6D3V3KX-GP

(1.8V@100mA VDD2DI)

ROB

SCD1U10V2KX-5GP

ROB

SCD1U10V2KX-5GP

(3.3V@130mA A2VDD)

Enrico Caruso 14

12

C8502

DIS

C8508

(1.8V@2mA A2VDDQ)

C8510

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

A00

5

SSID = VIDEO

1D5V_VGA_S0

D D

1D8V_VGA_S0

L8601

1 2

DIS

BLM15BD121SS1D-GP

68.00084.F81

2ND =

C C

B B

X02-0302 Add R8605, R8609 PU 5V for lower Rdson

A A

L8604

1 2

BLM15BD121SS1D-GP

68.00084.F81

2ND =

L8605

1 2

BLM15BD121SS1D-GP

68.00084.F81

2ND =

(Park: 1.8V@75mA MPV18)

DIS

5

12

C8604

DIS

SC4D7U6D3V3KX-GP

(1.8V@75mA SPV18)

12

C8605

DIS

2010/06/17_1

BIF_VDDC

12

R8605

R8605 1KR2J-1-GP

1KR2J-1-GP

DIS

12/28 Yellow mark for OPI change

12

C8697

C8698

DIS

SC10U6D3V5KX-1GP

(1.8V@110mA VDD_CT)

C8699

3D3V_VGA_S0

12

C8603

DIS

SC1U6D3V2KX-GP

12

DIS

SC4D7U6D3V3KX-GP

DIS

3D3V_VGA_S0

12

R8603

R8603 1KR2J-1-GP

1KR2J-1-GP

DY

SC4D7U6D3V3KX-GP

MPV18

12

C8690

DIS

SCD1U10V2KX-5GP

1V_VGA_S0

SPV18

12

C8694

C8692

DIS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Rds(on) = 1ow VGS=0.7~1.5V

U8601

AO3400A-GP

BIF_VDDC_CORE

DS

84.03400.B37 84.03400.B37

G

PX_EN## PX_EN#

X01: modify to DGPU_PWROK

8209A_EN/DEM_VGA92,93

PX_EN84

12

DIS

12

DIS

2ND =

DGPU_PWROK22,92,93

1D5V_VGA_PWOK

G

S

C8609

C8624

12

C8652

DIS

SC1U6D3V2KX-GP

12

C8601

DIS

SC4D7U6D3V3KX-GP

12

C8673

DIS

SC1U6D3V2KX-GP

L8606

1 2

DIS

BLM15BD121SS1D-GP

68.00084.F81

U8603

U8603 AO3400A-GP

AO3400A-GP

D S

Q8601

DIS

2N7002K-2-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

4

12

C8610

DIS

SCD1U10V2KX-5GP

12

C8625

DIS

SCD1U10V2KX-5GP

12

DIS

SCD1U10V2KX-5GP

12

C8666

DIS

SC1U6D3V2KX-GP

12

C8674

SCD1U10V2KX-5GP

DIS

R8602 0R2J-2-GP

VGA_CORE

DIS

12

C8611

DIS

SC1U6D3V2KX-GP

C8626

12

DIS

SCD1U10V2KX-5GP

12

C8667

DIS

SC1U6D3V2KX-GP

(120mA SPV10)

SPV10

12

C8634

DIS

SC4D7U6D3V3KX-GP

ROB

1 2

5V_S05V_S0

12

R8609

R8609 1KR2J-1-GP

1KR2J-1-GP

DIS

R8601

1 2

1

2

3

74LVC1G08GW-1-GP

12

C8612

DIS

SCD1U10V2KX-5GP

C8627

12

DIS

SCD1U10V2KX-5GP

12

C8635

DIS

SC1U6D3V2KX-GP

3D3V_VGA_S0

12

0R0402-PAD

U8605

B

VCC

DY

A

Y

GND

73.01G08.L04

2ND =

H13 H16 H19

J10 J23 J24

J9 K10 K23 K24

K9 L11 L12 L13 L20 L21 L22

VDDC_CT

AA20 AA21 AB20 AB21

AA17 AA18 AB17 AB18

V12 Y12

U12

AA11

Y11

V11

U11

L17

L16

PCIE_PVDD

AM30

MPV18

L8

SPV18

H7

H8

J7

C8636

M11 M12

SCD1U10V2KX-5GP

M11_M12

AO4468 MAX 3.1A Rds(on) = 101~155mOhm VGS=+/-12V

U8606

U8606 AO3418-GP

AO3418-GP

DIS

DS

84.03418.031

G

Change polarity , switch pin D and pin S.

R8604

9/6

1KR2J-1-GP

DY

1D5V_VGA_PWOK_R

3D3V_VGA_S0

5

4

VGA1D

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

M93-S3/M92-S2

VDDR3

I/O

VDDR3 VDDR3 VDDR3

VDDR4/VDDR5 VDDR4 VDDR4/VDDR5

NC#AA11/VDDR4 DVCLK/VDDR4

NC#V11/VDDR5 NC#U11

MEM CLK

VDDRHA

VSSRHA

PLL

PCIE_PVDD

MPV18

SPV18

SPV10

SPVSS

BACK BIAS

BBP#1 BBP#2

Seymour-S3-XT

BIF_VDDC_1V

PX_EN##

POWER

VGA1

P/N: FJPJP

U8604

U8604 AO3418-GP

AO3418-GP

D S

G

DIS

Q8602

6

2N7002KDW-GP

84.2N702.A3F

2nd =

12

DY

12

DIS

C8653

DIS

VGA_CORE

G

D

12/16 dumy U8605 and stuff R8601 to follow standard schematic.

4

PCIE

PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

CORE

VDDC/BIF_VDDC VDDC/BIF_VDDC

ISOLATED

ISOLATED CORE I/O

CORE I/O

1V_VGA_S0BIF_VDDC

DIS

84.03418.031

PX_EN#

2345

1

4 OF 7

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15

VDDC

N15

VDDC

N17

VDDC

R13

VDDC

R16

VDDC

R18

VDDC

Y21

VDDC

T12

VDDC

T15

VDDC

T17

VDDC

T20

VDDC

U13

VDDC

U16

VDDC

U18

VDDC

V21

VDDC

V15

VDDC

V17

VDDC

V20

VDDC

Y13

VDDC

Y16

VDDC

Y18

VDDC

R21 U21

M13

VDDCI

M15

VDDCI

M16

VDDCI

M17

VDDCI

M18

VDDCI

M20

VDDCI

M21

VDDCI

N20

VDDCI

Non-BACO= HIGH BACO = LOW

3

PCIE_PVDD

(1.8V@504mA PCIE_VDDR)

12

C8613

DIS

12

C8628

DIS

SC1U6D3V2KX-GP

BIF_VDDC

12

DIS

2010/07/08

1D5V_VGA_PWOK

1D5V_VGA_S0

Non-BACO

3

1D8V_VGA_S0

L8707

1 2

DIS

12

C8615

DIS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

(1.0V@1920mA PCIE_VDDC)

12

C8630

C8629

DIS

SC1U6D3V2KX-GP

12

C8646

DY

DIS

SC1U6D3V2KX-GP

12

C8679

DIS

DY

SCD1U10V2KX-5GP

12/28 Yellow mark for OPI change

12

C8657

C8655

DIS

SC1U6D3V2KX-GP

12

C8695

DIS

SC10U6D3V5KX-1GP

R8608

1 2

2K2R2J-2-GP

8209A_EN/DEM_VGA

PX_EN 1D5V_VGA_PWOK_R PX_EN# PX_EN##

DIS

12

HCB2012KF-221T30-GP

HCB2012KF-221T30-GP C8637

C8637

C8616

DIS

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

12

C8631

C8632

DIS

SC1U6D3V2KX-GP

12

C8665

C8649

DIS

SC1U6D3V2KX-GP

12

C8676

C8680

DIS

EMI

SCD1U10V2KX-5GP

12

C8651

DIS

SC10U6D3V5KX-1GP

1V_VGA_S0

12

C8669

C8647

DIS

SC1U6D3V2KX-GP

C8677

SC1U6D3V2KX-GP

12

C8661

C8654

DIS

SC10U6D3V5KX-1GP

SC4D7U6D3V5KX-3GP

(GDDR3/DDR3 1.12V@4A VDDCI)

12

C8659

C8656

DIS

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

12

R8607

R8607 10KR2J-3-GP

10KR2J-3-GP

DY

1

DY

Q8603_G

3

Q8604

Q8604 PMBS3904-1-GP

PMBS3904-1-GP

2

DY

Q8603

G

DY

S

2N7002K-2-GP

1 00 1

0 1BACO

0629 Modify

Q8604_B

0629 Modify

DY

SCD1U10V2KX-5GP

12

C8693

DY

1

0

PX_EN# = High, BIF_VDDC = 1V_VGA_S0 PX_EN## = High, BIF_VDDC = VGA_CORE

12

C8670

DIS

SCD1U10V2KX-5GP

12/2 change property to EMI for BOM control12/6 remove tp8604, 8605

VGA_CORE

3D3V_VGA_S03D3V_S5

D

2

VGA_CORE

12

C8645

DIS

SC1U6D3V2KX-GP

12

C8648

DIS

SC1U6D3V2KX-GP

12

C8675

C8672

SCD1U10V2KX-5GP

C8671

DIS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Close to VGA pin R21, U21

2010/07/13 Modify: Add C8601 for BIF_VDDC

BIF_VDDC

12

C8696

C8700

DIS

C8700

DIS

SC4D7U6D3V2MX-GP

X01: add capacity for BIF_VDDC

11/18 dummy 1D5V_VGA_PWOK

12

R8606

R8606 10KR2J-3-GP

10KR2J-3-GP

DY

circuit

11/2 change net name to 1D5V_VGA_PWOK

1D5V_VGA_PWOK 83

01

2

1

SC10U6D3V3MX-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A2

A2

Wednesday, April 13, 2011

Wednesday, April 13, 2011 Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU_POWER(4/5)

Enrico Caruso 14

1

86 105

A00

5

4

3

2

1

SSID = VIDEO

Vendor suggest

VGA1E

D D

C C

N11_GND N12_GND

B B

AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27

AF32 AG27 AH32

K28 K32

M32

N25 N27 P25 P32 R27 T25 T32 U25 U27

V32 W25 W26 W27

Y25

Y32

N11

N12

N13

N16

N18

N21

R12

R15

R17

R20

T13

T16

T18

T21

U15

U17

U20

V13

V16

V18

Y10

Y15

Y17

Y20

L27

M6

P6 P9

T6

U9

PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

VGA1

5 OF 7

GND GND

GND/EVDDQ

GND GND

GND/EVDDQ

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

VSS_MECH VSS_MECH VSS_MECH

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6 T11 R11

A32 AM1 AM32

VSS_MECH1 VSS_MECH2 VSS_MECH3

LVDS mode(1V@240mA DPEF_VDD10) DP mode(1V@220mA DPEF_VDD10)

2010/07/09 N11 and N12: in Seymour is NC

09/23

1D8V_VGA_S0

R8711

1 2

0R0402-PAD

1V_VGA_S0

R8713

1 2

0R0402-PAD

N11_GND

N12_GND DPCD_CALR DPAB_CALR

1 1 1

R8702 0R2J-2-GP

R8704 0R2J-2-GP

TP8701TPAD14TP8701TPAD14 TP8702TPAD14TP8702TPAD14 TP8703TPAD14TP8703TPAD14

1 2

ROB

1 2

ROB

LVDS mode(1.8V@440mA DPEF_VDD18) DP mode(1.8V@300mA DPEF_VDD18)

DPEF_VDD18

12

DY

12

C8717

DY

SC4D7U6D3V3KX-GP

12

C8721

DY

SC4D7U6D3V3KX-GP

12

C8718

C8719

DY

SC1U6D3V2KX-GP

C8720

SC1U6D3V2KX-GP

1 2

R8701 150R2F-1-GP

DIS

DY

12

SCD1U10V2KX-5GP

C8725

DPEF_VDD18

SCD1U10V2KX-5GP

DPEF_VDD10

DPEF_VDD18

DPEF_VDD10

Vendor suggest 9/23

R8715

1 2

0R0402-PAD

(1.8V@150mA DPB_VDD18)

VGA1G

AG15

DPE_VDD18

AG16

DPE_VDD18

AG20

DPE_VDD10

AG21

DPE_VDD10

AG14

DPE_VSSR

AH14

DPE_VSSR

AM14

DPE_VSSR

AM16

DPE_VSSR

AM18

DPE_VSSR

AF16

DPF_VDD18

AG17

DPF_VDD18

AF22

DPF_VDD10

AG22

DPF_VDD10

AF23

DPF_VSSR

AG23

DPF_VSSR

AM20

DPF_VSSR

AM22

DPF_VSSR

AM24

DPF_VSSR

AF17

DPEF_CALR

AG18

DPE_PVDD

AF19

DPE_PVSS

AG19

DPF_PVDD

AF20

DPF_PVSS

Seymour-S3-XT

DP PLL POWER

DPB_VDD181D8V_VGA_S0

VGA1

7 OF 7

DP A/B POWERDP E/F POWER

DPA_VDD18 DPA_VDD18

DPA_VDD10 DPA_VDD10

DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR

DPB_VDD18 DPB_VDD18

DPB_VDD10 DPB_VDD10

DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR

DPAB_CALR

DPA_PVDD

DPA_PVSS

DPB_PVDD

DPB_PVSS

P/N: FJPJP

DPAB_VDD18

AE11 AF11

DPAB_VDD10

AF6 AF7

AE1 AE3 AG1 AG6 AH5

DPAB_VDD18

AE13 AF13

AF8 AF9

AF10 AG9 AH8 AM6 AM8

AE10

AG8 AG7

AG10 AG11

DPAB_VDD10

R8703

R8703 150R2F-1-GP

150R2F-1-GP

1 2

DIS

DPAB_VDD18

Vendor suggest 09/23

(1.8V@300mA DPAB_VDD18)

12

DY

(1.0V@220mA DPAB_VDD10)

12

DY

12

C8714

C8712

DY

SCD1U10V2KX-5GP

C8702

DY

SCD1U10V2KX-5GP

DY

SC1U6D3V2KX-GP

12

C8703

DY

SC1U6D3V2KX-GP

1D8V_VGA_S0

R8714

1 2

0R0402-PAD

12

0R0402-PAD

C8713

SC4D7U6D3V3KX-GP

R8716

1 2

0R0402-PAD

C8705

SC10U6D3V5KX-1GP

1V_VGA_S0

Seymour-S3-XT

P/N: FJPJP

11/18 Del R8709, C8710,C8711

A A

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

GPU_DPPWR/GND(5/5)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

87 105

1

A00

5

4

3

2

1

SSID = VIDEO

1D5V_VGA_S0 1D5V_VGA_S0

D D

VRAM1_VREF VRAM2_VREF

C C

CLKA084 CLKA0#84

12

R8804

56R2F-1-GP

DIS

GPU_CLKA0_T

12

C8802

SCD01U16V2KX-3GP

B B

DIS

R8803

56R2F-1-GP

DIS

1D5V_VGA_S0

12

DIS

12

R8806

R8806 2K1R2F-GP

2K1R2F-GP

DIS

12

R8805

R8805 2K1R2F-GP

2K1R2F-GP

1 2

R8801 243R2F-2-GP

MAA084,89 MAA184,89 MAA284,89 MAA384,89 MAA484,89 MAA584,89 MAA684,89 MAA784,89 MAA884,89

MAA984,89 MAA1084,89 MAA1184,89 MAA1284,89 MAA1384,89

A_BA084,89 A_BA184,89 A_BA284,89

CKEA084

DQMA284 DQMA184 DQMA084

WEA0#84 CASA0#84 RASA0#84

VRAM1_VREF

VRAM_ZQ1 VRAM_ZQ2

DIS

12

C8803

C8803 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DIS

VRAM1

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

VRAM1

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

H5TQ2G63BFR-11C-GP

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7 NC#L9 NC#L1

NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

MDA3

E3 F7

MDA1

F2

MDA4

F8

MDA2 MDA28

H3

MDA6

H8

MDA0

G2

MDA5

H7

MDA21 MDA12

D7

MDA19

C3

MDA23

C8

MDA18

C2

MDA20

A7

MDA17

A2

MDA22

B8

MDA16

A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

MDA[0..31] 84

QSAP_2 84 QSAN_2 84

QSAP_0 84 QSAN_0 84

ODTA0 84

CSA0#_0 84 MEM_RST 84,89

X01-0211 change VRAM symbol for layout (larger package)

12

C8806

C8806 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

DY

VRAM1_VREF VRAM2_VREF

1 2

R8802 243R2F-2-GP

DIS

MAA084,89 MAA184,89 MAA284,89 MAA384,89 MAA484,89 MAA584,89 MAA684,89 MAA784,89 MAA884,89

MAA984,89 MAA1084,89 MAA1184,89 MAA1284,89 MAA1384,89

A_BA084,89 A_BA184,89 A_BA284,89

CLKA084 CLKA0#84

CKEA084

DQMA384

WEA0#84 CASA0#84 RASA0#84

1D5V_VGA_S0

12

R8808

R8808 2K1R2F-GP

2K1R2F-GP

DIS

12

R8807

R8807 2K1R2F-GP

2K1R2F-GP

DIS

VRAM2_VREF

VRAM2

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

H5TQ2G63BFR-11C-GP

12

C8805

C8805 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DIS

VRAM2

12

DY

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

C7

DQSU

B7

DQSU#

F3

DQSL

G3

DQSL#

K1

ODT

L2

CS#

T2

RESET#

T7

NC#T7

L9

NC#L9

L1

NC#L1

J9

NC#J9

J1

NC#J1

J8

VSS

M1

VSS

M9

VSS

J2

VSS

P9

VSS

G8

VSS

B3

VSS

T1

VSS

A9

VSS

T9

VSS

E1

VSS

P1

VSS

G1

VSSQ

F9

VSSQ

E8

VSSQ

E2

VSSQ

D8

VSSQ

D1

VSSQ

B9

VSSQ

B1

VSSQ

G9

VSSQ

C8807

C8807 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

MDA27 MDA29MDA7 MDA31 MDA25

MDA24 MDA30 MDA26

MDA10 MDA13 MDA11 MDA8 MDA15 MDA9 MDA14

MDA[0..31] 84

QSAP_1 84 QSAN_1 84

QSAP_3 84 QSAN_3 84

ODTA0 84

CSA0#_0 84 MEM_RST 84,89

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM1,2 (1/4)

Enrico Caruso 14

88 105

1

A00

5

4

3

2

1

SSID = VIDEO

Simulation 10/07

12

C8906

C8902

D D

DIS

SC1U6D3V2KX-GP

DIS

SCD1U10V2KX-5GP

12

C8909

C8908

C8911

DIS

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

Simulation 10/07

DIS

SC1U6D3V2KX-GP

12

C8910

C8913

DIS

SCD1U10V2KX-5GP

12

C8905

DIS

12

C8912

DIS

SCD1U10V2KX-5GP

12

C8907

DIS

12/28 Yellow mark for OPI change

SC10U6D3V5KX-1GP

VRAM3_VREF VRAM4_VREF

C C

CLKA184 CLKA1#84

12

R8907

56R2F-1-GP

DIS

C8903

DIS

C8903

SCD01U16V2KX-3GP

B B

R8908

56R2F-1-GP

DIS

GPU_CLKA1_T

12

SC10U6D3V5KX-1GP

1 2

R8903 243R2F-2-GP

DIS

MAA084,88 MAA184,88 MAA284,88 MAA384,88 MAA484,88 MAA584,88 MAA684,88 MAA784,88 MAA884,88

MAA984,88 MAA1084,88 MAA1184,88 MAA1284,88 MAA1384,88

A_BA084,88 A_BA184,88 A_BA284,88

12

CKEA184

DQMA584 DQMA484

WEA1#84 CASA1#84 RASA1#84

VRAM_ZQ3 VRAM_ZQ4

VRAM3

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

VRAM3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

H5TQ2G63BFR-11C-GP

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

MDA35

E3

MDA39

F7

MDA33

F2

MDA36

F8

MDA34

H3

MDA37

H8

MDA32

G2

MDA38

H7

MDA45

D7

MDA40 MDA53

C3

MDA47 MDA49

C8

MDA41

C2

MDA44

A7

MDA43

A2

MDA46

B8

MDA42

A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

MDA[32..63] 84

12/28 Yellow mark for OPI change

QSAP_5 84 QSAN_5 84

QSAP_4 84 QSAN_4 84

ODTA1 84

CSA1#_0 84 MEM_RST 84,88

Simulation 10/07

12

C8917

C8919

DIS

SCD1U10V2KX-5GP

CLKA184 CLKA1#84

12

C8921

C8920

DIS

SCD1U10V2KX-5GP

VRAM3_VREF VRAM4_VREF

DIS

SCD1U10V2KX-5GP

12

C8923

C8922

DIS

SCD1U10V2KX-5GP

12

C8916

DIS

SC10U6D3V5KX-1GP

R8904 243R2F-2-GP

MAA084,88 MAA184,88 MAA284,88 MAA384,88 MAA484,88 MAA584,88 MAA684,88 MAA784,88 MAA884,88

MAA984,88 MAA1084,88 MAA1184,88 MAA1284,88 MAA1384,88

A_BA084,88 A_BA184,88 A_BA284,88

X01-0211 change VRAM symbol for layout (larger package)

12

C8915

DIS

SC1U6D3V2KX-GP

C8918

1 2

DIS

CKEA184

DQMA684 DQMA784

WEA1#84 CASA1#84 RASA1#84

1D5V_VGA_S01D5V_VGA_S0

12

C8914

DIS

SC1U6D3V2KX-GP

12

DIS

SC10U6D3V5KX-1GP

VRAM4

K8

VDD

K2

VDD

N1

VDD

R9

VDD

B2

VDD

D9

VDD

G7

VDD

R1

VDD

N9

VDD

A8

VDDQ

A1

VDDQ

C1

VDDQ

C9

VDDQ

D2

VDDQ

E9

VDDQ

F1

VDDQ

H9

VDDQ

H2

VDDQ

H1

VREFDQ

M8

VREFCA

L8

ZQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC#

T3

A13

M7

NC#M7

VRAM4

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK#

K9

CKE

D3

DMU

E7

DML

L3

WE#

K3

CAS#

J3

RAS#

H5TQ2G63BFR-11C-GP

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSU#

DQSL

DQSL#

ODT

CS#

RESET#

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

MDA61

E3

MDA59

F7

MDA62

F2

MDA57

F8

MDA63

H3

MDA56

H8

MDA60

G2

MDA58

H7

MDA52

D7 C3 C8

MDA54

C2

MDA48

A7

MDA55

A2

MDA50

B8

MDA51

A3

C7 B7

F3 G3

K1

L2 T2

T7 L9 L1 J9 J1

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

G1 F9 E8 E2 D8 D1 B9 B1 G9

MDA[32..63] 84

QSAP_6 84 QSAN_6 84

QSAP_7 84 QSAN_7 84

ODTA1 84

CSA1#_0 84 MEM_RST 84,88

1D5V_VGA_S0

12

R8901

R8901 2K1R2F-GP

2K1R2F-GP

DIS

VRAM3_VREF

12

R8902

R8902 2K1R2F-GP

2K1R2F-GP

DIS

A A

5

4

12

C8901

C8901 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DIS

12

C8924

C8924 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

DY

3

1D5V_VGA_S0

2

12

R8905

R8905 2K1R2F-GP

2K1R2F-GP

DIS

12

R8906

R8906 2K1R2F-GP

2K1R2F-GP

DIS

VRAM4_VREF

12

C8904

SCD1U10V2KX-5GP

DIS

DN15ATI Whistler

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Wednesday, April 13, 2011

Date: Sheet of

12

C8925

C8925 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

GPU-VRAM3,4 (2/4)

Enrico Caruso 14

89 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

GPU-VRAM5,6 (3/4)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

90 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

GPU-VRAM7,8 (4/4)

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

91 105

1

A00

5

4

3

2

1

SSID = PWR.Plane.Regulator_VGACORE

VGA_CORE VGA_CORE_PWR VGA_CORE

PG9202

GAP-CLOSE-PWR-3-GP

11/10

GAP-CLOSE-PWR-3-GP

DCBATOUT PWR_DCBATOUT_VGA_CORE

PG9204

GAP-CLOSE-PWR-3-GP

D D

GAP-CLOSE-PWR-3-GP

C C

1 2

PG9207

1 2

PG9210

1 2

PG9213

1 2

PG9215

1 2

SC1U10V2KX-1GP

PC9208

SC1U10V2KX-1GP

12

DIS

PR9208

1 2

10KR2J-3-GP

2 1

CH551H-30PT-GP

PG9218

1 2

X01-0217 PR9205 to 10K (F)

12/17 change PR9208 to 5% for meet standard schematic.

3D3V_VGA_S0

DGPU_PWR_EN93

11/18 Stuff PD9201

12/16 Dummy PD9201 to follow DN13, 15

PD9201

PC9206

DIS

10R2F-L-GP

12

DIS

DY

12

DIS

PR9204

PR9205

PR9205 10KR2F-L1-GP

10KR2F-L1-GP

12/2

5V_S5

12

PWR_VGA_CORE_VDD

PWR_VGA_CORE_PGOOD

8209A_EN/DEM_VGA

12

PC9211

PC9211 SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

PWR_VGA_CORE_TON

PU9201

16

TON

9

VDDP

2

VDD

4

PGOOD

10

CS

DIS

15

EM/DEM

17

GND

RT8208BGQW-GP

8209A_EN/DEM_VGA 86,93

Freq=360KHz

13

BOOT

12

UGATE

11

PHASE

8

LGATE

7

G0

3

FB

14

G1

5

D1

6

D0

1

VOUT

PR9202

1 2

DIS

200KR2F-L-GP

PWR_VGA_CORE_BOOT

PWR_VGA_CORE_UGATE PWR_VGA_CORE_PHASE PWR_VGA_CORE_LGATE

PWR_VGA_CORE_FBPWR_VGA_CORE_CS

PWR_VGA_CORE_D1 PWR_VGA_CORE_D0

PWR_VGA_CORE_VOUT

PWR_VGA_CORE_PGOOD

SC100P50V2JN-3GP

PR9203

2D2R3-1-U-GP

DIS

PWRCNTL_0 85

PWRCNTL_1 85

PC9212

DIS

PWR_VGA_CORE_BOOT_C

12

3D3V_VGA_S0

12

PR9209

PR9209 10KR2J-3-GP

10KR2J-3-GP

PR9212

12

0R0402-PAD

12

DIS

PC9201

SCD1U25V3KX-GP

1 2

DIS

PWR_DCBATOUT_VGA_CORE

12/15

PU9202

567

DDD

G

4

12/15

PU9203

567

DDD

G

4

DIS

DGPU_PWROK22,86,93

DIS

1 2

SC10U25V5KX-GP

PC9213

PC9213 SC560P50V-GP

SC560P50V-GP

DIS

PC9203

SC10U25V5KX-GP

PL9201

1 2

COIL-D68UH-9-GP

X02-0310 stuff PC9205

1 2

PC9205

PC9204

SCD1U25V2KX-GP

SC10U25V5KX-GP

12/15

DIS

PWR_VGA_CORE_VOUT

PWR_VGA_CORE_FB

12

11/15

DIS

PR9210

75KR2F-GP

10R2J-2-GP

11/18

PR9218

10KR2F-2-GP

12

PR9211

DIS

PR9201

DIS

150KR2F-L-GP

12

PR9201_2

1 2

12

DIS

BOM merge 11/18

GAP-CLOSE-PWR-3-GP

PG9221

PC9209

12

SC10P50V2JN-4GP

DY

PR9213

PR9213 49K9R2F-L-GP

49K9R2F-L-GP

Design Current = 13.6A

21.3A<OCP< 25.3A

VGA_CORE_PWR

12

PC9207

SCD1U10V2KX-5GP

DIS

PC9210

12

SC10P50V2JN-4GP

DY

12

PT9201

ST330U2VDM-3GP

DY

X01-0217 change PT9202 -->79.33719.20L PT9203 -->79.33719.L01

I/P cap: 10U 25V K0805 X5R/ 78.10622.51L Inductor: 0.68UH PCMB063T-R68MS Cyntec 4.8mohm/5.3mohm Isat =17Arms 68.R6810.20J O/P cap: 330U2V EEFCX0D331R 15mOhm 2.7Arms Panasonic/79.33719.20D H/S: SIR172DP / 10.3mohm/12.4mOhm@4.5Vgs/ 84.00172.037 L/S: SiR460DP / 0.49mohm/0.61mOhm@4.5Vgs/ 84.00460.037

12

PT9202

PT9203

ST330U2VDM-4-GP

SE330U2VDM-L-GP

DIS

SE330U2VDM-L-GP

DIS

11/18

DIS

1 2

PC9202

8

D

DIS

SSS

123

RJK03B9DPA-00-J5A-GP

12

DY

8

D

PR9206

PR9206 2D2R5F-2-GP

2D2R5F-2-GP

SSS

PR9206_2

12

123

DY

RJK03D4DPA-00-J5A-GP

1 2

GAP-CLOSE-PWR-3-GP

PG9205

1 2

GAP-CLOSE-PWR-3-GP

PG9208

1 2

GAP-CLOSE-PWR-3-GP

PG9211

1 2

GAP-CLOSE-PWR-3-GP

PG9201

1 2

GAP-CLOSE-PWR-3-GP

PG9216

1 2

GAP-CLOSE-PWR-3-GP

PG9219

1 2

GAP-CLOSE-PWR-3-GP

PG9203

1 2

PG9209

1 2

PG9214

1 2

PG9217

1 2

PG9220

1 2

PG9212

1 2

PG9206

PWR_VGA_CORE_D1

RT8208B for Seymour-XT

PWRCNTL_1

L

B B

H

PWRCNTL_0

L

H

VGA_CORE_PWR

1.05V

1.0VH

0.9V

RT8208B for Robson-XT

PWRCNTL_1

L

H

For Robson: PR9218=10K PR9213=49.9K PR9211=150K PR9210=44.2K

PWRCNTL_0

VGA_CORE_PWR

L

H

1.12V

0.95VL

0.9V

Vout=0.75V*(R1+R2)/R2

PWR_VGA_CORE_D0

GND_SENSE_1

12

PR9216

10R2J-2-GP

DIS

11/15

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8208B_+VGA_CORE

Size Document Number Rev

A2

Enrico Caruso 14

Date: Sheet of

5

4

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

1

A00

92 105Wednesday, April 13, 2011

A00

5

4

3

2

1

3D3V_S0 to 3D3V_VGA_S0 Transfer

Change DUMMY Reference Name to PX_BACO

3D3V_S0

PR9316

3D3V_S0

PR9316 10KR2J-3-GP

10KR2J-3-GP

DIS

1 2

PR9319_1

2nd = 84.DM601.03F

DGPU_PWR_EN#

L

H

L

D D

C C

dGPU mode

IGPU

IGPU with BACO

1D5V_VGA_S0

1D5V_S3 to 1D5V_VGA_S0 trace need increase to avoid 1D5V_VGA_S0 DROP Voltage.

B B

Park_Madison Does Not Support BACO, So follow Old Sequence Seymour_Whistler_Robson Support BACO, So Change Sequence

DGPU_PWR_EN92

X01 :dummy PR9326

DGPU_PWROK22,86,92

8209A_EN/DEM_VGA86,92

11/18 Add PR9327 for 8209A_EN/DEM_VGA turn on 1D5V_VGA_S0 power.

A A

12

DIS

PC9324

PC9324 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1 2

PQ9303

PQ9303 2N7002KDW-GP

2N7002KDW-GP

84.2N702.A3F

PR9321

1 2

10KR2J-3-GP

PD9301

2 1

CH551H-30PT-GP

5

DY

PR9301

1 2

0R2J-2-GP

DMP2130L-7-GP

PQ9302

S

D

G

84.02130.031

2ND = 84.03413.A31

DIS

G

PQ9302_G

PR9319

DIS

10KR2J-3-GP

5

6

DIS

123 4

DIS

DGPU_PWR_EN

change low Rds(on) MOSFET

AO4468, SO-8 Id=?A, Qg=9~12nC Rdson=17.4~22m ohm

3D3V_AUX_S5

1 2

PR9332

DIS

2nd = 84.DM601.03F

DY

PR9326

1 2

0R2J-2-GP

DY

PR9327

1 2

0R0402-PAD

3D3V_VGA_S0

3.3V_RUN_VGA_1

100KR2J-1-GP

2N7002KDW-GP

84.2N702.A3F

3D3V_VGA discharge

PR9314

PR9314 470R2J-2-GP

470R2J-2-GP

DIS

1 2

DGPU_PWR_EN 92

1D5V_VGA_EN#

6

PQ9305

123 4

1D5V_VGA_EN

DGPU_PWR_EN#18

DIS_1D8V_VGA_S0

11/18 Merge PQ9803 PQ9804 to PQ9312

1D5V_S3 1D5V_VGA_S0

PU9305

S

D

S

D

1

8

S

D

S

D

2

7

S

D

S

D

3

6

GD

12

PC9327

DIS

2nd = 84.08882.037

SC10U6D3V3MX-GP

DIS

PC9326

SCD01U50V2KX-1GP

5

DIS

GGDDSS

1D5V_ENABLE

DIS

AO4468-GP

84.04468.037

1 2

12

20KR2F-L-GP

DIS

15V_S5

PR9331

PR9331 100KR2J-1-GP

100KR2J-1-GP

DIS

1 2

PR9330

45

1D5V_ENABLE_RC

4

PQ9312

1

2

DIS

3 4

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

12

PC9332

SC10U6D3V3MX-GP

DIS

Discharge Circuit

1D5V_VGA_S0

12

PR9336

PR9336 470R2J-2-GP

470R2J-2-GP

DIS

2ND = 84.2N702.031

84.2N702.J31

2N7002K-2-GP

DIS_1D5V_VGA_S0

D

DIS

PQ9307

6

5

G

S

DGPU_PWR_EN

1D8V_VGA_EN#

1D5V_VGA_EN#

G9731 for 1V_VGA_S0

Park_Madison Does Not Support BACO, So follow Old Sequence

Seymour_Whistler_Robson Support BACO, So Change Sequence

3D3V_VGA_S0 should ramp-up before VGA_Core

VGA_Core should ramp-up before 1V_VGA_S0

1V_VGA_S0 should ramp up before 1D8V_VGA_S0

so 1V_VGA_S0 EN have to fine tune RC delay after VGA_Core

3D3V_AUX_S5

1D8V_VGA_S0

DGPU_PWR_EN92

1D8V_VGA_S0

3D3V_VGA_S0

DGPU_PWR_EN92

PR9318

1 2

DIS

100KR2J-1-GP

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PWR_1V_EN

3

1D8V_VGA_ENG9731_PGOOD_1V

PR9320

1 2

0R0402-PAD

12

DY

PD9303

2 1

DY

CH551H-30PT-GP

1D8V_VGA_S0_PG

DY

PR9340

1 2

2K2R2J-2-GP

GAP-CLOSE-PWR-3-GP

DIS

1 2

PR9312 10KR2J-3-GP

PD9302

2 1

DY

CH551H-30PT-GP

PWR_1V_EN#

5

6

PQ9311

123 4

DIS

PQ9311_3

AO4468, SO-8 Id=??A, Qg=9~12nC Rdson=17.4~22m ohm

3D3V_AUX_S5

PR9334

PC9323

SCD1U10V2KX-5GP

PQ9310_B

SCD1U10V2KX-5GP

12

PC9301

DY

1D5V_S3

1 2

SC10U10V5KX-2GP

3D3V_VGA_S0

G9731_PGOOD_1V

PWR_1V_EN

Discharge Circuit

PR9317

12

DIS

470R2J-2-GP

1D8V_S0

PU9306

D

8

DIS

D

7

D

6

12

PC9330

SC10U6D3V3MX-GP

1 2

DIS

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PQ9310_C

3

DY

1

2

1V_VGA_S0_LDOIN

PG9301

PG9302

PG9303

PG9304

PC9303

DIS

1V_VGA_S0

DIS

1D8V_VGA_EN# 1D8V_ENABLE_RC

100KR2J-1-GP

6

PQ9306

123 4

PR9338

PR9338 100KR2J-1-GP

100KR2J-1-GP

DY

1 2

2N7002K-2-GP

G

S

PQ9309

PQ9310

84.2N702.J31

PMBS3904-1-GP

2ND = 84.2N702.031

84.03904.L06

2nd = 84.03904.P11

3rd = 84.03904.T11

5V_S5

SC1U10V2KX-1GP

1 2

DIS

1 2

PR9304 100KR2J-1-GP

PR9311

1 2

0R0402-PAD

PC9318

SCD1U10V2KX-5GP

12

AO4468-GP

84.04468.037

2nd = 84.08882.037

5

DIS

GGDDSS

1D8V_ENABLE

3D3V_VGA_S03D3V_S5

DY

D

12

PC9313

DIS

2

15V_S5

12

PR9339

10KR2J-3-GP

DY

PWR_1V_PGOOD

S

1

S

2

S

3

GD

45

PR9335

PR9335 100KR2J-1-GP

100KR2J-1-GP

DIS

1 2

1D8V_S0_VGA_PG 83

2nd = 74.05930.03D

1D8V_VGA_S0

PR9333

DIS

20KR2F-L-GP

PU9303

5

DIS

VIN

6

VO#4

VPP POK7VO#3

8

VEN

ADJ

9

GND

G9731F11U-GP

74.G9731.03D

12

PC9331

SC10U6D3V3MX-GP

DIS

12

DIS

PC9329

PC9329 SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

1D8V_VGA_S0

12

DIS_1D8V_VGA_S0

PR9337

PR9337 470R2J-2-GP

470R2J-2-GP

DIS

Discharge Circuit

1V_VGA_S0 Design current = 2.445A

Vout=0.8V*(R1+R2)/R2= 1.0036V

Vo(cal.)=1.0036V

4 3 2 1

12

PR9322

PR9322 1K27R2F-L-GP

1K27R2F-L-GP

DIS

PWR_1V_ADJ

12

PR9315

PR9315 4K99R2F-L-GP

4K99R2F-L-GP

DIS

Title

Size Document Number Rev

A2

Date: Sheet of

1V_PWR

12

PC9012

DY

DIS

PC9317

PC9316

12

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

DISCRETE VGA POWER

Enrico Caruso 14

1

1V_VGA_S0

PG9305

1 2

GAP-CLOSE-PWR-3-GP

PG9306

1 2

GAP-CLOSE-PWR-3-GP

PG9307

1 2

GAP-CLOSE-PWR-3-GP

PG9308

1 2

GAP-CLOSE-PWR-3-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

93 105Wednesday, April 13, 2011

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

LVDS_Switch

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

94 105

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

DN15ATI Whistler

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

CRT_Switch

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

95 105

1

A00

5

4

3

2

1

SSID = SDIO

D D

C C

(Blanking)

B B

A A

5

4

3

2

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

TOUCH PANEL

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

96 105

1

A00

H1

H1 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

5

H2

H2 HOLE256R115-GP

HOLE256R115-GP

H3

H3 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

H4

H4 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

4

H5

H5 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

H6

H6 HT85BE85R29-U-5-GP

HT85BE85R29-U-5-GP

3

H7

HT85B95X975R29-S-GP

2

X01-0208 stuff SPR1 and add SPR2

1

SSID = Mechanical

A00-0406 dummy SPR2

1

D D

1

SPR1

SPR1 SPRING-62-GP

SPRING-62-GP

1

34.39S07.003

SPR2

DY

SPRING-58-GP

1

34.4B312.002

X02-0314 stuff SPR2

12/17 add SPR1 for EMI

12/21 change SPR1 to 34.4B312.002

12/22 change SPR1 to 34.39S07.003

X01-0211 change SPR2, SPR3 to 34.4B312.002

X01-0210 add SPR3

For CPU BRACKET VGA Stand-Off PCH Stand-Off

H11

H11 STF237R117H83-1-GP

H8

H8 HOLE197R166-1-GP

HOLE197R166-1-GP

1

C C

H9

H9 HOLE197R166-1-GP

HOLE197R166-1-GP

1

H10

H10 HOLE197R166-1-GP

HOLE197R166-1-GP

1

STF237R117H83-1-GP

DIS

1

H12

H12 STF217R113H162-GP

STF217R113H162-GP

1

H13

H13 STF237R117H83-1-GP

STF237R117H83-1-GP

DY

1

SPR3

SPR3 SPRING-58-GP

SPRING-58-GP

1

34.4B312.002

SPR4

SPR4 SPRING-13-GP-U

SPRING-13-GP-U

1

34.43E24.001

X01-0211 add SPR4, SPR5

SPR5

SPR5 SPRING-13-GP-U

SPRING-13-GP-U

1

34.43E24.001

A00-0412 dummy H12, H13 for remove PCH Heatsink

A00-0413 change H12 to 34.4HL17.001

12/2 Delete SPR1, SPR2

DCBATOUT

12

EC9701

EC9702

SCD1U25V2KX-GP

5V_S5 PWR_3D3V_DCBATOUT 3D3V_S5 1D5V_S3 VCC_GFXCORE

B B

12

EC9720

SCD1U25V2KX-GP

VCC_CORE

12

EC9733

SCD1U25V2KX-GP

DY

SCD1U25V2KX-GP

X02-0314 stuff EC9722

12

EC9721

SCD1U25V2KX-GP

12

EC9734

SCD1U25V2KX-GP

12

EC9703

SCD1U25V2KX-GP

DY

EC9722

SCD1U25V2KX-GP

EC9735

SCD1U25V2KX-GP

12

EC9704

EC9705

SCD1U25V2KX-GP

12

EC9723

SCD1U25V2KX-GP

12

EC9736

SCD1U25V2KX-GP

12

EC9724

SCD1U25V2KX-GP

1D05V_VTT 5V_S5

12

EC9737

SCD1U25V2KX-GP

12

EC9707

EC9706

SCD1U25V2KX-GP

12

DY

EC9726

EC9725

SCD1U25V2KX-GP

12

EC9738

EC9739

SCD1U25V2KX-GP

12

EC9709

EC9708

SCD1U25V2KX-GP

12

EC9727

SCD1U25V2KX-GP

12

EC9740

SCD1U25V2KX-GP

3D3V_S5

12

DY

EC9710

SCD1U25V2KX-GP

12/15 Stuff EC9727

BT+

12

EC9741

SCD1U25V2KX-GP

DY

EC9711

SCD1U25V2KX-GP

12

DY

12/17 Add EC9741

A A

5

4

12

DY

12

EC9713

EC9714

SCD1U25V2KX-GP

12

EC9712

SCD1U25V2KX-GP

12

EC9716

EC9715

SCD1U25V2KX-GP

12

EC9717

SCD1U25V2KX-GP

12

DY

EC9718

EC9719

SCD1U25V2KX-GP

AUD_AGND

DY

1 2

EC9743

EC9742

SCD1U10V2KX-5GP

DY

1 2

EC9744

SCD1U10V2KX-5GP

1 2

EC9745

EC9746

SCD1U10V2KX-5GP

X01-0208 add EC9742~EC9746

12

DY

EC9729

EC9728

SCD1U25V2KX-GP

EC9729

SCD1U25V2KX-GP

12

DY

EC9731

EC9730

SCD1U25V2KX-GP

12

EC9732

SCD1U25V2KX-GP

12/6 Add EMI capacities

12/20 change EMI caps to 0402 package

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number Rev

Size Document Number Rev A3

A3

Wednesday, April 13, 2011

Date: Sheet of

3

2

Date: Sheet of

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

97 105

1

A00

5

4

3

2

1

Huron River Platform Power Sequence

(AC mode)

+RTC_VCC

RTC_RST#

Within logic high level and disable if it is less than the logic low level.

D D

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

Not floating.

Sense the power button status

This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input.

C C

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

DCBATOUT

3D3V_AUX_S5

S5_ENABLE

5V_S5

3D3V_S5

PM_RSMRST#(EC Delay 40ms)

PCH_SUSCLK_KBC

AC_PRESENT

AC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK T20

1D05V_VTT T21

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

B B

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

KBC_PWRBTN#

PM_PWRBTN#

AC

T1

>9ms

T2

3D3V_AUX_KBC

PM_PWRBTN#

T10

ALL_SYS_PWRGD=D85V_PWRGD

D85V_PWRGD

1D8V_S0

T3

T4

0D85V_S0

T5+5VA_PCH_VCC5REFSUS

T6

>10ms

Press Power button

T11

>30us

T12

T13

T14

T15

T17

T18

T19

T24

>99ms

T27

2ms< <650ms

T29

red word: KBC GPIO

KBC GPIO34 control power on by 3V_5V_EN

>5ms

<90msT7T8

0ms<

>16ms

T9

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

>0us

T28

>1ms

T30

>2ms

T31

5ms< <650ms

T32

KBC GPIO43 to PCH

PCH to KBC GPIO00

KBC GPO84 to PCH

Platform to KBC PSL_IN2

KBC GPIO20 to PCH

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

T22

SetVID ACK

T33

1ms<

T35

1D8V_S0 & 1D5V_S3 power ready

VT357FCX PGOOD

T23

TPS51461RGER PGOOD

<2000us50us<

T25

T26

ISL95831 PGOOD to system

<5ms

KBC GPIO77 to PCH

>0ms

<100ms

T34

>1ms+60us

T36

PCH to all system

<200us

PCH to CPU

(DC mode)

Sense the power button status

V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within

0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V.

V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V.

This signal represents the Power Good for all the non-CORE and non-graphics power rails.

+RTC_VCC

RTC_RST#

DCBATOUT

3D3V_AUX_S5

KBC_PWRBTN#

3D3V_AUX_KBC

S5_ENABLE

5V_S5

3D3V_S5

+5VA_PCH_VCC5REFSUS

PM_PWRBTN#

PM_RSMRST#

PCH_SUSCLK_KBC

DC

PM_SLP_S4#

PM_SLP_S3#

PM_LAN_ENABLE

1D5V_S3

DDR_VREF_S3(0.75V)

5V_S0

3D3V_S0

+5VS_PCH_VCC5REF

1D5V_S0

1D8V_S0

0D75V_S0

RUNPWROK T20

1D05V_VTT T21

1.05VTT_PWRGD

0D85V_S0

D85V_PWRGD

CPU SVID BUS

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

CLK_EXP_P

PWROK

VDDPWRGOOD

H_CPUPWRGD

SYS_PWROK

PLT_RST#

DMI

T1

PCH_RSMRST#

red word: KBC GPIO

>9ms

T2

Press Power button

T10

T11

>30us

0D85V_S0

ALL_SYS_PWRGD=D85V_PWRGD

T27

D85V_PWRGD

2ms< <650ms

1D8V_S0

>99ms

Platform to KBC PSL_IN2

T3

T4

T5

T6

T12

T13

T14

T15

T17

T18

T19

T24

T28

T29

EC_ENABLE#_1(GPIO31) keep low

KBC GPIO34 control power on by 3V_5V_EN

+5V_ALW & +3.3V_ALW need meet 0.7V difference

T7

>16ms

T8

>10ms

T9

>5ms

KBC GPIO20 to PCH

KBC GPIO43 to PCH

PCH to KBC GPIO00

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T16

SetVID ACK

>0us

>1ms

T30

>2ms

T31

5ms< <650ms

T32

PCH to KBC GPIO44

PCH to KBC GPIO01

KBC GPIO23 to LAN

Enable by PM_SLP_S4#

1D8V_S0 & 1D5V_S3 power ready

T22

T23

<2000us50us<

T25

T26

<5ms

>0ms

T33

<100ms

1ms<

T35

VT357FCX PGOOD

TPS51461RGER PGOOD

ISL95831 PGOOD to system

KBC GPIO77 to PCH

PCH to CPU

>1ms+60us

T34

PCH to all system

<200us

T36

Robson XT Power-Up/Down Sequence

DGPU_PWR_EN#(Discrete only)

3D3V_VGA_S0(Discrete only)

8209A_EN/DEM_VGA(Discrete only)

A A

VGA_CORE(Discrete only)

1V_VGA_S0(Discrete only)

9035_PGOOD_1V(Discrete only)

1D8V_VGA_S0(Discrete only)

DGPU_PWROK(Discrete only)

1D5V_VGA_S0(Discrete only)

3D3V_S0

Ta

>0ms

Tb

Tc

Td

>0ms

<20ms

For power-down, reversing the ramp-up sequence is recommended.

5

PCH GPIO54 output

3D3V_VGA_S0 above VT357 VIH

RT9035 PGOOD

VT357 PGOOD

4

Title

Size Document Number Rev

A1

Date: Sheet of

Wednesday, April 13, 2011

Date: Sheet of

Wednesday, April 13, 2011

Date: Sheet of

3

2

Wednesday, April 13, 2011

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence

Enrico Caruso 14

A00

98

105

5

4

3

2

1

Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

AC Adapter in

D D

PWR_CHG_ACOK

DC

Battery

C C

BT+

Page39

Page38

SWITCH

BQ24745 Charger

Page40

-1

Power Button

AD+

Page40

DCBATOUT

ACOK

5V_S5 DCBATOUT

-6.1

-4

AC_IN#

KBC_PWRBTN#

PM_SLP_S4#

PM_SLP_S3#

-3.1 -3.1 -3.1

1

PWR_5V3D3V_ENC

ENC

RT8223MGQW DC/DC (3V/5V)

VIN

-3

3D3V_AUX_KBC

GPIO70

KBC

GPIO6

NPCE795P

GPIO44

GPIO01

GPIO34

GPIO43

GPIO20

Page27

GPIO77

LL1

LL2

VREG5

VREG3

PGOOD

Page41

-3.2

5V_S5

3D3V_S5

5V_AUX_S5

3D3V_AUX_S5

3V_5V_POK

-3.1

S5_ENABLE

-2.1

PM_RSMRST#

PM_PWRBTN#

S0_PWR_GOOD

SYS_PWROK

2

3V_5V_EN S5_ENABLE

-3.3

15V_S5

PUMP

-5

-2

BJT

SLP_S4# SLP_S3#

RSMRST#

PWRBTN#

Cougar Point

3

4

DRAMPWRGD

PROCPWRGD

PM_SLP_S4#

PM_SLP_S3#

PCH

APWROK

PWROK

SYS_PWROK

PLTRST#

10

11

12

13

PLT_RST#

SWITCH

Page37

SWITCH

Page37

SWITCH

Page37

5V_S0

3D3V_S0

1D5V_S0

0D75V_EN

PM_DRAM_PWRGD

H_CPUPWRGD

AND GATE

B

A

Y

VDDPWRGOOD

H_CPUPWRGD_R

BUF_CPU_RST#

SM_DRAMPWROK

UNCOREPWRGOOD

Sandy Bridge CPU

RSTIN#

SVID

3

PM_SLP_S4#

4

PM_SLP_S3#

SVID

8

-6

DCBATOUT5V_S5

VDDP VIN

EN

TPS51116RGER

Page46

5V_S5 3D3V_S5

VDD VIN

TPS53311RGTR

EN

Page47

VOUT

REF

VTT

PGD

VOUT

PGD

1D5V_S3

DDR_VREF_S3

0D75V_S0

RUNPWROK

5

1D8V_S0

RUNPWROK

5

B B

5

RUNPWROK

5a

1.05VTT_PWRGD

8

A A

6

D85V_PWRGD

SVID

7

IMVP_VR_ON

5

V5IN VIN

TPS51218DSCR

EN

Page45

DCBATOUT

5V_S5

VIN

VDDP

RT8208BGQW

EN

Page48

DCBATOUT

VIN

VR

OUTPUT

SVID

ISL95831HRTZ

VR_ON

Page42 & 43 & 44

PGOOD

VOUT

PGOOD

VOUT

PGOOD

1D05_VTT

1.05VTT_PWRGD

5a

0D85_S0

D85V_PWRGD

6

VCC_CORE

VCC_GFXCORE

IMVP_PWRGD

Y

10

SYS_PWROK

-7

RTC_AUX_S5

-5

3D3V_AUX_S5

-8

+RTC_VCC

RTC battery

Power Up Sequence: -8 ~ 13

3

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A2

Date: Sheet of

Wednesday, April 13, 2011

Date: Sheet of

Wednesday, April 13, 2011

Date: Sheet of

2

Wednesday, April 13, 2011

Taipei Hsien 221, Taiwan, R.O.C.

Power Sequence Diagram

Enrico Caruso 14

1

99

A00

105

S0_PWR_GOOD

IMVP_PWRGD

AND GATE

A

B

9

4

5

4

3

2

1

Adapter

D D

AO4407A

DCBATOUT

TPS51218DSCR

TPS51216RUKR

RT8208BGQW

Charger

1D05V_VTT

0D75V_S01D5V_S3

VGA_CORE

Battery

BQ24707

+PBATT

APL5916

0D85V_S0

C C

RT9035 TPCA8062

1V_VGA_S0

1D5V_S0

TPS51125ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5 5V_S5

G547F2P81

AO4468

3D3V_S5

VT1317VT1316+VT1317

AO4468

TPS51311

AO3403

5V_USB2_S0

B B

5V_S0

VCC_CORE

VCC_GFXCORE

3D3V_S0

1D8V_S0

3D3V_LAN_S5

AO4468

ODD_PWR_5V

G5285T11

LCDVDD

A A

Power Shape

RTS5138

3D3V_CARD_S0

Regulator LDO Switch

5

4

3

2

DMP2130L

1D8V_VGA_S0

3D3V_VGA_S0

DN15ATI Whistler

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size Document Number Rev

A3

Date: Sheet of

Power Block Diagram

Enrico Caruso 14

Taipei Hsien 221, Taiwan, R.O.C.

1

A00

100 105Wednesday, April 13, 2011

A00

Dell 14 N4050 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual