The VNN3NV04, VNS3NV04, VND3NV04
VND3NV04-1, are mon ol ithi c devic es desi g ned in
STMicroelectronics VIPower M0-3 Technology,
BLOCK DIAGRAM
2
3
2
1
SOT-223
3
1
TO252 (DPAK)
ORDER CODES:
SOT-223
SO-8
TO-252 (DPAK)
TO-251 (IPAK)
SO-8
1
TO251 (IPAK)
VNN3NV04
VNS3NV04
VND3NV04
VND3NV04-1
3
2
intended for replacement of standard Power
MOSFETS from DC up to 50KHz applications.
Built in thermal shutdown, l inear curren t limitation
and overvoltage clamp protect the chip in harsh
environments.
Fault feedback can be de tected by mon itori ng the
voltage at the input pin.
DRAIN
2
INPUT
1
Februa ry 20031/21
Gate
Control
Over
Temperature
Overvoltage
Clamp
Linear
Current
Limiter
3
SOURCE
FC01000
Page 2
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
ABSOLUTE MAXIMUM RATI NG
SymbolParameter
Drain-source Voltage (VIN=0V)Intern ally Clam p edV
Input VoltageInternally ClampedV
IN
Input Current +/-20mA
Minimum I nput Series Impedance220Ω
Drain Current Internally LimitedA
Reverse DC Output Current -5.5A
Electros tatic Discharge (R=1.5KΩ, C=100pF)4000V
Electros tatic Discharge on output pin only
(R=330Ω, C=150pF)
Total Dissipation at Tc=25°C78.335W
(*) Pulsed: Pu ls e duration = 300µs, duty c y c le 1.5%
Drain Current LimitVIN=5V; VDS=13V 3.557A
=5V; VDS=13V
Step Response Current
Limit
Overtemperature
jsh
Shutdown
Overtemperature Reset135°C
jrs
Fault Sink CurrentVIN=5V; VDS=13V; Tj=T
gf
Sing l e Pu lse
as
Avala nche Energy
V
IN
starti ng T
V
IN
=25°C; VDD=24V
j
=5V R
gen=RIN MIN
(see figures 3 & 4)
jsh
=220Ω; L=24mH
10µs
150175200°C
101520mA
100mJ
4/21
2
Page 5
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC up
to 50KHz. The only difference from the user’s
standpoint is that a small DC current I
100µA) flows into the INPUT pin in order to supply
ISS
(typ.
the internal circuitry.
The de vice integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics o f the Power MOSFET
stage giv e this device unrivall ed ruggedne ss and
energy handl ing capability. This feat ure is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current ID to I
INPUT pin voltages. When the current limiter is
whatever the
lim
active, the device operates in the linear region, so
power dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip t emperatur e
and are not dependen t on the input voltage. The
location o f t he s ensing el emen t on the c h ip i n t he
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs in the range 150 to 190 °C, a typical
value being 170 °C. The device is auto matically
restarted when the chip temp eratu re fall s of about
15°C below shut-down temperature.
- STATUS FEEDBACK:
in the case of an overtem perature fault cond ition
(Tj > T
current Igf through the INPUT pin in order to
), the device tries to sink a diagnostic
jsh
indicate fault condition. If driven from a low
impedance source, this current may be used in
order to warn the control circuit of a device
shutdown. If the drive imped ance is high enough
so that the INPUT p in dri ver is no t abl e to su pply
the current Igf, the INPUT pin will fall to 0V. This
will not however affect the device operation:
no requirement is put on the current capability
of the INPUT pin driver except to be able to
supply the normal operation drive current I
ISS
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
.
5/21
Page 6
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Fig.1: Switching Time Test Circuit for Resistive Load
V
gen
I
D
90%
V
D
R
gen
t
r
t
V
gen
d(on)t
Fig.2: Test Circuit for Diode Recovery Times
A
D
I
OMNIFET
S
220Ω
B
10%
R
gen
FAST
DIODE
d(off)
I
t
f
A
B
OMNIFET
L=100uH
D
t
t
V
DD
6/21
1
V
gen
S
8.5 Ω
Page 7
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Thermal Impedance for DPAK/IPAKThermal Impedance for SOT-223
7/21
Page 8
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Fig. 3: Unclamped Inductive Load Test Circuits
R
V
IN
P
GEN
W
Fig. 5: Input Ch arge Test Circuit
IN
V
GEN
Fig. 4: Unclamped Inductive Waveforms
8/21
ND8003
Page 9
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Source-Drain Diode Forward Characteristics
Vsd (mV)
1100
1050
1000
950
900
850
800
750
700
650
600
Vin=0V
0123456789101112
Id (A)
Derating Curve
Voltage
Rds(on) (mohms)
250
225
200
175
150
125
100
75
50
25
0
33.544.555.566.5
Vin(V)
Id=1.5A
Tj=150ºC
Tj=25ºC
Tj=-40ºC
Static Drain Source On Resistance
Rds(on) (mo h ms )
1000
900
800
700
600
500
400
300
200
100
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
Tj=-40ºC
Vin=2.5V
Tj=25ºC
Tj=150ºC
Id(A)
Static Drain-Source On resistance Vs. Input
Voltage
Rds(on) (mohms)
300
275
250
225
Tj=150ºC
200
175
150
Tj=25ºC
125
100
Tj=-40ºC
75
50
25
0
33.544.555.566.5
Id=3.5A
Id=1A
Id=3.5A
Id=1A
Id=3.5A
Id=1A
Vin(V)
TransconductanceStatic Drain-Source On resistance Vs. Input
Gfs (S)
11
10
Vds=13V
9
8
7
6
5
4
3
2
1
0
00.511.522.533.544.555.5
Id (A)
Tj=-40ºC
Tj=25ºC
Tj=150ºC
9/21
Page 10
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Static Drain-Source On Resistance Vs. Id
Rds(on) (mo h ms )
250
225
200
175
150
125
100
75
50
25
0
Vin=5V
Tj=150ºC
Tj=25ºC
Tj= - 40ºC
00.511.522.533.54
Id (A)
Turn On Current Slope
di/dt(A/us)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
500
250
750
1000
1250
Rg(ohm)
1500
Vdd=15V
1750
Vin=5V
Id=1.5A
2000
2250
2500
Transfer Characteristics
Idon (A)
6
5.5
4.5
3.5
2.5
1.5
0.5
Vds=13.5V
5
4
3
2
1
0
1.522.533.544.555.56
Tj=150ºC
Tj=-40ºC
Tj=25ºC
Vin (V)
Turn On Current Slope
di/dt(A/usec)
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0 250 500 750 1000 1250 1500 1750 2000 2250 2500
Rg(ohm)
Vin=3.5V
Vdd=15V
Id=1.5A
Input Voltage Vs. Input Charge
Vin (V)
9
8
Vds=1V
Id=1.5A
7
6
5
4
3
2
1
0
01234567891011
Qg (nC)
10/21
Turn off drain source voltage slope
dv/dt(V/usec)
300
275
250
225
200
175
150
125
100
75
50
25
0
0
500
250
750
1000
1250
Rg(ohm)
1500
1750
Vin=5V
Vdd=15V
Id=1.5A
2000
2250
2500
Page 11
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Turn Off Drain-Source Voltage Slope
dv/dt(V/usec)
300
275
250
225
200
175
150
125
100
75
50
25
0
0
500
250
750
1000
1250
1500
Vin=3.5V
Vdd=15V
Id=1.5A
1750
Rg(ohm)
Switching Time Resistive Load
t(usec)
4
3.5
2.5
1.5
0.5
Vdd=15V
3
Id=1.5A
Vin=5V
2
1
0
0
500
250
750
1000
1250
1500
1750
td(off)
2000
Rg(ohm)
Output Characteristics
2000
tr
tf
td(on)
2250
2250
2500
2500
Capacitance Variations
C(pF)
350
300
250
200
150
100
50
05101520253035
f=1MHz
Vin=0V
Vds(V)
Switching Time Resistive Load
t(nsec)
900
800
700
600
500
400
300
200
100
0
3.253.53.7544.254.54.7555.25
td(off)
tf
td(on)
tr
Vdd=15V
Id=1.5A
Rg=220ohm
Vin(V)
Normalized On Resistance Vs. Temperature
Id (A)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
012345678910
Vin=5V
Vin=4V
Vin=3V
Vds (V)
Rds(on) (mOhm)
4
3.5
3
2.5
2
1.5
1
0.5
Vin=5V
Id=1.5A
-50 -250255075100 125 150 175
Tc )ºC)
11/21
Page 12
VNN3NV04 / VNS3NV04 / VND3NV04 / VND3NV04-1
Normalized Input Threshold Voltage Vs.
Temperature
Information furnish ed is believed to be accurate and r eliable. However, STMicroel ec tronics ass um es no responsibility for t he consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under a ny patent or patent rights of STMicroelect r onics. Specif ic ations mentioned in this publication are
subject to c hange without notice. T his publication supersedes and rep lac es all inform ation previously supplied. STMicroelect r onics produc ts
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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