Datasheet VP1550NW Datasheet (Supertex)

Page 1
Ordering Information
BV
/R
DSS
BV
DGS
-500V 125Ω -100mA VP1550NW
* Die in wafer form.
DS(ON)
(max) (min) Die*
P-Channel Enhancement-Mode Vertical DMOS FETs
I
D(ON)
Order Number / Package
VP1550
Features
❏ Free from secondary breakdown ❏ Low power drive requirement ❏ Ease of paralleling ❏ Low C ❏ Excellent thermal stability ❏ Integral Source-Drain diode ❏ High input impedance and high gain ❏ Complementary N- and P-channel devices
and fast switching speeds
ISS
Applications
❏ Motor controls ❏ Converters ❏ Amplifiers ❏ Switches ❏ Power supply circuits ❏ Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Advanced DMOS Technology
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Absolute Maximum Ratings
Drain-to-Source Voltage BV
Drain-to-Gate Voltage BV
Gate-to-Source Voltage ± 20V
Operating and Storage Temperature -55°C to +150°C
Soldering Temperature* 300°C *
Distance of 1.6 mm from case for 10 seconds.
01/14/02
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
DSS
DGS
1
Page 2
VP1550
Electrical Characteristics
(@ 25°C unless otherwise specified)
Symbol Parameter Min Typ Max Unit Conditions
BV
V ∆V I
GSS
I
DSS
DSS
GS(th)
GS(th)
Drain-to-Source Breakdown Voltage
-500
Gate Threshold Voltage -2.0 -4.5 V VGS = VDS, ID = -1mA Change in V
with Temperature 3.5 6 mV/°CVGS = VDS, ID = -1mA
GS(th)
Gate Body Leakage -100 nA VGS = ±20V, VDS = 0V Zero Gate Voltage Drain Current -10 VGS = 0V, VDS = Max Rating
-1000
I
D(ON)
ON-State Drain Current -90 VGS = -5V, VDS = -25V
-100 -240 V
R
DS(ON)
∆R
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
Notes:
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Static Drain-to-Source ON-State Resistance
Change in R
with Temperature 0.85 %/°CVGS = -10V, ID = -10mA
DS(ON)
Forward Transconductance 25 40 m VDS = -25V, ID = -10mA Input Capacitance 40 70 Common Source Output Capacitance 10 20 pF Reverse Transfer Capacitance 3 10 Turn-ON Delay Time 5 10 Rise Time 8 10 Turn-OFF Delay Time 8 15 Fall Time 5 16 Diode Forward Voltage Drop -0.8 -1.5 V VGS = 0V, ISD = -0.1A Reverse Recovery Time 200 ns VGS = 0V, ISD = -0.1A
85 VGS = -5V, ID = -5mA 80 125 V
VV
µAV
= 0V, ID = -1mA
GS
= 0V, VDS = 0.8 Max Rating
GS
= 125°C
T
A
mA
= -10V, VDS = -25V
GS
Ω
= -10V, ID = -10mA
GS
Ω
V
= 0V, VDS = -25V
GS
f = 1 MHz
VDD = -25V
ns ID = -100mA
= 25Ω
R
GEN
Switching Waveforms and Test Circuit
0V
INPUT
-10V
0V
OUTPUT
V
DD
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
10%
t
d(ON)
t
(ON)
t
r
10%
90%
90%
t
d(OFF)
t
(OFF)
90%
10%
t
F
2
PULSE
GENERATOR
R
gen
INPUT
D.U.T.
OUTPUT
R
L
V
DD
11/12/01
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
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