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VP0300
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
Note: See Package Outline section for dimensions.
P-Channel Enhancement-Mode
Vertical DMOS FETs
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage BV
DSS
Drain-to-Gate Voltage BV
DGS
Gate-to-Source Voltage ± 20V
Operating and Storage Temperature -55°C to +150°C
Soldering Temperature* 300°C
*
Distance of 1.6 mm from case for 10 seconds.
Applications
■■ Motor controls
■■ Converters
■■ Amplifiers
■■ Switches
■■ Power supply circuits
■■ Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Features
■■ Free from secondary breakdown
■■ Low power drive requirement
■■ Ease of paralleling
■■ Low C
ISS
and fast switching speeds
■■ Excellent thermal stability
■■ Integral Source-Drain diode
■■ High input impedance and high gain
■■ Complementary N- and P-channel devices
BV
DSS
/R
DS(ON)
I
D(ON)
BV
DGS
(max) (min) TO-92
-30V 2.5Ω -1.5A VP0300L
Order Number / Package
Ordering Information
TO-92
S G D
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90%
10%
90%
90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
0V
V
DD
R
gen
0V
-10V
VP0300
Thermal Characteristics
Package ID (continuous)* ID (pulsed) Power Dissipation
θ
ja
θ
jc
TC = 25°C °C/W °C/W
TO-92 -0.32A -0.87A 1.0W 170 125
*
ID (continuous) is limited by max rated Tj.
Electrical Characteristics (@ 25°C unless otherwise specified)
Symbol Parameter Min Typ Max Unit Conditions
BV
DSS
Drain-to-Source Breakdown Voltage -30 V VGS= 0V, ID =-10µA
V
GS(th)
Gate Threshold Voltage -1.0 -1.8 -4.5 V VGS = VDS, ID = -1mA
I
GSS
Gate Body Leakage -100 nA VGS = ±30V, VDS = 0V
I
DSS
Zero Gate Voltage Drain Current -10 VGS = 0V, VDS = -25V
-500 µAVGS = 0V, VDS = -25V
TA = 125°C
I
D(ON)
ON-State Drain Current -1.5 -1.7 A VGS = -12V, VDS = -10V
R
DS(ON)
Static Drain-to-SourceON-State Resistance 2.5 Ω VGS = -12V, ID = -1A
G
FS
Forward Transconductance 200 m VDS = -10V, ID = -0.5A
C
ISS
Input Capacitance 150
C
OSS
Common Source Output Capacitance 120 pF
C
RSS
Reverse Transfer Capacitance 60
t
(ON)
Turn-ON Time 30 ns
t
(OFF)
Turn-OFF Time 30
V
SD
Diode Forward Voltage Drop -1.2 V VGS = 0V, ISD = -1.5A
Notes
1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
VGS = 0V, VDS = -15V
f = 1MHz
V
DD
= -25V, ID = -1A
R
GEN
= 25Ω
Switching Waveforms and Test Circuit
Ω
– OBSOLETE –
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