Datasheet UAA3500HL Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UAA3500HL

Pager receiver

Objective specification
File under Integrated Circuits, IC17

1999 Mar 30

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

FEATURES

• Double frequency conversion, zero-IF receiver with:
– Configurable in all paging bands (130 to 930 MHz)
– Low noise amplifier featured with four step Automatic

Gain Control (AGC)
– Down-conversion mixers
– On-chip, zero-IF channel filter
– I/Q, non-demodulated outputs
– Highpass filters to remove DC offsets.

• External Voltage Controlled Oscillator (VCO).
– Both LOs derived from the VCO.

APPLICATIONS

• FLEX, ERMES and POCSAG pagers

• Remote control terminals.

GENERAL DESCRIPTION

The UAA3500HL is a one-chip pager receiver complying
with POCSAG, FLEX and ERMES standards.
The IC performs in accordance with specifications in the

−10 to +55 °C temperature range.

The UAA3500HL contains a front-end receiver
configurable, through external components, for any
frequency band between 130 and 930 MHz. The back-end
receiver consists of the channel filter and limiters.
An external VCO ensures the Local Oscillator (LO) for the
front-end. Designed in an advanced BiCMOS process, it
combines high performance with low-power consumption
and a high degree of integration, thus reducing external
component costs and total radio size.

Its first advantage is to remove the expensive SAW filter
necessary in a superhet architecture and to replace it by
an integrated, elliptic channel filter that provides 70 dB
adjacent channel rejection. The receive front-end section
consists of a low-noise amplifier that drives mixers through
an external LC image rejection filter. The output drives the
I and Q second mixers, whose outputs are at zero
frequency. The receiver back-end section consists of
filters (channel filtering), limiters (limited output required)
and high-pass filters (DC-block) to remove DC offsets.
Outputs are I and Q, undemodulated signals.

Its second advantage is to provide the two LO signals only
from one VCO tuned by a PLL. On-chip frequency
divider-by-2 and buffers provide the LO sources.

Its third advantage is to provide two voltage regulators,
allowing to obtain 1.0 and 1.8 V regulated voltages.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UAA3500HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

PACKAGE

1999 Mar 30 2

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS

V

CC1

V

CC2

I

CC1(RX)

supply voltage 1 (B++) 1.85 2.1 3.3 V
supply voltage 2 (B+) 1.05 1.4 1.5 V
receive supply current from B++ 160 MHz − 2.4 − mA

(1)

MIN. TYP. MAX. UNIT

280 MHz − 2.4 − mA
930 MHz − 2.5 − mA

I

CC2(RX)

receive supply current from B+ 160 MHz − 1.3 − mA

280 MHz − 1.4 − mA
930 MHz − 2.3 − mA

NF

RX

receiver noise figure 160 MHz − 2.7 − dB

280 MHz − 3.1 − dB
930 MHz − 4.4 − dB

Sens sensitivity; 3% BER and 1600 bits/s

2 level

160 MHz −−128.5 − dBm
280 MHz −−128 − dBm

930 MHz; note 2 −−126.5 − dBm
ACR adjacent channel rejection 65 70 − dB
T

amb

operating ambient temperature −10 +25 +55 °C

Notes

1. For 930 MHz band; for other conditions see Chapters “DC characteristics” and “AC characteristics”.

2. Sensitivity; 3% BER and 6400 bits/s 4 level: −123 dBm.

1999 Mar 30 3

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1999 Mar 30 4

V

CC(DC

)

DRV2

)
V

CC(LO

CAPI1A

)

FASTON

RXON

M1GND

M2GND

IMINA

IMOUTA

IMINB

IMOUTB

FILINA

FILOUTA

FILINB

FILOUTB

V

DRV1

CC(FE

andbook, full pagewidth

CAPI1B

CAPI2A

CAPI2B

BLOCK DIAGRAM

Pager receiver UAA3500HL

Philips Semiconductors Objective specification

RSET

LNAGND2

RFINA
RFINB

LNAGND1

LOIN

4037

33
32

LNA

31
30

29

BUFFER

21

2

22 14 13 20 19 10 9 48

LOGND

42 41 46 47 16 17 18 25 24 28 23 43 44 3 4

39383635

VOLTAGE

REGULATOR

PMA

BIAS

×

×

GYRATOR

REGULATOR

×

BUFFER

0

90

BUFFER

PMA

GYRCO1

GYRCO2

UAA3500HL

CAPQ1B

LIMITER

LIMITER

CAPQ2ACAPQ1A

CAPQ2B

BUFFER

BUFFER

LIMITER

AGC

LIMITER

BEGND

RSSI

OUTPUT

OUTPUT

45

5

2
1

6

26

34

27

7

11
12

8

15

GYROUTI
V

CC(O)

CAPI3A
CAPI3B

OUTI

AGCADJ

RSSI

AGCTAU

OUTQ

CAPQ3A
CAPQ3B

OGND
GYROUTQ

FCA022

Fig.1 Block diagram.

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

PINNING

SYMBOL PIN DESCRIPTION

CAPI3B 1 3rd DC filter (I path) external capacitor B (I path)
CAPI3A 2 3rd DC filter (I path) external capacitor A (I path)
CAPI2A 3 2nd DC filter (I path) external capacitor A (I path)
CAPI2B 4 2nd DC filter (I path) external capacitor A (I path)
V

CC(O)

OUTI 6 output I and Q signals (I path)
OUTQ 7 output I and Q signals (Q path)
OGND 8 output stage ground
CAPQ2B 9 2nd DC filter external capacitor B (Q path)
CAPQ2A 10 2nd DC filter external capacitor A (Q path)
CAPQ3A 11 3rd DC filter external capacitor A (Q path)
CAPQ3B 12 3rd DC filter external capacitor B (Q path)
GYRCO2 13 external resistor to set-up gyrator filter cut-off frequency
GYRCO1 14 external resistor to set-up gyrator filter cut-off frequency
GYROUTQ 15 Q-gyrator output
DRV1 16 regulator driver (1.8 V)
V

CC(FE)

V

CC(DC)

CAPQ1B 19 1st DC filter external capacitor (Q path)
CAPQ1A 20 1st DC filter external capacitor (Q path)
LOIN 21 LO input
LOGND 22 LO strip ground
FASTON 23 fast mode enable
V

CC(LO)

DRV2 25 regulator driver (1.0)
AGCADJ 26 AGC loop gain control
AGCTAU 27 AGC loop time constant
RXON 28 receiver mode enable
LNAGND1 29 receiver LNA ground 1
RFINB 30 LNA input B
RFINA 31 LNA input A
LNAGND2 32 receiver LNA ground 2
RSET 33 LNA current setup
RSSI 34 received signal strength indicator
IMINA 35 image rejection filter input A
IMINB 36 image rejection filter input B
M1GND 37 first mixer ground
IMOUTA 38 image rejection filter output A
IMOUTB 39 image rejection filter output B
M2GND 40 second mixers ground

5 output stage supply voltage B (I path)

17 regulated voltage for front-end (1.8 V)
18 input voltage from DC-to-DC converter (2.1 V)

24 regulated voltage for LO strip (1.0 V)

1999 Mar 30 5

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

SYMBOL PIN DESCRIPTION

FILINB 41 band filter input B
FILINA 42 band filter input A
CAPI1A 43 1st DC filter external capacitor (I path)
CAPI1B 44 1st DC filter external capacitor (I path)
GYROUTI 45 I-gyrator output
FILOUTA 46 band filter output to second mixers
FILOUTB 47 band filter output to second mixers
BEGND 48 receiver back-end ground

handbook, full pagewidth

CAPI3B
CAPI3A
CAPI2A
CAPI2B

V

CC(O)

OUTI

OUTQ

OGND
CAPQ2B
CAPQ2A
CAPQ3A
CAPQ3B

BEGND

FILOUTB

FILOUTA

GYROUTI

CAPI1B

CAPI1A

FILINA

FILINB

48

47

46

45

44

43

42

41

1
2
3
4
5
6
7
8

9
10
11
12

13

14

15

GYRCO2

GYRCO1

GYROUTQ

UAA3500HL

16

17

DRV1

CC(FE)

V

18

CC(DC)

V

19

20

CAPQ1B

CAPQ1A

IMOUTB

M2GND
40

39

21

22

LOIN

LOGND

IMOUTA

M1GND

38

37

23

24

CC(LO)

FASTON

V

36
35
34
33
32
31
30
29
28
27
26
25

FCA023

IMINB
IMINA
RSSI
RSET
LNAGND2
RFINA
RFINB
LNAGND1
RXON
AGCTAU
AGCADJ
DRV2

Fig.2 Pin configuration.

1999 Mar 30 6

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

FUNCTIONAL DESCRIPTION
Receiver front-end section

The receiver front-end consists of an LNA, followed by the
first and the second mixers. For operation at low frequency
(160 and 280 MHz for instance), the first mixer can be
bypassed saving some current. The image rejection is
made by an external LC filter placed between the LNA, the
first mixer and the antenna selectivity. The IF band filtering
is made by an external filter placed between the first mixer
and the second ones. There are two second mixers for the
two paths I and Q. The RF signals are in phase, and the
LO signals are 90° shifted. The output signals are at zero
frequency.

To increase the immunity to interferers an AGC loop
controls the LNA gain by attenuating the RF input signal.
Four steps of attenuation are possible (each having 8 dB),
ranging therefore from 0 to 32 dB. The AGC loop
threshold level and time constant may be controlled
externally at pins AGCADJ and AGCTAU. The 2nd
LO I/Q phase shift is made by a quadrature divider, whose
input is the VCO oscillating signal.

The LNA current is setup by an external resistor. All the
receivers (front-end and back-end) are turned on by the
pin RXON.

Receiver back-end section

The down-converted signal is amplified and then filtered
by a Sallen-Key filter, that shows a notch at 15 kHz and
about 6 dB rejection out-of-band. Then comes the first
high-pass filter (DC-block), followed by the gyrator filter. It
performs an elliptic, 7 poles low-pass filtering. The signal
is then amplified by the first limiter, then filtered by the
second DC-block, again amplified, and again filtered by
the third DC-block. Finally an output stage delivers the
signal with rail-to-rail logic levels.

The first, second and third DC-block frequency are set at
4, 8 and 12 Hz respectively by external 330 nF capacitors.

The two voltage regulators are also activated by RXON.
At the output of the gyrator filter the signal is buffered and

logarithmically converted. It controls then the AGC loop.
To rapidly reach the DC operating point a fast mode is built

in the 3 DC-blocks.

LO

The external VCO is AC-coupled at input LOIN. It is then
buffered to drive the first mixer. LOIN also enters a
quadrature divider-by-2, whose output signals are also
buffered to drive the second mixers. The VCO frequency

2

should be

⁄3of that of the input RF signal.

The VCO synthesizer is integrated in the baseband
controller chip, but an external synthesizer can also be
used.

OPERATING MODES

To use the IC, all V

pins must be connected to the

CC

supply voltage B++ (2.1 V). The 1.8 V regulated voltage
sinks current from B++ and the 1.0 V regulated voltage
from B+ (1.4 V). In a typical application, the B+ supply is
the battery and the B++ supply is the DC/DC converter
located in the baseband chip.

In normal operating mode the receiver should be
powered-on in fast mode. The fast mode can be turned off
after several milliseconds.

Table 1 gives the definition of the polarity of the switching
signals on the receive section.

Table 1 Switching signals on the receiver

SIGNAL SECTION LEVEL ON/OFF

RXON receive section powered-on HIGH on

receive section powered-off LOW off

FASTON fast mode powered-on HIGH on

fast mode powered-off LOW off

1999 Mar 30 7

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

∆GND difference in ground supply voltage applied

P

l(max)

T

j(max)

P

(max)

T

stg

Note

1. Pins short-circuited internally must be short-circuited externally.

THERMAL CHARACTERISTICS

supply voltage − 6V

note 1 − 0.3 V

between all grounds
maximum power input − 20 dBm
maximum operating junction temperature − 150 °C
maximum power dissipation in stagnant air

− 500 mW

at 25 °C

storage temperature −65 +150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 90 K/W

HANDLING

Every pin withstands the ESD test in accordance with

“MIL-STD-883C class 2 (method 3015.5)”

.

DC CHARACTERISTICS

V

CC

= 2.1 V; T

=25°C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Pins: V

V

CC1

, 2 V1, 1 V0, 1 V0DRV, 1 V8, and 1 V8DRV

CC(O)

supply voltage 1 (B++) over full temperature

1.85 2.1 3.3 V

range

V

CC2

supply voltage 2 (B+) over full temperature

1.05 1.4 1.5 V

range

I

CC1(RX)

supply current from B++ RX section on; DC tested

160 MHz − 2.4 − mA
280 MHz − 2.4 − mA
930 MHz − 2.5 − mA

I

CC2(RX)

supply current from B+ RX section on; DC tested

160 MHz − 1.3 − mA
280 MHz − 1.4 − mA
930 MHz − 2.3 − mA

I

CC1(pd)

standby current from B++ Power-down mode;

0 0.5 1 µA

DC tested

I

CC2(pd)

standby current from B+ Power-down mode;

0 0.1 0.5 µA

DC tested

1999 Mar 30 8

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Pins: RXON, FASTON, OUTI and OUTQ

V

IH

V

IL

I

IH

I

IL

HIGH-level voltage VCC− 0.3 V

CC

LOW-level voltage −0.3 − +0.4 V
HIGH-level static current VCC− 0.4 V −1 − +1 µA
LOW-level static current pin at 0.4 V −1 − +1 µA

Pins: CAPI1A, CAPI1B, CAPQ1A and CAPQ1B

V

CAP

DC level RX section on − 1.40 − V

Pins: CAPI2A, CAPI2B, CAPQ2A, CAPQ2B, CAPI3A, CAPI3B, CAPQ3A and CAPQ3B

V

CAP

DC level RX section on − 1.57 − V

Pins: RFINA and RFINB

V

RF

DC level RX section on − 0.92 − V

Pins: IMOUTA and IMOUTB

V

IMOUT

DC level RX section on − 0.17 − V

Pins: FILINA and FILINB

V

FILIN

DC level RX section on − 1 − V

Pins: FILOUTA and FILOUTB

V

FILOUT

DC level RX section on − 0.24 − V

Pins: GYROUTI and GYROUTQ

V

GYROUT

DC level RX section on − 1.42 − V

Output stage

V

OH

V

OL

HIGH-level output voltage Io= −5 µA − VCC− 0.2 − V
LOW-level output voltage Io=5µA − 0.2 − V

VCC+ 0.3 V

1999 Mar 30 9

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

AC CHARACTERISTICS

V

= 2.1 V; T

CC

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Receiver

G

CP

NF

RX

IP1 1 dB input compression point from RF input to 2nd mixer input −−38 − dBm
IP2 2nd order intercept point from 2nd mixer input to gyrator

IP3 3rd order intercept point from RF input to 2nd mixer input;

CCR co-channel rejection threshold +3 dB − 5 − dB

ACR adjacent channel rejection channel spacing = 25 kHz; from

Blocking blocking immunity frequency offset >1 MHz 75 80 − dB
G

AGC

AGC

th

t

turnon

∆IQ IQ channel unbalance −−2dB
R

LNA

R

gyr

=25°C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; unless otherwise specified.

amb

front-end conversion power gain from RF input to 2nd mixer input

160 MHz − 20 − dB
280 MHz − 12.8 − dB
930 MHz − 12.7 − dB

receiver noise figure from RF input to 2nd mixer input

160 MHz − 2.7 − dB
280 MHz − 3.1 − dB
930 MHz − 4.4 − dB

45 −−dBm

output

−−33 − dBm

note 1

65 70 − dB

RF input to gyrator output

front-end gain reduction by AGC

− 8 − dB

step
AGC threshold above sensitivity 20 25 30 dB
establishment time until sensitivity +3 dB is reached −−30 ms

LNA current set resistor 160 MHz − 56 − kΩ

280 MHz − 47 − kΩ
930 MHz − 27 − kΩ

gyrator cut-off frequency set

cut-off frequency=8kHz − 47 − kΩ

resistor

LO

f

VCO

VCO frequency −

1999 Mar 30 10

2

⁄3RF − Hz

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LNA

G

NF

IP1

IP3

LNA

LNA

LNA

LNA

RF amplifier power gain from RF input to image filter

output

160 MHz − 20 − dB
280 MHz − 16.2 − dB
930 MHz − 14.9 − dB

RF amplifier noise figure from RF input to image filter

output

160 MHz − 1.8 − dB
280 MHz − 1.9 − dB
930 MHz − 2.2 − dB

1 dB input compression point from RF input to image filter

output

3rd order intercept point from RF input to image filter

output

−−27 − dBm

−−17.6 − dBm

First mixer

G
NF
IP1
IP3

FM

FM

FM
FM

1st mixer power gain − 2.2 − dB
1st mixer noise figure − 10.2 − dB
1 dB input compression point −−22 − dBm
3rd order intercept point −−14 − dBm

Second mixer + PMA + Sallen-Key + 1st DC block + gyrator filter

G power gain from 2nd mixer input to gyrator

− 10.4 − dB

output

IM3 3rd order intermodulation from 2nd mixer input to gyrator

55 −−dB

output

1st DC block

f

cut-off

cut-off frequency measured at gyrator output − 4 − Hz

Note

1. The two tones for intermodulation test would normally be set at 2 and 4 or 4 and 8 channels for type approval tests
i.e 930 and 930.1 or 930.1 and 930.2 MHz.

1999 Mar 30 11

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

APPLICATION INFORMATION

handbook, full pagewidth

BAND

FILTER

GYROUTI

330 nF

IMAGE

FILTER

330 nF

330 nF

B++

OUTI

OUTQ

330 nF

330 nF

1
2
3
4
5
6
7
8

9
10
11
12

48 47

13

47 kΩ

46

14

15

GYROUTQ

10 nF

100 kΩ

45 44

16

43

UAA3500HL

17

1918

B++

100 pF

10 µF

42

330 nF

41 40

20

VCO

3839

232221

FASTON

37

36
35
34
33
32

31
30

29
28
27
26
25

24

R

100 pF

LNA

RSSI

RXON

10 µF

10 nF

B+

100

kΩ

RFIN

15
kΩ

B++

Electrical diagram of the UAA3500HL demonstration board for FLEX applications. All matching is to 50 Ω for measurement purpose.
B+ =1.4 V; B++ = 2.1 V.

FCA024

Fig.3 Demonstration board diagram.

1999 Mar 30 12

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

pin 1 index

48

25

Z

24

E

e

A

H

E

E

A

2

A

w M

b

p

13

SOT313-2

(A )

A

1

L

3

θ

L

p

1

e

w M

b

p

D

H

D

12

Z

D

v M

B

v M

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

mm

A

A1A2A3bpcE

max.

0.20

1.60

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

(1)

(1) (1)(1)

D

7.1

6.9

eH

H

7.1

6.9

0.5

9.15

8.85

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT313-2

D

A

B

9.15

8.85

LL

E

0.75

0.45

p

detail X

0.12 0.10.21.0

EUROPEAN

PROJECTION

Z

0.95

0.55

D

Zywv θ

E

0.95

0.55

o

7

o

0

ISSUE DATE

94-12-19
97-08-01

1999 Mar 30 13

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Mar 30 14

Philips Semiconductors Objective specification

Pager receiver UAA3500HL

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Mar 30 15

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 465008/750/01/pp16 Date of release: 1999 Mar 30 Document order number: 9397750 05038