Product specification
Supersedes data of 1995 Nov 27
File under Integrated Circuits, IC03
1996 Jan 15
Page 2
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
FEATURES
• Wide frequency range: VHF, UHF and 900 MHz bands
• High sensitivity
• High dynamic range
• Electronically adjustable filters on chip
• Suitable for data rates up to 2400 bits/s
• Wide frequency offset and deviation range
• Fully POCSAG compatible FSK receiver
• Power on/off mode selectable by the chip enable input
• Low supply voltage; low power consumption
• 1-cell battery-low detection circuit
• High integration level
• Interfaces directly to the PCA5000A, PCF5001 and
PCD5003 POCSAG decoders.
APPLICATIONS
• Wide area paging
• On-site paging
• Telemetry
• RF security systems
• Low bit-rate wireless data links.
GENERAL DESCRIPTION
The UAA2082 is a high-performance low-power radio
receiver circuit primarily intended for VHF, UHF and
900 MHz pager receivers for wide area digital paging
systems, employing direct FM non-return-to-zero (NRZ)
frequency shift keying (FSK).
The receiver design is based on the direct conversion
principle where the input signal is mixed directly down to
the baseband by a local oscillator on the signal frequency.
Two complete signal paths with signals of 90° phase
difference are required to demodulate the signal.
All channel selectivity is provided by the built-in IF filters.
The circuit makes extensive use of on-chip capacitors to
minimize the number of external components.
The battery monitoring circuit has an external sense input
and a 1.1 V detection threshold for easy operation in a
single-cell supply concept.
The UAA2082 was designed to operate together with the
PCA5000A, PCF5001 or PCD5003 POCSAG decoders,
which contain a digital input filter for optimum call success
rate.
ORDERING INFORMATION
TYPE
NUMBER
UAA2082HLQFP32plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mmSOT358-1
UAA2082U28 padsnaked die; see Fig.8
(change in frequency between series resonance and resonance with 8 pF series capacitor at 25 °C), dynamic
resistance R1 < 40 Ω, ∆f=±5×10−6 for T
= −10 to +55 °C with 25 °C reference, calibration plus aging tolerance:
amb
−5 × 10−6to +15 × 10−6.
2. This crystal recommendation is based on economic aspects and practical experience. Normally the spreads for R1,
pullability and calibration do not show their worst case limits simultaneously in one crystal. In such a rare event, the
tuning range will be reduced to an insufficient level.
1996 Jan 156
Page 7
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
BLOCK AND TEST DIAGRAMS (470 MHz)
L5
40
R2
47
P
V
L6
820 Ω
1 nF
8 nH
C12
L7
8 nH
2.5 to 6 pF
25
24
R3
C19
kΩ
GND2
21
22
20
18
19
UAA2082H
MIXER Q
nH
C9
MLC224
2.7 pF
= 469.95 MHz.
L4
40
nH
C11
22 pF
bias(osc)
V
C20
1 nF
L8
R6
R5
C13
C14
100
22
1.5
C18
10 µF
1 nF
C15
1 nF
3 to
nH
kΩ
XTAL
C16
kΩ
10 pF
13 to
L9
50 pF
560
R4
1.2 kΩ
SENSE
C17
nH
GND3
15 pF
2627
28
303132
MULTIPLIER
FREQUENCY
LOW
BATTERY
CRYSTAL
OSCILLATOR
1TS
low noise
amplifier Q
ACTIVE
INDICATOR
GYRATOR
Q
LIMITER
FILTER
FILTER
2
BLI
DEMO-
DULATOR
3
4
DO
ACTIVE
GYRATOR
5
TPI
RE
low noise
amplifier I
FILTER
FILTER
I
LIMITER
6
TPQ
MIXER I
BAND GAP
REFERENCE
RF pre-amplifier
7
C3
2.5 to
ref
V
P
V
8
6 pF
1516
C8
C7
C10
22 pF
C6
C5 1 nF
1314
L3
8 nH
L2
GND1
330
8 nH
R1
Ω
12
11
10
2.7 pF
6 pF
2.5 to
C4 1 nF
2.7 pF
P
V
i(RF)
handbook, full pagewidth
Fig.3 Block, test and application diagram drawn for LQFP32; f
1996 Jan 157
to
decoder
C1
2.7 pF
IF testpoints
i(RF)
V
L1
nH
C2
12.5
2.7 pF
Pins 9, 17, 23 and 29 are not connected.
Page 8
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
bias(osc)
V
C20
1 nF
V
P
R5
C18
R3
C13
L8
R6
1.5 kΩ
1 nF
C 19
820 Ω
10 µF
C14
C15
100
22
1 nF
1 nF
3 to
nH
kΩ
C16
L6
L7
10 pF
XTAL
13 to
L9
R2
8 nH
8 nH
C17
50 pF
560 nH
DO
BLI
47 kΩ
C12
R 4
1.2 kΩ
SENSE
15 pF
TS
RE
decoder
16151718
2.5 to 6 pF
1920
21
222324
GND3
272625
28
MULTIPLIER
FREQUENCY
CRYSTAL
BAND GAP
BATTERY
OSCILLATOR
ref
V
V
REFERENCE
Q
amplifier
low noise
UAA2082U
LOW
INDICATOR
P
FILTER
ACTIVE
FILTER
GYRATOR
Q
LIMITER
DEMODULATOR
FILTER
ACTIVE
FILTER
GYRATOR
I
LIMITER
I
amplifier
low noise
RF pre-amplifier
MIXER IMIXER Q
GND2
L5
40
L4
40
nH
C9
10 11121314
89
7
6
54
12 3
22 pF22 pF
L2
L3
R1
330
C3
TPITPQ
C10 C11
C7
2.7 pF
C6
C5 1 nF
8 nH
8 nH
GND1
Ω
2.5 to 6 pF
IF testpoints
MLC225
nH
2.7 pF
C8
2.5 to 6 pF
C4 1 nF
C2
2.7 pF
L1
12.5 nH
C1
2.7 pF
2.7 pF
P
V
i(RF)
V
= 469.95 MHz.
i(RF)
handbook, full pagewidth
Fig.4 Block, test and application diagram drawn for naked die; f
1996 Jan 158
Page 9
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
L5
40
R2
47
P
V
L6
820 Ω
1 nF
8 nH
C12
L7
8 nH
2.5 to 6 pF
24
25
R3
C19
kΩ
GND2
21
22
20
18
19
UAA2082H
MIXER Q
nH
L4
40
nH
C11
22 pF
MLC226
C23
2.5 to 6 pF
L10
12.5 nH
bias(osc)
V
C20
1 nF
L8
R6
R5
C13
C14
100
22
1.5
C18
10 µF
1 nF
C15
1 nF
3 to
nH
kΩ
XTAL
C16
kΩ
10 pF
13 to
50 pF
L9
560
R4
1.2 kΩ
SENSE
C17
nH
GND3
15 pF
2627
28
303132
MULTIPLIER
FREQUENCY
LOW
BATTERY
CRYSTAL
OSCILLATOR
1TS
low noise
amplifier Q
ACTIVE
INDICATOR
GYRATOR
Q
LIMITER
FILTER
FILTER
2
BLI
DEMO-
DULATOR
3
DO
ACTIVE
GYRATOR
5
4
TPI
RE
low noise
FILTER
FILTER
I
LIMITER
6
TPQ
amplifier I
RF pre-amplifier
7
MIXER I
V
BAND GAP
REFERENCE
V
8
ref
P
1516
= 469.95 MHz.
5.6 pF
i(RF)
handbook, full pagewidth
P
C21
C5
C22
5.6 pF
1 nF
V
C10
22 pF
1314
12
1110
GND1
i(RF)
V
Fig.5 Mixer input sensitivity test circuit; f
1996 Jan 159
to
IF testpoints
decoder
Page 10
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
Table 2 Tolerances of components shown in Figs 3, 4 and 5 (notes 1 and 2)
(change in frequency between series resonance and resonance with 8 pF capacitor at 25 °C), dynamic resistance
R1 < 30 Ω, ∆f=±5×10−6 for T
= −10 to +55 °C with 25 °C reference, calibration plus aging tolerance:
amb
−5 × 10−6to +15 × 10−6.
2. This crystal recommendation is based on economic aspects and practical experience. Normally the spreads for R1,
pullability and calibration do not show their worst case limits simultaneously in one crystal. In such a rare event, the
tuning range will be reduced to an insufficient level.
1996 Jan 1510
Page 11
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
BLOCK AND TEST DIAGRAM (930 MHz)
L5
12.5
R2
47
P
V
L6
R3
330 Ω
3 nH
C12
3 nH
1.7 to 3 pF
25
L7
24
22
kΩ
GND2
21
20
18
19
nH
L4
nH
12.5
MLC227
C13
C14
L8
4.7 µF
150
pF
33 nH
C15
C19
150 pF
3.3 pF
i(OSC)
V
R4
390 Ω
SENSE
2627
28
303132
GND3
MULTIPLIER
FREQUENCY
LOW
BATTERY
CRYSTAL
OSCILLATOR
1TS
low noise
amplifier Q
ACTIVE
INDICATOR
GYRATOR
Q
LIMITER
FILTER
FILTER
2
DEMO-
DULATOR
3
4
MIXER Q
FILTER
ACTIVE
FILTER
GYRATOR
LIMITER
5
low noise
amplifier I
I
6
MIXER I
BAND GAP
REFERENCE
RF pre-amplifier
7
UAA2082H
L11
1516
L10
ref
V
C5
P
V
1314
L3
L2
12
11
GND1
10
120
8
5 nH
5 nH
150 pF
3.5 nH
3.5 nH
R1
Ω
C7
C6
C9
1.7 to
1.2 pF
1.5 pF
C8
1.5 pF
3 pF
C4 150 pF
P
V
= 930.50 MHz.
i(RF)
handbook, full pagewidth
Fig.6 Test circuit; f
RE
DO
BLI
to
decoder
1996 Jan 1511
TPI
TPQ
IF testpoints
C1
1.2 pF
i(RF)
V
C3
3 pF
1.7 to
5
L1
nH
C2
1.0 pF
Pins 9, 17, 23 and 29 are not connected.
Page 12
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
Table 3 Tolerances of components shown in Fig.6 (note 1)
lower left corner of chip (typical values)−278−186
Note
1. All x/y co-ordinates are referenced to the centre of pad 4 (VI2RF); see Fig.8.
1996 Jan 1515
Page 16
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
INTERNAL CIRCUITS
handbook, full pagewidth
1
2
3
4
1 kΩ1 kΩ
5
6
7
5 kΩ
5 kΩ
150 kΩ
32313028272625
n.c.
V
29
P
UAA2082H
V
P
24
V
P
23
n.c.
22
21
V
20
P
19
8
n.c.
150 Ω
9
121110
V
P
14
13
Fig.9 Internal circuits drawn for LQFP32.
1996 Jan 1516
18
17
1615
n.c.
MLC493
Page 17
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
MLC231
P
V
P
V
14
1312111098765432
UAA2082U
P
V
P
V
handbook, full pagewidth
150 Ω
Fig.10 Internal circuits drawn for naked die.
P
V
5
kΩ
2728262524232221201918171615
150
5
kΩ
kΩ
1
kΩ
1
1
kΩ
1996 Jan 1517
Page 18
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
FUNCTIONAL DESCRIPTION
The complete circuit consists of the following functional
blocks as shown in Figs 1 to 6.
Radio frequency amplifier
The RF amplifier is an emitter-coupled pair driving a
balanced cascode stage, which drives an external
balanced tuned circuit. Its bias current is set by an external
300 Ω resistor R1 to typically 770 µA. With this bias
current the optimum source resistance is 1.3 kΩ at VHF
and 1.0 kΩ at UHF. At 930 MHz a higher bias current is
required to achieve optimum gain. A value of 120 Ω is
used for R1, which corresponds with a bias current of
approximately 1.3 mA and an optimum source resistance
of approximately 600 Ω.The capacitors C1 and C2
transform a 50 Ωsource resistance to this optimum value.
The output drives a tuned circuit with capacitive divider
(C7, C8 and C9) to provide maximum power transfer to the
phase-splitting network and the mixers.
Mixers
The double balanced mixers consist of common base
input stages and upper switching stages driven from the
frequency multiplier. The 300 Ω input impedance of each
mixer acts together with external components (C10, C11;
L4, L5 respectively) as phase shifter/power splitter to
provide a differential phase shift of 90 degrees between
the I channel and the Q channel. At 930 MHz all external
phase shifter components are inductive (L10, L11; L4, L5).
The resonant circuit at output pin OSC selects the second
harmonic of the oscillator frequency. In other applications
a different multiplication factor may be chosen.
At 930 MHz an external oscillator circuit is required to
provide sufficient local oscillator signal for the frequency
multiplier.
Frequency multiplier
The frequency multiplier is an emitter-coupled pair driving
an external balanced tuned circuit. Its bias current is set by
external resistor R4 to typically 190 µA (173 MHz), 350 µA
(470 MHz) and 1 mA (930 MHz). The oscillator signal is
internally AC coupled to one input of the emitter-coupled
pair while the other input is internally grounded via a
capacitor. The frequency multiplier output signal between
pins VO1MUL and VO2MUL drives the upper switching
stages of the mixers. The bias voltage on pins VO1MUL
and VO2MUL is set by external resistor R3 to allow
sufficient voltage swing at the mixer outputs. The value of
R3 depends on the operating frequency: 1.5 kΩ
(173 MHz), 820 Ω (470 MHz) and 330 Ω (930 MHz).
Low noise amplifiers, active filters and gyrator filters
The low noise amplifiers ensure that the noise of the
following stages does not affect the overall noise figure.
The following active filters before the gyrator filters reduce
the levels of large signals from adjacent channels. Internal
AC couplings block DC offsets from the gyrator filter
inputs.
Oscillator
The oscillator is based on a transistor in common collector
configuration. It is followed by a cascode stage driving a
tuned circuit which provides the signal for the frequency
multiplier. The oscillator transistor requires an external
bias voltage V
current (typically 250 µA) is determined by the 1.5 kΩ
external resistor R5. The oscillator frequency is controlled
by an external 3rd overtone crystal in parallel resonance
mode. External capacitors between base and emitter
(C17) and from emitter to ground (C16) make the oscillator
transistor appear as having a negative resistance for small
signals; this causes the oscillator to start. Inductance L9
connected in parallel with capacitor C16 to the emitter of
the oscillator transistor prevents oscillation at the
fundamental frequency of the crystal.
1996 Jan 1518
(1.22 V typ.). The oscillator bias
bias(osc)
The gyrator filters implement the transfer function of a 7th
order elliptic filter. Their cut-off frequencies are determined
by the 47 kΩ external resistor R2 between pins RGYR and
COM. The gyrator filter output signals are available on IF
test pins TPI and TPQ.
Limiters
The gyrator filter output signals are amplified in the limiter
amplifiers to obtain IF signals with removed amplitude
information.
Demodulator
The limiter amplifier output signals are fed to the
demodulator. The demodulator output DO is going LOW or
HIGH depending upon which of the input signals has a
phase lead.
Page 19
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
Battery LOW indicator
The battery LOW indicator senses the supply voltage and
sets its output HIGH when the voltage at input SENSE is
less than Vth (typically 1.10 V). Low battery warning is
Band gap reference
The whole chip except the oscillator section can be
powered-up and powered-down by enabling and disabling
the band gap reference via the receiver enable pin RE.
available at BLI.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Ground pins GND1, GND2 and GND3 connected together.
V
LOW level input voltage0−0.3V
HIGH level input currentVIH=VP= 3.5 V−−20µA
LOW level input currentVIL=0V0−−1.0µA
HIGH level output voltageV
LOW level output voltageV
voltage threshold for battery
LOW indicator
VP= 2.05 V; T
V
T
HIGH level output voltageIDO= −10 µAV
< Vth; I
SENSE
> Vth; I
SENSE
= 2.05 to 3.5 V;
P
= −10 to +70 °C
amb
= −10 µAV
BLI
= +10 µA−−0.5V
BLI
=25°C1.051.101.15V
amb
−0.5 −−V
P
1.031.101.17V
−0.5 −−V
P
LOW level output voltageIDO= +10 µA−−0.5V
1996 Jan 1520
Page 21
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
AC CHARACTERISTICS (173 MHz)
V
= 2.05 V; T
P
random bit sequence modulation (t
channel spacing; unless otherwise specified.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Radio frequency input
P
i(ref)
Mixers to demodulator
α
acs
α
ci
α
c
α
sp
α
im
α
bl
f
offset
∆f
dev
t
on
=25°C; test circuit Figs 1 or 2; f
amb
= 250 ±25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
r
input sensitivity (P
i(ref)
is the
maximum available power at
the RF input of the test board)
adjacent channel selectivityT
BER ≤3⁄
T
V
T
= 172.941 MHz with ±4.0 kHz deviation; 1200 baud pseudo
i(RF)
; note 1−−126.5−123.5dBm
100
= −10 to +70 °C; note 2−−−120.5dBm
amb
= 1.9 V−−−117.5dBm
P
=25°C6972−dB
amb
= −10 to +70 °C67−−dB
amb
IF filter channel imbalance−−2dB
co-channel rejection−47dB
spurious immunity5060−dB
intermodulation immunity5560−dB
blocking immunity∆f >±1 MHz; note 37885−dB
frequency offset range
(3 dB degradation in sensitivity)
deviation range
deviation f = ±4.0 kHz±2.0−−kHz
deviation f = ±4.5 kHz±2.5−−kHz
2.5−7.0kHz
(3 dB degradation in sensitivity)
receiver turn-on timedata valid after setting RE input
−−5ms
HIGH; note 4
Notes
1. The bit error rate BER is measured using the test facility shown in Fig.12. Note that the BER test facility contains a
digital input filter equivalent to the one used in the PCA5000A, PCF5001 and PCD5003 POCSAG decoders.
2. Capacitor C16 requires re-adjustment to compensate temperature drift.
3. ∆f is the frequency offset between the required signal and the interfering signal.
4. Turn-on time is defined as the time from pin RE going HIGH to the reception of valid data on output pin DO. Turn-on
time is measured using an external oscillator (turn-on time using the internal oscillator is dependent upon the
oscillator circuitry).
1996 Jan 1521
Page 22
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
AC CHARACTERISTICS (470 MHz)
V
= 2.05 V; T
P
random bit sequence modulation (t
channel spacing; unless otherwise specified.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Radio frequency input
P
i(ref)
Mixer input
P
i(mix)
Mixers to demodulator
α
acs
α
ci
α
c
α
sp
α
im
α
bl
f
offset
∆f
dev
t
on
=25°C; test circuit Figs 3 or 4; f
amb
= 250 ± 25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
r
input sensitivity (P
maximum available power at
the RF input of the test board)
i(ref)
is the
BER ≤3⁄
T
V
input sensitivityBER ≤3⁄
adjacent channel selectivityT
T
= 469.950 MHz with ±4.0 kHz deviation; 1200 baud pseudo
i(RF)
; note 1−−124.5−121.5dBm
100
= −10 to +70 °C; note 2−−−118.5dBm
amb
= 1.9 V−−−115.5dBm
P
; note 3−−115.0−110.0dBm
100
=25°C6770−dB
amb
= −10 to +70 °C65−−dB
amb
IF filter channel imbalance−−2dB
co-channel rejection−47dB
spurious immunity5060−dB
intermodulation immunity5560−dB
blocking immunity∆f >±1 MHz; note 47582−dB
frequency offset range
(3 dB degradation in sensitivity)
deviation range
deviation f = ±4.0 kHz±2.0−−kHz
deviation f = ±4.5 kHz±2.5−−kHz
2.5−7.0kHz
(3 dB degradation in sensitivity)
receiver turn-on timedata valid after setting RE input
−−5ms
HIGH; note 5
Notes
1. The bit error rate BER is measured using the test facility shown in Fig.12. Note that the BER test facility contains a
digital input filter equivalent to the one used in the PCA5000A, PCF5001 and PCD5003 POCSAG decoders.
2. Capacitor C16 requires re-adjustment to compensate temperature drift.
3. Test circuit Fig.5. P
is the maximum available power at the input of the test board. The bit error rate BER is
i(mix)
measured using the test facility shown in Fig.12.
4. ∆f is the frequency offset between the required signal and the interfering signal.
5. Turn-on time is defined as the time from pin RE going HIGH to the reception of valid data on output pin DO. Turn-on
time is measured using an external oscillator (turn-on time using the internal oscillator is dependent upon the
oscillator circuitry).
1996 Jan 1522
Page 23
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
AC CHARACTERISTICS (930 MHz)
V
= 2.05 V; T
P
random bit sequence modulation (t
channel spacing; unless otherwise specified.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Radio frequency input
P
i(ref)
Mixers to demodulator
α
acs
α
c
α
sp
α
im
α
bl
f
offset
∆f
dev
t
on
=25°C; test circuit Fig.6; note 1; f
amb
= 250 ± 25 µs measured between 10% and 90% of voltage amplitude) and 20 kHz
r
input sensitivity (P
i(ref)
is the
maximum available power at
the RF input of the test board)
adjacent channel selectivityT
BER ≤3⁄
V
P
amb
= 930.500 MHz with ±4.0 kHz deviation; 1200 baud pseudo
i(RF)
; note 2−−120.0−114.0dBm
100
= 1.9 V−−−108.0dBm
=25°C6069−dB
co-channel rejection−510dB
spurious immunity4060−dB
intermodulation immunity5360−dB
blocking immunity∆f >±1 MHz; note 36574−dB
frequency offset range
(3 dB degradation in sensitivity)
deviation range
deviation f = ±4.0 kHz±2.0−−kHz
deviation f = ±4.5 kHz±2.5−−kHz
2.5−7.0kHz
(3 dB degradation in sensitivity)
receiver turn-on timedata valid after setting RE input
−−5ms
HIGH; note 4
Notes
1. The external oscillator signal V
has a frequency of f
i(OSC)
= 310.1667 MHz and a level of −15 dBm.
OSC
2. The bit error rate BER is measured using the test facility shown in Fig.12. Note that the BER test facility contains a
digital input filter equivalent to the one used in the PCA5000A, PCF5001 and PCD5003 POCSAG decoders.
3. ∆f is the frequency offset between the required signal and the interfering signal.
4. Turn-on time is defined as the time from pin RE going HIGH to the reception of valid data on output pin DO. Turn-on
time is measured using an external oscillator (turn-on time using the internal oscillator is dependent upon the
oscillator circuitry).
1996 Jan 1523
Page 24
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator: f
gen=fi(RF)
+ 4 kHz, no modulation, V
= 1 mV (RMS).
i(RF)
2. Measure the IF with a counter connected to test pin TPI. Tune C16 to set the crystal oscillator to achieve fIF= 4 kHz
Change the generator frequency to f
frequency f
crystal frequency is f
signal must be used with f
= 172.941 MHz the crystal frequency is f
i(RF)
= 78.325 MHz. For a received input frequency f
XTAL
= 310.1667 MHz and a level of −15 dBm (for definition of crystal frequency, see
i(OSC)
gen=fi(RF)
− 4 kHz and check that fIF is also 4 kHz. For a received input
= 57.647 MHz, while for f
XTAL
i(RF)
= 930.500 MHz an external oscillator
= 469.950 MHz the
i(RF)
Table 1).
3. Set the signal generator to nominal frequency (f
wave modulation, V
receiver is tuned, to ensure V
= 1 mV (RMS). Note that the RF signal should be reduced in the following tests, as the
i(RF)
= 10 to 50 mV (p-p) on test pins TPI or TPQ.
o(IF)
) and turn on the modulation deviation ±4.0 kHz, 600 Hz square
i(RF)
4. Tune C15 (oscillator output circuit) and C12 (frequency multiplier output) to obtain a peak audio voltage on pin TPI.
5. Tune C3 and C6 (RF input and mixer input) to obtain a peak audio voltage on pin TPI. When testing the mixer input
sensitivity tune C23 instead of C3 and C6 (test circuit Fig.5).
6. Check that the output signal on pin TPQ is within 3 dB in amplitude and at 90° (±20°) relative phase of the signal on
pin TPI.
7. Check that data signal appears on output pin DO and proceed with the AC test.
AC test conditions
Table 5 Definitions for AC test conditions (see Table 6)
SIGNALDESCRIPTION
Modulated test signal 1
Frequency172.941, 469.950 or 930.500 MHz
Deviation±4.0 kHz
Modulation 1200 baud pseudo random bit sequence
Rise time250 ±25 µs (between 10% and 90% of final value)
Modulated test signal 2
Deviation±2.4 kHz
Modulation 400 Hz sine wave
Other definitions
f
f
f
∆f
P
P
P
P
1
2
3
cs
1
2
3
i(ref)
frequency of signal generator 1
frequency of signal generator 2
frequency of signal generator 3
channel spacing (20 kHz)
maximum available power from signal generator 1 at the test board input
maximum available power from signal generator 2 at the test board input
maximum available power from signal generator 3 at the test board input
maximum available power at the test board input to give a Bit Error Rate (BER) ≤3⁄
test signal 1, in the absence of interfering signals and under the conditions as specified in Chapters
“AC characteristics (173 MHz)”, “AC characteristics (470 MHz)” and “AC characteristics (930 MHz)”
1996 Jan 1524
for the modulated
100
Page 25
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
Table 6 AC test conditions; notes 1 and 2
SYMBOLPARAMETERCONDITIONSTEST SIGNALS
α
α
α
α
α
f
offset
∆f
t
on
a
c
sp
im
bl
dev
adjacent channel selectivity;
Fig.11(b)
co-channel rejection; Fig.11(b) f2=f1±up to 3 kHz
spurious immunity; Fig.11(b)f2= 100 kHz to 2 GHz
intermodulation immunity;
Fig.11(c)
blocking immunity; Fig.11(b)f2=f1±1 MHz
frequency offset range;
Fig.11(a)
deviation range; Fig.11(a)deviation = ±2.5 to ±7 kHz; (∆f
receiver turn-on time; Fig.1 1(a) note 3
f2=f1±∆f
CS
generator 1: modulated test signal 1P1=P
generator 2: modulated test signal 2P
generator 1: modulated test signal 1P
generator 2: modulated test signal 2P
generator 1: modulated test signal 1P
generator 2: modulated test signal 2P
f2=f1±∆fcs; f3=f1±2∆f
cs
generator 1: modulated test signal 1P1=P
generator 2: unmodulatedP
generator 3: modulated test signal 2P3=P
generator 1: modulated test signal 1P
generator 2: modulated test signal 2P
deviation = ±4.0 kHz, f1=f
i(RF)
± 2 kHz (f
offset(min)
)
generator 1: modulated test signal 1P
dev(min)
to ∆f
dev(max)
)
generator 1: modulated test signal 1P
generator 1: modulated test signal 1P
+3dB
i(ref)
2=P1+αa(min)
i(ref)
2
+3dB
+3dB
+3dB
+3dB
+3dB
+3dB
+10dB
1=Pi(ref)
2=P1−αc(max)
1=Pi(ref)
2=P1+αsp( min)
2=P1+αim(min)
1=Pi(ref)
2=P1+αbl(min)
1=Pi(ref)
1=Pi(ref)
1=Pi(ref)
Notes
1. The tests are executed without load on pins TPI and TPQ.
2. All minimum and maximum values correspond to a bit error rate (BER) ≤
3. The BER measurement is started 5 ms (t
(BER ≤3⁄
100
).
) after VRE goes HIGH; BER is then measured for 100 bits
on(max)
1996 Jan 1525
3
⁄
in the wanted signal (P1).
100
Page 26
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
(a) One generator.
(b) Two generators.
(c) Three generators.
(1) See Fig.12.
(a)
(b)
(c)
GENERATOR 1
R = 50 Ω
s
GENERATOR 1
R = 50 Ω
s
GENERATOR 2
R = 50 Ω
s
GENERATOR 1
R = 50 Ω
s
GENERATOR 2
R = 50 Ω
s
GENERATOR 3
R = 50 Ω
s
DEVICE
UNDER TEST
50 Ω 2-SIGNAL
POWER
COMBINER
50 Ω 3-SIGNAL
POWER
COMBINER
DEVICE
UNDER TEST
DEVICE
UNDER TEST
Fig.11 Test configurations.
BER TEST
FACILITY
BER TEST
FACILITY
BER TEST
FACILITY
MLC232
(1)
(1)
(1)
handbook, full pagewidth
GENERATOR
R = 50 Ω
s
DEVICE
UNDER TEST
DIGITAL
FILTER
250 µs
RISE TIME
Fig.12 BER test facility.
1996 Jan 1526
CLOCK
RECOVERY
PRESET
DELAY
PSEUDO
RANDOM
SEQUENCE
GENERATOR
recovered clock
retimed
Rx data
DATA
COMPARATOR
MASTER
CLOCK
MLC233
to error
counter
Page 27
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
PRINTED-CIRCUIT BOARDS
handbook, full pagewidth
Fig.13 PCB top view for LQFP32; test circuit Figs 1 and 3.
1996 Jan 1527
MBD562
Page 28
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
Fig.14 PCB bottom view for LQFP32; test circuit Figs 1 and 3.
1996 Jan 1528
MBD561
Page 29
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
C19
R3
VEE= GND; VC =VP.
TS
BLI
DO
RE
V
GND
L6L7
V
bosc
C14
C16
C12
UAA2082H
L8
C17
L9
R5
C18
V
sense
C15
C20
P
R6
C13
XTAL
DOTPITPQ
R2
L5
L4
C11
C10
VIRF
C9
C7
C8
L3
C6
C4
L2
R1
MLC234
Fig.15 PCB top view with components for LQFP32; test circuit Fig.3.
1996 Jan 1529
Page 30
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
C5
R4
C3
L1
C2
C1
MLC235
Fig.16 PCB bottom view with components for LQFP32; test circuit Fig.3.
1996 Jan 1530
Page 31
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
C19
R3
V
GND
C12
L8
C17
L9
L6
R2
UAA2082H
L5
L4
L7
V
bosc
C14
V
sense
C15
C16
C20
P
R6
C13
XTAL
C11
C23
C21
V
L10
C10
C22
i RF
R5
C18
TS
BLI
DO
RE
DOTPITPQ
MLC236
Fig.17 PCB top view with components for LQFP32; test circuit Fig.5.
1996 Jan 1531
Page 32
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
C5
R4
Fig.18 PCB bottom view with components for LQFP32; test circuit Fig.5.
1996 Jan 1532
MLC237
Page 33
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
ok, full pagewidth
V
i(OSC)
GND
V
C13
P
R3
C14
C19
C15
C12
L6
L7
L8
TS
BLI
DO
RE
TPI
TPQ
R2
UAA2082H
C1
C2
C8
R1
C9L4L5
L11
L10
C7
L3
C4
L2
C6
L1
C3
Fig.19 PCB top view with components for LQFP32; test circuit Fig.6.
1996 Jan 1533
V
MLC238
i(RF)
Page 34
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
handbook, full pagewidth
C5
R4
Fig.20 PCB bottom view with components for LQFP32; test circuit Fig.6.
1996 Jan 1534
MLC239
Page 35
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
c
y
X
2417
25
pin 1 index
32
1
16
Z
E
e
w M
b
p
9
8
A
H
E
E
A
2
A
SOT358-1
Q
(A )
A
1
L
detail X
3
θ
L
p
e
DIMENSIONS (mm are the original dimensions)
mm
OUTLINE
VERSION
SOT358 -1
A
A1A2A3bpcE
max.
0.20
1.45
1.60
0.05
0.25
1.35
IEC JEDEC EIAJ
UNIT
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
w M
b
p
D
H
D
0.4
0.3
Z
D
B
v M
02.55 mm
scale
(1)
(1)(1)(1)
D
0.18
7.1
0.12
6.9
REFERENCES
eH
H
7.1
6.9
0.8
9.15
8.85
1996 Jan 1535
v M
D
A
B
9.15
8.85
LLpQZywv θ
E
0.69
0.75
0.45
0.59
0.250.11.00.2
EUROPEAN
PROJECTION
Z
D
0.9
0.5
ISSUE DATE
93-06-29
95-12-19
0.9
0.5
E
o
7
o
0
Page 36
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
(order code 9398 652 90011).
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1996 Jan 1536
Page 37
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jan 1537
Page 38
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
NOTES
1996 Jan 1538
Page 39
Philips SemiconductorsProduct specification
Advanced pager receiverUAA2082
NOTES
1996 Jan 1539
Page 40
Philips Semiconductors – a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)
BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. (02)805 4455, Fax. (02)805 4466
Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,
Tel. (01)60 101-1236, Fax. (01)60 101-1211
Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
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