Transmit chain and synthesizer with
integrated VCO for DECT
Product specification
File under Integrated Circuits, IC17
1999 Jun 04
Page 2
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
FEATURES
• Economical integrated solution for frequency generation
in DECT cordless telephones
• Integrated low phase noise 950 MHz VCO with
frequency doubler
• Local Oscillator (LO) drive (−14 dBm) for RF mixer
circuit
• Dedicated DECT PLL synthesizer
• 3-line serial interface bus
• 3 dBm output preamplifier with an integrated switch
• Low current consumption from 3 V supply
• Compatible with Philips Semiconductors ABC baseband
chip (PCD509x series).
APPLICATIONS
• 1880 to 1920 MHz DECT cordless telephones.
GENERAL DESCRIPTION
The UAA2068AHL BiCMOS device integrates a 950 MHz
VCO, a frequency doubler, main and reference dividers
and a phase comparator, to implement a phase-locked
loop for DECT channel frequencies. The 1.9 GHz signal is
buffered and switched, in TX mode, to drive the transmit
power amplifier (CGY20xx series) or, in RX mode, to be
used as an LO signal for the receiver mixer IC
(UAA3540TS).
UAA2068AHL
The reference divider ratio is fixed at 16. Outputs of the
main and reference dividers drive a phase comparator
where a charge pump produces phase error current pulses
for integration in an external loop filter. Only a passive loop
filter is necessary. The charge-pump current (phase
comparator gain) is set by an external resistor (R
R
.
SET
The VCO is powered from an internally regulated voltage
source and includes internal varicap diodes. Its tuning
range is wider than the required band to allow for
production spreads. In a Time Division Multiple Access
(TDMA) system such as DECT, the VCO and the
synthesizer are switched on one slot before the required
one to lock the VCO to the required channel frequency.
Just before the required slot, the synthesizer is switched
off, allowing open-loop modulation of the VCO during
transmission. When opening the loop, the frequency
pulling (due to switching off the synthesizer) can be
maintained within the DECT specification.
The device is designed to operate from 3 NiCd cells in
pocket phones, with low current and nominal 3.6 V
supplies. Separate power and ground pins are provided to
the different parts of the circuit. The ground leads should
be short-circuited externally to prevent large currents
flowing across the die and thus causing damage.
All supply pins (VCC) must also be at the same potential,
except V
other supply pins (e.g. VCC= 3 V and V
wider VCO control voltage range).
which can be equal to or greater than the
CC(CP)
CC(CP)
) at pin
SET
= 5 V for
The synthesizer’s main divider is driven by the frequency
doubler output in the range from 1880 to 1920 MHz and
programmed via a 3-wire serial bus.
VCO and buffer parts supply currentVCO_ON = 1−9.514mA
doubler supply currentin RX mode−14.419mA
in TX mode−1014mA
TX preamplifier supply currentin RX mode−050µA
in TX mode−2432mA
total supply current in Power-down mode−550µA
RF output frequency1880−1920MHz
crystal reference input frequency−13.824−MHz
phase comparator frequency−864−kHz
operating ambient temperature−10−+60°C
1999 Jun 043
Page 4
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
BLOCK DIAGRAM
handbook, full pagewidth
V
R_OFF
AMPGND
V
CC(SYD)
V
CC(SYA)
TXA
TXB
LOA
LOB
26
29
28
27
12
13
2
5
CC(AMP)
3015111617242120
PREAMP
V
CC(DBL)
BUFFER
3-LINE BUS
32
131436107
T_EN
RF
SWITCH
LO
MAIN DIVIDER
REFERENCE DIVIDER
V
CC(DBL)
DOUBLER
V
CC(BUF)
BUFFER
V
UAA2068AHL
PHASE
COMPARATOR
CC(VCO)
V
REG
VCO
UAA2068AHL
LL
VCOB
VCOA
23
18
25
22
19
14
9
CHARGE
PUMP
8
V
TUNE
V
MOD
VCO_ON
VCGND
VCOGND
DBLGND
V
CC(CP)
CP
S_EN
DATA
CLK
XTAL
SYDGND
SYAGND
Fig.1 Block diagram.
1999 Jun 044
R
SET
CPGND
R
SET
FCA071
Page 5
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
PINNING
SYMBOLPINDESCRIPTION
DATA13-wire programming bus data input
V
CC(SYD)
SYDGND3synthesizer CMOS divider ground
XTAL4reference frequency input
V
CC(SYA)
SYAGND6synthesizer prescaler ground
CPGND7charge-pump ground
CP8charge-pump output signal
V
CC(CP)
R
SET
V
CC(DBL)
LOA12local oscillator output A
LOB13local oscillator output B
DBLGND14doubler ground
T_EN15transmit enable signal input
V
CC(BUF)
V
CC(VCO)
V
MOD
VCOGND19VCO ground; note 1
VCOA20VCO inductor connection A
VCOB21VCO inductor connection B
VCGND22internal varicap ground; note 1
V
TUNE
V
REG
VCO_ON25VCO power-on control input; note 2
R_OFF26power-on control for RX LO buffer/TX preamplifier; note 3
AMPGND27transmit amplifier ground
TXB28transmit amplifier output B
TXA29transmit amplifier output A
V
CC(AMP)
CLK313-wire programming bus clock input
S_EN32synthesizer enable signal input
2synthesizer CMOS divider positive supply voltage
5synthesizer prescaler positive supply voltage
9charge-pump positive supply voltage
10charge-pump current setting input
11doubler positive supply voltage
16VCO isolation buffer positive supply voltage
17VCO positive supply voltage
18transmit modulation input
23VCO tuning input
24VCO regulator output
30transmit amplifier positive supply voltage
UAA2068AHL
Notes
1. Pins 19 and 22 are internally short-circuited.
2. Use with S_PWR on ABC baseband chip.
3. Use with R_PWR on ABC baseband chip.
1999 Jun 045
Page 6
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
handbook, full pagewidth
CLK
S_EN
31
32
1
DATA
XTAL
CP
2
3
4
5
6
7
8
9
10
SET
R
CC(CP)
V
V
CC(SYD)
SYDGND
V
CC(SYA)
SYAGND
CPGND
CC(AMP)
V
30
TXA
29
TXB
28
UAA2068AHL
11
12
13
LOB
LOA
CC(DBL)
V
R_OFF
AMPGND
27
26
14
15
T_EN
DBLGND
VCO_ON
25
16
CC(BUF)
V
24
23
22
21
20
19
18
17
FCA070
V
REG
V
TUNE
VCGND
VCOB
VCOA
VCOGND
V
MOD
V
CC(VCO)
UAA2068AHL
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Transmit chain
BUFFER AND FREQUENCY DOUBLER
VCO,
The VCO operates at a nominal centre frequency of
950 MHz. The VCO is fully integrated apart from two
inductors which complete the resonator network. The VCO
operates from an on-chip regulated power supply (V
REG
which minimizes frequency disturbances due to variations
in supply voltage. The buffered VCO signal is fed into a
frequency doubler. The large difference between the
transmitted and VCO frequencies reduces transmitter
oscillator coupling problems.
The output of the doubler is used to drive the synthesizer
main divider and can also be switched to either the TX
preamplifier or the RX LO output buffer. The high isolation
obtained from the VCO buffer and the frequency doubler
ensures that very small frequency changes occur when
turning on the TX preamplifier or the RX LO output buffer.
In TX mode, the oscillator can be directly modulated with
GMSK filtered data at pin V
MOD
.
RF SWITCH
The RF switch passes the doubled VCO signal to either
the TX preamplifier (when T_EN is HIGH) or to the RX LO
buffer (when T_EN is LOW). In TX mode, the difference in
the RF power levels, observed at the TX output when
T_EN is switched from LOW-to-HIGH, is typically 40 dB.
TX
),
PREAMPLIFIER
The TX preamplifier amplifies the RF signal up to a level of
3 dBm which is suitable for use with Philips
Semiconductors DECT power amplifiers such as the
CGY20xx series. It is powered-up when both R_OFF and
VCO_ON are HIGH.
RX LO
BUFFER
The RX LO buffer outputs the frequency doubled VCO
signal at a level of −14 dBm. This signal can then be used
as the local oscillator drive for the receive mixers of
devices such as the UAA3540TS. The buffer is
powered-up when R_OFF is LOW and VCO_ON is HIGH.
1999 Jun 046
Page 7
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
Synthesizer
AIN DIVIDER
M
The main divider is clocked by the RF signal from the
internal frequency doubler. The divider operates at
frequencies from 1880 to 1920 MHz. It consists of a
bipolar prescaler followed by a CMOS counter. Any main
divider ratio from 2176 to 2303 inclusive can be
programmed.
EFERENCE DIVIDER
R
The reference divider is clocked by the signal at pin XTAL.
The circuit operates with levels from 50 to 500 mV (RMS)
at a frequency of 13.824 MHz, with a fixed divider ratio
of 16.
HASE COMPARATOR
P
The phase comparator is driven by the output of the main
and reference dividers. It produces current pulses at the
charge-pump output (pin CP). The pulse duration is equal
to the difference in time of arrival of the edges from the two
dividers. If the main divider edge arrives first, pin CP sinks
current; if the reference divider edge arrives first, pin CP
sources current. The DC value of the charge-pump current
is nominally ten times the current drawn by the external
resistor connected to pin R
included to ensure that the gain of the phase detector
remains linear even for small phase errors.
The charge pump has a separate supply, V
helps to reduce the interference on the charge-pump
output from other parts of the circuit. V
than the other supply voltages if a wider range on the VCO
input is required. The V
than that on other VCC pins.
Additional circuitry is
SET
CC(CP)
voltage must not be less
CC(CP)
, which
CC(CP)
can be higher
UAA2068AHL
For the divider ratio, the first bit (b6) entered is the most
significant (MSB).
S_EN must be LOW to capture new programming data.
S_EN must be HIGH to switch-on the synthesizer.
Operating modes
The synthesizer is on when the input signal S_EN is HIGH,
and off when S_EN is LOW. When turned on, the dividers
and phase detector are synchronized to avoid a random
initial phase error. When turned off, the phase detector is
synchronized with the dividers to avoid interrupting a
charge-pump pulse.
The VCO is on when the input signal VCO_ON is HIGH.
The polarity of VCO_ON is chosen for compatibility with
output S_PWR at the ABC chip. When turned on, it needs
some time (typically 30 µs) to reach its steady state.
The TX preamplifier is on when both R_OFF and VCO_ON
are HIGH. The polarity of R_OFF is chosen for
compatibility with output R_PWR at the ABC chip. When
turned on, it needs some time (typically 10 µs) to reach its
steady state. In transmit mode, the timing of the R_OFF
LOW-to-HIGH transition can be chosen such that the TX
preamplifier is turned on while the synthesizer loop
remains closed thus avoiding frequency pulling of the
VCO. In the receive mode, depending on the exact timing
of R_OFF compared to VCO_ON, the TX preamplifier can
be switched on at the beginning of the previous slot, but is
switched off when R_OFF goes LOW; this occurs when
the synthesizer loop is closed. The LO output amplifier is
turned on when R_OFF is LOW and VCO_ON is HIGH.
The UAA2068AHL has a very low current consumption in
Power-down mode.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. These 3 lines are data (DATA), clock (CLK) and
enable (S_EN). The data sent to the device is loaded in
bursts framed by S_EN. Programming clock edges and
their appropriate data bits are ignored until S_EN goes
active LOW. The programmed information is read directly
by the main divider when S_EN returns HIGH. During
synthesizer operation, S_EN should be kept HIGH.
In normal operating mode, the last 16 bits serially clocked
into the device are retained within the register. Additional
leading bits are ignored, and no check is made on the
number of clock pulses. The data format is given in
Table 2. The first bit entered is b15, the last bit is b0.
1999 Jun 047
Page 8
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
UAA2068AHL
integrated VCO for DECT
Table 1 Mode control; note 1
BLOCK STATUSVCO_ONR_OFFT_ENS_EN
VCO, buffer, doubler, RF switch, TX preamplifier and LO buffer
powered-down
VCO, buffer, doubler, RF switch and TX preamplifier powered-up111X
LO buffer powered-down
Nominal RF signal at TX output
VCO, buffer, doubler, RF switch and TX preamplifier powered-up110X
LO buffer powered-down
No RF signal output
VCO, buffer, doubler, RF switch and LO buffer powered-up100X
TX preamplifier powered-down
Nominal RF signal at LO buffer output
VCO, buffer, doubler, RF switch and LO buffer powered-up101X
TX preamplifier powered-down
No RF signal output
To power-down PLL blocks; notes 2 and 31XX0
To power-up PLL blocks; notes 2 and 31XX1
All blocks in power-down state; notes 2 and 30XX0
New PLL division ratio is loaded and the PLL blocks are powered-up on
the rising edge of S_EN; note 3
0XXX
1XX0 to 1
Notes
1. X = don’t care.
2. PLL blocks are the main divider, reference divider, phase detector and charge pump.
3. A reference signal is needed on pin XTAL for correct operation.
Table 2 Bit allocation; note 1
FIRST INREGISTER BIT ALLOCATIONLAST IN
DATA FIELD
b15b14b13b12b11b10b9b8b7b6
000100001main divider programming
Notes
1. For normal operation, b15 to b0 need to be programmed.
2. Bit b6 is the MSB of the main divider coefficient.
3. The main divider ratio is equal to 2176 plus the programmed value (see Table 3).
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
CC
V
CC(CP)
CC(CP)
− V
CC
V
∆GNDdifference in ground supply voltage applied
supply voltage−0.3+5.5V
charge-pump supply voltage−0.3+5.5V
difference in voltage between V
CC(CP)
and V
CC
note 1− 0.3V
between all ground pins
P
tot
T
stg
T
amb
T
j
total power dissipation−275mW
storage temperature−55+125°C
operating ambient temperature−10+60°C
junction temperature−150°C
SYNTHESIZED
FREQUENCY (MHz)
−0.3+5.5V
Note
1. Pins short-circuited internally must be short-circuited externally.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSVALUEUNIT
R
th(j-a)
thermal resistance from junction to ambientin free air100K/W
TX preamplifier output resistance
(real part of the parallel output
impedance)
C
o(TX)
TX preamplifier output
capacitance (imaginary part of
the parallel output impedance)
FTVCO
VCO frequency feedthrough at
TX
the TX output
CNR
CNR
∆f
o(offset)
carrier-to-noise ratio at TX output carrier offset
25
carrier-to-noise ratio at TX output carrier offset
4686
total frequency shift due to
200 mV VCC change disabling the
synthesizer
∆f
P
R
o(drift)
o(LO)
o(LO)
frequency drift during a slotnote 2−1± 10kHz
LO preamplifier output powernote 2−−14−dBm
LO preamplifier output
resistance (real part of the
parallel output impedance)
range; note 2
f = 1890 MHz; note 2−−50−dB
f = 1890 MHz; note 2−−40−dB
range; note 2
balanced−150−Ω
balanced−0.5−pF
referenced to the f
level; note 2
∆f = 25 kHz
∆f = 4686 kHz
measured 20 µs after
disabling the
synthesizer; note 2
balanced−120−Ω
940−960MHz
037dBm
1880−1920MHz
−−41−36dBc
o(TX)
−−75−
−−135−132
−−±15kHz
dBc/Hz
dBc/Hz
1999 Jun 0411
Page 12
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
UAA2068AHL
integrated VCO for DECT
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
C
o(LO)
Interface logic input signal levels; pins DATA, CLK, S_EN, T_EN, R_OFF and VCO_ON
V
IH
V
IL
I
bias
C
i
Notes
1. Condition: 0.5 < VCP<(V
2. Measured and guaranteed only on the Philips evaluation board, including PCB and balun filter.
3. VIH should never exceed 5.2 V.
SERIAL BUS TIMING CHARACTERISTICS
= 3.6 V; T
V
CC
LO preamplifier output
balanced−0−pF
capacitance (imaginary part of
the parallel output impedance)
HIGH-level input voltagenote 3 2.2−VCC+ 0.3 V
LOW-level input voltage−0.3−+0.5V
input bias currentlogic 1 or logic 0−5−+5µA
input capacitance−2−pF
− 0.5).
CC(CP)
=25°C; unless otherwise specified.
amb
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
Serial programming clock; CLK
t
r
t
f
T
cy
input rise time−1040ns
input fall time−1040ns
clock period100−−ns
Enable programming; S_EN
t
START
t
END
t
W
t
SU;S_EN
delay to rising clock edge40−−ns
delay from last falling clock edge−20−−ns
minimum inactive pulse width4000−−ns
enable set-up time to next clock edge20−−ns
Register serial input data; DATA
t
SU;DAT
t
HD;DAT
input data to clock set-up time20−−ns
input data to clock hold time20−−ns
1999 Jun 0412
Page 13
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
handbook, full pagewidth
CLK
DATA
S_EN
t
SU;DAT
t
START
MSBLSB
t
HD;DAT
Fig.3 Serial bus timing diagram.
UAA2068AHL
T
cy
t
t
f
r
t
ENDtSU;S_EN
MBK095
t
W
1999 Jun 0413
Page 14
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
TIMING CHARACTERISTICS
handbook, full pagewidth
slot time
In TX mode
DATA
CLK
S_EN
VCO_ON
= S_PWR
R_OFF
= R_PWR
(1)
(1)
previous slotactive slot
UAA2068AHL
In RX mode
VCO_ON
= S_PWR
R_OFF
= R_PWR
(1) On ABC baseband chip.
T_EN
DATA
CLK
S_EN
(1)
(1)
T_EN
MGK384
Fig.4 Application bus timing diagram.
1999 Jun 0414
Page 15
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
APPLICATION INFORMATION
handbook, full pagewidth
8.2 nH
1 pF
22 pF
CLK
SET
R
10 pF
CC(AMP)
V
CC(DBL)
V
V
CC
8.2
pF
6.8 nH
6.8 nH
S_EN
32 31 30 29
1
2
3
4
5
6
7
8
9 10111213141516
CC(CP)
V
R
SET
8.2 kΩ
120 pF
from
ABC
chip
8.2 pF
1 kΩ
1 kΩ
1 kΩ
V
CC
8.2 pF
V
CC
100 nF
loop filter
560 pF
8.2 pF
8.2 pF
V
CC(SYD)
SYDGND
V
CC(SYA)
SYAGND
CPGND
1.5 kΩ
V
CC
8.2 pF
DATA
XTAL
8.2 pF
3.9 kΩ
8.2 nF
NPO
CP
TXOUT
1.8 nH
3.9 pF
TXB
TXA
28 27 26 25
UAA2068AHL
LOB
LOA
8.2
pF
to receiver
1 pF
8.2 nH
10 pF
22 pF
R_OFF
AMPGND
T_EN
DBLGND
8.2
pF
VCO_ON
24
23
22
21
20
19
18
17
CC(BUF)
V
1 kΩ
8.2 pF
V
CC
8.2 pF
1 kΩ
8.2 pF
1 kΩ
8.2 pF
V
REG
V
TUNE
VCGND
VCOB
VCOA
VCOGND
V
MOD
V
CC(VCO)
8.2 pF
from ABC chip
L1
6.8 nH
L2
6.8 nH
V
CC
UAA2068AHL
from ABC
chip
82 nF
8.2
pF
from
ABC chip
FCA072
L1 and L2: order of magnitude.
Values depend on board layout.
Fig.5 Typical application diagram.
1999 Jun 0415
Page 16
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm
c
y
X
24
25
17
Z
16
E
A
UAA2068AHL
SOT401-1
e
pin 1 index
32
1
e
DIMENSIONS (mm are the original dimensions)
mm
A
max.
1.60
A
1A2A3bp
0.15
1.5
1.3
0.25
0.05
UNIT
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
w M
b
p
D
H
D
cE
0.27
0.18
0.17
0.12
9
8
Z
D
B
02.55 mm
(1)(1)(1)
D
5.1
4.9
w M
b
p
v M
v M
scale
(1)
eH
H
5.1
4.9
0.5
7.15
6.85
D
E
A
B
H
E
E
7.15
6.85
A
A
LL
p
0.75
1.0
0.45
2
A
1
detail X
Z
D
0.2
0.120.1
0.95
0.55
(A )
3
L
p
L
Zywvθ
E
0.95
0.55
o
7
o
0
θ
OUTLINE
VERSION
SOT401-1
IEC JEDEC EIAJ
REFERENCES
1999 Jun 0416
EUROPEAN
PROJECTION
ISSUE DATE
95-12-19
97-08-04
Page 17
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
“Data Handbook IC26; Integrated Circuit Packages”
our
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
UAA2068AHL
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jun 0417
Page 18
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
UAA2068AHL
integrated VCO for DECT
Suitability of surface mount IC packages for wave and reflow soldering methods
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJsuitablesuitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jun 0418
Page 19
Philips SemiconductorsProduct specification
Transmit chain and synthesizer with
integrated VCO for DECT
UAA2068AHL
NOTES
1999 Jun 0419
Page 20
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
199965
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands465008/01/pp20 Date of release: 1999 Jun 04Document order number: 9397 750 05841
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