Datasheet TMC2490A Datasheet (Fairchild Semiconductor)

www.fairchildsemi.com

TMC2490A

Multistandard Digital Video Encoder

Features

• All-digital video encoding

• Internal digital subcarrier synthesizer

• 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE
125M input format

• CCIR-624/SMPTE-170M compliant output

• Switchable chrominance bandwidth

• Switchable pedestal with gain compensation

• Pre-programmed horizontal and vertical timing

• 13.5 Mpps pixel rate

• Master or slave (CCIR656) operation

• MPEG interface

• Internal interpolation filters simplify output
reconstruction filters

• 10-bit D/A converters for video reconstruction

• Supports NTSC and PAL standards

• Closed-caption waveform insertion

• Simultaneous S-Video (Y/C) output

• Controlled edge rates

• Single +5V power supply

• 44 lead PLCC package

• Parallel and serial control interface

Applications

• Set-top digital cable television receivers

• Set-top digital satellite television receivers

• Studio parallel CCIR-601 to analog conversion

Description

The TMC2490A video encoder converts digital component
video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE
125M format) into a standard analog baseband television
(NTSC, NTSC-EIA, and all PAL standards) signal with a
modulated color subcarrier. Both composite (single lead) and
S-Video (separate chroma and luma) formats are active
simultaneously at all three analog outputs. Each video output
generates a standard video signal capable of driving a singly­or doubly-terminated 75 Ohm load.

The TMC2490A is intended for all non-Macrovision
encoder applications.

The TMC2490A is fabricated in a submicron CMOS
process and is packaged in a 44-lead PLCC. Performance is
guaranteed over the full 0 ° C to 70 ° C operating temperature
range.

Block Diagram

PIXEL DATA

PXCK

HSYNC

SELC

DEMUX AND

SYNC

EXTRACT

PD

7-0

VSYNC, B/T

PDC/CBSEL

LPF

INTERPOLATOR

4:2:2 TO 4:4:4

Y

DIGITAL

SYNC AND

BLANK

GENERATOR

SERIAL

PARALLEL

B-Y

R-Y

LPF

SUBCARRIER

SYNTHESIZER

SERIAL/PARALLEL CONTROL

SA

SA

0

1

ADR

MODULATOR

SDA
R/W

CHROMA

SCL

CS

INTER-

POLATION

FILTER

D

7-0

D

7-0

INTER-

POLATION

FILTER

GLOBAL

CONTROL

RESET

SER

10-BIT
D/A

10-BIT
D/A

10-BIT
D/A

REF

CHROMA

LUMA

COMPOSITE

V

REF

C

BYP

R

REF

65-2490(1)A-01

REV. 1.0.2 2/27/02

S-VIDEO

TMC2490A PRODUCT SPECIFICATION

Functional Description

The TMC2490A is a fully-integrated digital video encoder
with simultaneous composite and Y/C (S-Video) outputs,
compatible with NTSC, NTSC-EIA, and all PAL television
standards.

Digital component video is accepted at the PD port in 8-bit
parallel CCIR-601/656 format. It is demultiplexed into
luminance and chrominance components. The chrominance
components modulate a digitally synthesized subcarrier.
The luminance and chrominance signals are then separately
interpolated to twice the input pixel rate and converted to
analog signals by 10-bit D/A converters. They are also
digitally combined and the resulting composite signal is
output by a third 10-bit D/A converter.

The TMC2490A operates from a single clock at 27 MHz,
twice the system pixel rate. Programmable control registers
allow software control of subcarrier frequency and phase

C

parameters. Incoming YC
lated to YC

Internal control registers can be accessed over a standard
8-bit parallel microprocessor port or a 2-pin (clock and data)
serial port.

C

444 format for encoding.

B

R

Sync Generator

The TMC2490A operates in master or slave mode. In slave
mode, it extracts its horizontal and vertical sync timing and
field information from the CCIR-656 SAV (Start of Active
Video) and EAV (End of Active Video) signal in the incom­ing data stream. In master mode, it generates a 13.5 MHz
timebase and sends line and field synchronizing signals to
the host system.

Horizontal and vertical synchronization pulses in the analog
output are digitally generated by the TMC2490A with con­trolled rise and fall times on all sync edges, the beginning
and end of active video, and the burst envelope.

MSB LSB

PD

7

PD

7

422 digital video is interpo-

B

R

C

(n) PD

B

Y (n) PD

Chroma Modulator

A digital subcarrier synthesizer generates the reference for
a quadrature modulator, producing a digital chrominance
signal. The chroma bandwidth may be programmed to
650 kHz or 1.3 MHz.

Interpolation Filters

Interpolation filters on the luminance and chrominance
signals double the pixel rate to 27Mpps before D/A conver­sion. This low-pass filtering and oversampling process
reduces sin(x)/x roll-off, and greatly simplifies the analog
reconstruction filter required after the D/A converters.

D/A Converters

Analog outputs of the TMC2490A are driven by three 10-bit
D/A converters, The outputs drive standard video levels into

37.5 or 75 Ohm loads. An internal voltage reference is used
to provide reference current for the D/A converters. An
external fixed or variable voltage reference source can also
be used. The video signal levels from the TMC2490A may
be adjusted to overcome the insertion loss of analog low-pass
output filters by varying R

REF

or V

REF

.

Parallel and Serial Microprocessor Interfaces

The parallel microprocessor interface employs 11 pins.
These are shared with the serial interface. A single pin, SER,
selects between the two interface modes.

In parallel interface mode, one address pin is decoded to
enable access to the internal control register and its pointer.
Controls are reached by loading a desired address through
the 8-bit D
write) for that address. The control register address pointer
auto-increments to address 22h and then remains there.

A 2-line serial interface is also provided on the TMC2490A
for initialization and control. The same set of registers
accessed by the parallel port is available to the serial port.

The RESET
registers to their initialized conditions, disables the analog

0

0

outputs, and places the encoder in a reset mode. At the rising
edge of RESET
NTSC-M format.

port, followed by the desired data (read or

7-0

pin sets all internal state machines and control

, the encoder is automatically initialized in

PD

7

PD

7

Figure 1. Pixel Data Format

2

C

(n) PD

R

Y (n+1) PD

0

0

REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Pin Assignments

SCL/CS

SER

D
D
D
D

GND

D
D
D
D

/ADR

0

SDA/R/W

SA

SA1PD0GND

65432

7

8

9

7

10

6

11

5

12

4

13

14

3

15

2

16

1

17

0

1819202122232425262728

HSYNC

VSYNC,T/B

CBSEL,PDC

VDDPD1PD2PD3PD4PD

1

TMC2490A

DD

V

SELC

RESET

4443424140

GND

PXCK

DD

V

5

39

38

37

36

35

34

33

32

31

30

29

REFRREF

V

Pin Descriptions

Pin Name Pin Number Value Pin Function Description

Clock

PXCK 25 TTL

Data Input Port

PD

7-0

38–44, 3 TTL

Microprocessor Interface

D

7-0

9–12, 14–17 TTL

RESET 22 TTL

SA

1

SA

, ADR 5 TTL

0

4 TTL

Pixel Clock Input. This 27.0 MHz clock is internally divided by 2

to generate the internal pixel clock. PXCK drives the entire
TMC2490A, except the asynchronous microprocessor interface.
All internal registers are strobed on the rising edge of PXCK.

Pixel Data Inputs. Video data enters the TMC2490A on

PD

(Figure 1).

7-0

Data I/O, General Purpose I/O, Chroma Input Port. When SER

is HIGH, all control parameters are loaded into and read back
over this 8-bit port. When SER = LOW, D
composite sync output, D
porch, D

are General Purpose Outputs, and D

2-5

Purpose Inputs.

Master Reset Input. Bringing RESET LOW forces the internal

state machines to their starting states and disables all outputs.

Serial/Parallel Port Select. When SER

conjunction with SA

selects one of four addresses for the

0

TMC2490A.

Serial/Parallel Port Select. When SER is LOW, SA

conjunction with SA

selects one-of-four addresses for the

1

TMC2490A. When SER is HIGH, this control governs whether the
parallel microprocessor interface selects a table address or
reads/writes table contents.

PD

6

PD

7

V

DD

GND
CHROMA
V

DDA

C

BYP

LUMA
GND
COMPOSITE
GND

65-2490(1)A-02

can serve as a

0

outputs a burst flag during the back

1

are General

6-7

is LOW, SA

in

1

in

0

3

4

TMC2490A PRODUCT SPECIFICATION

Pin Descriptions

Pin Name Pin Number Value Pin Function Description

SDA, R/W

SCL, CS

SER 8 TTL

Outputs

CHROMA 35 1.35V p-p Chrominance-only Video. Analog output of chrominance D/A

COMPOSITE 30 1.35V p-p Composite NTSC/PAL Video. Analog output of composite D/A

LUMA 32 1.35V p-p Luminance-only Video. Analog output of luminance D/A

Analog Interface

C

BYP

R

REF

V

REF

SYNC Out

HSYNC 18 TTL

VSYNC

CBSEL

SELC 21 TTL

Power Supply

V

GND 2, 13, 24, 29,

V

, T/B 19 TTL

, PDC 20 TTL

DD

DDA

(continued)

6 R-Bus/TTL Serial Data/Read/Write Control. When SER is LOW, SDA is the

data line of the serial interface. When SER is HIGH, the pin is the
read/write control for the parallel interface. When R/W
LOW, the microprocessor can write to the control registers over
D

. When R/W

7-0

contents of any selected control register over D

7 R-Bus/TTL Serial Clock/Chip Select. When SER is LOW, SCL is the clock

line of the serial interface. When SER is HIGH, the pin is the chip
select control for the parallel interface. When CS
microprocessor interface port, D
and ignored. When CS is LOW, the microprocessor can read or
write parameters over D

Serial/Parallel Port Select. When LOW, the 2-line serial

interface is activated. Pins 5, 6, and 7 function as SA
SCL respectively. When HIGH, the parallel interface port is active
and pins 5, 6, and 7 function as ADR, R/W, and CS respectively.

converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.

converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.

converter. Maximum output is 1.35 volts peak-to-peak into a
doubly terminated 75 Ohm load.

33 0.1 µ F

28 787 Ω

27 +1.235V Voltage Reference Input. External voltage reference input,

1, 23, 26, 37 +5V

0.0V

31, 36

34 +5V

Reference Bypass Capacitor. Connection point for 0.1 µ F

decoupling capacitor to V

Current-setting Resistor. Connection point for external current-

setting resistor for D/A converters. The resistor is connected
between R
proportional to the value of R

internal voltage reference output, nominally 1.235 V.

Horizontal Sync Output.

Vertical Sync Output or Odd/Even Field ID Output .

Pixel Data Phase Output or Video Blanking Output.

Luma/Chroma MUX Control.

Power Supply. Positive power supply.

Ground.

Analog Power Supply. Positive power supply.

is HIGH and CS is LOW, it can read the

7-0

is HIGH, the

, is set to HIGH impedance

7-0

.

7-0

at pin 34.

DD

and GND. Output video levels are inversely

REF

.

REF

.

and CS are

, SDA, and

0

REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Control Registers

The TMC2490A is initialized and controlled by a set of reg­isters which determine the operating modes.

An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line

Table 1. Control Register Map

Reg Bit Mnemonic Function

TMC2490A Identification Registers (Read only)

00 7-0 PARTID2 Reads back 97h

01 7-0 PARTID1 Reads back 24h

02 7-0 PARTID0 Reads back 90h (91h)

03 7-0 REVID Silicon revision #

Global Control Register

04 7 MASTER Master Mode

04 6 NGSEL NTSC Gain Select

04 5 YCDELAY Luma to chroma delay

04 4 RAMPEN Modulated ramp enable

04 3 YCDIS LUMA, CHROMA disable

04 2 COMPDIS COMPOSITE disable

04 1-0 FORMAT Television standard select

Video Output Control Register

05 7 PALN Select PAL-N Subcarrier

05 6 BURSTF

05 5 CHRBW Chroma bandwidth select

05 4 SYNCDIS Sync pulse disable

05 3 BURDIS Color burst disable

05 2 LUMDIS Luminance disable

05 1 CHRDIS Chrominance disable

05 0 PEDEN Pedestal enable

Field ID Register

06 7-6 Reserved Program LOW

06 5-3 FIELD Field ID (Read only)

06 2-0 Reserved Program LOW

Reserved Registers

07-0D7-0 Reserved Program LOW

Burst flag disable

serial interface port. The parallel port, D
pins CS
SDA and SCL.

Notes:

1. For each register listed above, all bits not specified are

, R/W, and ADR. The serial port is controlled by

Reg Bit Mnemonic Function

General Purpose Port Register

0E 7 PORT7-6 General purpose Inputs

0E 6 PORT5-2 General purpose Outputs

0E 1 BURSTF Burst Flag Output

0E 0 CSYNC Composite Sync Output

General Control Register

0F 7 PED21 VBI Pedestal Enable

0F 5 VSEL Vertical Sync Select

0F 4 CBSEL CBSEL/PDC Pin Function

0F 3 VBIEN VBI Pixel Data Enable

0F 1-0 HDSEL HSYNC Delay

Reserved Registers

10-1F7-0 Reserved May be left unprogrammed

Closed-Caption Insertion Registers

20 7-0 CCD1 First Byte of CC Data

21 7-0 CCD2 Second Byte of CC Data

22 7 CCON Enable CC Data Packet

22 6 CCRTS Request To Send Data

22 5 CCPAR Auto Parity Generation

22 4 CCFLD CC Field Select

22 3-0 CCLINE CC Line Select

reserved and should be set to logic LOW to ensure proper
operation.

, is governed by

7-0

REV. 1.0.2 2/27/02

5

TMC2490A PRODUCT SPECIFICATION

Table 2. Default Register Values on Reset

Reg Dflt Reg Dflt Reg Dflt Reg Dflt Reg Dflt

00 97 04 00 08 00 0C 00 20 80

01 24 05 01 09 00 0D 00 21 80

02 90(91) 06 00 0A 00 0E 00 22 00

03 xx 07 00 0B 00 0F F2

Control Register Definitions

Reg Bit Name Description

00 7–0 PARTID2 Reads back 97h

01 7–0 PARTID1 Reads back 24h

02 7–0 PARTID0 Reads back 90h (91h)

03 7–0 REVID Reads back a value corresponding to the revision letter of the silicon.

Global Control Register (04)

76543210

MASTER NGSEL YCDELAY RAMPEN YCDIS COMPDIS FORMAT

Reg Bit Name Description

04 7 MASTER Master Mode. When MASTER = 1, the encoder generates its own video

timing and outputs signals VSYNC (or T/B), HSYNC, SELC, and PDC (or
CBSEL). When MASTER = 0, the TMC2490A extracts timing from the
embedded EAV codeword in the video datastream and optionally outputs
signals VSYNC (or T/B), HSYNC, SELC, and PDC (or CBSEL).

04 6 NGSEL NTSC Gain Selection.

04 5 YCDELAY Luma to chroma delay. When HIGH, the luminance path within the

TMC2490A is delayed by one PXCK period. The delay applies to both
COMPOSITE and LUMA outputs and may be used to compensate for group
delay variation of external filters. When LOW, luminance and chrominance
have the same latency.

04 4 RAMPEN Modulated ramp enable. When HIGH, the TMC2490A outputs a modulated

ramp test signal. When LOW, incoming digital video is encoded.

04 3 YCDIS LUMA, CHROMA disable. When HIGH, the LUMA and CHROMA outputs

are disabled. Set LOW for normal enabled operation.

04 2 COMPDIS COMPOSITE disable. When HIGH, the COMPOSITE output is disabled.

Set LOW for normal enabled operation.

04 1–0 FORMAT Television standard select. Selects basic H&V timing parameters and

subcarrier frequency. Pedestal level and chrominance bandwidth are
independently programmed.

0 0 NTSC
0 1 PAL-B,G,H,I,N
1 0 PAL-M
1 1 Reserved

REV. 1.0.2 2/27/02 6

PRODUCT SPECIFICATION TMC2490A

Control Register Definitions (continued)

Video Output Control Register (05)

76543210

PALN BURSTF CHRBW SYNCDIS BURDIS LUMDIS CHRDIS PEDEN

Reg Bit Name Description

05 7 PALN Select PAL-N Subcarrier. When HIGH, selects PAL-N subcarrier

frequency. When LOW, the encoder produces the PAL-B,G,H,I subcarrier.
Program LOW for NTSC and PAL-M video.

05 6 BURSTF Burst flag disable. When BURSTF is LOW, a clamp gate signal is

produced on the D1 output and register 0E bit 1.

05 5 CHRBW Chroma bandwidth select. When LOW, the chrominance bandwidth is

±650 kHz. When HIGH, the chrominance bandwidth is ±1.3 MHz.

05 4 SYNCDIS Sync pulse disable. When HIGH, horizontal and vertical sync pulses on the

COMPOSITE video output are suppressed (to blanking level). Color burst,
active video, and the CSYNC
composite video operation.

05 3 BURDIS Color burst disable. When HIGH, color burst is suppressed to the blanking

level. Set LOW for normal operation.

05 2 LUMDIS Luminance disable. When HIGH, incoming Y values are forced to black

level. Color burst, CHROMA, and sync are not affected. Set LOW for normal
operation.

05 1 CHRDIS Chrominance disable. When HIGH, incoming color components CB and

CR are suppressed, enabling monochrome operation. Output color burst is
not affected. Set LOW for normal color operation.

05 0 PEDEN Pedestal enable. When LOW, black and blanking are the same level for

ALL lines. When HIGH, a 7.5 IRE pedestal is inserted into the output video
for NTSC and PAL-M lines 23-262 and 286-525 only. Chrominance and
luminance gain factors are adjusted to keep video levels within range.
PEDEN is valid for NTSC and PAL-M only and should be LOW for all other
formats.

output remain active. Set LOW for normal

Field Data Register (06)

76543210

Reserved FIELD Reserved

Reg Bit Name Description

06 7–6 Reserved Program LOW.

06 5–3 FIELD Field ID (Read only). A value of 000 corresponds to field 1 and 111

corresponds to field 8.

06 2–0 Reserved Program LOW.

7

TMC2490A PRODUCT SPECIFICATION

Control Register Definitions (continued)

Reserved Registers (07–0D)

76543210

Reserved

Reg Bit Name Description

07–0D7–0 Reserved Program LOW.

General Purpose Port Register (0E)

76543210

PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 BURSTF CSYNC

Reg Bit Name Description

0E 7–6 PORT7–6 General purpose Inputs. When in serial control mode, these register read-

only bits indicate the state present on data port pins D7 and D6.

0E 5–2 PORT5–2 General purpose Outputs. When in serial control mode or when reading

register 0E in parallel control mode, these register read/write bits drive data
pins D5–D2 to the state contained in the respective register bits.

0E 1 BURSTF Burst Flag Output. Produces Burst Flag on data pin D1 when in serial

0E 0 CSYNC Composite Sync Output. Produces Composite Sync on data pin D0 when

control mode, or when reading register 0E.

in serial control mode, or when reading register 0E.

REV. 1.0.2 2/27/02 8

PRODUCT SPECIFICATION TMC2490A

Control Register Definitions (continued)

General Control Register (0F)

76543210

PED21 Reserved VSEL CBSEL VBIEN Reserved

Reg Bit Name Description

0F 7 PED21 VBI Pedestal Enable. When HIGH and FORMAT is 00 (NTSC) or 10

(PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no
pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only
and should be LOW for all other formats.

0F 6 Reserved Program HIGH.

0F 5 VSEL Vertical Sync Select. When LOW, the TMC2490A outputs a traditional

vertical sync on VSYNC
identification on the VSYNC

0F 4 CBSEL CBSEL/PDC pin function. When CBSEL = 0, the PDC signal is produced

on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced
on the CBSEL/PDC pin.

0F 3 VBIEN VBI Pixel Data Enable. When VBIEN = 0, the vertical interval lines are

blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines.

0F 2 Reserved Program LOW.

0F 1–0 HDEL Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the

PD port.

HDEL Result

00 H and V syncs are aligned with luminance pixel 735 (Y735)
01 H and V syncs are aligned with Blue color difference pixel 735

(Cb736)
10 H and V syncs are aligned with luminance pixel 736 (Y736)
11 H and V syncs are aligned with Red color difference pixel 735

(Cr736)

. When HIGH, the chip outputs odd/even field

pin, with 0 denoting an odd field.

Refer to Figure 2a, HDEL Timing

Reserved Registers (10–1F)

76543210

Reserved

Reg Bit Name Description

10–1F7–0 Reserved May be left unprogrammed

9

PRODUCT SPECIFICATION TMC2490A

Control Register Definitions (continued)

Closed-Caption Insertion (20)

76543210

CCD1

Reg Bit Name Description

20 7–0 CCD1 First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an

ODD Parity bit if CCPAR is HIGH.

Closed-Caption Insertion (21)

76543210

CCD2

Reg Bit Name Description

21 7–0 CCD2 Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by

an ODD Parity bit if CCPAR is HIGH.

Closed-Caption Insertion (22)

76543210

CCON CCRTS CCPAR CCFLD CCLINE

Reg Bit Name Description

22 7 CCON Enable CC Data Packet. Command the CC data generator to send either

CC data or a NULL byte whenever the specified line is transmitted.

22 6 CCRTS Request To Send Data. This bit is set HIGH by the user when bytes 20 and

21 have been loaded with the next two bytes to be sent. When the encoder
reaches the falling edge of the HSYNC preceding the line specified in bits
4-0 of this register, data will be transferred from registers 20 and 21, and
RTS will be reset LOW. A new pair of bytes may then be loaded into
registers 20 and 21. If CCON = 1 and CCRTS = 0 when the CC line is to be
sent, NULL bytes will be sent.

22 5 CCPAR Auto Parity Generation. When set HIGH, the encoder replaces the MSB of

bytes 20 and 21 with a calculated ODD parity. When set LOW, the CC
processor transmits the 16 bits exactly as loaded into registers 20 and 21.

22 4 CCFLD CC Field Select. When LOW, CC data is transmitted on the selected line of

ODD fields. When HIGH, it is sent on EVEN fields.

22 3–0 CCLINE CC Line Select. Defines (with an offset) the line on which CC data is

transmitted.

10

PRODUCT SPECIFICATION TMC2490A

General Purpose Port

The TMC2490A provides a general purpose I/O port for sys­tem utility functions. Input, output, and sync functions are
implemented. Register 0E is the General Purpose Register.

Full functionality is provided when the encoder is in Serial
control mode (SER
able in parallel interface mode (SER = HIGH).

General Purpose Input (serial mode only)

Bits 7 and 6 of Register 0E are general purpose inputs. When
the encoder is in serial control mode, data bits D
mirrored to these register locations. When Register 0E is
read, the states of bits 7 and 6 reflect the TTL logic levels
present on D7 and D6, respectively, at the time of read com­mand execution. Writing to these bits has no effect.

This function is not available when the encoder is in parallel
control mode.

General Purpose Output

Register 0E read/write bits 5-2 are connected to pins D
respectively, when the encoder is in serial control mode. The
output pins continually reflects the values most recently writ­ten into register 0E (1 = HIGH, 0 = LOW). Note that these
pins are always driven outputs when the encoder is in serial
control mode.

When register 0E is read, these pins report the values previ­ously stored in the corresponding register bits, i.e., it acts as
a read/write register. When the encoder is in parallel control
mode, this reading produces the output bit values on the cor­responding data pins, just as in the serial control mode. How­ever, the values are only present when reading register 0E.
The controller can command a continuous read on this regis­ter to produce continuous outputs from these pins.

Burst Flag and Composite Sync (output/
read-only)

Register 0E bit 1 is associated with the encoder burst flag. It
is a 1 (HIGH) from just before the start of the color burst to
just after the end of the burst. It is a 0 (LOW) at all other
times.

Register 0E bit 0 outputs the encoder composite sync status.
It is a 0 (LOW) during horizontal and vertical sync tips. It is
a 1 (HIGH) at all other times.

= LOW). Most of the functions are avail-

and D6 are

7

,

5-2

In serial control mode, these same data output pins (D
always act as a burst flag and composite sync TTL outputs,
the conditions of the serial control notwithstanding. The
states of the flags may be read over the serial port, but due to
the low frequency of the serial interface, it may be difficult to
get meaningful information.

1-0

)

Pixel Interface

The TMC2490A interfaces with an 8-bit 13.5 Mpps (27
MHz) video datastream. It will automatically synchronize
with embedded Timing Reference Signals, per CCIR-656.
It also includes a master sync generator on-chip, which can
produce timing reference outputs.

CCIR-656 Mode

When operating in CCIR-656 Mode (MASTER = 0), the
TMC2490A identifies the SAV and EAV 4-byte codewords
embedded in the video datastream to derive all timing. Both
SAV and EAV are required.

MASTER Mode

When in MASTER Mode (MASTER = 1), the Encoder
produces its own timing, and provides HSYNC, VSYNC (or
B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source.

SELC Output

The SELC output toggles at 13.5 MHz (1/2 the pixel rate),
providing a phase reference for the multiplexed luma/chroma
CCIR-656 datastream. It is HIGH during the rising edge of
the clock intended to load chroma data. This is useful when
interfacing with a 16-bit data source, and can drive a Y/C
multiplexer.

CBSEL Output

The CBSEL output identifies the CB element of the CB-Y-

-Y CCIR-656 data sequence. It is HIGH during the rising

C

R

edge of the clock to load C
tionally swapping the CB and CR color components when
operating in MASTER mode and reading data from a
framestore.

PDC Output

The PDC output is a blanking signal, indicating when the
encoder expected to receive pixel data. When PDC is HIGH,
the incoming PD is encoded.

data. This will prevent uninten-

B

These register bits may be read at any time over either the
serial or parallel control port. Since they are dynamic, their
states will change as appropriate during a parallel port read.
In fact, if the parallel control port is commanded to read reg­ister 0E continually, the pins associated with these bits
behave as burst flag and composite sync timing outputs.

REV. 1.0.2 2/27/02 11

TMC2490A PRODUCT SPECIFICATION

PXCK

PD

CBSEL

HYSNC

C

B732Y732CR732Y733

7-0

1464
1472

C

B734Y734CR734Y735CB736Y736

HDEL = 00

HDEL = 01

HDEL = 10

1592
1600

C

R736CB800Y800CR800Y801CB801CR856Y857

HDEL = 11

0

1727

0

1715

CB0Y0CR0Y1C

625-line
525-line

B2

65-2490A-03

Figure 2a. HDEL TIming

1430
1435

PXCK

PD

7-0

HSYNC (Output)

HDEL = 2

PDC

t

DO

1440
1440

FF FF00 00 FV

1464
1472

1

t

DO

t

HS

1724
1712

00 00 FV0CB0Y

SAVEAV

Figure 2b. CCIR-656 Horizontal Interval Timing Detail

1727
1715

0
0

t

t

HP

SP

0

17

3

625-line
525-line

t

DO

65-2490A-04

PXCK

PD

HSYNC (Output)

HDEL = 2

PDC

1430
1435

7-0

t

DO

1440
1440

1464
1472

Figure 3. Master Mode Horizontal Interval Timing Detail

Horizontal and Vertical Timing

Horizontal and vertical video timing in the TMC2490A is
preprogrammed for line-locked systems with a 2x pixel
clock of 27.0 MHz.

Table 3 and Table 4 show timing parameters for NTSC and
PAL standards and the resulting TMC2490A analog output
timing. The user provides exactly 720 pixels of active video
per line. In master mode, the TMC2490A precisely controls
the duration and activity of every segment of the horizontal
line and vertical field group. In external sync slave mode, it
holds the end-of-line blank state (e.g. front porch for active
video lines) until it receives the next horizontal sync signal.

1727
171500

t

t

H

S

CB0Y

0

t

DO

t

HS

17

3

65-2490A-05

In CCIR-656 slave mode, it likewise holds each end-of-line
blank state until it receives the next end of active video
(EAV) signal embedded in the incoming data stream.

The vertical field group comprises several different line
types based upon the Horizontal line time.

H = (2 x SL) + (2 x SH) [Vertical sync pulses]

= (2 x EL) + (2 x EH) [Equalization pulses]

SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The chip does this automatically, requiring
no user intervention. The TMC2490A digitally defines

625-line
525-line

t

DO

12 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

slopes compatible with SMPTE 170M NTSC or CCIR
Report 624 PAL on all vital edges:

1. Sync leading and trailing edges.

2. Burst envelope.

3. Active video leading and trailing edges.

4. All vertical interval equalization pulse and sync edges.

Table 3. Horizontal Timing Standards and Actual Values for 60 fps Video Standards (µs)

NTSC (SMPTE 170M) PAL-M (CCIR 624)

Parameter

Front porch FP 1.4 1.5 1.6 1.27 2.22 1.53

Horiz. Sync SY 4.6 4.7 4.8 4.6 4.7 4.8 4.74

Breezeway BR 0.608 0.9 1.1 1.3 0.59 (NTSC)

Color Burst BU 2.235 2.514 2.794 2.237 2.517 2.797 2.31

Color Back porch CBP 1.378 0.503 2.363 1.65 (NTSC)

Blanking BL 10.5 10.7 11.0 10.7 10.9 11.1 10.8

Active Video VA 52.56 52.86 53.06 52.46 52.66 52.86 52.633

Line Time H 63.556 63.556 63.557

Equalization HIGH EH 29.5 29.5 29.47

Equalization LOW EL 2.3 2.3 2.31

Sync HIGH SH 4.7 4.7 4.67

Sync LOW SL 27.1 27.1 27.13

Sync rise and fall
times

Min Nom Max Min Nom Max TMC2490A

1.04 (PAL-M)

0.89 (PAL-M)

140±20ns <250 ns 135ns

Table 4. Horizontal Timing Standards and Actual Values for 50 fps Video Standards (µs)

PAL-B,G,H,I (CCIR 624) PAL-N (CCIR 624)

Parameter

Front porch FP 1.2 1.5 1.8 1.2 1.5 1.8 1.57

Horiz. Sync SY 4.5 4.7 4.9 4.5 4.7 4.9 4.74

Breezeway BR 0.6 0.9 1.2 0.6 0.9 1.2 0.89

Color Burst BU 2.030 2.255 2.481 2.233 2.513 2.792 2.3

Color Back porch CBP 2.654 2.387 2.3

Blanking BL 11.7 12.0 12.3 11.7 12.0 12.3 1.8

Active Video VA 51.7 52.0 52.3 51.7 52.0 52.3 52.2

Line Time H 64 64 64.0

Equalization HIGH EH 29.65 29.65 29.63

Equalization LOW EL 2.35 2.35 2.37

Sync HIGH SH 4.7 4.7 4.67

Sync LOW SL 27.3 27.3 27.3

Sync rise and fall
times

Min Nom Max Min Nom Max TMC2490A

250±50

ns

200±100

ns

250

13

TMC2490A PRODUCT SPECIFICATION

H

H/2

BURST

CBP

SLEH

BUBRSYFPVA

VA

24318B

EL SH

24319A

Figure 4. Horizontal Blanking Interval Timing Figure 5. Vertical Sync and Equalization Pulse Detail

FIELDS 1 AND 3

524

525

10 … 19 20 21 22

EE EE EE SS SS SS EE EE EB

UVVUVV

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

262 263 273 … 282 283 284 285

UVV UVE EE EE ES SS SS SE EE EE EB

FIELDS 2 AND 4

264 265 266 267 268 269 270 271 272

UBB UBB UBB UVV UVV

UBB UBB UVV UVV UVV

24492B

Figure 6. NTSC Vertical Interval

14 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Table 6. NTSC Field/Line Sequence and Identification

Field 1, FID = 00 Field 2, FID = 01 Field 3, FID = 10 Field 4, FID = 11

Line ID Line ID Line ID Line ID

1 EE 264 EE 1 EE 264 EE

2 EE 265 EE 2 EE 265 EE

3 EE 266 ES 3 EE 266 ES

4 SS 267 SS 4 SS 267 SS

5 SS 268 SS 5 SS 268 SS

6 SS 269 SE 6 SS 269 SE

7 EE 270 EE 7 EE 270 EE

8 EE 271 EE 8 EE 271 EE

9 EE 272 EB 9 EE 272 EB

10 UBB 273 UBB 10 UBB 273 UBB

……………………

20 UBB 282 UBB 20 UBB 282 UBB

21 UVV 283 UVV 10 UVV 273 UVV

……………………

262 UVV 524 UVV 262 UVV 524 UVV

263 UVE 525 UVV 263 UVE 525 UVV

EE Equalization pulse EB Equalization broad pulse
SE Half-line vertical sync pulse, half-line equalization pulse UBB Black and Burst
SS Vertical sync pulse UVV Active video
ES Half-line equalization pulse, half-line vertical sync pulse UVE Half-line video, half-line equalization pulse

Note:

1. VBB lines are changed to UVV (Active Video) when VBIEN = 1.

1

15

TMC2490A PRODUCT SPECIFICATION

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

1247

UVV -BB UBB … UBB UVV UVV UVV UVV-VE

309

UVV EB UBB UBB … UBB UBB UVV UVV-VV

FIELDS 1 AND 5

1249 1 2 3 4 5

EE EE SS SS SE EE EE

FIELDS 2 AND 6

311 312 313 314 315 316 317 318

EE EE ES SS SS EE EE

67… 22 23 24 25 261248

319 320 … 334 335 336 337310

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

622

-VV UBB UBB … UBB UVV UVV UVV UVV-VE

934

UVV EB -BB UBB … UBB UBB

FIELDS 3 AND 7

624 625 626 627 628 629 630

EE EE SS SS SE EE EE

FIELDS 4 AND 8

936 937 938 939 940 941 942 943

EE EE ES SS SS EE EE

631

632 … 647 648 649 650 651623

944 945 … 959 960 961 962935

Figure 7. PAL-B,G,H,I,N Vertical Interval

UVV UVVUVV

24495B

REV. 1.0.2 2/27/02 16

PRODUCT SPECIFICATION TMC2490A

Table 7. PAL-B,G,H,I,N Field/Line Sequence and Identification

Fields 1 and 5
FID = 000, 100

Line ID Line ID Line ID Line ID

1 SS 313 ES 626 SS 938 ES

2 SS 314 SS 627 SS 939 SS

3 SE 315 SS 628 SE 940 SS

4 EE 316 EE 629 EE 941 EE

5 EE 317 EE 630 EE 942 EE

6 -BB 318 EV 631 UBB 943 EB

7 UBB 319 UBB 632 UBB 944 -BB

8 UBB 320 UBB 633 UBB 945 UBB

……………………

22 UBB 335 UBB 647 UBB 960 UBB

23 UVV 336 UVV 648 UVV 961 UVV

……………………

308 UVV 621 UVV 933 UVV 1246 UVV

309 UVV 622 -VV 934 UVV 1247 UVV

310 -VV 623 -VE 935 UVV 1248 -VE

311 EE 624 EE 936 EE 1249 EE

312 EE 625 EE 937 EE 1250 EE

EE Equalization pulse UBB Black and Burst
SE Half-line vertical sync pulse, half-line equalization pulse UVV Active video
SS Vertical sync pulse -BB Blank line with color burst suppression
ES Half-line equalization pulse, half-line vertical sync pulse -VV Active video with color burst suppressed
EB Equalization broad pulse -VE Half-line video, half-line equalization pulse,

Notes:

1. VBB lines are changed to UVV (Active Video) when VBIEN = 1.

2. -BB lines are changed to -VV (Active Video, Burst Suppressed) when VBIEN = 1.

Fields 2 and 6
FID = 001, 101

Fields 3 and 7
FID = 010, 110

1

color burst suppressed

Fields 4 and 8
FID = 011, 111

2

17

TMC2490A PRODUCT SPECIFICATION

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

521

UVV EE EE -BB -BB UBB … UBB UVVUVV

259

UVV EE EB -BB UBB … UBB UVV UVV-VE

FIELDS 1 AND 5

523 524 525 1 2 3 4

EE EE EE SS SS SS EE

FIELDS 2 AND 6

261 262 263 264 265 266 267

EE EE ES SS SS SE EE

789… 17 18522

56

270 271 … 279 280 281260

268 269

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

COMPOSITE

SYNC

HSYNC

VSYNC

B/T

521

UVV EE EE -BB -BB UBB … UBB UVV-VV

259

258

UVV EE EB -BB UBB … UBB UVV UVV-VE

260

-VV

FIELDS 3 AND 7

523 524 525 1 2 3 4

EE EE EE SS SS SS EE

FIELDS 4 AND 8

261 262 263 264 265 266 267

EE EE ES SS SS SE EE

Figure 8. PAL-M Vertical Interval

789… 17 18522

56

270 271 … 279 280 281

268 269

24496B

REV. 1.0.2 2/27/02 18

PRODUCT SPECIFICATION TMC2490A

Table 8. PAL-M Field/Line Sequence and Identification

Field 1 and 5

FID = 000, 100

Line ID Line ID Line ID Line ID

1 SS 263 ES 1 SS 263 ES

2 SS 264 SS 2 SS 264 SS

3 SS 265 SS 3 SS 265 SS

4 EE 266 SE 4 EE 266 SE

5 EE 267 EE 5 EE 267 EE

6 EE 268 EE 6 EE 268 EE

7 -BB 269 EB 7 -BB 269 EB

8 -BB 270 -BB 8 UBB 270 -BB

9 UBB 271 UBB 9 UBB 271 UBB

……………………

17 UBB 279 UBB 17 UBB 279 UBB

18 UVV 280 UVV 18 UVV 280 UVV

……………………

258 UVV 521 UVV 258 UVV 521 UVV

259 UVV 522 -VV 259 -VV 522 UVV

260 -VE 523 EE 260 -VE 523 EE

261 EE 524 EE 261 EE 524 EE

262 EE 525 EE 262 EE 525 EE

EE Equalization pulse UBB Black and Burst
SE Half-line vertical sync pulse, half-line equalization pulse UVV Active video
SS Vertical sync pulse -BB Blank line with color burst suppression
ES Half-line equalization pulse, half-line vertical sync pulse -VV Active video with color burst suppressed
EB Equalization broad pulse UVV Half-line black, half-line video

-VEHalf-line video, half-line equalization pulse,
color burst suppressed

Field 2 and 6

FID = 001, 101

Field 3 and 7

FID = 010, 110

Field 4 and 8

FID = 011, 111

1

2

Notes:

1. VBB lines are changed to UVV (Active Video) when VBIEN = 1

2. -BB lines are changed to -VV (Active Video, Burst Suppressed) when VBIEN = 1

Subcarrier Generation and Synchronization

The color subcarrier is generated by an internal digital
frequency synthesizer. The subcarrier synthesizer gets its
frequency and phase values preprogrammed into the
TMC2490A.

In Master Mode, the subcarrier is internally synchronized on
field 1 of the eight-field sequence to establish and maintain a
specific relationship between the leading edge of horizontal
sync and color burst phase (SCH). Proper subcarrier phase is
maintained through the entire eight field set, including the 25
Hz offset in PAL-N/B/I systems. The subcarrier is reset to
the phase values found in Table 9.

REV. 1.0.2 2/27/02 19

SCH Phase Control

SCH refers to the timing relationship between the 50% point
of the leading edge of horizontal sync and the first positive or
negative zero-crossing of the color burst subcarrier refer­ence. In PAL, SCH is defined for line 1 of field 1, but since
there is no color burst on line 1, SCH is usually measured at
line 7 of field 1. The need to specify SCH relative to a partic­ular line in PAL is due to the 25 Hz offset of PAL subcarrier
frequency. Since NTSC has no such 25 Hz offset, SCH
applies to all lines.

TMC2490A PRODUCT SPECIFICATION

Table 9. Subcarrier and Color Burst Reset
Values

NTSC PAL-M

Digital field: 1 1 1

Line number: 4 4 1

Subcarrier
phase reset
value:

Resultant color
burst phase:

Note:

1. Line numbering is in accordance with Figure 6, Figure 7,
and Figure 8. Subcarrier and color burst phase are relative
to the horizontal reference of the line specified above.

180° 0° 0°

0° +135° +135°

B,G,H,I,N

Table 10. Standard Subcarrier Parameters

Horizontal

Standard

NTSC 15.734266 3.579545455

PAL B,G,H,I 15.625000 4.43361875

PAL-M 15.734266 3.57561189

PAL-N 15.625000 3.58205625

Frequency (KHz)

Subcarrier

Frequency (MHz)

PAL-

Luminance Processing

During horizontal and vertical blanking, the luma processor
generates blanking levels and properly timed and shaped
sync and equalization pulses. During active video, it captures
and rescales the incoming Y components and adds the results
to the blank level to complete a proper monochrome televi­sion waveform, which is then upsampled to drive the luma
D/A and the composite adder.

For NTSC-EIA (5:2 white:sync, no black pedestal), the over­all luma input-to-output equation for 0<Y<255 is:

luma out (IRE, relative to blank) = (Y - 16) * 100/219

For NTSC and PAL-M (5:2, with 7.5 IRE pedestal), the
equation becomes:

luma out (IRE, relative to blank) = (Y - 16) * 92.5/219 + 7.5

For all 625-line PAL standards (7:3, no pedestal), the equa­tion becomes:

luma out (mV, relative to blank) = (Y-16) * 700/219

Since Y=0 and Y=255 are reserved values in CCIR-601,
results in the luma D/A outputting black, i.e., 0mV or 0 IRE
without pedestal, 7.5 IRE with pedestal. External compo­nents are needed to bias the blanking/black level to 0mV/0
IRE. The values given in Table 11 and Table 12 reflect a
biased output where the blanking level is at 0mV/0 IRE.

Table 11. Luminance Input Codes

PD

Input

7-0

255 FF Reserved 0 7.5 0

254 FE 108.7 108 761

235 EB 100% white 100 100 700

16 10 Black 0 7.5 0

1 01 -6.9 1.2 -48

0 00 Reserved 0 7.5 0

Luma Level

(CCIR-601)

NTSC, PAL-M Luma Level (IRE)

PAL-B,G,H,I,N

Luma Level (mV)Dec Hex PEDEN = 0 PEDEN = 1

Table 12. D/A Converter and Analog Levels

NTSC, PAL-M NTSC w/o Setup PAL-B,G,H,I,N

Video Level

Maximum Output 1022 134.8 1022 138.4 1022 817

100% white 820 100 820 100 800 700

Black 284 7.5 240 0 240 0

Blank 240 0 240 0 240 0

Sync 12 -40 12 -40 0 -300

White-to-blank 580 100 580 100 560 700

White-to- sync 808 140 808 140 800 1000

Color burst p-p 232 40 232 40 244 300

D/A IRE D/A IRE D/A mV

20 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Filtering Within the TMC2490A

The TMC2490A incorporates internal digital filters to estab­lish appropriate bandwidths and simplify external analog
reconstruction filter designs.

The chroma portion of the incoming digital video is band­limited to reduce edge effect and other distortions of the
image compression process. Chrominance bandwidth is
selected by CHRBW. When LOW, the chrominance pass­band attenuation is <3 dB within ±650 kHz from f
stopband rejection is >26 dB outside f

±2 MHz. When

SC

SC

. The

HIGH, the chrominance passband attenuation is <3 dB
within ±1.3 MHz from f

. The stopband rejection is

SC

>33 dB outside fSC ±4 MHz.

0

-10

-20

-30

-40

-50

Attenuation (dB)

-60

-70

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Narrowband

Wideband

Frequency (MHz)

24490A

Figure 9. Color-Difference Low-Pass Filter Response

The Chroma Modulator output and the luminance data are
digitally filtered with sharp-cutoff low-pass interpolation fil­ters. These filters ensure that aliased subcarrier, chromi­nance, and luminance frequencies are sufficiently suppressed
above the video base-band.

Virtually all digital-to-analog converters have a response
with high frequency roll-off as a result of the zero-order hold
characteristic of classic D/A converters. This response is
commonly referred to as a sin(x)/x response. The sin(x)/x vs.
sampling frequency is shown in Figure 12.

0.5

0.0

-0.5

-1.0

-1.5

-2.0

Attenuation (dB)

-2.5

-3.0

-3.5
0123456

Frequency (MHz)

24488A

Figure 11. Chrominance and Luminance Interpolation

Filter – Passband Detail

The TMC2490A’s digital interpolation filters convert the
data stream to a sample rate of twice the pixel rate. This
results in much less high frequency sin(x)/x rolloff and the
output spectrum between fS/4 and 3 x fS/4 contains very lit­tle energy. Since there is so little signal energy in this fre­quency band, the demands placed on the output
reconstruction filter are greatly reduced. The output filter
needs to be flat to fS/4 and have good rejection at 3 x fS/4.
The relaxed requirements greatly simplify the design of a fil­ter with good phase response and low group delay distortion.
A small amount of peaking may be added to compensate
residual sin(x)/x rolloff.

0

-10

-20

-30

-40

Attenuation (dB)

-50

-60

-70
0 1 2 3 4 5 6 7 8 9 10 11 12 13

Frequency (MHz)

24487A

Figure 10. Chrominance and Luminance Interpolation

0

-1

-2

-3

-4

Attenuation (dB)

-5

-6
012345678

Frequency (MHz)

Fs=27.0Msps
(Oversampled)

Fs=13.5Msps

Figure 12. Sin(x)/x Response

24489A

Filter – Full Spectrum Response

REV. 1.0.2 2/27/02 21

TMC2490A PRODUCT SPECIFICATION

Closed Caption Insertion

The TMC2490A includes a flexible closed caption processor.
It may be programmed to insert a closed caption signal on
any line within a range of 16 lines on ODD and/or EVEN
fields.

Closed Caption insertion overrides all other configurations
of the encoder. If it is specified on an active video line, it
takes precedence over the video data and removes NTSC
setup if setup has been programmed for the active video
lines.

Closed Caption Control

Closed caption is turned on by setting CCON HIGH. When­ever the encoder begins producing a line specified by
CCFLD and CCLINE, it will insert a closed caption line in
its place. If CCRTS is HIGH, the data contained in CCDx
will be sent. IF CCRTS is LOW, Null Bytes (hex 00 with
ODD parity) will be sent.

3. Write into register 22 the proper combination of CCFLD
and CCLINE. CCPAR may be written as desired. Set
CCRTS HIGH.

4. The CC data is transmitted during the specified line.

As soon as CCDx is transferred into the CC processor (and
CCRTS goes LOW), new data may be loaded into registers
20 and 21. This allows the user to transmit CC data on sev­eral consecutive lines by loading data for line n+1 while data
is being sent on line n.

Registers 20-21 auto-increment when read or written. Regis­ter 22 does not. The microcontroller can repeatedly read
register 22 until CCRTS is found to be LOW, then address
register 20 and write three auto-incremented bytes to set up
for the next CC line.

Parallel Microprocessor Interface

Line Selection

The line to contain CC data is selected by a combination of
the CCFLD bit and the CCLINE bits. CCLINE is added to
the offset shown in Table 13 to specify the line.

Table 13. Closed Caption Line Selection

Standard Offset Field Lines

525 12 ODD 12-27

274 EVEN 274-289

625 9 ODD 9-24

321 EVEN 321-336

Parity Generation

Standard Closed-Caption signals employ ODD parity, which
may be automatically generated by setting CCPAR HIGH.
Alternatively, parity may be generated externally as part of
the bytes to be transmitted, and, with CCPAR LOW, the
entire 16 bits loaded into the CCDx registers will be sent
unchanged.

Operating Sequence

A typical operational sequence for closed-caption insertion
on Line 21 is:

1. Read Register 22 and check that bit 6 is LOW, indicat­ing that the CCDx registers are ready to accept data.

The parallel microprocessor interface, active when SER is
HIGH, employs an 11-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the fall­ing edge of CS. Eight bits of data are presented on D
ing the subsequent rising edge of CS.

In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t
present on D

7-0 tDOM

after the falling edge of CS.

ns after CS falls. Valid data is

DOZ

Table 14. Parallel Port Control

ADR R/W Action

1 0 Load D

pointer.

1 1 Read Control Register pointer on

D

7-0

0 0 Write D

Register.

0 1 Read addressed Control Register

on D

into Control Register

7-0

.

to addressed Control

7-0

.

7-0

7-0

dur-

2. If ready, write two bytes of CC data into registers 20 and

21.

22 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

SCL/CS

SDA / R/W

SA

/ADR

0

D

7-0

SCL/CS

SDA / R/W

SA

/ADR

0

D

7-0

t

PWLCS

t

SA

t

HA

t

SD

t

PWHCS

t

HD

Figure 13. Microprocessor Parallel Port - Write Timing

t

PWLCS

t

SA

t

DOM

t

DOZ

t

HA

t

PWHCS

t

HOM

65-3548-02

65-3548-03

Figure 14. Microprocessor Parallel Port - Read Timing

Serial Control Port (R-Bus)

In addition to the 11-wire parallel port, a 2-wire serial con­trol interface is also provided, and active when SER is LOW.
Either port alone can control the entire chip. Up to four
TMC2490A devices may be connected to the 2-wire serial
interface with each device having a unique address.

The 2-wire interface comprises a clock (SCL/CS) and a bi­directional data (SDA/R/W) pin. The TMC2490A acts as a
slave for receiving and transmitting data over the serial inter­face. When the serial interface is not active, the logic levels
on SCL/CS
up resistors.

Data received or transmitted on the SDA/R/W line must be
stable for the duration of the positive-going SCL/CS pulse.
Data on SDA/R/W
If SDA/R/W
interface interprets that action as a start or stop sequence.

There are five components to serial bus operation:

• Start signal

• Slave address byte

and SDA/R/W are pulled HIGH by external pull-

can only change when SCL/CS is LOW.

changes state while SCL/CS is HIGH, the serial

• Base register address byte

• Data byte to read or write

• Stop signal

When the serial interface is inactive (SCL/CS

and
SDA/R/W are HIGH) communications are initiated by send­ing a start signal. The start signal is a HIGH-to-LOW transi­tion on SDA/R/W while SCL/CS is HIGH. This signal alerts
all slaved devices that a data transfer sequence is coming.

The first eight bits of data transferred after a start signal com­prise a seven bit slave address and a single R/W bit. As
shown in Figure 16A, the R/W bit indicates the direction of
data transfer, read from or write to the slave device. If the
transmitted slave address matches the address of the device
(set by the state of the SA

/ADR and SA1 input pins in Table

0

15), the TMC2490A acknowledges by bringing SDA/R/W
LOW on the 9th SCL/CS pulse. If the addresses do not
match, the TMC2490A does not acknowledge.

REV. 1.0.2 2/27/02 23

TMC2490A PRODUCT SPECIFICATION

Table 15. Serial Port Addresses

A1

A

A

6

A

5

A

4

3

(SA

A

2

0001100

0001101

0001110

0001111

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit
of the sequence.

If the TMC2490A does not acknowledge the master device
during a write sequence, the SDA/R/W
master can generate a stop signal. If the master device does
not acknowledge the TMC2490A during a read sequence,
the TMC2490A interprets this as “end of data.” The SDA/R/
W remains HIGH so the master can generate a stop signal.

Writing data to specific control registers of the TMC2490A
requires that the 8-bit address of the control register of inter­est be written after the slave address has been established.
This control register address is the base address for subse­quent write operations. The base address auto-increments by
one for each byte of data written after the data byte intended
for the base address. If more bytes are transferred than there

remains HIGH so the

are available addresses, the address will not increment and

0

(SA

)

1

higher than 22h will not produce an ACKnowledge signal.

)

0

will remain at its maximum value of 22h. Any base address

A

Data is read from the control registers of the TMC2490A in a
similar manner. Reading requires two data transfer opera­tions:

• The base address must be written with the R/W bit of the

slave address byte LOW to set up a sequential read
operation.

• Reading (the R/W

bit of the slave address byte HIGH)
begins at the previously established base address. The
address of the read register auto-increments after each
byte is transferred.

To terminate a read/write sequence to the TMC2490A, a stop
signal must be sent. A stop signal comprises of a LOW-to­HIGH transition of SDA/R/W

while SCL/CS is HIGH.

A repeated start signal occurs when the master device driv­ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica­tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.

SDA / R/W

SCL/CS

t

t

STAH

BUFF

t

DHO

t

DSU

t

DAL

t

DAH

Figure 15. Serial Port Read/Write Timing

t

STASU

t

STOSU

24469A

24 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Serial Interface Read/Write Examples

Write to one control register

• Start signal

• Slave Address byte (R/W bit = LOW)

• Base Address byte

• Data byte to base address

• Stop signal

Write to four consecutive control registers

• Start signal

• Slave Address byte (R/W bit = LOW)

• Base Address byte

• Data byte to base address

• Data byte to (base address + 1)

• Data byte to (base address + 2)

• Data byte to (base address + 3)

• Stop signal

Read from one control register

• Start signal

• Slave Address byte (R/W

bit = LOW)

• Base Address byte

• Stop signal

• Start signal

• Slave Address byte (R/W

bit = HIGH)

• Data byte from base address

• No Acknowledge

Read from four consecutive control registers

• Start signal

• Slave Address byte (R/W

bit = LOW)

• Base Address byte

• Stop signal

• Start signal

• Slave Address byte (R/W

bit = HIGH)

• Data byte from base address

• Data byte from (base address + 1)

• Data byte from (base address + 2)

• Data byte from (base address + 3)

• No Acknowledge

SDA / R/W

SCL/CS

SDA / R/W

SCL/CS

MSB LSB ACK

Figure 16. Serial Interface – Typical Byte Transfer

A

6

A

5

Figure 16A. Chip Address with Read/Write

A

4

A

3

A

2

SA

1

Bit

SA

0

R/W ACK

24470A

65-3548-05

REV. 1.0.2 2/27/02 25

TMC2490A PRODUCT SPECIFICATION

Equivalent Circuits and Threshold Levels

V

DD

V

DD

R

V

p

REF

REF

GND

p

27012B

np

V

DD

OUT

GND

27013B

Figure 18. Equivalent Analog Input Circuit Figure 19. Equivalent Analog Output Circuit

Digital
Input

V

DD

p

V

DD

p

Digital
Output

GND

n

27014C

n

GND

27011C

Figure 20. Equivalent Digital Input Circuit Figure 21. Equivalent Digital Output Circuit

t

ENA

CS

Three-State
Outputs

t

DIS

0.5V

High Impedance

0.5V

2.0V

0.8V

7048C

Figure 22. Threshold Levels for Three-State Measurements

REV. 1.0.2 2/27/02 26

PRODUCT SPECIFICATION TMC2490A

Absolute Maximum Ratings

(beyond which the device may be damaged)

Parameter Min. Typ. Max. Unit

Power Supply Voltage -0.5 7.0 V

Digital Inputs

Applied Voltage

Forced Current

2

3,4

Output

Applied Voltage

Forced Current

2

3,4

Short Circuit Duration (single output in HIGH state to ground) 1 sec

Analog Short Circuit Duration (all outputs to ground) Infinite

Temperature

Operating, Ambient -20 110 °C

Junction 140 °C

Storage Temperature -65 150 °C

Lead Soldering (10 seconds) 300 °C

Vapor Phase Soldering (1 minute) 220 °C

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

1

-0.5 VDD + 0.5 V

-20.0 20.0 mA

-0.5 VDD + 0.5 V

-3.0 6.0 mA

Operating Conditions

Parameter Conditions Min. Typ. Max. Units

V

DD

V

IH

V

IL

V

REF

I

REF

R

I

OH

I

OL

T

A

REF

Power Supply Voltage 4.75 5.0 5.25 V

Input Voltage, Logic HIGH TTL Compatible Inputs 2.0 V

CLK Input 2.4 V

R-Bus Inputs 0.7V

DD

DD

DD

Input Voltage, Logic LOW TTL Compatible Inputs GND 0.8 V

R-Bus Inputs 0.3V

DD

External Reference Voltage 1.235 V

D/A Converter Reference Current (I

External Reference Resistor V

= V

REF

REF/RREF

flowing out of the R

= NOM, RL = 75Ω 787 Ω

REF

),

REF

1.57 mA

pin

Output Current, Logic HIGH -2.0 mA

Output Current, Logic LOW 4.0 mA

Ambient Temperature, Still Air 0 70 °C

V

27

TMC2490A PRODUCT SPECIFICATION

Operating Conditions (continued)

Parameter Conditions Min. Typ. Max. Units

Pixel Interface

f

PXL

f

PXCK

t

PWHPX

t

PWLPX

t

SP

t

HP

Parallel Microprocessor Interface

t

PWLCS

t

PWHCS

t

SA

t

HA

t

SD

t

HD

t

PWLR

Serial Microprocessor Interface

t

DAL

t

DAH

t

STAH

t

STASU

t

STOSU

t

BUFF

t

DSU

t

DHO

Pixel Rate 13.5 Mpps

Master Clock Rate = 2X pixel rate 27.0 MHz

PXCK pulse width, HIGH 10 ns

PXCK pulse width, LOW 15 ns

PD

Setup Time 15 ns

7-0

PD

Hold Time 0 ns

7-0

CS Pulse Width, LOW 95 ns

CS Pulse Width, HIGH 3 pixels

Address Setup Time 17 ns

Address Hold Time 0 ns

Data Setup Time (write) 17 ns

Data Hold Time (write) 0 ns

RESET Pulse Width, LOW 16 PXCK

SCL Pulse Width, LOW 1.3 µs

SCL Pulse Width, HIGH 0.6 µs

SDA Start Hold Time 0.6 µs

SCL to SDA Setup Time (Stop) 0.6 µs

SCL to SDA Setup Time (Start) 0.6 µs

SDA Stop Hold Time Setup 1.3 µs

SDA to SCL Data Setup Time 300 ns

SDA to SCL Data Hold Time 300 ns

REV. 1.0.2 2/27/02 28

PRODUCT SPECIFICATION TMC2490A

DC Electrical Characteristics

Parameter Conditions Min. Typ. Max. Units

I

DD

I

DDQ

V

I

BR

Z

I

IH

I

IL

I

OZH

Power Supply Current, Unloaded

Power Supply Current, Quiescent

Voltage Reference Output 1.173 1.235 1.297 V

RO

Reference Bias -100 100 µA

V

RO

REF

Input Current, HIGH VDD = Max, VIN = V

Input Current, LOW VDD = Max, VIN = 0V ±10 µA

Hi-Z Output Leakage Current,
Output HIGH

I

OZL

Hi-Z Output Leakage Current,
Output LOW

I

OS

V

V

C

C

V

R

C

Notes:

1. Maximum I

2. I

Short-Circuit Current -50 -10 mA

Output Voltage, HIGH IOH = Max 2.4 V

OH

Output Voltage, LOW IOL = Max 0.4 V

OL

Digital Input Capacitance 4 10 pF

I

Digital Output Capacitance 10 pF

I

Video Output Compliance -0.3 2.0 V

OC

Video Output Resistance 15 kΩ

OUT

Video Output Capacitance I

OUT

when RESET = LOW, disabling D/A converters.

DDQ

Output Impedance 1000 Ω

with VDD = Max and TA = Min. Outputs loaded wtih 75Ω.

DD

1

VDD = Max, f

2

VDD = Max 20 mA

VDD = Max, VIN = V

= 27MHz 130 mA

PXCK

DD

DD

VDD = Max, VIN = 0V ±10 µA

= 0mA, f = 1MHz 15 25 pF

OUT

±10 µA

±10 µA

AC Electrical Characteristics

Parameter Conditions Min. Typ. Max. Units

t

DOZ

t

HOM

t

DOM

t

R

t

F

t

DOV

Note:

1. Timing reference points are at the 50% level. Analog C

Output Delay, CS to low-Z 14 ns

Output Hold Time, CS to high-Z 30 ns

Output Delay, CS to Data Valid 40 ns

D/A Output Current Risetime 10% to 90% of full scale 2 ns

D/A Output Current Falltime 90% to 10% of full scale 2 ns

Analog Output Delay 3 11 17 ns

LOAD

<10pF, D

load <40pF.

7-0

29

TMC2490A PRODUCT SPECIFICATION

System Performance Characteristics

Parameter Conditions Min. Typ. Max. Units

RES D/A Converter Resolution 10 10 10 Bits

dp Differential Phase PXCK = 27 MHz,

40 IRE Ramp

dg Differential Gain PXCK = 27 MHz,

40 IRE Ramp

CNLP Chroma Nonlinear Phase NTC-7 Combination 0.3 degree

CNLG Chroma Nonlinear Gain NTC-7 Combination TBD %

CLIM Chroma/Luma Intermodulation NTC-7 Combination 0.3 IRE

CLGI Chroma/Luma Gain inequality NTC-7 Composite TBD %

CLDI Chroma/Luma Delay inequality NTC-7 Composite 7.1 ns

LNLD Luma Nonlinear Distortion NTC-7 TBD %

FTWD Field Time Waveform Distortion NTC-7 0.1 %

LTWD Line Time Waveform Distortion NTC-7 0.3 %

NOISE Noise Level

CAMN Chroma AM Noise Red field -63 dB rms

CPMN Chroma PM Noise Red field -62 dB rms

SYR Sync Pulse Rise Time NTSC 140 ns

SYF Sync Pulse Fall Time NTSC 140 ns

PSRR Power Supply Rejection Ratio C

Note:

1. Noise Level is uniformly weighted, 10 kHz to 5.0 MHz bandwidth, with Tilt Null ON measured using VM700 "Measure Mode."

1

100% unmod. ramp -55 dB rms

PAL 250

PAL 250

= 0.1 µF, f = 1 kHz 0.02 %/%V

BYP

0.6 degree

0.7 %

DD

REV. 1.0.2 2/27/02 30

PRODUCT SPECIFICATION TMC2490A

Applications Information

The circuit in Figure 24 shows the connection of power sup­ply voltages, output reconstruction filters and the external
voltage reference. All VDD pins should be connected to the
same power source.

The full-scale output voltage level, V
ITE, LUMA, and CHROMA pins is found from:

V

OUT

= I

OUT

= K x (V

x RL = K x I

REF/RREF

REF

) x R

where:

•I

is the full-scale output current sourced by the

OUT

TMC2490A D/A converters.

•RL is the net resistive load on the COMPOSITE,

CHROMA, and LUMA output pins.

• K is a constant for the TMC2490A D/A converters

(approximately equal to 10.4).

•I

is the reference current flowing out of the R

REF

to ground.

•V

•R

is the voltage measured on the V

REF

is the total resistance connected between the R

REF

pin and ground.

• A 0.1µF capacitor should be connected between the C

pin and the adjacent V

DDA

, pin.

, on the COMPOS-

OUT

x R

L

L

REF

pin.

REF

pin

REF

BYP

The reference voltage in Figure 24 is from an LM185 1.2
Volt band-gap reference. The 392 Ohm resistor connected
from R

to ground sets the overall "gain" of the three D/A

REF

converters of the TMC2490A. A 787Ω resistor is used for
single 75Ω termination. Varying R

±5% will cause the

REF

full-scale output voltage on COMPOSITE, LUMA, and
CHROMA to vary by ±5%.

The suggested output reconstruction filter is the same one
used on the TMC2063P7C Demonstration Board. The phase
and frequency response of this filter is shown in Figure 23.
The Schottky diode is for ESD protection.

Analog Reconstruction Filter

0

-10

-20

-30

-40

Attenuation (dB)

-50

-60
0 5 10 15 20 25

Frequency (MHz)

Figure 23. Response of Recommended Output Filter

40

0

-40

-80

-120

-160

-200

24365A

Phase (deg)

VIDEO

MPEG-2
Decoder

PIXCLK

B/T

HSYNC

INTERFACE

YC

7-0

27.0 MHz
CLOCK

VIDEO
FROM
ENCODER

7-0

D

1.0µH

SCL/CS

SDA / R/W

+5V

10µF

0.1µF

V

PXCK CHROMA

VSYNC

HSYNC

PD

PDC

SELC

DD

7-0

GND

TMC2490A

Multistandard

Digital Video

Encoder

SER

RESET

SA1

SA0/ADR

CONTROL INTERFACE

75Ω

75Ω

100pF

LUMA

COMPOSITE

V

DDA

C

BYP

V

REF

R

REF

Figure 24. Typical Application Circuit

1.8µH

1N5818

27pF

330pF 330pF

LPF

+5V

0.1µF

392Ω

+5V

3.3kΩ

LM185-1.2

65-2490(1)A-03

VIDEO
OUTPUT
TO 75Ω
LOAD

0.1µF

REV. 1.0.2 2/27/02 31

TMC2490A PRODUCT SPECIFICATION

Notes:

32 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Notes:

REV. 1.0.2 2/27/02 33

TMC2490A PRODUCT SPECIFICATION

Notes:

34 REV. 1.0.2 2/27/02

PRODUCT SPECIFICATION TMC2490A

Mechanical Dimensions – 44-Pin PLCC Package

Symbol

A .165 .180 4.20 4.57

A1 .090 .120 2.29 3.04

A2 .020 .51——

B .013 .021 .33 .53
B1 .026 .032 .66 .81

D/E .685 .695 17.40 17.65

D1/E1 .650 .656 16.51 16.66

D3/E3 .500 BSC 12.7 BSC

e .050 BSC 1.27 BSC

J .042 .056 1.07 1.42 2

ND/NE 11 11

N44 44

ccc .004 0.10——

Inches

Min. Max. Min. Max.

Millimeters

E

E1

Notes

3

Notes:

1.

All dimensions and tolerances conform to ANSI Y14.5M-1982

2.

Corner and edge chamfer (J) = 45°

3.

Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)

J

D

D1

D3/E3

B1

e

A

A1

A2

J

– C –

B

LEAD COPLANARITY

ccc C

35

TMC2490A PRODUCT SPECIFICATION

Ordering Information

Product Number Temperature Range Screening Package Package Marking

TMC2490AR2C 0°C to 70°C Commercial 44-Lead PLCC 2490AR2C

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

2/27/02 0.0m 003

 1998 Fairchild Semiconductor Corporation

Stock# DS7002490A