Datasheet TMC2249AX2 Datasheet (Fairchild Semiconductor)

www.fairchildsemi.com

REV. 1.0.2 7/6/00

Features

• 60 MHz input and computation rate

• Two 12-bit multipliers

• Separate data and coefﬁcient inputs

• Independent, user-selectable pipeline delays of 1 to 16 clocks on all input ports

• Separate 16-bit input port allows cascading or addition of a constant

• User-selectable rounded output

• Internal 1/2 LSB rounding of products

• Fully registered, pipelined architecture

• Available in 120-Pin CPGA, PPGA, MPGA or MQFP

Applications

• Video switching

• Image mixing

• Digital signal modulation

• Complex frequency synthesis

• Digital ﬁltering

• Complex arithmetic functions

Description

The TMC2249A is a high-speed digital arithmetic circuit consisting of two 12-bit multipliers, an adder and a cascadeable accumulator. All four multiplier inputs are simultaneously accessible to the user, and each includes a userprogrammable pipeline delay of up to 16 clocks in length. The 24-bit adder/subtractor is followed by an accumulator and 16-bit input port which allows the user to cascade multiple TMC2249As. A new 16-bit accumulated output is available every clock, up to the maximum rate of 60 MHz. All inputs and outputs are registered except the three-state output enable, and all are TTL compatible.

Logic Symbol

TMC2249A

Digital Mixer

CLK NEG1

NEG2 SWAP

OE ACC

RND FT CASEN

S

15-0

Delay

1-16

Delay

1-16

Delay

1-16

Delay

1-16

B

11-0

ADEL

3-0

A

11-0

BDEL

3-0

ENA

ENB

C

11-0

CDEL

3-0

ENC

D

11-0

CAB

15-0

DDEL

3-0

END

The TMC2249A utilizes a pipelined, bus-oriented structure offering signiﬁcant ﬂexibility. Input register clock enables and programmable input data pipeline delays on each port offer an adaptable input structure for high-speed digital systems. Following the multipliers, the user may perform addition or subtraction of either product, arithmetic rounding to 16 bits, and accumulation and summation of products with a cascading input. The output port allows access to all 24 bits of the internal accumulator by switching between overlapping least and most-signiﬁcant 16-bit words, and a three-state output enable simpliﬁes connection to an external system bus.

The TMC2249A has numerous applications in digital processing algorithms, from executing simple image mixing and switching, to performing complex arithmetic functions and complex waveform synthesis. FIR ﬁlters, digital quadrature mixers and modulators, and vector arithmetic functions may also be implemented with this device.

Fabricated in a submicron CMOS process, the TMC2249A operates at guaranteed clock rates of up to 60 MHz over the full temperature and supply voltage ranges. It is pin- and function-compatible with Fairchild’s TMC2249, while providing higher speed operation and lower power dissipation. It is available in a 120 pin Ceramic Pin Grid Array (CPGA), 120 pin Plastic Pin Grid Array (PPGA), 120 lead MQFP to PPGA package (MPGA), and a 120 lead Metric Quad FlatPack (MQFP).

TMC2249A

Digital Mixer

12 x 12 Bit, 60 MHz

PRODUCT SPECIFICATION TMC2249A

2

REV. 1.0.2 7/6/00

Block Diagram

ADEL

3-0

A

11-0

1-16

ENA BDEL

3-0

NEG1

NEG2

RND

FT

16

24

16

M

16

L

ACC

I0

01 01

2's Comp 2's Comp

CASEN

ACC

SWAP

OE

CAS

15-0

S

15-0

B

11-0

1-16

ENB

DDEL

3-0

D

11-0

1-16

ENDCDEL

3-0

C

11-0

1-16

ENC

124

12

E

1

2

16

12

01 F

12

12 x (16:1) MUX

12

ADEL

3-0

A

11-0

ENA

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00

3

Functional Description

The TMC2249A performs the summation of products described by the formula:

S(N+5) =A(N-ADEL) × B(N-BDEL) × (-1

NEG1(N)

) +

C(N-CDEL) × D(N-DDEL) × (-1

NEG2(N)

) +

CAS(N+3 × FT)

where ADEL through DDEL range from 1 to 16 pipe delays.

All inputs and controls utilize pipeline delay registers to maintain synchronicity with the data input during that clock,

except when the Cascade data input is routed directly to the accumulator by use of the Feedthrough control. One-half LSB rounding to 16 bits may be performed on the sum of products while summing with the cascade input data.

The user may access either the upper or lower 16 bits of the 24-bit accumulator by swapping overlapping registers. The output bus has an asynchronous high-impedance enable, to simplify interfacing to complex systems.

Pin Assignments

120 Pin Metric Quad Flat Pack, KE Package

CLK ACC NEG1 NEG2 RND S

15

S

14

GND S

13

S

12

S

11

V

DD

S

10

S

9

S

8

GND S

7

S

8

S

5

V

DD

S

4

S

3

S

2

GND S

1

S

0

OE SWAP BDEL

0

BDEL

1

30

120 91

31 60

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

90

61

BDEL

2

BDEL

3

ENB B

0

B

1

B

2

B

3

B

4

B

5

B

6

B

7

GND B

8

B

9

B

10

V

DD

B

11

A

11

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

ENA

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Pin Name Pin Name

ADEL

3

ADEL

2

ADEL

1

ADEL

0

NC CAS

15

CAS

14

CAS

13

CAS

12

CAS

11

CAS

10

GND CAS

9

CAS

8

CAS

7

CAS

6

CAS

5

CAS

4

CAS

3

CAS

2

CAS

1

CAS

0

CASEN FT CDEL

0

CDEL

1

CDEL

2

CDEL

3

ENC C

0

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

C

1

C

2

C

3

C

4

C

5

C

6

C

7

C

8

C

9

C

10

C

11

V

DD

D

11

D

10

D

9

GND D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

END DDEL

3

DDEL

2

DDEL

1

DDEL

0

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

Pin Name Pin Name

PRODUCT SPECIFICATION TMC2249A

4

REV. 1.0.2 7/6/00

Pin Assignments

120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and 120 Pin Metric Quad FlatPack to 120 Pin Plastic Pin Array, H6 Package

BADEFGHJKLMNC

1

2

3

4

5

6

7

8

9

10

11

12

13

Top View

Cavity Up

KEY

DDEL

0

DDEL

3 END D

2

D

4

D

7

D

8

D

10

C

11

C

9

C

6

C

3

C

0 NEG1 ACC DDEL

1

D

0 D

3 D

6 D

9 D

11 C

10 C

7 C

5 C

2 CDEL

2

S

15 RND CLK DDEL

2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4

D

1

D

5 GND V

DD C

8 C

4 C

1 ENC

CDEL

1

S

13 S

14 GND CDEL

3

CDEL

0

CASEN S

11 S

12 GND

FT CAS

0

CAS

1

S

9 S

10 V

DD CAS

2

CAS

3

CAS

4

S

7 S

8 GND

C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3

Pin Name Pin Name

CAS

6

CAS

7

CAS

5

S

6

S

5

V

DD

GND CAS

9

CAS

8

S

4

S

3

GND CAS

13

CAS

11

CAS

10

S

2

S

1

SWAP ADEL

0

CAS

14

CAS

12

S

0

BDEL

0

BDEL

2

B

0

B

4

GND V

DD

A

9

A

5

G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9

A

1

ADEL

3

NC CAS

15

OE BDEL

3

B

1

B

3

B

6

B

8

B

10

A

10

A

7

A

4

A

0

ADEL

2

ADEL

1

BDEL

1

ENB B

2

B

5

B

7

B

9

B

11

A

11

A

8

A

6

A

3

A

2

ENA

L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

Pin Name Pin Name

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00

5

Pin Descriptions

Pin Name

Pin Number

Pin Function Description

CPGA/PPGA/

MPGA

MQFP

Power

V

DD

F3, H3, L7, C8 12, 20, 46, 102 Supply Voltage. The TMC2249A operates from a single +5V

supply. All power and ground pins must be connected.

GND E3, G3, J3, L6,

H11, C7

8, 16, 24, 42,

72, 106

Ground. The TMC2249A operates from a single +5V supply. All

power and ground pins must be connected.

Clock

CLK C3 1

System Clock. The TMC2249A operates from a single master

clock input. The rising edge of clock strobes all enabled registers. All timing specifications are referenced to the rising edge of CLK.

Inputs

A

11-0

N8, M8, L8,

N9, M9, N10,

L9, M10, N11,

N12, L10, M11

48, 49, 50, 51, 52, 53, 54, 55,

56, 57, 58, 59

A-D Input. A through D are the four 12-bit registered data input

ports. A

0

-D

0

are the LSBs (see Table 1). Data presented to the input ports is clocked in to the top of the 16-stage delay pipeline on the next clock when enabled, "pushing" data down the register stack.

B

11-0

N7, M7, N6,

M6, N5, M5,

N4, L5, M4,

N3, M3, L4

47, 45, 44, 43, 41, 40, 39, 38,

37, 36, 35, 34

C

11-0

A9, B9, A10,

C9, B10, A11,

B11, C10, A12,

B12, C11, A13

101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91,

90

D

11-0

B8, A8, B7, A7, A6, B6, C6, A5, B5, A4, C5, B4

103, 104, 105, 107, 108, 109,

110, 111, 112 113, 114, 115

ADEL

3-0

L11, M12,

M13, K11

61, 62, 63, 64 A-D Delay. ADEL through DDEL are the four-bit registered input

data pipe delay select word inputs. Data to be presented to the multipliers is selected from one of sixteen stages in the input data delay pipe registers, as indicated by the delay select word presented to the respective input port during that clock. The minimum delay is one clock (select word=0000), and the maximum delay is 16 clocks (select word=1111). Following powerup these values are indeterminate and must be initialized by the user.

BDEL

3-0

M2, L3, N1, L2 32, 31, 30, 29

CDEL

3-0

D11, B13,

C13, D12

88, 87, 86, 85

DDEL

3-0

A2, C4, B3, A1 117, 118, 119,

120

CAS

15-0

L13, K12, J11, K13, J12, J13,

H12, H13,

G12, G11,

G13, F13, F12,

F11, E13, E12

66, 67, 68, 69, 70, 71, 73, 74, 75, 76, 77, 78,

79, 80, 81, 82

Cascade Input. CAS is the 16-bit Cascade data input port. CAS

0

is

the LSB. See Table 1.

Controls

S

15-0

C1, D2, D1,

E2, E1, F2, F1,

G2, G1, H1,

H2, J1, J2, K1,

K2, L1

6, 7, 9, 10, 11, 13, 14, 15, 17, 18, 19, 21, 22,

23, 25, 26

Sum Output. The current 16-bit result is available at the Sum

output. The output may be the most or least significant 16 bits of the current accumulator output, as determined by SWAP. S

0

is the LSB.

See Table 1.

PRODUCT SPECIFICATION TMC2249A

6

REV. 1.0.2 7/6/00

Controls

ENA

-END N13, N2, C12, A360, 33, 89, 116 Input Enables. Input data presented to port i11-0 (i=A,B,C, or D) are latched into delay pipeline i, and data already in pipeline i advance by one register position, on each rising edge of CLK for which ENi

is LOW. When ENi is HIGH, the data in pipeline i do not move and the value at the input port i will be lost before it reaches the multiplier.

NEG1,2 B1, D3 3, 4

Negate. The products of the multipliers are negated causing a

subtraction to be performed during the internal summation of products, when the NEGate controls are HIGH, NEG1 negates the product A x B, while NEG2 acts on the output of the multiplier which generates the product C x D. When the length controls ADEL– DDEL are set to zero, these controls indicate the operation to be performed on data input during the same clock. As nonzero values for ADEL–DDEL do not affect the pipelining of these controls, their effect is not synchronous with the data input in these cases.

RND C2 5

Round. When the rounding control is HIGH, the 24-bit sum of

products resulting from data input during that clock is rounded to 16 bits. When enabled rounding is automatically performed only during the first cycle of each accumulation sequence, to avoid the accumulation of roundoff errors.

FT E11 84

Feedthrough. When the Feedthrough control is HIGH, the pipeline

delay through the cascade data path is minimized to simplify the cascading of multiple devices. When FT is LOW and ADEL through DDEL are all set to 0, the data inputs are aligned, such that S(n+6) = CAS(n) + A(n)B(n) + C(n)D(n). See Table 2.

CASEN

D13 83

Cascade Enable. Data presented at the cascade data input port

are latched and accumulated internally when the input enable CASEN during that clock is LOW. When CASEN is HIGH, the cascade input port is ignored.

ACC B2 2

Accumulate. When the registered ACCumulator control is LOW, no

internal accumulation will be performed on the data input during the current clock, effectively clearing the prior accumulated sum. When ACC is HIGH, the internal accumulator adds the emerging product to the sum of the previous products and RND is disabled.

SWAP K3 28

Swap Output Words. The user may access both the most and

least-significant 16 bits of the 24-bit accumulator by utilizing SWAP. Normal operation of the device, with SWAP = HIGH, outputs the most significant word. Setting SWAP = LOW puts a double-register structure into "toggle" mode, allowing the user to examine the LSW on alternate clocks. New output data will not be clocked into the output registers until SWAP returns HIGH.

OE M1 27

Output Enable. Data currently in the output registers is available at

the output bus S

15-0

when the asynchronous Output Enable is LOW.

When OE is HIGH, the outputs are in the high-impedance state.

No Connect

L12 65 Do Not Connect

D4 Index Pin (optional)

Pin Descriptions

(continued)

Pin Name

Pin Number

Pin Function Description

CPGA/PPGA/

MPGA

MQFP

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00

7

Table 1. Data Formats and Bit Weighting

Notes:

A minus sign indicates the two’s complement sign bit. RND adds 1 to the 2

7

position if ACC is low.

1514131211109876543210BIT

-2

11

2

10

2

9

2

8

2

7

2

6

2

5

2

4

2

3

2

1

2

0

DATA (A

11-0

-D

11-0

)

-2

23

2

22

2

21

2

20

2

19

2

18

2

17

2

16

2

15

2

14

2

13

2

12

2

11

2

10

2

9

2

8

CASCADE INPUT (CAS

15-0

)

SUM (S

15-0

)

2

15

2

14

2

13

2

12

2

11

2

10

2

9

2

8

2

7

2

6

2

5

2

4

2

3

2

22120

LSW

-223222221220219218217216215214213212211210292

8

MSW

Equivalent Circuits and Threshold Levels

Figure 1. Equivalent Digital Input Circuit

Figure 2. Equivalent Digital Output Circuit

Data or Control Input

V

DD

p

n

GND

V

DD

p

n

GND

Output

Figure 3. Threshold Levels for Three-State Measurement

2.0V

0.8V

t

DIS

t

ENA

Three-State Outputs

OE

High Impedance

0.5V

PRODUCT SPECIFICATION TMC2249A

8 REV. 1.0.2 7/6/00

Absolute Maximum Ratings (beyond which the device may be damaged)1

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

Operating Conditions

Parameter Min Max Unit

Supply Voltage -0.5 7.0 V Input Voltage -0.5 VDD + 0.5 V Applied Voltage (Output)

2

-0.5 VDD + 0.5 V

Externally Forced Current (Output)

3,4

-3.0 6.0 mA Output Short Circuit Duration (single output in HIGH state to ground) 1 sec Operating, Ambient Temperature -20 110 °C Operating, Junction Temperature 140 °C Storage Temperature -65 150 °C Lead, Soldering (10 seconds) 300 °C

Parameter Min Nom Max Units

V

DD

Power Supply Voltage 4.75 5.0 5.25 V

f

CLK

Clock frequency TMC2249A 25 MHz

TMC2249A-1 40 MHz TMC2249A-2 60 MHz

t

PWH

CLK pulse width, HIGH 6 ns

t

PWL

CLK pulse width, LOW 7 ns

t

S

Input Data Set-up Time 6 ns

t

H

Input Data Hold Time 1.5 ns

V

IH

Input Voltage, Logic HIGH Data Inputs 2.0 V

CLK Input 2.2 V

V

IL

Input Voltage, Logic LOW 0.8 V

I

OH

Output Current, Logic HIGH -2.0 mA

I

OL

Output Current, Logic LOW 4.0 mA

T

A

Ambient Temperature, Still Air 0 70 °C

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00 9

Electrical Characteristics

Switching Characteristics

Note:

1. All transitions are measured at a 1.5V level except for t

ENA

and t

DIS

.

Figure 4. Timing Diagram

Parameter Conditions Min Typ Max Units

I

DD

Total Power Supply Current

V

DD

= Max, C

LOAD

= 25pF, f

CLK

= Max TMC2249A 75 mA TMC2249A-1 105 mA TMC2249A-2 145 mA

I

DDU

Power Supply Current, Unloaded

V

DD

= Max, OE = HIGH, f

CLK

= Max TMC2249A 68 mA TMC2249A-1 92 mA TMC2249A-2 124 mA

I

DDQ

Power Supply Current, Quiescent

V

DD

= Max, CLK = LOW 5 mA

C

I/O Pin Capacitance 5 pF

I

IH

Input Current, HIGH VDD = Max, VIN = V

DD

±10 µA

I

IL

Input Current, LOW VDD = Max, VIN = 0 V ±10 µA

I

OZH

Hi-Z Output Leakage Current, Output HIGH

VDD = Max, VIN = V

DD

±10 µA

I

OZL

Hi-Z Output Leakage Current, Output LOW

VDD = Max, VIN = 0 V ±10 µA

I

OS

Short-Circuit Current -20 -80 mA

V

OH

Output Voltage, HIGH S

15-0

, IOH = Max 2.4 V

V

OL

Output Voltage, LOW S

15-0

, IOL = Max 0.4 V

Parameter Conditions

1

Min Typ Max Units

t

DO

Output Delay Time C

LOAD

= 25 pF 14 ns

t

HO

Output Hold Time C

LOAD

= 25 pF 2.5 ns

t

ENA

Three-State Output Enable Delay C

LOAD

= 0 pF 12 ns

t

DIS

Three-State Output Disable Delay C

LOAD

= 0 pF 12 ns

CLK

A

11-0

D

11-0

CONTROLS

1

S

15-0

2

DA DB

5321

SA

1/f

CLK

t

PWHtPWL

t

DO

t

HO

t

S

t

H

67

1

Except OE.

2

Assumes OE = LOW and ADEL-DDEL set to 0.

PRODUCT SPECIFICATION TMC2249A

10 REV. 1.0.2 7/6/00

Application Notes

The TMC2249A is a ﬂexible signal and image processing building block with numerous user-selectable functions which expand its usefulness. Table 2 clariﬁes the operation of the device, demonstrating the various feature available to the user and the timing delays incurred.

Table 2. TMC2249A Operation Sequence

CASEN = 0, H=HIGH, L=LOW, “ms” indicates most significant output word (bits 23-8), “ls” indicates least significant word (bits 15-0). The appropriate enables for the indicated data are assumed, otherwise ‘-’ indicates that port not enabled. Note that the output data summations including A(8)-D(8) is lost, since the output on cycle 13 is swapped to the LSW of S(12) on cycle 8. In general, RND may be left high unless the ls output is to be used, as on line 8 above.

CLK ADEL A

11-0

BDEL B

11-0

CDEL C

11-0

DDEL D

11-0

NEG1 NEG2 CAS

15-0

FT ACC RND SWAP S

15-0

1 0 A(1) 0 B(1) 0 C(1) 0 D(1) L L 0 L L H H — 2 0 A(2) 0 B(2) 0 C(2) 0 D(2) L H 0 L L H H — 3 0 A(3) 0 B(3) 0 C(3) 0 D(3) H L 0 L L L H — 4 0 A(4) 0 B(4) 0 C(4) 0 D(4) L L CAS(4) L L L H — 5 0 A(5) 0 B(5) 0 C(5) 0 D(5) L L 0 L L L H — 6 0 A(6) 0 B(6) 0 C(6) 0 D(6) L L 0 L L H H (A(1) × B(1)+C(1) × D(1)+27)

ms

7 0 A(7) 0 B(7) 0 C(7) 0 D(7) L L 0 L H X H (A(2) × B(2)-C(2) × D(2)+27)

ms

8 0 A(8) 0 B(8) 0 C(8) 0 D(8) L L CAS(8) H L L L (-A(3) × B(3)+C(3) × D(3))

ms

9 0 A(9) 0 B(9) 0 C(9) 0 D(9) L L 0 L L H H (A(4) × B(4)+C(4) × D(4)+CAS(4))

ms

10 (A(5) × B(5)+C(5) × D(5)+CAS(8))

ms

11 (A(6) × B(6)+C(6) × D(6)+27)

ms

12 (A(7) × B(7)+C(7) × D(7)+S(11))

ms

13 (S(12))

ls

14 (A(9) × B(8)+C(7) × D(6)+27)

ms

Digital Filtering

The input structure of the TMC2249A demonstrates great versatility when all four multiplier inputs and the programmable delay registers are utilized.

Table 3 and Table 4 illlustrate how a direct-form symmetric FIR ﬁlter of up to 32 taps can be implemented. By utilizing

the four input delay registers as pipelined storage banks, the user can store up to 32 coefﬁcient-data word pairs, split into alternate "even" and "odd" halves. Two taps of the ﬁlter are calculated on each clock, and the user then increments/decrements the delay words (ADEL-DDEL). The sums of products are successively added to the global sum in the internal accumulator.

Table 3. FIR Filtering with the TMC2249A—Initial Data Loading

Even Data Odd Data Coefﬁcient Storage

Register Position (Hex) A C B D

0 x(31) x(30) h(0) h(1) 1 x(29) x(28) h(2) h(3) 2 x(27) x(26) h(4) h(5) 3 x(25) x(24) h(6) h(7) 4 x(23) x(22) h(8) h(9) 5 x(21) x(20) h(10) h(11) 6 x(19) x(18) h(12) h(13) 7 x(17) x(16) h(14) h(15) 8 x(15) x(14) h(15) h(14)

9 x(13) x(12) h(13) h(12) A x(11) x(10) h(11) h(10) B x(9) x(8) h(9) h(8)

C x(7) x(6) h(7) h(6) D x(5) x(4) h(5) h(4)

E x(3) x(2) h(3) h(2) F x(1) x(0) h(1) h(0)

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00 11

Once all of the products of the desired taps have been summed, the result is available at the output. The user then "pushes" a new time-data sample on to the appropriate even or odd data register "stack" and reiterates the summation. Note that the coefﬁcient bank "pointers", the BDEL and DDEL delay words, are alternately incremented and decremented on successive ﬁlter passes to maintain alignment between the incoming data samples and their respective coefﬁcients.

The effective ﬁlter speed is calculated by dividing the clock rate by one-half the number of taps implemented.

Alternatively , non-symmetric FIR ﬁlters can be implemented using the TMC2249A in a similar fashion. Here, a shift register is used to delay the incoming data fed to the A input by an amount equal to one-half the length of the ﬁlter (the length of the A delay register).

As shown in Figure 5, the data is then sent to the C input, thus "stacking" the A and C delay registers to create a single N-tap FIR ﬁlter. The incremented delay words (ADELDDEL) for all four inputs are identical. Again, the ﬁlter throughput is equal to the clock speed divided by one-half the number of taps implemented.

Figure 5. Non-Symmetric 32-Tap FIR Filtering Using the

TMC2249A

TMC2011A

16-Stage Shift Register

Filter Output

AB CD

x(m+0)

x(m)

h(0) x(m+16) h(16)

x(m+15) h(15) x(m+31)

S

15-0

TMC2249A

h(31)

Table 4. FIR Filtering – Operation Sequence

Notes:

1. If only the 16 MSBs of the result are used, the user may leave RND HIGH and SWAP

low. If the 16 LSBs or all 24 bits of the

result are used, then RND should be set low.

2.

Cycle

Push

AB

Push

C D ADEL CDEL BDEL DDEL ACC ENA ENB ENC END Convolutional Sum

Resultant

Output

1 – – – – 0 0 0 0 L H H H H x(31)•h(0)+x(30)•h(1) See Note 2 2 – – – – 1 1 1 1 H H H H H +x(29)•h(2)+x(28)•h(3) 3 – – – – 2 2 2 2 H H H H H +x(27)•h(4)+x(26)•h(5) 4 – – – – 3 3 3 3 H H H H H +x(25)•h(6)+x(24)•h(7) 5 – – – – 4 4 4 4 H H H H H +x(23)•h(8)+x(22)•h(9) 6 – – – – 5 5 5 5 H H H H H +x(21)•h(10)+x(20)•h(11) 7 – – – – 6 6 6 6 H H H H H +x(19)•h(12)+x(18)•h(13) 8 – – – – 7 7 7 7 H H H H H +x(17)•h(14)+x(16)•h(15)

9 – – – – 8 8 8 8 H H H H H +x(15)•h(15)+x(14)•h(14) 10 – – – – 9 9 9 9 H H H H H +x(13)•h(13)+x(12)•h(12) 11 – – – – A A A A H H H H H +x(11)•h(11)+x(10)•h(10) 12 – – – – B B B B H H H H H +x(9)•h(9)+x(8)•h(8) 13 – – – – C C C C H H H H H +x(7)•h(7)+x(6)•h(6) 14 – – – – D D D D H H H H H +x(5)•h(5)+x(4)•h(4) 15 – – – – E E E E H H H H H +x(3)•h(3)+x(2)•h(2) 16 – – x(32) – F F F F H H H L H +x(1)•h(1)+x(0)•h(0) 17 – – – – 0 0 F F H H H H H +x(31)•h(1)+x(32)•h(0) 18 – – – – 1 1 E E H H H H H +x(29)•h(3)+x(30)•h(2) 19 – – – – 2 2 D D H H H H H +x(27)•h(5)+x(28)•h(4) 20 – – – – 3 3 C C H H H H H +x(25)•h(7)+x(26)•h(6) 21 – – – – 4 4 B B H H H H H +x(23)•h(9)+x(24)•h(8)

•

sxk()hk() xk 16+()hk()+()

K0=

15

∑

=

PRODUCT SPECIFICATION TMC2249A

12 REV. 1.0.2 7/6/00

Complex Arithmetic Functions

The TMC2249A can also be used to perform complex arithmetic functions. The basic function performed by the device, ignoring the delay controls,

SUM = (±A•B) + (±C•D)

can realize in two steps the familiar summation:

(P+jR)(S+jT)=(PS-RT) + j(PT+SR)

(1) (2)

by loading the TMC2249A as follows:

where H and L indicate a logic HIGH and LOW.

Thus we can perform a complex multiplication in two clock cycles. Notice that the user must switch the two components of the second input vector between the B and D inputs to obtain the second complex summation.

Calculating a Butterﬂy

Taking advantage of the complex multiply which we implemented above using the TMC2249A, we can expand slightly to calculate a Radix-2 Butterﬂy, the core of the Fast Fourier Transform algorithm. To review, the Butterﬂy is calculated as shown in Figure 6.

Figure 6. Signal Flow of Radix-2 Butterfly

Where

X=A+B(W

N

r

)

Y=A–B(W

N

r

),

and W

N

r

is the complex phase coefﬁcient, or "twiddle factor"

for the N-point transform, which is:

W

N

r

=e

j(2π/N)

= cos(2π/N) + j(sin(2π/N)) = Re(W) + jIm(W)

with Re and Im indicating the real and imaginary parts of the vector.

Expanding the complex vectors A and B to calculate X and Y, we get:

X = (Re(A)+jlm(A))+(Re(B)Re(W)lm(B)lm(W)+j(Re(B)lm(W)+lm(B)Re(W)))

= (Re(A)+Re(B)Re(W)-

lm(B)lm(W))+j(lm(A)+Re(B)lm(W)+lm(B)Re(W))

= Re(X)+jlm(X)

and,

Y = (Re(A)+jlm(A))-(Re(B)Re(W)lm(B)lm(W)+j(Re(B)lm(W)+lm(B)Re(W)))

= (Re(A)Re(B)Re(W)+lm(B)lm(W))+j(lm(A)-Re(B)lm(W)lm(B)Re(W))

= Re(Y)+jlm(Y)

The butterﬂy is then neatly implemented in four clocks, as follows:

Notice again that the components of the second vector must be switched by the user on the second half of the computation, as well as the parts of the vector presented to the cascade input.

Quadrature Modulation

The TMC2249A can also be used to advantage as a digitaldomain complex frequency synthesizer, as demonstrated in Figure 7.

Here, orthogonal sinusoidal waveforms are generated digitally in the TMC2330A Coordinate Transformer. These quadrature phase coefﬁcients are then multiplied with two input signals, such as digitized analog data.

The TMC2249A then adds these products, which can be output directly to a high-speed digital-to-analog converter such as the Fairchild TDC1012 for direct waveform synthesis. This 12-bit, 20MHz DAC is ideally suited to waveform generation, featuring extremely low glitch energy for low spurious harmonics and distortion.

TMC2249A Inputs

Resultant

Output

Step A B C D NEG1 NEG2

1 P S R T L H (PS-RT) 2 P T R S L L (PT+SR)

XA

B

-1

W

N

r

Y

Step

TMC2249A Inputs

Result-

ant

Output

ABCD

CAS

Input

NEG1 NEG2

1 Re(B) Re(W) Im(B) Im(W) Re(A) L H Re(X) 2 Re(B) Re(W) Im(B) Im(W) Re(A) H L Re(Y) 3 Re(B) Im(W) Im(B) Re(W) Im(A) L L Im(X) 4 Re(B) Im(W) Im(B) Re(W) Im(A) H H Im(Y)

TMC2249A PRODUCT SPECIFICATION

REV. 1.0.2 7/6/00 13

Figure 7. Direct Quadrature Waveform Synthesizer using the TMC2249A and TMC2330A