Datasheet TMC2246AX1 Datasheet (Fairchild Semiconductor)

www.fairchildsemi.com

REV. 1.0.3 9/11/00

Features

• 60 MHz computation rate

• 60 MHz data and coefﬁcient input

• Four 11 x 10-bit multipliers

• Individual data and coefﬁcient inputs

• 25-Bit accumulator

• Fractional and integer two’s complement data formats

• Input and output data latches with user-conﬁgurable enables

• Selectable 16-bit rounded output

• Internal 1/2 LSB rounding

• Available in 120-pin CPGA, PPGA, MPGA, or MQFP

Applications

• Fast pixel interpolation

• Fast image manipulation

• Image mixing and keying

• High-performance FIR ﬁlters

• Adaptive digital ﬁlters

• One- and two-dimensional image processing

Description

The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data. A pipelined architecture, fully registered input and output ports, and asynchronous three-state output enable control simplify the design of complex systems.

The data or coefﬁcient inputs to the multipliers may be held over multiple clock cycles, providing storage for mixing and ﬁltering coefﬁcients. The 25-bit internal accumulator path allows two bits of cumulative word growth and may be internally rounded to 16 bits. Output data are updated every clock cycle, or may be held under user control. All data inputs, outputs, and controls are TTL compatible and (except for the three-state output enable) are registered on the rising edge of CLK.

The TMC2246A is uniquely suited to performing pixel interpolation in image manipulation and ﬁltering applications. As a companion to the Fairchild Semiconductor TMC2301 and TMC2302 Image Manipulation Sequencers, the TMC2246A can execute a bilinear interpolation of an image (4-pixel kernels) at real-time video rates. Larger kernels or other, more complex, functions can be realized with no loss in performance by utilizing multiple devices.

With unrestricted access to all data and coefﬁcient input ports, the TMC2246A offers considerable ﬂexibility in applications performing digital ﬁltering, adaptive FIR ﬁlters, mixers, and other similar systems requiring high-speed processing.

Fabricated in a submicron CMOS process, the TMC2246A operates at a guaranteed clock rate of 60 MHz over the full temperature and supply voltage ranges. It is pin- and function-compatible with Fairchild’s TMC2246, while providing higher speed operation and lower power dissipation. It is available in a 120 pin Plastic Pin Grid Array (PPGA), 120 pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to PPGA (MPGA), and a 120 lead Metric Quad FlatPack (MQFP).

Logic Symbol

D1

9-0

D2

9-0

D3

9-0

D4

9-0

ENB1-4 ENSEL ACC FSEL

OCEN OEN CLK

TMC2246A

Image Filter

C1

10-0

C2

10-0

C3

10-0

C4

10-0

S

15-0

TMC2246A

Image Filter

11 x 10 bit, 60 MHz

PRODUCT SPECIFICATION TMC2246A

2

REV. 1.0.3 9/11/00

Block Diagram

ENB2D1

9-0

D2

9-0

D3

9-0

D4

9-0

C1

10-0

C2

10-0

C3

10-0

C4

10-0

ENB1

ENSEL

ACC

FSEL

*

*Automatic rounding function

OCEN

OEN

S

15-0

ENB3 ENB4

CLK

25

2

-10

LSB MSB

Functional Description

The TMC2246A Image Filter is a ﬂexible multiplier-summer array which computes the accumulated sum of four 11x10 bit products, allowing word growth up to 25 bits.

The inputs are user-conﬁgurable, allowing latching of either the 10- or 11-bit input data. The data format is user-selectable between integer or fractional two’s complement arithmetic. Total latency from input registers to output data port is 5 clocks.

The output data path is 16 bits wide, providing the lower 16 bits of the accumulator when in integer format or the upper 16 bits of the 25-bit accumulator path when fractional two’s complement notation is selected. One-time rounding to 16 bits is performed automatically when accumulating fractional data, but is disabled when operating in integer format to maintain the integrity of the least-signiﬁcant bits.

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00

3

Pin Assignments

120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and 120 Pin Metric Quad FlatPack to 120 Pin Plastic Pin Array, H6 Package

B

A

D

E

F

G

H

J

K

L

M

N

C

12345678910111213

ENSEL ENB2 ENB3 D4

7

D4

5

D4

2

D4

1

C4

10

C4

8

C4

6

C4

3

C4

0

C3

2

ACC FSEL ENB4 D4

9

D4

6

D4

3

D4

0

C4

9

C4

7

C4

4

C4

2

C3

0

C3

5

S

15 OEN CLK ENB1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4

D4

8

D4

4

GND V

DD

C4

5

C4

1

C3

1

C3

3

C3

6

S

13

S

14 OCEN C3

4

C3

7

C3

9

S

11 S

12 GND

C3

8

C3

10

D3

0

S

9 S

10 V

DD D3

1

D3

2

D3

3

S

7 S

8 GND

C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3

Pin Name Pin Name

D3

5

D3

6

D3

4

S

6

S

5

V

DD

GND D3

8

D3

7

S

4

S

3

GND D2

7

D2

9

D3

9

S

2

S

1

D1

8

D2

3

D2

6

D2

8

S

0

D1

7

D1

5

D1

2

C1

9

GND V

DD

C2

0

C2

4

G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9

C2

8

D2

0

D2

4

D2

5

D1

9

D1

4

D1

1

C1

10

C1

7

C1

5

C1

3

C1

0

C2

2

C2

5

C2

9

D2

1

D2

2

D1

6

D1

3

D1

0

C1

8

C1

6

C1

4

C1

2

C1

1

C2

1

C2

3

C2

6

C2

7

C2

10

L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

Pin Name Pin Name

Top View

Cavity Up

KEY

PRODUCT SPECIFICATION TMC2246A

4

REV. 1.0.3 9/11/00

Pin Assignments

120 Lead Metric Quad Flat Pack (KE) Package

C4

4

C4

5

C4

6

C4

7

C4

8

V

DD

C4

9

C4

10

D4

0

GND D4

1

D4

2

D4

3

D4

4

D4

5

D4

6

D4

7

D4

8

D4

9

ENB3 ENB2 ENB1 ENB4 ENSEL

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

Pin Name

CLK FSEL ACC OCEN OEN S

15

S

14

GND S

13

S

12

S

11

V

DD

S

10

S

9

S

8

GND S

7

S

6

S

5

V

DD

S

4

S

3

S

2

GND

1

120

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

S

1

S

0

D1

9

D1

8

D1

7

D1

6

D1

5

D1

4

D1

3

D1

2

D1

1

D1

0

C1

10

C1

9

C1

8

C1

7

C1

6

GND C1

5

C1

4

C1

3

V

DD

C1

2

C1

1

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Pin Name Pin Name

C1

0

C2

0

C2

1

C2

2

C2

3

C2

4

C2

5

C2

6

C2

7

C2

8

C2

9

C2

10

D2

0

D2

1

D2

2

D2

3

D2

4

D2

5

D2

6

D2

7

D2

8

D2

9

D3

9

GND

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

D3

8

D3

7

D3

6

D3

5

D3

4

D3

3

D3

2

D3

1

D3

0

C3

10

C3

9

C3

8

C3

7

C3

6

C3

5

C3

4

C3

3

C3

2

C3

1

C3

0

C4

0

C4

1

C4

2

C4

3

73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Pin Name Pin Name

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00

5

Pin Descriptions

Pin Name

Pin Number

Pin Function Description

CPGA/PPGA/

MPGA

MQFP

Power

V

DD

F3, H3, L7, C8 12, 20, 46, 102 Supply Voltage. The TMC2246A operates from a single +5V

supply. All power and ground pins must be connected.

GND E3, G3, J3, L6,

H11, C7

8, 16, 24, 42,

72, 106

Ground. The TMC2246A operates from a single +5V supply. All

power and ground pins must be connected.

Clock

CLK C3 1

System Clock. The TMC2246A operates from a single master

clock input. The rising edge of clock strobes all enabled registers. All timing specifications are referenced to the rising edge of CLK.

Inputs

D1

9-0

M1, K3, L2, N1, L3, M2, N2, L4,

M3, N3

27, 28, 29, 30, 31, 32, 33, 34,

35, 36

Data Input Ports. D1 through D4 are the 10-bit data input ports.

The LSB is Dx

0

.

D2

9-0

J12, K13, J11, K12, L13, L12,

K11, M13, M12,

L11

70, 69, 68, 67, 66, 65, 64, 63,

62, 61

D3

9-0

J13, H12, H13,

G12, G11, G13,

F13, F12, F11,

E13

71, 73, 74, 75, 76, 77, 78, 79,

80, 81

D4

9-0

B4, C5, A4, B5, A5, C6, B6, A6,

A7, B7

115, 114, 113, 112, 111, 110, 109, 108, 107,

105

C1

10-0

M4, L5, N4, M5,

N5, M6, N6, M7,

N7, N8, M8

37, 38, 39, 40, 41, 43, 44, 45,

47, 48, 49

Coefficient Input Ports. C1 through C4 are the 11-bit coefficient

input ports. The LSB is Cx

0

.

C2

10-0

N13, M11, L10,

N12, N11, M10,

L9, N10, M9,

N9, L8

60, 59, 58, 57, 56, 55, 54, 53,

52, 51, 50

C3

10-0

E12, D13, E11, D12, C13, B13, D11, C12, A13,

C11, B12

82, 83, 84, 85, 86, 87, 88, 89,

90, 91, 92

C4

10-0

A8, B8, A9, B9,

A10, C9, B10,

A11, B11, C10,

A12

104, 103, 101,

100, 99, 98, 97,

96, 95, 94, 93

Outputs

S

15-0

C1, D2, D1, E2,

E1, F2, F1, G2, G1, H1, H2, J1,

J2, K1, K2, L1

6, 7, 9, 10, 11, 13, 14, 15, 17, 18, 19, 21, 22,

23, 25, 26

Sum Output. The current 16-bit result is available at the Sum

output. The LSB is S

0

. See the Functional Block Diagram .

PRODUCT SPECIFICATION TMC2246A

6

REV. 1.0.3 9/11/00

Note:

1. X denotes a "Don't Care" condition.

2. Any register not explicitly held is updated on the next rising edge of CLK.

Controls

FSEL B2 2

Format Select. Coefficients input during the current clock are

assumed to be in fractional two's complement format. Rounding to 16 bits is performed as determined by the accumulator control, ACC, and the upper 16 bits of the accumulator are output when the registered Format Select input (FSEL) is LOW. When FSEL is HIGH, two's complement integer format is assumed, and the lower 16 bits of the accumulator are presented at the output. No rounding is performed when operating in integer mode. See the Functional Block Diagram and the Applications Discussion.

ENSEL A1 120

Enable Select. The registered Enable Select determines whether

the data or the coefficient input registers may be held on the next rising edge of clock, in conjunction with the individual input enables ENB1–ENB4. See Table 1.

ENB1– ENB4

C4, A2, A3, B3 118, 117, 116,

119

Input Enables. When ENBi (i=1, 2, 3, or 4) is LOW, registers Ci

and Di are both strobed by the next rising edge of CLK. When ENBi is HIGH and ENSEL is LOW, Di is strobed, but Ci is held. When ENBi and ENSEL are both HIGH, Di is held and Ci is strobed. See Table 1. Thus, either or both input registers to each multiplier are updated on each clock cycle.

ACC B1 3

Accumulate. When the registered ACCumulator control is LOW,

no internal accumulation will be performed on the data input during the current clock, effectively clearing the prior accumulated sum. If operating in fractional two's complement format (FSEL = LOW), one-half LSB rounding to 16 bits is performed on the result. This allows the user to perform summations without propagating roundoff errors.

When ACC is HIGH, the internal accumulator adds the emerging products to the sum of previous products, without performing additional rounding.

OCEN

D3 4

Output Register Enable. The output of the accumulator is

latched into the output register on the next clock when the Output Register Clock Enable is LOW. When OCEN is HIGH the contents of the output register remain unchanged; however, accumulation will continue internally if ACC remains HIGH.

OEN

C2 5

Output Enable. Data currently in the output registers is available

at the output bus S

15-0

when the asynchronous Output Enable is

LOW. When OEN

is HIGH, the outputs are in the high-impedance

state.

No Connect

NC D4 (Index Pin) Not Connected. (Optional)

Pin Descriptions

(continued)

Pin Name

Pin Number

Pin Function Description

CPGA/PPGA/

MPGA

MQFP

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00

7

Table 1. Input Register Control

Data Formats

Note: A minus sign indicates the sign bit.

Figure 1. Data Formats

ENB1-4

ENSEL Input Register Held

1

1 Data i 1 0 Coefﬁcient i 0 X None

Fractional Two’s Complement Format (FSEL = LOW)

1514131211109876543210 BIT

-2

0

.2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

2

-8

2

-9

DATA (D1-4)

-2

1

2

0

.2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

2

-8

2

-9

COEFFICIENT (C1-4)

-2

6

2

5

2

4

2

3

2

1

2

0

.2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

2

-8

2

-9

SUM

Integer Two’s Complement Format (FSEL = HIGH)

1514131211109876543210 BIT

-2

9

2

8

2

7

2

6

2

5

2423222120. DATA (D1-4)

-21029282726252423222120. COEFFICIENT (C1-4)

-21521421321221121029282726252423222120. SUM

Integer Two’s Complement Data / Fractional Two’s Complement Coefﬁcient Format (FSEL = LOW)

1514131211109876543210BIT

-29282726252423222120. DATA (D1-4)

-2120.2-12-22-32-42-52-62-72-82-9COEFFICIENT (C1-4)

-21521421321221121029282726252423222120. SUM

Equivalent Circuits and Threshold Levels

Figure 2. Equivalent Digital Input Circuit

Figure 3. Equivalent Digital Output Circuit

Data or Control Input

V

DD

p

n

GND

V

DD

p

n

GND

Output

PRODUCT SPECIFICATION TMC2246A

8 REV. 1.0.3 9/11/00

Figure 4. Threshold Levels for Three-State Measurement

Absolute Maximum Ratings (beyond which the device may be damaged)

1

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

Operating Conditions

Parameter Min Max Unit

Supply Voltage -0.5 7.0 V Input Voltage -0.5 V

DD

+ 0.5 V

Output, Applied Voltage

2

-0.5 VDD + 0.5 V

Output, Externally Forced Current

3,4

-3.0 6.0 mA Output, Short Circuit Duration (single output in HIGH state to ground) 1 sec Operating, Ambient Temperature -20 110 °C Junction Temperature 140 °C Storage Temperature -65 150 °C Lead Soldering (10 seconds) 300 °C

Parameter Min Nom Max Units

V

DD

Power Supply Voltage 4.75 5.0 5.25 V

f

CLK

Clock frequency TMC2246A 30 MHz

TMC2246A-1 40 MHz TMC2246A-2 60 MHz

t

PWH

CLK pulse width, HIGH 8 ns

t

PWL

CLK pulse width, LOW 6 ns

t

S

Input Data Set-up Time 6 ns

t

H

Input Data Hold Time 1.5 ns

V

IH

Input Voltage, Logic HIGH 2.0 V

V

IL

Input Voltage, Logic LOW 0.8 V

I

OH

Output Current, Logic HIGH -2.0 mA

I

OL

Output Current, Logic LOW 4.0 mA

T

A

Ambient Temperature, Still Air 0 70 °C

2.0V

0.8V

t

DIS

t

ENA

Three-State Outputs

OEN

High Impedance

0.5V

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00 9

Electrical Characteristics

Switching Characteristics

Note:

1. All transitions are measured at a 1.5V level except for t

ENA

and t

DIS

.

Parameter Conditions Min Typ Max Units

I

DD

Total Power Supply Current V

DD

= Max, C

LOAD

= 25pF, f

CLK

= Max TMC2246A 95 mA TMC2246A-1 120 mA TMC2246A-2 170 mA

I

DDU

Power Supply Current, Unloaded

V

DD

= Max, OEN = HIGH, f

CLK

= Max TMC2246A 80 mA TMC2246A-1 100 mA TMC2246A-2 140 mA

I

DDQ

Power Supply Current, Quiescent

V

DD

= Max, CLK = LOW 5 mA

C

I/O Pin Capacitance 5 pF

I

IH

Input Current, HIGH VDD = Max, VIN = V

DD

±10 µA

I

IL

Input Current, LOW VDD = Max, VIN = 0 V ±10 µA

I

OZH

Hi-Z Output Leakage Current, Output HIGH

VDD = Max, VIN = V

DD

±10 µA

I

OZL

Hi-Z Output Leakage Current, Output LOW

VDD = Max, VIN = 0 V ±10 µA

I

OS

Short-Circuit Current -20 -80 mA

V

OH

Output Voltage, HIGH S

15-0

, IOH = Max 2.4 V

V

OL

Output Voltage, LOW S

15-0

, IOL = Max 0.4 V

Parameter Conditions

1

Min Typ Max Units

t

DO

Output Delay Time C

LOAD

= 25 pF 14 ns

t

HO

Output Hold Time C

LOAD

= 25 pF 4 ns

t

ENA

Three-State Output Enable Delay C

LOAD

= 0 pF 10 ns

t

DIS

Three-State Output Disable Delay C

LOAD

= 0 pF 10 ns

PRODUCT SPECIFICATION TMC2246A

10 REV. 1.0.3 9/11/00

Application Notes

Typical Operation

The versatile input clock enables and unrestricted data and coefﬁcient inputs provided on the TMC2246A allow considerable ﬂexibility in numerous image and signal processing architectures.

Table 2 shows a typical sequence of operations which clariﬁes the inherent latencies of the device and illustrates ﬁxed coefﬁcient storage, product accumulation, and device reconﬁguration prior to beginning a new accumulation. This assumes that the device is set to fractional two’s complement mode (FSEL = LOW) with OCEN

= LOW, OEN = LOW, and the input registers conﬁgured to hold coefﬁcients only (ENSEL = LOW). X= “don’t care.”

Using the TMC2246A for Pixel Interpolation

As a companion product to the TMC2301 Image Resampling Sequencer, the TMC2246A offers an excellent tool for performing high-speed pixel interpolation and image ﬁltering.

Any pixel resampling operation with multiple-pixel kernels must utilize some parallel-processing technique, such as memory banding, to maintain high-speed image throughput rates. Memory banding utilizes adders to generate parallel offset addresses, allowing the user to access multiple pixel locations simultaneously. Using such techniques, one TMC2246A can perform bilinear interpolation (four-pixel kernel) with no loss in system performance.

Larger kernels can be realized in similar systems with additional TMC2246As. Figure 5 illustrates a basic pixel interpolation application.

Timing Diagram

CLK

D1-4

9-0

CONTROLS

1

S

15-0

2

DA DB

54321

SA

1/f

CLK

t

S

t

H

t

PWH

t

DO

t

HO

t

PWKL

6

C1-4

10-0

CA

CB

Notes:

1. Except OEN.

2. Assumes OEN = LOW.

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00 11

Table 2. Typical TMC2246A Operation Sequence

Notice in this example, operating in fractional two’s complement mode, that rounding is imposed on the first cycle only of an accumulation. This avoids the propagation of accumulated roundoff errors.

CLK D1 C1 ENB1 D2 C2 ENB2 D3 C3 ENB3 D4 C4 ENB4 ACC Sum

0--0--0--0--0- 1 D1(1) C1(1) 1 D2(1) C2(1) 1 D3(1) C3(1) 1 D4(1) C4(1) 1 0 2 D1(2) X 0 D2(2) C2(2) 0 D3(2) X 1 D4(2) X 1 1 3 D1(3) C1(3) 0 D2(3) C2(3) 0 D3(3) X 0 D4(3) X 0 1 4 D1(4) C1(4) - D2(4) C2(4) - D3(4) C3(4) - D4(4) C4(4) - 0 5 S(5)=D1(1)C1(1)+D2(1)C2(1)

+D3(1)C3(1)+D4(1)C4(1)+ 2

-10

6 S(6)=S(5)+D1(2)C1(1)+D2(2)C2(1)

+D3(2)C3(1)+D4(2)C4(1)

7 S(7)=S(6)+D1(3)C1(3)+D2(3)C2(3)

+D3(3)C3(1)+D4(3)C4(1)

8 S(8)=D1(4)C1(4)+D2(4)C2(4)

+D3(4)C3(4)+D4(4)C4(4)+2

-10

PRODUCT SPECIFICATION TMC2246A

12 REV. 1.0.3 9/11/00

Figure 5. Bilinear Interpolation Using the TMC2246A

“X”

SADR

7-4

SADR

23-8

SADR

23-8

TADR

11-0

TADR

11-0

“Y”

TMC2302A TMC2302A

SADR

7-4

ADDR

X,Y

DOUT

ADDR

X+1,Y

DOUT

ADDR

X,Y+1

DOUT

ADDR

X+1,Y+1

DOUT

TMC2246A

D1 D2 D3 D4

C1 C2 C3 C4

S

15-0

Address

Offset

Adders

Banded Source Image RAM

Banded Interpolation Coefficient ROM

Interpolated Pixel Data

TMC2011A Pipeline

Delay Register

D

IN

D

OUT

ADDR

Target Image RAM

To Display

U,VAddress

+1

TMC2246A Applications in Digital Filtering

Unrestricted access to all input ports of the TMC2246A allows the user considerable ﬂexibility in realizing numerous digital ﬁlter architectures. Figure 6 illustrates how the device may be utilized as a ﬂexible high-speed FIR ﬁlter with the ability to modify all of the ﬁlter coefﬁcients dynamically or to store a ﬁxed set if desired.

Longer ﬁlters, with more taps, are realized by including an external adder (such as the common 74381 type) to cascade multiple TMC2246As. Alternatively, two additional taps and a cascading adder are available in the Fairchild TMC2249A Digital Mixer.

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00 13

Figure 6. Using the TMC2246A For FIR Filtering

Related Products

• TMC2301 Image Resampling Sequencer

• TMC2302A Image Manipulation Sequencer

• TMC2249A Video Mixer

• TMC2242B Half-Band Filter

TMC2246A

S

15-0

TMC2246A

S

15-0

+

++

Data

Coefficients Select

Filter Output

PRODUCT SPECIFICATION TMC2246A

14 REV. 1.0.3 9/11/00

Mechanical Dimensions

120-Lead CPGA Package

D

Pin 1 Identifier

Top View

Cavity Up

D1

P

L

A2

A

øB

e

øB2

A1

A .080 .160 2.03 4.06

Symbol

Inches

Min. Max. Min. Max.

Millimeters

Notes

A1 .040 .060 1.01 1.53

.215 5.46

A2 .125 3.17 øB .016 .020 0.40 0.51

D 1.340 1.380 33.27 35.05

2 2

SQ

D1

.110 .145 2.79 3.68

e

.050 NOM. 1.27 NOM.

1.200 BSC 30.48 BSC .100 BSC 2.54 BSC

L L1 .170 .190 4.31 4.83

.003 — .076 —

M13 13

120 120

3 4

N P

øB2

Notes:

1.

2.

3.

4.

5.

6.

Pin #1 identifier shall be within shaded area shown. Pin diameter excludes solder dip finish. Dimension "M" defines matrix size. Dimension "N" defines the maximum possible number of pins. Orientation pin is at supplier's option. Controlling dimension: inch.

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00 15

Mechanical Dimensions

120-Lead PPGA Package

D

Pin 1 Identifier

Top View Cavity Up

D1

P

L

A2

A

øB

e

øB2

A1

A .080 .160 2.03 4.06

Symbol

Inches

Min. Max. Min. Max.

Millimeters

Notes

A1 .040 .060 1.01 1.53

.215 5.46

A2 .125 3.17 øB .016 .020 0.40 0.51

D 1.340 1.380 33.27 35.05

2 2

SQ

D1

.110 .145 2.79 3.68

e

.050 NOM. 1.27 NOM.

1.200 BSC 30.48 BSC .100 BSC 2.54 BSC

L L1 .170 .190 4.31 4.83

.003 — .076 —

M13 13

120 120

3 4

N P

øB2

Notes:

1.

2.

3.

4.

5.

6.

Pin #1 identifier shall be within shaded area shown. Pin diameter excludes solder dip finish. Dimension "M" defines matrix size. Dimension "N" defines the maximum possible number of pins. Orientation pin is at supplier's option. Controlling dimension: inch.

PRODUCT SPECIFICATION TMC2246A

16 REV. 1.0.3 9/11/00

Mechanical Dimensions

120-Lead Metric Quad Flat Package to Pin Grid Array Package (MPGA)

D

Pin 1 Identifier

Fairchild

TMC2249A

D1

A

A2

L

e

øB

øB2

A1

A3

e

A .309 .311 7.85 7.90

Symbol

Inches

Min. Max. Min. Max.

Millimeters

Notes

A1 .145 .155 3.68 3.94

.090 2.29

A2 A3

.080 2.03

øB .016 .020 0.40 0.51

D 1.355 1.365 34.42 34.67

2 2

SQ

D1

.175 .185 4.45 4.70

e

.050 NOM. 1.27 NOM.

.050 TYP. 1.27 TYP.

1.200 BSC 30.48 BSC .100 BSC 2.54 BSC

L M13 13

120 120

3 4

N

øB2

Notes:

1.

2.

3.

4.

5.

6.

Pin #1 identifier shall be within shaded area shown. Pin diameter excludes solder dip finish. Dimension "M" defines matrix size. Dimension "N" defines the maximum possible number of pins. Orientation pin is at supplier's option. Controlling dimension: inch.

TMC2246A PRODUCT SPECIFICATION

REV. 1.0.3 9/11/00 17

Mechanical Dimensions

120-Lead MQFP Package

α

D

D1

E1

E

e

PIN 1 IDENTIFIER

A2

A1

A

B

Base Plane

Seating Plane

See Lead Detail

C

0° Min.

R

0.063" Ref (1.60mm)

Lead Detail

L

.20 (.008) Min.

.13 (.005) R Min.

-C-

ccc

C

LEAD COPLANARITY

Notes:

1.

2.

3.

4.

5.

All dimensions and tolerances conform to ANSI Y14.5M-1982. Controlling dimension is millimeters. Dimension "B" does not include dambar protrusion. Allowable

dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot.

"L" is the length of terminal for soldering to a substrate. "B" & "C" includes lead finish thickness.

A — .154 — 3.92

Symbol

Inches

Min. Max. Min. Max.

Millimeters

Notes

A1 .010 — .25 —

.018 .45

A2 .125 .144 3.17 3.67 B .012 3, 5.30

.009 .23

C .005 .13

D1/E1 1.098 1.106 27.90 28.10

.0315 BSC .80 BSC

e L .026 .037 .65 .95

120 120

30 30

4

5

N ND

α 0° 7° 0° 7°

— .004 — .10

ccc

D/E 1.219 1.238 30.95 31.45

.13/.30 .005/.012

PRODUCT SPECIFICATION TMC2246A

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

9/11/00 0.0m 002

Stock#DS30002246A

 2000 Fairchild Semiconductor Corporation

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Product Number

Temperature

Range

Speed Grade

Screening Package

Package

Marking

TMC2246AG1C 0°C to 70°C 30 MHz Commercial 120 Pin Ceramic Pin Grid Array 2246AG1C TMC2246AG1C1 0°C to 70°C 40 MHz Commercial 120 Pin Ceramic Pin Grid Array 2246AG1C1 TMC2246AG1C2 0°C to 70°C 60 MHz Commercial 120 Pin Ceramic Pin Grid Array 2246AG1C2

TMC2246AH5C 0°C to 70°C 30 MHz Commercial 120 Pin Plastic Pin Grid Array 2246AH5C TMC2246AH5C1 0°C to 70°C 40 MHz Commercial 120 Pin Plastic Pin Grid Array 2246AH5C1 TMC2246AH5C2 0°C to 70°C 60 MHz Commercial 120 Pin Plastic Pin Grid Array 2246AH5C2

TMC2246AH6C 0°C to 70°C 30 MHz Commercial 120 Lead Metric Quad Flat Pack

to Pin Grid Array

N/A

TMC2246AH6C1 0°C to 70°C 40 MHz Commercial 120 Lead Metric Quad Flat Pack

to Pin Grid Array

N/A

TMC2246AH6C2 0°C to 70°C 60 MHz Commercial 120 Lead Metric Quad Flat Pack

to Pin Grid Array

N/A

TMC2246AKEC 0°C to 70°C 30 MHz Commercial 120 Lead Metric Quad FlatPack 2246AKEC TMC2246AKEC1 0°C to 70°C 40 MHz Commercial 120 Lead Metric Quad FlatPack 2246AKEC1 TMC2246AKEC2 0°C to 70°C 60 MHz Commercial 120 Lead Metric Quad FlatPack 2246AKEC2