The third generation of MESH O VERLAY™ Power
MOSFETs for very high voltage exhibits unsurpassed on-resistance per unit area while integrating
back-to-back Zener diodes between gate and
source. Such arrangement gives extra ESD capability with higher ruggedness performance as requested by a large variety of single-switch applications.
APPLICATIONS
■ SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
■ WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
STU10NC70ZSTU10NC70ZI
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
I
GS
V
ESD(G-S)
dv/dt(
V
ISO
T
stg
T
(•)Pu l se width limited by safe operating area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
700V
700V
Gate- source Voltage±25V
(1)
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
Drain Current (pulsed)37.637.6(*)A
Total Dissipation at TC = 25°C
VDD = 100V, Tj = 150°C
(see test circuit, Figure 5)
34ns
72100nC
34ns
1.6V
660ns
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)25V
Voltage
α
TVoltage Thermal CoefficientT=25°C Note(3)1.3
I
RzDynamic Resistance
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c yc l e 1.5 %.
2. Pulse width li mited by safe operating area.
3. ∆
= αT (25°-T) BV
V
BV
GSO
(25°)
= 50 mA, VGS = 0
GS
90
10
-4
/°C
Ω
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specif ically been designed to enhanc e not only t he dev ice’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the 25V Zener voltage is appropiate to achieve an efficient and
cost-effective intervention to protect the device’s int egrity. These integrated Zener diode s thus avoid the
usage of external components.
3/10
Page 4
STU10NC70Z/STU10NC70ZI
Safe Operating Area For I-Max2 20Safe Operating Area For Max220
Thermal Impedance For Max220Thermal Impedance For I-Max220
Output Characteristics
4/10
Transfer Characteristics
Page 5
STU10NC70Z/STU10NC70ZI
Transconductance
Gate Charge vs Gate-source Voltage
Static Drain-source On Resistance
Capacitance Variations
Normalized On Resistance vs Temperatur eNormalized Gate Threshold Volta ge vs Temp.
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