Page 1
STN2NE10L
N-CHANNEL 100V - 0.33Ω - 2A SOT-223
STripFET POWER MOSFET
TYPE V
DSS
R
DS(on)
I
D
ST N2NE10L 100 V < 0. 4 Ω 1.8 A
■ TYPICALR
■ EXCEPTIONALdv/dtCAPABILITY
■ AVALANCHERUGGEDTECHNOLOGY
■ 100 % AVALANCHETESTED
■ LOW THRESHOLDDRIVE
DS(on)
= 0.33 Ω
DESCRIPTION
This Power Mosfet is the latest development of
STMicroelectronics unique ”Single Feature
Size” stip-based process. The resulting transistor shows extremely high packing density forlow
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a remarkablemanufacturingreproducibility.
APPLICATIONS
■ DC MOTOR CONTROL(DISK DRIVES,etc.)
■ DC-DC& DC-AC CONVERTERS
■ SYNCHRONOUSRECTIFICATION
2
3
2
1
SOT-223
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Uni t
V
V
V
I
DM
P
dv/ dt (
T
(•) Pulse width limited by safe operating area (1)ISD≤ 7.2 A, di/dt ≤ 200 A/µs,VDD≤ V
March 2000
Drain-source Voltage (VGS= 0) 100 V
DS
Drain- gate Volt age (RGS=20kΩ) 100 V
DGR
Gate-source Voltage ± 20 V
GS
Drain Current (continuous ) at Tc=25oC1.8A
I
D
Drain Current (continuous ) at Tc=100oC1.3A
I
D
(•) Drain Current (pulsed) 7.2 A
Total Dissipation at Tc=25oC2.5W
tot
Derat ing Factor 0.02 W/
) Peak Diode Re c overy volt age s lope 6 V/ns
1
Sto rage Temperature -65 t o 150
stg
Max. Operating Junct ion Temperat ur e 150
T
j
(BR)DSS,Tj≤TJMAX
o
C
o
C
o
C
1/8
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STN2NE10L
THERMAL DATA
R
thj-pcb
R
thj-amb
T
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
Ther mal Resistanc e Junct ion-PC Board Max
Ther mal Resistanc e Junct ion-ambient Max
(Surface Mounted)
Maximum Lead Te m perature For Soldering Purpos e
l
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
Single Pulse Avalanche Energy
AS
(starting T
=25oC, ID=IAR,VDD=25V)
j
max)
j
50
60
260
1.8 A
20 mJ
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unless otherwisespecified)
(T
case
OFF
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID=250µAVGS= 0 100 V
Break dow n Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gat e- bod y Leakage
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRating Tc= 125oC
V
DS
V
=± 20 V
GS
1
10
100 nA
±
ON(∗)
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
I
D(on)
Gate Threshold Voltage VDS=VGSID= 250 µA11.72.5V
Sta t ic Dr ain -s ource On
Resistance
VGS=10V ID=1A
=5V ID=1A
V
GS
On State Drain Current VDS>I
D(on)xRDS(on )max
0.33
0.38
1.8 A
0.4
0.45
VGS=10V
DYNAMIC
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
g
(∗)Forward
fs
Tr ansc on duc tance
C
C
C
Input C apac i t ance
iss
Out put Capacitanc e
oss
Reverse T r ansfer
rss
Capacit a nc e
VDS>I
D(on)xRDS(on )maxID
=1A 1 3 S
VDS=25V f=1MHz VGS= 0 V 345
45
20
µ
µA
Ω
Ω
pF
pF
pF
A
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Page 3
STN2NE10L
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHINGON
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
t
d(on)
Tur n-on Delay Time
Rise T i me
t
r
VDD=50V ID=3.5A
R
=4.7
G
Ω
VGS=5V
7
17
(Resis t iv e Load, see f ig. 3)
Q
Q
Q
Tot al G at e Char ge
g
Gat e- Source Charge
gs
Gate-Drain Charge
gd
VDD=80V ID=7A VGS=5V 10
5
4
14 nC
SWITCHINGOFF
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
t
d(off)
Tur n-of f Delay Time
t
Fall T ime
f
VDD=80V ID=3.5A
R
G
=4.7
Ω
VGS=5V
22
8
(Resis t iv e Load, see f ig. 3)
t
r(Voff)
t
t
Off-volt age R ise Time
Fall T ime
f
Cross-over T ime
c
VDD=80V ID=7A
R
=4.7
G
Ω
VGS=5V
(Indu ct iv e L oad , see f ig . 5)
8
9
19
SOURCEDRAINDIODE
Symbol Parameter Test Condit ions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Source-drain Current
(•)
Source-drain Current
2
8
(pulsed)
(∗)ForwardOnVoltage ISD=2A VGS=0 1.5 V
Reverse Re covery
rr
Time
Reverse Re covery
rr
ISD= 7 A di/dt = 100 A/µs
=30V TJ=150oC
V
DD
(see test circuit, fig. 5)
75
190
Charge
Reverse Re covery
5
Current
ns
ns
nC
nC
ns
ns
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating Area ThermalImpedance
3/8
Page 4
STN2NE10L
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/8
CapacitanceVariations
Page 5
STN2NE10L
NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
5/8
Page 6
STN2NE10L
Fig. 1:
UnclampedInductiveLoad TestCircuit
Fig. 3: Switching Times Test CircuitsFor
ResistiveLoad
Fig. 2:
UnclampedInductiveWaveform
Fig. 4: Gate Charge test Circuit
Fig. 5:
Test CircuitFor InductiveLoad Switching
And Diode Recovery Times
6/8
Page 7
SOT-223 MECHANICALDATA
STN2NE10L
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a 2.27 2.3 2.33 89.4 90.6 91.7
b 4.57 4.6 4.63 179.9 181.1 182.3
c 0.2 0.4 0.6 7.9 15.7 23.6
d 0.63 0.65 0.67 24.8 25.6 26.4
e1 1.5 1.6 1.7 59.1 63 66.9
e4 0.32 12.6
f 2.9 3 3.1 114.2 118.1 122.1
g 0.67 0.7 0.73 26.4 27.6 28.7
l1 6.7 7 7.3 263.8 275.6 287.4
l2 3.5 3.5 3.7 137.8 137.8 145.7
L 6.3 6.5 6.7 248 255.9 263.8
mm mils
L
e1
a
b
f
C
l1
BE
C
g
d
l2
c
e4
P008B
7/8
Page 8
STN2NE10L
Information furnishedis believedto beaccurate and reliable.However, STMicroelectronics assumes no responsibilityfor the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under anypatent or patent rights ofSTMicroelectronics. Specificationmentioned in this publicationare
subjecttochange withoutnotice.This publication supersedes andreplaces all information previouslysupplied. STMicroelectronics products
are not authorized for use as critical components in lifesupportdevices or systems without express written approvalof STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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8/8
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