Datasheet NDS9956 Datasheet (Fairchild Semiconductor)

February 1996

N

NDS9956A

Dual N-Channel Enhancement Mode Field Effect Transistor

General Description Features

These N-Channel enhancement mode power field effect
transistors are produced using National's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as DC/DC conversion and DC motor
control where fast switching, low in-line power loss, and
resistance to transients are needed.

________________________________________________________________________________

3.7A, 30V. R
High density cell design for extremely low R

= 0.08Ω @ VGS = 10V

DS(ON)

DS(ON)

.

High power and current handling capability in a widely used
surface mount package.

Dual MOSFET in surface mount package.

4

3

2

1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

5

6

7

8

Symbol Parameter NDS9956A Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ± 20 V
Drain Current - Continuous (Note 1a) ± 3.7 A

- Pulsed ± 15

P

D

Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θ

R

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

JC

NDS9956A.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV
I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Zero Gate Voltage Drain Current

VDS = 24 V, V

GS

= 0 V

2 µA
TJ = 55°C

25 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.7 2.8 V

TJ = 125°C 0.7 1.2 2.2

R

DS(ON)

Static Drain-Source On-Resistance

VGS = 10 V, ID = 2.2 A

TJ = 125°C

0.06 0.08

0.08 0.13

Ω

VGS = 4.5 V, ID = 1.0 A 0.08 0.11

0.11 0.18

15 A

3.5
6 S

I

g

D(on)

TJ = 125°C

On-State Drain Current

VGS = 10 V, VDS = 10 V
VGS = 4.5 V, VDS = 10 V

FS

Forward Transconductance

VDS = 15 V, ID = 3.7 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance 225 pF

VDS = 10 V, VGS = 0 V,
f = 1.0 MHz

Reverse Transfer Capacitance 85 pF

320 pF

SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A,

V

= 10 V, R

Turn - On Rise Time 13 20 ns

GEN

GEN

= 6 Ω

10 20 ns

Turn - Off Delay Time 21 50 ns
Turn - Off Fall Time 5 50 ns
Total Gate Charge VDS = 10 V,
Gate-Source Charge 1.5 nC

ID = 3.7 A, VGS = 10 V

9.5 27 nC

Gate-Drain Charge 3.3 nC

NDS9956A.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

t

rr

Notes:

1. R

P

design while R

D

Typical R

Maximum Continuous Drain-Source Diode Forward Current 1.2 A
Drain-Source Diode Forward Voltage

VGS = 0 V, IS = 1.25 A

(Note 2)

0.8 1.3 V

Reverse Recovery Time VGS = 0 V, IF = 1.25 A, dIF/dt = 100 A/µs 100 ns

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

−T

T

A

J

=

R

θJA

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

θ

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.

J−TA

=

(t )

R

θJC+RθCA

1a

2

= I

(t ) ×R

DS(ON ) T

D

(t)

J

1b

1c

is guaranteed by

JC

θ

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDS9956A.SAM

Typical Electrical Characteristics

20

15

10

5

D

I , DRAIN-SOURCE CURRENT (A)

0

0 1 2 3

V =10V

GS

8.0

6.0

V , DRAIN-SOURCE VOLTAGE (V)

DS

5.0

4.5

4.0

3.5

3.0

3

V = 3.5V

2.5

GS

4.0

2

1.5

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5
0 3 6 9 12 15

I , DRAIN CURRENT (A)

D

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate

Voltage and Drain Current.

1.6

I = 3.7A

1.4

1.2

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

D

V = 10V

GS

1

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

2

V = 10 V

GS

1.5

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5
0 3 6 9 12 15

I , DRAIN CURRENT (A)

D

4.5

5.0

T = 125°C

J

25°C

6.0

8.0

-55°C

10

Figure 3. On-Resistance Variation with

Temperature.

10

V = 10V

DS

8

6

4

D

I , DRAIN CURRENT (A)

2

0

1 2 3 4 5

V , GATE TO SOURCE VOLTAGE (V)

GS

T = -55°C

J

125°C

Figure 5. Transfer Characteristics.

25°C

Figure 4. On-Resistance Variation with Drain

Current and Temperature.

1.2

V = V

1.1

1

0.9

th

V , NORMALIZED

0.8

0.7

GATE-SOURCE THRESHOLD VOLTAGE

0.6

-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)

J

DS GS

I = 250µA

D

Figure 6. Gate Threshold Variation with

Temperature.

NDS9956A.SAM

T , JUNCTION TEMPERATURE (°C)

Typical Electrical Characteristics

1.12

I = 250µA

D

1.08

1.04

1

DSS

BV , NORMALIZED

0.96

DRAIN-SOURCE BREAKDOWN VOLTAGE

0.92

-50 -25 0 25 50 75 100 125 150

J

Figure 7. Breakdown Voltage Variation with

Temperature.

1000

800

500

300

200

CAPACITANCE (pF)

100

50

f = 1 MHz
V = 0V

GS

0.1 0.2 0.5 1 2 5 10 30
V , DRAIN TO SOURCE VOLTAGE (V)

DS

Figure 9. Capacitance Characteristics.

10

V = 0V

GS

5

1

T = 125°C

0.5

0.1

0.01

S

I , REVERSE DRAIN CURRENT (A)

0.001

J

0.2 0.4 0.6 0.8 1 1.2 1.4
V , BODY DIODE FORWARD VOLTAGE (V)

SD

25°C

-55°C

Figure 8. Body Diode Forward Voltage Variation

with Current and Temperature.

10

I = 3.7A

D

8

C

iss

C

oss

C

rss

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 2 4 6 8 10 12

Q , GATE CHARGE (nC)

g

V = 10V

DS

20V

15V

Figure 10. Gate Charge Characteristics.

10

V =10V

DS

8

6

4

2

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

0 2 4 6 8 10

I , DRAIN CURRENT (A)

D

Figure 11. Transconductance Variation with Drain

Current and Temperature.

T = -55°C

J

25°C

125°C

NDS9956A.SAM

Typical Thermal Characteristics

2.5

2

1.5

1b

1

1c

0.5

STEADY-STATE POWER DISSIPATION (W)

0 0.2 0.4 0.6 0.8 1

2oz COPPER MOUNTING PAD AREA (in )

Total Power for Dual Operation

1a

Power for Single Operation

4.5"x5" FR-4 Board
T = 25 C

A

Still Air

2

Figure 12. SO-8 Dual Package Maximum

Steady-State Power Dissipation versus
Copper Mounting Pad Area.

30

10

3

RDS(ON) LIMIT

1

0.3

0.1

D

I , DRAIN CURRENT (A)

0.03

0.01

V = 10V

GS

SINGLE PULSE

R = See Note 1c

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 30 50
V , DRAIN-SOURCE VOLTAGE (V)

DS

DC

1ms

10ms

100ms

1s

10s

o

100us

5

4

3

1b

1c

2

D

I , STEADY-STATE DRAIN CURRENT (A)

1

0 0.1 0.2 0.3 0.4 0.5

2oz COPPER MOUNTING PAD AREA (in )

4.5"x5" FR-4 Board

o

T = 25 C

A

Still Air
V = 10V

GS

2

Figure 13. Maximum Steady- State Drain

Current versus Copper Mounting Pad
Area.

1a

Figure 14. Maximum Safe Operating Area.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

D = 0.5

0.2

R (t) = r(t) * R

JA

θ

0.1

0.05

0.02

0.01
Single Pulse

t , TIME (sec)

1

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

R = See Note 1c

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

1

JA

θ

2

NDS9956A.SAM