Page 1
NDT452AP
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1996
Power SOT P-Channel enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and DC motor
-5A, -30V. R
R
High density cell design for extremely low R
= 0.065Ω @ VGS = -10V
DS(ON)
= 0.1Ω @ VGS = -4.5V.
DS(ON)
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
control.
________________________________________________________________________________
D
D S
G
D
G
S
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter NDT452AP Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) -5 A
- Pulsed - 15
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -65 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
θ
R
θ
* Order option J23Z for cropped center drain lead.
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
JA
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
JC
NDT452AP Rev. B1
Page 2
Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
I
DSS
I
GSSF
I
GSSR
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Zero Gate Voltage Drain Current
VDS = -24 V, V
GS
= 0 V
TJ = 55°C
-1 µA
-10 µA
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
R
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
-0.7 -1.2 -2.2
0.052 0.065
Static Drain-Source On-Resistance
TJ = 125°C
VGS = -10 V, ID = -5.0 A
Ω
TJ = 125°C 0.075 0.13
0.085 0.1
-5
I
g
D(on)
VGS = -4.5 V, ID = -4.3 A
On-State Drain Current VGS = -10 V, VDS = -5 V -15 A
VGS = -4.5 V, VDS = -5 V
FS
Forward Transconductance VDS = -10 V, ID = -5.0 A 7 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 430 pF
VDS = -15 V, V
f = 1.0 MHz
GS
= 0 V,
Reverse Transfer Capacitance 160 pF
690 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 20 30 ns
VDD = -10 V, ID = -1 A,
V
= -10 V, R
GEN
GEN
= 6 Ω
Turn - Off Delay Time 40 50 ns
Turn - Off Fall Time 19 40 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 3.2 nC
Gate-Drain Charge 5.2 nC
VDS = -10 V,
ID = -5.0 A, VGS = -10 V
9 20 ns
22 30 nC
NDT452AP Rev. B1
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Electrical Characteristics (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
t
rr
Notes:
1. R
θ
design while R
P
D
Typical R
Maximum Continuous Drain-Source Diode Forward Current -2.5 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -2.5 A
(Note 2)
-0.85 -1.2 V
Reverse Recovery Time VGS = 0 V, IF = -2.5 A, dIF/dt = 100 A/µs 100 ns
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
(t)
is determined by the user's board design.
CA
θ
T
=
R
JA
θ
a. 42oC/W when mounted on a 1 in2 pad of 2oz copper.
b. 95oC/W when mounted on a 0.066 in2 pad of 2oz copper.
c. 110oC/W when mounted on a 0.0123 in2 pad of 2oz copper.
1a
T
J−TA
θJA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
J−TA
=
(t)
R
θJC+RθCA
2
= I
(t) ×R
DS(ON ) T
D
(t)
J
1b
1c
is guaranteed by
JC
θ
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT452AP Rev. B1
Page 4
Typical Electrical Characteristics
-20
V = -10V
GS
-15
-10
-5
D
I , DRAIN-SOURCE CURRENT (A)
0
-6.0
V , DRAIN-SOURCE VOLTAGE (V)
DS
-5.0
-4.5
-4.0
-3.5
-3.0
-4-3-2-10
3
V = -3.5V
2.5
2
1.5
DS(on)
R , NORMALIZED
1
DRAIN-SOURCE ON-RESISTANCE
0.5
GS
- 4.0
-4.5
I , DRAIN CURRENT (A)
D
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
I = -5.0A
D
1.4
V = -10V
GS
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. On-Resistance Variation with
Temperature.
2
V = -10V
GS
1.5
1
DS(on)
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
I , DRAIN CURRENT (A)
D
T = 125°C
J
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
-5.0
-6.0
-10
-20-16-12-8-40
25°C
-55°C
-20-16-12-8-40
-20
V = -10V
DS
-15
-10
-5
D
I , DRAIN CURRENT (A)
0
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
T = -55°C
J
125°C
25°C
-6-5-4-3-2-1
1.2
V = V
1.1
1
0.9
th
0.8
V , NORMALIZED
0.7
GATE-SOURCE THRESHOLD VOLTAGE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
DS
I = -250µA
D
Figure 6. Gate Threshold Variation with
Temperature.
GS
NDT452AP Rev. B1
Page 5
Typical Electrical Characteristics
1.1
I = -250µA
1.08
1.06
1.04
1.02
DSS
BV , NORMALIZED
0.98
0.96
DRAIN-SOURCE BREAKDOWN VOLTAGE
0.94
D
1
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation with
Temperature.
2000
1000
500
300
CAPACITANCE (pF)
200
100
f = 1 MHz
V = 0V
GS
0.1 0.2 0.5 1 2 5 10 30
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
iss
oss
C
rss
20
V = 0V
10
GS
5
T = 125°C
J
1
0.1
0.01
S
-I , REVERSE DRAIN CURRENT (A)
0.001
0 0.4 0.8 1.2 1.6 2
25°C
-55°C
-V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature.
10
I = -5.0A
D V = -5V
8
6
4
2
GS
-V , GATE-SOURCE VOLTAGE (V)
0
0 5 10 15 20 25
Q , GATE CHARGE (nC)
DS
g
-10V
-20V
Figure 9. Capacitance Characteristics.
-V
V
IN
D
V
GS
R
GEN
G
S
Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms.
DD
Figure 10. Gate Charge Characteristics.
t t
on off
t
R
d(on)
L
V
OUT
V
OUT
r
90%
10%
DUT
V
IN
50%
10%
PULSE WIDTH
t
d(off)
50%
90%
10%
90%
NDT452AP Rev. B1
tt
f
INVERTED
Page 6
Typical Thermal Characteristics
12
V = -10V
DS
9
6
3
FS
g , TRANSCONDUCTANCE (SIEMENS)
0
I , DRAIN CURRENT (A)
D
T = -55°C
J
25°C
125°C
Figure 13. Transconductance Variation with Drain
Current and Temperature.
6
5
4
1b
1c
3
D
I , STEADY-STATE DRAIN CURRENT (A)
2
0 0.2 0.4 0.6 0.8 1
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
V = -10V
GS
2
-20-16-12-8-40
1a
0.5
0.1
D
-I , DRAIN CURRENT (A)
0.05
0.01
3.5
3
2.5
2
1.5
1b
1c
1
STEADY-STATE POWER DISSIPATION (W)
0.5
0 0.2 0.4 0.6 0.8 1
2oz COPPER MOUNTING PAD AREA (in )
4.5"x5" FR-4 Board
o
T = 25 C
A
Still Air
2
Figure 14. SOT-223 Maximum Steady- tate
Power Dissipation versus Copper
Mounting Pad Area.
50
20
10
RDS(ON) LIMIT
5
1
V = -10V
GS
SINGLE PULSE
R = See Note 1c
JA
θ
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 30 50
- V , DRAIN-SOURCE CURRENT (V)
DS
10s
DC
100us
1ms
10ms
100ms
1s
1a
Figure 15. Maximum Steady-State Drain
Figure 16. Maximum Safe Operating Area.
Current versus Copper Mounting Pad
Area.
1
0.5
D = 0.5
0.2
0.2
0.1
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.05
0.02
0.01
Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 300
Figure 17. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R = See Note 1 c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
θ
JA
θ
JA
2
1
NDT452AP Rev. B1
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
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STAR*POWER is used under license
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Formative or
In Design
First Production
Full Production
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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