Datasheet NDS9947 Datasheet (Fairchild Semiconductor)

February 1996

NDS9947

Dual P-Channel Enhancement Mode Field Effect Transistor

General Description Features

These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

________________________________________________________________________________

-3.5A, -20V. R

High density cell design for extremely low R

= 0.1Ω @ V

DS(ON)

= 10V

GS

DS(ON)

.

High power and current handling capability in a widely used surface mount package.

Dual MOSFET in surface mount package.

4

3

2

1

Absolute Maximum Ratings T

= 25°C unless otherwise noted

A

5

6

7

8

Symbol Parameter NDS9947 Units

V

DSS

V

GSS

I

D

Drain-Source Voltage -20 V

Gate-Source Voltage ± 20 V

Drain Current - Continuous TA = 25°C (Note 1a)

- Continuous TA = 70°C (Note 1a)

± 3.5 A

± 2.5

- Pulsed TA = 25°C ± 10

P

D

Power Dissipation for Dual Operation 2 W

Power Dissipation for Single Operation (Note 1a) 1.6 (Note 1b) 1 (Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θ

R

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

JA

Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

JC

NDS9947.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV

I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -20 V Zero Gate Voltage Drain Current

VDS = -16 V, V

GS

= 0 V

TJ = 55°C

-1 µA

-10 µA

Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA Gate - Body Leakage, Reverse

VGS = -20 V, VDS= 0 V

-100 nA

ON CHARACTERISTICS (Note 2)

V

GS(th)

Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -2.2 -3 V

TJ = 125°C -0.8 -1.9 -2.5

R

DS(ON)

Static Drain-Source On-Resistance

VGS = -10 V, ID = -3.5 A

TJ = 125°C

0.08 0.1

0.11 0.16

Ω

VGS = -4.5 V, ID = -1 A 0.165 0.19 I g

D(on)

On-State Drain Current

FS

Forward Transconductance VDS = -15 V, ID = -3.5 A 5 S

VGS = -10 V, VDS = -5 V

-14 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance 500 pF

VDS = -10 V, VGS = 0 V,

f = 1.0 MHz

Reverse Transfer Capacitance 245 pF

785 pF

SWITCHING CHARACTERISTICS (Note 2)

t t t t Q Q Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = -10 V, ID = -1 A,

V

= -10 V, R

Turn - On Rise Time 17 25 ns

GEN

= 6 Ω

9 40 ns

Turn - Off Delay Time 26 30 ns Turn - Off Fall Time 13 20 ns Total Gate Charge VDS = -10 V, Gate-Source Charge 6 nC

ID = -3.5 A, VGS = -10 V

19 30 nC

Gate-Drain Charge 12 nC

NDS9947.SAM

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

design while R

P

D

Typical R

Scale 1 : 1 on letter size paper

Maximum Continuous Drain-Source Diode Forward Current -1.7 A Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

(t)

is determined by the user's board design.

CA

θ

T

=

R

θ

a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.

b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.

c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.

T

J−TA

=

(t)

R

θJ A

θ

J C

for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

JA

J−TA

+R

2

= I

(t) × R

DS(O N ) T

D

(t)

θ

CA

J

1a

VGS = 0 V, IS = -1.7 A

1b

(Note 2)

1c

-0.9 -1.2 V

is guaranteed by

JC

θ

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..

NDS9947.SAM

Typical Electrical Characteristics

-20

V = -10V

GS

-15

-8.0

-7.0

-6.0

-5.5

-10

-5

D

I , DRAIN-SOURCE CURRENT (A)

0

V , DRAIN-SOURCE VOLTAGE (V)

DS

-5.0

-4.5

-4.0

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation

1.5

I = -3.5A

D

1.4

V = -10V

GS

1.3

1.2

1.1 1

DS(ON)

R , NORMALIZED

0.9

0.8

DRAIN-SOURCE ON-RESISTANCE (OHMS)

0.7

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

3.5

V = -4.0V

GS

3

2.5

2

1.5

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

-5-4-3-2-10

0.5

-4.5

-5.0

I , DRAIN CURRENT (A)

D

-5.5

-6.0

-7.0

-8.0

-10

-20-16-12-8-40

with Drain Current and Gate Voltage.

2

V = -10V

GS

1.5

1

DS(on)

R , NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

0.5

I , DRAIN CURRENT (A)

D

T = 125°C

J

25°C

-55°C

-20-15-10-50

Figure 3. On-Resistance Variation

with Temperature.

-10

V = -10V

DS

-8

-6

-4

D

I , DRAIN CURRENT (A)

-2

0

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics.

T = -55°C

J

25°C

125°C

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

1.1

V = V

GS

1.05

1

0.95

th

0.9

V , NORMALIZED

0.85

GATE-SOURCE THRESHOLD VOLTAGE (V)

-6-5-4-3-2-1

0.8

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

DS

I = -250µA

D

Figure 6. Gate Threshold Variation

with Temperature.

NDS9947.SAM

Typical Electrical Characteristics (continued)

1.1

I = -250µA

D

1.05

DSS

1

BV , NORMALIZED

0.95

DRAIN-SOURCE BREAKDOWN VOLTAGE (V)

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

Figure 7. Breakdown Voltage

Variation with Temperature.

1500

1000

500

300

CAPACITANCE (pF)

200

100

f = 1 MHz V = 0V

GS

0.1 0.2 0.5 1 2 5 10 20

-V , DRAIN TO SOURCE VOLTAGE (V)

DS

Figure 9. Capacitance Characteristics.

C

10

5

V = 0V

GS

T = 125°C

J

1

0.5

0.1

0.01

S

-I , REVERSE DRAIN CURRENT (A)

0.001

0.3 0.6 0.9 1.2 1.5 1.8

25°C

-55°C

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 8. Body Diode Forward Voltage

Variation with Source

Current and Temperature.

-10

I = -3.5A

iss

oss

C

rss

DS

-8

-6

-4

-2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 5 10 15 20

Q , GATE CHARGE (nC)

g

V = -5V

DS

-10V

-15V

Figure 10. Gate Charge Characteristics.

V

IN

V

GS

R

GEN

G

Figure 11. Switching Test Circuit.

V

DD

t

V

d(on)

OUT

R

L

D

V

OUT

t t

on off

t

r

d(off)

90%

10%

90%

10%

tt

f

DUT

90%

V

S

IN

50%

10%

PULSE WIDTH

INVERTED

Figure 12. Switching Waveforms.

NDS9947.SAM

Typical Electrical Characteristics (continued)

8

6

V = -15V

DS

T = -55°C

J

25°C

125°C

4

2

FS

g , TRANSCONDUCTANCE (SIEMENS)

0

I , DRAIN CURRENT (A)

D

Figure 13. Transconductance Variation with Drain

Current and Temperature.

1

0.5

0.2

0.1

0.05

0.02

0.01

0.005

r(t), NORMALIZED EFFECTIVE

0.002

TRANSIENT THERMAL RESISTANCE

0.001

0.0001 0.001 0.01 0.1 1 10 100 300

D = 0.5

0.2

0.1

0.05

0.02

0.01

Single Pulse

20

10

3

RDS(ON) LIMIT

1

0.3

V = -20V

GS

SINGLE PULSE

T = 25°C

A

- V , DRAIN-SOURCE VOLTAGE (V)

DS

-15-12-9-6-30

0.1

D

-I , DRAIN CURRENT (A)

0.03

0.01

0.1 0.2 0.5 1 2 5 10 20 30

Figure 14. Maximum Safe Operating Area.

R (t) = r(t) * R

R = See Note 1c

P(pk)

T - T = P * R (t)

J

Duty Cycle, D = t / t

t , TIME (sec)

1

10ms

100ms

1s

10s

DC

JA

θ

JA

θ

t

1

t

2

A

JA

θ

JA

θ

2

1

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change

depending on the circuit board design.

NDS9947.SAM

SO-8 Tape and Reel Data and Package Dimensions

SOIC(8lds) Packaging Configuration: Figure 1.0

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS

TNR DATE PT NUMBER PEEL STRENGTH MIN ______________gms

Customized Label

Packaging Option Packaging type

Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg)

Note/Comments

MAX _____________ gms

ESD Label

SOIC (8lds) Packaging Information

Standard

(no flow code)

TNR

2,500 95 4,000

13" Dia

343x64x343 530x130x83 343x64x343

5,000 30,000 8,000

0.0774 0.0774 0.0774 0.0774

0.6060 - 0.9696 0.1182

L86Z F011

Rail/Tube-TNR

13" Dia

Embossed Car rier Tape

Antistatic Cover Tape

Static Dissipative

F63TNR Label

D84Z

TNR

500

7" Dia

184x18 7x47

1,000

F

NDS

9959

852

SOIC-8 Unit Orientation

343mm x 342mm x 64mm

Stand a r d In t e rm ed iate box

Packaging Description:

SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm di ameter reel. This and some o ther options are further described in the Packaging Information table.

These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts shippe d.

F

NDS

9959

F

NDS

9959

F

NDS

852

F

NDS 9959

852

Pin 1

F63TNR Label sample

LOT: CBVK741B019

FSID: FDS9953A

D/C1: D9842 QTY1: SPEC REV: D/C2: QTY2: CPN:

QTY: 2500

SPEC:

N/F: F (F63TNR)3

SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0

Carrier Tape

Cover Tape

Trailer Tape 640mm minimum or 80 empty pockets

F63TNLab el

ESD Label

Components

ESD Label

F63TNLabel

Leader Tape 1680mm minimum or 210 empty pockets

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0

T

K0

Wc

B0

P0

D0

E1

F

W

E2

Tc

A0

D1

P1

User Direction of Feed

Dimensions are in millimeter

Pkg type

SOIC

(12mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

SOIC(8lds) Reel Configuration: Figure 4.0

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

(8lds)

6.50

5.30

12.0

1.55

1.60

1.75

+/-0.10

+/-0.3

+/-0.05

+/-0.10

10.25 min

rotational and lateral movement requirements (see sketches A, B, and C).

B0

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

5.50 +/-0.05

20 deg maximum

A0

8.0 +/-0.1

Typical component cavity center line

Typical component center line

Dim A

Max

4.0 +/-0.1

0.450

2.1 +/-0.10

0.5mm maximum

Sketch C (Top View)

Component lateral movement

+/-

0.150

9.2 +/-0.3

0.5mm maximum

0.06 +/-0.02

Dim A

max

Tape Size

12mm 7" Dia

12mm 13" Dia

 1998 Fairchild Semiconductor Corporation

Reel

Option

Dim N

Diameter Option

7"

See detail AA

B Min

Dim C

13" Diameter Option

See detail AA

W2 max Measured at Hub

Dim D

W3

min

DETAIL AA

Dimensions are in inches and millimeters

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00 330

1.5

0.059

1.5

512 +0.020/-0.008 13 +0.5/-0.2

0.795

2.165550.488 +0.078/-0.000

20.2

0.795

7.00

20.2

178

12.4 +2/0

0.488 +0.078/-0.000

12.4 +2/0

0.724

18.4

0.724

18.4

0.469 – 0.606

11.9 – 15.4

0.469 – 0.606

11.9 – 15.4

July 1999, Rev. B

SO-8 Tape and Reel Data and Package Dimensions, continued

SOIC-8 (FS PKG Code S1)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

inches [millimeters]

Part Weight per unit (gram): 0.0774

9

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™

2

CMOS

E

TM

FACT™ FACT Quiet Series™



FAST FASTr™ GTO™

HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench



QFET™ QS™

Quiet Series™ SuperSOT™-3 SuperSOT™-6

SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STA TUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. E