Datasheet MT9162AE, MT9162AN, MT9162AS Datasheet (MITEL)

ISO

2

-CMOS

MT9162

5 Volt Single Rail Codec

Advance Information

Features

• Single 5 volt supply

• Programmable µ−law/A-law Codec and filters

• Fully differential output driver

• SSI digital interface

• SSI speed control via external pins CSLO-CSL2

• Individual transmit and receive mute controls

• 0dB gain in receive path

• 6dB gain in transmit path

• Low power operation

• ITU-T G.714 compliant

Applications

• Cellular radio sets

• Local area communications stations

• Line cards

DS5178 ISSUE 4 August 1999

Ordering Information

MT9162AE 20 Pin Plastic DIP (300 mil)
MT9162AS 20 Pin SOIC
MT9162AN 20 Pin SSOP

-40°C to +85°C

Description

The MT9162 5V single rail Codec incorporates a
built-in Filter/Codec, transmit anti-alias filter, a
reference voltage and bias source. The device
supports both A-law and µ-law requirements.

The analog interface is capable of driving a 20k ohm
load.

The MT9162 is fabricated in Mitel's ISO2-CMOS
technology ensuring low power consumption and
high reliability.

VDD

VSS

VBias

VRef

Din

Dout

STB

CLOCKin

PCM

Serial

Interface

FILTER/CODEC GAIN

PWRST

Timing

IC

ENCODER
DECODER

A/µ CSL0 CSL1 CSL2 RXMute TXMute

6dB

0 dB

Control

Figure 1 - Functional Block Diagram

Analog

Interface

AIN+
AIN-

AOUT +
AOUT -

7-161

MT9162 Advance Information

VBias

VRef

PWRST

A/µ

RXMUTE

TXMUTE

CSL0
CSL1
CSL2

1
2

3
4

IC

5
6

7
8
9

10

20
19
18
17
16
15
14
13
12
11

AIN+
AIN­VSS

AOUT +

AOUT ­VDD
CLOCKin
STB
Din
Dout

20 PIN PDIP/SOIC/SSOP

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1V

Bias

2V

3 PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).
4ICInternal Connection. Tie externally to VSS for normal operation.

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1 µ F capacitor to VSS. Connect 1 µF capacitor to Vref.

Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally.

Ref

Connect 0.1 µ F capacitor to VSS. Connect 1 µF capacitor to VBias

5A/µ A/µ Law Selection. CMOS level compatable input pin governs the companding law used by

the device. A-law selected when pin tied to VDDor µ-law selected when pin tied to VSS.

6 RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatible.

7 TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatible.

8
9

10
11 D

CSL0
CSL1
CSL2

out

Clock Speed Select. These pins are used to program the speed of the SSI mode as well as
the conversion rate between the externally supplied MCL clock and the 512 kHz clock required
by the filter/codec. Refer to Table 2 for details. CMOS level compatible.

Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.

12 D

Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the

in

falling edge of BCL during the timeslot defined by STB. CMOS level compatible.

13 STB Data Str obe. This input determines the 8-bit timeslot used by the device f or both transmit and

receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.

14 CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions.

Connect bit clock to this pin when it is 512 kHz or greater . Connect a 4096 kHz cloc k to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatible.

15 V

Positive Power Supply. Nominally 5 volts.

DD

16 AOUT- Inverting Analog Output. (balanced).
17 AOUT+ Non-Inverting Analog Output. (balanced).
18 V

Ground. Nominally 0 volts.

SS

19 Ain- Inverting Analog Input. No external anti-aliasing is required.
20 Ain+ Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.

7-162

Advance Information MT9162

Overview

The 5V single rail Codec features complete Analog/
Digital and Digital/Analog conversion of audio
signals (Filter/Codec) and an analog interface to a
standard analog transmitter and receiver (Analog
Interface). The receiver amplifier is capable of
driving a 20k ohm load.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are ITU-T
G.711 A-law or µ-Law, with true-sign/Alternate Digit
Inversion.

The Filter/Codec block also implements a transmit
audio path gain in the analog domain. Figure 3
depicts the nominal half-channel for the MT9162.

The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
design. This fully differential architecture is
continued into the analog interface section to provide
full chip realization of these capabilities for the
external functions.

A reference voltage (V
requirements of the Codec section, and a bias
voltage (V

), for biasing the internal analog

Bias

sections, are both generated on-chip. V
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
capacitor must be connected from V
ground at all times. Likewise, although V
be used internally, a 0.1µF capacitor from the V
pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V

Ref

and V

pins are situated on adjacent pins.

Bias

The transmit filter is designed to meet ITU-T G.714
specifications. An anti-aliasing filter is included. This
is a second order lowpass implementation with a
corner frequency at 25 kHz.

), for the conversion

Ref

is also

Bias

to analog

Bias

may only

Ref

Ref

Companding law selection for the Filter/Codec is
provided by the A/

µ companding control pin. Table

1 illustrates these choices.

ITU-T (G.711)

Code

µ -Law A-Law

+ Full Scale 1000 0000 1010 1010

+ Zero 1111 1111 1101 0101

-Zero

(quiet code)

- Full Scale 0000 0000 0010 1010

0111 1111 0101 0101

Table 1: Law Selection

Analog Interfaces

Standard interfaces are provided by the MT9162.
These are:

• The analog inputs (transmitter), pins AIN+/AIN-.
The maximum peak to peak input is 3.667Vpp
µ−law and across AIN+/AIN- 3.8Vpp A-law.

• The analog outputs (receiver), pins AOUT+/
AOUT-.This internally compensated fully
differential output driver is capable of driving a
load of 20k ohms.

PCM Serial Interface

A serial link is required to transport data between the
MT9162 and an external digital transmission device.
The MT9162 utilizes the strobed data interface found
on many standard Codec devices. This interface is
commonly referred to as Simple Serial Interface
(SSI).

The required mode of operation is selected via the
CSL2-0 control pins. See Table 2 for selections
based in CSL2-0 pin settings.

Quiet Code

The PCM serial port can be made to send quiet code
to the decoder and receive filter path by setting the
RxMute pin high. Likewise, the PCM serial port will
send quiet code in the transmit path when the

The receive filter is designed to meet ITU-T G.714
specifications. Filter response is peaked to
compensate for the sinx/x attenuation caused by the
8 kHz sampling rate.

7-163

MT9162 Advance Information

The timing requirements for SSI are shown in

External

CSL2CSL1CSL

1 0 0 128 4096
1 0 1 256 4096
0 0 0 512 512
0 0 1 1536 1536
0 1 0 2048 2048
0 1 1 4096 4096

Clock Bit

0

Rate (kHz)

CLOCKin

(kHz)

Table 2: Bit Clock Rate Selection

TxMute pin is high. When either of these pins are low
their respective paths function normally. The -Zero
entry of Table 1 is used for the quiet code definition.

SSI Mode

Figures 5 & 6.

In SSI mode the MT9162 supports only B-Channel
operation. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.

The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.

SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT9162 functions allowing synchronous
operation. If the available bit clock is 128 kHz or 256
kHz, then a 4096 kHz master clock is required to
derive clocks for the internal MT9162 functions.

The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock is also required for
SSI operation if the bit clock is less than 512 kHz.

Serial Port

PCM

D

in

Decoder

2.05 dB

Filter/Codec and Analog Interface

Receive

Filter Gain

0 dB

Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT9162 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control pins CSL2, CSL1 and CSL0 are used to
program the bit rates.

-2.05 dB
Receiver

Driver

Aout +

Aout-

20kΩ

7-164

PCM

D

out

Encoder

-2.05 dB

Transmit Filter

Transmit Filter

Gain

Gain

0dB

0 to +7 dB

Transmit Gain

-0.37 dB

Transmit

Gain

8.42 dB

AIN+

AIN-

Analog

Input

(1 dB steps)

Internal To Device

External To Device

Figure 3 - Audio Gain Partitioning

Advance Information MT9162

For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.

For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.

PWRST

While the MT9162 is held in PWRST no device
control or functionality is possible.

Applications

Figure 4 shows the MT9162 in a line card
application.

+5V

0.1 µF

0.1 µF

100k

100k

1k

100k
1k

100k

1k

CS0

100k

1k

CS1

100k
1k

CS2

100k

1k

From Digital

Phone

VBias

1 µF

A/µ
RxMUTE
TxMUTE

Twisted Pair

Typical External Gain

()

1
2

3
4

5
6

7
8
9

10

DC to DC
Converter

AV= 5-10

MT9162

20
19
18
17
16
15
14
13
12
11

+5V

Lin

Z

Lout

T

Input from Subscriber

Line Interface

+5V

Din

MT8972

DNIC

Dout

Frame Pulse

Clock

Out to Subscriber Line

Interface

Figure 4 - Line Card Application

7-165

MT9162 Advance Information

Absolute Maximum Ratings

†

Parameter Symbol Min Max Units

1 Supply Voltage VDD - V
2 Voltage on any I/O pin VI/V
3 Current on any I/O pin (transducers excluded) II/I
4 Storage Temperature T
5 Power Dissipation (package) P

†

Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to V

SS

O

O
S
D

SS

- 0.3 7 V

VSS - 0.3 VDD + 0.3 V

- 65 + 150 °C

unless otherwise stated

Characteristics Sym Min Typ Max Units Test Conditions

1 Supply Voltage V
2 CMOS Input Voltage (high) V
3 CMOS Input Voltage (low) V
4 Operating Temperature T

IHC
ILC

4.75 5 5.25 V

DD

4.5 V

V

SS

- 40 + 85 °C

A

DD

0.5 V

V

± 20 mA

750 mW

Power Characteristics

Characteristics Sym Min Typ Max Units Test Conditions

1 Static Supply Current (clock

disabled)

2 Dynamic Supply Current:

Total all functions enabled I

Note 1: Power delivered to the load is in addition to the bias current requirements.

I

DDC1

DDFT

420µA Outputs unloaded, Input

7.0 10 mA See Note 1

signals static, not loaded

7-166

Advance Information MT9162

DC Electrical Characteristics

†

- Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym Min Typ

1 Input HIGH Voltage CMOS inputs V
2 Input LOW Voltage CMOS inputs V
3 VBias Voltage Output V
4V

Output Voltage V

Ref

5 Input Leakage Current I
6 Positive Going Threshold

Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)

7 Output HIGH Current I

8 Output LOW Current I

9 Output Leakage Current I
10 Output Capacitance C
11 Input Capacitance C

V

V

IHC

ILC

Bias

Ref

IZ

T+

T-

OH

OL

OZ

o

‡

3.5 V

VDD/2 V Max. Load = 10kΩ

VDD/2-1.9

0.1 10 µAVIN=VDD to V

3.7

3 7 mA VOH = 0.9*V

510 mAV

0.01 10 µAV
15 pF

i

10 pF

Max Units Test Conditions

1.5 V

V No load

SS

V

1.3

V

DD

See Note 1

= 0.1*V

OL

DD

See Note 1

= VDD and V

OUT

SS

† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

* Note 1 - Magnitude measurement, ignore signs.

Clockin Tolerance Characteristics

Characteristics Min Typ

1 CLOCKin Frequency (Asynchronous

†

‡

Max Units Test Conditions

4095.6 4096 4096.4 kHz (i.e., 100 ppm)

Mode)

† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

7-167

MT9162 Advance Information

AC Characteristics† for A/D (Transmit) Path - 0dBm0 = A

0dBm0 = A

1 Analog input equivalent to

overload decision

2 Absolute half-channel gain

AIN ± to Dout G

3 Gain tracking vs. input level

ITU-T G.714 Method 2

4 Signal to total Distortion vs. input

level.
ITU-T G.714 Method 2

5 Transmit Idle Channel Noise N

6 Gain relative to gain at

<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz

- 3.14dB = 1.843V

Lo3.14

for A-Law, at the Codec. (V

rms

Characteristics Sym Min Typ

A

Li3.17

A

Li3.14

5.2 6.0 6.8 dB

-0.3

G

AX1

TX

-0.6

-1.6

D

QX

35
29
24

CX

N

PX

G

RX

-0.25

-0.9

=0.6 volts and V

Ref

7.334

7.6

8.5

-71

-45

-23

-40

‡

- 3.17dB = 1.773V

Lo3.17

=2.5 volts.)

Bias

for µ-Law and

rms

Max Units Test Conditions

Vp-p
Vp-p

µ-Law
A-Law
Both at Codec

Transmit filter gain=0dB
setting.
@1020Hz

0.3

0.6

1.6

12

-69

-25

-30

0.0

0.25

0.25

-12.5

-25

dB
dB
dB

dB
dB
dB

dBrnC0

dBm0p

dB
dB
dB
dB
dB
dB
dB

3 to -40 dBm0

-40 to -50 dBm0

-50 to -55 dBm0
0 to -30 dBm0

-40 dBm0

-45 dBm0
µ-Law

A-Law

7 Absolute Delay D

AX

360 µs at frequency of minimum

delay

8 Group Delay relative to D

AX

9 Power Supply Rejection

f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz

† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

D

DX

PSSR
PSSR1
PSSR2
PSSR3

750
380
130
750

37 37

40
35
40

µs

µs
µs
µs

dB
dB
dB
dB

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

±100mV peak signal on
V

DD

µ-law
PSSR1-3 not production
tested

7-168

Advance Information MT9162

AC Characteristics† for D/A (Receive) Path - 0dBm0 = A

0dBm0 = A

1 Analog output at the Codec full

scale

2 Absolute half-channel gain.

Din to AOUT±

3 Gain tracking vs. input level

ITU-T G.714 Method 2

4 Signal to total distortion vs. input

level.
ITU-T G.714 Method 2

5 Receive Idle Channel Noise N

6 Gain relative to gain at 1020Hz

200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz

- 3.14dB = 1.843V

Lo3.14

for A-Law, at the Codec. (V

rms

Characteristics Sym Min Typ

A

Lo3.17

A

Lo3.14

G

G

AR1

TR

-0.8 0 0.8 dB @1020Hz

-0.3

-0.6

-1.6

G

QR

35
29
24

CR

N

PR

G

RR

-0.25

-0.90

=0.6 volts and V

Ref

‡

7.225

7.481

7

-84

- 3.17dB = 1.773V

Lo3.17

=2.5 volts.)

Bias

for µ-Law and

rms

Max Units Test Conditions

0.3

0.6

1.6

10

-80

0.25

0.25

0.25

-12.5

-25

Vp-p
Vp-p

dB
dB
dB

dB
dB
dB

dBrnC0

dBm0p

dB
dB
dB
dB
dB

µ-Law
A-Law

3 to -40 dBm0

-40 to -50 dBm0

-50 to -55 dBm0
0 to -30 dBm0

-40 dBm0

-45 dBm0
µ-Law

A-Law

7 Absolute Delay D
8 Group Delay relative to D

AR

9 Crosstalk D/A to A/D

A/D to D/A

† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

D

CT

CT

AR
DR

RT
TR

240 µs at frequency of min. delay
750

380
130
750

-74

-80

µs
µs
µs
µs

dB
dB

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

G.714.16
ITU-T

Electrical Characteristics† for Analog Outputs

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Load impedance at Output E
2 Allowable output capacitive

E

load

3 Analog output harmonic

E

distortion

† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

20k ohms across AOUT±

ZL

CL

D

20 pF each pin: AOUT+,

0.5 % 20k ohms load across
AOUT±
VO≤693mV

AOUT-

RMS

7-169

MT9162 Advance Information

Electrical Characteristics† for Analog Inputs

Characteristics Sym Min Typ

1 Maximum input voltage without

overloading Codec

‡

Max Units Test Conditions

across AIN+/AIN- V

2 Input Impedance Z

† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

IOLH

I

50 kΩ AIN+/AIN- to V

2.90

3.00

Vp-p A/µ = 0

A/µ = 1

AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5)

Characteristics Sym Min Typ

1 BCL Clock Period t
2 BCL Pulse Width High t
3 BCL Pulse Width Low t

BCL

BCLH

BCLL

4 BCL Rise/Fall Time tR/t
5 Strobe Pulse Width t
6 Strobe setup time before BCL falling t
7 Strobe hold time after BCL falling t
8 Dout High Impedance to Active Low

ENW

SSS
SSH

t

DOZL

244 1953 ns BCL=4096 kHz to 512 kHz

F

70
80

from Strobe rising

9 Dout High Impedance to Active High

t

DOZH

from Strobe rising

10 Dout Active Low to High Impedance

t

DOLZ

from Strobe falling

11 Dout Active High to High Impedance

t

DOHZ

from Strobe falling

12 Dout Delay (high and low) from BCL

t

DD

rising
13 Din Setup time before BCL falling t
14 Din Hold Time from BCL falling t

† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.

DIS
DIH

20 ns
50 ns

‡

Max Units Test Conditions

122 ns BCL=4096 kHz
122 ns BCL=4096 kHz

20 ns Note 1

8 x t

BCL

t

BCL-80

t

BCL

-80

ns Note 1
ns
ns

50 ns CL=150 pF, RL=1K

50 ns CL=150 pF, RL=1K

50 ns CL=150 pF, RL=1K

50 ns CL=150 pF, RL=1K

50 ns CL=150 pF, RL=1K

SS

7-170

Advance Information MT9162

t

BCL

t

F

t

BCLL

t

t

DIS

DIH

t

DD

t

t

SSS

t

ENW

NOTE: Levels refer to % VDD (CMOS I/O)

t

SSH

DOLZ

t

DOHZ

CLOCKin

(BCL)

Din

Dout

STB

70%
30%

70%
30%

70%
30%

70%
30%

t

R

t

t

DOZL

DOZH

t

BCLH

Figure 5 - SSI Synchronous Timing Diagram

AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6)

Characteristics Sym Min Typ

1 Bit Cell Period T

2 Frame Jitter T
3 Bit 1 Dout Delay from STB

DATA

t

dda1

j

going high

4 Bit 2 Dout Delay from STB

going high

5 Bit n Dout Delay from STB

going high

6 Bit 1 Data Boundary T
7 Din Bit n Data Setup time from

STB rising

t

dda2

t

ddan

DATA1

t

SU

600+

T

DATA-Tj

600 +

(n-1) x

T

DATA-Tj

T

DATA-Tj

T

\2

DATA

+500ns-T

j

+(n-1) x

T

DATA

8 Din Data Hold time from STB

rising

t

ho

T

\2

DATA

+500ns+T

j

+(n-1) x

T

DATA

† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

‡

7812
3906

600+

T

DATA

600 +

(n-1) x

T

DATA

Max Units Test Conditions

nsnsBCL=128 kHz

BCL=256 kHz

600 ns

Tj+600 ns CL=150 pF, RL=1K

600 +

T

DATA+Tj

600 +

(n-1) x

T

DATA+Tj

T

DATA+Tj

ns CL=150 pF, RL=1K

ns CL=150 pF, RL=1K

n=3 to 8

ns
ns n=1-8

ns

7-171

MT9162 Advance Information

T

j

STB

Dout

Din

70%
30%

70%
30%

70%
30%

t

dda1

t

dda2

t

dha1

Bit 1 Bit 2 Bit 3

T

t

su

DATA

T

DAT A1

t

ho

D1

/2

T

D2

DAT A

T

DATA

T

DATA

D3

Figure 6 - SSI Asynchronous Timing Diagram

NOTE: Levels refer to % VDD (CMOS I/O)

7-172

Pin 1

Package Outlines

E

A

L

H

e

D

A

2

A

1

B

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin

5) A & B Maximum dimensions include allowable mold flash

C

20-Pin 24-Pin 28-Pin 48-Pin

Dim

Min Max Min Max Min Max Min Max

A 0.079

(2)

A

0.002

1

(0.05)

B 0.0087

(0.22)

C 0.008

D 0.27

(6.9)

E 0.2

(5.0)

e 0.025 BSC

A

0.065

2

(1.65)

H 0.29

(7.4)

L 0.022

(0.55)

0.013
(0.33)

(0.21)

0.295
(7.5)

0.22
(5.6)

(0.635 BSC)

0.073

(1.85)

0.32
(8.2)

0.037

(0.95)

- 0.079

0.002
(0.05)

0.0087
(0.22)

0.31
(7.9)

0.2

(5.0)

0.025 BSC

(0.635 BSC)

0.065
(1.65)

0.29
(7.4)

0.022
(0.55)

(2)

0.013
(0.33)

0.008
(0.21)

0.33
(8.5)

0.22
(5.6)

0.073
(1.85)

0.32
(8.2)

0.037
(0.95)

0.002
(0.05)

0.0087
(0.22)

0.39
(9.9)

0.2

(5.0)

0.025 BSC

(0.635 BSC)

0.065
(1.65)

0.29
(7.4)

0.022
(0.55)

0.079
(2)

0.013

(0.33)

0.008

(0.21)

0.42

(10.5)

0.22
(5.6)

0.073

(1.85)

0.32
(8.2)

0.037

(0.95)

0.095
(2.41)

0.008
(0.2)

0.008
(0.2)

0.62

(15.75)

0.291

(7.39)

0.025 BSC

(0.635 BSC)

0.089

(2.26)

0.395

(10.03)

0.02

(0.51)

0.110
(2.79)

0.016

(0.406)

0.0135
(0.342)

0.010
(0.25)

0.63

(16.00)

0.299
(7.59)

0.099
(2.52)

0.42

(10.67)

0.04

(1.02)

Small Shrink Outline Package (SSOP) - N Suffix

General-11

Pin 1

Package Outlines

E

A

A

1

16-Pin 18-Pin 20-Pin 24-Pin 28-Pin

DIM

Min Max Min Max Min Max

A 0.093

A

1

B 0.013

C 0.009

D 0.398

E 0.291

e 0.050 BSC

H 0.394

L 0.016

(2.35)

0.004
(0.10)

(0.33)

(0.231)

(10.1)

(7.40)

(1.27 BSC)

(10.00)

(0.40)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(0.318)

0.413
(10.5)

0.299
(7.40)

0.419

(10.65)

0.050
(1.27)

D

0.093
(2.35)

0.004
(0.10)

0.013
(0.33)

0.009

(0.231)

0.447

(11.35)

0.291
(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016
(0.40)

L

e

4 mils (lead coplanarity)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) A & B Maximum dimensions include allowable mold flash

B

0.104

(2.65)

0.012

(0.30)

0.030

(0.51)

0.013

(0.318)

0.4625
(11.75)

0.299

(7.40)

0.419

(10.65)

0.050

(1.27)

0.093

(2.35)

0.004

(0.10)

0.013

(0.33)

0.009

(0.231)

0.496

(12.60)

0.291

(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016

(0.40)

0.104

(2.65)

0.012

(0.30)

0.020

(0.51)

0.013

(0.318)

0.512

(13.00)

0.299

(7.40)

0.419

(10.65)

0.050

(1.27)

Lead SOIC Package - S Suffix

C

H

L

Min Max Min Max

0.093

(2.35)

0.004

(0.10)

0.013

(0.33)

0.009

(0.231)

0.5985
(15.2)

0.291

(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016

(0.40)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(0.318)

0.614
(15.6)

0.299
(7.40)

0.419

(10.65)

0.050
(1.27)

0.093

(2.35)

0.004

(0.10)

0.013

(0.33)

0.009

(0.231)

0.697

(17.7)

0.291

(7.40)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.016

(0.40)

(0.318)

0.7125

(10.65)

0.104
(2.65)

0.012
(0.30)

0.020
(0.51)

0.013

(18.1)

0.299
(7.40)

0.419

0.050
(1.27)

NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.

2. Converted inch dimensions are not necessarily exact.

General-7

Package Outlines

E

1

D

32

n-2 n-1 n

1

E

L

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

A

b

D

1

e

2

b

A

2

Plastic Dual-In-Line Packages (PDIP) - E Suffix

8-Pin 16-Pin 18-Pin 20-Pin

DIM

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

A

A

2

b

b

2

C
D

D

1

E

E

1

e

e

A

L

e

B

e

C

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)

0.008

(0.203)

0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)

0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)

0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)

0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)

0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)

0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)

0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)

C

e

A

e

B

e

C

General-8

E

1

L

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

Package Outlines

32

1

E

n-2 n-1 n

D

A

b

D

1

e

2

b

A

2

C

e

A

e

B

Plastic Dual-In-Line Packages (PDIP) - E Suffix

α

DIM

A

A

2

b

b

2

C
D

D

1

E
E

E

1

E

1

e

e

A

e

A

e

B

L

α

22-Pin 24-Pin 28-Pin 40-Pin

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)

0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)

0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)

1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)

0.290 (7.37) .330 (8.38)

0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)

0.246 (6.25) 0.254 (6.45)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08)
15° 15° 15° 15°

Shaded areas for 300 Mil Body Width 24 PDIP only

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