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MT9125AP
Datasheet (MITEL)
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Datasheet MT9125AP, MT9125AE Datasheet (MITEL)

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CMOS
MT9125
Dual ADPCM Transcoder
Preliminary Information
Features
• Dual chann el fu ll duple x trans c oder
• 32 kbit/s an d 24 k bit/s AD PC M codi ng,
• compatib le to G. 721 & and G .723 (1988) an d ANSI T1.303-1989
• Low power o perat ion, tot al 25mW ty pical
• Transparent ADP CM bypa ss cap abili ty
• Serial interf ace for bot h PCM and ADPCM data streams
• ST-BUS interface supported
• Pin s ele cte d µ -la w or A-l aw o pe ra tio n
• Pin sele ct ed CCITT or sign-magnitude PCM coding
• Single 5 vol t pow er suppl y
• Optional reset value (CCITT Table 3/G.721) capabilit y
Applications
• Pair gain
• Voice mail systems
• Wireless set base sta tions
ISSUE 3 August 1993
Ordering Information
MT9125AE 24 Pin Plastic D IP MT9125AP 28 Pin PLC C
-40 to +85°C
Description
The Dual-channel ADPCM transcoder is a low power, CMOS device capable of two encoder functions and two decoder functions. Two 64 kbit/s PCM channels are compressed into two 32 kbit/s ADPCM channels, and two 32 kbit/s ADPCM channels are expanded into two 64 kbit/s PCM channels. The 32 kbit/s ADPCM transcoding algorithm utilized conforms to CCITT Recom­mendation G.721 and ANSI T1.303-1989. The device also supports a 24 kbit/s (three bit word) algorithm (CCITT/G.723).
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s, is possible by toggling the appropriate Mode Select (MS1-MS4) control pins.
C2o
BCLK
F0i
MCLK
ENS
ADPCMi
ADPCMo
ENA
Timing
ST-BUS
Converter
ADPCM
I/O
VDD VSS PWRDN
Transcoder 1
Transcoder 2
PCM
I/O
Control Decode
IC MS1 MS2 A/µ FORMAT MS3 MS4
Figure 1 - Functional Block Diagram
EN1
EN2
DSTo DSTi
ENB1 ENB2
8-17
MT9125 Preliminary Information
24 PIN PDIP
28 PIN PLCC
MCLK
DSTo BCLK ENB2
ENB1
DSTo
DSTi
BCLK
VSS
NC ENB2 ENB1
F0i
C2o
DSTi
VSS
MS1 MS2 MS3
5 6 7 8 9 10 11
10 11 12
1 2
3 4 5
6 7 8 9
K
L
i
C
0
M
F
C
4
3
3
2
4
1
1
1
3
2
1
S
S
S
M
M
M
24
ENS
23
EN2
22
EN1
21
ADPCMo
20
ADPCMi
19
ENA
18
VDD
17
IC
16
PWRDN
15
FORMAT
14
A/µ
13
MS4
2
S
o
2
2
•
1
C
N
N
N
N
E
E
E
1
6
8
7
2
2
2
ADPCMo
25
ADPCMi
24
ENA
23 22
VDD
21
NC
20
IC
19
5
6
7
1
1
1
4
µ
C
/
S
N
A
M
PWRDN
8
1
T A
M R O F
Figure 2 - Pin Connections
Pin Description
Pin #
DIP PLCC
1 2 MCLK Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be
23 F0i
3 4 C2o 2.048MHz Clock output for ST-BUS applications. This clock is MCLK divided by 2 and
Name Description
provided during both ST-BUS and SSI modes of operation. This is a TTL level input. In ST-BUS mode the MCLK input (also known as C4i
synchronous 4.096 MHz clock available from the layer 1 transceiver device. The C4i input to MCLK, is used in this mode as both the internal master clock and for deriving the C2o output clock and EN1/EN2 out put enable strobes.
In SSI mode a 4.096 MHz master clock must be derived from an external source. Th is master clock may be asynchronous relative to the 8 kHz frame reference.
Frame alignment input pulse for ST-BUS interface operation. This input should be tied low if ST-BUS operation is not required. This is a TTL level input.
inverted. The C2o output activity state is governed by the F0i
F0i in pu t
V
SS
V
DD
Active F0i
strobe enabled and aligned to F0i due to C4i input at MCLK
C2o output
disabled (SSI mode automatically activated) enabled
in ST-BUS terms) is derived from the
clock,
input pin condition.
4 5 DSTo S erial PCM octe t output stream. Refer to the serial timing diagram of Figure 12. 5 6 DSTi Serial PCM octet input data stream . Refer to the serial timing diagram of Figure 12.
This is a TTL level input.
8-18
Preliminary Information MT9125
Pin Description (continued)
Pin #
Name Description
DIP PLCC
6 7 BCLK Bit Clock input for both PCM and ADPCM ports; used in SSI mode only . The falling edge of
this clock is used to clock data in on DSTi and ADPCM i. The rising edge is used to clock data out on DSTo and ADPCMo. Can be any rate between 128 kHz and 2.048 MHz. Refer to the serial timing diagrams of Figures 12 and 13. When not used, this pin shoul d be tied
.
to V
SS
This is a TTL level input.
78 V
Power supply ground (0 volts).
SS
8 10 ENB2 Enable Strobe input for B2 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i detects a valid frame pulse at F0i
, PCM timing for the B2 ST-BUS channel is decoded
internally and the ENB2 input is ignored. When not used this pin should be tied to V
and MCLK. When the device
.
SS
This is a TTL level input.
9 11 ENB1 Enable Strobe input for B1 channel PCM timing in SSI mode only. A valid 8-bit strobe must
be present at this input if there are no ST-BUS signals at F0i detects a valid frame pulse at F0i
, PCM timing for the B1 ST-BUS channel is decoded
internally and the ENB1 input is ignored. When not used this pin should be tied to V
and MCLK. When the device
.
SS
This is a TTL level input.
10, 1112, 13MS1,
MS2
Mode select control input pins 1 and 2 for the B1 channel according to the following:
MS2
MS1 B1 Channel
0 0 algorithm reset 0 1 ADPCM bypass mode (24 or 32 kbit/s) 1 0 24 kbit/s ADPCM mode 1 1 32 kbit/s ADPCM mode
These are TTL level inputs .
12,1314, 16MS3,
MS4
Mode select contro l input pins 3 and 4 for the B2 channel according to the following:
MS4
MS3 B2 Channel
0 0 algorithm reset 0 1 ADPCM bypass mode (24 or 32 kbit/s) 1 0 24 kbit/s ADPCM mode 1 1 32 kbit/s ADPCM mode
These are TTL level inputs .
14 17 A /µ
Law select input. Sel ects µ-Law when low, A-Law when high. This is a TTL level input.
15 18 FORMA T Format select input. Selects CCITT PCM coding if high, or SIGN MAGNITUDE PCM if low.
This is a TTL level input.
16 19 PWRDN
Power Down input. Logic low on this pin forces the device to assume an internal power down mode where all operation is halted. This mode mini mize s power consumption.
Outputs are tri- stated. This is a schmid t trig ger input . 17 20 IC Internal Connection. Tie to V 18 22 V
Positive power supply input, 5 volts ± 10%.
DD
for normal operation.
SS
19 23 ENA Enable S trobe input for both input and output ADPCM channels; used fo r SSI operation
only. Refer to Figure 3. When not used, tie to VSS.
This is a TTL level input. 20 24 ADPCMi Serial ADPCM word input data stream. Refer to the serial timing diagram of Fig. 13. This is
a TTL level input. 21 25 ADPC M o Serial ADPCM word output stream. Refer to the serial timing diagram of Fig.1 3.
8-19
MT9125 Preliminary Information
Pin Description (continued)
Pin #
DIP PLCC
22 26 EN1 Channe l 1 Output Enable strobe. This output is decoded from the ST-BUS C4i and F0i
23 27 EN2 Channe l 2 Output Enable strobe. This output is decoded from the ST-BUS C4i
24 28 ENS Enable S elect input for ST-BUS operation only. This control pin chang e s the ST-BUS
1, 9,
15,
21
Functional Description
The Dual-channel ADPCM Transcoder is a low power, CMOS device capable of two encoder functions and two decoder functions. Two 64 kbit/s PCM channels (PCM octets) are compressed into two 32 kbit/s ADPCM channels (ADPCM words), and two 32 kbit/s ADPCM channels (ADPCM words) are expanded into two 64 kbit/s PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to CCITT recommendation G.721 and ANSI T1.303-1989. The device also supports a 24 kbit/s (three bit word) algorithm (CCITT/G.723). Switching, on-the-fly, between 32 kbit/s and 24 kbit/s is possible by toggling the appropriate Mode Select (MS1 -MS4) cont ro l p in s .
The internal circuitry requires very little power to operate; 25mW typically for dual channel operation. A master clock frequency of 4.096 MHz is required for the circuit to complete two encode channels and two decode channels. Operation with an asynchronous master clock, relative to the 8 kHz reference, is allowed.
All optional functions of the device are pin selected, no microprocessor is required. This allows a simple interface with industry standard Codecs, Dual Codecs, Digital Phone devices, and Layer 1 transceivers.
The PCM and ADPCM serial busses are a Synchronous Serial Interface (SSI), allowing serial clock rates from 128 kHz to 2.048 MHz. Additional pins on the device allow an easy interface to an ST­BUS component. On chip channel counters provide channel enable outputs, as well as a 2.048 MHz
Name Description
signals and its position, within the ST-BUS stream, may be controlled via the E NS pin. Refer to the ST-BUS relative timing dia gram shown in Figure 4.
signals and its position, within the ST-BUS stream, may be controlled via the E NS pin. Refer to the ST-BUS timing diagram shown in Figure 4.
channel position of EN1 and EN2 as well as the ADPCM channel position. Refer to the ST­BUS timing diagram shown in Figure 4. When not used this pin should be tied to V is a TTL level input.
NC No Connect ion. Leave open cir cuit.
clock output, useful for driving the timing input pins of standard CODEC devices.
Serial I/ O Ports (ADPCMi, ADPC Mo, EN A, EN B1, ENB2, DSTi, DSTo, C2o, EN1, EN2, ENS, F0i
Serial I/O data transfer to the Dual ADPCM Transcoder is provided through the PCM and the ADPCM ports. Serial I/O port operation is similar for both ST-BUS and SSI modes. The Dual ADPCM Transcoder determines the mode of operation by monitoring the signal applied to the F0i valid ST-BUS Frame Pulse (244ns low going pulse) is connected to the F0i assume ST-BUS o p er a tion . If F 0i to V
the transcoder will assume SSI operation. Pin
SS
functionality in each of these modes is described in the following sub-sections.
ADPCM Port Operation (ADPCMi, ADPCMo, ENA)
The ADPCM port consists of ADPCMi, ADPCMo and ENA. ADP CM port functionali ty is simi la r fo r both ST­BUS and SSI operation, the difference being in where the BCLK signal is derived and in where the ADPCM words are placed within the 8 kHz frame.
For SSI o perat ion (i .e., w hen F0i to V transferred over ADPCMi/ADPCMo at the bit clock rate (BCLK) during the channel time defined by the input strobe at ENA. Refer to Figure 3 and to Figure
13. Data is latched into the ADPCMi pin with the falling edge of BCLK while output data is made available at ADPCMo on the rising edge of BCLK.
) both channels of ADPCM code words are
SS
and F0i
DD
pin. When a
pin the transcoder will
is tied continuously
is tied continuously
. This
)
8-20
Preliminary Information MT9125
For ST-BUS operation (i.e., when a valid ST-BUS frame pulse is applied to the F0i
input) the bit rate, at
2.048 MHz, is generated internally from the master clock input at the MCLK pin. The BCLK and ENA inputs are ignored. Data is latched into the ADPCMi pin at the three-quarter bit position which occurs at the second rising edge of MCLK (C4i
) within the bit cell boundary. Output data, on ADPCMo, is made available at the first falling edge of MCLK (C4i
) within
the bit cell boundary. Refer to Figure 13.
ADPCM word placement, within the ST-BUS frame, is governed by the logic state applied at the ENS input pin. Referring to Figure 4, when ENS = 0, the ADPCM words are placed in channel 2 while when ENS = 1 the ADPCM words are placed in channel 3. Unlike the PCM octets the ADPCM words never reside within the ST-BUS channel 0 or 1 timeslots.
PCM Port Operation (DSTi, DSTo, ENB1, ENB2) The PCM port consists of DSTi, DSTo, ENB1 and
ENB2. PCM port functionality is almost identical for both ST-BUS and SSI operation, the difference being from where the BCLK signal is derived and whether the enable strobes are generated internally or sourced externally.
Both channels of PCM octets are transferred over DSTi/DSTo at the bit clock rate during the channel
time defined by the input strobes at ENB1 and ENB2 or by internally generated timeslots.
For ST-BUS operation, (i.e., when a valid ST-BUS frame pulse is applied to the F0i
input) the bi t r at e, at
2.048 MHz, is generated internally from the master clock input at the MCLK pin. The BCLK and ENA inputs are ignored. ST-BUS timeslot assignment is also generated internally and can be programmed into channels 0 and 1 or into channels 2 and 3 with the ENS input pin. Refer to Figure 4. In this mode the ENB1 and ENB2 inputs are ignored by the device. The decoded channel timeslots (0 and 1 or 2 and 3) are made available, along with the 2.048 MHz bit clock, at EN1, EN2 and C2o for controlling CODEC devices as shown in the Applications section (refer to Figures 7 and 11). Data is latched into the DSTi pin at the three-quarter bit position which occurs at the second rising edge of MCLK (C4i
) within th e bit cell boundary. Output data, on DSTo, is made available at the first falling edge of MCLK (C4i
) within
the bit cell b oun d ary. Refer to Figu re 1 2 .
For SSI operation, (i.e., when F0i is tied continuously to V
) the bit rate is set by the input clock presented
SS
at the BCLK pin. Data is transferred at the bit clock rate (BCLK) during the B1 and B2 channels as defined by input strobes ENB1 and ENB2, respectively. Note that ENB1 and ENB2 are also used as the framing inputs for internal operation of
ENB1
ENB2
DSTi/o
ENA
ADPCMi/o
8 bits
8 bits
B1 Channel B2 Channel
4 bits 4 bits
4 bits
B1 B2
Normally ENA is derived from the same strobes which drive the ENB1 or ENB2 inputs. However, as long as ENA is eight cycles of BCLK length, it may be positioned anywhere within the 8 kHz frame.
4 bits
B1 B2
Figure 3 - SSI Mode Relative Timing
8-21
MT9125 Preliminary Information
F0i
Channel 0 Channel 1 Channel 2 Channel 3
DSTi/o
EN1
EN2
ADPCMi/o
EN1
EN2
ADPCMi/o
In ST-BUS mode the ENA, ENB1 and ENB2 input strobes are ignored. All timing is dervied internally from the F0i
B1 B2 B1 B2
B1 B2
, MCLK and ENS inputs.
Figure 4 - ST-BUS Mode Relative Timing
ENS=0
ENS=1
B1 B2
the device and must, therefore, be present whenever a transcoding operation is required. These inputs may be tied together and connected to the same strobe for single channel operation. Only the B1 nibble is valid in this mode. Data is latched into the DSTi pin with the falling edge of the bit clock while output data is made available at DSTo on the rising edge of the bit clock.
ST-BUS Conversion (
F0i, C2o, EN1, EN2, ENS)
A simple converter circuit is incorporated which allows ST-BUS signals to be converted to SSI signals. In this manner it is very simple for an ST­BUS application to be mixed with CODECs utilizing a strobed data I/O.
This converter circuit consists of the F0i
input and C2o, EN1 and EN2 output pins (as well as the MCLK input master clock). The output C4b pulse strobe (F0b
), from the ST-BUS layer 1
clock and frame
transceiver, are connected directly to the master clock (MCLK) and frame pulse (F0i
) inputs of the transcoder. A 2.048 MHz (C2o) bit clock output is made available when a valid Frame Pulse is connected to t he F0i the F0i
pin is tied low the C2o output is forced
pin or the F0i pin is tied high. If
continuously to a logic low level (not tri-stated).
Forcing the C2o output to logic low enhances power conservation as well as removing a non-required clock signal from the circuit . This 2.048 MHz bit clock may be used to control external CODEC functions.
The 4.096 MHz and frame pulse signals are also decoded into two output strobes corresponding to the B1 and B2 channel timeslots of the ST-BUS. These strobes (EN1 and EN2) are then used to control the timing inputs of an external CODEC. A typical exam ple of this connection schem e is shown in the application diagram of Figure 7.
The Enable Strobe pin (ENS) is used to position the output strobes EN1 and EN2 within the ST-BUS frame. Referring to Figure 4, when ENS=0 the output strobes are positioned in channels 0 and 1 of the ST­BUS frame. When ENS=1 the output strobes are positioned in channels 2 and 3 of the ST-BUS frame. This flexibility allows the transcoder to be used in ST-BUS basic rate applications where channels 0 and 1 are defined as the D and C channels, respectively, and also in line-card applications where the full 2.048 MHz bandwidth is used for conveying data and/or digitally encoded voice information.
8-22
Preliminary Information MT9125
Mode Sel ection (MS1, MS2, M S3, M S4)
DSTo
DSTi
Separate mode select pins are available for per­channel B1 and B2 operation. MS1 and MS2 are used to configure the B1 channel while MS3 and MS4 configure the B2 channel. Normally the mode select pins are operated as static control lines. The exception to this is for on-the-fly programming to/ from 32 kbit/s from/to 24 kbit/s modes.
ADPCMi
ADPCMo
B1 B2
3 2 1 0
Dual ADPCM Transcoder
3 2 1 0
ADPCM i/o
B1 Channel
B2 Channel
MS2 MS1 Operational Mode MS4 MS3
0
0
algorithm reset
0
1
ADPCM bypass mode
0 0
0 1
(24 or 32 kbit/s)
1
0
24 kbit/s ADPCM mode
1
1
32 kbit/s ADPCM mode
1 1
0 1
Algorithm Reset Mode
An algorithm reset is accomplished by forcing all mode select pins simultaneously to logic zero. While asserted, this will cause the device to incrementally converge the internal variables of both channels to the 'Optional reset values' per G.721. Invoking the reset conditon on only one channel will cause that channel to be reset properly and the other channel’s operation to be undefined. This optional reset requires that the master clock (MCLK) and frame pulse (ENB1/2 or F0i
) remain active and that the reset cond i tion b e va li d f or a t l e ast four frame s. Note that this is not a power down mode.
ADPCM By-Pass Mode
DSTi/o
In ADPCM by-pass mode, the B1 and B2 channel ADPCM words are transpa ren tl y passed (wi th a two frame delay) to the most significant nibbles of the PCM octets. This feature allows two voice terminals, which utilize ADPCM transcod­ing, to communica te throu gh a system (i.e., PBX, key- system) without incurring unnecessary transcode conversions. This arrangement also allows byte-wide or nibble-wide transport through a switching matrix.
3 2 1 0 3 2 1 0
X X X X X X X X
B1 B2
Figure 5 - ADPC M By-pa ss Mo de
requirements necessary for on-the-fly control of the Mode Select pins. The 3-bit ADPCM words occupy the most significant bit positions of the standard 4-bit ADPCM word .
32 kbit/s AD PCM M ode
In 32 kbit/s mode PCM octets are transcoded into four bit words as described in CCITT G.721. This is the standard mode of operation and, if the other modes are not required, can be implemented by simply tying the per-channel mode select pins to VDD.
In ADPCM bypass mode the B1 and B2 channel words are transparently relayed (with a two-frame delay) to/from the ADPCM port and placed into the most significant nibbles of the B1 and B2 channel PCM octets. Refer to Figure 5. The ability to transfer ADPCM words transparently through the transcoder enables set-to-set connections for wireless telephony applications.
24 kbit/s Mode
In 24 kbit/s mode (CCITT G.723) PCM octets are transcoded into three bit words rather than the four bit words of the standard 32 kbit/s ADPCM. This is useful in situations where lower bandwidth transmission is required. Dynamic operation of the mode select control pins will allow switching from 32 kbit/s mode to 24 kbit/s mode on a frame by frame basis. Figure 6 shows the internal pipelining of the conversion sequence and how the mode select pins are to be used. Fig. 15 details the timing
Master Clock (MCL K)
A 4.096 MHz master clock is required for execution of the dual transcoding algorithm. The algorithm requires 512 cycles of MCLK during one frame for proper operation. This input, at the MCLK pin, may be asynchronous with the 8 kHz frame provided that the lowest frequency, and/or deviation due to clock jitter, still meets the minimum strobe period requirement of 512 t
-50nSec. (See AC Electrical
C4P
Characteristics - Serial PCM/ADPCM Interface s.)
For example, a system producing large jitter values can be accommodated by running an over-speed MCLK to ensure that a minimum 512 MCLK cycles per frame is obtained. The minimum MCLK period is 190 nSeconds, which translates to a maximum frequency of 5.26 MHz. Extra MCLK cycles (>512/ frame) are acceptable because the transcoder is re­aligned by the appropriate strobe signals each frame.
8-23
MT9125 Preliminary Information
frame n-1 frame n frame n+1
DSTi
PCM Byte "X" processed according
to MSn input states latched during
1,0=24 kb / s
ADPCMo
ENA
ENB1 or EN1
MS1/3
MS2/4
PCM Byte "X" latched into device
during frame n-1
1,1=32 kb / s
This diagram shows the conversion seque nce fro m PCM to ADPCM. The same pipelining occu rs in the reverse ADPCM to PCM direction. Total delay from data input to data output = 2 frames. See Figure 15 for detailed ENB1/EN1 timing.
Figure 6 - Pi peli ning for Dynam ic 32 /24 kb /s O pera tion
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK must be eight periods in duration and synchronous with the 8 kHz frame input at ENB1. Data is sampled at DSTi and at ADPCMi concurrent with the falling edge of BCLK. Data is available at DSTo and ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128 kHz and 2.048 MHz. Refer to Figures 12 and 13.
ADPCM Word "X" output from
frame n
device during fram e n+1
1,1=32 kb/s
FORMAT
01
PCM Code
+ Full Scale 1111 1111 100 0 0000 1010 1010
+ Zero 1000 0000 1111 1111 1101 0101
Magnitude
= 0 or 1
A/µ
Sign-
CCITT (G.711)
(A/µ
= 0) (A/µ = 1)
For ST-BUS operation BCLK is ignored and the bit rate is internally set to 2.048 MHz.
PCM Law Control (A/µ
, FORMAT)
The PCM companding/coding law invoked by the transcoder is controlled via the A/µ
and FORMAT
pins. CCITT G.711 companding curves, µ-Law and A-Law, are determined by the A/µ
pin (0 =µ­Law; 1=A-Law). Per sample, digital code assignment can conform to CCITT G.711 (when FORMAT=1) or to Sign-Magnitude coding (when FORMAT=0). Table 1 illustrates th ese ch o ice s.
8-24
- Zero 0000 0000 0111 1111 0101 0101
- Full Scale 0 111 1111 0000 0000 0010 1010
Table 1
Processing Delay through the Device
One 8 kHz frame is required for serial loading of the input buffers, and one frame is required for processing, for a total of two frame delays through the device. All internal input/output PCM and ADPCM shift registers are parallel loaded through secondary buffers on an internal frame pulse. The device derives its internal frame reference from the F0i
, ENB1 and ENB2 pins in the following manner. If
a valid ST-BUS fram e pulse is present at the F0i
pin the transcoder will assume ST-BUS operation and will use this input as the frame reference. In this
Preliminary Information MT9125
D
MT8910
T
R
Lin+ L
in
L
out
L
out
F0b
­C4b
+
­DSTo
DSTi
MT9125
C2o BCLK F0i MCLK
ADPCMi ADPCMo ENA
ENS
EN1 EN2
DSTi DSTo ENB1 ENB2
X
D
R
FS
X
FS
R
BCLK MCLK
D
X
D
R
FS
X
FS
R
BCLK MCLK
V
FxL+
V
FxL-
X
V
FRO
X
V
FxL+
V
FxL-
X
V
FRO
X
S
L
I
C
T
R
S L
I
C
T
R
FPi C4i
DSTi
DSTo
Gate Array
Ring
Generator
to SLICs
Hookswitch from SLIC s
MT9125
C2o BCLK F0i MCLK
ADPCMi ADPCMo ENA
ENS
EN1 EN2
DSTi DSTo ENB1 ENB2
V
DD
D
X
D
R
FS
X
FS
R
BCLK MCLK
D
X
D
R
FS
X
FS
R
BCLK MCLK
V
FxL+
V
FxL-
X
V
FRO
X
V
FxL+
V
FxL-
X
V
FRO
X
S L
I
C
T
R
S L
I
C
T
R
Figure 7 - Pair Gain Application (ST-BUS/SSI)
MT8910
T
R
Lin+ L
in
L
out
L
out
F0b
­C4b
+
­DSTo
DSTi
MT9125
C2o BCLK F0i MCLK
ADPCMi ADPCMo ENA
ENS
EN1 EN2
DSTi DSTo ENB1 ENB2
Dout Din
Ain+
STB1
Ain-
CLK
Aout
Dual Codec
2 x
R
S L
I
C
T
R
T
DSTi
DSTo
Gate Array
Ring
Generator
to SLICs
FPi C4i
MT9125
C2o
ENS
V
DD
BCLK
Hookswitch from SLICs
F0i MCLK
ADPCMi ADPCMo ENA
EN1 EN2
DSTi
DSTo ENB1 ENB2
Figure 8 - Pair Gain Application (ST-BUS/ST-BUS)
Dout Din STB1
Ain+
CLK
Aout
Dual Codec
Ain-
2 x
S L
C
R
T
I
R
T
8-25
MT9125 Preliminary Information
configuration the ENB1 and ENB2 inputs are ignored. If F0i
is tied continuously to VSS, then SSI operation will be assumed and the transcoder will use the strobes connected to ENB1 and ENB2 as its internal reference.
Power-Down Operation (PWRDN
)
To minimize power consumption a pin selected, power- down option is provided. Device pow er down is accomplished by forcing the PWRDN
pin to VSS. This asynchronous control forces all internal clocking to halt and the C2o, EN1, EN2, DSTo and ADPCMo outputs to become tri-stated. Upon returning PWRDN
to VDD coincident with the next alignment signal, all outputs will return to their active state and the internal clocks are re-started. In this mode the ADPCM algorithm is not reset to the 'optional reset values', however, the self-convergent nature of the algorithm will ensure that convergence of the (AD)PCM streams will occur within 3496 frames as specified by CCITT G.721.
Removal of the BCLK and MCLK inputs is not necessary during power-down mode. If the device is released from power-down without a valid MCLK the ADPCMo and PCMo outputs will become active, driving either continuous logic high or logic low, until a MCLK signal is applied to resume internal operation.
PWRDN is a schmidt trigger input.
Applications
Various configurations of Pair Gain drops are depicted in Figures 7, 8 and 9. These show applications using mixed ST-BUS/SSI, all ST-BUS and all SSI implementations. Figure10 shows an ST­BUS line card application for Pair Gain while Figure 11 shows a 2-channel, wireless-set, base station application based upon ST-BUS.
V
MT9125
DD
BCLK
T
R
Lin+ L
-
in
L
+
out
L
-
out
Gate
Array
Ring
Generator
to SLICs
BCLK
MCLK
TX
RX
EN1 EN2
Hookswitch from SLIC s
F0i
MCLK
ADPCMi ADPCMo ENA
MT9125
BCLK F0i
MCLK
ADPCMi ADPCMo ENA
ENS
DSTi
DSTo ENB1 ENB2
ENS
DSTi DSTo ENB1 ENB2
V
DD
D
X
D
R
FS
X
FS
R
BCLK MCLK
D
X
D
R
FS
X
FS
R
BCLK MCLK
D
X
D
R
FS
X
FS
R
BCLK MCLK
D
X
D
R
FS
X
FS
R
BCLK MCLK
V
FxL+
V
FxL-
X
V
FRO
X
V
FxL+
V
FxL-
X
V
FRO
X
V
FxL+
V
FxL-
X
V
FRO
X
V
FxL+
V
FxL-
X
V
FRO
X
S L
I
C
S
L
I
C
T
R
T
R
S
L
I
C
T
R
S L
I
C
T
R
8-26
Figure 9 - Pair Gain Application (SSI/SSI)
Preliminary Information MT9125
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AA
V
MT8910
L
+
in
L
-
in
L
+
out
L
-
out
FPob
F0b
C4b
DSTo
DSTi
C4ib
MT9125
C2o BCLK F0i MCLK
ADPCMi ADPCMo ENA
ENS
EN1 EN2
DSTi
DSTo ENB1 ENB2
DD
DSTi
DSTo
FPib
FPob
FPib
DSTo
DSTi C4ib
1
MT8980
B Channel Switch
DSTi
DSTo
C4ib
FPb
System Frame pulse or delayed frame pulse from previous selectio n
MT8980
C & D Channel
Switch
1/2 bandwidth unusable
T
R T
MT89xx
L
out
L
in
L
in
F0b
C4b
DSTo
DSTi
MT9125
C2o BCLK F0i MCLK
ADPCMi ADPCMo ENA
ENS
EN1 EN2
DSTi DSTo ENB1 ENB2
FPib
FPob
FPib
FPob
Figure 10 - Application (ST-BUS Line Card)
V
DD
MT9125
C2o BCLK F0i MCLK
DSTi DSTo
ENS
EN1 EN2
ADPCMi ADPCMo
DSTo
DSTi
C4ib
7
DSTo
DSTi
C4ib
8
BIT CLOCK ADPCM ENABLE
RFB1
R
The layer 1 device shown may be the 2-wire MT8910 or MT8972 or the 4-wire MT8930.
L
out
ENB1 ENB2
B1 B2
B0B1B2B3
B4B5B6B7
B1 B2
B0B1B2B3
ENB1 (and ENA)
Figure 11 - Application (2-Channel, Wireless-set, Base Station)
B0B1B2B3
B0B1B2B3
XXXX
B4B5B6B7
B0B1B2B3
ENB2
ENA
RFB2
2 Channel RF Section
ADPCM nibbles concat enated into one 8 bit times l ot
B2B1
Normal ST-BUS channel assignme nt
B0B1B2B3
In ADPCM by-pass mode (MS pin contro l) the ADPCM nibbles are automatical ly
XXX
inserted into the most significant nibbles
X
of the 8-bit DSTi/o B1 and B2 bytes.
8-27
MT9125 Preliminary Information
Absolute Maximum Ratings*
Parameter Symbol Min Max Units
1 Supply Voltage V 2 Voltage on any I/O pin V 3 Continuous Current on any I/O pin I 4 Storage Temperature T 5 Power Dissipation P 6 Latch-up Immunity I
* Exceeding these values may cause pe rman ent dama ge . Function al operati on under these co nditi ons is not implie d.
DD-VSS
| V
i
o
| I
i
o
ST
D
LU
Recommended Operating Conditions - Voltages are with respect to ground (V
Characteristi cs Sym Min Typ
1 S upply Voltage V 2 Input High Voltage V 3 In put Low Voltage V 4 Operating Temperature T
‡ Typ ical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
DD
IH IL A
4.5 5.0 5.5 V
2.4 V 0 0.4 V 400m V noise margin
-40 85 °C
DC Electrical Characteristics - Voltages are with respect to ground (V
Characteristics Sym Min Typ
‡
Max Units Test Conditions
DD
) unless otherwise stated.
SS
‡
Max Units Test Conditions
-0.3 7.0 V
-0.3 VDD+ 0.3 V
-65 15 0 °C
±100 mA
) unless otherwise stated.
SS
V 400m V noise margin
±20 mA
500 mW
1 Supply Current
static
operating
I
2 High level input voltage V 3 Low level input voltage V 4 Input leakage current I
IH/IIL
I
CC
DD1
IH IL
2.0 V All inputs except PWRDN
100
5
µA
mA
PWRDN = 0 PWRDN
0.8 V All inputs except PWRDN
0.1 10 µAVDD=5.5V, V
IN=VSS
5 High level output voltage VOH 2.4 V 6 Low level output voltage V 7 Output low (sink) current I 8 Output high (source) current I 9 High impedan ce leakage I
10 Output capacitance C
11 Input capacita nce C
12 Positive Going Threshol d
Voltage (PWRDN
only) Hysteresis Negative Going Threshold Voltage (PWRDN
‡ Typ ical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
only)
OL
4.0 15 mA VOL=0.4V , VDD=4.5V
4.0 10 mA VOH=2.4V, VDD=4.5V 110µAVDD=5.5V,
10 pF
i
15 pF
3.7
-
1.0
V
OL OH OZ
V+
+
V
o
-V
-
0.4 V
1.3
V
IN=VSS
V V
V
= 1, clocks active
to V
DD
to V
DD
8-28
Preliminary Information MT9125
AC Electrical Characteristics† - Serial PCM/ADPCM Interfaces (see Figures 12 & 13)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ
†
Max Units Test Conditions
1 Data Clock High t 2 Data Clock Low t 3 BCLK Period t 4 Data Output Delay (excluding
first bit) t 5 Output Active to High Z t 6 Strobe Signal Setup t
7 Strobe Signal Hold t
8 Strobe period relative to MCLK
(ENB1, ENB2, ENA ) 9 Data Input Setup t
10 Data Input Hold t 11 Strobe to Data Dela y (fi rst bit) t 12 F0i 13 F0i 14 MCLK (C4i
Setup t Hold t
) duty cycle tH/t
CLH CLL BCL
DD
AHZ
SSS
SSH
DIS DIH
SD F0iS F0iH
x100
160 ns CL=150pF 160 ns CL=150pF 400 7900 ns CL=150pF
60 ns CL=150pF
60 ns CL=150pF
80 t
BCL
-
ns CL=150pF
80
80 t
BCL
-
ns CL=150pF
80
512t
C4P
-
ns CL=150pF
50 50 ns CL=150pF 50 ns CL=150pF
60 ns CL=150pF 50 122 150 ns CL=150pF 50 122 150 ns CL=150pF
L
40 50 60 % C
=150pF
L
15 MCLK (C4i 16 Data Output delay t 17 Data in Hold time t 18 Data in Setup time t
† Timing is over recommended temperature & power supply voltages. ‡ Typ ical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
) period t
C4P
DSToD
DSTiH DSTiS
190 244.2 ns CL=150pF
125 ns CL=150pF 50 ns CL=150pF 50 ns CL=150pF
8-29
MT9125 Preliminary Information
t
BCL
BCLK
S S
ENB1
I
or
t
SSS
ENB2
DSTi
t
SD
DSTo
S
MCLK
T
­B U S
F0i
t
F0iS
t
F0iH
b7 b6 b5 b1 b0
t
DSTiS
b7 b6 b5 b1 b0
t
H
t
L
t
t
DSTiH
CLH
t
DIS
t
t
CLL
DIH
t
DSToD
V
IH
V
t
SSH
t
DD
t
C4P
t
AHZ
IL
V
IH
V
IL
V
IL
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
S S I
S T
­B U S
BCLK
ENA
ADPCMi
ADPCMo
MCLK
F0i
Figure 12- Serial PCM Port Timing
t
BCL
t
SSS
b1-1 b1-2 b1-3
t
t
SD
DSTiS
b1-1 b1-2 b1-3
t
H
t
F0iH
t
L
t
CLH
t
DIStDIH
t
DSTiH
t
CLL
b2-3 b2-4
t
DD
b2-3 b2-4
t
DSToD
t
C4P
t
AHZ
t
SSH
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
8-30
t
F0iS
Figure 13 - Serial ADPCM Port Timing
Preliminary Information MT9125
AC Electrical Characteristics† - ST-BUS Conversion (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ
†
Max Units Test Conditions
1 Delay MCLK falling to C2o rising t 2 Delay MCLK falling to Enable t
† Timing is over recommended temperature & power supply voltages. ‡ Typ ical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
F0i
MCLK (C4i
)
t
D1
C2o
EN1 EN2
t
D2
D1 D2
100 ns 150pF Load 100 ns 150pF Load
t
D2
Figure 14 - ST-BUS Timing for External Signal Generation
V
IH
V
IL
V
IL
V
IL
V
OH
V
OL
V
OH
V
OL
AC Electrical Characteristics† - Mode Select Timing (see Figure 15)
Voltages are with respect to ground (VSS) unless otherwise stated.
t
HOLD
†
Max Units Test Conditions
500 ns
Characteristics Sym Min Typ
1 Mode Select Setup t 2 Mode Select Hold t
† Timing is over recommended temperature & power supply voltages. ‡ Typ ical figures are at 25°C and are for design aid only: not guaranteed and not subject to producti on testing.
MS1-MS4
ENB1 (SSI Mode)
EN1 (ST-BUS Mode)
SU
HOLD
500 ns
t
SU
Figure 15 - Mode Select Set-up and Hold Timing for Dynamic Operation
8-31
MT9125 Preliminary Information
NOTE S:
8-32
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