Datasheet MT9074AP, MT9074AL Datasheet (MITEL)

MT9074

T1/E1/J1 Single Chip Transceiver

Advance Information

Features

• Combined E1 (PCM 30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode

• In T1 mode the LIU can recover signals attenuated
by up to 36 dB (6000 ft. of 24 AWG cable)

• In E1 mode the LIU can recover signals attenuated
by up to 36 dB (2000 m. of 0.65mm cable)

• Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode

• Two-frame elastic buffer in Rx & Tx (T1) directions

• Programmable transmit dela y through tr ansmit slip
buffer

• Low jitter DPLL for clock generation

• Enhanced alarms, performance monitoring and
error insertion functions

• Intel or Motorola non-multiplexed parallel
microprocessor interface

• ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling

• Japan Telecom J1 Framing and Yellow Alarm

• Hardware data link access

• JTAG Boundary Scan

Applications

• E1/T1 add/drop multiplexers and channel banks

• CO and PBX equipment interfaces

• Primary Rate ISDN nodes

• Digital Cross-connect Systems (DCS)

DS5024 ISSUE 5 September 1999

Ordering Information

MT9074AP 68 Pin PLCC
MT9074AL 100 Pin MQFP

-40°C to 85°C

Description

The MT9074 is a single chip device, operable in
either T1 or E1 mode, integrating either an advanced
T1 (T1 mode) or PCM 30 (E1 mode) framer with a
Line Interface Unit (LIU).

The framer interfaces to a 2.048 Mbit/s backplane
providing selectable data link access with optional
HDLC controllers for either the FDL bits and channel
24 (T1 mode) or Sa bits and channel 16 (E1 mode).
The LIU interfaces the framer to T1 (T1 mode) or
PCM 30 (E1 mode) transformer-isolated four-wire
line with minimal external components required.

In T1 mode the MT9074 supports D4, ESF and SLC­96 formats, meeting the latest recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T1.403 and T1.408. In E1 mode the
MT9074 supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also supports ETSI ETS 300
011, ETS 300 166 and ETS 300 233.

DSTi
CSTi

Tdi

Tdo

Tms
Tclk

Trst

IRQ

D7~D0

AC4

AC0

R/W/WR

CS

DS/RD

DSTo
CSTo

ST-BUS

Interface

ST Loop

IEEE

1149.1

Interface

Microprocessor

ST-BUS

Interface

RxDLCLK RxDL

TxDL TxDLCLK

Data Link,

HDLC0

HDLC1

Alarm Detection, 2 Frame Slip Buffer

Figure 1 - Functional Block Diagram

TxMF

Transmit Framing, Error,

Test Signal Generation and Slip Buffer

PL Loop

National

Bit Buffer

CAS

Buffer

Receive Framing, Performance Monitoring,

TxAO TxB TxA

DG Loop

RxFP

Pulse

Generator

Jitter Attenuator

& Clock Control

Recovery

Clock,Data

E1.5o

F0b C4bRxMF LOS

Line

Driver

RM

Loop

MT

Rx Equalizer

& Data Slicer

Loop

TTIP
TRING

S/FR
BS/LS

OSC1
OSC2

RTIP
RRING

1

MT9074 Advance Information

RESET

INT/

R/

W/WR

CS

IRQ

D0
D1
D2
D3

VSS

MOT
VDD

D4
D5
D6
D7

AC0

DSTo

DS/RD

DSTi

CSTi

CSTo

987654321
10
11
12
13
14
15
16
17
18

IC

19
20
21
22
23
24
25
26

27

282930313233343536373839404142

AC1

AC2

AC3

AC4

GNDARx

VDD

RTIP

VSS

OSC2

RRING

VDDArx

OSC1

VDD

VSS

VDD

TxDLICIC

TxLCLK

S/FR/C1.5i

68676665646362

TxA

TxB

VSS

RxDL

RxDCLK

TxMF

LOS

61
60

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

RxMF

BS/LS

TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o

68 PIN PLCC

RESET

INT/

R/

NC
NC
CS

IRQ

D0
D1
D2
D3

VSS

IC
MOT
VDD

D4
D5
D6
D7

W/WR

AC0

NC

82

84

86

88

90

92

94

96

98

100

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSS

VDD

CSTo

CSTi

DSTo

DSTi

DS/RD

NC

NCNCNC

AC2

AC1

AC3

AC4

RTIP

GNDARx

OSC1

OSC2

RRING

VDARx

VSS

VDD

VDD

VSS

100 PIN MQFP (JEDEC MO-112)

FR/C1.5i

TXDL

S/

TxB

TxA

TCDLCK

22 24 26 28 30

2018161412108642

RXDL

RXDLCK

TxMF

RxMF

NC

BS/LS

LOS

IC

NC

IC

NCNCNC

NC

525456586062646668707274767880

50

48

46

44

42

40

38

36

34

32

NCNCNCNCNC

NC

NC
NC
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o
NC

Figure 2 - Pin Connections

2

Advance Information MT9074

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

1 66 OSC1 Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2

2 67 OSC2 Oscillator Output. Connect a 20.0 MHz crystal between OSC1 and OSC2. Not

368 VSSNegative Power Supply (Input). Digital ground.
469 VDDPositive Power Supply (Input). Digital supply (+5V ± 5%).
5 70 CSTo Control ST-BUS Output. CSTo carries serial streams for CAS and CCS

Name Description

where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is
employed.

suitable for driving other devices.

respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive
signalling nibbles (ABCDZZZZ or ZZZZABCD). The most significant nibbles of
each ST-BUS time slot are valid and the least significant nibbles of each ST-BUS
time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set
to 1. If MSN=0, the position of the valid and tristated nibbles are reversed.

6 71 CSTi Control ST-BUS Input. CSTi carries serial streams for CAS and CCS respectively

a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling
nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this pin
has no function. The most significant nibbles of each ST-BUS time slot are valid
and the least significant nibbles of each ST-B US time slot are ignored when control
bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the
valid and ignored nibbles is reversed.

7 72 DSTo Data ST-BUS Output. A 2.048 Mbit/s serial stream which contains the 24/30

PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.

8 73 DSTi Data ST-BUS Input. A 2.048 Mbit/s serial stream which contains the 24/30 (T1/

E1)PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)line.

974DS/RD Data/Read Strobe (Input).

In Motorola mode (DS), this input is the active low data strobe of the
microprocessor interface.
In Intel mode (RD), this input is the active low read strobe of the microprocessor
interface.

10 83 CS Chip Select (Input). This active low input enables the non-multiplexed parallel

microprocessor interface of the MT9074. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance
state.

11 84 RESET RESET (Input). This active low input puts the MT9074 in a reset condition. RESET

should be set to high for normal operation. The MT9074 should be reset after
power-up. The RESET pin must be held low for a minimum of 1µsec. to reset the
device properly.

12 85 IRQ Interrupt Request (Output). A low on this output pin indicates that an interrupt

request is presented. IRQ is an open drain output that should be connected to V
through a pull-up resistor. An active low CS signal is not required for this pin to
function.

13 -1686-89 D0 - D3 Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the

bidirectional data bus of the microprocessor interface (D0 is the least significant
bit).

DD

3

MT9074 Advance Information

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

17 90 Vss Negative Power Supply (Input). Digital ground.
18 91 IC Internal Connection. Tie to Vss (ground) for normal operation.
19 92 INT/MOT Intel/Motorola Mode Selection (Input).A high on this pin configures the

20 93 VDD Positive Power Supply (Input). Digital supply (+5V± 5%).

21 -2494-97 D4 - D7 Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the

25 98 R/W/WR Read/Write/Write Strobe (Input). In Motorola mode (R/W), this input controls the

Name Description

processor interface for the Intel parallel non-multiplexed bus type . A low configures
the processor interface for the Motorola parallel non-multiplexed type.

bidirectional data bus of the parallel processor interface (D7 is the most significant
bit).

direction of the data bus D[0:7] during a microprocessor access. When R/W is
high, the parallel processor is reading data from the MT9074. When low, the
parallel processor is writing data to the MT9074. For Intel mode (WR), this active
low write strobe configures the data bus lines as output.

26 -3099, 8-11 AC0 - AC4 Address/Control 0 to 4 (Inputs). Address and control inputs for the non-

multiplexed parallel processor interface. AC0 is the least significant input.

31 12 GND
32

33

34 15 VDD

35 16 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).
36 17 VSS Negative Power Supply (Input). Digital ground.
37 18 TxA Transmit A (Output). When the internal LIU is disabled (digital framer only

38 19 TxB Transmit B (Output). When the internal LIU is disabled and control bit NRZ=0,

13
14

RTIP

RRING

Receive Analog Ground (Input). Analog ground for the LIU receiver.

ARx

Receive TIP and RING (Input). Differential inputs for the receive line signal - must

be transformer coupled (See Figure 5). In digital framer mode these are TTL level
inputs that connect to the digital outputs of a receiver. If the receiver serial data
output is NRZ connect that output to RTIP. If the receiver data output is split phase
unipolar signal connect one signal to RTIP and the complementary signal to
RRING.

Receive Analog Power Suppl y (Input). Analog supply for the LIU receiv er (+5V±

ARx

5%).

mode), if control bit NRZ=1, and NRZ output data is clocked out on pin TxA with
the rising edge of C1.50 (TxB has no function when NRZ format is selected). If
NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital
dual-rail clocked out with the rising edge of C1.50.

pins TxA and TxB are a complementary pair of signals that output digital dual-rail
data clocked out with the rising edge of C1.50.

39 20 RxDLCLK Data Link Clock (Output). A gapped clock signal derived from the extracted clock

from the line clock, available for an external device to clock in RxDL data (at 4, 8,
12, 16 or 20 kHz) on the rising edge.

40 21 RxDL Receive Data Link (Output). A serial bit stream containing received line data after

zero code suppression. This data is clocked out with the rising edge of E1.5o.

41 22 TxMF Transmit Multiframe Boundary (Input). An active low input used to set the

transmit multiframe boundary (CAS or CRC multiframe). The MT9074 will generate
its own multiframe if this pin is held high. This input is usually pulled high for most
applications.

4

Advance Information MT9074

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

42 23 RxMF Receive Multiframe Boundary (Output). An output pulse delimiting the received

43 24 BS/LS Bus/Line Synchronization Mode Selection (Input). If high, C4b and F0b will be

44 32 E1.5o/C1.5o 2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (Output).

45 33 C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS

Name Description

multiframe boundary. The next frame output on the data stream (DSTo) is basic
frame zero on the T1 or PCM 30 link. In E1 mode this receive multiframe signal
can be related to either the receive CRC multiframe (page 01H, address 17H, bit 6,
MFSEL=1) or the receive signalling multiframe (MFSEL=0).

inputs; if low, C4b and F0b will be outputs.

If the internal L/U is enabled, this output is the clock extracted from the received
signal and used internally to clock in data received on RTIP and RRING. If the
internal LIU is disabled (digital framer mode), this output is a 1.544MHz clock
(T1) C1.5o or a 2.048 MHz clock C2o which clocks out the transmit digital data
TXA, TXB.

sections and transmit serial PCM data of the MT9074. In the free-run (S/FR=0) or
line synchronous mode (S/FR=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR=1) this signal is an input clock which is phase­locked to the extracted clock (E1.5o).

46 34 F0b Frame Pulse (Input/Output). This is the ST-BUS frame synchronization signal,

which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the PCM30
link. In the free-run (S/FR=0) or line synchronous mode (S/FR=1 and BS/LS=0)
this signal is an output, while in the line synchrounous mode (S/FR=1 and BS/
LS=0) this signal is an input.

47 35 RxFP Receive Frame Pulse (Output). An 8kHz pulse signal, which is low for one

extracted clock period. This signal is synchronized to the receive DS1 or PCM 30
basic frame boundary.

48 36 IC Internal Connection. Must be left open for normal operation.
49 37 V
50 38 V
51 39 VDD

SS
DD

Negative Power Supply (Input). Digital ground.
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter

ATx

(+5V ± 5% 10%)).

52
53

54 42 GND

40
41

TTIP

TRING

ATx

Transmit TIP and RING (Outputs). Differential outputs for the transmit DS1 line

signal - must be transformer coupled (See Figure 5).

Transmit Analog Ground (Input). Analog ground for the LIU transmitter.
55 43 Tdi IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high.
56 44 Tdo IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected.
57 45 Tms IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled

high.

58 46 Tclk IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high.
59 47 Trst IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low.
60 48 TxAO Transmit All Ones (Input).High - TTIP, TRING will transmit data normally. Low -

TTIP, TRING will transmit an all ones signal.

5

MT9074 Advance Information

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

61 57 LOS Loss of signal or synchronization (Output).When high, and LOS/LOF (page

62 58 IC Internal Connection. Tie to Vss (Ground) for normal operation.

59 NC No Connection. Leave open for normal operation.
63 60 IC Internal Connection. Tie to VSS (Ground) for normal operation.
64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated

Name Description

02H address 13H bit 2) is zero, this signal indicates that the receive por tion of the
MT9074 is either not detecting an incoming signal (bit LLOS on page 03H address
18H is one) or is detecting a loss of basic frame alignment condition (bit SYNC on
page 03H address 10H is one). If LOS/LOF=1, a high on this pin indicates a loss of
signal condition.

2.048 Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data
link data (TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also
be used to clock DL data out of an external serial controller.

65 62 TxDL Transmit Data Link (Input). An input serial stream of transmit data link data at 4,

8, 12, 16 or 20 kbit/s.

66 63 S/FR/C1.5i Sychronous/Freerun Extracted Clock (Input): If low, and the internal LIU is

enabled, the MT9074 is in free run mode. Pins 45 C4b and 46 F0b are outputs
generating system clocks. Slips will occur in the receive slip buffer as a result of
any deviation between the MT9074's internal PLL (which is free - running) and the
frequency of the incoming line data. If high, and the internal LIU is enabled, the
MT9074 is in Bus or Line Synchronization mode depending on the BS/LS pin. If
the internal LIU is disabled, in digital framer mode, this pin (C1.5i) takes an input
clock 1.544Mhz (T1) / 2.048Mhz (E1) that clocks in the received digital data on
pins RTIP and RRING with its rising edge.

67 64 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).
68 65 VSS Negative Power Supply (Input). Digital ground.

Device Overview

The MT9074 in T1 mode operates as an advanced
T1 framer with an on-chip Line Interface Unit (LIU)
that meets or supports the recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T.403 and T.408.

DS1 (T1 mode) or PCM 30 (E1 mode) transformer­isolated four wire line. The transmit portion of the
MT9074 LIU consists of a digital buffer, a digital-to­analog converter, and a differential line driver. The
receiver portion of the MT9074 LIU consists of an
input signal peak detector, an optional equalizer, a
smoothing filter, data and clock slicers and a clock
extractor.

The MT9074 in E1 mode operates as an advanced
PCM 30 framer with an on-chip Line Interface Unit
(LIU) that meets or supports the latest ITU-T
Recommendations for PCM 30 and ISDN primary
rate including G.703, G.704, G.706, G.775, G.796,
G.732, G.823 and I.431. It also meets or supports
the layer 1 requirements of ETSI ETS 300 011, ETS
300 166, ETS 300 233 and BS6450.

The Line Interface Unit (LIU) of the MT9074
interfaces the digital framer functions to either the

6

System timing may be slaved to the line, operated in
free-run mode or controlled by an external timing
source. In T1 mode the MT9074 contains a PLL
which always generates the transmit timing for the
LIU. In E1 mode the LIU also contains a Jitter
Attenuator (JA), which can be included in either the
transmit or receive path. The MT9074 will attenuate
jitter from 2.5 Hz and roll-off at a rate of 20 dB/
decade. The intrinsic jitter is less than 0.02 UI. The
PLL output (@1.544 MHz for T1 mode and @2.048
MHz for E1 mode) clocks out the transmit line data.

Advance Information MT9074

To accommodate some special applications, the
MT9074 also supports a digital framer only mode by
providing direct access to the transmit and receive
data in digital format, i.e. by-passing the analog LIU
front-end.

The digital portion of the MT9074 connects selected
channels of an incoming stream of time multiplexed

2.048 Mbit/s PCM channels to the transmit payload
of either the T1 or E1 trunk, while the receive
payload is connected to the ST-BUS 2.048 Mbit/s
backplane bus for both data and signalling with
channel times and the frame boundary synchronous
to the transmit side. Control, reporting and
conditioning of the line is implemented via a parallel
microprocessor interface.

The MT9074 has a comprehensive suite of status,
alarm, performance monitoring and reporting
features. These include counters for BPVs, CRC
errors, F-bit errors (T1 only), E-bit errors (E1 only),
errored frame alignment signals (E1 only), BERT,
OOF (T1 only), and RAI and continuous CRC errors
(E1 only). Also, included are transmission error
insertion for BPVs, CRC-6 errors (T1 only), CRC-4
errors (E1 only), framing bit errors (T1 only), frame
and non-frame alignment signal errors (E1 only),
payload errors and loss of signal errors. A built-in
PRBS generator (215 -1) can be connected to any
combination of outgoing channels; an equivalent
PRBS error detector can be independently
connected to any combination of receive channels.

calculation is performed as part of the framing
algorithm. In the transmit transparent mode, no
framing or signalling is imposed on the data transmit
from DSTi on the line. In addition, the MT9074
optionally allows the data link maintenance channel
to be modified and updates the CRC-4 remainder
bits to reflect the modification. All channel, framing
and signalling data passes through the device
unaltered. This is useful for intermediate point
applications of a PCM 30 link where the data link
data is modified, but the error information
transported by the CRC-4 bits must be passed to the
terminating end. In the receive transparent mode,
the received line data is channelled to DSTo with
framing operations disabled, consequently, the data
passes through the slip buffer and drives DSTo with
an arbitrary alignment.

In E1 mode the Sa bits can be accessed by the
MT9074 in the following three ways:

• Programming a register;

• Data link pins TxDL, RxDL, RxDLCLK and
TxDLCLK;

• HDLC Controller with a 128 byte FIFO.

A second HDLC Controller with a 128 byte FIFO is
available for connection to timeslot 16 in E1 mode.

Functional Description

MT9074 Line Interface Unit (LIU)

A complete set of loopbacks has been implemented,
which include digital, remote, ST-BUS, payload,
local, metallic and remote time slot.

The MT9074 also provides a comprehensive set of
maskable interrupts. Interrupt sources consist of
synchronization status, alarm status, counter
indication and overflow, timer status, slip indication,
maintenance functions and receive channel
associated signaling bit changes.

In T1 mode the framer operates in any one of the
framing modes: D4, SLC-96 and Extended
Superframe (ESF). The ESF FDL bits of the MT9074
can be accessed either through the data link pins
TxDL, RxDL, RxDLCLK and TxDLCLK, or through
internal registers for Bit Oriented Messages, or
through a built-in HDLC. A second HDLC may be
connected to DS1 channel 24 for the ISDN Primary
Rate signaling applications.

In E1 mode the MT9074 operates in either
termination or transparent modes selectable via
software control. In the termination mode the CRC-4

Receiver
The receiver portion of the MT9074 LIU consists of

an input signal peak detector, an optional equalizer
with two separate high pass sections, a smoothing
filter, data and clock slicers and a clock extractor.
Receive equalization gain can be set manually (i.e.,
software) or it can be determined automatically by
peak detectors.

The output of the receive equalizer is conditioned by
a smoothing filter and is passed on to the clock and
data slicer. The clock slicer output signal drives a
phase locked loop, which generates an extracted
clock (C1.50). This extracted clock is used to sample
the output of the data comparator

In T1 mode, the receiver portion of the LIU can
reliably recover clock and data from signals
attenuated by up to 36 dB @ 772 kHz (translates to
6000 ft. of PIC 24 AWG cable) and tolerate jitter to
the maximum specified by AT&T TR 62411 (see
Figure 3).

In E1 mode the receiver portion of the LIU can
reliably recover clock and data from signals

7

MT9074 Advance Information

attenuated by up to 36 dB @ 1024 kHz (translates to
2000 m. of PIC 0.65mm or 22 AWG cable) and
tolerate jitter to the maximum specified by ETS 300
011 (Figure 4).

The LOS output pin function is user selectable to
indicate any combination of loss of signal and/or loss
of basic frame synchronization condition.

The LLOS (Loss of Signal) status bit indicates when
the receive signal level is lower than the analog
threshold for at least 1 millisecond, or when more
than 192 consecutive zeros have been received. In
E1 mode the analog threshold is either of -20 dB or ­40 dB. For T1 mode the analog threshold is -40 dB.

In T1 mode, the receive LIU circuit requires a
terminating resistor of 100Ω across the device side
of the receive 1:1 transformer.

In E1 mode the receive LIU circuit requires a
terminating resistor of either 120Ω or 75Ω across the
device side of the receive1:1 transformer.

produce an analog signal, which is passed to the
complementary line drivers.

The complementary line drivers are designed to
drive a 1:2 step-up transformer (see Figure 5 for T1
mode and Figure 6 for E1 mode). A 0.68 uF
capacitor is required between the TTIP and the
transmit transformer. Resistors RT (as shown in
Figure 5) are for termination for transmit return loss.
The values of RT may be optimized for T1 mode, E1
120Ω lines, E1 75Ω lines or set at a compromise
value to serve multiple applications. Program the LIU
Control Word (address 1FH page 1) to adjust the
pulse amplitude accordingly.

Alternatively, the pulse level and shape may be
discretely programmed by writing to the Custom
Pulse Level registers (addresses 1CH to 1FH, page

2) and setting the Custom Transmit Pulse bit high (bit
3 of the Transmit Pulse Control Word). In this case
the output of each of the registers directly drives the
D/A converter going to the line driver. Tables 1 and 2
show recommended transmit pulse amplitude
settings.

The jitter tolerance of the clock extractor circuit
exceeds the requirements of TR 62411 in T1 mode
(see Figure 3) and G.823 in E1 mode (see Figure 4).

Transmitter
The transmit portion of the MT9074 LIU consists of a

high speed digital-to-analog converter and
complementary line drivers.

When a pulse is to be transmitted, a sequence of
digital values (dependent on transmit equalization)
are read out of a ROM by a high speed clock. These
values drive the digital-to-analog converter to

Peak to Peak

Jitter Amplitude

(log scale)

138UI
100UI

28UI
10UI

In T1 mode, the template for the transmitted pulse
(the DSX-1 template) is shown in Figure 7. The
nominal peak voltage of a mark is 3 volts. The ratio
of the amplitude of the transmit pulses generated by
TTIP and TRING lie between 0.95 and 1.05.

In E1 mode, the template for the transmitted pulse,
as specified in G.703, is shown in Figure 8. The
nominal peak voltage of a mark is 3 volts for 120 Ω
twisted pair applications and 2.37 volts for 75 Ω coax
applications. The ratio of the amplitude of the
transmit pulses generated by TTIP and TRING lie
between 0.95 and 1.05.

1.0UI

0.4UI

Jitter Frequency

0.1Hz

1.0Hz

10Hz 1.0kHz 10kHz 100kHz

4.9Hz

100Hz

(log scale)

Figure 3 - Input Jitter Tolerance as Recommended by TR-62411 (T1)

8

Advance Information MT9074

Peak to Peak

Jitter Amplitude

(log scale)

18UI

MT9074

Tolerance

1.5UI

0.2UI

1.667Hz 20Hz 2.4kHz 18kHz 100kHz

Jitter Frequency

(log scale)

Figure 4 - Input Jitter Tolerance as recommended by ETSI 300 011 (E1)

Name Functional Description

TXL2-0 Transmit Line Build Out 2 - 0. Setting these bits shapes the transmit pulse as detailed in

the table below:
TXL2 TXL1 TXL0 Line Build Out
0 0 0 0 to 133 feet/ 0 dB
0 0 1 133 to 266 feet
0 1 0 266 to 399 feet
0 1 1 399 to 533 feet
1 0 0 533 to 655 feet
1 0 1 -7.5 dB
1 1 0 -15 dB
1 1 1 -22.5 dB
After reset these bits are zero.

Table 1 - Transmit Line Build Out (T1)

TTIP

TRING

RTIP

RRING

0.68uF

RT

RT

1:2

+5V

1:1

100 Ω

Figure 5 - Analog Line Interface (T1)

Fuse

Tx

Fuse

RT: 2.4 Ω

Fuse

Fuse

Rx

9

MT9074 Advance Information

Name Functional Description

TX2-0 Transmit pulse amplitude. Select the TX2 –TX0 bits according to the line type, value of

termination resistors (RT), and transformer turns ratio used
TX2 TX1 TX0 Line Impedance(Ω) RT(Ω) Transformer Ratio
0 0 0 120 0 1:2
0 0 1 120 0 1:1
0 1 0 120 15 1:2
0 1 1 120 / 75 12.1 1:2
1 0 0 75 0 1:2
1 0 1 75 0 1:1
1 1 1 75 9.1 1:2
1 1 1 75 / 120 12.1 1:2
After reset these bits are zero.

Table 2 -Transmit Pulse Amplitude (E1)

TTIP

TRING

RTIP

RRING

0.68uF

+5V

T

R

T

1:2

R

1:1

120 Ω /

75 Ω

Figure 6 - Analog Line Interface (E1)

Fuse

Fuse

Fuse

Fuse

Tx

RT: Termination resis­tor. Please check Table

2 for specific resistor
values.

Rx

10

Advance Information MT9074

1.20

1.05

0.95

0.90

0.80

0.50

0.05
0

NORMALIZED AMPLITUDE

-0.05

-0.26

-0.45

Time (Nanoseconds)

Time U.I.

Normalized Amplitude

Time (Nanoseconds)

Time U.I.

Normalized Amplitude

0

0.15

0.23

0.34

0.46

0.61

0.77

-0.39

-0.27

-0.23

--0.12

--0.15
Time, in unit intervals (UI)

0.27

0.93

1.16

Figure 7 - Pulse Template (T1.403) (T1)

-499 -253 -175 -175 -78 0 175 220 499 752 --- ---

-.77 -.39 -.27 -.27 -.12 0 .27 .34 .77 1.16 --- --­.05 .05 .8 1.2 1.2 1.05 1.05 -.05 .05 .05 --- ---

Table 3 - Maximum Curve for Figure 7

-499 -149 -149 -97 0 97 149 149 298 395 603 752

-.77 -.23 -.23 -.15 0 .15 .23 .23 .46 .61 .93 1.16

-.05 -.05 .5 .9 .95 .9 .5 -.45 -.45 -.26 -.05 -.05

Table 4 - Minimum curve for Figure 7

Note: One Unit Interval = 648 nanoseconds

11

MT9074 Advance Information

Percentage of
Nominal Peak
Voltage

120

269nS

110
100

90
80

50

20

-10

-20

244nS

194nS

0

Nominal Pulse

219nS
488nS

Figure 8 Pulse Template (G.703)(E1)

20 Mhz Clock

The MT9074 requires a 20 Mhz clock. This may
provided by a 50 ppm oscillator as per Figure 9.

+5V

OSC1

OSC2

20MHz

OUT

Vdd

GND

.1µF

(open)

Figure 9 - Clock Oscillator Circuit

Alternatively, a crystal oscillator may be used. A
complete oscillator circuit made up of a crystal,
resistors and capacitors is shown in Figure 10. The
crystal specification is as follows.

Frequency: 20MHz
Tolerance: 50ppm
Oscillation Mode: Fundamental
Resonance Mode: Parallel
Load Capacitance: 32pF
Maximum Series Resistance: 35

Ω

Approximate Drive Level: 1mW

20MHz

OSC1

56pF

1MΩ

OSC2

Note: the 1µH inductor is optional

39pF

1µH*

100Ω

Figure 10 - Crystal Oscillator Circuit

12

Advance Information MT9074

dB

-0.5

0

-20 dB/decade

JITTER ATTENUATION (dB)

19.5

10 40 400 10K

Frequency (Hz)

Figure 11- TR 62411 Jitter Attenuation Curve

Phase Lock Loop (PLL)

The MT9074 contains a PLL, which can be locked to
either an input 4.096 Mhz clock or the extracted line
clock.The PLL will attenuate jitter from less than

2.5 Hz and roll-off at a rate of 20 dB/decade. Its
intrinsic jitter is less than 0.02 UI. The PLL will meet
the jitter transfer characteristics as specified by ATT
document TR 62411 and the relevant
recommendations as shown in Figure 11.

Clock Jitter Attenuation Modes

MT9074 has three basic jitter attenuation modes of
operation, selected by the BS/LS and S/FR control
pins. Referring to the mode names given in Table 5
the basic operation of the jitter attenuation modes
are:

• System Bus Synchronous Mode.

• Line Synchronous Mode.

• Free-run mode.

In System Bus Synchronous mode pins C4b and F0b
are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are
configured as outputs.

In

System Bus Synchronous

is applied to C4b. The applied clock is dejittered by

mode an external clock

Mode Name BS/LS S/FR Note

System Bus

Synchronous

Line Synchronous 0 1 PLL locked to E1.5o.

Free-Run x 0 PLL free - running.

1 1 PLL locked to C4b.

Table 5 - Selection of clock jitter attenuation

modes using the M/S and MS/FR pins

the internal PLL before being used to synchronize
the transmitted data. The clock extracted (with no
jitter attenuation performed) from the receive data
can be monitored on pin E1.5o.

In

Line Synchronous

mode, the clock extracted from
the receive data is dejittered using the internal PLL
and then output on pin C4b. Pin E1.5o provides the
extracted receive clock before it has been dejittered.
The transmit data is synchronous to the clean
receive clock.

In

Free-Run

mode the transmit data is synchronized
to the internally generated clock. The internal clock
is output on pin C4b. The clock signal extracted from
the receive data is not dejittered and is output
directly on E1.5o.

Depending on the mode selection above, the PLL
can either attenuate transmit clock jitter or the
receive clock jitter. Table 5 shows the appropriate
configuration of each control pin to achieve the

13

MT9074 Advance Information

appropriate mode and Jitter attenuation capability of
the MT9074

The Digital Interface

T1 Digital Interface

In T1 mode DS1 frames are 193 bits long and are
transmitted at a frame repetition rate of 8000 Hz,
which results in an aggregate bit rate of 193 bits x
8000/sec= 1.544 Mbits/sec. The actual bit rate is

1.544 Mbits/sec +/-50 ppm optionally encoded in
B8ZS format. The Zero Suppression control register
(page 1, address 15H,) selects either B8ZS
encoding, forced one stuffing or alternate mark
inversion (AMI) encoding. Basic frames are divided
into 24 time slots numbered 1 to 24. Each time slot is
8 bits in length and is transmitted most significant bit
first (numbered bit 1). This results in a single time
slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.

It should be noted that the Mitel ST-BUS has 32
channels numbered 0 to 31. When mapping to the
DS1 payload only the first 24 time slots and the last
(time slot 31, for the overhead bit) of an ST-BUS are
used (see Table 6). All unused channels are tristate.

When signalling information is written to the MT9074
in T1 mode using ST-BUS control links (as opposed
to direct writes by the microport to the on - board
signaling registers), the CSTi channels
corresponding to the selected DSTi channels
streams are used to transmit the signalling bits.

The most significant bit of an eight bit ST-BUS
channel is numbered bit 7 (see Mitel Application
Note MSAN-126). Therefore, ST-BUS bit 7 is
synonymous with DS1 bit 1; bit 6 with bit 2: and so
on.

Frame and Superframe Structure in T1 mode

Multiframing
In T1 mode, DS1 trunks contain 24 bytes of serial

voice/data channels bundled with an overhead bit.
The frame overhead bit contains a fixed repeating
pattern used to enable DS1 receivers to delineate
frame boundaries. Overhead bits are inserted once
per frame at the beginning of the transmit frame
boundary. The DS1 frames are further grouped in
bundles of frames, generally 12 (for D4 applications)
or 24 frames (for ESF - extended superframe
applications) deep. Table 7 and 8 illustrate the D4
and ESF frame structures respectively.

For D4 links the frame structure contains an
alternating 101010... pattern inserted into every
second overhead bit position. These bits are
intended for determination of frame boundaries, and
they are referred to as Ft bits. A separate fixed
pattern, repeating every superframe, is interleaved
with the Ft bits. This fixed pattern (001110), is used
to delineate the 12 frame superframe. These bits are
referred to as the Fs bits. In D4 frames # 6 and #12,
the LSB of each channel byte may be replaced with
A bit (frame #6) and B bit (frame #12) signalling
information.

For ESF links the 6 bit framing pattern 001011,

Since the maximum number of signalling bits
associated with any channel is 4 (in the case of
ABCD), only half a CSTi channel is required for
sourcing the signaling bits. The choice of which half
of the channel to use is selected by the control bit
MSN (page 01H address 14H). The same control bit
selects which half of the CSTo channel will contain
receive signaling information (the other nibble in the
channel being tristate). Unused channels are tristate.

DS1 Timeslots 12345678910111213141516
Voice/Data Channels

(DSTi/o and CSTi/o)
Ds1 Timeslots 17 18 19 20 21 22 23 24 -------­Voice/Data Channels

(DSTi/o and CSTi/o)

0123456779101112131415

16 17 18 19 20 21 22 23 24x25x26x27x28x29x30x31

Table 6 - STBUS vs. DS1 to Channel Relationship(T1)

inserted into every 4th overhead bit position, is used
to delineate both frame and superframe boundaries.
Frames #6, 12, 18 and 24 contain the A, B, C and D
signalling bits, respectively. A 4 kHz data link is
embedded in the overhead bit position, interleaved
between the framing pattern sequence (FPS) and the
transmit CRC-6 remainder (from the calculation done
on the previous superframe), see Table 8.

S
bit

14

Advance Information MT9074

The SLC-96 frame structure is similar to the D4
frame structure, except a facility management
overlay is superimposed over the erstwhile Fs bits,
see Table 9.

The protocol appropriate for the application is
selected via the Framing Mode Selection Word,
address 10H of Master Control page 1. In T1 mode
MT9074 is capable of generating the overhead bit
framing pattern and (for ESF links) the CRC
remainder for transmission onto the DS1 trunk. The
beginning of the transmit multiframe may be
determined by any of the following criteria:

(i)It may free - run with the internal multiframe
counters;

(ii)The multiframe counters may be reset with the
external hardware pin TxMF. If this signal is not
synchronous with the current transmit frame count it
may cause the far end to go temporarily out of sync.

(iii) Under software control (by setting the TxSYNC
bit in page 01 address 12H) the transmit multiframe
counters will be synchronized to the framing pattern
present in the overhead bits multiplexed into channel
31 bit 0 of the incoming 2.048 Mb/s digital stream
DSTi. Note that the overhead bits extracted from the
receive signal are multiplexed into outgoing DSTo
channel 31 bit 0.

(iv) In SLC - 96 mode the transmit frame counters
synchronize to the framing pattern clocked in on the
TXDL input.

Frame # Ft Fs Signalling

11
20
30
40
51
61A
70
81

91
10 1
11 0
12 0 B

Table 7 - D4 Superframe Structure(T1)

Frame # FPS FDL CRC Signalling

1X
2 CB1
3X
40
5X
6 CB2 A
7X
80

9X
10 CB3
11 X
12 1 B
13 X
14 CB4
15 X
16 0
17 X
18 CB5 C
19 X
20 1
21 X
22 CB6
23 X
24 1 D

Table 8 - ESF Superframe Structure (T1)

15

MT9074 Advance Information

Frame # Ft Fs Notes Frame # Ft Fs Notes Frame # Ft Fs Notes

1 1 25 1 C 49 1
2 0 R 26 X o 50 S S = Spoiler Bits
30 e270 n510
40s28Xc52S
51 y291 e531
6 0 n 30 X n 54 C C = Maintenance Field Bits
70 c310 t550
81h32Xr56C

91 r331 a571
10 1 o 34 X t 58 C
11 0 n 35 0 o 59 0
12 1 i 36 X r 60 A A = Alarm Field Bits
13 1 z 37 1 61 1
14 0 a 38 X F 62 A
15 0 t 39 0 i 63 0
16 0 i 40 X e 64 L L = Line Switch Field Bits
17 1 o 41 1 l 65 1
18 0 n 42 X d 66 L
19 0 43 0 67 0
20 1 d 44 X B 68 L
21 1 a 45 1 i 69 1
22 1 t 46 X t 70 L
23 0 a 47 0 s 71 0
24 1 48 S 72 S S = Spoiler Bits

Table 9 - SLC-96 Framing Structure(T1)

E1 Digital Interface

PCM 30 (E1) basic frames are 256 bits long and are
transmitted at a frame repetition rate of 8000 Hz,
which results in an aggregate bit rate of 256 bits x
8000/sec = 2.048 Mbits/sec. The actual bit rate is

2.048 Mbits/sec +/-50 ppm encoded in HDB3 format.
The HDB3 control bit (page 01H, address 15H, bit 5)
selects either HDB3 encoding or alternate mark
inversion (AMI) encoding. Basic frames are divided
into 32 time slots numbered 0 to 31, see Figure 34.
Each time slot is 8 bits in length and is transmitted
most significant bit first (numbered bit 1). This results
in a single time slot data rate of 8 bits x 8000/sec. =
64 kbits/sec.

It should be noted that the Mitel ST-BUS also has 32
channels numbered 0 to 31, but the most significant
bit of an eight bit channel is numbered bit 7 (see
Mitel Application Note MSAN-126). Therefore, ST­BUS bit 7 is synonymous with PCM 30 bit 1; bit 6
with bit 2: and so on (Figure 34).

PCM 30 time slot 0 is reserved for basic frame
alignment, CRC-4 multiframe alignment and the
communication of maintenance information. In most
configurations time slot 16 is reserved for either
Channel Associated Signalling (CAS or ABCD bit
signalling) or Common Channel Signalling (CCS).
The remaining 30 time slots are called channels and
carry either PCM encoded voice signals or digital
data. Channel alignment and bit numbering is
consistent with time slot alignment and bit
numbering. However, channels are numbered 1 to 30
and relate to time slots as per Table 10.

PCM 30
Timeslots

Voice/Data
Channels
(DSTi/o
and
CSTi/o)

Table 10 - STBUS vs. PCM-30 to Channel

0 1,2,3...15 16 17,18,19,... 31

0 1,2,3...15 16 17,18,19,... 31

Relationship(E1)

16

Advance Information MT9074

a

Basic Frame Alignment

PCM 30 Channel Zero

12345678

01ASa4Sa5Sa6Sa7S

01ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

01ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

1ASa4Sa5Sa6Sa7S

1

1ASa4Sa5Sa6Sa7S

2

a8

a8

a8

a8

a8

a8

a8

a8

Time slot 0 of every basic frame is reserved for basic
frame alignment and contains either a Frame
Alignment Signal (FAS) or a Non-Frame Alignment
Signal (NFAS). FAS and NFAS occur in time slot zero
of consecutive basic frames as shown in Table 12.
Bit two is used to distinguish between FAS (bit two =

0) and NFAS (bit two = 1).

Basic frame alignment is initiated by a search for the
bit sequence 0011011 which appears in the last
seven bit positions of the FAS, see the Frame
Algorithm section. Bit position one of the FAS can be
either a CRC-4 remainder bit or an international
usage bit.

Bits four to eight of the NFAS (i.e., Sa4 - Sa8) are
additional spare bits which may be used as follows:

•Sa4 to Sa8 may be used in specific point-to-point
applications (e.g. transcoder equipments
conforming to G.761).

•Sa4 may be used as a message-based data link
for operations, maintenance and performance
monitoring.

•Sa5to Sa8 are for national usage.

CRC

CRC

Frame/

Type

0/FAS C10011011
1/NFAS
2/FAS C20011011
3/NFAS
4/FAS C30011011
5/NFAS

Sub Multi Frame 1

6/FAS C40011011
7/NFAS
8/FAS C10011011
9/NFAS
10/FAS C20011011
11/NFAS
12/FAS C30011011
13/NFAS E

Sub Multi Frame 2

14/FAS C40011011
15/NFAS E

Table 11 - FAS and NFAS Structure

A maintenance channel or data link at 4,8,12,16,or
20 kHz for selected Sa bits is provided by the
MT9074 in E1 mode to implement these functions.
Note that for simplicity all Sa bits including Sa4 are
collectively called national bits throughout this
document.

Bit three (designated as “A”), the Remote Alarm
Indication (RAI), is used to indicate the near end
basic frame synchronization status to the far end of a
link. Under normal operation, the A (RAI) bit should
be set to 0, while in alarm condition, it is set to 1.

Bit position one of the NFAS can be either a CRC-4
multiframe alignment signal, an E-bit or an
international usage bit. Refer to an approvals
laboratory and national standards bodies for specific
requirements.

indicates position of CRC-4 multiframe alignment sign

CRC-4 Multiframing in E1 mode

The primary purpose for CRC-4 multiframing is to
provide a verification of the current basic frame
alignment, although it can also be used for other
functions such as bit error rate estimation. The CRC­4 multiframe consists of 16 basic frames numbered 0
to 15, and has a repetition rate of 16 frames X 125
microseconds/frame = 2 msec.

CRC-4 multiframe alignment is based on the 001011
bit sequence, which appears in bit position one of the
first six NFASs of a CRC-4 multiframe.

The CRC-4 multiframe is divided into two
submultiframes, numbered 1 and 2, which are each
eight basic frames or 2048 bits in length.

The CRC-4 frame alignment verification functions as
follows. Initially, the CRC-4 operation must be
activated and CRC-4 multiframe alignment must be
achieved at both ends of the link. At the local end of
a link, all the bits of every transmit submultiframe are
passed through a CRC-4 polynomial (multiplied by
X4 then divided by X4 + X + 1), which generates a
four bit remainder. This remainder is inserted in bit

17

MT9074 Advance Information

position one of the four FASs of the following
submultiframe before it is transmitted (see Table 12).

The submultiframe is then transmitted and, at the far
end, the same process occurs. That is, a CRC-4
remainder is generated for each received
submultiframe. These bits are compared with the bits
received in position one of the four FASs of the next
received submultiframe. This process takes place in
both directions of transmission.

When more than 914 CRC-4 errors (out of a possible

1000) are counted in a one second interval, the
framing algorithm will force a search for a new basic
frame alignment. See Frame Algorithm section for
more details.

The result of the comparison of the received CRC-4
remainder with the locally generated remainder will
be transported to the far end by the E-bits.
Therefore, if E1 = 0, a CRC-4 error was disco vered in
a submultiframe 1 received at the far end; and if E2 =
0, a CRC-4 error was discovered in a submultiframe
2 received at the far end. No submultiframe
sequence numbers or re-transmission capabilities
are supported with layer 1 PCM 30 protocol. See
ITU-T G.704 and G.706 for more details on the
operation of CRC-4 and E-bits.

There are two CRC multiframe alignment algorithm
options selected by the AUTC control bit (address
10H, page 01H). When AUTC is zero, automatic
CRC-to-non-CRC interworking is selected. When
AUTC is one and ARAI is low, if CRC-4 multiframe
alignment is not found in 400 msec, the transmit RAI
will be continuously high until CRC-4 multiframe
alignment is achieved.

The control bit for transmit E bits (TE, address 11H
of page 01H) will have the same function in both
states of AUTC. That is, when CRC-4
synchronization is not achieved the state of the
transmit E-bits will be the same as the state of the
TE control bit. When CRC-4 synchronization is
achieved the transmit E-bits will function as per ITU­T G.704. Table 12 outlines the operation of the
AUTC, ARAI and TALM control bits of the MT9074.

CAS Signalling Multiframing in E1 mode

The purpose of the signalling multiframing algorithm
is to provide a scheme that will allow the association
of a specific ABCD signalling nibble with the
appropriate PCM 30 channel. Time slot 16 is
reserved for the communication of Channel
Associated Signalling (CAS) information (i.e., ABCD
signalling bits for up to 30 channels). Refer to ITU-T

AUTC ARAI TALM Description

0 0 X Automatic CRC-interworking is activated. If no valid CRC MFAS is being

received, transmit RAI will flick er high with e very reframe (8msec.), this cycle
will continue for 400 msec., then transmit RAI will be low continuously. The
device will stop searching for CRC MFAS, continue to transmit CRC-4
remainders, stop CRC-4 processing, indicate CRC-to-non-CRC operation
and transmit E-bits to be the same state as the TE control bit (page 01H,

address 16H).
0 1 0 Automatic CRC-interworking is activated. Transmit RAI is low continuously.
0 1 1 Automatic CRC-interworking is activated. Transmit RAI is high continuously.
1 0 X Automatic CRC-interworking is de-activated. If no valid CRC MFAS is being

received, transmit RAI flickers high with every reframe (8 msec.), this cycle

continues for 400 msec, then transmit RAI becomes high continuously. The

device continues to search for CRC MFAS and transmit E-bits are the same

state as the TE control bit. When CRCSYN = 0, the CRC MFAS search is

terminated and the transmit RAI goes low.
1 1 0 Automatic CRC-interworking is de-activated. Transmit RAI is low

continuously.
1 1 1 Automatic CRC-interworking is de-activated. Transmit RAI is high

continuously.

18

Table 12 - Operation of AUTC, ARAI and TALM Control Bits (E1 Mode)

Advance Information MT9074

G.704 and G.732 for more details on CAS
multiframing requirements.

A CAS signalling multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a
multiframe repetition rate of 2 msec. It should be
noted that the boundaries of the signalling
multiframe may be completely distinct from those of
the CRC-4 multiframe. CAS multiframe alignment is
based on a multiframe alignment signal (a 0000 bit
sequence), which occurs in the most significant
nibble of time slot 16 of basic frame 0 of the CAS
multiframe. Bit 6 of this time slot is the multiframe
alarm bit (usually designated Y). When CAS
multiframing is acquired on the receive side, the
transmit Y-bit is zero; when CAS multiframing is not
acquired, the transmit Y-bit is one. Bits 5, 7 and 8
(usually designated X) are spare bits and are
normally set to one if not used.

Time slot 16 of the remaining 15 basic frames of the
CAS multiframe (i.e., basic frames 1 to 15) are
reserved for the ABCD signalling bits for the 30
payload channels. The most significant nibbles are
reserved for channels 1 to 15 and the least
significant nibbles are reserved for channels 16 to

30. That is, time slot 16 of basic frame 1 has ABCD
for channel 1 and 16, time slot 16 of basic frame 2
has ABCD for channel 2 and 17, through to time slot
16 of basic frame 15 has ABCD for channel 15 and

30.

MT9074 Access and Control

The Control Port Interface

The control and status of the MT9074 is achieved
through a non-multiplexed parallel microprocessor
port. The parallel port may be configured for
Motorola style control signals (by setting pin INT/
MOT low) or Intel style control signals (by setting pin
INT/MOT high).

Control and Status Register Access

The controlling microprocessor gains access to
specific registers of the MT9074 through a two step
process. First, writing to the Command/Address
Register (CAR) selects one of the 15 pages of
control and status registers (CAR address: AC4 = 0,
AC3-AC0 = don't care, CAR data D7 - D0 = page
number). Second, each page has a maximum of 16
registers that are addressed on a read or write to a
non-CAR address (non-CAR: address AC4 = 1, AC3­AC0 = register address, D7-D0 = data). Once a page
of memory is selected, it is only necessary to write to
the CAR when a different page is to be accessed.
See the AC Electrical Characteristics section.

Please note that for microprocessors with read/write
cycles less than 200 ns, a wait state or a dummy
operation (for C programming) between two

Page Address

D7 - D

0

00000001 (01H) Master
00000010 (02H) R/W
00000011 (03H) Master
00000100 (04H) R/W
00000101 (05H) Per Channel Transmit Signalling R/W CSTi
00000110 (06H) Per Channel Transmit Signalling R/W CSTi
00000111 (07H) Per Time Slot Control - - ­00001000 (08H) Per Time Slot Control R/W - - ­00001001 (09H) Per Channel Receive Signalling R/W CSTo
00001010 (0AH) Per Channel Receive Signalling R/W CSTo
00001011 (0BH) HDLC0 Control and Status R/W --­00001011 (0CH) HDLC1 Control and Status R/W ---

Control

Status

Register Description

Table 13 - Page Summary

Processor

Access

R/W

R

ST-BUS

Access

- - -

- - -

19

MT9074 Advance Information

successive read/write operations to the HDLC FIFO
is required.

Table 13 associates the MT9074 control and status
pages with access and page descriptions.

Identification Code

The MT9074 shall be identified by the code
10101111, read from the identification code status
register (page 03H, address 1FH).

ST-BUS Streams

In T1 mode, there is one control and one status ST­BUS stream that can be used to program / access
channel associated signalling nibbles. CSTo contains
the received channel associated signalling bits, and
for those channels whose Per Time Slot Control word
bit 1 "RPSIG" is set low, CSTi is used to control the
transmit channel associated signalling. The DSTi
and DSTo streams contain the transmit and receive
voice and digital data. Only 24 of the 32 ST-BUS
channels are used for each of DSTi, DSTo, CSTi and
CSTo. In each case individual channel mapping is as
illustrated in Table , “Table 6 - STBUS vs. DS1 to
Channel Relationship(T1),” on page 14.

In E1 mode, the ST-BUS stream can also be used to
access channel associated signalling nibbles. CSTo
contains the received channel associated signalling
bits (e.g., ITU-T R1 and R2 signalling),and for those
channels whose Per Time Slot Control word bit 1
"RPSIG" is set low, CSTi is used to control the
transmit channel associated signalling. The DSTi
and DSTo streams contain the transmit and receive
voice and digital data.

Only 30 of the 32 ST-BUS channels are used for
each of DSTi, DSTo, CSTi and CSTo. In each case
individual channel mapping is as illustrated in Table
10 Time slot to Channel Relationship.

Reset Operation (Initialization)

The MT9074 can be reset using the hardware
RESET pin (see pin description for external reset
circuit requirements) for T1 and (pin 11 in PLCC, pin
84 in MQFP) or the software reset bit RST (page 1H,
address 1AH) for E1/T1. When the device emerges
from its reset state it will begin to function with the
default settings described in Table 14 (T1) and Table
15 (E1), all control registers default to 00H. A reset
operation takes 1 full frame (125 us) to complete.

Function Status

Mode D4

Loopbacks Deactivated

SLC-96 Deactivated

Zero Coding Deactivated

Line Codes Deactivated

Data Link Serial Mode

Signalling CAS Registers

AB/ABCD Bit

Debounce

Interrupts masked

Error Insertion Deactivated

HDLC0,1 Deactivated
Counters Cleared

Transmit Data All Ones

Table 14 - Reset Status(T1)

Function Status

Mode Termination

Loopbacks Deactivated

Transmit FAS Cn0011011

Transmit non-FAS 1/Sn1111111

Transmit MFAS (CAS) 00001111

Data Link Deactivated

CRC Interworking Activated

Signalling CAS Registers

ABCD Bit Debounce Deactivated

Interrupts Masked

RxMF Output Signalling Multiframe

Error Insertion Deactivated

HDLCs Deactivated

Counters Cleared

Transmit Data All Ones

Table 15 - Reset Status(E1)

Deactivated

Transmit Data All Ones (TxAO)
Operation

The TxAO (Transmit all ones) pin allows the PRI
interface to transmit an all ones signal from the point
of power-up without writing to any control registers.
During this time the IRQ pin is tristated. After the
interface has been initialized normal operation can
take place by making TxAO high.

20

Advance Information MT9074

Data Link Operation

Data Link Operation in E1 mode

In E1 mode MT9074 has a user defined 4, 8, 12, 16
or 20 kbit/s data link for transport of maintenance
and performance monitoring information across the
PCM 30 link. This channel functions using the Sa bits
(Sa4~Sa8) of the PCM 30 timeslot zero non-frame
alignment signal (NFAS). Since the NFAS is
transmitted every other frame - a periodicity of 250
microseconds - the aggregate bit rate is a multiple of
4 kb/s. As there are five Sa bits independently
available for this data link, the bit rate will be 4, 8, 12,
16 or 20 kb/s, depending on the bits selected for the
Data Link (DL).

The Sa bits used for the DL are selected by setting
the appropriate bits, Sa4~Sa8, to one in the Data Link
Select Word (page 01H, address 17H, bits 4-0).
Access to the DL is provided by pins TxDLCLK,
TxDL, RxDLCLK and RxDL, which allow easy
interfacing to an external controller.

Data Link Operation in T1 mode

SLC-96 and ESF protocol allow for carrier messages
to be embedded in the overhead bit position. The
MT9074 provides 3 separate means of controlling
these data links. See Data Link and Rx Equalization
Control Word - address 12H, page 1H.

• The data links (transmit and receive) may be
sourced (sunk) from an external controller using
dedicated pins on the MT9074 in T1 mode (enabled
by setting the bit 7 - EDL of the Data link Control
Word).

• Bit - Oriented Messages may be transmit and
received via a dedicated TxBOM register (page 1H,
address 13H) and a RxBOM (page 3H, address
15H). Transmission is enabled by setting bit 6 ­BIOMEn in the Data link Control Word. Bit - oriented
messages may be periodically interrupted (up to
once per second) for a duration of up to 100
milliseconds. This is to accommodate bursts of
message - oriented protocols. See Table 16 for
message structure.

Data to be transmit onto the line in the Sa bit position
is clocked in from the TxDL pad (pin 65 in PLCC, pin
62 in MQFP) with the clock TxDLCLK (pin 64 in
PLCC, pin 61 in MQFP). Although the aggregate
clock rate equals the bit rate, it has a nominal pulse
width of 244 ns, and it clocks in the TxDL as if it were
a 2.048 Mb/s data stream. The clock can only be
active during bit times 4 to 0 of the STBUS frame.
The TxDL input signal is clocked into the MT9074 by
the rising edge of TxDLCLK. If bits are selected to be
a part of the DL, all other programmed functions for
those Sa bit positions are overridden.

The RxDLCLK signal (pin 39 in PLCC, pin 20 in
MQFP) is derived from the receive extracted clock
and is aligned with the receive data link output RxDL.
The HDB3 decoded receive data, at 2.048 Mbit/s, is
clocked out of the device on pin RxDL (pin 40 in
PLCC, pin 21 in MQFP). In order to facilitate the
attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of
positive pulses, of nominal width of 244 ns, during
the Sa bit cell times that are selected for the data
link. Again, this selection is made by programming
address 17H of master control page 01H. No DL
data will be lost or repeated when a receive frame
slip occurs. See the AC Electrical Characteristics for
timing requirements.

• An internal HDLC controller may be attached to the
data link.

External Data Link

In T1 mode MT9074 has two pairs of pins (TxDL and
TxDLCLK, RxDL and RxDLCLK) dedicated to
transmitting and receiving bits in the selected
overhead bit positions. Pins TxDLCLK and RxDLCLK
are clock outputs available for clocking data into the
MT9074 (for transmit) or exter nal device (for receive
information). Each clock operates at 4 Khz. In the
SLC-96 mode the optional serial data link is
multiplexed into the Fs bit position. In the ESF mode
the serial data link is multiplexed into odd frames, i.e.
the FDL bit positions.

Bit - Oriented Messaging

In T1 mode MT9074 Bit oriented messaging may be
selected by setting bit 6 (BIOMEn) in the Data Link
Control Word (page 1H, address 12H). The transmit
data link will contain the repeating serial data stream
111111110xxxxxx0 where the byte 0xxxxxx0
originates from the user programmed register
"Transmit Bit Oriented Message" - page 1H address
13H. The receive BIOM register "Receive Bit
Oriented Message" - page 3H, address 15H, will
contain the last received valid message (the
0xxxxxx0 portion of the incoming serial bit stream).
To prevent spurious inputs from creating false

21

MT9074 Advance Information

Octet # 8 7 6 54321Content

1 F L A G 01111110
2 S A P I C / R EA 00111000 or

00111010
3 T E I EA 00000001
4 C O N T R O L 00000011
5 G3LVG4U1U2G5SLG6t0
6FESELBG1RG2NmNIt0
7 G3LVG4U1U2G5SLG6t0-1
8FESELBG1RG2NmNIt0-1
9 G3LVG4U1U2G5SLG6t0-2

10 FE SE LB G1 R G2 Nm NI t0-2
11 G3 LV G4 U1 U2 G5 SL G6 t0-3
12 FE SE LB G1 R G2 Nm NI t0-3
13 F C S VARIABLE
14

Table 16 - Message Oriented Performance Report Structure (T1.403 and T1.408)

Note: ADDRESS INTERPRETATION

00111000 SAPI = 14, C/R = 0 (CI) EA = 0

00111010 SAPI = 14, C/R = 1(Carrier) EA = 0
00000001 TEI = 0, EA =1

CONTROL INTERPRETATION

00000011 Unacknowledged Information Transfer

ONE SECOND REPORT INTERPRETATION

G1 = 1 CRC Error Event =1

G2 =1 1 < CRC Error Event < 5
G3 =1 5 < CRC Error Event < 10
G4 =1 10 < CRC Error Event < 100
G5 =1 100 < CRC Error Event < 319
G6 =1 CRC Error Event > 320
SE = 1 Severely - Errored Framing Event >=1
FE = 1 Frame Synchronization Bit Error Event >=1
LV = 1 Line code Violation Event >=1
SL = 1 Slip Event >=1
LB = 1 Payload Loopback Activated
U1,U2 = 0 Under Study for sync.
R = 0 Reserved - set to 0
NmNI = 00, 01, 10, 11 One Second Module 4 counter

FCS INTERPRETATION

VARIABLE CRC16 Frame Check Sequence

22

Advance Information MT9074

messages, a new message must be present in 7 of
the last 10 appropriate byte positions before being
loaded into the receive BIOM register. When a new
message has been received, a maskable interrupt
(maskable by setting bit 1 low in Interrupt Mask Word
Three - page 1H, address 1EH) may occur.

Dual HDLC

MT9074 has two embedded HDLC controllers
(HDLC0, HDLC1) each of which includes the
following features:

• Independent transmit and receive FIFO's;

• Receive FIFO maskable interrupts for nearly
full (programmable interrupt levels) and
overflow conditions;

• Transmit FIFO maskable interrupts for
nearly empty (programmable interrupt
levels) and underflow conditions;

• Maskable interrupts for transmit end-of­packet and receive end-of-packet;

• Maskable interrupts for receive bad-frame
(includes frame abort);

• Transmit end-of-packet and frame-abort
functions.

mode. It should be noted that the AIS16S function
will always be active and the TAIS16 (page 01H,
address 11h) function will override all other transmit
signalling.

HDLC1 can be selected by setting the control bit
HDLC1. When this bit is zero all interrupts from
HDLC1 are masked.

HDLC Description

The HDLC handles the bit oriented packetized data
transmission as per X.25 level two protocol defined
by ITU-T. It provides flag and abort sequence
generation and detection, zero insertion and
deletion, and Frame Check Sequence (FCS)
generation and detection. A single byte, dual byte
and all call address in the received frame can be
recognized. Access to the receive FCS and inhibiting
of transmit FCS for terminal adaptation are also
provided. Each HDLC controller has a 128 byte deep
FIFO associated with it. The status and interrupt
flags are programmable for FIFO depths that can
vary from 16 to 128 bytes in steps of 16 bytes. These
and other features are enabled through the HDLC
control registers on page 0BH and 0CH.

HLDC0 Functions

In T1 mode ESF Data Link (DL) can be connected to
internal HDLC0, operating at a bit rate of 4 kbits/sec.
HDLC0 can be activated by setting the control bit 5,
address 12H in Master Control Page 0. Interrupts
from HDLC0 are masked when it is disconnected.

In E1 mode when connected to the Data Link (DL)
HDLC0 will operate at a selected bit rate of 4, 8, 12,
16 or 20 kbits/sec. HDLC0 can be selected by setting
the control bit HDLC0 (page 01H, address 12H).
When this bit is zero all interrupts from HDLC0 are
masked. For more information refer to following
sections.

HDLC1 Functions

In T1 mode DS1 channel 24 can be connected to
HDLC1, operating at 56 or 64 Kb/s. HDLC1 can be
activated by setting the control bit HDLC1 (page
01H, address 12H). Setting control bit H1R64
(address 12 H on page 01H) high selects 64 Kb/s
operation for HDLC1. Setting this bit low selects 56
Kb/s for HDLC1. Interrupts from HDLC1 are masked
when it is disconnected.

In E1 mode this controller may be connected to time
slot 16 under Common Channel Signalling (CCS)

HDLC Frame structure

In T1 mode or E1 mode a valid HDLC frame begins
with an opening flag, contains at least 16 bits of
address and control or information, and ends with a
16 bit FCS followed by a closing flag. Data formatted
in this manner is also referred to as a “packet”. Refer
to Table 17: HDLC Frame Format

Flag (7E) Data Field FCS Flag (7E)

One Byte

01111110

Table 17 - HDLC Frame Format

All HDLC frames start and end with a unique flag
sequence “01111110”. The transmitter generates
these flags and appends them to the packet to be
transmitted. The receiver searches the incoming
data stream for the flags on a bit- by-bit basis to
establish frame synchronization.

The data field consists of an address field, control
field and information field. The address field consists
of one or two bytes directly following the opening
flag. The control field consists of one byte directly
following the address field. The information field
immediately follows the control field and consists of

n Bytes

n ≥ 2

Two

Bytes

One Byte

01111110

23

MT9074 Advance Information

N bytes of data. The HDLC does not distinguish
between the control and information fields and a
packet does not need to contain an infor mation field
to be valid.

The FCS field, which precedes the closing flag,
consists of two bytes. A cyclic redundancy check
utilizing the CRC-CCITT standard generator
polynomial “X16+X12+X5+1” produces the 16-bit
FCS. In the transmitter the FCS is calculated on all
bits of the address and data field. The complement
of the FCS is transmitted, most significant bit first, in
the FCS field. The receiver calculates the FCS on
the incoming packet address, data and FCS field and
compares the result to “F0B8”. If no transmission
errors are detected and the packet between the flags
is at least 32 bits in length then the address and data
are entered into the receive FIFO minus the FCS
which is discarded.

Data Transparency (Zero Insertion/Deletion)

Transparency ensures that the contents of a data
packet do not imitate a flag, go-ahead, frame abort
or idle channel. The contents of a transmitted frame,
between the flags, is examined on a bit-by-bit basis
and a 0 bit is inserted after all sequences of 5
contiguous 1 bits (including the last five bits of the
FCS). Upon receiving five contiguous 1s within a
frame the receiver deletes the following 0 bit.

Invalid Frames

Frame Abort

The transmitter will abort a current packet by
substituting a zero followed by seven contiguous 1s
in place of the normal packet. The receiver will abort
upon reception of seven contiguous 1s occurring
between the flags of a packet which contains at least
26 bits.

Note that should the last received byte before the
frame abort end with contiguous 1s, these are
included in the seven 1s required for a receiver
abort. This means that the location of the abort
sequence in the receiver may occur before the
location of the abort sequence in the originally
transmitted packet. If this happens then the last data
written to the receive FIFO will not correspond
exactly with the last byte sent before the frame abort.

Interframe Time Fill and Link Channel States

When the HDLC transmitter is not sending packets it
will wait in one of two states

• Interframe Time Fill state: This is a
continuous series of flags occurring between
frames indicating that the channel is active
but that no data is being sent.

• Idle state: An idle Channel occurs when at
least 15 contiguous 1s are transmitted or
received.

In both states the transmitter will exit the wait state
when data is loaded into the transmitter FIFO.

A frame is invalid if one of the following four
conditions exists (Inserted zeros are not part of a
valid count):

• If the FCS pattern generated from the
received data does not match the “F0B8”
pattern then the last data byte of the packet
is written to the received FIFO with a ‘bad
packet’ indication.

• A short frame exists if there are less than 25
bits between the flags. Short frames are
ignored by the receiver and nothing is written
to the receive FIFO.

• Packets which are at least 25 bits in length
but less than 32 bits between the flags are
also invalid. In this case the data is written to
the FIFO but the last byte is tagged with a
“bad packet” indication.

• If a frame abort sequence is detected the
packet is invalid. Some or all of the current
packet will reside in the receive FIFO,
assuming the packet length before the abort
sequence was at least 26 bits long.

Go-Ahead

A go ahead is defined as the pattern "011111110"
(contiguous 7Fs) and is the occurrence of a frame
abort sequence followed by a zero, outside of the
boundaries of a normal packet. Being able to
distinguish a proper (in packet) frame abort
sequence from one occurring outside of a packet
allows a higher level of signalling protocol which is
not part of the HDLC specifications.

HDLC Functional Description

The HDLC transceiver can be reset by either the
power reset input signal or by the HRST Control bit
in the test control register (software reset). When
reset, the HDLC Control Registers are cleared,
resulting in the transmitter and receiver being
disabled. The Receiver and Transmitter can be
enabled independent of one another through Control
Register 1. The transceiver input and output are
enabled when the enable control bits in Control
Register 1 are set. Transmit to receive loopback as

24

Advance Information MT9074

well as a receive to transmit loopback are also
supported. Transmit and receive bit rates and
enables can operate independently. In MT9074 the
transceiver can operate at a continuous rate
independent of RXcen and TXcen (free run mode) by
setting the Frun bit of Control Register 1.

Received packets from the serial interface are
sectioned into bytes by an HDLC receiver that
detects flags, checks for go-ahead signals, removes
inserted zeros, performs a cyclical redundancy
check (CRC) on incoming data, and monitors the
address if required. Packet reception begins upon
detection of an opening flag. The resulting bytes are
concatenated with two status bits (RQ9, RQ8) and
placed in a receiver first-in-first-out (Rx FIFO); a
buffer register that generates status and interrupts
for microprocessor read control.

In conjunction with the control circuitry, the
microprocessor writes data bytes into a Tx buffer
register (Tx FIFO) that generates status and
interrupts. Packet transmission begins when the
microprocessor writes a byte to the Tx FIFO. Two
status bits are added to the Tx FIFO for transmitter
control of frame aborts (FA) and end of packet (EOP)
flags. Packets have flags appended, zeros inserted,
and a CRC, also referred to as frame checking
sequence (FCS), added automatically during serial
transmission. When the Tx FIFO is empty and
finished sending a packet, Interframe Time Fill bytes
(continuous flags (7E hex)), or Mark Idle (continuous
ones) are transmitted to indicate that the channel is
idle.

HDLC Transmitter

Following initialization and enabling, the transmitter
is in the Idle Channel state (Mark Idle), continuously
sending ones. Interframe Time Fill state (Flag Idle) is
selected by setting the Mark idle bit in Control
Register 1 high. The Transmitter remains in either of
these two states until data is written to the Tx FIFO.
Control Register 1 bits EOP (end of packet) and FA
(Frame Abort) are set as status bits before the
microprocessor loads 8 bits of data into the 10 bit
wide FIFO (8 bits data and 2 bits status). To change
the tag bits being loaded in the FIFO, Control
Register 1 must be written to before writing to the
FIFO. However, EOP and FA are reset after writing to
the TX FIFO. The Transmit Byte Count Register may
also be used to tag an end of packet. The register is
loaded with the number of bytes in the packet and
decrements after every write to the Tx FIFO. When a
count of one is reached, the next byte written to the
FIFO is tagged as an end of packet. The register
may be made to cycle through the same count if the

packets are of the same length by setting Control
Register 2 bit Cycle.

If the transmitter is in the Idle Channel state when
data is written to the Tx FIFO, then an opening flag is
sent and data from Tx FIFO follows. Otherwise, data
bytes are transmitted as soon as the current flag byte
has been sent. Tx FIFO data bytes are continuously
transmitted until either the FIFO is empty or an EOP
or FA status bit is read by the transmitter. After the
last bit of the EOP byte has been transmitted, a 16­bit FCS is sent followed by a closing flag. When
multiple packets of data are loaded into Tx FIFO,
only one flag is sent between packets.

Frame aborts (the transmission of 7F hex), are
transmitted by tagging a byte previously written to
the Tx FIFO. When a byte has an FA tag, then an FA
is sent instead of that tagged byte. That is, all bytes
previous to but not including that byte are sent. After
a Frame Abort, the transmitter returns to the Mark
Idle or Interframe Time Fill state, depending on the
state of the Mark idle control bit.

Tx FIFO underrun will occur if the FIFO empties and
the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun
occurs.

Below is an example of the transmission of a three
byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill).
TXcen can be enabled before or after this sequence.

(a) Write ’04’hex to Control Register 1

-Mark idle bit set

(b) Write ’AA’ hex to TX FIFO

-Data byte

(c) Write ’03’hex to TX FIFO

-Data byte

(d) Write ’34’hex to Control Register 1

-TXEN; EOP; Mark idle bits set

(e) Write ’77’hex to TX FIFO

-Final data byte

The transmitter may be enabled independently of the
receiver. This is done by setting the TXEN bit of the
Control Register. Enabling happens immediately
upon writing to the register. Disabling using TXen will
occur after the completion of the transmission of the
present packet; the contents of the FIFO are not
cleared. Disabling will consist of stopping the
transmitter clock. The Status and Interrupt Registers
may still be read and the FIFO and Control Registers
may be written to while the transmitter is disabled.
The transmitted FCS may be inhibited using the Tcrci
bit of Control Register 2. In this mode the opening

25

MT9074 Advance Information

flag followed by the data and closing flag is sent and
zero insertion still included, but no CRC. That is, the
FCS is injected by the microprocessor as part of the
data field. This is used in V.120 terminal adaptation
for synchronous protocol sensitive UI frames.

HDLC Receiver

After initialization and enabling, the receiver clocks in
serial data, continuously checking for Go-aheads (0
1111 1110), flags (0111 1110), and Idle Channel
states (at least fifteen ones). When a flag is
detected, the receiver synchronizes itself to the
serial stream of data bits, automatically calculating
the FCS. If the data length between flags after zero
removal is less than 25 bits, then the packet is
ignored so no bytes are loaded into Rx FIFO. When
the data length after zero removal is between 25 and
31 bits, a first byte and bad FCS code are loaded into
the Rx FIFO (see definition of RQ8 and RQ9 below).
For an error-free packet, the result in the CRC
register should match the HEX pattern of ’F0B8’
when a closing flag is detected.

If address recognition is required, the Receiver
Address Recognition Registers are loaded with the
desired address and the Adrec bit in the Control
Register 1 is set high. Bit 0 of the Address Registers
is used as an enable bit for that byte, thus allowing
either or both of the first two bytes to be compared to
the expected values. Bit 0 of the first byte of the
address received (address extension bit) will be
monitored to determine if a single or dual byte
address is being received. If this bit is 0 then a two
byte address is being received and then only the first
six bits of the first address byte are compared. An all
call condition is also monitored for the second
address byte; and if received the first address byte is
ignored (not compared with mask byte). If the
address extension bit is a 1 then a single byte
address is being received. In this case, an all call
condition is monitored for in the first byte as well as
the mask byte written to the comparison register and
the second byte is ignored. Seven bits of address
comparison can be realized on the first byte if this is
a single byte address by setting the Seven bit of
Control Register 2.

The following two Status Register bits (RQ8 and
RQ9) are appended to each data byte as it is written
to the Rx FIFO. They indicate that a good packet has
been received (good FCS and no frame abort), or a
bad packet with either incorrect FCS or frame abort.
The Status and Interrupt Registers should be read
before reading the Rx FIFO since status and
interrupt information correspond to the byte at the
output of the FIFO (i.e. the byte about to be read).
The Status Register bits are encoded as follows:

RQ9 RQ8 Byte status
1 1 last byte (bad packet)
0 1 first byte
1 0 last b yte (good packet)
0 0 packet byte

The end-of-packet-detect (EOPD) interrupt indicates
that the last byte written to the Rx FIFO was an EOP
byte (last byte in a packet). The end-of-packet-read
(EopR) interrupt indicates that the byte about to be
read from the Rx FIFO is an EOP byte (last byte in a
packet). The Status Register should be read to see if
the packet is good or bad before the byte is read.

A minimum size packet has an 8-bit address, an 8-bit
control byte, and a 16-bit FCS pattern between the
opening and closing flags (see Section 9.3.2). Thus,
the absence of a data transmission error and a frame
length of at least 32 bits results in the receiver
writing a valid packet code with the EOP byte into Rx
FIFO. The last 16 bits before the closing flag are
regarded as the FCS pattern and will not be
transferred to the receiver FIFO. Only data bytes
(Address, Control, Information) are loaded into the
Rx FIFO.

In the case of an Rx FIFO overflow, no clocking
occurs until a new opening flag is received. In other
words, the remainder of the packet is not clocked into
the FIFO. Also, the top byte of the FIFO will not be
written over. If the FIFO is read before the reception
of the next packet then reception of that packet will
occur. If two beginning of packet conditions
(RQ9=0;RQ8=1) are seen in the FIFO, without an
intermediate EOP status, then overflow occurred for
the first packet.

The receiver may be enabled independently of the
transmitter. This is done by setting the RXEN bit of
Control Register 1. Enabling happens immediately
upon writing to the register. Disabling using RXEN
will occur after the present packet has been
completely loaded into the FIFO. Disabling can occur
during a packet if no bytes have been written to the
FIFO yet. Disabling will consist of disabling the
internal receive clock. The FIFO, Status, and
Interrupt Registers may still be read while the
receiver is disabled. Note that the receiver requires a
flag before processing a frame, thus if the receiver is
enabled in the middle of an incoming packet it will
ignore that packet and wait for the next complete
one.

The receive CRC can be monitored in the Rx CRC
Registers. These registers contain the actual CRC
sent by the other transmitter in its original form; that
is, MSB first and bits inverted. These registers are

26

Advance Information MT9074

updated by each end of packet (closing flag)
received and therefore should be read when an end
of packet is receiv ed so that the next packet does not
overwrite the registers.

Slip Buffers

Slip Buffer in T1 mode

In T1 mode MT9074 contains two sets of slip buffers,
one on the transmit side, and one on the receive
side. Both sides may perform a controlled slip. The
mechanisms that govern the slip function are a
function of backplane timing and the mapping
between the ST-BUS channels and the DS1
channels. The slip mechanisms are different for the
transmit and receive slip buffers. The extracted 1.544
Mhz clock (E1.5o) and the internally generated
transmit 1.544 Mhz clock are distinct. Slips on the
transmit side are independent from slips on the
receive side.

The transmit slip buffer has data written to it from the
near end 2.048 Mb/s stream. The data is clocked out
of the buffer using signals derived from the transmit

1.544 Mhz clock. The transmit 1.544 Mhz clock is
always phase locked to the DSTi 2.048 Mb/s stream.
If the system 4.096 Mhz clock (C4b) is internally
generated (pin BS/LS low), then it is hard locked to

the 1.544 Mhz clock. No phase drift or wander can
exist between the two signals - therefore no slips will
occur. The delay through the transmit elastic buffer is
then fixed, and is a functions of the relative mapping
between the DSTi channels and the DS1 timeslots.
These delays vary with the position of the channel in
the frame. For example, DS1 timeslot 1 sits in the
elastic buffer for approximately 1 usec and DS1
timeslot 24 sits in the elastic buffer for approximately
32 usec.

If the system 4.096 Mhz clock (C4b) is externally
generated (pin BS/LS high), the transmit 1.544 Mhz
clock is phase locked to it, but the PLL is designed to
filter jitter present in the C4b clock. As a result phase
drift will result between the two signals. The delay
through the transmit elastic buffer will vary in
accordance with the input clock drift, as well as being
a function of the relative mapping between the DSTi
channels and the DS1 timeslots. If the read pointers
approach the write pointers (to within approximately
1 usec) or the delay through the transmit buffer
exceeds 218 usecs a controlled slip will occur. The
contents of a single frame of DS1 data will be
skipped or repeated; a maskable interrupt (masked
by setting bit 1 - TxSLPI high in Interrupt Mask Word
Zero - page 1H, address 1bH) will be generated, and
the status bit TSLIP (page 3H, address 17H) of MSB
Transmit Slip Buffer register will toggle. The direction
of the slip is indicated by bit 6 of the same register

0 uS

Write

Pointer

Read Pointer

221 uS

512 Bit

188 uS

Read Vectors
Minimum Delay

Write Vectors

Read Vectors - Maximum Delay

Elastic

Store

129 uS

Read Pointer

4 uS

Frame 0 Frame 1

Read Pointer

92 uS

Wander Tolerance

62 uS

92 uS

96 uS

Read Pointer

Frame 0 Frame 1

Frame 0 Frame 1

Figure 12 - Read and write pointers in the transmit slip buffers

27

MT9074 Advance Information

(TSLPD). The relative phase delay between the
system frame boundary and the transmit elastic
frame read boundary is measured every frame and
reported in the Transmit Slip Buffer Delay register­(page 3H, address 17H). In addition the relative
offset between these frame boundaries may be
programmed by writing to this register. Every write to
Transmit Elastic Buffer Set Delay Word resets the
transmit elastic frame count bit TxSBMSB (address
17H, page 3H). After a write the delay through the
slip buffer is less than 1 frame in duration. Each write
operation will result in a disturbance of the transmit
DS1 frame boundary, causing the far end to go out of
sync. Writing BC (hex) into the TxSBDLY register
maximizes the wander tolerance before a controlled
slip occurs. Under normal operation no slips should
occur in the transmit path. Slips will only occur if the
input C4b clock has excess wander, or the Transmit
Elastic Buffer Set Delay Word register is initialized
too close to the slip pointers after system
initialization.

The two frame receive elastic buffer is attached
between the 1.544 Mbit/s DS1 receive side and the

2.048 Mbit/s ST-BUS side of the MT9074. Besides
performing rate conversion, this elastic buffer is
configured as a slip buffer which absorbs wander
and low frequency jitter in multi-trunk applications.
The received DS1 data is clocked into the slip buffer
with the E1.5o clock and is clocked out of the slip
buffer with the system C4b clock. The E1.5o
extracted clock is generated from, and is therefore
phase-locked with, the receive DS1 data. In the case
of Internal mode (pin BS/LS set low) operation, the
E1.5o clock may be phase-loc k ed to theC4b clock by
an internal phase locked loop (PLL). Therefore, in a
single trunk system the receive data is in phase with
the E1.5o clock, the C4b clock is phase locked to the
E1.5o clock, and the read and write positions of the
slip buffer track each other.

tolerance). The MT9074 will allow 92 usec (140 UI,
DS1 unit intervals) of wander and low frequency jitter
before a frame slip will occur.

When the C4b and the E1.5o clocks are not phase­locked, the rate at which data is being written into the
slip buffer from the DS1 side may differ from the rate
at which it is being read out onto the ST-BUS. If this
situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full DS1 frame is either repeated or lost. All frame
slips occur on frame boundaries.

The minimum delay through the receive slip buffer is
approximately 1 usec and the maximum delay is
approximately 249 uS. Figure 13 illustrates the
relationship between the read and write pointers of
the receive slip buffer (contiguous time slot
mapping). Measuring clockwise from the write
pointer, if the read page pointer comes within 8 usec
of the write page pointer a frame slip will occur,
which will put the read page pointer 157 usec from
the write page pointer. Conversely, if the read page
pointer moves more than 249 usec from the write
page pointer, a slip will occur, which will put the read
page pointer 124 usec from the write page pointer.
This provides a worst case hysteresis of 92 usec
peak = 142 U.I.

The RSLIP and RSLPD status bits (page 3H,
address 13H, bits 7 and 6 respectively) give
indication of a receive slip occurrence and direction.
A maskable interrupt RxSLPI (page 1H, address
1BH, bit 0 - set high to mask) is also provided. RSLIP
changes state in the event of a slip. If RSLPD=0, the
slip buffer has overflowed and a frame was lost; if
RSLPD=1, an underflow condition occurred and a
frame was repeated

In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network synchronizer, which will function as
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the DS1 signals from the network are
synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the C1.50
clocks of non-synchronized trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus. Network standards state that, within
limits, trunk interfaces must be able to receive error­free data in the presence of jitter and wander (refer
to network requirements for jitter and wander

28

Slip Buffer in E1 mode

In E1 mode in addition to the elastic buffer in the jitter
attenuator(JA), another elastic buffer (two frames
deep) is present, attached between the receive side
and the ST-BUS (or GCI Bus) side of the MT9074 in
E1 mode. This elastic buffer is configured as a slip
buffer which absorbs wander and low frequency jitter
in multi-trunk applications. The received PCM 30
data is clocked into the slip buffer with the E1.5o
clock and is clocked out of the slip buffer with the
C4b clock. The E1.5o extracted clock is generated
from, and is therefore phase-locked with, the receive
PCM 30 data. In normal operation, the C4b clock will
be phase-locked to the E1.5o clock by a phase
locked loop (PLL). Therefore, in a single trunk

Advance Information MT9074

system the receive data is in phase with the E1.5o
clock, the C4b clock is phase-locked to the E1.5o
clock, and the read and write positions of the slip
buffer will remain fixed with respect to each other.

In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network synchronizer, which will function as
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the PCM 30 signals from the network
are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the E1.5o
clocks of non-synchronizer trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus.

Network standards state that, within limits, trunk
interfaces must be able to receive error-free data in
the presence of jitter and wander (refer to network
requirements for jitter and wander tolerance). The
MT9074 will allow a maximum of 26 channels (208
UI, unit intervals) of wander and low frequency jitter
before a frame slip will occur.

The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 14).

When the C4b and the E1.5o clocks are not phase­locked, the rate at which data is being written into the
slip buffer from the PCM 30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full PCM 30 frame is either repeated or lost. All
frame slips occur on PCM 30 frame boundaries.

Two status bits, RSLIP and RSLPD (page03H,
address13H) give indication of a slip occurrence and
direction. RSLIP changes state in the event of a slip.
If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, an underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.

Figure 14 illustrates the relationship between the
read and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer 34 channels from the write pointer.
Conversely, if the read pointer moves more than 60

Write

Pointer

Read Pointer

249 uS

512 Bit

188 uS

Read Pointer

Read Vectors
Minimum Delay

Write Vectors

Read Vectors - Maximum Delay

Elastic

Store

157 uS

0 uS

Read Pointer

Frame 0 Frame 1

Read Pointer

32 uS

62 uS

92 uS

124 uS

Frame 0 Frame 1

XXX XXX

92 uS

Wander Tolerance

Frame 0 Frame 1

XXX XXX

Figure 13 - Read and write pointers in the receive slip buffers

29

MT9074 Advance Information

channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 channels peak (26 channels peak-to-peak) or a
wander tolerance of 208 UI.

Framing Algorithm

Frame Alignment in T1 Mode

In T1 mode MT9074 will synchronize to DS1 lines
formatted with either the D4 or ESF protocol. In
either mode the framer maintains a running 3 bit
history of received data for each of the candidate bit
positions. Candidate bit positions whose incoming
patterns fail to match the predicted pattern (based on
the 3 bit history) are winnowed out. If, after a 10 bit
history has been examined, only one candidate bit
position remains within the framing bit period, the
receive side timebase is forced to align to that bit
position. If no candidates remain after a 10 bit
history, the process is re-initiated. If multiple
candidates exist after a 24 bit history timeout period,
the framer forces the receive side timebase to
synchronize to the next incoming valid candidate bit
position. In the event of a reframe, the framer starts
searching at the next bit position over. This prevents
persistent locking to a mimic as the controller may
initiate a software controlled reframe in the event of
locking to a mimic.

multiframer alignment is forced at the same time as
terminal frame alignment. If only Ft bits are checked,
multiframe alignment is forced separately, upon
detection of the Fs bit history of 00111 (for normal
D4 trunks) or 000111000111 (for SLC-96 trunks).
For D4 trunks, a reframe on the multiframe alignment
may be forced at any time without affecting terminal
frame alignment.

In ESF mode the circuit will optionally confirm the
CRC-6 bits before forcing a new frame alignment.
This is programmed by setting control bit CXC high
(bit 5 of the Framing Mode Select Word, page 1H,
address 10H). A CRC-6 confirmation adds a
minimum of 6 milliseconds to the reframe time. If no
CRC-6 match is found after 16 attempts, the framer
moves to the next valid candidate bit position
(assuming other bit positions contain a match to the
framing pattern) or re-initiates the whole framing
procedure (assuming no bit positions have been
found to match the framing pattern).

The framing circuit is off - line. During a reframe, the
rest of the circuit operates synchronous with the last
frame alignment. Until such time as a new frame
alignment is achieved, the signalling bits are frozen
in their states at the time that frame alignment was
lost, and error counting for Ft, Fs, ESF framing
pattern or CRC-6 bits is suspended.

Frame Alignment in E1 mode

Under software control the framing criteria may be
tuned (see Framing Mode Select Register, page 1H,
address 10H). Selecting D4 framing invites a further
decision whether or not to include a cross check of
Fs bits along with the Ft bits. If Fs bits are checked
(by setting control bit CXC high - bit 5 of the Framing
Mode Select Word, page 1H, address 10H),

Write

Read Pointer

60 CH 2 CH

512 Bit

47 CH 15 CH

Read Pointer

Elastic

Store

34 CH 28 CH

Pointer

Read Pointer

Read Pointer

In E1 mode MT9074 contains three distinct framing
algorithms: basic frame alignment, signalling
multiframe alignment and CRC-4 multiframe
alignment. Figure 17 is a state diagram that
illustrates these algorithms and how they interact.

13 CH

Wander Tolerance

26 Channels

-13 CH

30

Figure 14 - Read and Write Pointers in the Slip Buffers

Advance Information MT9074

After power-up, the basic frame alignment framer will
search for a frame alignment signal (FAS) in the
PCM 30 receive bit stream. Once the FAS is
detected, the corresponding bit 2 of the non-frame
alignment signal (NFAS) is checked. If bit 2 of the
NFAS is zero a new search for basic frame alignment
is initiated. If bit 2 of the NFAS is one and the next
FAS is correct, the algorithm declares that basic
frame synchronization has been found (i.e., page
03H, address 10H, bit 7, SYNC is zero).

Once basic frame alignment is acquired the
signalling and CRC-4 multiframe searches will be
initiated. The signalling multiframe algorithm will
align to the first multiframe alignment signal pattern
(MFAS = 0000) it receives in the most significant
nibble of channel 16 (page 3, address 10H, bit 6,
MFSYNC = 0). Signalling multiframing will be lost
when two consecutive multiframes are received in
error.

The CRC-4 multiframe alignment signal is a 001011
bit sequence that appears in PCM 30 bit position one
of the NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table

9). In order to achieved CRC-4 synchronization two
consecutive CRC-4 multiframe alignment signals
must be received without error (page 03H, address
10H CRCSYN = 0).

The E1 framing algorithm supports automatic
interworking of interfaces with and without CRC-4
processing capabilities. That is, if an interface with
CRC-4 capability, achieves valid basic frame
alignment, but does not achieve CRC-4 multiframe
alignment by the end of a predefined period, the
distant end is considered to be a non-CRC-4
interface. When the distant end is a non-CRC-4
interface, the near end automatically suspends
receive CRC-4 functions, continues to transmit CRC­4 data to the distant end with its E-bits set to zero,
and provides a status indication. Naturally, if the
distant end initially achieves CRC-4 synchronization,
CRC-4 processing will be carried out by both ends.
This feature is selected when control bit AUTC (page
01H, address 10H) is set to zero.

Notes for Synchronization State Diagram
(Figure 15)

1) The basic frame alignment, signalling multiframe
alignment, and CRC-4 multiframe alignment
functions operate in parallel and are independent.

3) Manual re-framing of the receive basic frame
alignment and signalling multiframe alignment functi-

ons can be performed at any time.

4) The transmit RAI bit will be one until basic frame
alignment is established, then it will be zero.

5) E-bits can be optionally set to zero until the
equipment interworking relationship is established.
When this has been determined one of the following
will take place:

a) CRC-to-non-CRC operation - E-bits = 0,
b) CRC-to-CRC operation - E-bits as per G.704 and

I.431.

6) All manual re-frames and new basic frame
alignment searches start after the current frame
alignment signal position.

7) After basic frame alignment has been achieved,
loss of frame alignment will occur any time three
consecutive incorrect basic frame alignment signals
are received. Loss of basic frame alignment will reset
the complete framing algorithm.

8) When CRC-4 multiframing has been achieved, the
primary basic frame alignment and resulting
multiframe alignment will be adjusted to the basic
frame alignment determined during CRC-4
synchronization. Therefore, the primary basic frame
alignment will not be updated during the CRC-4
multiframing search, but will be updated when the
CRC-4 multiframing search is complete.

Reframe

E1 Mode
The MT9074 will automatically force a reframe, if

three consecutive frame alignment patterns or three
consecutive non-frame alignment bits are in error.

T1 Mode
The MT9074 will automatically force a reframe if the

framing bit error density exceeds the threshold
programmed by control bits RS1-0 (Framing Mode
Select Word page 1H, address 10H). RS1 = RS0 = 0
forces a reframe for 2 errors out of a sliding window
of 4 framing bits. RS1 = 0, RS0 = 1 forces a reframe
with 2 errors out of 5. RS1 = 1, RS0 = 0 forces a
reframe with 2 errors out of 6. RS1 = RS0 = 1
disables the automatic reframe.

2) The receive channel associated signalling bits and
signalling multiframe alignment bit will be frozen
when multiframe alignment is lost.

In ESF mode all framing bits are checked. In D4
mode either Ft bits only (if control bit 2 - FSI - of
Framing Mode Select Register is set low) or Ft and

31

MT9074 Advance Information

Out of synchronization

>914 CRC errors

in one second

No CRC

multiframe alignment.

8 msec. timer expired*

CRC-4 multi-frame alignment

Start 400 msec timer.

Note 7.

YES

Search for primary basic frame
alignment signal RAI=1, Es=0.

YES

NO

Verify Bit 2 of non-frame

alignment signal.

YES

Verify second occurrence of

frame alignment signal.

YES

Primary basic frame synchronization

acquired. Enable traffic RAI=0, E’s=0. Start

loss of primary basic frame alignment

checking. Notes 7 & 8.

NO

3 consecutive

incorrect frame

alignment

signals

NO

Signalling multi-frame alignment

Search for multiframe

alignment signal.

Note 7.

Start 8 msec timer.

Note 7.

Basic frame

alignment acquired

Find two CRC frame

alignment signals.

Note 7.

CRC multiframe

alignment

CRC-to-CRC interworking. Re-align to new basic

frame alignment. Start CRC-4 processing. E-bits set

as per G.704 and I.431. Indicate CRC synchronization

achieved.

Notes 7& 8.

only if CRC-4 synchronization is selected and automatic CRC-4
interworking is de-selected

* only if CRC-4 synchronization is selected and automatic CRC-4

interworking is de-selected.

** only if automatic CRC-4 interworking is selected.

NO

RAI = 0

NO

No CRC

multiframe

alignment.

8 msec

Parallel search for new basic frame

RAI = 1

CRC-to-non-CRC interworking. Maintain primary

basic frame alignment. Continue to send CRC-4
data, but stop CRC processing. E-bits set to ‘0’.

Indicate CRC-to-non-CRC operation. Note 7.

alignment signal.

Notes 6 & 7.

Check for two consecutive errored

multiframe alignment signals.

400 msec timer expired

YES

Multiframe synchronization

acquired as per G.732.

Note 7.

YES

Notes 7 & 8.

32

Figure 15 - Synchronization State Diagram

Advance Information MT9074

Fs bits are checked (FSI set high). If the D4
secondary yellow alarm is enabled (control bit 1 ­D4SECY of Transmit Alarm Control Word page 1H,
address 11H) then the Fs bit of frame 12 is not
verified for the loss of frame circuit.

In E1 or T1 mode, receive transparent mode
(selected when bit 3 page 1 address 12H is high) no
reframing is forced by the device.

The user may initiate a software reframe at any time
by setting bit 1, page 1, address 10H high (ReFR).
Once the circuit has commenced reframing the
signalling bits are frozen until multiframe
synchronization has been achieved.

MT9074 Channel Signaling

Channel Signaling in T1 mode

In T1 mode,when control bit RBEn (page 1H,
address 14H) is low the MT9074 will insert ABCD or
AB signaling bits into bit 8 of every transmit DS0
channel every 6th frame. The AB or ABCD signaling
bits from received frames 6 and 12 (AB) or from
frames 6, 12, 18 and 24 (ABCD) will be loaded into
an internal storage ram. The transmit AB/ ABCD
signaling nibbles can be passed either via the micro­ports (for channels with bit 1 set high in the Per Time
Slot Control Word - pages 7H and 8H) or through
related channels of the CSTi serial links, see “Table
6 - STBUS vs. DS1 to Channel Relationship(T1)” on
page 14. The receive signaling bits are always
mapped to the equivalent ST-BUS channels on
CSTo. Memory pages five and six contain the
transmit AB or ABCD nibbles and pages eight and
nine the receive AB or ABCD nibbles for micro-por t
CAS access.

The serial control streams that contain the transmit /
receive signaling information (CSTi and CSTo
respectively) are clocked at 2.048 Mhz. The number
of signaling bits to be transmit / received = 24
(timeslots) x 4 bits per timeslot (ABCD) = 24 nibbles.
This leaves many unused nibble positions in the

2.048 Mhz CSTi / CSTo bandwidth. These unused
nibble locations are tristated. The usage of the bit
stream is as follows: the signaling bits are inserted /
reported in the same CSTi / CSTo channels that
correspond to the DS1 channels used in DSTi / DSTo

- see Table , “Table 6 - STBUS vs. DS1 to Channel
Relationship(T1),” on page 14. The control bit MSN
(Signalling Control Word, page 01H, address 14H)
allows for the ABCD bit to use the most significant
nibble of CSTi / CSTo (MSN set high) or the least
significant nibble (MSN set low). Unused nibbles and
timeslots are tristate. In order to facilitate

multiplexing on the CSTo control stream, an
additional control bit CSToEn (Signalling Control
Word, page 01H, address 14H) will tristate the whole
stream when set low. This control bit is forced low
with the reset pin. In the case of D4 trunks, only AB
bits are reported. The control bits SM1-0 allow the
user to program the 2 unused bits reported on CSTo
in the signalling nibble otherwise occupied by CD
signalling bits in ESF trunks.

A receive signaling bit debounce of 6 msec. can be
selected (DBEn set high - Signalling Control Word,
page 01H, address 14H). It should be noted that
there may be as much as 3 msec. added to this
duration because signaling equipment state changes
are not synchronous with the D4 or ESF multiframe.

If multi - frame synchronization is lost (page 3H,
address 10H, bit 6 MFSYNC = 1) all receive
signalling bits are frozen. They will become unfrozen
when multi - frame synchronization is acquired (this
is the same as terminal frame synchronization for
ESF links).

When the SIGI interrupt is unmasked, IRQ will
become active when a signalling state change is
detected in any of the 24 receive channels. The SIGI
interrupt mask is located on page 1, address 1EH, bit
0 (set high to enable interrupt); and the SIGI interrupt
vector (page 4, address 12H) is 01H.

Channel Signaling in E1 mode

In E1 mode,when control bit TxCCS is set to one, the
MT9074 is in Common Channel Signalling (CCS)
mode. When TxCCS is low it is in Channel
Associated Signalling mode (CAS). The CAS mode
ABCD signalling nibbles can be passed either via the
micro-ports (when RPSIG = 1) or through related
channels of the CSTo and CSTi serial links (when
RPSIG = 0). Memory page 09H and 0AH contains
the receive ABCD nibbles and page 05H and 06H
the transmit ABCD nibbles for micro-port CAS
access.

In CAS operation an ABCD signalling bit debounce
of 14 msec. can be selected by writing a one to
DBNCE control bit. This is consistent with the
signalling recognition time of ITU-T Q.422. It should
be noted that there may be as much as 2 msec.
added to this duration because signalling equipment
state changes are not synchronous with the PCM 30
multiframe.

If multiframe synchronization is lost (page 03H,
address 10H, when MFSYNC = 1) all receive CAS
signalling nibbles are frozen. Receive CAS nibbles

33

MT9074 Advance Information

will become unfrozen when multiframe
synchronization is acquired.

When the CAS signalling interrupt is unmasked
(page 01H, address 1EH, SIGI=0), pin IRQ (pin 12 in
PLCC, 85 in MQFP) will become active when a
signalling nibble state change is detected in any of
the 30 receive channels.

In CCS mode the data transmit on channel 16 is
either sourced from channel 16 data on DSTi or from
the pin CSTi. Data received from channel 16 is
clocked out on CSTo (pin 5 in PLCC, pin 70 in
MQFP). By dividing down the extracted 2.048 MHz
clock.

Loopbacks

In order to meet PRI Layer 1 requirements and to
assist in circuit fault sectioning, the MT9074 has six
loopback functions. These are as follows:

a) Digital loopback (DSTi to DSTo at the framer/LIU
interface). Bit DLBK = 0 normal; DLBK = 1 activate.

MT9074

DSTi

System

DSTo

b) Remote loopback (RTIP and RRING to TTIP and
TRING respectively at the DS1 side). Bit RLBK = 0
normal; RLBK = 1 activate.

Tx

DS1

within the MT9074. Sbit information and the DL
originate at the point of loopback.

MT9074

System

DSTi

DSTo

Tx
Rx

DS1

e) Metallic Loopback. MLBK = 0 normal; MLBK = 1
activate, will isolate the external signals RTIP and
RRING from the receiver and internally connect the
analog output TTIP and TRING to the receiver
analog input.

MT9074

System

DSTi

DSTo

Tx
Rx

DS1

f) Local and remote time slot loopback. Remote time
slot loopback control bit RTSL = 0 normal; RTSL = 1
activate, will loop around transmit ST-BUS time slots
to the DSTo stream. Local time slot loopback bits
LTSL = 0 normal; LTSL = 1 activate, will loop around
receive PCM 30 time slots towards the remote PCM
30 end.

MT9074

System

DSTi

DSTo

Tx

DS1

Rx

MT9074

System

DSTo

Tx

Rx

DS1

c) ST-BUS loopback (DSTi to DSTo at the system
side). Bit SLBK = 0 normal; SLBK = 1 activate.

MT9074

System

DSTi

DSTo

Tx

DS1

d) Payload loopback (RTIP and RRING to TTIP and
TRING respectively at the system side). Bit PLBK =
0 normal; PLBK = 1 activate. The payload loopback
is effectively a physical connection of DSTo to DSTi

34

The digital, remote, ST-BUS, payload and metallic
loopbacks are located on page 1, address 15H ­Coding and Loopback Control Word. The remote and
local time slot loopbacks are controlled through
control bits 5 and 4 of the Per Time Slot Control
Words, pages 7H and 8H.

Performance Monitoring

Error Counters

In T1 mode, MT9074 has eight error counters, which
can be used for maintenance testing, an ongoing
measure of the quality of a DS1 link and to assist the
designer in meeting specifications such as TR62411
and T1.403. All counters can be preset or cleared by
writing to the appropriate locations.

Advance Information MT9074

Associated with each counter is a maskable event
occurrence interrupt and a maskable counter
overflow interrupt. Overflow interrupts are useful
when cumulative error counts are being recorded.
For example, every time the framing bit error counter
overflow interrupt (FERO) occurs, 256 frame errors
have been received since the last FERO (page 04H,
address 1DH)interrupt. All counters are cleared and
held low by programming the counter clear bit ­CNTCLR - high (bit 4 of the Reset Control Word,
page 1H, address 1AH). An alternative approach to
event reporting is to mask error events and to enable
the 1 second sample bit (SAMPLE - bit 3 of the
Reset Control Word). When this bit is set the
counters for change of frame alignment, loss of
frame alignment, bpv errors, crc errors, errored
framing bits, and multiframes out of sync are
updated on one second intervals coincident with the
maskable one second interrupt timer.

In E1 mode, MT9074 has six error counters, which
can be used for maintenance testing, an ongoing
measure of the quality of a PCM 30 link and to assist
the designer in meeting specifications such as ITU-T
I.431 and G.821. All counters can be preset or
cleared by writing to the appropriate locations.

Associated with each counter is a maskable event
occurrence interrupt and a maskable counter
overflow interrupt. Overflow interrupts are useful
when cumulative error counts are being recorded.
For example, every time the frame error counter
overflow (FERO) interrupt occurs, 256 frame errors
have been receiv ed since the last FERO interrupt. All
counters are cleared and held low by programming
the counter clear bit (master control page 01H,
address 1A, bit 4) high. Counter overflows set bits in
the counter overflow latch (page 04H, address 1FH);
this latch is cleared when read.

The overflow reporting latch (page 04H, address
1FH) contains a register whose bits are set when
individual counters overflow. These bits stay high
until the register is read.

T1 Counters

Framing Bit Error Counter (FC7-0)
This eight bit counter counts errors in the framing

pattern. In ESF mode any error in the 001011
framing pattern increments the counter. In SLC-96
mode any error in the Ft bit position is counted. In D4
mode Ft errors are always counted, Fs bits (except
for the Sbit in frame 12) may optionally be counted (if
control bit FSI is set high - page 1H, address 10H, bit

2). The counter is located on page 4H, address 13H.

There are two maskable interrupts associated with
the Framing bit error measurement. A single error
may generate an interrupt (enable by setting FERI
high - bit 7 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit FEOM high - bit 2 of
Interrupt Mask Word Two (page 1H, address 1DH).

Out Of Frame / Change Of Frame Alignment
Counter (OOF3-0/COFA3-0)

This register space is shared by two nibbles. One is
the count of out of frame events. The other
independent counter is incremented when, after a
resynchronization, the frame alignment has moved.
This count is reported in page 4, address 13H.

There are two interrupts associated with the Change
of Frame Alignment counter. A single error may
generate an interrupt (enable by setting COFAI high ­bit 4 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit COFAO high - bit 4 of
Interrupt Mask Word Two (page 1H, address 1DH).

There is one interrupt associated with the Out of
Frame counter. A counter overflow interrupt may be
enabled by setting control bit OOFO high - bit 5 of
Interrupt Mask Word Two (page 1H, address 1DH).

Multiframes out of Sync Counter (MFOOF7­MFOOF0)

This eight bit counter MFOOF7 - MFOOF0 is located
on page 4 address 15H, and is incremented once per
multiframe (1.5 ms for D4 and 3 ms for ESF) during
the time that the framer is out of terminal frame
synchronization.

There is a maskable interrupt associated with the
measurement. A counter overflow interrupt may be
enabled by setting control bit MFOOFO high - bit 1 of
Interrupt Mask Word Two (page 1H, address 1DH).

CRC-6 Error Counter (CC15-0)
CRC-6 errors are recorded by this counter for ESF

links. This 16 bit counter is located on page 4H,
addresses 18H and 19H.

There are two maskable interrupts associated with
the CRC error measurement. A single error may
generate an interrupt (enable by setting CRCI high ­bit 6 of the Interrupt Mask Word One, page 1H,
address 1CH). A counter overflow interrupt may be
enabled by setting control bit CRCO high - bit 6 of
Interrupt Mask Word Two (page 1H, address 1DH).

35

MT9074 Advance Information

Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar

violations or encoding errors that are not part of
B8ZS encoding. This counter BPV15-BPV0 is 16 bits
long (page 4H, addresses 16H and 17H) and is
incremented once for every BPV error received. It
should be noted that when presetting or clearing the
BPV error counter, the least significant BPV counter
address should be written to before the most
significant location.

There are two maskable interrupts associated with
the bipolar violation error measurement. A single
error may generate an interrupt (enable by setting
BPVI high - bit 3 of the Interrupt Mask Word One,
page 1H, address 1CH). A counter overflow interrupt
may be enabled by setting control bit BPVO high - bit
3 of Interrupt Mask Word Two (page 1H, address
1DH).

PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS

comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
which counts receive CRC multiframes. A maskable
PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.

CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4

multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.

E1 Counters

E-bit Counter (EC9-0)
E-bit errors are counted by the MT9074 in order to

support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
14H and 15H respectively. It is incremented by single
error events, with a maximum rate of twice per CRC­4 multiframe.

There are two maskable interrupts associated with
the E-bit error measurement. EBI (page 1, address
1CH) is initiated when the least significant bit of the
counter toggles, and FEBEO (page 01H, address
1DH) is initiated when the counter overflows.

Bipolar Violation Error Counter (BPV15-BPV0)
The bipolar violation error counter will count bipolar

violations or encoding errors that are not part of
HDB3 encoding in E1 mode. This counter BPV15­BPV0 is 16 bits long (page 4H, addresses 16H and
17H) and is incremented once for every BPV error
received. It should be noted that when presetting or
clearing the BPV error counter, the least significant
BPV counter address should be written to before the
most significant location.

In E1 mode, there are two maskable interrupts
associated with the bipolar violation error
measurement. BPVI (page 01H, address 1CH) is
initiated when the l significant bit of the BPV error
counter toggles. BPVO (page 01H, address 1DH) is
initiated when the counter changes from FFFFH to
0000H.

CRC-4 Error Counter (CC9-0)
CRC-4 errors are counted by the MT9074 in order to

support compliance with ITU-T requirements. This
ten bit counter is located on page 04H, addresses
18H and 19H in E1 mode. It is incremented by single
error events, which is a maximum rate of twice per
CRC-4 multiframe.

Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter

EFAS7 - EFAS0 is located on page 04H address
13H, and is incremented once for every receive
frame alignment signal that contains one or more
errors.

There are two maskable interrupts associated with
the frame alignment signal error measurement. FERI
(page 01H, address 1CH) is initiated when the least
significant bit of the errored frame alignment signal
counter toggles, and FERRO (page 01H, address
1DH) is initiated when the counter changes from
FFH to 00H.

36

There is a maskable interrupt associated with the
CRC error measurement. CRCIM (page 01H,
address 1CH) is initiated when the least significant
bit of the counter toggles, and CRCOM (page 01H,
address 1DH) is initiated when the counter
overflows.

PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS

comparison; one for errors and one for time. Any
errors that are detected in the receive PRBS will
increment the PRBS Error Rate Counter of page
04H, address 10H. Writes to this counter will clear an
8 bit counter, PSM7-0 (page 01H, address 11H)
which counts receive CRC multiframes. A maskable

Advance Information MT9074

PRBS counter overflow (PRBSO) interrupt (page 1,
address 1DH) is associated with this counter.

CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4

multiframes. It can be directly loaded via the
microport. The counter will also be automatically
cleared in the event that the PRBS error counter is
written to by the microport. This counter is located on
page 04H, address 11H.

Error Insertion

In T1 mode MT9074 has six types of error conditions
can be inserted into the transmit DS1 data stream
through control bits, which are located on page 1,
address 19H - Error Insertion Word. These error
events include the bipolar violation errors (BPVE),
CRC-6 errors (CRCE), Ft errors (FTE), Fs errors
(FSE), payload (PERR) and a loss of signal condition
(LOSE). The LOSE function overrides the B8ZS
encoding function.

In E1 mode MT9074 has six types of error conditions
can be inserted into the transmit PCM 30 data
stream through control bits, which are located on
page 01H, address 19H. These error events include
the bipolar violation errors (BPVE), CRC-4 errors
(CRCE), FAS errors (FASE), NFAS errors (NFSE),
payload (PERR) and a loss of signal error (LOSE).
The LOSE function overrides the HDB3 encoding
function.

Clear Channel Capability

In T1 mode when bit zero (CC) in the per time slot
control word is set no bit robbing for the purpose of
signalling will occur in this channel. This bit is not
used in E1 mode.

Microport Signalling

When bit one (RPSIG) is set, the transmit signalling for
the addressed channel can only be programmed by
writing to the transmit signalling page (pages 5H and
6H) via the microport. If zero, the transmit signalling
information is constantly updated with the information
from the equivalent channel on CSTi.

Per Time Slot Looping

Any channel or combination of channels may be
looped from transmit (sourced from DSTi) to receive
(output on DSTo) STBUS channels. When bit four
(LTSL) in the Per Time Slot Control Word is set the
data from the equivalent transmit timeslot is looped
back onto the equivalent receive channel.

Any channel or combination of channels may be
looped from receive (sourced from the line data) to
transmit (output onto the line) channels. When bit
five (RTSL) in the Per Time Slot Control Word is set
the data from the equivalent receive timeslot is
looped back onto the equivalent transmit channel.

PRBS Testing

Per Time Slot Control Words

There are two per time slot control pages (addresses
AH and BH) (T1/E1) occupying a total of 24 unique
addresses in T1 mode or a total of 32 unique
addresses in E1 mode. Each address controls a
matching timeslot on the 24 DS1 channels (T1) or 32
PCM-30 channels (E1) and the equivalent channel
data on the receive (DSTo) data. For example
address 0 of the first per time slot control page
contains program control for transmit timeslot 0 and
DSTo channel 0.

Per Time Slot Control Word
Bit 7 Bit 0

T1 Mode

TXMSG PCI RTSL LTSL TTST RRST RPSIG CC

E1 Mode

TXMSG ADI RTSL LTSL TTST RRST RPSIG - - -

If the control bit ADSEQ is zero (from master control
page 1 - access control word), any channel or
combination of transmit channels may be
programmed to contain a generated pseudo random
bit sequence (215 -1). The channels are selected by
setting bit three (TTST), in the per time slot control
word.

If the control bit ADSEQ is zero, any combination of
receive channels may be connected to the PRBS
decoder (215-1). Each error in the incoming
sequence causes the PRBS error counter to
increment. The receive channels are selected by
setting bit 2 (RRST) in the per time slot control word.

If PRBS is performed during a metallic or external
looparound, per time slot control words with TTST
set should have RRST set as well.

37

MT9074 Advance Information

Digital Milliwatt

If the control bit ADSEQ is one, a digital milliwatt
sequence (Table 18) in T1 mode or (Table 19) in E1
mode may be transmit on any combination of
selected channels. The channels are selected by
setting bit three (TTST), in the Per Time Slot Control
Word.

Under the same control condition (ADSEQ equal to
one), the same digital milliwatt sequence is available
to replace received data on any combination of DSTo
channels. This is accomplished by setting bit two
(RRST) in the Per Time Slot Control Word for the
corresponding channel.

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

00011110
00001011
00001011
00011110
10011110
10001011
10001011
10011110

Table 18 - Digital Milliwatt Pattern (T1)

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

00110100
00100001
00100001
00110100
10110100
10100001
10100001
10110100

Table 19 - A-Law Digital Milliwatt Pattern (E1)

Per Channel Inversion

When bit six (PCI) in the Per Time Slot Control Word
is set both transmit and receive data for the selected
channel is inverted before going onto the line / DSTo
respectively.

Transmit Message

When bit seven (TXMSG) in the Per Time Slot
Control Word is set the data transmit in the selected

channel is sourced from the transmit message word
in Master Control page 1.

Alarms

The following alarms are detected by the receiver in
T1 mode. Each may generate a maskable interrupt:

• Yellow alarm - in D4 mode there are two
possible yellow alarm signals. If control bit
D4SECY is set low, (page 1H, address 11Hb
it 1) the criteria for a yellow alarm is an
excess of ’0’s (more than 285) in bit position
2 of incoming DS0 channels during an
integration period of 1.5 milliseconds. It is
cleared after more than 3 ’1’s are detected in
bit position 2 of normal data in a 1.5
millisecond integration period. If D4SECY is
set high the secondary yellow alarm is
selected. The detection criteria becomes 2
consecutive’1’s in the Sbit position of the
12th frame. In ESF mode the alarm is set if
the pattern 0000000011111111 is received
in seven or more codewords out of ten.;

• All Ones - This bit (page 3H, address 11H,
bit 3) is set if less than six zeros are received
on the incoming line data during a 3 ms
interval

• Loss of Signal - a loss of signal condition
occurs when the receive signal level is lower
than 40 dB below the nominal signal level for
at least a millisecond or when 192
consecutive zeros have been received. A
loss of signal condition will terminate when
than average ones density of at least 12.5%
has been received over a period of 193
contiguous pulse positions starting with a
pulse. The loss of signal is reported in the
Receive Signal Status Word - page 3,
address 16H bit 4.

The following alarms are detected by the receiver in
E1 mode. Each may generate a maskable interrupt:

• Remote Alarm Indication (RAI) - bit 3 (A) of
the receive NFAS;

• Alarm Indication Signal (AIS) - unframed all
ones signal for at least a double frame (512
bits) or two double frames (1024 bits);

• Channel 16 Alarm Indication Signal - all ones
signal in channel 16;

• Auxiliary pattern - 101010... pattern for at
least 512 bits;

• Loss of Signal - a loss of signal condition
occurs when the receive signal level is lower
than 20dB or 40 dB (by setting the bit ELOS
on page 2) below the nominal signal level for

38

Advance Information MT9074

more than a millisecond or when more than
192 zeros have been received in a row. A
loss of signal condition will terminate when
an average ones density of at least 12.5%
has been received over a period of 255
contiguous pulse positions starting with a
pulse.

• Remote Signalling Multiframe Alarm - (Y-bit)
of the multiframe alignment signal.

The alarm reporting latch (address 12H page 04H)
contains a register whose bits are set high for
selected alarms. These bits stay high until the
register is read. This allows the controller to record
intermittent or sporadic alarm occurrences.

Automatic Alarms

In E1 mode the transmission of RAI and signalling
multiframe alarms can be made to function
automatically from control bits ARAI and AUTY
(page 01H, address 10H). When ARAI = 0 and basic
frame synchronization is lost (SYNC = 1), the
MT9074 will automatically transmit the RAI alarm
signal to the far end of the link. The transmission of
this alarm signal will cease when basic frame
alignment is acquired.

(bit 0 address 11H of page 3H) will be asserted when
a repeating 001 pattern (either framed or unframed)
has persisted for 48 milliseconds. Line Loopback
Enable Detect LLED in the Alarm Status Word will be
asserted when a repeating 00001 pattern (either
framed or unframed) has persisted for 48
milliseconds.

Pulse Density Violation Detect
In T1 mode bit 2 of address 11H on page 3H (PDV)

toggles if the receive data fails to meet ones density
requirements. It will toggle upon detection of 16
consecutive zeros on the line data, or if there are
less than N ones in a window of 8(N+1) bits - where
N = 1 to 23.

Timer Outputs
In T1 mode MT9074 has a one second timer derived

from the 20 Mhz oscillator pins. The timer may be
used to trigger interrupts for T1.403/408
performance messaging.

E1 mode

Consecutive Frame Alignment Patterns (CONFAP)
Two consecutive frame alignment signals in error.

When AUTY = 0 and signalling multiframe alignment
is not acquired (MFSYNC = 1), the MT9074 will
automatically transmit the multiframe alarm (Y-bit)
signal to the far end of the link. This transmission will
cease when signalling multiframe alignment is
acquired.

Detected Events and Words

T1 mode

Severely Errored Frame Event
In T1 mode bit 5 page 3H address 10H toggles

whenever a sliding window detects 2 framing errors
events (Ft or ESF) in a sliding window of 6.

Loop Code Detect
T1.403 defines SF mode line loopback activate and

deactivate codes. These codes are either a framed
or un-framed repeating bit sequence of 00001 for
activation or 001 for deactivation. The standard goes
on to say that these codes will persist for five
seconds or more before the loopback action is taken.
In T1 mode MT9074 will detect both framed and
unframed line activate and de-activate codes even in
the presence of a BER of 3 x 10-3. Line Loopback
Disable Detect - LLDD - in the Alarm Status Word

Receive Frame Alignment Signals
These bits are received on the PCM 30 and link in bit

positions two to eight of time slot 0 - frame alignment
signal. These signals form the frame alignment
signal and should be 0011011.

Receive Non Frame Alignment Signal
This signal is received on the PCM 30 and link in bit

position two of time slot 0 - non frame alignment
signal.

Receive Multiframe Alignment Signals
These signal are received on the PCM 30 and link in

bit position one to four of time slot 16 of frame zero
of every signalling multiframe.

Interrupts

The MT9074 has an extensive suite of maskable
interrupts, which are divided into four categories
based on the type of event that caused the interrupt.
Each interrupt has an associated mask and interrupt
bit. When an unmasked interrupt event occurs, IRQ
will go low and one or more bits of the appropriate
interrupt register will go high. After each interrupt
register is read it is automatically cleared. When all

39

MT9074 Advance Information

interrupt registers are cleared IRQ will return to a
high impedance state. This function can also be
accomplished by toggling the INTA bit (page 1,
address 1AH).

All the interrupts of the MT9074 in T1 and E1 mode
are maskable. This is accomplished through interrupt
mask words zero to three, which are located on page
1, addresses 1BH to 1EH and the (optional) HDLC
interrupt mask located at address 16 of page B.

After a MT9074 reset (RESET pin or RST control bit),
all interrupts are masked.

All interrupts may be suspended, without changing
the interrupt mask words, by making the SPND
control bit of page 1, address 1AH high.

All interrupts are cleared by forcing the pin TxAO low.

Interrupts on T1 mode

Interrupt Mask Word Zero
Bit 7 Bit 0

TFSYNI MFSYNI TSAI AISI LOSI SEI TxSLPI RxSLPI

Interrupt Mask Word One
Bit 7 Bit 0

FEI CRCI YELI COFAI BPVI PRBSI PDVI - - -

Interrupt Mask Word Two
Bit 7 Bit 0

FEO CRCO OOFO COFAO BPVO PRBSO MFOOFO - - -

Interrupt Mask Word Three
Bit 7 Bit 0

- - - - - - - - - LCDI 1SECI 5SECI BIOMI SIGI

HDLC Interrupt Masks
Bit 7 Bit 0

Ga EOPD TEOP EopR TxFl FATxU RxFf RxOv

Interrupts on E1 mode

Interrupt Mask Word Zero
Bit 7 Bit 0

SYNI MFSYI CSYNI AISI LOSI CEFI YI SLPI

Interrupt Mask Word One
Bit 7 Bit 0

FERI CRCI EBI AIS16I BPVI PRBSI AUXPI RAII

Interrupt Mask Word Two
Bit 7 Bit 0

FEOM CRCO EBOI - - - BPVO PRBSO PRBSMO - - -

Interrupt Mask Word Three
Bit 7 Bit 0

- - - - - - - - - JAI 1SECI 5SECI RCRI SIGI

HDLC Interrupt Masks
Bit 7 Bit 0

Ga EOPD TEOP EopR TxFl FATxU RxFf RxOv

40

Advance Information MT9074

Digital Framer Mode

T1 mode

Setting bit 4 in the Configuration Control Word
(address 10H of Master Control Page 2) disables the
LIU and converts the MT9074 into a digital T1
transceiver. The digital 2.048 Mb/s ST-BUS
backplane maps into transmit and receive digital

1.544 Mb/s streams. The 1.544 Mb/s transmit
streams may be formatted for single phase NRZ (by
setting bit 7 of the LIU Control Word - Master Page 1
high) or two phase NRZ. The data rate conversion
(between 2.048 Mb/s and 1.544 Mb/s) is done within
the MT9074. The transmit 1.544 MHz clock is
internally generated from a PLL that locks onto the
input C4b clock. This clock is then output on pin
E1.5o (PLCC pin 44 - QFP pin 32). The digital 1.544
Mb/s transmit data is output on pins TXA and TXB
(PLCC pins 37,38 - QFP pins 18,19) with the rising
edge of C1.5o. Receive digital data is clocked in on
pins RRING and RTIP. This data is clocked in with
the rising edge of the input 1.544 Mhz clock S/FR/
E1.5i (PLCC pin 66, QFP pin 63). Coding is optional
under software control.

E1 mode

Setting bit 4 in the Configuration Control Word
(address 10H of Master Control Page 2) disables the
LIU and converts the MT9074 into a digital E1
transceiver. The digital 2.048 Mb/s ST-BUS
backplane maps into transmit and receive digital

2.048 Mb/s streams. The 2.048 Mb/s transmit data
streams may be formatted for single phase NRZ (by
setting bit 7 of the LIU Control Word - Master Page 1
high) or two phase NRZ. The transmit 2.048 MHz
clock is derived from the input C4b clock. This clock
is then output on pin E1.5o (PLCC pin 44 - QFP pin

32). The digital 2.048 Mb/s transmit data is output on
pins TXA and TXB (PLCC pins 37,38 - QFP pins
18,19) with the rising edge of E1.5o. Receive digital
data is clocked in on pins RRING and RTIP. This
data is clocked in with the rising edge of the input

2.048 Mhz clock MS/FR/E1.5i (PLCC pin 66, QFP
pin 63). Coding is optional under software control.

41

MT9074 Advance Information

Control and Status Registers

T1 Mode

Master Control 1 (Page 01H) (T1)

Address

(A4A3A2A1A0)

10H (Table 21) Framing Mode Select ESF, SCL96, CXC, RS1-0, FSI, ReFR,

11H (Table 22) Transmit Alarm Control Word ESFYEL, TXSECY, D4YEL, TxAO, LUA, LDA,

12H (Table 23) Data Link Control Word EDL, BIOMEn, HDLC0, HDLC1, TxSYNC,

13H (Table 24) Transmit Bit Oriented Message BIOMTx7-0
14H (Table 25) Signalling Control Word DSToEn, CSToEn, RBEn, DBEn, MSN, SM1-0,

15H (Table 26) Coding and Loopback Control Word RxB8ZS, MLBK,TxB8ZS,FBS, DLBK, RLBK,

16H (Table 27) Reserved Set all bits to zero for normal operation
17H (Table 28) Transmit Elastic buffer Set Delay Word TxTSD7-0
18H (Table 29) Transmit Message Word TXM7-0
19H (Table 30) Error Insertion Word BPVE, CRCE, FTE, FSE, LOSE, PERR,

Register Function

MFReFR

D4SECY, SO

TRSP,JT, H1R64

JYEL

SLBK, PLBK

LOS/LOF

1AH (Table 31) Reset Control Word RST, SPND, INTA, CNTCLR, SAMPLE,

EXTOSC

1BH (Table 32) Interrupt Mask Word Zero TFSYNIM, MFSYNIM, AISIM, LOSIM, SEIM,

TxSLPIM, RxSLPIM

1CH (Table 33) Interrupt Mask Word One FEIM, CRCIM, YELIM, COFAIM, BPVIM,

PRBSIM, PDVIM

1DH (Table 34) Interrupt Mask Word Two FEOM, CRCOM, OOFOM, COFAOM, BPVOM,

PRBSOM, PRBSMFOM,MFOOFOM
1EH (Table 35) Interrupt Mask Word Three LCDIM, 1SECIM, 5SECIM, BIOIM, SIGIM
1FH (Table 36) LIU Control Word NRZ, TxL2-0, REDBL, RES2-0

Table 20 - Master Control 1 (Page 1) (T1)

42

Advance Information MT9074

Bit Name Functional Description

7 ESF Extended Super Frame.

Setting this bit enables
transmission and reception of
the 24 frame superframe DS1
protocol.

6 SLC96 SLC96 Mode Select. Setting

this bit enables input and output
of the Fs bit pattern on the TxDL
and RxDL pins. Frame
synchronization is the same as
in the case of D4 operation. The
transmitter will insert A and B
bits every 6 frames after
synchronizing to the Fs pattern
clocked into Txdl. Receive Fs
bits are not monitored for the
Framing Bit Error Counter.

5 CXC Cross Check. Setting this bit in

ESF mode enables a cross
check of the CRC-6 remainder
before the frame synchronizer
pulls into sync. This process
adds at least 6 milliseconds to
the frame synchronization time.
Setting this bit in D4 (not ESF)
mode enables a check of the Fs
bits in addition to the Ft bits
during frame synchronization

Bit Name Functional Description

2 FSI Fs Bit Include. Only applicable

in D4 mode (not ESF or
SLC96). Setting this bit causes
errored Fs bits to be included as
framing bit errors. A bad Fs bit
will increment the Framing Error
Bit Counter, and will potentially
cause a reframe (if it is the
second bad framing bit out of 5).
The Fs bit of the receive frame
12 will only be included if
D4SECY is set low.

1 ReFR Reframe. Setting this bit causes

an automatic reframe.

0 MFReFR MultiFrame Reframe. Only

applicable in D4 or SLC96
mode. Setting this bit causes an
automatic multiframe reframe.
The signalling bits are frozen
until multiframe synchronization
is achieved. Terminal frame
synchronization is not affected.

Table 21 - Framing Mode Select (T1)

(Page 1, Address 10H)

4 - 3 RS1- 0 Reframe Select 1 - 0. These

bits set the criteria for an
automatic reframe in the event
of framing bits errors. The
combinations available are:

RS1 - 0, RS0 - 0 = sliding
window of 2 errors out of 4.

RS1 - 0, RS0 - 1 = sliding
window of 2 errors out of 5.

RS1 - 1, RS0 - 0 = sliding
window of 2 errors out of 6.

RS1 - 1, RS0 - 1 = no reframes
due to framing bit errors.

Table 21 - Framing Mode Select (T1)

(Page 1, Address 10H)

43

MT9074 Advance Information

Bit Name Functional Description

7 ESFYEL ESFYellow Alarm. Setting this bit

while in ESF mode causes a
repeating pattern of eight 1’s
followed by eight 0’s to be insert
onto the transmit FDL (JTS bit set
low - see Data Link Control Word)
or sixteen 1’s (Japan Telecom bit
set high).

6 TXSECY Transmit Secondary D4 Yellow

Alarm. Setting this bit (in D4
mode) causes the S bit of
transmit frame 12 to be set.

5 D4YEL D4 Yellow Alarm. When set bit 2

of all DS0 channels are forced
low.

4 TxAO Transmit All Ones. When low,

this control bit forces a framed or
unframed (depending on the state
of Transmit Alarm Control bit 0)
all ones to be transmit at TTIP
and TRING.

3 LUA Loop Up Activate. Setting this bit

forces transmission of a framed
or unframed (depending on the
state of Transmit Alarm Control
bit 0) repeating pattern of 00001.

2 LDA Loop Down Activate. Setting

this bit forces transmission of a
framed or unframed (depending
on the state of Transmit Alarm
Control bit 0) repeating pattern of

001.

1 D4SECY D4 Secondary Alarm. Set this bit

for trunks employing the
secondary Yellow Alarm. The Fs
bit in the 12th frame will not be
used for counting errored framing
bits. If a one is received in the Fs
bit position of the 12th frame a
Secondary Yellow Alarm Detect
bit will be set.

0SOOverhead Sbits Override. If set,

this bit forces the overhead bits to
be inserted as an overlay on any
of the following alarm conditions:
i) transmit all ones, ii) loop up
code insertion, iii) loop down code
insertion.

Bit Name Functional Description

7 EDL Enable Data Link. Setting this bit

multiplexes the serial stream
clocked in on pin TxDL into the
FDL bit position (ESF mode) or the
Fs position (D4 mode).

6 BIOMEn Bit Oriented Messaging Enable.

Setting this bit enables
transmission of bit - oriented
messages on the ESF facility data
link. The actual message transmit
at any one time is contained in the
BIOMTx register (page 1, address
13H). The receive bit - oriented
message register is always active,
although the interrupt associated
with it may be masked.

5 HDLC0 HDLC0 Enable. Setting this bit

selects the internal HDLC
controller for transmission of data
link information in the FDL Sbits of
an ESF frame. The HDLC receiver
is always active, although
interrupts associated with it may
be masked.

4 HDLC1 HDLC1 Enable. Setting this bit

selects the internal HDLC
controller for transmission on DS1
channel 24. The HDLC receiver is
always active, although interrupts
associated with it may be masked.

3 TxSYNC Transmit Synchronization.

Setting this bit causes the transmit
multiframe boundary to be
internally synchronized to the
incoming Sbits on DSTi channel
31 bit 0.

2 TRSP Transparent Mode. Setting this

bit causes unframed data to be
transmit from DSTi channels 0 to
23 and channel 31 bit 7 to be
transmit transparently onto the
DS1 line. Unframed data received
from the DS1 line is piped out on
DSTo channels 0 to 23 and
channel 31 bit 0.

Table 23 - Data Link Control Word (T1)

(Page 1, Address 12H)

Table 22 - Transmit Alarm Control Word (T1)

(Page 1, Address 11H)

44

Advance Information MT9074

Bit Name Functional Description

1 JTS Japan Telecom Synchro-

nization. Setting this bit forces the

inclusion of Sbits in the CRC-6
calculation.

0 H1R64 HDLC1 Rate Select. Setting this

pin high while HDLC1 is activated
enables 64 Kb/s operation of the
data link on channel 24. Setting
this pin low while HDLC1 is
activated enables 56 Kb/s
operation on channel 24 (this
prevents data corruption due to
forced bit stuffing).

Table 23 - Data Link Control Word (T1)

(Page 1, Address 12H)

Bit Name Functional Description

7 - 0 BIOMTx7-0 Transmit Bit Oriented

Message. The contents of this

register are concatenated with a
sequence of eight 1’s and
continuously transmit in the FDL
bit position of ESF trunks.
Normally the leading bit (bit 7)
and last bit (bit 0) of this register
are set to zero.

Table 24 - Transmit Bit Oriented Message (T1)

(Page 1, Address 13H)

Bit Name Functional Description

7 DSToEn DSTo Enable. If zero pin DSTo is

tristate. If set the pin DSTo is
enabled.

6 CSToEn CSTo Enable. If zero pin CSTo is

tristate. If set the pin CSTo is
enabled.

5 RBEn Robbed Bit Signalling Enable.

Setting this bit multiplexes the AB
or ABCD signalling bits into bit
position 8 of all DS0 channels
every 6th frame.

4 DBEn Debounce Enable. Setting this

bit causes incoming signalling bits
to be debounced for a period of 6
to 9 milliseconds before reporting
on CSTo or in the Receive
Signalling Bits Page.

3 MSN Most Significant Nibble. If set to

one the most significant nibble of
CSTi and CSTo are activated.
The reporting stream CSTo
contains signalling information
for the equivalent channel in the
most significant nibble, and least
significant nibble is tristate. If set
to zero the least significant nibble
is active for CSTi and CSTo and
the most significant nibble of
CSTo is tristate.

2-1 SM1-0 Signalling Message. These two

bits are used to fill the vacant bit
positions available on CSTo when
the MT9074 is operating on a D4
trunk. The first two bits of each
reporting nibble of CSTo contain
the AB signalling bits. The last
two contain SM1 and SM0 (in that
order). When the MT9074 is
connected to ESF trunks four
signalling bits (ABCD) are
reported and bits SM1-0 become
unused.

0 JYEL Japan Yellow Alarm. Set this bit

high to select a pattern of 16 ones
(1111111111111111) as the ESF
yellow alarm, both for the case
when and ESF yellow alarm is to
be transmitted or in recognizing a
received yellow alarm.

Table 25 - Signalling Control Word (T1)

(Page 1, Address 14H)

45

MT9074 Advance Information

Bit Name Functional Description

7 RxB8ZS Receive B8ZS Enable. If one,

receive B8ZS decoding is
enabled.

6 MLBK Metallic Loopback. If one, then

RRTIP/RRING are connected
directly to TTIP and TRING
respectively. If zero, this feature is
disabled. Set the transmit line
build out to -7.5dB when metallic
loopback is enabled.

5 TxB8ZS Transmit B8ZS Enable. If one, all

zero octets are substituted with
B8ZS codes.

4 FBS Forced Bit Stuffing. If set any

transmit DS0 channel containing
all zeros has bit 7 forced high.

3 DLBK Digital Loopback. If one, the

digital stream to the transmit LIU
is looped back in place of the
digital output of the receive LIU.
Data coming out of DSTo will be a
delayed version of DSTi. If zero,
this feature is disabled.

2 RLBK Remote Loopback. If one, all

time slots received on RRTIP/
RRING are connected to TTIP/
TRING on the DS1 side of the
MT9074. If zero, this feature is
disabled.

Bit Name Functional Description

0 PLBK Payload Loopback. If one, all

time slots received on RTIP/
RRING are connected to TTIP/
TRING on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. If receive robbed bit
signaling data is to be included in
the looped data, then the control
bit RBEn (Page 1 Address 14H,
Bit 5) must be set low, otherwise
transmit signaling data will be
placed into the LSB of each
timeslot every sixth frame. Setting
all Clear Channel control bits high
(Bit 0 in the Per Time Slot Control
words - Pages 7 and 8 Address
10H to IFH inclusive) has the
same effect as setting control bit
RBEn low.

Table 26 - Coding and Loopback Control Word

(T1)(Page 1, Address 15H)

Bit Name Functional Description
7-0 - - - Unused

Table 27 - Reserved (T1)

(Page 1, Address 16H)

Bit Name Functional Description

1 SLBK ST-BUS Loopback. If one, all

time slots of DSTi are connected
to DSTo on the ST-BUS side of the
MT9074. If zero, this feature is
disabled. See Loopbacks section.

Table 26 - Coding and Loopback Control Word

(T1)(Page 1, Address 15H)

7-0 TxSD7-0 Transmit Set Delay Bits 7-0.

Writing to this register forces a one
time setting of the delay through the
transmit slip buffer. Delay is defined
as the time interval between the
write of the transmit STBUS channel
containing DS1 timeslot 1 and its
subsequent read. Delay is modified
by moving the position of the
internally generated DS1 frame
boundary.Delay (when set) will
always be less than 1 frame
(125uS). This register must be
programmed with a non-zero value
(such as 0FH).

Table 28 - Transmit Elastic Buffer Set Delay

Word (T1) (Page 1, Address 17H)

46

Advance Information MT9074

Bit Name Functional Description

7-0 TxM7-0 Transmit Message Bits 7 - 0. The

contents of this register are
transmitted into those outgoing DS1
channels selected by the Per Time
Slot Control registers.

Table 29 - Transmit Message Word (T1)

(Page 1, Address 18H)

Bit Name Functional Description

7 BPVE Bipolar Violation Error

Insertion. A zero-to-one transition

of this bit inserts a single bipolar
violation error into the transmit
DS1 data. A one, zero or one-to­zero transition has no function.

6 CRCE CRC-6 Error Insertion. A zero-to-

one transition of this bit inserts a
single CRC-6 error into the
transmit ESF DS1 data. A one,
zero or one-to-zero transition has
no function.

5 FTE Terminal Framing Bit Error

Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit D4 Ft pattern or the
transmit ESF framing bit pattern
(in ESF mode). A one, zero or
one-to-zero transition has no
function.

4 FSE Signal Framing Bit Error

Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit Fs bits (in D4 mode
only). A one, zero or one-to-zero
transition has no function.

3 LOSE Loss of Signal Error Insertion. If

one, the MT9074 transmits an all
zeros signal (no pulses). Zero
code suppression is overridden. If
zero, data is transmitted normally.

2 PERR Payload Error Insertion. A zero -

to - one transition of this bit inserts
a single bit error in the transmit
payload. A one, zero or one-to­zero transition has no function.

Bit Name Functional Description

1 - - - Unused.
0 LOS/

LOF

Table 30 - Error Insertion Word (T1)

Bit Name Functional Description

7 RST Software reset. Setting this bit is

6 SPND Suspend Interrupts. If one, the

5 INTA Interrupt Acknowledge. Setting

4 CNTCLR Counter Clear. If one, all status

3 SAMPLE One Second Sample. Setting

Table 31 - Reset Control Word (T1)

Loss of Signal or Loss of Frame
Selection. If one, pin LOS will go

high when a loss of signal state
exists (criteria as per LLOS status
bit). If low, pin LOS will go high
when either a loss of signal or a
loss of frame alignment state exits.

(Page 1, Address 19H)

equivalent to performing a
hardware reset. All counters are
cleared and the control registers
are set to their default values.
This control bit is internally
cleared after the reset operation
is complete.

IRQ output will be in a high­impedance state and all
interrupts will be ignored. If zero,
the IRQ output will function
normally.

this bit clears all the interrupt
status bits and forces the IRQ pin
into high impedance. The control
bit itself is then internally cleared.

error counters are cleared and
held low.

this bit causes the error counters
(change of frame alignment, loss
of frame alignment, bpv errors,
crc errors, severely errored frame
events and multiframes out of
sync) to be updated on one
second intervals coincident with
the one second timer (status
page 3 address 12H bit 7).

(Page 1, Address 1AH)

Table 30 - Error Insertion Word (T1)

(Page 1, Address 19H)

47

MT9074 Advance Information

Bit Name Functional Description

2 EXTOSC External Oscillator Select.

Setting this bit connects the pin
OSC1 to a TTL compatible input.
This allows for a system design
employing a TTL output oscillator
as a 20.000 Mhz reference clock.

1 RSV Reserved. Set to zero for normal

operation.

0 RSV Reser ved. Set to zero for normal

operation.

Table 31 - Reset Control Word (T1)

(Page 1, Address 1AH)

Bit Name Functional Description

7 TFSYNIM Terminal Frame

Synchronization Interrupt
Mask. When unmasked an

interrupt is initiated whenever
a change of state of terminal
frame synchronization condition
exists. If 1 - unmasked, 0 ­masked.

6 MFSYNIM Multiframe Synchronization

Interrupt Mask. When
unmasked an interrupt is
initiated whenever a change of
state of multiframe
synchronization condition exist.

If 1 - unmasked, 0 - masked.
5 - - - Unused.
4 AISIM Alarm Indication Signal

Interrupt Mask. When

unmasked a change of state of

received all ones condition will

initiate an interrupt. If 1 -

unmasked, 0 - masked.
3 LOSIM Loss of Signal Interrupt Mask.

When unmasked an interrupt is

initiated whenever a change of

state of loss of signal condition

exists. If 1 - unmasked, 0 -

masked. Interrupt vector =

01000000.

Table 32 - Interrupt Mask Word Zero (T1)

(Page 1, Address 1BH)

Bit Name Functional Description

2 SEFIM Severely Errored Frame

Interrupt Mask. When

unmasked an interrupt is
initiated when a sequence of 2
framing errors out of 6 occurs. If
1 - unmasked, 0 - masked.

1 TxSLPIM Transmit SLIP Interrupt Mask.

When unmasked an interrupt is
initiated whenever a controlled
frame slip occurs in the transmit
elastic buffer. If 1 - unmasked, 0

- masked.

0 RxSLPIM Receive SLIP Interrupt Mask.

When unmasked an interrupt is
initiated whenever a controlled
frame slip occurs in the receive
elastic buffer. If 1 - unmasked, 0

- masked.

Table 32 - Interrupt Mask Word Zero (T1)

(Page 1, Address 1BH)

Bit Name Functional Description

7 FEIM Framing Bit Error Interrupt

Mask. When unmasked an

interrupt is initiated whenever an
erroneous framing bit is detected
(provided the circuit is in terminal
frame sync). If 1 - unmasked, 0 ­masked.

6 CRCIM CRC-6 Error Interrupt Mask.

When unmasked an interrupt is
initiated whenever a local CRC-6
error occurs. If 1 - unmasked, 0 ­masked.

5 YELIM Yellow Alarm Interrupt Mask.

When unmasked detection of a
yellow alarm triggers an
interrupt. If 1 - unmasked, 0 ­masked.

4 COFAIM Change of Frame Alignment

Interrupt Mask. When
unmasked an interrupt is initiated
whenever a change of frame
alignment occurs after a reframe.
If 1 - unmasked, 0 - masked.

48

Table 33 - Interrupt Mask Word One (T1)

(Page 1, Address 1CH

Advance Information MT9074

Bit Name Functional Description

3 BPVIM Bipolar Violation Interrupt

Mask. When unmasked an

interrupt is initiated whenever a
bipolar violation (excluding
B8ZS encoding) is encountered.
If 1- unmasked, 0 - masked.

2 PRBSIM Psuedo Random Bit

Sequence Error Interrupt
Mask. When unmasked an

interrupt will be generated upon
detection of an error with a
channel selected for PRBS
testing. 1 - unmasked, 0 ­masked.

1 PDVIM Pulse Density Violation

Interrupt Mask. When
unmasked an interrupt is
triggered whenever a sequence
of excessive consecutive zeros
is received on the line, or the
incoming pulse density is less
than N ones in a time frame of
8(N+1) where N = 1 to 23. If 1 ­unmasked, 0 - masked.

Bit Name Functional Description

5 OOFOM Out Of Frame Counter

Overflow Interrupt Mask.

When unmasked an interrupt
is initiated whenever the out
of frame counter changes
state from changes from
FFH to 00H. If 1 - unmasked,
0 - masked.

4 COFAOM Change of Frame

Alignment Counter
Overflow Interrupt Mask.

When unmasked an interrupt
is initiated whenever the
change of frame alignment
counter changes from FFH
to 00H. If 1 - unmasked, 0 ­masked.

3 BPVOM Bipolar Violation Counter

Overflow Interrupt Mask.
When unmasked an interrupt
is initiated whenever the
bipolar violation counter
changes from FFH to 00H. If
1- unmasked, 0 - masked.

0 - - - Unused.

Table 33 - Interrupt Mask Word One (T1)

(Page 1, Address 1CH

Bit Name Functional Description

7 FEOM Framing Bit Error Counter

Overflow Interrupt Mask.

When unmasked an interrupt
is initiated whenever the
framing bit error counter
changes from FFH to 00H. If
1 - unmasked, 0 - masked.

6 CRCOM CRC-6 Error Counter

Overflow Interrupt Mask.

When unmasked an interrupt
is initiated whenever the
CRC-6 error counter
changes from FFH to 00H. If
1 - unmasked, 0 - masked.

Table 34 - Interrupt Mask Word Two (T1)

(Page 1, Address 1DH)

2 PRBSOM Psuedo Random Bit

Sequence Error Counter
Overflow Interrupt Mask.

When unmasked an interrupt
will be generated whenever
the PRBS error counter
changes from FFH to 00H. If
1 - unmasked, 0 - masked.

1 PRBSMFOM Psuedo Random Bit

Sequence Multiframe
Counter Overflow
Interrupt Mask. When

unmasked an interrupt will
be generated whenever the
multiframe counter attached
to the PRBS error counter
overflows. FFH to 00H. If 1 ­unmasked, 0 - masked.

0 MFOOFOM Multiframes Out Of Sync

Overflow Interrupt Mask.

When unmasked an interrupt
will be generated when the
multiframes out of frame
counter changes from FFH
to 00H. If 1 - unmasked, 0 ­masked.

Table 34 - Interrupt Mask Word Two (T1)

(Page 1, Address 1DH)

49

MT9074 Advance Information

Bit Name Functional Description

7-5 - - - Unused.

4 LCDIM Loop Code Detected Interrupt

Mask. When unmasked an
interrupt is triggered when either
the loop up (00001) or loop down
(001) code has been detected on
the line for a period of 48
milliseconds. If 1 - unmasked, 0 ­masked.

3 1SECIM One Second Status Interrupt

Mask. When unmasked an
interrupt is initiated when the
1SEC status bit (page 3 address
12H bit 7) goes from low to high.
If 1 - unmasked, 0 - masked.

2 5SECIM Five Second Status Interrupt

Mask. When unmasked an
interrupt is initiated when the 5
SEC status bit goes from low to
high. If 1 - unmasked, 0 ­masked.

1 BIOMIM Bit Oriented Message

Interrupt Mask. When
unmasked an interrupt is initiated
when a pattern
111111110xxxxxx0 has been
received on the FDL that is
different from the last message.
The new message must persist
for 8 out the last 10 message
positions to be accepted as a
valid new message. If 1­unmasked, 0 - masked.

0 SIGIM Signalling Interrupt Mask.

When unmasked an interrupt will
be initiated when a change of
state (optionally debounced - see
DBEn in the Data Link, Signalling
Control Word page 1 address
12H) is detected in the signalling
bits (AB or ABCD) pattern. If 1 ­unmasked, 0 - masked.

Table 35 - Interrupt Mask Word Three (T1)

(Page 1, Address 1EH)

Bit Name Functional Description

7 NRZ NRZ Format Selection. Only

used in the digital framer only
mode (LIU is disabled). A one sets
the MT9074 to accept a unipolar
NRZ format input stream on RxA
as the line input, and to transmit a
unipolar NRZ format stream on
TxB. A zero causes the MT9074 to
accept a complementary pair of
dual rail inputs on RxA/RxB and to
transmit a complementary pair of
dual rail outputs on TxA/TxB.

6 -4TXL2-0 Transmit Line Build Out 2 - 0.

Setting these bits shapes the
transmit pulse as detailed in the
table below:

TX22 TXL1 TXL0 Line Build Out
0 0 0 0 to 133 feet/ 0 dB
0 0 1 133 to 266 feet
0 1 0 266 to 399 feet
0 1 1 399 to 533 feet
1 0 0 533 to 655 feet
1 0 1 -7.5 dB
1 1 0 -15 dB
1 1 1 -22.5 dB
After reset these bits are zero.

3 REDBL Receive Equalizer Disable. If one

the receive equalizer is turned off.
If zero, the receive equalizer is
turned on and will compensate for
loop length automatically.

2-0 RES2-0 Receive Equalization Select.

Setting these pins forces a level of
equalization of the incoming line
data.

RES2 RES1 RES0 Receive
Equalization

0 0 0 none
0 0 1 6dB
0 1 0 12dB
0 1 1 18dB
1 0 0 24dB
1 0 1 reserved
1 1 0 reserved
1 1 1 reserved
These settings have no effect if

REDBL is set to zero.

50

Table 36 - LIU Control Word (T1)

(Page 1, Address 1FH)

o

Advance Information MT9074

Master Control 2 (Page 02H) (T1)

Address

(A4A3A2A1A0)

10H (Table 38) Configuration Control Word T1/E1, LIUEn, ADSEQ
11H (Table 39) Custom Tx Pulse Enable CPL
12H Reserved Set all bits to zero for normal operation.
13H Reserved Set all bits to zero for normal operation.
14H Reserved Set all bits to zero for normal operation.
15H Reserved Set all bits to zero for normal operation.
16H Reserved Set all bits to zero for normal operation.
17H Reserved Set all bits to zero for normal operation.
18H Reserved Set all bits to zero for normal operation.
19H Reserved Set all bits to zero for normal operation.
1AH Reserved Set all bits to zero for normal operation.
1BH Reserved Set all bits to zero for normal operation.
1CH (Table 40) Custom Pulse Word 1 CP6-0

Register Names

1DH (Table 41) Custom Pulse Word 2 CP6-0
1EH (Table 42) Custom Pulse Word 3 CP6-0
1FH (Table 43) Custom Pulse Word 4 CP6-0

Table 37 - Master Control 2 (Page 02H) (T1)

51

MT9074 Advance Information

Bit Name Functional Description

7 T1/E1 T1/E1 mode selection. when this

bit is zero, the device is in T1
mode. When set high, the device
is in E1 mode.

6-5 RSV Reserved. Must be kept at 0 for

normal operation.

4 LIUEn LIU Enable. Setting this bit low

enables the internal LIU front-end.
Setting this pin high disables the
LIU. Digital inputs RXA and RXB
are sampled by the rising edge of
E1.5i (C1.50) to strobe in the
received line data. Digital transmit
data is clocked out of pins TXA
and TXB with the rising edge of
C1.5o

3-2 RSV Reserved. Must be kept at 0 for

normal operation.

1 ADSEQ Digital Milliwatt or Digital Test

Sequence. If one, the Alaw digital
milliwatt analog test sequence will
be selected for those channels
with per time slot control bits
TTST, RRST set. If zero, a PRBS
generator / detector will be
connected to channels with TTST,
RRST respectively.

0 RSV Reserved. Must be kept at 0 for

normal operation.

Table 38 - Configuration Control Word

(Page 2, Address 10H) (T1)

Bit Name Functional Description

7 RSV Reserved. Must be kept high for

normal operation.

6-4 RSV Reserved. Must be kept low for normal

operation.

3 CPL Custom Pulse Level. Setting this bit

low enables the internal ROM values in
generating the transmit pulses. The
ROM is coded for different line
terminations or build out, as specified
in the LIU Control word. Setting this bit
high disables the pre-programmed
pulse templates. Each of the 4 phases
that generate a mark derive their D/A
coefficients from the values
programmed in the CPW registers.

2-0 RSV Reserved. Must be kept at 0 for normal

operation.

Table 39 - Custom Tx Pulse Enable

(Page 2, Address 11H) (T1)

Bit Name Functional Description

7 RSV Reserved. Must be kept low for normal

operation.

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the first
phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.

52

Table 40 - Custom Pulse Word 1

(Page 2, Address 1CH) (T1)

Advance Information MT9074

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for normal

operation.

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the
second phase of a mark. The greater
the binary number loaded into the
register, the greater the amplitude
driven out. This feature is enabled
when the control bit 3 - CPL of the
Custom Tx Pulse Enable Register ­address 11H of Page 2 is set high.

Table 41 - Custom Pulse Word 2

(Page 2, Address 1DH) (T1)

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for normal

operation.

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for normal

operation.

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the
fourth phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.

Table 43 - Custom Pulse Word 4

(Page 2, Address 1FH) (T1)

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the
third phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.

Table 42 - Custom Pulse Word 3

(Page 2, Address 1EH) (T1)

53

MT9074 Advance Information

Master Status 1 (Page03H) (T1)

Address

(A4A3A2A1A0)

10H (Table 45) Synchronization Status Word TFSYNC, MFSYNC, SE, LOS
11H (Table 46) Alarm Status Word D4YALM, D4Y48, SECYEL, ESFYEL, BLUE,

12H (Table 47) Timer Status Word 1SEC, 2SEC, 5SEC
13H (Table 48) Most Significant Phase Status Word RSLIP, RSLPD, RxFRM
14H (Table 49) Least Significant Phase Status Word RxTS4-0, RxBC2-0
15H (Table 50) Receive Bit Oriented Message RxBOM7-0
16H (Table 51) Receive Signal Status Word PD4-PD0, LLOS
17H (Table 52) MSB Transmit Slip Buffer TSLIP, TSLPD, TxSBMSB
18H (Table 53) Transmit Slip Buffer Delay TxTS4-0, TxBC2-0
19H - - - Unused.
1AH - - - Unused.
1BH - 1EH - - - Unused.
1FH(Table 54) Identification Register Internally set to 10101111

Register Function

PDV, LLED, LLDD

Table 44 - Master Status 1 (Page 3) (T1)

54

Advance Information MT9074

Bit Name Functional Description

7 TFSYNC Terminal Frame Synchroniza-

tion. Indicates the Terminal

Frame Synchronization status (1

- loss; 0 - acquired). For ESF
links terminal frame synchroni­zation and multiframe synchro­nization are synonymous.

6 MFSYNCMultiframe Synchronization.

Indicates the Multiframe Syn­chronization status (1 - loss; 0 ­acquired). For ESF links multi­frame synchronization and ter­minal frame synchronization are
synonymous.

5SESeverely Errored Frame. This

bit toggles when 2 of the last 6
received framing bits are in
error. The framing bits
monitored are the ESF framing
bits for ESF links, the Ft bits for
SLC-96 links and a combination
of Ft and Fs bits for D4 links
(See Framing Mode Selection
Word - page 1 address 10H).

4 LOS Digital Los Of Signal. This bit

goes high after the detection of
192 consecutive zeros. It returns
low when the incoming pulse
density exceeds 12.5% over a
250 ms period

3 - 0 - - - Unused.

Table 45 - Synchronization Status Word

(Page 3, Address 10H) (T1)

Bit Name Functional Description

7 D4YALM D4 Yellow Alarm. This bit is set if

bit position 2 of virtually every
DS0 channel is a zero for a period
of 600 milliseconds. The alarm is
tolerant of errors by permitting up
to 16 ones in a 48 millisecond
integration period. The alarm
clears in 200 milliseconds after
being removed from the line.

Table 46 - Alarm Status Word

(Page 3, Address 11H) (T1)

Bit Name Functional Description

6 D4Y48 D4 Yellow Alarm - 48

millisecond sample. This bit is

set if bit position 2 of virtually
every DS0 channel is a zero for a
period of 48 milliseconds. The
alarm is tolerant of errors by
permitting up to 16 ones in the
integration period. This bit is
updated every 48 milliseconds.

5 SECYEL Secondary D4 Yellow Alarm.

This bit is set if 2 consecutive ’1’s
are received in the Sbit position of
the 12th frame of the D4
superframe.

4 ESFYEL ESF Yellow Alarm. This bit sets if

the ESF yellow alarm
0000000011111111 is received in
seven or more codewords out of
ten.

3 BLUE Blue Alarm. This bit is set if less

than 6 zeros are received in a 3
millisecond window.

2 PDV Pulse Density Violation. This bit

toggles if RxB8ZS is set high, it
will toggle upon detection of 8
consecutive zeros. If RxB8ZS is
set low, it will toggle upon
detection of 16 consecutive
zeros on the line data, or if there
are less than N ones in a window
of 8(N+1) bits - where N=1 to 23.

1 LLED Line Loopback Enable Detect.

This bit will be set when a framed
or unframed repeating pattern of
00001 has been detected during a
48 millisecond interval. Up to
fifteen errors are permitted per
integration period.

0 LLDD Line Loopback Disable Detect.

This bit will be set when a framed
or unframed repeating pattern of
001 has been detected during a
48 millisecond interval. Up to
fifteen errors are permitted per
integration period.

Table 46 - Alarm Status Word

(Page 3, Address 11H) (T1)

55

MT9074 Advance Information

Bit Name Functional Description

7 1SEC One Second Timer Status. This bit

changes state once every 0.5 seconds.

6 2SEC Two Second Timer Status. This bit

changes state once every second and
is synchronous with the 1SEC timer.

5

5SEC Five Second Timer Status. This bit

changes state once every 2.5 seconds
and is synchronous with the 1SEC
timer.

4-0 - - - Unused.

Table 47 - Timer Status Word

(Page 3, Address 12H) (T1)

Bit Name Functional Description

7 RSLIP Receive Slip. A change of state (i.e.,

1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.

6 RSLPD Receive Slip Direction. If one,

indicates that the last received frame
slip resulted in a repeated frame, i.e.,
the system clock (C4b) is faster than
network clock (E2o). If zero, indicates
that the last received frame slip
resulted in a lost frame, i.e., system
clock slower than network clock.
Updated on an RSLIP occurrence
basis.

5 RxFRM Receive Frame Delay. The most

significant bit of the Receive Slip
Buffer Phase Status Word. If zero, the
delay through the receive elastic
buffer is greater than one frame in
length; if one, the delay through the
receive elastic buffer is less than one
frame in length.

Bit Name Functional Description

7 - 3 RxTS4 - 0 Receive Time Slot. A five bit

counter that indicates the number
of time slots between the receive
elastic buffer internal write frame
boundary and the ST-BUS read
frame boundary. The count is
updated every 250 uS.

2 - 0 RxBC2 - 0 Receive Bit Count. A three bit

counter that indicates the number
of STBUS bit times there are
between the receive elastic buffer
internal write frame boundary and
the ST-BUS read frame boundary.
The count is updated every 250
uS.

Table 49 - Least Significant Phase Status Word

(Page 3, Address 14H) (T1)

Bit Name Functional Description

7 - 0 RxBOM7 - 0 Received Bit Oriented

Message. This register contains

the eight least significant bits of
the ESF bit oriented message
codeword. The contents of this
register is updated when a new
bit - oriented message
codeword has been detected in
8 out of the last ten codeword
positions.

Table 50 - Receive Bit Oriented Message

(Page 3, Address 15H) (T1)

4-0 - - - Unused
Table 48 - Most Significant Phase Status Word

(Page 3, Address 13H) (T1)

56

Advance Information MT9074

Bit Name Functional Description

7 - 3 PD4 -

PD0

Peak Detector Voltage Levels.

These five bits indicate the level of the
received signal AMI pulses.

PD4 PD3 PD2 PD1 PD0 Line Attenuation
0 0 0 0 1 less than 4dB
0 0 0 1 0 3-8dB
0 0 1 0 0 8-14dB
0 1 0 0 0 14-20dB
1 0 0 0 0 more than 20dB

2 LLOS LIU Loss of Signal indication. This

bit will be high when the received
signal is less than 40 dB below the
nominal value for a period of at least 1
msec. This bit will be low for normal
operation.

1-0 - - - Unused

Table 51 - Receive Signal Status Word

(Page 3, Address 16H) (T1)

Bit Name Functional Description

7 TSLIP Transmit Slip. A change of state (i.e.

1-to-0 or 0-to-1) indicates that a
transmit controlled frame slip has
occurred.

Bit Name Functional Description

7 - 3 TxTS4 - 0 Transmit Time Slot. A five bit

counter that indicates the number
of STBUS time slots between the
transmit elastic buffer STBUS write
frame boundary and the internal
transmit read frame boundary. The
count is updated every 250 uS.

2 - 0 TxBC2 - 0 Transmit Bit Count. A three bit

counter indicating the number of
STBUS bit times there are between
the transmit elastic buffer STBUS
write frame boundary and the
internal read frame boundary. The
count is updated every 250 uS.

Table 53 - Transmit Slip Buffer Delay

(Page 3, Address 18H) (T1)

Bit Name Functional Description

7-0 ID7-0 ID Number. Contains device code

10101111

Table 54 - Identification Word

(Page 3, Address 1FH) (T1)

6 TSLPD Transmit Slip Direction. If one,

indicates that the last transmit frame
slip resulted in a repeated frame, i.e.,
the internally generated 1.544 Mhz.
transmit clock is faster than the system
clock (C4b). If zero, indicates that the
last transmit frame slip resulted in a
lost frame, i.e., the internally generated

1.544 Mhz. transmit clock is slower
than network clock. Updated on an
TSLIP occurrence basis.

5 TxSB

MSB

Transmit Slip Buffer MSB. The most
significant bit of the phase status word.
If one, delay through the transmit
elastic buffer is greater than one frame
in length; if zero, delay through the
receive elastic buffer is less than one
frame in length. Bit is reset whenever
page 3 address 17H - Transmit Slip
Buffer Delay - is written to.

4 - 0 - - - Unused.

Table 52 - MSB Transmit Slip Buffer

(Page 3, Address 17H) (T1)

57

MT9074 Advance Information

Master Status 2 (Page04H)(T1)

Address

(A4A3A2A1A0)

10H (Table 56) PRBS Error Counter PS7-0
11H (Table 57) CRC Multiframe counter for PRBS PSM7-0
12H (Table 58) Alarm Reporting Latch D4YALML, D4Y48L, SECYELL, ESFYELL,

13H (Table 59) Framing Bit Counter FC7-0
14H (Table 60) Out of Frame / Change of Frame Alignment

Counters

15H (Table 61) Multiframes Out of Sync Counter MFOOF7-0
16H (Table 62) Most Significant Bipolar Violation Error

Counter

17H (Table 63) Least Significant Bipolar Violation Error

Counter

18H (Table 64) CRC- 6 Error Counter CEt CC15-CC8
19H (Table 65) CRC- 6 Error Counter CEt CC7 - CC0
1AH Unused.

Register Function

BLUEL, PDVL, LLEDL, LLDDL

OOF3-0/COFA3-0

BPV15 - BPV8

BPV7 - BPV0

1BH (Table 66) Interrupt Word Zero TFSYNI, MFSYNI, AISI, LOSI, SEI, TxSLPI,

RxSLPI
1CH (Table 67) Interrupt Word One FEI, CRCI, YELI, COFAI, BPVI, PRBSI, PDVI
1DH (Table 68) Interrupt Word Two FEO, CRCO, OOFO, COFAO, BPVO, PRBSO,

PRBSMFO,MFOOFO
1EH (Table 69) Interrupt Word Three HDLC0I, HDLC1I, LCDI, 1SECI, 5SECI,

BIOMI, SIGI
1FH (Table 70) Overflow Reporting Latch FEOL, CRCOL, OOFOL, COFAOL, BPVOL,

PRBSOL, MFOOFOL

Table 55 - Master Status 2 (Page 4) (T1)

58

Advance Information MT9074

Bit Name Functional Description

7 - 0 PS7-0 This counter is incremented for each

PRBS error detected on any of the
receive channels connected to the
PRBS error detector.

Table 56 - PRBS Error Counter

(Page 4, Address 10H) (T1)

Bit Name Functional Description

7 - 0 PSM7-0 This counter is incremented for each

received CRC multiframe. It is
cleared when the PRBS Error
Counter is written to.

Table 57 - CRC Multiframe Counter for PRBS

(Page 4, Address 11H) (T1)

Bit Name Functional Description

7 D4YALML D4 Yellow Alarm Latch. This bit is

set if a D4 yellow alarm is detected
within a 600 millisecond integration
period. It is cleared after a read.

6 D4Y48L D4 Yellow Alarm (48

milliseconds) Latch. This bit is
set if a D4 yellow alarm is detected
within a 48 millisecond integration
period. It is cleared after a read.

5 SECYELL Secondary D4 Yellow Alarm

Latch. This bit is set if an alternate
D4 (S bit in 12 th frame) is
detected. It is cleared after a read.

4 ESFYELL ESF Yellow Alarm Latch. This bit

is set upon receipt of a ESF yellow
alarm. It is cleared after a read.

3 BLUEL Blue Alarm Latch. This bit is set

upon receipt of a blue alarm. It is
cleared after a read.

2 PDVL Pulse Density Violation Latch.

This bit is set upon receipt of a
pulse density violation. It is cleared
after a read.

1 LLEDL Line Loopback Enable Detect

Latch. This bit is set upon receipt
of a line loopback enable code. It is
cleared after a read.

0 LLDDL Line Loopback Disable Detect

Latch. This bit is set upon receipt
of a line loopback disable code. It
is cleared after a read.

Table 58 - Alarm Reporting Latch

(Page 4, Address 12H) (T1)

Bit Name Functional Description

7 - 0 FC7 - 0 Framing Bit Counter. This eight bit

counter will be incremented for each
error in the received framing pattern.
In ESF mode the ESF framing bits
are monitored. In D4 mode Fs bits
may be monitored as well as Ft bits.
See - Section 15.5 Framing Bit
Counter. The count is only active if
the MT9074 is in synchronization.

Table 59 - Framing Bit Counter

(Page 4, Address 13H) (T1)

59

MT9074 Advance Information

Bit Name Functional Description

7 - 4 OOF3 - 0 Out Of Frame Counter. This four

bit counter is incremented with
every loss of receive frame
synchronization.

3 - 0 COFA3 - 0 Change of Frame Alignment

Counter. This four bit counter is
incremented if a
resynchronization is done which
results in a shift in the frame
alignment position.

Table 60 - Out Of Frame / Change of Frame

Alignment Counter

(Page 4, Address 14H) (T1)

Bit Name Functional Description

7 - 0 MFOO

F7 - 0

Table 61 - Multiframes Out of Sync Counter

Multiframes Out of
Synchronization Counter. This

eight bit counter will be incremented
once for every multiframe (1.5
milliseconds in D4 mode, 3
milliseconds in ESF mode) in which
basic frame synchronization is lost.

(Page 4, Address 15H) (T1)

Bit Name Functional Description

7 - 0 BPV7 - 0 Least Significant Bits of the BPV

Counter. The least significant eight

bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.

Table 63 - Least Significant Bits of the BPV

Counter

(Page 4, Address 17H) (T1)

Bit Name Functional Description

7 - 0 CC15 - 8 CRC-6 Error Counter Bits Fifteen

to Eight. These are the most

significant eight bits of the CRC-6
error counter.

Table 64 - CRC-6 Error Counter

(Page 4, Address 18H) (T1)

Bit Name Functional Description

7 - 0 CC7 - 0 CRC-6 Error Counter Bits Seven

to Zero. These are the least

significant eight bits of the CRC-6
error counter.

Bit Name Functional Description

7 - 0 BPV15 - 8 Most Significant Bits of the BPV

Counter. The most significant

eight bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.

Table 62 - Most Significant Bits of the BPV

Counter

(Page 4, Address 16H) (T1)

Table 65 - CRC-6 Error Counter

(Page 4, Address 19H) (T1)

60

Advance Information MT9074

Bit Name Functional Description

7 TFSYNI Terminal Frame Synchronization

Interrupt. When unmasked this

interrupt bit goes high whenever a
change of state of terminal frame
synchronization condition exists.
Reading this register clears this bit.

6 MFSYNI Multiframe Synchronization

Interrupt. When unmasked this
interrupt bit goes high whenever a
change of state of multiframe
synchronization condition exists.

Reading this register clears this bit.
5 - - - Unused.
4 AISI Alarm Indication Signal Interrupt.

When unmasked this interrupt bit

goes high whenever a change of

state of received all ones condition

exists. Reading this register clears

this bit.
3 LOSI Loss of Signal Interrupt. When

unmasked this interrupt bit goes

high whenever a change of state of

loss of signal (either analog - signal

40 dB below nominal or digital - 192

consecutive 0’s received) condition

exists. Reading this register clears

this bit.
2 SEI Severely Errored Frame Interrupt.

When unmasked this interrupt bit

goes high whenever a sequence of

2 framing errors out of 6 occurs.

Reading this register clears this bit.

Bit Name Functional Description

7 FEI Framing Bit Error Interrupt. When

unmasked this interrupt bit goes high
whenever an erroneous framing bit is
detected (provided the circuit is in
terminal frame sync). Reading this
register clears this bit.

6 CRCI CRC-6 Error Interrupt. When

unmasked this interrupt bit goes high
whenever a local CRC-6 error occurs.
Reading this register clears this bit.

5 YELI Yellow Alarm Interrupt. When

unmasked this interrupt bit goes high
upon detection of a yellow alarm.
Reading this register clears this bit.

4 COFAI Change of Frame Alignment

Interrupt. When unmasked this
interrupt bit goes high whenever a
change of frame alignment occurs
after a reframe. Reading this register
clears this bit.

3 BPVI Bipolar Violation Interrupt. When

unmasked this interrupt bit goes high
whenever a bipolar violation
(excluding B8ZS encoding) is
encountered. Reading this register
clears this bit.

2 PRBSI Psuedo Random Bit Sequence

Error Interrupt. When unmasked this
interrupt bit goes high upon detection
of an error with a channel selected for
PRBS testing. Reading this register
clears this bit.

1 TxSLPI Transmit SLIP Interrupt. When

unmasked this interrupt goes high

whenever a controlled frame slip

occurs in the transmit elastic buffer.

Reading this register clears this bit.
0 RxSLPI Receive SLIP Interrupt. When

unmasked this interrupt bit goes

high whenever a controlled frame

slip occurs in the receive elastic

buffer. Reading this register clears

this bit.

Table 66 - Interrupt Word Zero

(Page 4, Address 1BH) (T1)

1 PDVI Pulse Density Violation Interrupt.

When unmasked this interrupt bit goes
high whenever in the absence of B8ZS
coding a sequence of 16 consecutive
zeros is received on the line, or the
incoming pulse density is less than N
ones in a time frame of 8(N+1) where
N = 1 to 23. In the case of B8ZS
coding, the interrupt is set upon
detection of 8 consecutive zeros.
Reading this register clears this bit.

0 - - - Unused.

Table 67 - Interrupt Word One

(Page 4, Address 1CH) (T1)

61

MT9074 Advance Information

Bit Name Functional Description

7 FEO Framing Bit Error Counter

Overflow Interrupt. When

unmasked this interrupt bit
goes high whenever the
framing bit error counter
changes from FFH to 00H.
Reading this register clears this
bit.

6 CRCO CRC-6 Error Counter

Overflow Interrupt. When
unmasked this interrupt bit
goes high whenever the CRC-6
error counter changes from
FFH to 00H. Reading this
register clears this bit.

5 OOFO Out Of Frame Counter

Overflow Interrupt. When
unmasked this interrupt bit
goes high whenever the out of
frame counter changes state
from changes from FFH to
00H. Reading this register
clears this bit.

Bit Name Functional Description

1 PRBSMFO Psuedo Random Bit

Sequence Multiframe
Counter Overflow Interrupt.

When unmasked this interrupt
bit goes high whenever the
multiframe counter attached to
the PRBS error counter
overflows. FFH to 00H. 1 ­unmasked, 0 - masked.

0 MFOOFO Multiframes Out Of Sync

Overflow Interrupt. When
unmasked this interrupt bit
goes high whenever the
multiframes out of frame
counter changes from FFH to
00H. Reading this register
clears this bit.

Table 68 - Interrupt Word Two

(Page 4, Address 1DH) (T1)

4 COFAO Change of Frame Alignment

Counter Overflow Interrupt.

When unmasked this interrupt
bit goes high whenever the
change of frame alignment
counter changes from FFH to
00H. Reading this register
clears this bit.

3 BPVO Bipolar Violation Counter

Overflow Interrupt. When
unmasked this interrupt bit
goes high whenever the bipolar
violation counter changes from
FFH to 00H. Reading this
register clears this bit.

2 PRBSO Psuedo Random Bit

Sequence Error Counter
Overflow Interrupt. When

unmasked this interrupt bit
goes high whenever the PRBS
error counter changes from
FFH to 00H. Reading this
register clears this bit.

62

Table 68 - Interrupt Word Two

(Page 4, Address 1DH) (T1)

Advance Information MT9074

Bit Name Functional Description

7 - - - Unused.
6 HDLC0I HDLC0 Interrupt. Whenever an

unmasked HDLC0 interrupt occurs
(from the 4 kHz data link) this bit
goes high. Reading this register
clears this bit.

5 HDLC1I HDLC1 Interrupt. Whenever an

unmasked HDLC1 interrupt occurs
(from the DS1 channel 24
signalling channel) this bit goes
high. Reading this register clears
this bit.

4 LCDI Loop Code Detected Interrupt.

When unmasked this interrupt bit
goes high whenever either the
loop up (00001) or loop down
(001) code has been detected on
the line for a period of 48
milliseconds. Reading this register
clears this bit.

3 1SECI One Second Status Interrupt.

When unmasked this interrupt bit
goes high whenever the 1SEC
status bit (page 3 address 12H bit

7) goes from low to high. Reading
this register clears this bit.

Bit Name Functional Description

1 BIOMI Bit Oriented Message Interrupt.

When unmasked this interrupt bit
goes high whenever a pattern
111111110xxxxxx0 has been
received on the FDL that is
different from the last message.
The new message must persist for
8 out the last 10 message
positions to be accepted as a valid
new message. Reading this
register clears this bit.

0 SIGI Signalling Interrupt. When

unmasked this interrupt bit goes
high whenever a change of state
(optionally debounced - see DBEn
in the Data Link, Signalling Control
Word page 1 address 12H) is
detected in the signalling bits (AB
or ABCD) pattern. Reading this
register clears this bit.

Table 69 - Interrupt Word Three

(Page 4, Address 1EH) (T1)

2 5SECI Five Second Status Interrupt.

When unmasked this interrupt bit
goes high whenever the 5 SEC
status bit goes from low to high.
Reading this register clears this
bit.

Table 69 - Interrupt Word Three

(Page 4, Address 1EH) (T1)

63

MT9074 Advance Information

Bit Name Functional Description

7 FEOL Framing Bit Error

Counter Overflow Latch.

This bit is set when the
framing bit counter
overflows. It is cleared after
being read.

6 CRCOL CRC-6 Error Counter

Overflow Latch. This bit is
set when the crc error
counter overflows. It is
cleared after being read.

5 OOFOL Out Of Frame Counter

Overflow Latch. This bit is
set when the out of frame
counter overflows. It is
cleared after being read.

4 COFAOL Change of Frame

Alignment Counter
Overflow Latch. This bit is

set when the change of
frame alignment counter
overflows. It is cleared after
being read.

3 BPVOL Bipolar Violation

Counter Overflow Latch.
This bit is set when the
bipolar violation counter
overflows. It is cleared after
being read.

2 PRBSOL Psuedo Random Bit

Sequence Error Counter
Overflow Latch. This bit is

set when the PRBS error
counter overflows. It is
cleared after being read.

1 PRBSMFOFOL Psuedo Random Bit

Sequence Multiframe
Counter Overflow Latch.

This bit is set when the
multiframe counter
attached to the PRBS error
counter overflows. It is
cleared after being read

0 MFOOFOL Multiframes Out Of Sync

Overflow Latch. This bit is
set when the multiframes
out of sync counter
overflows. It is cleared after
being read.

64

Table 70 - Overflow Reporting Latch

(Page 4, Address 1FH) (T1)

Advance Information MT9074

Per Channel Transmit Signalling (Pages 5 and 6) (T1)

Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit
Signalling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 107 illustrates the mapping
between the addresses of these pages and the DS1 channel numbers. Control of these bits for any one
channel is through the processor or controller port when the Per Time Slot Control bit RPSIG bit is high. Table
72 describes bit allocation within each of these registers.

Page 5-6 Address: 0123456789101112131415
Equivalent DS1

channel
Page 6 Address: 0123456789101112131415
Equivalent DS1

channel

Bit Name Functional Description

7 - 4 - - - Unused.

3 A(n) Transmit Signalling Bits A for Channel n. Where signalling is enabled, these bits

2 B(n) Transmit Signalling Bits B for Channel n. Where signalling is enabled, these bits

12345678910111213141516

1718192021222324xxxxxxxx

Table 71 - Page 5, 6 Address Mapping to DS1 Channels (T1)

are transmitted in bit position 8 of the 6th DS1 frame (within the 12 frame
superframe structure for D4 superframes and the 24 frame structure for ESF
superframes).

are transmitted in bit position 8 of the 12th DS1 frame (within the 12 frame
superframe structure for D4 superframes and the 24 frame structure for ESF
superframes).

1 C(n) Transmit Signalling Bits C for Channel n. Where signalling is enabled, these bits

are transmitted in bit position 8 of the 18th DS1 frame within the 24 frame structure
for ESF superframes. In D4 mode these bits are unused.

0 D(n) Transmit Signalling Bits D for Channel n. Where signalling is enabled, these bits

are transmitted in bit position 8 of the 24th DS1 frame within the 24 frame structure
for ESF superframes. In D4 mode these bits are unused.

Table 72 - Transmit Channel Associated Signalling (T1) (Pages 5,6)

Serial per channel transmit signalling control through CSTi is selected when the Per Time Slot Control bit
RPSIG bit is low. Table 71 describes the bit allocation within each of the 24 active ST-BUS time slots of CSTi.

65

MT9074 Advance Information

Bit Name Functional Description

7 - 4 A(n),

B(n)

C(n),

D(n)

3 - 0 A(n),

B(n),
C(n),

D(n)

NOTE: This table illustrates bit mapping on the serial input stream - it does not refer to an internal register.

Per Time Slot Control Words)(Pages 7 and 8) (T1)

The control functions described by Table 75 are repeated for each DS1 time slot. Page 7 addresses 10000 to
11111 correspond to DS1 time slot 1 to 16, while page 8 addresses 10000 to 10111 correspond to time slots
17 to 24. Table 74 illustrates the mapping between the addresses of these pages and the DS1 channel
numbers.

Page 7 Address: 0123456789101112131415

Transmit Signalling Bits for Channel n. When control bit MSN = 1 and RPSIG =
1 this nibble is used. For ESF links these 4 bits are transmitted on the associated
DS1 channel (see table 8) in frames 6, 12, 18 and 24. For D4 links bits A are
transmit on the associated DS1 channel of frame 6 and bits B are transmit on the
associated DS1 channel of frame 12. For D4 links bits C and D are unused.

Transmit Signalling Bits for Channel n. When control bit MSN = 0 and RPSIG =
1 this nibble is used. For ESF links these 4 bits are transmitted on the associated
DS1 channel (see table 8) in frames 6, 12, 18 and 24. For D4 links bits A are
transmit on the associated Ds1 channel of frame 6 and bits B are transmit on the
associated DS1 channel of frame 12. For D4 links bits C and D are unused.

Table 73 - T1 / Transmit Channels Usage - CSTi

Equivalent DS1
channel

Page 8 Address: 0123456789101112131415
Equivalent DS1

channel

12345678910111213141516

1718192021222324xxxxxxxx

Table 74 - Pages 7 and 8 Address Mapping to DS1 Channels

66

Advance Information MT9074

Bit Name Functional Description

7 TXMSG Transmit Message Mode . If high,

the data contained in the Transmit
Message Register (address 18H,
page 1) is transmitted in the
corresponding DS1 time slot. If
zero, the data on DSTi is
transmitted on the corresponding
DS1 time slot.

6 PCI Per Channel Inversion. When set

high the data for this channel
sourced from DSTi is inverted
before being transmit onto the
equivalent DS1 channel; the data
received from the incoming DS1
channel is inverted before it
emerges from DSTo.

5 RTSL Remote Time Slot Loopback. If

one, the corresponding DS1
receive time slot is looped to the
corresponding DS1 transmit time
slot. This received time slot will
also be present on DSTo. If zero,
the loopback is disabled.

Bit Name Functional Description

1 RPSIG Serial Signaling Enable. If set

low, the transmit signaling buffer
for the equivalent DS1 channel will
be sourced from the ST-BUS
channel on CSTi associated with
it. If set high the transmit signaling
RAM must be programmed via the
microport.

0CCClear Channel. When set high no

robbed bit signaling is inserted in
the equivalent transmit DS1
channel. When set low robbed bit
signaling is included in every 6th
channel.

Table 75 - Per Time Slot Control Words

(Pages 7 and 8) (T1)

4 LTSL Local Time Slot Loopback. If

one, the corresponding transmit
time slot is looped to the
corresponding receive time slot.
This transmit time slot will also be
present on the transmit DS1
stream. If zero, this loopback is
disabled.

3 TTST Transmit Test. If one, a test

signal, either digital milliwatt (when
control bit ADSEQ is one) or
PRBS (Z15-1) (ADSEQ is zero),
will be transmitted in the
corresponding DS1 time slot. More
than one time slot may be
activated at once. If zero, the test
signal will not be connected to the
corresponding time slot.

2 RTST Receive Test. If one, the

corresponding DSTo time slot will
be used for testing. If control bit
ADSEQ is one, a digital milliwatt
signal will be transmitted into the
DSTo channel. If ADSEQ is zero,
the receive channel will be
connected to the PRBS (215 - 1)
detector.

Table 75 - Per Time Slot Control Words

(Pages 7 and 8) (T1)

67

MT9074 Advance Information

Per Channel Receive Signalling (T1 and E1 mode) (Pages 9 and 0AH)

Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive
Signalling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 76 illustrates the mapping
between the addresses of these pages and the DS1 channel numbers. Table 77 describes bit allocation within
each of these registers.

Page 9 Address: 0123456789101112131415
Equivalent DS1

channel
Page A Address: 0123456789101112131415
Equivalent DS1

channel

Bit Name Functional Description

7 - 4 - - - Unused

3 A(n) Receive Signalling Bits A for Channel n. These bits are extracted from bit

3 B(n) Receive Signalling Bits B for Channel n. These bits are extracted from bit

12345678910111213141516

1718192021222324xxxxxxxx

Table 76 - Page 9, A Address Mapping to DS1 Channels (T1)

position 8 of every channel in received frame 6 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.

position 8 of every channel in received frame 12 (within the 12 frame superframe
structure for D4 superframes and the 24 frame structure for ESF superframes). The
bits may be debounced for 6 to 9 milliseconds where control bit DBNCE is set high.

2 C(n) Receive Signalling Bits C for Channel n. These bits are extracted from bit

position 8 of every channel in received frame 18 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.

0 D(n) Receive Signalling Bits D for Channel n. These bits are extracted from bit

position 8 of every channel in received frame 24 within the 24 frame structure for
ESF superframes. The bits reported may be debounced for 6 to 9 milliseconds
where control bit DBNCE is set high. In D4 mode these bits are unused.

Table 77 - Receive Channel Associated Signalling (Pages 9 and A) (T1)

68

Advance Information MT9074

E1 Mode

Master Control 1 (Page 01H) (E1)

Address

(A4A3A2A1A0)

10H (Table 79) Mode Selection Control Word ASEL, CRCM, AUTC, ARAI, AUTY, CSYN,

11H (Table 80) Transmit Alarm Control Word TE, TAIS16, TxAO
12H (Table 81) HDLC Selection Word HDLC0, HDLC1, RxTRSP, TxTRSP, TIU1,TIU0
13H (Table 82) Transmit Multiframe Alignment Signal TMA1-4,X1,Y, X2, X3
14H (Table 83) Interrupt and Signalling Control Word DstoEn, CSToEn, TxCCS, DBNCE, MSN
15H (Table 84) Coding and Loopback Control Word RxHDB3, MLBK, HDB3, DLBK, RLBK, SLBK,

16H (Table 85) Non Frame Alignment Control Word RxNFA, TALM, TNU4-8
17H (Table 86) Multiframe and Data Link Selection MFSEL, Sa4-Sa8
18H (Table 87) Transmit Message Word TXM7-0
19H (Table 88) Error Insertion Word BPVE, CRCE, FASE, NFSE, LOSE, PERR,

1AH (Table 89) Signalling Control Word RST, SPND, INTA, CNTCLR, SAMPLE,

Register Function

REFRM, MFRF

PLBK

LOS/LOF

EXTOSC, GCI/ST

1BH (Table 90) Interrupt Mask Word Zero SYNIM, MFSYIM, CSYNIM, AISIM, LOSIM,

CEFIM, YIM, SLPIM

1CH (Table 91) Interrupt Mask Word One FERIM, CRCIM, EBIM, AIS16IM, BPVIM,

PRBSIM, AUXPIM & RAI

1DH (Table 92) Interrupt Mask Word Two FEOM, CRCOM, EOM, BPVOM, PRBSOM,

PRBSMFO
1EH (Table 93) Interrupt Mask Word Three JAIM,1SECIM, 5SECIM, RCRIM, SIGIM
1FH (Table 94) LIU Control Word NRZUNI, REDBL, REMID, REMAX

Table 78 - Master Control 1 (Page 1) (E1)

69

MT9074 Advance Information

Bit Name Functional Description

7 ASEL AIS Select. This bit selects the

criteria on which the detection of a
valid Alarm Indication Signal (AIS)
is based. If zero, the criteria is less
than three zeros in a two frame
period (512 bits). If one, the criteria
is less than three zeros in each of
two consecutive double-frame
periods (512 bits per double
frame).

6 CRCM CRC-4 Modification. If one

activates the CRC-4 remainder
modification function when the
device is in transparent mode. The
received CRC-4 remainder is
modified to reflect only the
changes in the transmit DL. If zero,
time slot zero data from DSTi will
not be modified in transparent
mode.

5 AUTC Automatic CRC-interworking. If

zero, automatic CRC-interworking
is activated. If one it is
deactivated. See Framing
Algorithm for a detailed
description.

4 ARAI Automatic Remote Alarm

Indication. if zero, the Remote
Alarm Indication bit (the A bit) will
function automatically. That is,
RAI=1 when basic synchronization
has been acquired. And, RAI=0
when basic synchronization has
not been acquired. if one, the
remote alarm indication bit is
controlled through the TALM bit of
the transmit Non-Frame Alignment
Control Word.

3 AUTY Automatic Y-Bit Operation. If

zero, the Y-bit of the transmit
multiframe alignment signal will
report the multiframe alignment
status to the far end i.e., zero ­multiframe alignment acquired,
one - lost. If one, the Y-bit is under
the manual control of the Transmit
Multiframe Alignment Control
Word.

Table 79 - Mode Selection Control Word (E1)

(Page 1, Address 10H)

Bit Name Functional Description

2 CSYN CRC-4 Synchronization. If zero,

basic CRC-4 synchronization
processing is activated, and the
TIU0 Bit and the TIU1 bit
programming will be overwritten.
If one, CRC-4 synchronization is
disabled. If AUTC (Page 1,
Address 10H, bit 5) is also one
then the first bits of channel 0 are
used as international use bits and
are programmed by the TIU0 and
TIU1.

1 REFRM Reframe. If one for at least one

frame, and then cleared, the
device will initiate a search for a
new basic frame position.
Reframing function is activated on
the one to zero transition of the
REFRM bit.

0 MFRF Multiframe Reframe. If one, for at

least one frame, and then cleared
the MT9074 will initiate a search
for a new signalling multiframe
position. Reframing function is
activated on the one to zero
transition of the MFRM bit.

Table 79 - Mode Selection Control Word (E1)

(Page 1, Address 10H)

Bit Name Functional Description

7 - - - Unused
6TETransmit E bits. When zero and

CRC-4 synchronization is achieved,
the E-bits transmit the received CRC­4 comparison results to the distant
end of the link, as per G.703. That is,
when zero and CRC-4
synchronization is lost, the transmit E­bits will be zero. If one, and CRC-4
synchronization is lost the transmit E­bits will be one.

5 TAIS16 Transmit AIS Time Slot 16. If one, an

all ones signal is transmitted in time
slot 16. If zero, time slot functions
normally.

4 TxAO Transmit All Ones. When low, this

control bit forces an unframed all ones
to be transmit at TTIP and TRING.

70

Table 80 - Transmit Alarm Control Word (E1)

(Page 1, Address 11H)

Advance Information MT9074

Bit Name Functional Description

3-0 - - - Unused

Table 80 - Transmit Alarm Control Word (E1)

(Page 1, Address 11H)

Bit Name Functional Description

7 - - - Unused.
6 - - - Unused.
5 HDLC0 HDLC0 Select. If one, then

HDLC0 is connected to the data
link on selected Sa bits at a rate of
4, 8, 12, 16 or 20 kbits/sec. If zero,
HDLC0 is deselected and all
HDLC0 interrupts are masked.

4 HDLC1 HDLC1 Select. If one, then

HDLC1 is connected to time slot
16 in CCS mode. If zero, HDLC1 is
deselected and all HDLC1
interrupts are masked.

3 RxTRSP Receive Transparent Mode.

When this bit is set to one, the
framing function is disabled on the
receive side. Data coming from the
receive line passes through the
slip buffer and drives DSTo with an
arbitrary alignment. When zero,
the receive framing function
operates normally.

2 TxTRSP Transmit Transparent Mode. If

one, the MT9074 is in transmit
transparent mode. No framing or
signaling is imposed on the data
transmit from DSTi onto the line. If
zero, it is in termination mode.

1 TIU1 Transmit International Use One.

When CRC-4 operation is disabled
(CSYN=1), this bit is transmit on
the PCM 30 2048 kbit/sec. link in
bit position one of time-slot zero of
non-frame-alignment frames. It is
reserved for international use and
should normally be kept at one. If
CRC processing is used, i.e.,
CSYN =0, this bit is ignored.

Bit Name Functional Description

0 TIU0 Transmit International Use Zero.

When CRC-4 operation is disabled
(CSYN=1), this bit is transmit on
the PCM 30 2048 kbit/sec. link in
bit position one of time-slot zero of
frame-alignment frames. It is
reserved for international use and
should normally be kept at one. If
CRC processing is used, i.e.,
CSYN =0, this bit is ignored.

Table 81 - HDLC Selection Word (E1)

(Page 1, Address 12H)

Bit Name Functional Description

7-4 TMA1-4 Transmit Multiframe Alignment

Bits One to Four. These bits are

transmitted on the PCM 30 2048
kbit/sec. link in bit positions one to
four of time slot 16 of frame zero
of every signalling multiframe.
These bits are used by the far end
to identify specific frames of a
signalling multiframe. TMA1-4 =
0000 for normal operation.

3 X1 This bit is transmitted on the PCM

30 2048 kbit/sec. link in bit
position five of time slot 16 of
frame zero of every multiframe.
X1 is normally set to one.

2 Y This bit is transmitted on the PCM

30 2048 kbit/sec. link in bit
position six of time slot 16 of
frame zero of every multiframe. It
is used to indicate the loss of
multiframe alignment to the
remote end of the link. If one ­loss of multiframe alignment; if
zero - multiframe alignment
acquired. This bit is ignored when
AUTY is zero (page 01H, address
10H).

Table 82 - Transmit Multiframe Alignment

Signal (E1)

(Page 1, Address 13H)

Table 81 - HDLC Selection Word (E1)

(Page 1, Address 12H)

71

MT9074 Advance Information

Bit Name Functional Description

1- 0 X2, X3 These bits are transmitted on the

PCM 30 2048 kbit/sec. link in bit
positions seven and eight
respectively, of time slot 16 of
frame zero of every multiframe.
X2 and X3 are normally set to
one. If receive channel 16 data is
to be included in the looped data
then the control bit TxCCS (Page,
Address 14H, bit 5) must be set
high, otherwise transmit signaling
data, or HOLCC data will be
placed into the outgoing channel
16 timeslot.

Table 82 - Transmit Multiframe Alignment

Signal (E1)

(Page 1, Address 13H)

Bit Name Functional Description

7 DSToEn DSTo Enable. If zero pin DSTo is

tristate. If set, the pin DSTo is
enabled.

6 CSToEn CSTo Enable. If zero pin CSTo is

tristate. If set, the pin CSTo is
enabled.

5 TxCCS Transmit Common Channel

Signalling. If one, the transmit
section of the device is in common
channel signalling (CCS) mode. If
zero, it is in Channel Associated
Signalling (CAS) mode.

4 DBNCE, Debounce Select. This bit selects

the debounce period (1 for 14
msec.; 0 for no debounce). Note:
there may be as much as 2 msec.
added to this duration because
the state change of the signalling
equipment is not synchronous
with the PCM 30 signalling
multiframe.

Table 83 - Interrupt and Signalling Control Word

(E1)

(Page 1, Address 14H)

Bit Name Functional Description

3 MSN Most Significant Signalling

Nibble. If one, the CSTo and

CSTi channel associated
signalling nibbles will be valid in
the most significant portion of
each ST-BUS time slot. If zero,
the CSTo and CSTi channel
associated signalling nibbles will
be valid in the least significant
portion of each ST-BUS time slot.

2-0 - - - Unused.

Table 83 - Interrupt and Signalling Control Word

(E1)

(Page 1, Address 14H)

Bit Name Functional Description

7 RxHDB3 High Density Bipolar 3 Encoding. If

one, HDB3 encoding is enabled in
the receive direction. If zero, AMI
signal without HDB3 encoding is
received

6 MLBK Metallic Loopback. If one, then the

external RRTIP and RRING signals
are isolated from the receiver, and
TTIP and TRING are internally
connected to the receiver analog
input instead. If zero, metallic
loopback is disabled.

5 TxHDB3 High Density Bipolar 3 Encoding. If

one, HDB3 encoding is enabled in
the transmit direction. If zero, AMI
signal without HDB3 encoding is

transmitted.
4 - - - Unused.
3 DLBK Digital Loopback. If one, then the

digital stream to the transmit LIU is

looped back in place of the digital

output of the receive LIU. Data

coming out of DSTo will be a delayed

version of DSTi. If zero, this feature is

disabled.

Table 84 - Coding and Loopback Control Word

(E1)

(Page 1, Address 15H)

72

Advance Information MT9074

Bit Name Functional Description

2 RLBK Remote Loopback. If one, then all

bipolar data received on RRTIP/
RRING are directly routed to TTIP/
TRING on the PCM 30 side of the
MT9074. If zero, then this feature is
disabled.

1 SLBK ST-BUS Loopback. If one, then all

time slots of DSTi are connected to
DSTo on the ST-BUS side of the
MT9074. If zero, then this feature is
disabled. See Loopbacks section.

0 PLBK Payload Loopback. If one, then all

time slots received on RTIP/RRING
are connected to TTIP/TRING on the
ST-BUS side of the MT9074 (this
excludes time slot zero). If zero, then
this feature is disabled. If receive
channel 16 data is to be included in
the looped data, then the control bit
TxCCS (Page 1, Address 14H, bit 5)
must be set high, otherwise transmit
signalling data, or HDLC1 data will
be placed into the outgoing channel
16 timeslot.

Table 84 - Coding and Loopback Control Word

(E1)

(Page 1, Address 15H)

Bit Name Functional Description

7 - - - Unused.
6 RxNFA Receive Non-frame Alignment

Byte. This bit decides the
contents of channel 0 of DSTo.
When RxNFA=1, channel 0 of
DSTo contains only data from the
received non frame alignment
signal (NFAS). When RxNFA = 0,
channel 0 of DSTo contains both
frame alignment and non frame
alignment bytes received with the
rest of the frame.

Bit Name Functional Description

5 TALM Transmit Remote Alarm. This bit

is transmitted on the PCM 30
2048 kbit/sec. link in bit position
three (A bit) of time slot zero of
NFAS frames. It is used to signal
an alarm to the remote end of the
PCM 30 link (one - alarm, zero ­normal). This control bit is ignored
when ARAI is zero (page 01H,
address 10H).

4-0 TNU4-8 Transmit National Use Four to

Eight (Sa4 - Sa8). These bits are
transmitted on the PCM 30 2048
kbit/sec. link in bit positions four to
eight of time slot zero of the NFA
frame, if selected by Sa4 - Sa8
control bits of the DL selection
word (page 01H, address 17H).

Table 85 - Non Frame Alignment Control Word

(E1)

(Page 1, Address 16H)

Bit Name Functional Description

7 - - - Unused
6 MFSEL Multiframe Select. This bit

determines which receive
multiframe signal (CRC-4 or
signalling) the RxMF (pin 42 in
PLCC, 23 in MQFP) signal is
aligned with. If zero, RxMF is
aligned with the receive signalling
multiframe. If one, RxMF is aligned
with the receive CRC-4
multiframe.

5 - - - - Unused

Table 86 - Multiframe and Data Link Selection

(E1)

(Page 1, Address 17H)

Table 85 - Non Frame Alignment Control Word

(E1)

(Page 1, Address 16H)

73

MT9074 Advance Information

Bit Name Functional Description

4-0 Sa4-

Sa8

Table 86 - Multiframe and Data Link Selection

Bit Name Functional Description

7-0 TxM7-0 Transmit Message Bits 7 - 0. The

Table 87 - Transmit Message Word (E1)

Bit Name Functional Description

7 BPVE Bipolar Violation Error

6 CRCE CRC-4 Error Insertion. A zero to

A one selects the corresponding
Sa bits of the NFA signal for 4, 8,
12, 16 or 20 kbits/sec. data link
channel. Data link (DL) selection
will function in termination mode
only; in transmit transparent mode
Sa4 is automatically selected - see
TxTRSP control bit of page 01H,
address 11H. If zero, the
corresponding bits of transmit non­frame alignment signal are
programmed by the Non-Frame
Alignment Control Word (page
01H, address 16H).

(E1)

(Page 1, Address 17H)

contents of this register are transmit
into those outgoing DS1 channels
selected by the Per Time Slot Control
registers.

(Page 1, Address 18H)

Insertion. A zero to one transition

of this bit inserts a single bipolar
violation error into the transmit
PCM 30 data. A one, zero or one
to zero transition has no function.

one transition of this bit inserts a
single CRC-4 error into the
transmit PCM 30 data. A one,
zero, or one to zero transition has
no function.

Bit Name Functional Description

4 NFSE Non-frame Alignment Signal

Error Insertion. A zero to one

transition of this bit inserts a single
error into bit two of the time slot
zero non-frame alignment signal of
the transmit PCM 30 data. A one,
zero, or one to zero transition has
no function.

3 LOSE Loss of Signal Error Insertion. If

one, the MT9074 transmits an all
zeros signal (no pulses) in every
PCM 30 time slot. When HDB3
encoding is activated no violations
are transmitted. If zero, data is
transmitted normally.

2 PERR Payload Error Insertion. A zero

to one transition of this bit inserts a
single error in the transmit
payload. A one, zero, or one to

zero transition has no function.
1 - - - Unused
0 LOS/

LOF

Table 88 - Error Insertion Word (E1)

Loss of Signal or Loss of Frame

Selection. If one, pin LOS (pin 61

in PLCC, 57 in MQFP) will go high

when a loss of signal state exits. A

loss of signal is defined as either

receipt of a signal attenuated

below the analog loss of signal

threshold (selectable as 20 dB or

40 dB below nominal) or receipt

of 192 consecutive 0’s. If low, pin

LOS will go high when either a

loss of signal or a loss of basic

frame alignment state exits (bit

SYNC on page 03H address 10H

is zero).

(Page 1, Address 19H)

5 FASE Frame Alignment Signal Error

Insertion. A zero to one transition

of this bit inserts a single error into
the time slot zero frame alignment
signal of the transmit PCM 30
data. A one, zero, or one to zero
transition has no function.

Table 88 - Error Insertion Word (E1)

(Page 1, Address 19H)

74

Advance Information MT9074

Bit Name Functional Description

7 RST Reset. When this bit is changed

from zero to one the device will
reset to its default mode. See the
Reset Operation section for the
default settings.

6 SPND Suspend Interrupts. If one, the

IRQ output (pin 12 in PLCC, 85 in
MQFP) will be in a high-impedance
state and all interrupts will be
ignored. If zero, the IRQ output will
function normally.

5 INTA Interrupt Acknowledge. A zero-to-

one or one-to-zero transition will
clear any pending interrupt and
make IRQ high impedance.

4 CNTCLR Counter Clear. If one, all status

counters are cleared and held low.
Zero for normal operation.

3 SAMPLE One Second Sample. Setting this

bit causes the error counters
(change of frame alignment, loss of
frame alignment, bpv errors, crc
errors, severely errored frame
events and multiframes out of sync)
to be updated on one second
intervals coincident with the one
second timer (status page 3
address 12H bit 7).

2 EXTOSC External Oscillator Select. Setting

this bit connects the pin OSC1 to a
TTL compatible input. This allows
for a system design employing a
TTL output oscillator as a 20.000
Mhz reference clock.

Bit Name Functional Description

7 SYNIM Synchronization Interrupt

Mask. When unmasked (SYNI=1)

an interrupt is initiated whenever
change of state of basic frame
synchronization condition exists.
If 1 - unmasked, 0 - masked.

6 MFSYIM Multiframe Synchronization

Interrupt Mask. When unmasked
(MFSYI=1), an interrupt is
initiated whenever a change of
state of multiframe synchro­nization is lost. If 1 - unmasked, 0

- masked.

5 CSYNIM CRC-4 Multiframe

Synchronization Interrupt
Mask. When unmasked

(CSYNI=1), an interrupt is
initiated whenever a change of
state of CRC-4 multiframe
synchronization exists. If 1 ­unmasked, 0 - masked.

4 AISIM Alarm Indication Signal

Interrupt Mask. When unmasked
(AISI=1) a change of state of
received AIS will initiate an
interrupt. If 1 - unmasked, 0 ­masked.

3 LOSIM Loss of Signal Interrupt Mask.

When unmasked this interrupt bit
goes high whenever a change of
state of loss of signal (either
analog - received signal 20 or 40
dB below nominal or digital - 192
consecutive 0’s received)
condition exists. If 1 - unmasked,
0 - masked.

1 RSV Reserved. Must be kept at 0 for

normal operation.

0 - - - Unused.

Table 89 - Signalling Control Word (E1)

(Page 1, Address 1AH)

2 CEFIM Consecutively Errored FASs

Interrupt Mask. When unmasked

an interrupt is initiated when two
consecutive errored frame
alignment signals are received. If
1 - unmasked, 0 - masked.

Table 90 - Interrupt Mask Word Zero (E1)

(Page 1, Address 1BH)

75

MT9074 Advance Information

Bit Name Functional Description

1 YIM Remote Signalling Multiframe

Alarm Interrupt Mask. When

unmasked (YI=1), an interrupt is
initiated whenever a change of
state of remote signalling
multiframe alarm signal is
received. If 1 - unmasked, 0 ­masked.

0 SLPIM SLIP Interrupt Mask. When

unmasked (SLPI=1), an interrupt
is initiated when a controlled
frame slip occurs. If 1 ­unmasked, 0 - masked.

Table 90 - Interrupt Mask Word Zero (E1)

(Page 1, Address 1BH)

Bit Name Functional Description

7 FERIM Frame Error Interrupt Mask. When

unmasked (FERI = 1), an interrupt is
initiated when an error in the frame
alignment signal occurs. If 1 ­unmasked, 0 - masked.

6 CRCIM CRC-4 Error Interrupt Mask. When

unmasked an interrupt is initiated
when a local CRC-4 error occurs. 1 ­unmasked, 0 - masked. If 1 ­unmasked, 0 - masked.

5 EBIM Receive E-bit Interrupt Mask. When

unmasked an interrupt is initiated
when a receive E-bit indicates a
remote CRC-4 error. 1 - unmasked, 0

- masked. If 1 - unmasked, 0 ­masked.

4 AIS16IM Channel 16 Alarm Indication Signal

Interrupt Mask. When unmasked
(AIS16I = 1), a received AIS16 will
initiate an interrupt. If 1 - unmasked, 0

- masked.

3 BPVIM Bipolar Violation Interrupt Mask.

When unmasked an interrupt is
initiated when a bipolar violation error
occurs. 1 - unmasked, 0 - masked.

Table 91 - Interrupt Mask Word One (E1)

(Page 1, Address 1CH)

Bit Name Functional Description

2 PRBSIM PRBS Interrupt Mask. When

unmasked (PRBSI = 1), an interrupt
is initiated on a single PRBS
detection error. If 1 - unmasked, 0 ­masked.

1 AUXPIM Auxiliary Pattern Interrupt Mask.

When unmasked (AUXPI = 1), an
interrupt is initiated when the AUXP
status bit of page 03H, address 15H
goes high. If 1 - unmasked, 0 ­masked.

0 RAIIM Remote Alarm Indication Interrupt

Mask. When unmasked (RAII = 1) a
received RAI will initiate an interrupt.
If 1 - unmasked, 0 - masked.

Table 91 - Interrupt Mask Word One (E1)

(Page 1, Address 1CH)

Bit Name Functional Description

7 FEOM Frame Alignment Signal

Error Counter Overflow
Interrupt Mask. When

unmasked an interrupt is
initiated when the frame
alignment signal error counter
overflows. If 1 - unmasked, 0 ­masked.

6 CRCOIM CRC-4 Error Counter

Overflow Interrupt. When
unmasked an interrupt is
initiated when the CRC-4 error
counter overflows. If 1 ­unmasked, 0 - masked.

5 EBOIM Receive E-bit Counter

Overflow Interrupt. When
unmasked an interrupt is
initiated when the E-bit error
counter overflows. If 1 -

unmasked, 0 - masked.
4 - - - Unused.
3 BPVCOM Bipolar Violation Counter

Overflow Interrupt. When

unmasked (BPVO = 1), an

interrupt is initiated when the

bipolar violation error counter

changes form FFFFH to 0H. If

1 - unmasked, 0 - masked.

76

Table 92 - Interrupt Mask Word Two (E1)

(Page 1, Address 1DH)

Advance Information MT9074

Bit Name Functional Description

2 PRBSOM PRBS Counter Overflow

Interrupt. When unmasked

(PRBSO = 1), an interrupt is
initiated on overflow of PRBS
counter (page 04H, address
10H) from FFH to 0H. If 1 ­unmasked, 0 - masked.

1 PRBSMFOMPRBS MultiFrame Counter

Overflow Interrupt When
unmasked an interrupt will be
generated whenever the
multiframe counter attached
to the PRBS error counter
overflows. If 1 - unmasked, 0 ­masked.

0 - - - Unused.

Table 92 - Interrupt Mask Word Two (E1)

(Page 1, Address 1DH)

Bit Name Functional Description

Bit Name Functional Description

0 SIGIM Signalling (CAS) Interrupt Mask.

When unmasked and any of the
receive ABCD bits of any channel
changes state an interrupt is initiated.
If 1 - unmasked, 0 - masked.

Table 93 - Interrupt Mask Word Three (E1)

(Page 1, Address 1EH)

7-5 - - - Unused

4 JAIM Jitter Attenuation Interrupt Mask.

When unmasked, an interrupt will be
initiated when the jitter attenuator
FIFO comes within four bytes of an
overflow or underflow condition. If 1 ­unmasked, 0 - masked.

3 1SECIM One Second Status Interrupt Mask.

When unmasked (1SECI = 1), an
interrupt is initiated when the 1SEC
status bit changes from zero to one. If
1 - unmasked, 0 - masked.

2 5SECIM Five Second Status Interrupt Mask.

When unmasked (5SECI = 1), an
interrupt is initiated when the 5SECI
status bit changes from zero to one. If
1 - unmasked, 0 - masked.

1 RCRIM RCRI Interrupt Mask. When

unmasked (RCRI=1), an interrupt is
initiated when RCR (remote alarm &
CRC-4 error) status bit changes from
zero to one. If 1 - unmasked, 0 ­masked.

Table 93 - Interrupt Mask Word Three (E1)

(Page 1, Address 1EH)

77

MT9074 Advance Information

Bit Name Functional Description

7 NRZ NRZ Format Selection. Only used in the digital framer only mode (LIU is

disabled). A one sets the MT9074 to accept a unipolar NRZ format input
stream on RxA as the line input, and to transmit a unipolar NRZ format
stream on TxB. A zero causes the MT9074 to accept a complementary pair
of dual rail inputs on RxA/RxB and to transmit a complementary pair of dual
rail outputs on TxA/TxB.

6-4 TX2-0 Transmit pulse amplitude. Select the TX2 –TX0 bits according to the line

type, value of termination resistors (RT), and transformer turns ratio used
TX2 TX1 TX0 Line Impedance(ohms) RT(ohms) Transformer Ratio
0 0 0 120 0 1:2
0 0 1 120 0 1:1
0 1 0 120 15 1:2
0 1 1 120/75 12.1 1:2
1 0 0 75 0 1:2
1 0 1 75 0 1:1
1 1 1 75 9.1 1:2
1 1 1 75/120 12.1 1:2
After reset these bits are zero.

3 REDBL Receive Equalizer Disable. If one the receive equalizer is turned off. If zero,

the receive equalizer is turned on and will compensate for loop length
automatically.

2-0 RES2-0 Receive Equalization Select. Setting these pins forces a level of

equalization of the incoming line data.
RES2 RES1 RES0 Receive Equalization
0 0 0 none
0 0 1 6dB
0 1 0 12dB
0 1 1 18dB
1 0 0 24dB
1 0 1 reserved
1 1 0 reserved
1 1 1 reserved
These settings have no effect if REDBL is set to zero.

Table 94 - LIU Control Word (E1)

(Page 1, Address 1FH)

78

Advance Information MT9074

Master Control 2 (Page-2)

Master Control 2 (Page 02H) (E1)

Address

(A4A3A2A1A0)

10H (Table 96) Configuration Control Word T1/E1, LIUEn, ELOS, ADSEQ
11H (Table 97) Custom Tx Pulse Enable CPL
12H Reserved Set all bits to zero for normal operation.
13H Reserved Set all bits to zero for normal operation.
14H Reserved Set all bits to zero for normal operation.
15H Reserved Set all bits to zero for normal operation.
16H Reserved Set all bits to zero for normal operation.
17H Reserved Set all bits to zero for normal operation.
18H Reserved Set all bits to zero for normal operation.
19H Reserved Set all bits to zero for normal operation.
1AH Reserved Set all bits to zero for normal operation.
1BH Reserved Set all bits to zero for normal operation.
1CH (Table 98) Custom Pulse Word 1 CP6-0

Register Names

1DH(Table 99) Custom Pulse Word 2 CP6-0
1EH (Table 100) Custom Pulse Word 3 CP6-0
1FH (Table 101) Custom Pulse Word 4 CP6-0

Table 95 -Master Control 2 (Page 02H) (E1)

79

MT9074 Advance Information

Bit Name Functional Description

7 T1/E1 E1 mode selection. when this bit is

one, the device is in E1 mode.

6-5 RSV Reserved. Must be kept at 0 for

normal operation.

4 LIUEn LIU Enable.Setting this bit low

enables the internal LIU front-end.
Setting this pin high disables the
LIU. Digital inputs RXA and RXB are
sampled by the rising edge of E2.0i
(C1.50) to strobe in the received line
data. Digital transmit data is clocked
out of pins TXA and TXB with the
rising edge of C2.0o

3 ELOS ELOS Enable. Set this bit low to set

the analog loss of signal threshold to
40 dB below nominal. Set this bit
high to set the analog loss of signal
threshold to 20 dB below nominal.

2 RSV Reserved. Must be kept at 0 for

normal operation.

Bit Name Functional Description

7 RSV Reserved. Must be kept high for

normal operation.

6-4 RSV Reserved. Must be kept low for normal

operation.

3 CPL Custom Pulse Level. Setting this bit

low enables the internal ROM values in
generating the transmit pulses. The
ROM is coded for different line
terminations or build out, as specified
in the LIU Control word. Setting this bit
high disables the pre-programmed
pulse templates. Each of the 4 phases
that generate a mark derive their D/A
coefficients from the values
programmed in the CPW registers.

2-0 RSV Reserved. Must be kept at 0 for normal

operation.

Table 97 - Custom Tx Pulse Enable

(Page 2, Address 11H) (E1)

1 ADSEQ Digital Milliwatt or Digital Test

Sequence. If one, the A-law digital

milliwatt analog test sequence will
be selected by the Per Time Slot
Control bits TTST and RTST.If zero,
a PRBS generator / detector will be
connected to channels with TTST,
RRST respectively

0 RSV Reserved. Must be kept at 0 for

normal operation.

Table 96 - Configuration Control Word

(Page 2, Address 10H) (E1)

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for normal

operation.

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the first
phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.

Table 98 - Custom Pulse Word 1

(Page 2, Address 1CH) (E1)

80

Advance Information MT9074

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for

normal operation.

6-0 CP6-0 Custom Pulse . These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the
second phase of a mark. The greater
the binary number loaded into the
register, the greater the amplitude
driven out. This feature is enabled
when the control bit 3 - CPL of the
Custom Tx Pulse Enable Register ­address 11H of Page 2 is set high.

Table 99 - Custom Pulse Word 2

(Page 2, Address 1DH) (E1)

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for

normal operation.

Bit Name Functional Description

7 RSV Reserved. Must be kept at 0 for

normal operation.

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/TRING
line driver A/D converter during the
fourth phase of a mark. The greater
the binary number loaded into the
register, the greater the amplitude
driven out. This feature is enabled
when the control bit 3 - CPL of the
Custom Tx Pulse Enable Register ­address 11H of Page 2 is set high.

Table 101 - Custom Pulse Word 4

(Page 2, Address 1FH) (E1)

6-0 CP6-0 Custom Pulse. These bits provide the

capability for programming the
magnitude setting for the TTIP/
TRING line driver A/D converter
during the third phase of a mark. The
greater the binary number loaded into
the register, the greater the amplitude
driven out. This feature is enabled
when the control bit 3 - CPL of the
Custom Tx Pulse Enable Register ­address 11H of Page 2 is set high.

Table 100 - Custom Pulse Word 3

(Page 2, Address 1EH) (E1)

81

MT9074 Advance Information

Master Status 1 (Page03H) (E1)

Address

(A4A3A2A1A0)

10H (Table 103) Synchronization Status Word SYNC, MFSYNC, CRCSYN, REB1, REB2,

11H (Table 104) Alarm Status Word 1 CRCS1, CRCS2, RFAIL, LOSS, AIS16S, AISS,

12H (Table 105) Timer Status Word 1SEC, 2SEC, 400T, 8T, CALN, KLVE, T1,T2
13H (Table 106) Most Significant Phase Status Word RSLIP, RSLPD, RXFRM, AUXP, CEFS
14H (Table 107) Least Significant Phase Status Word RxTS4-0, RxBC2-0
15H (Table 108) Receive Frame Alignment Signal RIU0 &RFA2-8
16H (Table 109) Receive Signal Status Word EQSTAT4-0, LLOS
17H (Table 110) Jitter Attenuator Status Word JACS, JACF, JAE, JAF4, JAFC, JAE4, JAF
18H (Table 111) Receive Non-frame Alignment Signal RIU1, RNFAB, RALM, &RNU4-8
19H (Table 112) Receive Multiframe Alignment Signal RMAI1-4, X1, Y, X2, & X3
1AH Unused
1BH (Table 113) Alarm Status Word 2 RAIS, AISS, AIS16S, LOSS, AUXPS,

Register Function

CRCRF, RED, CRCIWK

RAIS, RCRS

MFALMS, SLIPS
1CH-1EH Unused
1FH (Table 114) Identification Register Set to 10101111

Table 102 - Master Status 1 (Page 3) (E1)

82

Advance Information MT9074

Bit Name Functional Description

7 SYNC Receive Basic Frame Alignment.

SYNC indicates the basic frame
alignment status (1 - loss; 0 ­acquired).

6 MFSYNC Receive Multiframe Alignment.

MFSYNC indicates the multiframe
alignment status (1 - loss; 0 ­acquired).

5 CRCSYN Receive CRC-4 Synchronization.

CRCSYN indicates the CRC-4
multiframe alignment status (1 ­loss; 0 - acquired).

4 REB1 Receive E-Bit One Status. REB1

indicates the status of the received
E1 bit of the last multiframe.

3 REB2 Receive E-Bit Two Status. REB2

indicates the status of the received
E2 bit of the last multiframe.

2 CRCRF CRC-4 Reframe. A one indicates

that the receive CRC-4 multiframe
synchronization could not be found
within the time out period of 8 msec.
after detecting basic frame
synchronization. This will force a
reframe when the maintenance
option is selected and automatic
CRC-4 interworking is de-selected.

1 RED RED Alarm. RED goes high when

basic frame alignment has been lost
for at least 100 msec. This bit will be
low when basic frame alignment is
acquired (I.431).

0 CRCIWK CRC-4 Interworking. CRCIWK

indicates the CRC-4 interworking
status (1 - CRC-to-CRC; 0 - CRC­to-non-CRC).

Table 103 - Synchronization Status Word

(Page 3, Address 10H) (E1)

Bit Name Functional Description

7 CRCS1 Receive CRC Error Status One.

If one, the evaluation of the last
received submultiframe 1 resulted
in an error. If zero, the last
submultiframe 1 was error free.
Updated on a submultiframe 1
basis.

6 CRCS2 Receive CRC Error Status Two.

If one, the evaluation of the last
received submultiframe 2 resulted
in an error. If zero, the last
submultiframe 2 was error free.
Updated on a submultiframe 2
basis.

5 RFAIL Remote CRC-4 Multiframe

Generator/Detector Failure. If
one, then each of the previous five
seconds have an E-bit error count
of greater than 989, and for this
same period the receive RAI bit
was zero (no remote alarm), and
for the same period the SYNC bit
was equal to zero (basic frame
alignment has been maintained). If
zero, indicates normal operation.

4 LOSS Loss of Signal Status. If one,

indicates the presence of a loss of
signal condition. If zero, indicates
normal operation. A loss of signal
condition occurs when 192
consecutive bit periods are zero. A
loss of signal condition terminates
when an average ones density of
at least 12.5% has been received
over a period of 192 contiguous
pulse positions starting with a
pulse.

3 AIS16S Alarm Indication Signal 16

Status. If one, indicates an all
ones alarm is being received in
channel 16. If zero, normal
operation. Updated on a frame
basis.

2 AISS Alarm Indication Status

Signal. If one, indicates that a
valid AIS or all ones signal is
being received. If zero, indicates
that a valid AIS signal is not being
received. The criteria for AIS
detection is determined by the
control bit ASEL.

Table 104 - Alarm Status Word 1

(Page 3, Address 11H) (continued) (E1)

83

MT9074 Advance Information

Bit Name Functional Description

1 RAIS Remote Alarm Indication Status.

If one, there is currently a remote
alarm condition (i.e., received A bit
is one). If zero, normal operation.
Updated on a non-frame alignment
frame basis.

0 RCRS RAI and Continuous CRC Error

Status. If one, there is currently an
RAI and continuous CRC error
condition. If zero, normal
operation. Updated on a
multiframe basis.

Table 104 - Alarm Status Word 1

(Page 3, Address 11H) (continued) (E1)

Bit Name Functional Description

7 1SEC One Second Timer Status. This bit

changes state once every 0.5 second
and is synchronous with the 2SEC
timer.

6 2SEC Two Second Timer Status. This bit

changes state once every second and
is synchronous with the 1SEC timer.

5 400T 400 msec. Timer Status. This bit

changes state when the 400 msec.
CRC-4 multiframe alignment timer

expires.
4
3 CALN CRC-4 Alignment. This bit changes

2 KLVE Keep Alive. This bit is high when the

--

Unused.

state every msec. When CRC-4

multiframe alignment has been

achieved state changes of this bit are

synchronous with the receive CRC-4

synchronization signal.

AIS status bit has been high for at least

100msec. This bit will be low when AIS

goes low (I.431).
1T1Timer One. This bit will be high upon

loss of terminal frame synchronization

persisting for 100 msec. This bit shall

be low when T2 becomes high. Refer

to I.431 Section 5.9.2.2.3.
0T2Timer Two. This bit will be high when

the MT9074 acquires terminal frame

synchronization persisting for 10 msec.

This bit shall be low when non-normal

operational frames are received. I.431

Section 5.9.2.2.3.

Table 105 - Timer Status Word

(Page 3, Address 12H) (E1)

84

Advance Information MT9074

Bit Name Functional Description

7 RSLIP Receive Slip. A change of state (i.e.,

1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.

6 RSLPD Receive Slip Direction. If one,

indicates that the last received frame
slip resulted in a repeated frame, i.e.,
system clock is faster than network
clock. If zero, indicates that the last
received frame slip resulted in a lost
frame, i.e., system clock is slower than
network clock. Updated on an RSLIP
occurrence basis.

5 RXFRMReceive Frame Delay. The most

significant bit of the Receive Slip
Buffer Phase Status Word. If zero, the
delay through the receive elastic buffer
is greater than one frame in length; if
one, the delay through the receive
elastic buffer is less than one frame in
length.

4 AUXP Auxiliary Pattern. This bit will go high

when a continuous 101010... bit
stream (Auxiliary Pattern) is received
on the PCM 30 link for a period of at
least 512 bits. If zero, auxiliary pattern
is not being received. This pattern will
be decoded in the presence of a bit
error rate of as much as 10-3.

3 CEFS Consecutively Errored Frame

Alignment Signal. This bit goes high
when the last two frame alignment
signals were received in error. This bit
will be low when at least one of the last
two frame alignment signals is without
error.

2-0 - - - Unused.

Bit Name Functional Description

7 - 3 RxTS4 - 0 Receive Time Slot. A five bit

counter that indicates the number
of time slots between the receive
elastic buffer internal write frame
boundary and the ST-BUS read
frame boundary. The count is
updated every 250 uS.

2 - 0 RxBC2 - 0 Receive Bit Count. A three bit

counter that indicates the number
of STBUS bit times there are
between the receive elastic buffer
internal write frame boundary and
the ST-BUS read frame boundary.
The count is updated every 250
uS.

Table 107 - Least Significant Phase Status Word

(Page 3, Address 14H) (E1)

Bit Name Functional Description

7 RIU0 Receive International Use Zero.

This is the bit which is received on
the PCM 30 2048 kbit/sec. link in bit
position one of the frame alignment
signal. It is used for the CRC-4
remainder or for international use.

6-0 RFA2-8 Receive Frame Alignment Signal

Bits 2 to 8. These bit are received on
the PCM 30 2048 kbit/sec. link in bit
positions two to eight of frame
alignment signal. These bits form the
frame alignment signal and should
be 0011011.

Table 108 - Receive Frame Alignment Signal

(Page 3, Address 15H) (E1)

Table 106 - Most Significant Phase Status Word

(Page 3, Address 13H) (E1)

85

MT9074 Advance Information

Bit Name Functional Description

7 -3PD4 -

PD0

Peak Detector Voltage Levels.

These five bits indicate the level of the
received signal AMI pulses.

PD4 PD3 PD2 PD1 PD0 Line Attenuation
0 0 0 0 1 less than 4dB
0 0 0 1 0 3-8dB
0 0 1 0 0 8-14dB
0 1 0 0 0 14-20dB
1 0 0 0 0 more than 20dB

2 LLOS LIU Loss of Signal indication. This

bit will be high if the received signal is
below the threshold selected by ELOS
(page 2, address 10H) for a period of
at least 1 msec. This bit will be low for
normal operation.

1-0 - - - Unused

Table 109 - Receive Signal Status Word

(Page 3, Address 16H) (E1)

Bit Name Functional Description

7 RIU1 Receive International Use 1. This

bit is received on the PCM 30 2048
kbit/sec. link in bit position one of the
non-frame alignment signal. It is used
for CRC-4 multiframe alignment or
international use.

6 RNFAB Receive Non-frame Alignment Bit.

This bit is received on the PCM 30
2048 kbit/sec. link in bit position two
of the non-frame alignment signal.
This bit should be one in order to
differentiate between frame
alignment frames and non-frame
alignment frames.

5 RALM Receive Alarm. This bit is received

on the PCM 30 2048 kbit/sec. link in
bit position three (the A bit) of the
non-frame alignment signal. It is used
as a remote alarm indication (RAI)
from the far end of the PCM 30 link (1

- alarm, 0 - normal).

Bit Name Functional Description

7 JACS Jitter Attenuated Clock Slow. If one it

indicates that the dejittered clock
period is increased by 1/16 UI. If zero
the clock is at normal speed.

6 JACF Jitter Attenuated Clock Fast. If one it

indicates that the dejittered clock
period is decreased by 1/16 UI. If zero
the clock is at normal speed.

5 JAE Jitter Attenuator FIFO Empty. If one it

indicates that the JA FIFO is empty.

4 JAF4 Jitter Attenuator FIFO with 4 Full

Locations. If one it indicates that the
JA FIFO has at least 4 full locations.

3 JAFC Jitter Attenuator Center Full. If one it

indicates that the JA FIFO is at least
half full.

2 JAE4 Jitter Attenuator FIFO with 4 Empty

Locations. If one it indicates that the
JA FIFO has at most 4 empty locations.

4-0 RNU4-8 Receive National Use Four to

Eight. These bits are received on the
PCM 30 2048 kbit/sec. link in bit
positions four to eight (the Sa bits) of
the non-frame alignment signal.

Table 111 - Receive Non-Frame Alignment

Signal

(Page 3, Address 18H) (E1)

1 JAF Jitter Attenuator FIFO Full. If one it

indicates that the JA FIFO is full.

0 - - - Unused.

Table 110 - Jitter Attenuator Status Word

(Page 3, Address 17H) (E1)

86

Advance Information MT9074

Bit Name Functional Description
7-4 RMAI1-4 Receive Multiframe Alignment Bits

One to Four. These bits are received

on the PCM 30 2048 kbit/sec. link in
bit positions one to four of time slot
16 of frame zero of every signalling
multiframe. These bit should be 0000
for proper signalling multiframe
alignment.

3X1Receive Spare Bit X1. This bit is

received on the PCM 30 2048 kbit/
sec. link in bit position five of time slot
16 of frame zero of every signalling
multiframe.

2 YReceive Y-bit. This bit is received on

the PCM 30 2048 kbit/sec. link in bit
position six of time slot 16 of frame
zero of every signalling multiframe.
The Y bit may indicate loss of
multiframe alignment at the remote
end (1 -loss of multiframe alignment;
0 - multiframe alignment acquired).

1-0 X2, X3 Receive Spare Bits X2 and X3.

These bits are received on the PCM
30 2048 kbit/sec. link in bit positions
seven and eight respectively, of time
slot 16 of frame zero of every
signalling multiframe.

Table 112 - Receive Multiframe Alignment Signal

(Page 3, Address 19H) (E1)

Bit Name Functional Description

5 AIS16S Alarm Indication Signal 16

Status. If one, indicates an all

ones alarm is being received in
channel 16. If zero, normal
operation. Updated on a frame
basis.

4 LOSS Loss of Signal Status. If one,

indicates the presence of a loss
of signal condition. If zero,
indicates normal operation. A
loss of signal condition occurs
when 192 consecutive bit
periods are zero. A loss of signal
condition terminates when an
average ones density of at least

12.5% has been received over a
period of 192 contiguous pulse
positions starting with a pulse.

3 AUXPS Auxiliary Pattern Status. This

bit goes high when a continuous

101010... bit stream (Auxiliary
Pattern) is received on the PCM
30 link for a period of at least 512
bits. If zero, auxiliary pattern is
not being received. This pattern
will be decoded in the presence
of a bit error rate of as much as
10-3.

2 MFALMS Multiframe Alarm Status. This

bit goes high in the event of
receipt of a multiframe alarm. It
goes low when the received
multiframe alarm bit goes low.

Bit Name Functional Description

7 RAIS Remote Alarm Indication

Status. If one, there is currently

a remote alarm condition (i.e.,
received A bit is one). If zero,
normal operation. Updated on a
non-frame alignment frame
basis.

6 AISS Alarm Indication Status

Signal. If one, indicates that a
valid AIS or all ones signal is
being received. If zero , indicates
that a valid AIS signal is not
being received. The criteria for
AIS detection is determined by
the control bit ASEL.

Table 113 - Alarm Status Word 2

(Page 3, Address 1BH) (E1)

1 RSLIPS Receive Slip Status. A change

of state (i.e., 1-to-0 or 0-to-1)
indicates that a receive
controlled frame slip has
occurred.

0 - - - Unused.

Table 113 - Alarm Status Word 2

(Page 3, Address 1BH) (E1)

Bit Name Functional Description

7-0 ID7-0 ID Number. Contains device code

10101111

Table 114 - Identification Word

(Page 3, Address 1FH) (E1)

87

MT9074 Advance Information

Master Status 2 (Page-4)

Master Status 2 (Page 04H) (E1)

Address

(A4A3A2A1A0)

10H (Table 116) PRBS Error Counter PS7-0
11H (Table 117) CRC Multiframe counter for PRBS PSM7-0
12H (Table 118) Alarm Reporting Latch RAI, AIS, AIS16, LOS, AUXP, MFALM, RSLIP
13H (Table 119) Framing Bit Counter EFAS7-0
14H (Table 120) E-bit Error Counter Ebt EC9-EC8
15H (Table 121) E-bit Error Counter Ebt EC7-EC0
16H (Table 122) Most Significant Bipolar Violation Error

Counter

17H (Table 123) Least Significant Bipolar Violation Error

Counter
18H (Table 124) CRC- 4 Error Counter CEt CC9-CC8
19H (Table 125) CRC- 4 Error Counter CEt CC7 - CC0
1AH Unused.
1BH (Table 126) Interrupt Word Zero TFSYNI, MFSYNI, AISI, LOSI, CEF,Y, RxSLPI

Register Function

BPV15 - BPV8

BPV7 - BPV0

1CH (Table 127) Interrupt Word One RAII,AUXPI,PRBSERRI,BPVI,AIS16I,EBITI,

CRCERRI, FERRI

1DH (Table 128) Interrupt Word Two FERRO,CRCO,FEBEO,BPVO,PRBSO,PRBSM

FO
1EH (Table 129 Interrupt Word Three HDLC0I,HDLC1I,JAII,1SECI,5SECI,RCRI,SIGI
1FH (Table 130) Overflow Reporting Latch FERROL,CRCOL,FEBEOL,BPVOL, PRBSOL,

PRBSMFOFOL

Table 115 - Master Status 2 (Page 4) (E1)

88

Advance Information MT9074

Bit Name Functional Description

7 - 0 PS7-0 This counter is incremented for each

PRBS error detected on any of the
receive channels connected to the
PRBS error detector.

Table 116 - PRBS Error Counter

(Page 4, Address 10H) (E1)

Bit Name Functional Description

7 - 0 PSM7-0 This counter is incremented for each

received CRC multiframe. It is
cleared when the PRBS Error
Counter is written to.

Table 117 - CRC Multiframe Counter for PRBS

(Page 4, Address 11H) (E1)

Bit Name Functional Description

7 RAI Remote Alarm Indication. This bit is

set to one in the event of receipt of a
remote alarm, i.e. A(RAI) = 1. It is
cleared when the register is read.

6 AIS Alarm Indication Signal. This bit is

set to one in the event of receipt of an
all ones alarm. It is cleared when the
register is read.

5 AIS16 AIS Time Slot 16 Alarm. This bit is

set to one in the event of receipt of an
all ones alarm in the time slot 16. It is
cleared when the register is read.

4 LOS Loss of Signal. This bit is set to one

in the event of digital loss of received
signal. It is cleared when the register
is read.

3 AUXP Auxiliary Alarm. This bit is set to one

in the event of receipt of the auxiliary
alarm pattern. It is cleared when the
register is read.

2 MFALM Multiframe Alarm. This bit is set to

one in the event of receipt of a
multiframe alarm. It is cleared when
the register is read.

1 RSLIP Received Slip. This bit is set to one

in the event of receive elastic buffer
slip. It is cleared when the register is
read.

0 - - - Unused.

Table 118 - Alarm Reporting Latch

(Page 4, Address 12H) (E1)

Bit Name Functional Description

7 - 0 EFAS7 - 0 Errored FAS Counter. An 8 bit

counter that is incremented once
for every receive frame alignment
signal that contains one or more
errors.

Table 119 - Errored Frame Alignment Signal

Counter

(Page 4, Address 13H) (E1)

89

MT9074 Advance Information

Bit Name Functional Description

7-2 - - - Unused
1-0 EC9-8 E bit Error Counter. The most

significant 2 bits of the E bit error
counter.

Table 120 - E-bit Error Counter

(Page 4, Address 14H) (E1)

Bit Name Functional Description

7 - 0 EC7-0 E bit Error Counter. The least

significant 8 bits of the E-bit error
counter.

Table 121 - E-bit Error Counter

(Page 4, Address 15H) (E1)

Bit Name Functional Description

7 - 0 BPV15 - 8 Most Significant Bits of the

BPV Counter. The most

significant eight bits of a 16 bit
counter that is incremented once
for every bipolar violation error
received.

Table 122 - Most Significant Bits of the BPV

Counter

(Page 4, Address 16H) (E1)

Bit Name Functional Description

7 - 0 BPV7 - 0 Least Significant Bits of the BPV

Counter. The least significant eight

bits of a 16 bit counter that is
incremented once for every bipolar
violation error received.

Table 123 - Least Significant Bits of the BPV

Counter

(Page 4, Address 17H) (E1)

Bit Name Functional Description

7-2 - - - Unused
1-0 CC9 - 8 CRC-4 Error Counter These are the

most significant eight bits of the
CRC-64error counter.

Table 124 - CRC-4 Error Counter CEt

(Page 4, Address 18H) (E1)

Bit Name Functional Description

7 - 0 CC7 - 0 CRC-4 Error Counter. These are

the least significant eight bits of the
CRC-4 error counter.

Table 125 - CRC-4 Error Counter CEt

(Page 4, Address 19H) (E1)

Bit Name Functional Description

7 TFSYNI Terminal Frame

Synchronization Interrupt.

When unmasked this interrupt
bit goes high whenever a
change of state of terminal
frame synchronization condition
exists. Reading this register
clears this bit.

6 MFSYNI Multiframe Synchronization

Interrupt. When unmasked this
interrupt bit goes high whenever
a change of state of multiframe
synchronization condition
exists. Reading this register
clears this bit.

5 CRCSYNI CRC-4 Synchronization

Interrupt. When unmasked this
interrupt bit goes high whenever
change of state of CRC-4
synchronization condition
exists. Reading this register
clears this bit.

4 AISI Alarm Indication Signal

Interrupt. When unmasked this
interrupt bit goes high whenever
a change of state of received all
ones condition exists. Reading
this register clears this bit.

90

Table 126 - Interrupt Word Zero

(Page 4, Address 1BH) (E1)

Advance Information MT9074

Bit Name Functional Description

3 LOSI Loss of Signal Interrupt.

When unmasked this interrupt
bit goes high whenever a loss of
signal (either analog - received
signal 20 or 40 dB below
nominal or digital - 192
consecutive 0’s received)
condition exists.

2 CEFI Consecutively Errored Frame

Alignment Interrupt. When
unmasked this interrupt bit goes
high whenever the error in last
two frame alignment signals
occurs. Reading this register
clears this bit.

1YIReceive Y-bit Interrupt. When

unmasked this interrupt goes
high whenever a change of
status loss of multiframe
alignment occurs. Reading this
register clears this bit.

0 RxSLPI Receive SLIP Interrupt. When

unmasked this interrupt bit goes
high whenever a controlled
frame slip occurs in the receive
elastic buffer. Reading this
register clears this bit.

Table 126 - Interrupt Word Zero

(Page 4, Address 1BH) (E1)

Bit Name Functional Description

7 FERRI Errored Framing Alignment

Signal Interrupt. When unmasked

this interrupt bit goes high
whenever an erroneous bit in
frame alignment signal is detected
(provided the circuit is in terminal
frame sync). Reading this register
clears this bit.

6 CRCERRI CRC-4 Error Interrupt. When

unmasked this interrupt bit goes
high whenever a local CRC-4 error
occurs. Reading this register
clears this bit.

5 EBITI Receive E-bit Error Interrupt.

When unmasked this interrupt bit
goes high upon detection of a
wrong E-bit in multiframe. Reading
this register clears this bit.

4 AIS16I Alarm Indication Signal

Interrupt. When unmasked this
interrupt bit goes high whenever all
ones in time slot 16 occur.Reading
this register clears this bit.

3 BPVI Bipolar Violation Interrupt. When

unmasked this interrupt bit goes
high whenever a bipolar violation
(excluding HDB3 encoding) is
encountered. Reading this
register clears this bit.

2 PRBSERRIPseudo Random Bit Sequence

Error Interrupt. When unmasked
this interrupt bit goes high upon
detection of an error with a
channel selected for PRBS testing.
Reading this register clears this bit.

1 AUXPI Auxiliary Pattern Alarm

Interrupt. When unmasked this
interrupt bit goes high whenever a
sequence of 512 bit consecutive

101010. occur. Reading this
register clears this bit.

0 RAII Remote alarm Indication

Interrupt. When unmasked this
interrupt bit goes high

whenever the bit 3 of non-frame
alignment signal is high. Reading
this register clears this bit.

Table 127 - Interrupt Word One

(Page 4, Address 1CH) (E1)

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MT9074 Advance Information

Bit Name Functional Description

7 FERRO Errored Framing Alignment

Signal Counter Overflow
Interrupt. When unmasked this

interrupt bit goes high whenever
the errored frame alignment signal
counter changes from FFH to 00H.
Reading this register clears this
bit.

6 CRCO CRC Error Counter Overflow

Interrupt. When unmasked this
interrupt bit goes high whenever
the CRC error counter changes
from FFH to 00H. Reading this
register clears this bit.

5 FEBEO E-bit Counter Overflow

Interrupt. When unmasked this
interrupt bit goes high whenever
the E-bit counter changes from
FFH to 00H. Reading this register

clears this bit.
4 - - - Unused
3 BPVO Bipolar Violation Counter

Overflow Interrupt. When

unmasked this interrupt bit goes

high whenever the bipolar violation

counter changes from FFH to 00H.

Reading this register clears this

bit.

Bit Name Functional Description

7 - - - Unused
6 HDLC0I HDLC0 Interrupt. Whenever an

unmasked HDLC0 interrupt occurs.
This bit goes high. Reading this
register clears this bit.

5 HDLC1I HDLC1 Interrupt. Whenever an

unmasked HDLC1 interrupt occurs.
this bit goes high. Reading this
register clears this bit.

4 JAI Jitter Attenuator Error Interrupt.

Whenever an unmasked JAI interrupt
occurs.

If jitter attenuator FIFO comes within
four bytes of an overflow or underflow,
this bit goes high. Reading this
register clears this bit.

3 1SECI One Second Status Interrupt. When

unmasked this interrupt bit goes high
whenever the 1SEC status bit (page 3
address 12H bit 7) goes from low to
high. Reading this register clears this
bit.

2 5SECI Five Second Status Interrupt. When

unmasked this interrupt bit goes high
whenever the 5 SEC status bit goes
from low to high. Reading this register
clears this bit.

2 PRBSO Pseudo Random Bit Sequence

Error Counter Overflow

Interrupt. When unmasked this

interrupt bit goes high whenever

the PRBS error counter changes

from FFH to 00H. Reading this

register clears this bit.
1 PRBSMFO Pseudo Random Bit Sequence

Multiframe Counter Overflow

Interrupt. When unmasked this

interrupt bit goes high whenever

the multiframe counter attached to

the PRBS error counter overflows.

FFH to 00H. 1 - unmasked, 0 -

masked.
0 - - - Unused

Table 128 - Interrupt Word Two

(Page 4, Address 1DH) (E1)

1 RCRI RCRI Interrupt. Whenever an

unmasked RCRI interrupt occurs. If
remote alarm and CRC error occur
this bit goes high. Reading this
register clears this bit.

0 SIGI Signalling Interrupt. When

unmasked this interrupt bit goes high
whenever a change of state
(optionally debounced - see DBEn in
the Data Link, Signalling Control
Word) is detected in the signalling bits
(AB or ABCD) pattern. Reading this
register clears this bit.

Table 129 - Interrupt Word Three

(Page 4, Address 1EH) (E1)

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Advance Information MT9074

Bit Name Functional Description

7 FERROL Errored Frame Alignment Signal

Counter Overflow Latch. This bit

is set when the errored frame
alignment signal counter overflows.
It is cleared after being read.

6 CRCOL CRC Error Counter Overflow

Latch. This bit is set when the crc
error counter overflows. It is cleared
after being read.

5 FEBEOL E bit Counter Overflow Latch.

This bit is set when E bit counter
overflows. It is cleared after being

read.
4 - - ­3 BPVOL Bipolar Violation Counter

Overflow Latch. This bit is set

when the bipolar violation counter

overflows. It is cleared after being

read.
2 PRBSOL Pseudo Random Bit Sequence

Error Counter Overflow Latch.

This bit is set when the PRBS error

counter overflows. It is cleared after

being read.
1 PRBSM

FOFOL

0 - - - Unused.

Table 130 - Overflow Reporting Latch

Pseudo Random Bit Sequence

Multiframe Counter Overflow

Latch. This bit is set when the

multiframe counter attached to the

PRBS error counter overflows. It is

cleared after being read

(Page 4, Address 1FH) (E1)

93

MT9074 Advance Information

Per Channel Transmit Signalling (Pages 5 and 6) (E1)

Page 05H, addresses 10000 to 11111, and page 06H addresses 10000 to 10111 contain the Transmit
Signalling Control Words for Channel Associated Signalling (CAS) channels 2 to 16 and 18 to 32 respectively.
Table 132 illustrates the mapping between the addresses of these pages and the CAS channel numbers.
Control of these bits for any one channel is through the processor or controller port when the Per Time Slot
Control bit RPSIG bit is high. Table 133 describes bit allocation within each of these registers.

Page 5 Address: 0123456789101112131415
Equivalent CAS

channel
Page 6 Address: 0123456789101112131415
Equivalent CAS

channel

Table 131 - Page 5, 6 Address Mapping to CAS Signalling Channels (E1)

Bit Name Functional Description

7 - 4 - - - Unused.
3 - 0 A(n)

B(n)
C(n)
D(n)

Table 132 - Transmit Channel Associated Signalling (E1) (Pages 5,6)

12345678910111213141516

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM
30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (when

n = 1 to 15), and are the A, B, C, D signaling bits associated with channel n.

Serial per channel transmit signalling control through CSTI is selected when RPSIG bit is zero. Table 132
describes the function of CSTI time slots 1 to 30. if MSN bit is high, CSTI time slots 17 to 31 are selected. if
MSN bit is low, CSTI time slots 1 to 15 are selected.

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Advance Information MT9074

Bit Name Functional Description

7 - 4 A(n),

B(n),
C(n),

D(n)

3 - 0 A(n),

B(n),
C(n),

D(n)

NOTE: This table illustrates bit mapping on the serial input stream - it does not refer to an internal register.

Per Time Slot Control Words(Pages 7 and 8) (E1)

The control functions described by Table 135 are repeated for each PCM-30 channel. Page 07H addresses
10H to 1FH correspond to time slots 0 to 15, while page 08H addresses 10H to 1FH correspond to time slots
16 to 31.Table 136 illustrates the mapping between the addresses of these pages and the CEPT channel
numbers.

Page 8H Address: 0123456789101112131415

Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM
30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where

n = 1 to 15), and are the A, B, C, D signalling bits associated with channel n.

Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM
30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where

n = 1 to 15), and are the A, B, C, D signalling bits associated with channel n.

Table 133 - E1 / Transmit Channels Usage - CSTi

Equivalent PCM 30
Timeslots

Page 9H Address: 0123456789101112131415

Equivalent PCM 30
Timeslots

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Table 134 - Mapping to CEPT Channels(Page 8H and 9H) (E1)

95

MT9074 Advance Information

Bit Name Functional Description

7 TXMSG Transmit Message Mode. if high, the data from the corresponding address

location of Tx message mode buffer is transmitted in the corresponding PCM 30
time slot. If zero, the data on DSTI is transmitted on the corresponding PCM 30
time slot.

6 ADI Alternate Digit Inversion. If one, the corresponding transmit time slot data on

DSTI has every second bit inverted. If zero, this bit has no effect on channel data.

5 RTSL Remote Time Slot Loopback. If one, the corresponding PCM 30 receive time slot

is looped to the corresponding PCM 30 transmit time slot. This received time slot
will also be present on DSTO. If zero, the loopback is disabled.

4 LTSL Local Time Slot Loopback. If one, the corresponding transmit time slot is looped

to the corresponding receive time slot. This transmit time slot will also be present on
the transmit PCM 30 stream. If zero, this loopback is disabled.

3 TTST Transmit Test. If one, a test signal, either digital milliwatt (when control bit ADSEQ

is one) or PRBS (215-1) (ADSEQ is zero), will be transmitted in the corresponding
PCM 30 time slot. More than one time slot may be activated at once. If zero, the
test signal will not be connected to the corresponding time slot.

2 RTST Receive Test. If one, the corresponding DSTo time slot will be used for testing. If

control bit ADSEQ is one, a digital milliwatt signal will be transmitted into the DSTo
channel. If ADSEQ is zero, the receive channel will be connected to the PRBS (2

- 1) detector

1 RPSIG Serial Signaling Enable. If one, the transmit CAS signalling will be controlled by

programming Page 05H. If zero, the transmit CAS signalling will be controlled
through the CSTI stream.

0 - - - Unused.

Table 135 - Per Time Slot Control Words (Pages 7 and 8) (E1)

15

96

Advance Information MT9074

Per Channel Receive Signalling (Pages 9 and 0AH) (E1)

Page 09H, addresses 10001 to 11111, and page 1AH addresses 10001 to 11111 contain the Receive
Signalling Control Words for CAS channels 2 to 16 and 18 to 32. Table 137 illustrates the mapping between the
addresses of these pages and the CAS channel numbers. Table 138 describes bit allocation within each of
these registers.

Page 9 Address: 0123456789101112131415
Equivalent PCM 30

Timeslots
Page A Address: 0123456789101112131415
Equivalent PCM 30

Timeslots

Bit Name Functional Description

7 - 4 - - - Unused
3 - 0 A(n)

B(n)
C(n)
D(n)

Table 137 - Receive Channel Associated Signalling (Pages 9 and A) (E1)

Serial per channel receive signalling status bits appear on ST-BUS stream CSTo. Table 139 describes the bit
allocation within each of the 30 active ST-BUS time slot of CSTo.

0123456789101112131415

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Table 136 - Page 9, A Address Mapping to CAS Channels (E1)

Receive Signalling Bits for Channel n. These bits are received on the PCM 30

2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where n = 1
to 30) and are the A, B, C, D signalling bits associated with channel n.

Bit Name Functional Description

7 - 4 A(n),

B(n),
C(n),

D(n)

3 - 0 A(n),

B(n),
C(n),

D(n)

Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM
30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where

n = 1 to 15), and are the A, B, C, D signalling bits associated with channel n.

Transmit Signalling Bits for Channel n. These bits are transmitted on the PCM
30 2048 kbit/sec. Link in bit positions one to four of time slot 16 in frame n (where

n = 1 to 15), and are the A, B, C, D signalling bits associated with channel n.

Table 138 - Receive CAS Channels (CSTo) (E1)

97

MT9074 Advance Information

HDLC Control and Status (Page B for HDLC0 and Page C for HDLC1)

Register

Address

Control (Write/Verify) Status (Read)

10H(Table 140) Address Recognition 1 --- ADR16-10,A1EN
11H(Table 141) Address Recognition 2 --- ADR26-20, A2EN

Function

12H (Table
142/143)

13H(Table 144) HDLC Control 1 --- ADREC, RxEN, TxEN, EOP, FA, Mark-

14H(Table 145) --- HDLC Status INTGEN, Idle-Chan, RQ9, RQ8,

15H(Table 146) HDLC Control 2 --- INTSEL, CYCLE, TxCRCI,

16H(Table 147) Interrupt Mask --- GaIM, RxEOPIM, TxEOPIM, RxFEIM,

17H(Table 148) --- Interrupt Status (*) Ga, RxEOP, TxEOP, RxFE, TxFL,

18H(Table 149) --- Rx CRC MSB CRC15-CRC8
19H(Table 150) --- Rx CRC LSB CRC7-CRC0
1AH(Table 151) TX byte count --- TxCNT7-0
1BH(Table 152) Test Control --- HRST, RTLOOP, CRCTST, FTST, ARTST,

TX FIFO RX FIFO BIT7-0

idle,TR, FRUN

TxSTAT2, TxSTAT1, RxSTAT2, RxSTAT1

SEVEN,RxFRST, TxFRST

TxFLIM, FA:TxUNDERIM, RxFFIM,
RxOVFIM

FA:TxUNDER, RxFF, RxOVF

HLOOP
1CH(Table 153) --- Test Status RxCLK, TxCLK, VCRC, VADDR
1DH(Table 154) HDLC Control 3 --- RSV, RFD2-0,RSV, TFD2-0
1EH(Table 155) HDLC Control 4 --- RSV, RFFS2-0, RSV, TFLS2-0

Table 139 - HDLC 0 & 1 Control and Status (Page B & C)

98

Advance Information MT9074

Bit Name Functional Description

7 - 2 ADR16-11 Address 16 - 11. A six bit

address used for comparison
with the first byte of the received
address. ADR16 is MSB.

1 ADR10 Address 10. This bit is used in

address comparison if a seven
bit address is being checked for
(control bit four of control register
2 is set).

0 A1EN First Address Comparison

Enable. When this bit is high, the
above six (or seven) bit address
is used in the comparison of the
first address byte.

If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A1EN must be high
for All-call (1111111) address
recognition for single byte
address. When this bit is low, this
bit mask is ignored in address
comparison

T ab le 140 - HDLC Address Recognition Register

1

(Page B & C, Address 10H)

Bit Name Functional Description

7 - 0 BIT7-0 This eight bit word is tagged with the

two status bits from the control register
1 (EOP and FA), and the resulting 10
bit word is written to the TX FIFO. The
FIFO status is not changed
immediately after a write or read
occurs. It is updated after the data has
settled and the transfer to the last
available position has finished.

Table 142 - TX FIFO Write Register

(Page B & C, Address 12H)

Bit Name Functional Description

7 - 0 BIT7-0 This is the received data byte read

from the RX FIFO. The status bits of
this byte can be read from the status
register. The FIFO status is not
changed immediately when a write or
read occurs. It is updated after the
data has settled and the transfer to the
last available position has finished.

Table 143 - RX FIFO Read Register

(Page B & C, Address 12H)

Bit Name Functional Description

7 - 1 ADR26-20 Address 26 - 20. A seven bit

address used for comparison with
the second byte of the received
address. ADR26 is MSB. This
mask is ignored (as well as first
byte mask) if all call address
(1111111) is received.

0 A2EN Second Address Comparison

Enable. When this bit is set high,
the above seven bit address is
used in the comparison of the
second address byte.

If address recognition is enabled,
any packet failing the address
comparison will not be stored in
the RX FIFO. A2EN must be high
for All-call address recognition.
When this bit is low, this bit mask
is ignored in address comparison

Table 141 - HDLC Address Recognition

Register2 (Page B & C, Address 11H)

99

MT9074 Advance Information

Bit Name Functional Description

7 ADREC When high this bit will enable

address recognition. This
forces the receiver to recognize
only those packets having the
unique address as programmed
in the Receive Address
Recognition Registers or if the
address is an All call address.

6 RxEN When low this bit will disable

the HDLC receiver. The
receiver will disable after the
rest of the packet presently
being received is finished. The
receiver internal clock is
disabled.

When high the receiver will be
immediately enabled and will
begin searching for flags, Go­aheads etc.

5 TxEN When low this bit will disable

the HDLC transmitter. The
transmitter will disable after the
completion of the packet
presently being transmitted.
The transmitter internal clock is
disabled.

When high the transmitter will
be immediately enabled and
will begin transmitting data, if
any, or go to a mark idle or
interframe time fill state.

Bit Name Functional Description

2 Mark-Idle When low, the transmitter will

be in an idle state. When high it
is in an interframe time fill state.
These two states will only occur
when the TX FIFO is empty.

1 TR When high this bit will enable

transparent mode. This will
perform the parallel to serial
conversion without inserting or
deleting zeros. No CRC bytes
are sent or monitored nor are
flags or aborts. A falling edge of
TxEN for transmit and a falling
edge of RxEN for receive is
necessary to initialize
transparent mode. This will also
synchronize the data to the
transmit and receive channel
structure. Also, the transmitter
must be enabled through
control register 1 before
transparent mode is entered.

0 FRUN When high the HDLC TX and

RX are continuously enabled
providing the RxEN and TxEN
bits are set

Table 144 - HDLC Control register 1

(Page B & C, Address 13H)

4 EOP Forms a tag on the next byte

written the TX FIFO, and when
set will indicate an end of
packet byte to the transmitter,
which will transmit an FCS
following this byte. This
facilitates loading of multiple
packets into TX FIFO. Reset
automatically after a write to the
TX FIFO occurs.

3 FA Forms a tag on the next byte

written to the TX FIFO, and
when set will indicate to the
transmitter that it should abort
the packet in which that byte is
being transmitted. Reset
automatically after a write to the
TX FIFO.

Table 144 - HDLC Control register 1

(Page B & C, Address 13H)

100