Datasheet MT90710AP Datasheet (MITEL)

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CMOS

MT90710

High-Speed Isochronous Multiplexer

Preliminary Information

Features

• Multiplexe s eight 2.048 M bit/ s, ST-BUS links onto one seri al hig h-spee d 20 .48 Mbi t/s link

• 15.808 Mbit/s clear bandwidth transport

• Two 8 kbit/s and one 32 k bit/s o versa mpled signalling cha nnels

• Embedded system timing and frame synchronization

• Frame buffer co ntrol s ignals gener ated on-ch ip

• Check-su m gen erate d on multipl exe d fram e

• Remote synchronization indication

• Both mas ter an d slave t iming mode ope ration

• On-chip re ferenc e gene ration f or slave mode synchronization

• 4B/5B data encoding/decoding

Applications

• Fibre distributed sytems

• Backpla ne conc ent rato rs

• Local Area Networks (LANs)

ISSUE 1 January 1995

Ordering Information

MT90710AP 84 Pin PLCC

0 °C to +70 °C

Description

The High-Speed Isochronous Multiplexer integrated circuit multiplexes up to eight Serial Telecom (ST-BUS) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete electric to photonic conversion circuit. Optical transmission allows large bandwidth inter-shelf or, in distributed systems, inter-node communication by eliminating multiple data buses, cable inter-connect and attendant driver interfaces. The final result is a simple physical interface free of the radiated emissions and background noise susceptibility problems encountered in copper-wired environments.

STi0

STi5 STi6A STi6B

STi7

DIN8K0 DIN8K1 DIN32K

STo0

STo5 STo6A STo6B

STo7

DOUT8K0 DOUT8K1 DOUT32K

MUX

DEMUX

TRANSMIT

Overhead

Checksum

Frame Sync

RECEIVE

Overhead

Extract &

Insert

Error Check

To Transmit Driver

4B/5B &

NRZI

Encode

Frame Alignment & Buffer

External Memory Control

FBDATA0

FBADDR0

FBADDR7

FBDATA7

FBOE

Amplifier and Fiber

Driver Transducer

PISO

NRZI Decode

Sync Detect

4B/5B Decod e

From Receive Pin Diode,

Pre-amp and Post-amp

FBWE

Figure 1 - Functional Block Diagram

Circuits

Control

SIPO

RxDATA

Signals to

External PLL

TxDATA MODE0

MODE1 MODE2 F0b C4b E20i RLED LLED C20o POR RESET C4REFo

C4o C40i

5-3

MT90710 Preliminary Information

VSS

TxDATA

DOUT32K

F0b

STo1

FBWE

STo4

STo3

VSS

VDD

STo0

MODE0

MODE1

MODE2

FBOE

RLED

STo2

RxDATANCVDD

VDD POR

FBDATA7

C4b FBDATA6 FBDATA5

DIN8K0

FBDATA4

DIN32K

VDD

VSS

FBDATA3

STi0

FBDATA2

DIN8K1

FBDATA1

LLED

FBDATA0

RESET

VDD

VSS

FBADDR0

FBADDR1

84 PIN PLCC

FBADDR2

FBADDR3

FBADDR4

FBADDR5

FBADDR6

STo6B

VSS

VDD

STo7

DOUT8K0

C20o

DOUT8K1

STo6A

FBADDR7

VSS NC

E20i

STi7 STi6B

STi6A STi5

STi4 STi3

VDD VSS

STi2 STi1

C40i NC

NC NC

C4REFo C4o

VSS

VDD

STo5

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1V 2V

3STo7Serial, 32 Channel , 2.048 Mb/s Lin k 7 (Outpu t Type 3). Only channels 9 - 31 are

4 DOUT8K0 Asynchron ou s 8 kHz Signal 0 (Outpu t Type 3). Sourced from the far-end DIN8K 0

5 DOUT8K1 Asynchron ou s 8 kHz Signal 1 (Outpu t Type 3). Sourced from the far-end DIN8K 1

6 C20o 20.48 MHz Clock (Output Type 3). Derived from transmit PLL 40.96 MHz clock divided

7NCNo Internal Connection. 8 FBADDR7 Frame Buffer RAM Addr ess Bit 7 (Outpu t Type 2). 9STo6ASerial, 32 Channel , 2.048 Mb/s Lin k 6A (Outpu t Type 3). Output is active only when

Power Supply Ground. Nominally 0 volts . Positive Power Supply. Nominally 5 volts.

available for user data transfer (1.474 Mb/s). Channels 0 - 8 (0.576 Mb/ s) are reserved for access to fiber overhead information. Output is active only when the receiver detects the synchronization pattern on RxDA TA input stream; output is high impedance during loss of synchronization.

input.

by 2 (see pin 18). Made available for system use.

the receiver detects the synchronization pattern on RxDATA input stream; output is high impedance during loss of synchronizat ion.

5-4

Preliminary Information MT90710

Pin Description

Pin # Name Description

10 STo5 Serial, 32 Channel, 2.048 Mb/s Lin k 5 (Outpu t Type 3). Output is active only when

the receiver detects the synchronization pattern on RxDATA input stream; output is high

impedance during loss of synchronizat ion. 11 V 12 V

13 C4o

Positive Po wer Supply. Nominally 5 volts.

Power Sup pl y Grou nd. Nominal ly 0 volts .

4.096 MHz Clock (Output Type 3). Used by the transmit PLL. This clock is the input

C40i (40.96MHz, see pin 18) master clock divided by 10 (inverted) and is fed back to

the external PLL circuit as a reference. 14 C4REF o 4.096 MHz Reference Cloc k (Ou tpu t Type 3). Used by transmit PLL. When in control-

ler mode this clock is derived from the system C4b

(4.096 MHz) clock input (see pin

57). When in peripheral mode this clock is extracted from the receive data on the fiber

port.

15,16,

NC No Internal Connection.

17 18 C40i Transmit 40.96 M H z Clock (In put Type 2). Derived from the transmit PL L. This is the

master clock used by the device. 19 STi1 Seri al , 32 Channel , 2.048 M b/s Lin k 1 (Inp ut Type 1). 20 STi2 Seri al , 32 Channel , 2.048 M b/s Lin k 2 (Inp ut Type 1). 21 V 22 V

Power Sup pl y Grou nd. Nominal ly 0 volts .

Positive Po wer Supply. Nominally 5 volts.

23 STi3 Seri al , 32 Channel , 2.048 M b/s Lin k 3 (Inp ut Type 1). 24 STi4 Seri al , 32 Channel , 2.048 M b/s Lin k 4 (Inp ut Type 1). 25 STi5 Seri al , 32 Channel , 2.048 M b/s Lin k 5 (Inp ut Type 1). 26 STi6A Serial, 32 Channel , 2.048 Mb/s Lin k 6A (Input Type 1). 27 STi6B Serial, 32 Channel , 2.048 Mb/s Lin k 6B (Input Type 1). 28 STi7 Seri al , 32 Channel , 2.048 M b/s Lin k 7 (Inp ut Type 1). Only channels 9 - 31 are avail-

able for user data transfer (1.47 2 Mb/s ). Data input on channel s 0 - 8 (0.576 Mb/s) is

ignored by the device. This bandwidth is reserved for fiber overhead information. 29 E20i Receiver 20.96 MHz Clock (Input Type 2). Extracted clo ck from the receive data

stream. Divided internally by 5 and phase corrected to frame synch pattern to produce

internal 2.048 MHz data clock for parsing the receive STi streams. 30 NC No Internal Connection. 31 V

Power Sup pl y Grou nd. Nominal ly 0 volts . 32 NC No Internal Connection. 33 V

Positive Po wer Supply. Nominally 5 volts. 34 NC No Internal Connection. 35 RxDATA Re ceiv e 4B/5B, NRZI Enc ode d Seria l Data (Input Type 1). 36 RLED " Rem o te Sync" LED Driver (Op en Col lector, Output Type 3). Drives the "Remote

Sync" LED on/off at approxi mately a 4 Hz rate when the remote interface is not syn-

chronized. Active only when the local interface is synchronized. 37 FBOE

Frame Buffer Ram Enab le (Ou tput Type 2). Generates a low going strobe during

valid RAM read access.

5-5

MT90710 Preliminary Information

Pin Description

Pin # Name Description

38 MODE2 Operatin g Mode Sele ct 2 (Input Type 1). See Table 1. 39 MODE1 Operatin g Mode S ele ct 1 (Inpu t Type 1). See Table 1. 40 MODE0 Operatin g Mode Sele ct 0 (Input Type 1). See Table 1. 41 STo0 Serial, 32 Channel, 2.048 Mb/s link 0 (O utput Type 3). Output is active only when

receiver detects the synchronization pattern on RxDATA input stream; output is high

impedance during loss of synchronizat ion. 42 V 43 V

Positive Power Supply. Nominally 5 volts.

Power Supply Ground. Nominally 0 volts .

44 STo2 Serial, 32 Channel, 2.048 Mb/s link 2 (O utput Type 3). Output active only when

receiver detects the synchronization pattern on RxDATA input stream; high impedance

output during loss of synchronization. 45 STo3 Serial, 32 Channel, 2.048 Mb/s link 3 (O utput Type 3). Output active only when

receiver detects the synchronization pattern on RxDATA input stream; high impedance

output during loss of synchronization. 46 STo4 Serial, 32 Channel, 2.048 Mb/s link 4 (O utput Type 3). Output active only when

receiver detects the synchronization pattern on RxDATA input stream; high impedance

output during loss of synchronization. 47 FBWE

Frame Buffer RAM Write Enable (Outpu t Type 2). Generates a low going strobe dur-

ing valid RAM write access. 48 STo1 Serial, 32 Channel, 2.048 Mb/s link 1 (O utput Type 3). Output active only when

receiver detects the synchronization pattern on RxDATA input stream; high impedance

output during loss of synchronization. 49 F0 b

System 8 kHz Reference Frame Pulse (Bi-directi on al; I npu t and Outpu t Types 3).

When in controller mode this is an input accepting the system referen ce pulse. In

peripheral mode this is an output supplying the system an 8 kHz reference frame pulse. 50 DOUT32K Asynchronous 32 kHz Signal 1 (Open Collector, Output Type 3). Sourced from the

far-end DIN32K input. 51 TxDATA Transmit 4B/5B, NRZI Encoded Serial Data (Output Type 3). 52 V

Power Supply Ground. Nominally 0 volts . 53 IC Internally Connected (Output Type 1). Drives continuous logic 1. Leave open circuit. 54 V

55 POR

Positive Power Supply. Nominally 5 volts.

Power On Reset (Input Type 2). Active low.

56 FBDATA 7 Frame Buffer Data Bit 7 (Bidirectional; Input Type 1 and Output Type 2). Data bit 7. 57 C4b

4.096 MHz Reference Clock (Bidirecti on al; Inpu t and Outp ut Types 3). Input used

by PLL in controller mode and derived from the system. In peripheral mod e this is an

output supplying the system 4. 096 MH z reference cloc k. 58 FBDATA 6 Frame Buffer Data Bit 6 (Bidirectional; Input Type 1 and Output Type 2). Data bit 6. 59 FBDATA5 Frame Buffer Data Bit 5 (Bidirectional; Input Type 1 and Output Type 2). Data bit 5. 60 DIN8K0 Asynchronous 8 kHz Signal 0 (Input Type 1). Transmitted to the far-end DOUT8K0

output. 61 FBDATA 4 Frame Buffer Data Bit 4 (Bidirectional; Input Type 1 and Output Type 2). Data bit 4.

5-6

Preliminary Information MT90710

Pin Description

Pin # Name Description

62 DIN32K Asynchron ou s 32 kH z Signal (Inp ut Type 1). Transmitted to the far-end DOU T32K

output. 63 V 64 V

Positive Po wer Supply. Nominally 5 volts.

Power Sup pl y Grou nd. Nominal ly 0 volts .

65 FBDATA 3 Frame Buffer Data Bit 3 (Bidirectional; Input Type 1 and Output Type 2). Data bit 3. 66 STi0 Seri al , 32 Channel , 2.048 M b/s Lin k 0 (Inp ut Type 1). 67 FBDATA 2 Frame Buffer Data Bit 2 (Bidirectional; Input Type 1 and Output Type 2). Data bit 2. 68 DIN8K1 Asynchronous 8 kHz Signal 1 (Input Type 1). Transmitted to the far-end DOUT8K1

output. 69 FBDATA 1 Frame Buffer Data Bit 1 (Bidirectional; Input Type 1 and Output Type 2). Data bit 1. 70 LLED "Local Sync" LED Driver (Open Col l ector, Output Type 2). Drives the "Local Sync"

LED on/off at app ro ximat ely a 4 Hz rate when the local interface is not in

synchronization. 71 FBDATA 0 Frame Buffer Data Bit 0 (Bidirectional; Input Type 1 and Output Type 2). Data bit 0. 72 RESET Reset Control (Input Type 1). 73 IC Internally Connected. 74 V

Positive Po wer Supply. Nominally 5 volts. 75 NC No Internal Connection. 76 V

Power Sup pl y Grou nd. Nominal ly 0 volts . 77 FBADDR0 Frame Buffer RAM Address Bit 0 (Outpu t Type 2). 78 FBADDR1 Frame Buffer RAM Address Bit 1 (Outpu t Type 2). 79 FBADDR2 Frame Buffer RAM Address Bit 2 (Outpu t Type 2). 80 FBADDR3 Frame Buffer RAM Address Bit 3 (Outpu t Type 2). 81 FBADDR4 Frame Buffer RAM Address Bit 4 (Outpu t Type 2). 82 FBADDR5 Frame Buffer RAM Address Bit 5 (Outpu t Type 2). 83 FBADDR6 Frame Buffer RAM Address Bit 6 (Outpu t Type 2). 84 STo6B Serial, 32 Channel , 2.048 Mb/s Lin k 6B (Outpu t Type 3). Output active only when

receiver detects the synchronization patt ern on RxDATA input stream; high impedance

output during loss of synchronization.

Notes:

All unused inputs should be connected to logic high or low unless otherwise stated. All outputs should be left open circuit when not used. All output types are CMOS with CMOS logic levels (see DC Electrical Characteristics for Type drive capability). Input Type 1 has TTL compatible logic levels, Type 2 has CMOS compatible logic levels and Type 3 has TTL Schmitt trigger compatible

logic levels (see DC Electrical Characteristics).

Overview

transmission allows large bandwidth inter-shelf or, in distributed systems, inter-node communication by

The MT90710 multiplexes multiple Serial Telecom (ST-BUS timing, Figure 7) links onto a single 20 MHz loop to facilitate point-to-point data transport requirements. The MT90710 connects easily with standard Fiber Optic interfaces to form a complete electric to photonic conversion circuit. Optical

eliminating multiple data busses, cable inter-connect and the attendant driver interfaces. The final result is a simple physical interface free of the radiated emissions and background noise susceptibility problems encountered in copper-wired environments.

5-7

MT90710 Preliminary Information

Frame Pulse

Fiber Timeslot

255 0 1 2 3 4 5 6 7 8 9 .......... 246 247 248 249 250 251 252

Channel Assignment

ST6 Ch0 ST5 Ch0 ST4 Ch0 ST3 Ch0 ST2 Ch0 ST1 Ch0 S T0 Ch0 ST6 Ch1ST7 Ch0 ST7 Ch1

4B/5B Encoded Data Bit Assignment

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Figure 3 - Fiber Timeslot Assignment

The MT90710 provides 15.808 Mb/s clear channel, user bandwidth in both transmit and receive directions. In addition, two 8 kHz sampled signals and one 32 kHz sampled signal are encoded and transported over the loop as additional user bandwidth. These asynchronous signals, in combination with overhead information and clear channel bandwidth produce an aggregate data rate of 16.384 Mb/s. After encoding (4B/5B) the final transmitted baud rate is 20.48 Mbaud.

Transmit

The transmit data interface consists of nine ST-BUS input links and three asynchronously sampled input signals. These are STi0 - STi5, STi6A and STi6B, STi7, DIN8K0, DIN8K1 and DIN32K. Six ST-BUS input links, STi0-5, each provide 2.048 Mb/s transparent transmission bandwidth. With ST6MUX Mode disabled STi6A is also a 2.048 Mb/s link while STi6B is not used (see ST6MUX description). The first nine channels of the STi7 input are ignored leaving the remaining 23 channels for user bandwidth. This allows a total of 15.808 Mb/s clear bandwidth for application use. The first nine (576 kb/s) channels of STi7 are made available for transmitting the three asynchronous signals combined with fiber overhead information. This overhead is automatically compiled in the transmit interface and inserted into these timeslots for transmission over the fiber interface.

Once compiled, the contents of the transmit data bandwidth is first 4B/5B encoded, then NRZI encoded before it is applied to the transmit fiber interfac e dr i ve r v i a Tx DATA. 4B/5B en s ur e s th a t th e NRZI encoded data will contain a minimum of two transitions per baud. This is sufficient to allow the far end to extract the embedded clock information. As a result of 4B/5B encoding the information bandwidth of 16.384 Mb/s increases to a total baud rate of

20.48 MBaud/s at the fiber interface.

Incoming ST-BUS link data is latched at the mid-bit position of the internal timeslot. Since there is a phase difference between the internal and external timeslots, due to the operation of the PLL, latching occurs at approximately the 3/4 bit position of the external timeslot when in Controller mode. In Peripheral mode data is latched at the midpoint of the timeslot. Asynchronous signals DIN8K0-1 are sampled once per frame (8,000 times per second) and are intended to convey relatively static information where a state transition is not time critical enough that a resolution of one frame is detrimental. Asynchronous signal DIN32K is sampled four times per frame (32,000 times per second) and may be used to transport data at a higher rate than the other two asynchronous inputs. As an example, this sampling rate is sufficient to support 19.2K Baud RS-232 signals (TTL levels) so that remote programming or loop maintenance may be performed.

Overhead information includes a frame synchronization byte, an error count and a checksum calculated on the previous frame of transmitted data.

5-8

Preliminary Information MT90710

ST-BUS input data latched here

C20o

(Pin 6)

Bit Cell

C4o

(Pin 13)

122 ns

FBOE

170.8ns

FBWE

FBADDR

FBDATA

WR ADDR RD ADDR

Figure 4 - Fram e Buf fer Mem ory Typical Tim ing

Receive

The 4B/5B and NRZI encoded data from the receive fiber interface is NRZI decoded and the frame synchroni zati o n in fo rma ti on is extra c te d. After 4B/5 B decoding the remaining data is frame aligned either to the system frame pulse (when in Controller Mode) or to the extracted frame pulse (when in Peripheral Mode). After alignment, the received dat a package is disassembled into the clear channel ST-BUS streams, the asynchronous signals and the overhead/status information. When ST6MUX mode is disabled, received 15.808 Mb/s bandwidth is made available on STo0-STo6A and the last 23 channels of STo7. The asynchronous signals are presented on DOUT8K0, DOUT8K1 and DOUT32K while the received overhead information, as well as local status information, is presented on ST07 in channels 0 to 7.

Control

48.8ns

WR ADDR

RD ADDR

receive data interface when it’s in peripheral mode. Switching between these two primary references is automatic and under the control of the MODE0-2 pins. The selected reference is fed to the external PLL from the C4REFo output pin. The MT90710 also divides the 40.96 MHz master clock by ten and supplies this secondary reference to the external PLL on C4o

for com pa r is on to th e pr i ma r y re fe r en c e.

The PLL creates a 40.96 MHz master clock from a

4.096 MHz reference by multiplying by 10 and attenuates jitter present on the extracted reference.

The master clock is divided down to create internal clocks, external ST-BUS clocks (when in peripheral mode) and timeslot counters.

Control signals are also created for the transmitter and receiver. The transmitter timeslot counter is synchronized to the backplane frame pulse while the receiver timeslot counter is sync to the extracted synchron iza ti on p u l se .

An external, 40.96 MHz PLL provides the master clock (C40i) for the MT90710. This PLL uses either the system ’s C4b

clock (pin 57) for reference when

it’s in controller mode or the extracted clock from the

Frame Buffer

To re-align the received data from the fiber interface to the system, or node, a frame reference buffer is

5-9

MT90710 Preliminary Information

required. This is implemented using an external 8x8 static RAM (35 ns). Only 256 bytes are used of the 8K total. RAM address and data (FBADDR0-7 and FBDATA0-7) signals are generated along with an output enable strobe (FBOE strobe (FBWE

Mode # Mode 2 Mode 1 Mode 0 ST6MUX Configuration

0 0 0 0 ENABLED CONTROLLER 1 0 0 1 ENABLED PERIPHERAL 2 0 1 0 not used not used 3 0 1 1 DISABLED CONTROLLER 4 1 0 0 not used not used 5 1 0 1 not used not used 6 1 1 0 not used not used 7 1 1 1 DISABLED PERIPHERAL

) and a write enable

Table 1 - Operational Mo de Sele ct

ST-BUS Interface

The first nine STo7 channels are reserved for overhead information:

STo7 Channel

Function 0 not available 1 not available 2 Reserved 3 Local error count

(most significant byte) 4 Local error count

(least significant byte) 5 Reserved 6 Remote error count

(most significant byte) 7 Remote error count

(least significant byte) 8 synchronization detect

(see STo7 channel 8 definition)

STo7 Channel 8 Definition:

Overhead Inform ation

Fiber In te rfa ce

Eight of the 256 fiber channels are reserved for overhead information. These are fiber channels:

Channel #

0 Frame Alignment 8 Asynchronous signal transfer and

16 Checksum of previous frame 24 Reserved 32 Reserved 40 Reserved 48 Re mote error count most significant byte 56 Remote error count least significant byte

Function

synchronization detect

B7 remote receiver is in frame synch

when logic 1

B6 Local receiver is in frame synch

when logic 1 B5, B4, B3 Reserved B2, B1, B0 Reserved

ST6MUX

ST-BUS to Fiber

When ST6MUX is enabled the STi6A and STi6B input streams are alternately multiplexed onto the fiber link. (i. e., only half of the bandwidth of each link is utilized). The transmit pattern at the fiber interface is:

STi6A-Chan0,STi6B-Chan1,STi6A-Chan2,STi6B-Chan3,..., STi6B-Chan29,STi6A-Chan30,STi6B-Chan31

Multiplexed Strea m

STo6A Data from ST i6A ST o6B D ata from ST i6B

5-10

Chan 0 Chan 1 Chan 2 Chan 3 Chan 4 Chan 5 ..... Chan 28 Chan 29 Chan 30 Chan 31

Chan 0 Chan 0 Chan 2 Chan 2 Chan 4 Chan 4 ..... Chan 28 Chan 28 Chan 30 Chan 30

Chan 1 Chan 1 Chan 3 Chan 3 Chan 5 Chan 5 ..... Chan 29 Chan 29 Chan 31 Chan 31

Ta bl e 2 - ST6MUX Ch ann el Assign m ent

Preliminary Information MT90710

CORRECT SYNC SET SYNC = LAST STATE

STATE 1

CORRECT SYNC SET SYNC = FALSE

INCORRECT SYNC

SET SYNC = LAST STATE

STATE 2

STATE 0

INCORRECT SYNC

SET SYNC = FALSE

INCORRECT SYNC

SET SYNC = FALSE

Figure 5 - State Diagram

Fiber to ST-BUS

When ST6MUX is enabled the STo6A and STo6B output streams are comprised of the demultiplexed information received from the fiber link. The received data is duplicated on two channels since the ST-BUS channels support twice the bandwidth of the data from the incoming fiber link. See Table 2.

INCORRECT SYNC SET SYNC = TRUE

STATE 3

CORRECT SYNC SET SYNC = TRUE

approximately a 4 Hz rate when the far-end is out of synchronization but the near-end is synchronized. If the near-end is not synchronized this output is inactive.

The open collector LLED output (pin 70) will cause an LED, pulled up to +5 volts, to flash at approximately a 4 Hz rate when the near-end is out of synchronization.

When ST6MUX is disabled the STi6B and STo6B ports are not operational. The STi6A and STo6A ports operate as clear 2.048 MHz links in the same manner as STi/o links 0 to 5.

Fiber Loop Synchronization

A receiver is declared in synchronization after detection of three consecutive frames containing a valid sync pattern. Once synchronized a receiver will lose sync if a valid sync pattern is not detected in two of four consecutive frames (refer to Figure 5).

LED Control

The open collector RLED output (pin 36) will cause an LED, pulled up to +5 volts, to flash at

Checksum Generator

Checksum =

255

DATAiC

∑

i 1=

Where i-1 is the carry out from the previous operation. The checksum is calculated on all 255 channels except on channel 0 where the frame synchronization code is transported. During this channel the previous checksum is stored and the register initialized for the next calculation.

i1–

5-11

MT90710 Preliminary Information

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

AAAA

AAA

Transmit Amplifier

and Fiber Transmitter

AAA

Fibre Receiver

and Amplifier

and

Rx Clock Recovery

Bit Regeneration

TxDATA

RxDATA

RAM

8K x 8

Frame Buffer

Checksum

STi0

STi1

Framesynch

MUX

STi2

STi3

TEM

Frame

Buffer

Alignment

Controller

and Exte rna l

Frame Buffer

Control Signals

Figure 6 - Typical Fibre Interface Application

Clock

4B/5B and NRZI

Encode

Parallel-to-Serial

Shift

NRZI Decode

Synch Detect

Serial-to-Parallel

Shift

4B/5B Decode

Error C heck

DEMUX

STi4

STi5

STi6

STi7

STo0

STo1

STo2

STo3

STo4

STo5

STo6

STo7

NTERFAC

Interface

PLL

Clock

Transmit

5-12

Preliminary Information MT90710

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 DC Sup ply Voltage V 2 In put Voltage V 3 DC Inpu t Current I 4 Storage Temperature T

stg

- 0.3 7 V

VSS - 0.3 VDD + 0.3 V

+/- 50 m A

- 65 + 150 °C

* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.

Recommended Operating Conditions

Characteristics Sym Min Typ M ax Units Test Cond itions

1 Input 2 Operating Temperature T

Voltage V

DC Electrical Characteristics - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 Supply Current operating I 2 Input HIGH voltage (TT L) V 3 Input LOW voltage (T TL) V 4 Input HIGH voltage (CMOS ) V

IHT

ILT

IHC

0.7V

4.5 5.5 V 0+70°C

) unless otherwise stated.

‡

Max Units Test Conditions

230 276 mA

2.0 V In put Type 1

0.8 V Input Type 1

V In put Type 2

5 Input LOW voltage (CM O S) V

6 Positive threshold (schmitt) V 7 Negative threshold (schmitt) V 8 Hysteresis V 9 Input leakage current I

IH/IIL

ILC

0.8 V In put Type 3

0.5 V In put Type 3

0.3V

V In put Type 2

2.0 V Input Type 3

150 µAVDD=5.5V ,

IN=VSS

to V

10 High level output voltage VOH 3.7 V All output t yp es @ max I 11 Low level output voltage V 12 Output Current I

13 High impedance leakage I

14 Output capacit ance C 15 Input capaci tance C

‡ Typical figures are at 25°C and are for desi gn aid only: not guarantee d and not subje ct to producti on testing.

O12

1 4

720pF

0.4 V All output typ es @ max I mA

mA mA

Output Type 1 Output Type 2 Output Type 3

20 µAVDD=5.5V ,

IN=VSS

to V

20 pF

5-13

MT90710 Preliminary Information

AC Electrical Characteristics† - ST-BUS Timing

Voltages are with respect to ground (VSS) unless otherwise stated.

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Frame Pulse width t 2 F ram e Pulse setup time t 3 Frame Pulse hold time t 4 STo delay Active to Active t 5 S Ti setup time t 6 STi hold time t 7 Clock period 8 CK Input Low t 9 CK Input High

10 Clock Rise/Fall Time t

† Timing is over recommended temperature & power supply voltages (V ‡ Typical figures are at 25°C and are for de sign aid only: not guaran teed and not subje ct to producti on testing.

2.0V

F0i

0.8V

F0iW

F0iH

F0iW

F0iS

F0iH

DAA

STiS

STiH

C4i

r,tf

10 190 ns 20 190 ns

20 ns 20 ns

200 244 300 ns

85 122 150 ns 85 122 150 ns

244 ns

45 100 ns CL=150 pF

10 ns

=5V±10% , VSS=0V, TA=0 t o 70°C).

C4i

STo

STi

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

Ch. 31 Bit 0

F0iS

DAA

Ch. 0 Bit 7

STiS

Ch. 0 Bit 7

Figur e 7 - S T-BUS Ti ming

STiH

Ch. 0 Bit 6

Ch. 0 Bit 5

5-14

Datasheet MT90710AP Datasheet (MITEL)

Specifications and Main Features

Frequently Asked Questions

User Manual