Datasheet MT8980DE, MT8980DP Datasheet (MITEL)

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Page 1

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ISO-CMOS ST-BUS FAMILY

MT8980D

Digital Switch

Features

• Mitel ST-BUS compatible

• 8-line x 32-channel inputs

• 8-line x 32-channel outputs

• 256 ports non-blocking switch

• Single power supply (+5 V)

• Low power consumption: 30 mW Typ.

• Microprocessor-control interface

• Three-state serial outputs

ISSUE8 March 1997

Ordering Information

MT8980DE 40 Pin Plastic DIP MT8980DP 44 Pin PLCC

-40°C to +85°C

Description

This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Ofﬁce. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT8980 provides microprocessor read and write access to individual ST-BUS channels.

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7

Serial

Parallel

Converter

Data

Memory

F0i

C4i

Frame

Counter

Control Register

Control Interface

CS R/W A5/A0DTA D7/

Figure 1 - Functional Block Diagram

Output

MUX

Connection

Memory

CSTo

ODE

Parallel

Serial

Converter

STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7

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MT8980D

STi3 STi4 STi5 STi6 STi7 VDD

F0i

C4i

A0 A1 A2

7 8 9 10 11 12 13 14 15 16 17

Pin Description

Pin #

DIP44PLCC

Name Description

STi1

STi2

65432

1819202122

DTA

STi0

44 PIN PLCC

ODE

CSTo

W R/

STo1

STo0

4443424140

2425262728

STo2

STo3

STo4

STo5

STo6

STo7

VSS

Figure 2 - Pin Connections

DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7

VDD

C4i

1 2 3 4

5 6

7 8

9 10 11

F0i

12 13

40 PIN PLASTIC DIP

40 39

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7

12DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the

microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A 909 Ω, 1/4W, resistor is recommended to be used as a pullup.

2-4 3-5 STi0-

STi2

5-9 7-11 STi3-

STi7

10 12 V

ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams.

ST-BUS Input 3 to 7 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams.

Power Input. Positive Supply.

11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the

2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i.

12 14 C4i 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this

clock.

13-1515-17A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor

interface.

16-1819-21A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor

interface.

19 22 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor

interface.

20 23 R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor

interface - high for read, low for write.

21 24 CS Chip Select (Input). This is the input for the active low chip select on the microprocessor

interface

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Pin Description (continued)

Pin #

DIP44PLCC

22-2425-27D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the

25-2929-33D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the

Name Description

microprocessor interface.

MT8980D

30 34 V

31-3535-39STo7-

STo3

36-3841-43STo2-

STo0

39 44 ODE Output Drive Enable (Input).If this input is held high, the STo0-STo7 output drivers function

40 1 CSTo Control ST-BUS Output (Complementary Output). Each frame of 256 bits on this ST-BUS

6, 18,

28,

Power Input. Negative Supply (Ground).

ST-BUS Output 7 to 3 (Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams.

ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams.

normally . If this input is lo w, the ST o0-STo7 output drivers go into their high impedance state . NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control.

output contains the values of bit 1 in the 256 locations of the Connection Memory High.

NC No Connection.

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MT8980D

Functional Description

In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems.

In accordance with these trends, MITEL has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future.

The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames which contain 32 8-bit channels. MITEL manufactures a number of devices which interface to the ST-BUS; a key device being the MT8980 chip.

The MT8980 can switch data from channels on STBUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-BUS outputs (Message Mode). To the microprocessor, the MT8980 looks lik e a memory peripheral. The microprocessor can write to the MT8980 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT8980, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established.

By integrating both switching and interprocessor communications, the MT8980 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture.

Hardware Description

Serial data at 2048 kbit/s is received at the eight STBUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., MITEL’s MT8964).

This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory . Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip.

Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes.

The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory.

A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION

0 1 1

•

* Writing to the Control Register is the only fast transaction.

†

Memory and stream are speciﬁed by the contents of the Control Register.

2-6

X 0 0

•

X 0 0

•

0 0

•

X 0 0

•

X 0 1

•

Figure 3- Address Memory Map

00 - 1F

20 21

•

Control Register *

Channel 0 Channel 1

Channel 31

† †

•

†

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MT8980D

The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly.

The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8980s to be constructed. It also controls the CSTo pin.

All ST-BUS timing is derived from the two signals C4i and F0i.

Software Control

The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.

If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register.

The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits deﬁne one of the ST-BUS input or output streams.

Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low.

The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values.

(unused)

Mode

Control

Bits

76543210

Memory

Select

Bits

Stream

Address

Bits

BIT NAME DESCRIPTION

7 Split

Memory

When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.

6 Message

Mode

When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output.

5 (unused)

4-3 Memory

Select Bits

0-0 - Not to be used 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High

2-0 Stream

Address

Bits

The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations.

Figure 4 - Control Register Bits

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MT8980D

No Corresponding Memory

- These bits give 0s if read.

76 5432 10

Per Channel

Control Bits

BIT NAME DESCRIPTION

2 Message

Channel

When 1, the contents of the corresponding location in Connection Memory Low are output on the location’s channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location’s channel and stream.

1 CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output

ﬁrst.

0 Output

Enable

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location’s channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it.

Figure 5 - Connection Memory High Bits

Stream

Address

Bits

76 5432 10

Channel Address

Bits

BIT NAME DESCRIPTION

7-5* Stream

Address

Bits*

4-0* Channel

Address

Bits*

The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most signiﬁcant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.

The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is deﬁned by bits 7, 6 and 5.). Bit 4 is the most signiﬁcant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to deﬁne the source of the connection which is output on the channel and stream associated with this location.

Figure 6 - Connection Memory Low Bits

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MT8980D

If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated STBUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low deﬁne the ST-BUS input stream and channel where the byte is to be found (see Fig. 6).

If the ODE pin is low, then all ser ial outputs are highimpedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).

Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any exter nal control circuitr y the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output ﬁrst in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0.

Applications

Use in a Simple Digital Switching System

Fig. 7 shows the interface between the MT8980s and the ﬁlter/codecs. Fig. 8 shows the position of these components in an example architecture.

The MT8964 ﬁlter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and ST-BUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT8980, which is used as a digital speech switch.

The MT8964 is controlled by the ST-BUS input D originating from the bottom MT8980, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom MT8980.

Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single MT8980 as a speech switch and a second MT8980 for communication with the line interface circuits.

A larger digital switching system may be designed by cascading a number of MT8980s. Fig. 9 shows how four MT8980s may be arranged in a non-blocking conﬁguration which can switch any channel on an y of the ST-BUS inputs to any channel on the ST-BUS outputs.

Figs. 7 and 8 show how MT8980s can be used with MT8964s to form a simple digital switching system.

STo0 STi0

8980 used

speech

switch

8980 used

in message

mode for

control and

signalling

MT8980

STo0 STi0

Line Interface Circuit with 8964 Filter/Codec

MT8964

Filter/Codec

Signalling

Logic

Line Driver

and

2- to 4-

Wire

Converter

Figure 7 - Example of Typical Interface between 8980s and 8964s for Simple Digital Switching System

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MT8980D

Line Interface Circuit

with Codec (e.g. 8964)

Line 1

Speech

Switch

8980

Controlling

Micro-

Processor

Control &

Signalling

8980

STo0-7

STi0-7

Figure 8 - Example Architecture of a Simple Digital Switching System

Application Circuit with 6802 Processor

Fig. 10 shows an example of a complete circuit which may be used to evaluate the chip.

For convenience, a 4 MHz crystal oscillator has been used rather than a 4.096 MHz clock, as both are within the limits of the chip’s speciﬁcations. The RC delay used with the 393 counters ensures a sufﬁcient hold time for the FP signal, but the values used may have to be changed if faster 393 counters become available.

STi0-7

•

Repeated for Lines

Line Interface Circuit

with Codec (e.g.8964)

• Repeated for Lines

2 to 255

Line 256

•

2 to 255

The chip is shown as memory mapped into the MEK6802D3 system. Chip addresses 00-3F correspond to processor addresses 2000-203F. Delay through the address decoder requires the VMA signal to be used twice to remove glitches. The MEK6802D3 board uses a 10KΩ pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a processor.

2-10

8980

IN 0/7

IN 8/15

STi0/7 STo0/7

8980

STi0/7 STo0/7

8980

STi0/7 STo0/7

8980

STi0/7 STo0/7

OUT 0/7

OUT 8/15

Figure 9 - Four 8980s Arranged in a Non-Blocking 16 x 16 Conﬁguration

Page 9

MT8980D

MEK6802D3 System

909 Ω,

1/4W

5V 5V

DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7

VDD

F0i

C4i

A0 A1 A2 A3 A4 A5

R/W

D7-D0

A15-A0

VMA

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8980

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS

A15 A14 A13

0V 0V

VMA

A12 A11 A10

0V 0V

A9 A8 A7 0V 0V

VMA

0V 0V 0V

1 2 3 4 5

6 7 8

1 2 3 4 5

6 7 8

1 2 3 4 5

6 7 8

1 2 3 4 5

6 7 8

HCT

138

HCT

138

HCT

138

HCT

138

16 15 14 13 12

11 10 9

16 15 14 13 12

11 10 9

16 15 14 13 12

11 10 9

16 15 14 13 12

11 10 9

C4i 0V

1 2 3 4 5 6 7

HCT

393

HCT

393

14 13 12 11 10 9 8

5V 0V

510 Ω

100pF

DTA

C4i

F0i

0V 0V

1 2 3 4 5

6 7 8 9 10

HCT

240

4 MHz

2MΩ

20 19 18 17 16

15 14 13 12 11

5V 0V MR

Figure 10 - Application Circuit with 6802

2-11

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MT8980D

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1VDD - V 2 Voltage on Digital Inputs V 3 Voltage on Digital Outputs V 4 Current at Digital Outputs I 5 Storage Temperature T 6 Package Power Dissipation P

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 Operating Temperature T 2 Positive Supply V

3 Input Voltage V

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

-40 +85 °C

4.75 5.25 V

DC Electrical Characteristics - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 2 Input High Voltage V 3 Input Low Voltage V 4 Input Leakage I 5 Input Pin Capacitance C 6 7 Output High Current I 8 Output Low Voltage V

9 Output Low Current I 10 High Impedance Leakage I 11 Output Pin Capacitance C

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Supply Current I

I N P U T S

Output High Voltage V

O U T P U T S

2.0 V

2.4 V IOH = 10 mA 10 15 mA Sourcing. VOH=2.4V

5 10 mA Sinking. VOL = 0.4V

‡

Max Units Test Conditions

) unless otherwise stated.

‡

6 10 mA Outputs unloaded

0.8 V 5 µAVI between VSS and V

8pF

0.4 V IOL = 5 mA

5 µAVO between VSS and V

8pF

-0.3 7 V VSS-0.3 VDD+0.3 V VSS-0.3 VDD+0.3 V

-65 +150 °C

) unless otherwise stated.

40 mA

2-12

Output

Test Point

S1 is open circuit except when testing output levels or high impedance states.

S2 is switched to V

when testing output

levels or high impedance states.

Figure 11 - Output Test Load

Page 11

AC Electrical Characteristics† - Clock Timing (Figures 12 and 13)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

MT8980D

1 2 Clock Width High t 3 Clock Width Low t 4 Clock Transition Time t 5 Frame Pulse SetupTime t 6 Frame Pulse Hold Time t 7 Frame Pulse Width t

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.

NB: Frame Pulse is repeated ever y 512 cycles of C4i.

C4i

F0i

Clock Period* t

I N P U T S

CLK

CTT

FPS

FPH

FPW

220 244 300 ns

95 122 150 ns

110 122 150 ns

20 ns

20 200 ns

0.020 50 µs 244 ns

BIT CELLS

C4i

F0i

2.0V

0.8V

2.0V

0.8V

FPH

Channel 31

Bit o

Figure 12 - Frame Alignment

CLK

CTT

FPS

CHL

CTT

Channel 0

FPH

Bit 7

FPS

FPW

Figure 13 - Clock Timing

2-13

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MT8980D

AC Electrical Characteristics† - Serial Streams (Figures 11, 14, 15 and 16)

Characteristics Sym Min Typ‡Max Units Test Conditions

1 2 STo0/7 Delay - High Z to Active t 3 STo0/7 Delay - Active to Active t 4 STo0/7 Hold Time t 5 Output Driver Enable Delay t 6 External Control Hold Time t 7 External Control Delay t 8 9 Serial Input Hold Time t

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25 * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

C4i

STo0/7 Delay - Active to High Z t

O U

T P U

T S

Serial Input Setup Time t

°C and are for design aid only: not guaranteed and not subject to production testing.

Bit Cell Boundary

2.0V

0.8V

SAZ

SZA

SAA

SOH

OED

XCH

XCD

SIS

SIH

20 50 80 ns RL=1 KΩ*, CL=150 pF 25 60 125 ns CL=150 pF 30 65 125 ns CL=150 pF 25 45 ns CL=150 pF

45 125 ns RL=1 KΩ*, CL=150 pF

050 nsC

=150 pF

75 110 ns CL=150 pF

-40 -20 ns

90 ns

2.0V

ODE

0.8V

STo0 to STo7

CSTo

2.4V

0.4V

2.4V

0.4V

2.4V

0.4V

2.4V

0.4V

SOH

SAZ

SZA

SOH

SAA

XCH

XCD

STo0 to STo7

C4i

STi0 to STi7

2.4V

0.4V

OED

Figure 15 - Output Driver Enable

Bit Cell Boundaries

2.0V

0.8V

2.0V

0.8V t

SIS

SIH

Figure 14 - Serial Outputs and External Control

2-14

Figure 16 - Serial Inputs

Page 13

AC Electrical Characteristics† - Processor Bus (Figures 11 and 17)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

MT8980D

1 Chip Select Setup Time t 2 Read/Write Setup Time t 3 Address Setup Time t 4 Acknowledgement Delay Fast

Slow 5 Fast Write Data Setup Time t 6 Slow Write Data Delay t 7 Read Data Setup Time t 8 Data Hold Time Read

Write

9 Read Data To High Impedance t

10 Chip Select Hold Time t 11 Read/Write Hold Time t 12 Address Hold Time t 13 Acknowledgement Hold Time t

† Timing is over recommended temperature & power supply voltages. ‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.

➀

Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.

CSS

RWS

ADS

AKD

FWS

SWD

RDS

DHT

RDZ

CSH

RWH

ADH

AKH

20 0 ns 25 5 ns 25 5 ns

40 100 ns CL=150 pF

2.7 7.2 cycles C4i cycles

➀

20 ns

2.0 1.7 cycles C4i cycles

➀

0.5 cycles C4i cycles➀, CL= 150 pF 20 ns RL=1 KΩ∗, CL=150 pF 20 10 ns

50 90 ns RL=1 KΩ∗, CL=150 pF 0ns 0ns 0ns

10 60 80 ns RL=1 KΩ∗, CL=150 pF

A5 to A0

DTA

D7 to D0

2.0V

0.8V

2.0V

0.8V t

CSS

2.0V

0.8V t

RWS

2.0V

0.8V t

ADS

2.4V

0.4V

2.4V (Read) 2.0V (Write)

0.8V (Read 0.8V (Write)

CSH

RWH

AKD

AKH

ADH

RDS

SWD

FWS

DHT

RDZ

Figure 17 - Processor Bus

2-15

Page 14

MT8980D

Notes:

2-16

Page 15

Package Outlines

e: (lead coplanarity)

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

4) For D & E add for allowable Mold Protrusion 0.010"

Dim

D/E

D1/E

D2/E

e F

20-Pin 28-Pin 44-Pin 68-Pin 84-Pin

Min Max Min Max Min Max Min Max Min Max

0.165 (4.20)

0.090

(2.29)

0.385 (9.78)

0.350

(8.890)

0.290

(7.37)

0.026

(0.661)

0.013

(0.331)

0.020 (0.51)

0.180

(4.57)

0.120 (3.04)

0.395

(10.03)

0.356

(9.042)

0.330 (8.38)

0 0.004 0 0.004 0 0.004 0 0.004 0 0.004

0.032

(0.812)

0.021

(0.533)

0.050 BSC (1.27 BSC)

0.165 (4.20)

0.090 (2.29)

0.485

(12.32)

0.450

(11.430)

0.390 (9.91)

0.026

(0.661)

0.013

(0.331)

0.050 BSC

(1.27 BSC)

0.020 (0.51)

0.180

(4.57)

0.120 (3.04)

0.495

(12.57)

0.456

(11.582)

0.430

(10.92)

0.032

(0.812)

0.021

(0.533)

0.165 (4.20)

0.090 (2.29)

0.685

(17.40)

0.650

(16.510)

0.590

(14.99)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.180 (4.57)

0.120 (3.04)

0.695

(17.65)

0.656

(16.662)

0.630

(16.00)

0.032

(0.812)

0.021

(0.533)

0.165

(4.20)

0.090

(2.29)

0.985

(25.02)

0.950

(24.130)

0.890

(22.61)

0.026

(0.661)

0.013

(0.331)

0.050 BSC (1.27 BSC)

0.020

(0.51)

0.200

(5.08)

0.130

(3.30)

0.995

(25.27)

0.958

(24.333)

0.930

(23.62)

0.032

(0.812)

0.021

(0.533)

(30.10)

(29.210)

(27.69)

(0.661)

(0.331)

0.165 (4.20)

0.090 (2.29)

1.185

1.150

1.090

0.026

0.013

0.050 BSC (1.27 BSC)

0.020 (0.51)

0.200 (5.08)

0.130 (3.30)

1.195

(30.35)

1.158

(29.413)

1.130

(28.70)

0.032

(0.812)

0.021

(0.533)

General-10

Plastic J-Lead Chip Carrier - P-Sufﬁx

Page 16

Package Outlines

n-2 n-1 n

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

8-Pin 16-Pin 18-Pin 20-Pin

DIM

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

C D

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77)

0.008

(0.203)

0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26)

0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)

0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81)

0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52)

0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)

0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356)

0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92)

General-8

Page 17

Notes:

1) Not to scale

2) Dimensions in inches

3) (Dimensions in millimeters)

Package Outlines

n-2 n-1 n

Plastic Dual-In-Line Packages (PDIP) - E Sufﬁx

DIM

C D

E E E

22-Pin 24-Pin 28-Pin 40-Pin

Plastic Plastic Plastic Plastic

Min Max Min Max Min Max Min Max

0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35)

1 1

0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95)

0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558)

0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77)

0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381)

1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2)

0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)

0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02)

0.290 (7.37) .330 (8.38)

0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73)

0.246 (6.25) 0.254 (6.45)

0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)

0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 15° 15° 15° 15°

Shaded areas for 300 Mil Body Width 24 PDIP only

Page 18

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