Datasheet M48T212Y, M48T212V Datasheet (SGS Thomson Microelectronics)

5V/3.3V TIMEKEEPERCONTROLLER

■ CONVERTS LOW POWER SRAM into

NVRAMs

■ YEAR 2000 COMPLIANT (4-Digit Year)

■ BATTERY LOW FLAG

■ INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROLCIRCUIT,BATTERY
and CRYSTAL

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WATCHDOG TIMER

■ CHOICE of WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T212Y: 4.2V ≤ V
– M48T212V: 2.7V ≤ V

■ MICROPROCESSOR POWER-ON RESET

■ PROGRAMMABLE ALARM OUTPUT ACTIVE

in the BATTERY BACKED-UP MODE

■ PACKAGING INCLUDESa44-LEADSOICand

SNAPHATTOP (to be Ordered Separately)

PFD
PFD

≤ 4.5V

≤ 3.0V

SNAPHAT (SH)

Battery

44

1

SOH44 (MH)

Figure 1. Logic Diagram

V

CC

M48T212Y
M48T212V

V

CCSW

DESCRIPTION

The M48T212Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.

Access to all TIMEKEEPERfunctions and the
external RAM is the same as conventional byte­wide SRAM. The16TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Calibration,Alarm, Watchdog,and Flags.
Externally attached static RAMs are controlled by
the M48T212Y/V via the E1

CON

and E2

CON

sig-

nals (see Table 4).
The 44 pin 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con­nection to a separate SNAPHAT housing contain­ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.

A0-A3

EX

W

WDI
RSTIN1
RSTIN2

4

A
E

M48T212Y
M48T212V

G

V

SS

8

DQ0-DQ7

IRQ/FT
RST
E1

CON

E2

CON

V

OUT

AI03019

1/23April 2000

M48T212Y, M48T212V

Figure 2. SOIC Connections

RSTIN1
RSTIN2

RST

NC
NC EX
NC
NC
NC

NC
NC
NC

A3
A2
A1
A0

WDI

E2

CON

DQ1
DQ2

V

SS

1
2
3
4
5
6
7
8

A

9
10

M48T212Y

11

M48T212V

12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

AI03020

V

CC

V

OUT

V

CCSW

IRQ/FT

NC
NC
NC
NC
NC
G
W
NC
NC
E
E1

CON

DQ7
DQ6
DQ5DQ0
DQ4
DQ3
NC

Table 1. Signal Names

A0-A3 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
RSTIN1 Reset 1 Input
RSTIN2 Reset 2 Input
RST Reset Output (Open Drain)
WDI Watchdog Input
A Bank Select Input
E Chip Enable Input
EX External Chip Enable Input
G Output Enable Input
W Write Enable Input
E1

CON

E2

CON

IRQ/FT Int/Freq Test Output (Open Drain)
Vccsw
V

OUT

V

CC

V

SS

NC Not Connected internally

RAM Chip Enable 1 Output
RAM Chip Enable 2 Output

V

Switch Output

CC

Supply Voltage Output
Supply Voltage
Ground

Insertion of the SNAPHAT housing after reflow
prevents potential battery andcrystal damagedue
to the high temperatures required for device sur­face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.

The SOIC and battery/crystal packages are
shipped separately inplastic anti-static tubesor in
Tape & Reel form. For the 44 lead SOIC, the bat­tery/crystal package (i.e. SNAPHAT) part number
is ”M4TXX-BR12SH” (see Table 15).

Caution: Do not placetheSNAPHAT battery/crys­tal topin conductive foam,as this will drain thelith­ium button-cell battery.

Automatic backup and write protection for an ex­ternal SRAM is provided through V
and E2

pins. (Users are urged to insure that

CON

OUT

,E1

CON

voltage specifications, for both the controller chip
and external SRAM chosen, are similar). The
SNAPHAT containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
VCCpower through the V

The chip enable outputs to RAM (E1
E2

) are controlled during power transients to

CON

OUT

pin.

CON

and

prevent data corruption. The date is automatically

adjusted for months with less than 31 days and
corrects forleap years. The internalwatchdog tim­er provides programmable alarm windows.

The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORTTMread/write memory cells
within the static RAM array. Clock circuitry up­dates the clock byteswith current information once
per second. The information can be accessed by
the userin thesame manner asany otherlocation
in the staticmemory array.

Byte 8h isthe clock control register.This byte con­trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con­tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
bit (WDS). Bytes 6h-2hinclude bits that,when pro­grammed, provide for clock alarm functionality.

Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.

2/23

M48T212Y, M48T212V

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

STG

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greaterthan those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (totalthermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOTwave solder SOIC to avoid damaging SNAPHATsockets.

Table 3. Operating Modes

Mode

Deselect

Write
Read
Read

Deselect
Deselect

Note: 1. X = VIHor VIL.

2. V

SO

Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCCOff, Oscillator Off) SNAPHAT

SOIC

(2)

Lead Solder Temperature for 10 sec 260 °C

–40 to 85

–55 to 125

Input or Output Voltages –0.3 to VCC+0.3 V
Supply Voltage M48T212Y

M48T212V

–0.3 to 7

–0.3 to 4.6
Output Current 20 mA
Power Dissipation 1 W

(1)

V

CC

4.5V to 5.5V
or

3.0V to 3.6V

to V

V

SO

PFD

≤ V

SO

= Battery Back-up Switchover Voltage. (See Tables 7A and 7B fordetails).

(min)

(2)

(2)

E G W DQ7-DQ0 Power

V

IH

V

IL

V

IL

V

IL

X X High-Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High-Z Active

X X X High-Z CMOS Standby
X X X High-Z Battery Back-Up

°C

V

Active
Active

Table 4. Truth Table for SRAM Bank Select

Mode V

Select

Deselect High X High High Standby
Deselect

V

SO

Deselect

Note: 1. X = VIHor VIL.

= Battery Back-up Switchover Voltage. (See Tables 7A and 7B fordetails).

2. V

SO

CC

4.5V to 5.5V
or

3.0V to 3.6V

to V

≤ V

PFD

SO

(min)

(2)

(2)

(1)

EX A E1

CON

E2

CON

Low Low Low High Active
Low High High Low Active

X X High High CMOS Standby
X X High High Battery Back-Up

Power

3/23

M48T212Y, M48T212V

Figure 3. Hardware Hookup

A0-A18

0.1µF

5V/3.3V

1N5817

0.1µF

MOTOROLA
MTD20P06HDL

V

CC

E

V

CC

E

A0-Axx

CMOS
SRAM

A0-Axx

CMOS
SRAM

A0-A3

V

V

CC

(1)

A

E

EX

W

G

WDI

RSTIN1

RSTIN2

DQ0-DQ7

V

SS

M48T212Y/V

CCSW

V

OUT

E1

CON

E2

CON

RST

IRQ/FT

Note 2

Note: 1. See description in Power Supply Decoupling and Undershoot Protection.

2. Traces connecting E1

Figure 4. AC Testing Load Circuit

CON

and E2

to external SRAM should be as short as possible.

CON

Table 5. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns

DEVICE

UNDER

TEST

645Ω

Input Pulse Voltages 0 to 3V
Input and Output Timing Ref.Voltages 1.5V

Note that Output Hi-Z is defined as the point where data
is no longer driven.

(1)

(2)

1.75V

AI03239

CLincludes JIG capacitance

Note: 1. DQ0-DQ7

2. E1

CON

and E2

CL= 100pF or 5pF
CL=30pF

CON

4/23

AI03046

M48T212Y, M48T212V

Table 6. Capacitance

(1)

(TA=25°C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Input Capacitance

(2)

Input/Output Capacitance

V

V

OUT

IN

=0V

=0V

10 pF
10 pF

Table 7A. DC Characteristics for M48T212V

(TA= 0 to70°C; VCC= 3V to 3.6V)

Symbol Parameter TestCondition Min Typ Max Unit

(1,2)

I

LI

I

LO

I

CC

I

CC1

I

CC2

I

BAT

V
V

Input Leakage Current 0V ≤ VIN≤ V

(1)

Output Leakage Current
Supply Current Outputs open 4 10 mA

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Battery Current OSC ON 575 800 nA
Battery Current OSC OFF 100 nA
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.0

IH

Output Low Voltage IOL= 2.1mA 0.4 V

V

OL

Output Low Voltage (open drain)

V

V

OHB

I

OUT1

I

OUT2

V

PFD

V

V

BAT Battery Voltage

Note: 1. Outputs deselected.

Output High Voltage

OH

(4)

VOHBattery Back-up I

(5)

V

Current (Active) V

OUT

V

Current (Battery Back-up) V

OUT

Power-fail Deselect Voltage 2.7 2.9 3.0 V
Battery Back-up Switchover Voltage

SO

2. RSTIN1 andRSTIN2 internally pulled-up to V

3. For IRQ/FT & RST pins (Open Drain).

4. Conditioned outputs (E1
rents will reduce battery life.

5. External SRAM mustmatch TIMEKEE PER Controller chip V

CON

-E2

CON

(3)

) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-

CC

0V ≤ V

E=V

OUT

E=V

CC

≤ V

IH

–0.2

CC

IOL= 10mA

I

= –1.0mA

OH

= –1.0µA

OUT2

OUT1>VCC

OUT2>VBAT

–0.3

–0.3 100 µA

2.4 V

2.0 3.6 V

V

–100mV

PFD

3.0 V

through 100KΩ resistor. WDI internallypulled-down toVSSthrough 100KΩ resistor.

CC

specification.

CC

±1 µA
±1 µA

3mA
2mA

V

+ 0.3

CC

0.4 V

70 m A

V

V

5/23

M48T212Y, M48T212V

Table 7B. DC Characteristics for M48T212Y

(TA= 0 to70°C; VCC= 4.5V to 5.5V)

Symbol Parameter Test Condition Min Typ Max Unit

(1,2)

I

LI

I

LO

I

CC

I

CC1

I

CC2

I

BAT

V

IL

V

IH

V

OL

V

OH

V

OHB

I

OUT1

I

OUT2

V

PFD

V

SO

Input Leakage Current

(1)

Output Leakage Current
Supply Current Outputs open 8 15 mA

Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Battery Current OSC ON 575 800 nA

Battery Current OSC OFF 100 nA
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2
Output Low Voltage

Output Low Voltage (open drain)

(3)

Output High Voltage

(4)

VOHBattery Back-up I

(5)

V

Current (Active) V

OUT

V

Current (Battery Back-up) V

OUT

Power-fail Deselect Voltage 4.2 4.35 4.5 V
Battery Back-up Switchover Voltage 3.0 V

0V ≤ V

0V ≤ V

E=V

I

OL

E=V

≤ V

IN

≤ V

OUT

IH

–0.2

CC

= 2.1mA

CC

CC

IOL= 10mA

I

= –1.0mA

OH

= –1.0µA 2.0 3.6 V

OUT2

OUT1>VCC

OUT2>VBAT

–0.3

–0.3

2.4 V

±1 µA
±1 µA

5mA
3mA

V

+ 0.3

CC

0.4 V

0.4 V

100 mA
100 µA

V

V

BAT Battery Voltage

Note: 1. Outputs deselected.

2. RSTIN1 andRSTIN2 internally pulled-up to V

3. For IRQ/FT & RST pins (Open Drain).

4. Conditioned outputs (E1
rents will reduce battery life.

5. External SRAM mustmatch TIMEKEE PER Controller chip V

CON

-E2

) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-

CON

through 100KΩ resistor. WDI internallypulled-down toVSSthrough 100KΩ resistor.

CC

The M48T212Y/Valso hasits own Power-Fail De­tect circuit. This control circuitry constantly moni­tors the supply voltage for an out of tolerance
condition. When VCCis outof tolerance, the circuit
write protects the TIMEKEEPER registerdata and
external SRAM, providing data security in the
midst of unpredictable system operation. As V

CC

falls, the controlcircuitry automatically switchesto
the battery, maintaining data and clock operation
until valid power is restored.

3.0 V

specification.

CC

Address Decoding

The M48T212Y/V accommodates 4 address lines
(A3-A0) which allow access to thesixteen bytes of
the TIMEKEEPERclock registers.All TIMEKEEP­ER registers reside in the controller chip itself. All
TIMEKEEPER registersare accessed by enabling
E (Chip Enable).

6/23

Figure 5. Power Down/Up AC Waveform

V

CC

V

(max)

PFD

V

(min)

PFD

V

SO

tF

tFB

M48T212Y, M48T212V

tR

tRECtRB

INPUTS

OUTPUTS

RST

V

CCSW

VALID VALID

VALID VALID

DON’T CARE

HIGH-Z

AI02638

Table 8. Power Down/Up AC Characteristics

(TA= 0 to70°C)

Symbol Parameter Min Max Unit

V

t

t

FB

t

t

REC

t

RB

(max) to V

F

R

PFD

V

(min) to VSSVCCFallTime

PFD

V

(min) to V

PFD

V

(max) to RST High 40 200 ms

PFD

VSSto V

PFD

(min) VCCFall Time

PFD

(max) VCCRise Time

PFD

(min) VCCRise Time

300 µs

M48T212Y 10 µs
M48T212V 150 µs

10 µs

1 µs

7/23

M48T212Y, M48T212V

Figure 6. Chip Enable Control and Bank Select Timing

EX

tEXPD tAPD

A

tEXPD

E1

CON

E2

CON

Table 9. Chip Enable Control and Bank Select Characteristics

(TA= 0 to70°C)

M48T212Y M48T212V

Symbol Parameter

AI02639

Unit-70 -85

t

EXPD

t

APD

EX to E1
AtoE1

CON

CON

or E2

or E2

(Low or High)

CON

(Low or High)

CON

Min Max Min Max

10 15 ns
10 15 ns

8/23

M48T212Y, M48T212V

READ MODE

The M48T212Y/V executes a read cycle whenev­er W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
the address presented to the M48T212Y/V is in
the range of 0h-Fh, one of the on-board TIME­KEEPER registers is accessed and valid data will
be available to the eight data outputdrivers within
t

after the address input signal is stable, pro-

AVQV

Figure 7. Read Cycle Timing: RTC Control Signals

ADDRESS

E

G

READ READ WRITE

tAVAV

tELQV

tELQX

tGLQV

viding that the E and G access times are also sat­isfied.If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either t
t

for G rather than the address access time.

GLQV

ELQV

for E or

When EX input is low, an external SRAM location
will be selected.

Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten­tion.

tAVAV tAVAV

tAVQV tWHAXtAVWL

tWLWH

W

DQ7-DQ0

Table 10. Read Mode Characteristics

(TA= 0 to70°C)

Symbol Parameter

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. CL= 5pF

Read Cycle Time 70 85 ns
Address Valid to Output Valid 70 85 ns
Chip Enable Low to Output Valid 70 85 ns
Output Enable Low toOutput Valid 25 35 ns

(1)

Chip Enable Low to Output Transition 5 5 ns

(1)

Output Enable Low toOutput Transition 0 0 ns

(1)

Chip Enable High toOutput Hi-Z 20 25 ns

(1)

Output Enable High to Output Hi-Z 20 25 ns
Address Transition to Output Transition 5 5 ns

DATA OUT

VALID

tAXQXtGLQX

DATA OUT

VALID

tGHQZ

DATA IN

VALID

M48T212Y M48T212V

Min Max Min Max

AI02640

Unit-70 -85

9/23

M48T212Y, M48T212V

WRITE MODE

The M48T212Y/V is in the Write Mode whenever
W (Write Enable) and E(Chip Enable) are in alow
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge ofW orE. A write is terminated by the
earlier rising edge of W or E. The addresses must
be heldvalid throughout thecycle. E or W must re­turn high for aminimum of t
or t

fromWrite Enable prior to the initiation of

WHAX

fromChip Enable

EHAX

another read or write cycle. Data-in must be valid
t
t

priorto the end of write and remainvalid for

DVWH

afterward.

WHDX

Figure 8. Write Cycle Timing: RTC Control Signals

ADDRESS

tAVEL

WRITE WRITE READ

tAVAV

tAVEH

tELEH tEHAX

G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated bya low on E and G alow on W will
disable the outputs t

WLQZ

after W falls.

When E is low during the write, one of the on­board TIMEKEEPER registers willbeselected and
data willbe written into the device. When EXis low
(and E is high) an external SRAM location is se­lected.

Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten­tion.

tAVAV tAVAV

tAVWH

tWHAX

tAVQV

E

G

W

DQ0-DQ7

tAVWL

DATA OUT

VALID

tEHDX

tWLWH

tEHQZ tDVEH

DATA IN

VALID

tDVWH

tWHQX tWLQZ

tWHDX

DATA IN

VALID

tGLQV

DATA OUT

VALID

AI02641

10/23

Table 11. Write Mode AC Characteristics

(TA= 0 to70°C)

M48T212Y M48T212V

Symbol Parameter

Min Max Min Max

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

t

WLQZ

t

AVWH

t

AVEH

t

WHQX

Note: 1. CL= 5pF.

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Write Cycle Time 70 85 ns
Address Valid to Write Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
Write Enable Pulse Width 45 55 ns
Chip Enable Low to Chip Enable High 50 60 ns
Write Enable High to Address Transition 0 0 ns
Chip Enable High toAddress Transition 0 0 ns
Input Valid to Write Enable High 25 30 ns
Input Valid to Chip Enable High 25 30 ns
Write Enable High to Input Transition 0 0 ns
Chip Enable High toInput Transition 0 0 ns

(1,2)

Write Enable Low to Output High-Z 20 25 ns
Address Valid to Write Enable High 55 65 ns

Address Valid to Chip Enable High 55 65 ns

(1,2)

Write Enable High to Output Transition 5 5 ns

M48T212Y, M48T212V

Unit-70 -85

DATA RETENTION MODE

With valid VCCapplied, the M48T212Y/V can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCCfalls between V

(max) and V

PFD

PFD

(min).
This is accomplished by internally inhibiting ac­cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCCreturns to nominal levels.

External RAM accessis inhibited in a similar man­ner by forcing E1
This level is within 0.2 volts of the V
and E2

will remain atthis level as long asV

CON

CON

and E2

to a high level.

CON

BAT

.E1

CON

CC

remains at an out-of tolerance condition.
When VCCfalls below the level of the battery

(V

), power input is switched from the VCCpin

BAT

to the SNAPHAT battery and the clock registers
and external SRAM are maintained from the at­tached batterysupply. Alloutputs become highim-

pedance. The V

pin is capable of supplying

OUT

100µA of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCCreturnsto anominal value, write protec­tion continues for 200ms (max) by inhibiting
E1

CON

or E2

CON

.

The RST signal also remains active during this
time (see Figure 5).

Note: Most low power SRAMs on the market to­day can be used with the M48T212Y/V TIME­KEEPER Controller. There are, however some
criteria which should be used in making the final
choice of anSRAM to use.The SRAM mustbe de­signed in a way where the chip enable input dis­ables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to beDon’t
Care once VCCfalls below V

(min). The SRAM

PFD

should also guarantee data retention down to
VCC= 2.0V. The chip enableaccess time must be
sufficient to meet the system needs with the chip
enable output propagation delays included.

11/23

M48T212Y, M48T212V

Figure 9. Alarm Interrupt Reset Waveforms

A0-A3

ACTIVE FLAG BIT

IRQ/FT

1h Fh

Table 12. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 Once per Second
1 1 1 1 0 Once per Minute
1 1 1 0 0 Once per Hour
1 1 0 0 0 Once per Day
1 0 0 0 0 Once per Month
0 0 0 0 0 Once per Year

ADDRESS 0h

HIGH-Z

AI03021

If the SRAM includes a second chip enable pin
(E2), this pin should be tied to V

OUT

.

If data retention lifetime is a critical parameter for
the system,it is important to reviewthe datareten­tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen­erally specify a typical condition for room temper­ature along with a worst case condition (generally
at elevated temperatures). The system level re­quirements will determine the choice of which val­ue to use.

Thedata retentioncurrent valueofthe SRAMs can
then be added tothe I

valueof the M48T212Y/

BAT

V to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT of your choice can then be divided
by thiscurrent todetermine the amount of data re­tention available (see Table 15).

For afurther moredetailed review of lifetime calcu­lations, please see ApplicationNote AN1012.

12/23

Figure 10. Back-Up Mode Alarm Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

AFE bit/ABE bit

AF bit inFlags Register

IRQ/FT

M48T212Y, M48T212V

tREC

HIGH-Z

TIMEKEEPER REGISTERS

The M48T212Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Flag, and Control data. These registers are mem­ory locationswhich contain external(useraccessi­ble) and internal copies of the data (usually
referred to as BiPORTTMTIMEKEEPER cells).

The external copies are independent of internal
functions exceptthat they are updatedperiodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data inBinary Format.

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted beforeclock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cellsin the RAM array areonly data reg­isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.

Updating is halted when a ‘1’ is written to the
READ bit, D6in the Control Register (8h). Aslong
as a‘1’ remains inthat position,updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were

HIGH-Z

AI03622

current at the moment the halt command was is­sued.

All of the TIMEKEEPER registers are updated si­multaneously. Ahalt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a ‘0’.

Setting the Clock

Bit D7 of the Control Register (8h) is the WRITE
bit. Setting the WRITE bit to a ‘1’, like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 13).

Resetting the WRITE bit to a ‘0’ then transfers the
values of alltime registers (Fh-9h, 1h)to theactual
TIMEKEEPER counters andallows normal opera­tion to resume. After the WRITE bit is reset, the
next clock update will occur one second later.

Note: Upon power-up following a power failure,
the READbit will automatically be set to a ‘1’. This
will prevent the clock from updating the TIME­KEEPER registers, and will allow the user to read
the exact time of the power-down event.

Resetting theREAD Bit to a ‘0’ will allow the clock
to update these registers with the current time.
The WRITE Bit will be reset to a ‘0’ upon power­up.

13/23

M48T212Y, M48T212V

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time onthe shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit islocated atBit D7within theSeconds Register
(9h). Setting ittoa ‘1’ stops theoscillator. Whenre­set toa ‘0’, the M48T212Y/Voscillator startswithin
one second.

Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).

SETTING ALARM CLOCK

Address locations 6h-2h contain the alarm set­tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro­grammed to go off whilethe M48T212Y/V isin the
battery back-upto serve asa system wake-upcall.

Bits RPT5-RPT1 putthe alarm in the repeatmode
of operation. Table 12 shows the possible config­urations. Codesnot listedin thetabledefault to the
once per second mode to quickly alert the user of
an incorrect alarm setting.

Note: User must transition address (or toggle chip
enable) to see Flagbit change.

When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm
condition activates the IRQ/FT pin. To disable
alarm, write ’0’ to the Alarm Date registers and
RPT1-4. TheIRQ/FT output isclearedby aread to
the Flags register as shown in Figure 9. A subse­quent read of the Flags register will reset the
Alarm Flag (D6; Register 0h).

The IRQ/FT pin can also be activated in the bat­tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits arereset during power-up, therefore
an alarm generated during power-up will only set
AF. Theuser can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T212Y/V was in the deselect mode
during power-up. Figure 10 illustrates the back-up
mode alarm timing.

WATCHDOG TIMER

The watchdog timer can be used to detect an out­of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.

Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu­tion, where 00=1/16 second, 01=1/4 second,10=1
second, and 11=4 seconds. The amount of time­out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg­ister = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected
resolution.

If theprocessor does not reset the timer within the
specified period, the M48T212Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter­rupt or a microprocessor reset. WDF is reset by
reading the FlagsRegister (Address 0h).

The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a ‘1’, the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog register and
the FT bit will reset to a ‘0’ at the end of a Watch­dog time-out when the WDS bit is set to a ‘1’.

The watchdog timercan bereset by two methods:

1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a write of the
Watchdog Register.

The time-out period then starts over. The WDI pin
should be tied to VSSif not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, theoriginal time-out period
can be written into the Watchdog Register, effec­tively restarting the count-down cycle.

Should the watchdog timertime-out,and the WDS
bit is programmedto output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FTpin. This will also dis­able the watchdog function until it is again pro­grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7;Register 0h).

The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. Ifthe watchdog functionis set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.

14/23

Table 13. TIMEKEEPER Register Map

M48T212Y, M48T212V

Address

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99

Eh 0 0 0 10M Month Month 01-12
Dh 0 0 10 Date Date: Day of Month Date 01-31
Ch 0 FT 0 0 0 Dayof Week Day 01-7

Bh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0h WDF AF Y BL Y Y Y Y Flag

Function/Range

BCD Format

Keys: S = Sign Bit

FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits

VCCSWITCH OUTPUT

Vccsw output goes low when V

OUT

switches to
VCCturning on a customer supplied P-Channel
MOSFET (see Figure 3). The Motorola
MTD20P06HDL is recommended. This MOSFET
in turn connects V
the current requirement is greater than I

to a separate supply when

OUT

OUT1

(see
Tables 7A and 7B). This output may also be used
simply to indicate the statusof the internal battery
switchover comparator, which controls the source
(VCCor battery) of the V

OUT

output.

POWER-ON RESET

The M48T212Y/V continuously monitors VCC.
When VCCfalls to the power fail detect trip point,
the RSTpulls low (open drain) andremains lowon
power-up for 40 to 200msafter VCCpasses V

PFD

AFE =Alarm FlagEnable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF =Watchdog flag
AF = Alarm flag
Y = ‘1’ or ‘0’

The RST pin is an open drain output andan appro­priate pull-up resistor to VCCshould be chosen to
control rise time.

Note: If the RST output is fed back into either of
the RSTIN inputs (for a microprocessor with a bi­directional reset) then a 1kΩ (max) pull-up resistor
is recommended.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T212Y/V provides two independent in­puts which can generate an output reset. The du­ration and function of these resets is identical to a
reset generated by a power cycle. Table 14 and
Figure 12 illustrate the AC reset characteristics of
this function. During the time RST is enabled
(t

R1HRH&tR2HRH

Note: RSTIN1 and RSTIN2 are each internally

.

pulled up to VCCthrough a 100KΩ resistor.

), the ResetInputs are ignored.

15/23

M48T212Y, M48T212V

Figure 11. Calibration Waveform

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

AI00594B

Calibrating the Clock

The M48T212Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. Whenthe Calibrationcircuitis properly em­ployed, accuracy improves to better than +1/–2
PPM at 25°C.

The oscillation rate of crystals changes with tem­perature. The M48T212Y/V design employs peri­odic counter correction. The calibration circuit
adds orsubtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig­ure 11. The number of times pulses which are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting countsslows the clock down.

The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent any value between 0 and
31 in binary form. Bit D5 is a Sign bit; ‘1’ indicates
positive calibration, ‘0’ indicates negative calibra­tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles.

If a binary ‘1’ is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modi­fied; if a binary 6 is loaded, the first 12 will be af­fected, and so on.

Therefore, each calibration step has the effect of
adding 512 or subtracting 256oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra­tion step in the calibration register. Assuming that
the oscillatoris runningat exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month
which corresponds to a totalrange of +5.5 or–2.75
minutes per month.

Two methods are available for ascertaining how
much calibration a given M48T212Y/V may re­quire. The first involves setting the clock, letting it
run for a month and comparing it toa knownaccu­rate reference and recordingdeviation overafixed
period of time. Calibration values, including the
number of seconds lost or gained in a given peri­od, can be found in Application Note AN934:
TIMEKEEPER Calibration.

This allows the designer to give the end user the
ability tocalibrate the clock as the environment re­quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.

The second approach is better suited to a manu­facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, whenthe
Stop bit (ST,D7 of 9h)is ‘0’,the FrequencyTest bit
(FT, D6 of Ch) is ‘1’, the Alarm Flag Enable bit
(AFE, D7 of 6h) is ‘0’, and the Watchdog Steering
bit(WDS, D7of7h) is ‘1’ ortheWatchdog Register
(7h=0) is reset.

Any deviation from 512 Hz indicates the degree
anddirection of oscillatorfrequency shift at the test
temperature. For example, a reading of

512.010124 Hz wouldindicate a +20 PPM oscilla­tor frequency error, requiring a –10 (WR001010)
to be loaded into the Calibration Byte for correc­tion. Note that setting or changing the Calibration
Byte does not affect the Frequency test output fre­quency.

The IRQ/FT pin is an open drain output which re­quires a pull-up resistor to VCCfor proper opera­tion. A 500-10kΩ resistor is recommended inorder
to control the rise time. The FT bit is cleared on
power-up.

16/23

M48T212Y, M48T212V

Table 14. Reset AC Characteristics

(TA= 0 to70°C; VCC= 3V to 3.6V or VCC= 4.5V to 5.5V)

Symbol Parameter Min Max Unit

(1)

t

R1

(2)

t

R2

t

R1HRH

t

R2HRH

Note: 1. Pulse width less than 50ns will result in no RESET(for noise immunity).

2. Pulse width less than 20ms will result inno RESET (for noise immunity).

3. C

L

Table 15. SNAPHAT Battery Table

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

Figure 12. RSTIN1 & RSTIN2 Timing Waveforms

RSTIN1 Low to RSTIN1 High 200 ns
RSTIN2 Low to RSTIN2 High 100 ms

(3)

RSTIN1 High to RST High 40 200 ms

(3)

RSTIN2 High to RST High 40 200 ms

= 5pF (see Figure 4).

RSTIN1

tR1

RSTIN2

(1)

RST

BATTERY LOW WARNING

The M48T212Y/V automatically performs battery
voltage monitoring upon power-up and at factory­programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0h, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL bit will remain asserted until completion of bat­tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.

If a battery lowis generatedduring apower-up se­quence, this indicates that the battery is belowap­proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.

If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-

tR2

tR1HRH

tR2HRH

AI02642

tery is near end of life. However, data is not com­promised due to the fact that a nominal Vcc is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT bat­tery/crystal top should be replaced with VCCpow­ering the device to avoid data loss.

Note: this will cause the clock to lose time during
the time interval the battery crystal is removed.

The M48T212Y/V only monitors the battery when
a nominal Vcc is applied to thedevice. Thus appli­cations which require extensive durations in the
battery back-up mode should bepowered-up peri­odically (at least once every few months) in order
for this technique to be beneficial.

Additionally, if a battery low is indicated, data in­tegrity should be verified upon power-up via a
checksum or other technique.

17/23

M48T212Y, M48T212V

INITIAL POWER-ON DEFAULTS

Upon application of power to the device, the fol­lowing register bits are set to a ‘0’ state: WDS,
BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT.
(See Table 16)

POWER SUPPLY DECOUPLING
AND UNDERSHOOT PROTECTION

Note: ICCtransients, including those produced by
output switching, can produce voltage fluctua­tions, resulting in spikes on the VCCbus. These
transients canbe reduced if capacitorsare used to
store energy, which stabilizes the VCCbus. The
energy stored in the bypass capacitors will be re­leased as low going spikes are generated or ener­gy will be absorbed when overshoots occur.

A ceramic bypass capacitor value of 0.1µF is rec­ommended inorder to provide the neededfiltering.
In addition to transients that are caused bynormal
SRAM operation,power cyclingcangenerate neg­ative voltage spikes on VCCthat drive it to values
below VSSbyas much asonevolt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode.

To protect from these voltage spikes, ST recom­mends connecting a schottky diode from VCCto

Figure 13. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

V

SS

AI02169

VSS(cathode connected to VCC, anode to VSS).
(Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount).

Table 16. Default Values

Condition W R FT AFE ABE

Initial Power-up
(Battery Attach for SNAPHAT)

Subsequent Power-up / RESET
Power-down

Note: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to ‘1’ prior to power-down.

(4)

(2)

(3)

WATCHDOG

Register

00000 0

00000 0
00011 0

(1)

18/23

M48T212Y, M48T212V

Table 17. Ordering Information Scheme

Example: M48T212Y -70 MH 1 TR

Device Type

M48T

SupplyVoltage and Write Protect Voltage

212Y = V
212V = V

Speed

-70 = 70ns (for M48T212Y)

-85 = 85ns (for M48T212V)

Package

(1)

MH

Temperature Range

1=0to70°C
6=–40to85°C

= 4.5V to 5.5V;V

CC

= 3.0V to 3.6V;V

CC

= SOH44

= 4.2V to 4.5V

PFD

= 2.7V to 3.0V

PFD

Shipping Method for SOIC

blank = Tubes
TR = Tape& Reel

Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number

“M4Txx-BR12SH1” in plastictube or ”M4Txx-BR12SH1TR” in Tape & Reel form.

Caution: Do not placethe SNAPHATbatterypackage ”M4Txx-BR12SH1” in conductive foam sincewill drain the lithium button-cell battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 18. Revision History

Date Revision Details

October 1999 First Issue

03/01/00

04/21/00 From Preliminary Data to Data Sheet

Document Layout changed
Default Values table added (Table 16)

19/23

M48T212Y, M48T212V

Table 19. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –
eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°

N44 44

CP 0.10 0.004

mm inches

Figure 14. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Outline

A

eB

Be

A2

CP

D

N

E

H

1

SOH-A

Drawing is not to scale.

C

LA1 α

20/23

M48T212Y, M48T212V

Table20. M4T28-BR12SH SNAPHAT Housingfor48 mAh Battery &Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 15. M4T28-BR12SH SNAPHAT Housing for 48mAhBattery & Crystal, Package Outline

A2

A3

L

eA

D

A1

A

B

eB

E

SHTK-A

Drawing is not to scale.

21/23

M48T212Y, M48T212V

Table21.M4T32-BR12SH SNAPHATHousingfor 120mAh Battery& Crystal, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 16. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, PackageOutline

A2

A3

L

eA

D

A1

A

B

eB

E

SHTK-A

Drawing is not to scale.

22/23

M48T212Y, M48T212V

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of use of such information nor for any infringement ofpatents or other rights of third parties which may result from itsuse. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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23/23