Page 1
TECHNICAL DATA
Quad 2-Input AND Gate
The IN74LV08 is low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT08A.
The IN74LV08 provides the 2-input AND function.
• Optimized for Low Voltage applications: 1.2 to 3.6 V
• Accepts TTL input levels between V
• Low Input Current
= 2.7 V and VCC = 3.6 V
CC
IN74LV08
ORDERING INFORMATION
IN74LV08N Plastic
IN74LV08D SOIC
IZ74LV08 Chip
TA = -40° ÷ 125°C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
PIN 14 =VCC
PIN 7 = GND
Y1
Y2
Y3
Y4
FUNCTION TABLE
Input Output
A B Y = A*B
L L L
L H L
H L L
H H H
H - high level
L - low level
INTEGRAL
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IN74LV08
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC supply voltage (Referenced to GND)
-0.5 ÷ +5.0
IIK *1 DC input diode current
IOK *2 DC output diode current
IO *3 DC output source or sink current
-bus driver outputs
ICC DC VCC current for types with
- bus driver outputs
I
DC GND current for types with
GND
- bus driver outputs
PD Power dissipation per package, plastic DIP+
SOIC package+
Tstg Storage temperature
-65 ÷ +150 °C
TL Lead temperature, 1.5 mm from Case for 10
seconds (Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
1
*
: V
2
*
: Vo < -0.5V or Vo > VCC+0.5V
3
*
: -0.5V < Vo < VCC+0.5V
SOIC Package: : - 8 mW/°C from 70° to 125°C
< -0.5V or V
I
I
> V
+0.5V
CC
±20
±50
±25
±50
±50
750
500
260
V
mA
mA
mA
mA
mA
mW
°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 1.2 3.6 V
VIN, V
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
outputs must be left open.
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -40 +125
tr, tf Input Rise and Fall Time VCC =1.2 V
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
V
CC
0
0
0
0
1000
700
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
and V
IN
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
should be constrained to the range
OUT
). Unused
CC
°C
ns
INTEGRAL
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IN74LV08
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
VIH High-Level Input
Voltage
VIL Low -Level Input
Voltage
VOH High-Level
Output Voltage
VOL Low-Level Output
Voltage
IIL Low-Level Input
Leakage Current
IIН High-Level Input
Leakage Current
IСС Quiescent Supply
Current
(per Package)
1.2
1.2
VI = VIL or VIH
I
= -50 µА
O
= VIL or VIH
V
I
= -6.0 mА
I
O
VI = VIL or VIH
I
= 50 µА
O
VI = VIL or VIH
= 6.0 mА
I
O
VI = 0 V 3.6 - -0.1 - -1.0 - -1.0
VI = VCC 3.6 - 0.1 - 1.0 - 1.0
= 0 В or V
V
I
CC
IO = 0 µА
(Voltages Referenced to GND)
,
V
CC
V
25°C
min max
0.9
2.0
1.4
3.0
2.1
3.6
2.5
-
2.0
3.0
3.6
1.2
2.0
3.0
3.6
-
-
-
1.1
1.92
2.92
3.52
Guaranteed Limit
-40°C ÷
85°C
-40°C ÷
125°C
min max min max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.9
1.4
2.1
2.5
1.0
1.9
2.9
3.5
-
0.9
-
1.4
-
2.1
-
2.5
-
0.3
-
0.6
-
0.9
-
1.1
-
-
-
-
-
1.0
-
1.9
-
2.9
-
3.5
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
Unit
V
V
V
3.0 2.48 - 2.34 - 2.20 - V
1.2
2.0
3.0
3.6
-
0.09
-
0.09
-
0.09
-
0.09
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
-
0.1
V
3.0 - 0.33 - 0.4 - 0.5 V
µA
µA
3.6 - 2.0 - 20 - 40
µA
INTEGRAL
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IN74LV08
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter
V
CC
V
(CL=50 pF, tLH = tHL = 6.0 ns, VIL=0V, VIH=VCC, RL=1kΩ)
-40°C ÷ 85°C -40°C ÷ 125°C
25°C
min max
t
(t
THL,
) Output Transition
TLH
Time, Any Output
(Figure 1)
t
PHL,
(t
Propagation Delay,
PLH)
Input A to Output Y
(Figure 1)
CI Input Capacitance 3.0
1.2
2.0
*
1.2
2.0
*
-
-
-
-
-
-
CPD Power Dissipation Capacitance (Per Gate)
* - VCC= (3.3±0.3) V
Used to determine the no-load dynamic power consumption:
= CPDV
P
D
∑(C
LVCC
2
fI+ ∑(CLV
CC
2
fo) – sum of the outputs
2
fo), fI-input frequency, fo- output frequency (MHz)
CC
Guaranteed Limit
Unit
min max min max
60
16
10
135
23
14
7.0 - - - - pF
-
-
-
-
-
-
75
20
13
405
28
18
ТА=25°С, VI=0V÷VCC
44
-
-
-
-
-
-
90
24
15
405
34
21
ns
pF
Input А, B
Output Y
V = 0.5 V
1 CC
t
HL
0.9
V
1
0.1
t
PHL
0.9
V
1
0.1
t
THL
t
LH
V
0.9
V
1
0.1
t
PLH
0.9
V
1
0.1
t
TLH
CC
GND
V
V
OH
OL
Figure 1. Switching Waveforms
V
CC
PULSE
GENERATOR
V
I
DEVICE
UNDER
TEST
R
T
V
O
Termination resistance RT -
C
R
L
should be equal to Z
L
generators
OUT
pulse
Figure 2. Test Circuit
INTEGRAL
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CHIP PAD DIAG RAM IZ74LV08
IN74LV08
10
09
08
13
12
11
14
±
07
1.20 0.03
01
02
03
1.23 0.03
Pad size 0.108 x 0.108 mm (Pad size is given as per
Thickness of chip 0.46 ± 0,02 mm
metallization
PAD LOCATION
Pad No Symbol X Y
01 A1 0.111 0.287
02 B1 0.111 0.119
03 Y1 0.504 0.111
04 A2 0.672 0.111
05 B2 1.009 0.111
06 Y2 1.009 0.277
07 GND 1.009 0.447
08 Y3 1.009 0.806
09 A3 1.009 0.974
10 B3 0.672 0.974
11 Y4 0.504 0.974
12 A4 0.336 0.974
13 B4 0.111 0.772
14 Vcc 0.111 0.618
04
±
layer)
06
05
Chip marking
25LV08
(x=1.009; y=0.727)
INTEGRAL
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