Datasheet FDP42AN15A0, FDB42AN15A0 Datasheet (Fairchild Semiconductor)

FDP42AN15A0 / FDB42AN15A0

N-Channel PowerTrench® MOSFET
150V, 35A, 42mΩ

FDP42AN15A0 / FDB42AN15A0

September 2002

Features

•r

•Q

• Low Miller Charge

• Low Qrr Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82864

MOSFET Maximum Ratings T

= 36mΩ (Typ.), V

DS(ON)

(tot) = 33nC (Typ.), V

g

GATE

SOURCE

TO-263AB

FDB SERIES

= 10V, ID = 12A

GS

= 10V

GS

DRAIN

(FLANGE)

DRAIN

(FLANGE)

= 25°C unless otherwise noted

C

Applications

• DC/D C C onverter s an d Of f-line UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 24V and 48V Syst ems

• High Voltage Synchronous Rectifier

• Direct Injection / Diesel Injection Systems

• 42V Automotiv e Load Control

• Elec tr on ic Valve Train Sys tems

D

SOURCE

DRAIN

GATE

TO-220AB

FDP SERIES

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 150 V
Gate to Source Voltage ±20 V
Drain Curr e nt
Continuous (T

I

D

Continuous (T
Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 24

C

= 25oC, VGS = 10V, with R

amb

= 43oC/W) 5 A

θJA

35 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 90 mJ
Power dissipation 150 W

o

Derate above 25

C1.00W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristi cs

R

θJC

R

θJA

R

θJA

This product has been designed to meet the extreme test conditions and environment demanded by the automotive

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality

©2002 Fairchild Semiconductor Corporation

Thermal Resistance Junction to Case TO-220,TO-263 1.0
Thermal Resistance Junction to Ambient TO-220,TO-263 62
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad ar ea 43

industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

systems certification.

FDP42AN15A0 / FDB42AN15A0 Rev. C

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB42AN15A0 FDB42AN15A0 TO-263AB 330mm 24mm 800 units
FDP42AN15A0 FDP42AN15A0 TO-220AB Tube N/A 50 units

FDP42AN15A0 / FDB42AN15A0

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Con ditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Volt ag e ID = 250µA, VGS = 0V 150 - - V

V

= 120V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 12A, VGS = 10V - 0.036 0.042

I

D

I

= 6A, VGS = 6V - 0.040 0.060

Drain to S ou r c e On Re si st ance

D

= 12A, VGS = 10V,

I

D

T

= 175oC

J

- 0.090 0.107

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitanc e - 225 - pF
Reverse Transfer Capacitance - 45 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 4.2 5.4 nC
Gate to Source Gate Charg e - 9.5 - nC
Gate Charge Threshold to Plateau - 5.3 - nC

V

DD

I

= 12A

D

I

= 1.0m A

g

= 75V

Gate to Drain “Miller” Charge - 6.9 - nC

- 2150 - pF

30 39 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 11 - ns
Rise Time - 19 - ns
Turn-Off D elay Time - 27 - ns
Fall Time - 23 - ns
Turn-Off Time - - 74 ns

(VGS = 10V)

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 0.2mH, IAS = 30A.

©2002 Fairchild Semiconductor Corporation

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 12A, dISD/dt = 100A/µs- -82ns

Reverse Recovered Charge ISD = 12A, dISD/dt = 100A/µs - - 204 nC

- - 46 ns

V

= 75V, ID = 12A

DD

V

= 10V, RGS = 7.5Ω

GS

I

= 12A - - 1.2 5 V

SD

= 6A - - 1.0 V

I

SD

FDP42AN15A0 / FDB42AN15A0 Rev. C

FDP42AN15A0 / FDB42AN15A0

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

10

40

30

20

, DRAIN CURRENT (A)

D

10

I

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-1

10

θJC

10

x R

0

t

1

t

2

2

+ T

θJC

C

1

10

500

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

10

-5

10

©2002 Fairchild Semiconductor Corporation

Figure 3. Normalized Maximum Transient Thermal Impedance

TC = 25oC
FOR TEMPERATURES

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:

I = I

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

175 - T

25

10

FDP42AN15A0 / FDB42AN15A0 Rev. C

C

150

0

10

1

FDP42AN15A0 / FDB42AN15A0

Typical Characteristics T

200

100

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

1

, DRAIN CURRENT (A)

D

I

SINGLE PULSE
TJ = MAX RATED

TC = 25oC

0.1
1 10 100 300

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

= 25°C unless otherwise noted

C

10µs

100µs

DC

Figure 5. Forward Bias Safe Operating Area

80

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

60

1ms

10ms

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.001 0.01 0.1 1 10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

80

VGS = 20V

60

VGS = 10V

VGS = 6V

40

TJ = 25oC

, DRAIN CURRENT (A)

D

I

20

0

345678

TJ = 175oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

40

, DRAIN CURRENT (A)

D

I

20

PULSE DURATION = 80µs

0

012345

DUTY CYCLE = 0.5% MAX

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

50

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

45

40

DRAIN TO SOURCE ON RESISTANCE(mΩ)

35

0 10203040

ID, DRAIN CURRENT (A)

VGS = 6V

VGS = 10V

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

TC = 25oC

VGS = 10V, ID =12A

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

©2002 Fairchild Semiconductor Corporation

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDP42AN15A0 / FDB42AN15A0 Rev. C

FDP42AN15A0 / FDB42AN15A0

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

4000

C

= CGS + C

1000

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

GD

100

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10 150
VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 75V

8

6

4

WAVEFORMS IN

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25 30 35

Qg, GATE CHARGE (nC)

DESCENDING ORDER:

ID = 24A
ID = 12A

Figure 13. Capacitance vs Drain to Sour ce

Voltage

©2002 Fairchild Semiconductor Corporation

Figure 14. Gat e Charge Waveforms for Constant

Gate Current

FDP42AN15A0 / FDB42AN15A0 Rev. C

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

GS

FDP42AN15A0 / FDB42AN15A0

V

DS

V

DD

V

= 10V

GS

V

GS

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2002 Fairchild Semiconductor Corporation

V

DS

R

L

V

GS

R

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

FDP42AN15A0 / FDB42AN15A0 Rev. C

50%50%

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

P

----------------- ------------=

DM

R

θJA

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of P
comple x and influenced by many factors:

1. Mou nting pad area ont o which the device is attached and
whet her the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the
duty cycle and the transient thermal response of the part,
the boa rd and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w i th 1 oz c opper af ter 100 0 se c on ds
of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manually u tilizing the normalized
maximum transient thermal impedance curve.

DM

(oC/W)

θJA

(EQ. 1)

, in an

is

DM

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDP42AN15A0 / FDB42AN15A0

Therma l resi stances correspondi ng to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inch es squ are and equ ation 3 is for area in cent imeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84

26.51

=

R

θJA

26.51

=

R

θJA

©2002 Fairchild Semiconductor Corporation

-------------------------------------+

0.262 Area+()

Area in Iches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

FDP42AN15A0 / FDB42AN15A0 Rev. C

PSPICE Electrical Model

.SUBCKT FDB 42AN15A0 2 1 3 ; rev June 11, 2002
Ca 12 8 6.0e-10
Cb 15 14 8e-10
Cin 6 8 2.1e-9

Dbod y 7 5 DbodyMOD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 159.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 4.81e-9

Ldrain 2 5 1.0e -9
Lsource 3 7 4.63e-9

RLgate 1 9 48.1
RLdr ai n 2 5 10
RLsource 3 7 46.3

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 14e-3
Rgate 9 20 1.36
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 20e-3
Rvthres 22 8 RvthresMO D 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13814

S1B

EGS EDS

-

13

6
8

10

RSLC2

6

13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CIN

CB

-

+

-

5

51

5

51

21

MSTRO

14

5
8

RSLC1

+

ESLC

­50

RDRAIN

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

FDP42AN15A0 / FDB42AN15A0

LDRAIN

RLDRAIN

11

+

17

DBODY

18

-

LSOURCE

7

RLSOURCE

RVTEMP
19

­VBAT

+

22

DRAIN

2

SOURCE

3

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e-6 *65),3))}
.MODEL DbodyMOD D (IS=2.4E-11 N=1.08 RS=4.2e-3 TRS1=2.2e-3 TRS2=2.5e-9

+ CJO=1.35e-9 M=6.3e-1 TT= 4. 8e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=.43e-9 IS=1e-30 N=10 M=0.66)

.MODEL MmedMOD NMOS (VTO=3.5 KP=4 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=9.3e-1)
.MODEL MstroMOD NMOS (VTO =4.0 KP=70 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL Mwe akMOD NMOS (VTO =3.12 KP=0. 06 IS=1e-30 N=10 T O X = 1 L=1u W=1u RG=9.3e-1 RS=.1)

.MODEL Rb reakMOD RES (T C1=1e-3 TC2= -15e-7)
.MODEL Rd rai nMOD RES (TC1=1.7e-2 TC 2=4e-5)
.MODEL RSLCMOD RES (TC1=2.5e-3 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e -3 T C2=-1.5e-5 )
.MODEL RvtempMOD RES (T C1=-2.7e-3 TC2=1e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4 VOFF =-1 .5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=- 4)
.MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1 VOFF =0.5)
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .5 VOFF= -1)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by Wil liam J. Hepp and C. F rank
Wheatley.

©2002 Fairchild Semiconductor Corporation

FDP42AN15A0 / FDB42AN15A0 Rev. C

SABER Electrical Model

rev June 11, 20 02
template FDB 42AN15A0 n2, n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-11,nl=1.08,rs=4.2e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=1.35e-9,m=6.3e-1,tt=4.8e-8,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1 e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=.43e-9,isl=10e-30,nl=10,m=0.66)
m..model mmedmod = (type=_n,vto=3.5,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.0,kp=70,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.12,kp=0.06,is=1e-30, tox=1,rs=.1)
sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0. 1, von=-4,voff=-1.5)
sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0. 1, von=-1.5,voff=-4)
sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)

10

sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
c.ca n12 n8 = 6.0e -10
c.cb n15 n14 = 8e- 10

RSLC2

c.cin n6 n8 = 2.1e -9
dp.dbody n7 n5 = model=dbodym od

dp.dbreak n5 n11 = model=dbr eakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 159.5
spe.eds n14 n8 n5 n8 = 1

GATE

spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

LGATE

1

RLGATE

RGATE

9

ESG

EVTEMP
+

18
22

20

­6

8

+

6

-

spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1
l.lgate n1 n9 = 4.81e-9

l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.63e-9

res.rlgate n1 n9 = 48.1
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 46.3

CA

S1A

12

13814

S1B

EGS EDS

13

13

+

+

6
8

-

-

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u
m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

EVTHRES

+

19

S2A

S2B

5

RSLC1

51

ISCL

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

50
RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

17
18

­7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDP42AN15A0 / FDB42AN15A0

res.rbreak n17 n18 = 1, tc1=1e-3, tc 2=-15e-7
res.rdrain n50 n16 = 14e-3, tc1=1.7e-2,tc2=4e-5
res.rgate n9 n20 = 1.36
res.rslc1 n5 n51 = 1e-6, tc1=2.5e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 20e-3, tc1=1e -3, tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1. 5e-5
res.rvtemp n18 n19 = 1, tc1=-2.7e-3,tc2=1e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = mode l= s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = mode l= s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model = s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n 5, n51)/(1e-9+a bs(v(n5,n51))))*((abs (v(n5,n51)* 1e6/65))** 3) )}
}

©2002 Fairchild Semiconductor Corporation

FDP42AN15A0 / FDB42AN15A0 Rev. C

FDP42AN15A0 / FDB42AN15A0

PSPICE Thermal Model

REV 23 June 11 , 2002
FDB42AN15A0_Thermal
CTHERM1 TH 6 2e-3

CTHERM2 6 5 4. 5e-3
CTHERM3 5 4 7e-3
CTHERM4 4 3 3e-2
CTHERM5 3 2 4e-2
CTHERM6 2 TL 8.5e-1

RTHERM1 TH 6 6.2e-2
RTHERM2 6 5 8. 2e-2
RTHERM3 5 4 9. 2e-2
RTHERM4 4 3 9. 7e-2
RTHERM5 3 2 0. 2
RTHERM6 2 TL 0.22

SABER Thermal Model

SABER ther m al m odel F DB42AN15A 0_T hermal
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =2e-3
ctherm.ctherm2 6 5 =4.5e-3
ctherm.ctherm3 5 4 =7e-3
ctherm.ctherm4 4 3 =3e-2
ctherm.ctherm5 3 2 =4e-2
ctherm.ctherm6 2 tl =8.5e-1

RTHERM1

RTHERM2

RTHERM3

RTHERM4

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

rtherm.rtherm1 th 6 =6.2e-2
rtherm.rt herm2 6 5 =8.2e-2
rtherm.rt herm3 5 4 =9.2e-2
rtherm.rt herm4 4 3 =9.7e-2
rtherm.rt herm5 3 2 =0.2
rthe r m.rtherm6 2 tl =0.2 2}

RTHERM5

RTHERM6

CTHERM5

2

CTHERM6

tl

CASE

©2002 Fairchild Semiconductor Corporation

FDP42AN15A0 / FDB42AN15A0 Rev. C

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Adva nce Information Formative or In

Design

Preliminary First Production This data s heet contains preliminary data, and

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Rev. I1