Page 1
FAN8006D3
4-CH Motor Driver
www.fairchildsemi.com
Features
• 4-Channel BTL (Balanced transformer-less) driver
• Built-in thermal shutdown circuit
• Built-in power save circuit
• Separated power suppl y
• Operating supply voltage: 4.5V ~ 13.2V
• Corresponds to 3.3V or 5V DSP
Description
The FAN8006D3 is a monolithic integrated circuit, suitable
for 4-CH motor driver which drives focus actuator, tracking
actuator, sled motor and loading motor of a CD-media system.
28-SSOPH-375SG2
Target Application
• Compact disk player
• Digital video disk player
• Compact disk ROM
Ordering Information
Device Package Ope. Temp.
FAN8006D3 28-SSOPH-375SG2 −35°C ~ +85°C
FAN8006D3TF
28-SSOPH-375SG2 −35°C ~ +85°C
Rev . 1.0.0
©2002 Fairchild Semiconductor Corporation
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FAN8006D3
FAN8006D3 Pin Assignments
−)
PreVcc
OPIN4(+)
OPIN4(
262728
123
BIAS
−)
OPIN1(
OPIN1(+)
−)
OPOUT4
OPIN3(+)
OPIN3(
232425
OPOUT3
FIN(GND)
STBY1
GND
−)
VO3(
PowVcc3 CH3/4
19202122
FAN8006D3
567 8910111213
4
−)
VO2(
PowVcc CH2
IN2
OPOUT1
MUTE
STBY2
FIN(GND)
GND
PowVcc CH1
−)
VO3(+)
VO4(
VO4(+)
15161718
14
−)
VO2(+)
VO1(+)
VO1(
2
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Pin Defi ni ti o n s
Pin Number Pin Name I/O Pin Function Description
1 BIAS I Bias voltage input 2 OPIN1(+) I Op-amp CH1 input (+) 3OPIN1(−) I Op-amp CH1 input (−) 4 OPOUT1 O Op-amp CH1 output 5 IN2 I CH2 input 6 MUTE I CH1 mute control when STBY1 is logic high 7 STBY2 I CH2 standby control 8 GND - Signal ground
9 PowVcc1 CH1 - BTL CH1 power supply 10 PowVcc2 CH2 - BTL CH2 power supply 11 VO2( 12 VO2( 13 VO1( 14 VO1( 15 VO4(+) O Drive4 output ( 16 VO4(−) O Drive4 output ( 17 VO3(+) O Drive3 output ( 18 VO3(−) O Drive3 output ( 19 PowVcc3 CH3/4 - BTL CH3/4 power supply 20 STBY1 I Input for CH1/3/4 standby control 21 GND - Ground 22 OPOUT3 O Op-amp CH3 output 23 OPIN3(−) I Op-amp CH3 input (−) 24 OPIN3(+) I Op-amp CH3 input (+) 25 O POUT4 O Op-amp CH4 output 26 OPIN4(−) I Op-amp CH4 input (−) 27 OPIN4(+) I Op-amp CH4 input (+) 28 PreVcc - Vcc for pre block
−)
+)
−)
+)
O Drive2 output (−)
O Drive2 output (+)
O Drive1 output (−)
O Drive1 output (+)
+
−
+
−
)
)
)
)
FAN8006D3
3
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FAN8006D3
Internal Bl oc k Diag r am
PreVcc
OPIN4(+)
OPIN4(−)
OPOUT4
FIN
OPIN3(−)
OPIN3(+)
(GND)
OPOUT3
STBY1
GND
PowVcc3 CH3/4
VO3(−)
VO3(+)
VO4(−)
VO4(+)
1516171819202122232425262728
−
+
20k
10k
10k
−
+
+
-
1234567 891011121314
BIAS
OPIN1(+)
−
+
+
−
20k
OPIN1(−)
OPOUT1
+
IN2
−
TSD
20k
10k
10k
MUTE
−
+
+
−
20k
(GND)
FIN
STBY2
GND
10k
10k
LEVEL
SHIFT
PowVcc CH2
−
10k
PowVcc CH1
−
-
−
10k
+
+
+
−
PowVcc CH2
10k
−
10k
PowVcc
LEVEL
SHIFT
+
10k
−
+
10k
+
+−
+
CH3/4
VO2(−)
10k
-
−
10k
LEVEL
SHIFT
PowVcc CH1
−
10k
VO2(+)
10k
+
−
VO1(−)
−
10k
10k
+
+
+
PowVcc
CH3/4
LEVEL
SHIFT
10k
−
+
VO1(+)
+
−
−+
10k
+
4
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Equivalent Circuits (Continued)
POWER OUTPUT CHANNEL OPAMP INPUT
FAN8006D3
28
9 10
19
11 12
13 14
15 16
17 18
28
2
25Ω
24
27
2KΩ
1KΩ
CHANNEL OP-AMP OUTPUT BIAS INPUT
28
20KΩ
10KΩ
27p
25Ω
20KΩ
4 22 25
20KΩ
28
25Ω
1
2KΩ
1KΩ
28
28
3
25Ω
23
26
CHANNEL 2 INPUT ST ANDBY 1/2 INPUT
28
28
25Ω
5
10KΩ
1KΩ
20KΩ
20KΩ
20KΩ
1KΩ
1KΩ
7
1KΩ
28
25Ω
40KΩ
100KΩ
20KΩ
40KΩ
28
20KΩ
40KΩ
28
25Ω
20KΩ
40KΩ
20
100KΩ
20KΩ
80KΩ
20KΩ
5
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FAN8006D3
Equivalent Circuits
MUTE INPUT
28
6
25Ω
30KΩ
40KΩ
1KΩ
1KΩ
1KΩ
6
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Absolute Maximum Ratin gs ( Ta= 25°C)
Parameter Symbol Value Unit
Maximum s u pp ly volt a ge PreV
Power dissipation P
Operating temperature range T
Storage temperature range T
NOTE:
Epoxy board
Pd=2.5W
1. Test PCB is single layer PCB which has only 1 signal plane. PCB size is 76mm × 114mm × 1.6mm.
2. Power dissipation is reduced for using above Ta=25°C. It’ s slope is -20.0mW/°C.
3. Do not exceed P
and SOA (Safe Operating Area).
D
cc
max
D
OPR
STG
Pd is measured
base on the JE-
DEC/STD(JESD
51-2)
15 V
note
2.5
−35 ~ +85 °C
−55 ~ +150 °C
FAN8006D3
W
Pd (mW)
2,000
1,500
500
0
0 25 50 75 100 125 150 175
SOA
85
Ambient temperature, Ta [°C]
Recommended Operating Conditions ( Ta=25°C)
Parameter Symbol Min. Typ. Max. Unit
Supply voltage PreVcc 4.5 - 13.2 V Supply voltage PowVcc CH1 4.5 - PreVcc V Supply voltage PowVcc CH2 4.5 - PreVcc V Supply voltage PowVcc CH3/4 4.5 - PreVcc V
7
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FAN8006D3
Electrical Characteristics
(Unless otherwise specified, Ta=25°C, PreVcc=12V, PowVcc CH1=PowVcc CH3/4=5V, PowVcc CH2=12V,
RL=8Ω,24Ω)
Parameter Symbol Conditions Min. Ty p. Max. Unit
Quiescent current1 I
Quiescent current2 I
Quiescent current3 I
Quiescent current4 I
Quiescent current5 I
Mute on voltage V
Mute off voltage V
STBY1 on voltage V
STBY1 off voltage V
STBY2 on voltage V
STBY2 off voltage V
CC1
CC2
CC3
CC4
CC5
MON
MOFF
STON1
STOFF1
STON2
STOFF2
BTL DRIVE CIRCUIT
Channel 1,3,4(RL=8Ω)
Output offset voltage 1,3,4 V
Maximum output voltage 1,3,4 V
Closed loop voltage gain 1,3,4 G
Ripple rejection ratio 1,3,4 RR
Slew rate 1,3,4 SR
OF1,3,4
OM1,3,4
VC1,3,4
1,3,4
1,3,4
Channel 2(RL=24Ω)
Output offset voltage 2 V
Maximum output voltage 2 V
Closed loop voltage gain 2 G
OF2
OM2
VC2
Ripple rejection ratio 2 RR
Slew rate 2 SR
INPUT OP-AMP
Input offset voltage V
Input bias current I
High level output voltage V
Low level output voltage V
Output sink current I
Output source current I
Open loop voltage gain G
OFOP
BOP
OHOP
OLOP
SINK
SOURCE
VO
Ripple rejection ratio RR Slew rate SR Common mode rejection ratio CMRR V Common mode input range CMIR PreVcc=5V -0.3 - 4 V
STBY1,2=0.5V,Mute=2V,RL=∞
STBY1,2=2V,Mute=0.5V,RL=∞
STBY2=2V, STBY1,Mute=0.5V
STBY2=0.5V, STBY1,Mute=2V
STBY2,Mute=0.5V,STBY1=2V,
- 0.1 1 mA
- 22.0 31.0 mA
- 5.5 8.5 mA
- 12.0 17.0 mA
- 17.5 24.5 mA
-2.0--V
---0.5V
---0.5V
-2.0--V
---0.5V
-2.0--V
- −50 - +50 mV
-3.64.0-V
- 171819dB
--60-dB
--1-V/µs
- −50 - +50 mV
- 9.5 10.5 - V
- 171819dB
2
2
--60-dB
--1-V/µs
- −10 - +10 mV
- - - 400 nA
PreVcc=5V, RL=∞ 4.5 - - V
PreVcc=5V, RL=∞ --0.5V
PreVcc=5V, RL=50Ω 3- -mA
PreVcc=5V, RL=50Ω 2- -mA
VIN= -75dB, 1KHz - 75 - dB
VIN= 120KHz, 2V
OP
VIN= -20dB, 120Hz - 1 - V/µs
OP
= -20dB, 1KHz - 80 - dB
IN
PP
-60-dB
8
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FAN8006D3
Application Information
1. Standby/Mute Input
FAN8006D3 have 2 independent standby inputs that is , pin #7(STBY2) and pin #20(STBY1), and 1 independent mute
input(pin #7) . Th e digital logics of the se functions are as below.
STBY1=>Low STBY1=>High STBY2
Mute=>Low Mute=>High Mute=>Low Mute=>High High Low
CH 1
CH3/4 operate - -
standby operate
CH2 - - - - operate standby
2. Mute Timing Chart
If the mute input( pin #6) voltage rises above 2.0V, the output(CH1) current can be muted under normal operating conditions,
make sure to open pin #7 or pull it down below 0.5V. Below figure is high impedanc e mu te timing chart.
high impedance - -
Mute(pin #6)
Vout
(pin#13,14)
Voltage
2[V]
Voltage
V
om
0.5[mV]
PreVcc = 12V
PowVcc CH1= 5V
BIAS = 1.65 V
RL = 8Ω
≤ 125µsec
T
0
T
m
0
time
time
m
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FAN8006D3
3. CH2 Drive Output Schematic
PowVccCH2
−
11
DO
M
DO+
12
Inside IC
10K
10
R
−
+
R
PowVccCH2
1
Bias
+
−
10K
Power amp
Current Conveyor Type 2
−
+
10K
5
20K
+
10K
−
10K
• The reference voltage BIAS is given externally through pin 1.
• The input signal is ampl ified by (20K/10K) times and the n fed to the current conveyor type 2 ci rcuit and the power amp
circuit.
• The power amp circuit produces the diffe r ential output vol tages and drives two output power amplifier circu its.
• Since the differential gain of the power amplifier is equal to 2 × (1+10K / 10K) , the output signal of the input OP-amp is
amplified totally 8.
• If the total gain is insufficient or large, external resistor can be used to adjust the gain.
10
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4. CH1/3/4 Drive Output Schematic
FAN8006D3
19
9
PowVccCH1
(PowVccCH3/4)
Inside IC
R
13 16 18
−
+
R
PowVccCH1
(PowVccCH3/4)
10K
1
Bias
DO
−
+
−
10K
Current Conveyor Type 2
224
M
Power amp
+
+
27
−
10K
14 15 17
DO+
+
20K
−
23
3
26
10K
−
10K
4
25
22
• The reference voltage BIAS is given externally through pin 1.
• The input OP-amp output sign al is amplified by (20K/ 10K) ti mes and then fed to t he current conv eyor type 2 circu it and the
power amp circuit.
• The power amp circuit produces the diffe r ential output vol tages and drives two output power amplifier circu its.
• Since the differential gain of the power amplifier is equal to 2 × (1+10K / 10K) , the output signal of the input OP-amp is
amplified totally 8.
• If the total gain is insufficient or large, the input OP-amp and the external re sistors can be used to adjus t the gain.
11
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FAN8006D3
Application Circuits
(Voltage control mode)
VOLTAGE
BIAS
SERVO AMP
FOCUS
SLED
TRACKING
LOADING
MUTE
STBY2
LOADING
MOTOR
1
1
BIAS
2
OPIN1(+)
3
OPIN1(
4
OPOUT1
5
IN2
6
MUTE
7
STBY
8
GND
9
PowVcc CH1
10
PowVcc CH2
11
VO2(
12
VO2(+)
−)
FAN8006D3
PowVcc CH3/4
−)
PreVcc
OPIN4(+)
OPIN4(
OPOUT4
OPIN3(+)
OPIN3(−)
OPOUT3
GND
STBY1
VO3(
VO3(+)
28
12V
27
26
−)
25
24
23
22
21
20
19
18
−)
17
STBY1
SLED MOTOR
TRACKING
ACTUATOR
13
14
VO1(
VO1(+)
−)
VO4(
VO4(+)
16
−)
15
FOCUS
ACTUATOR
12
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FAN8006D3
13
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FAN8006D3
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
user.
1. Life support devices or systems are devices or systems
which, (a) are inte nded for surgical implant into the body,
or (b) support or sustain life, and (c) whose fail ure to
perform when proper ly used in accordance with
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably exp ected to c ause t he failure of the l ife suppo rt
device or system, or to aff ect its safety or effectiveness.
instruct ions for use provided in the labeling, can be
reasonably expected to result in a signi ficant injury of the
www.fairchildsemi.com
6/24/02 0.0m 001
2002 Fairchild Semiconductor Corporation
Stock#DSxxxxxxxx
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