Datasheet EV54Y39A Datasheet
PIC24FJ256GA705 FAMILY
16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and
16-Kbyte RAM in Low Pin Count Packages
High-Performance CPU
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Fast RC Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• Six-Channel DMA Controller
Analog Features
• Up to 14-Channel, Software-Selectable,
10/12-Bit Analog-to-Digital Converter:
- 12-bit, 200K samples/second conversion rate
(single Sample-and-Hold)
- Sleep mode operation
- Charge pump for operating at lower AV
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
- Programmable reference voltage for
comparators
• LVD Interrupt Above/Below Programmable
LVD Level
V
• Charge Time Measurement Unit (CTMU):
- Allows measurement of capacitance and time
- Operational in Sleep
DD
Low-Power Features
• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
• Doze mode allows CPU to Run at a Lower Clock
Speed than Peripherals
• Alternate Clock modes allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Dual Voltage Regulators:
- 1.8V core regulator
- 1.2V regulator for Retention Sleep mode
• Operating Ambient Temperature Range of
-40°C to +125°C
• ECC Flash Memory (256 Kbytes):
- Single Error Correction (SEC)
- Double Error Detection (DED)
- 10,000 erase/write cycle endurance, typical
- Data retention: 20 years minimum
- Self-programmable under software control
• 16-Kbyte SRAM
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
Low-Power RC (LPRC) Oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
and Oscillator Start-up Timer (OST)
• Programmable Low-Voltage Detect (LVD)
• Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40°C to +125°C)
• Class B Safety Library, IEC 60730
2016-2020 Microchip Technology Inc. DS30010118E-page 1
PIC24FJ256GA705 FAMILY
Peripheral Features
• High-Current Sink/Source 18 mA/18 mA on
All I/O Pins
• Independent, Low-Power 32 kHz Timer Oscillator
• Timer1: 16-Bit Timer/Counter with External Crystal
Oscillator; Timer1 can Provide an A/D Trigger
• Timer2,3: 16-Bit Timer/Counter, can Create 32-Bit
Timer; Timer3 can Provide an A/D Trigger
• Three Input Capture modules, Each with a
16-Bit Timer
• Three Output Compare/PWM modules, Each with
a 16-Bit Timer
• Four MCCP modules, Each with a Dedicated
16/32-Bit Timer:
- One 6-output MCCP module
- Three 2-output MCCP modules
• Three Variable Widths, Synchronous Peripheral
Interface (SPI) Ports on All Devices; Three
Operation modes:
- Three-wire SPI (supports all four SPI modes)
- 8 by 16-bit or 8 by 8-bit FIFO
2
-I
S mode
•Two I
2
C Masters and Slaves w/Address Masking,
and IPMI Support
• Two UART modules:
- LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect (ABD), Break character support)
- RS-232 and RS-485 support
®
-IrDA
mode (hardware encoder/decoder
functions)
• Five External Interrupt Pins
• Parallel Master Port/Enhanced Parallel Slave Port
(PMP/EPSP), 8-Bit Data with External
Programmable Control (polarity and protocol)
• Enhanced CRC module
• Reference Clock Output with Programmable
Divider
• Two Configurable Logic Cell (CLC) Blocks:
- Two inputs and one output, all mappable to
peripherals or I/O pins
- AND/OR/XOR logic and D/JK flip-flop
functions
• Peripheral Pin Select (PPS) with Independent I/O
Mapping of Many Peripherals
TABLE 1: PIC24FJ256GA705 FAMILY DEVICES
Memory
Pins
Device
PIC24FJ64GA705 64K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ128GA705 128K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ256GA705 256K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ64GA704 64K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ128GA704 128K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ256GA704 256K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes
PIC24FJ64GA702 64K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes
PIC24FJ128GA702 128K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes
PIC24FJ256GA702 256K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes
Program
(bytes)
SRAM
(bytes)
GPIO
DMA Channels
10/12-Bit A/D Channels
CRC
Comparators
MCCP 6-Output/2-Output
Peripherals
IC/OC/PWM
16-Bit Timers
®
C
2
I
CTMU Channels
LIN-USART/IrDA
Variab le Width SPI
CLC
RTCC
EPMP (Address/Data Line)
JTAG
DS30010118E-page 2 2016-2020 Microchip Technology Inc.
Pin Diagrams (PIC24FJ256GA702 Devices)
Legend: See Table 2 for a complete description of pin functions.
Note 1: Gray shading indicates 5.5V tolerant input pins.
2: The large center pad on the bottom of the package may be left floating or connected to V
SS.
28-Pin QFN, UQFN
(1,2)
MCLR
AVDD/VDD
AVSS/VSS
VSS
VDD
VSS
VCAP
RB12
RB0
RB1
RB2
RB3
RA2
RA3
RB4
RA4
RB5
RB6
RB7
RB8
RB9
RB10
RB11
RB13
RB14
RB15
RA0
RA1
10 11
2
3
6
1
18
19
12 13 14
15
8
7
16
17
232425262728
9
PIC24FJ256GA702
5
4
20
21
22
PIC24FJ256GA705 FAMILY
TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA702 QFN, UQFN)
Pin Function Pin Function
1 PGD1/AN2/CTCMP/C2INB/RP0/RB0 15 TDO/C1INC/C2INC/C3INC/TMPRN
2 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 16 Vss
3 AN4/C1INB/RP2/SDA2/CTED13/RB2 17 V
4 AN5/C1INA/RP3/SCL2/CTED8/RB3 18 PGD2/TDI/RP10/OCM1C/CTED11/RB10
5 Vss 19 PGC2/TMS/REFI1/RP11/CTED9/RB11
6 OSCI/CLKI/C1IND/RA2 20 AN8/LVDIN/RP12/RB12
7 OSCO/CLKO/C2IND/RA3 21 AN7/C1INC/RP13/OCM1D/CTPLS/RB13
8SOSCI/RP4/RB4 22 CV
9 SOSCO/PWRLCLK/RA4 23 AN9/C3INA/RP15/CTED6/RB15
10 V
11 PGD3 /RP5/ASDA1/OCM1E/RB5 25 AVDD/VDD
12 PGC3/RP6/ASCL1/OCM1F/RB6 26 MCLR
13 RP7/OCM1A/CTED3/INT0/RB7 27 VREF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0
14 TCK/RP8/SCL1/OCM1B/CTED10/RB8 28 V
Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.
CAP
REF/AN6/C3INB/RP14/CTED5/RB14
REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1
DD 24 AVSS/VSS
/RP9/SDA1/T1CK/CTED4/RB9
2016-2020 Microchip Technology Inc. DS30010118E-page 3
PIC24FJ256GA705 FAMILY
Legend: See Table 3 for a complete description of pin functions.
Note: Gray shading indicates 5.5V tolerant input pins.
28-Pin SOIC, SSOP, SPDIP
MCLR
VSS
VDD
RA0
RA1
AVDD/VDD
AVSS/VSS
RB0
RB6
RA4
RB4
V
SS
RA3
RA2
V
CAP
RB7
RB9
RB8
RB3
RB2
RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB15
RB14
RB13
RB12
RB10
RB11
RB5
PIC24FJ256GA702
Pin Diagrams (PIC24FJ256GA702 Devices)
TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA702 SOIC, SSOP, SPDIP)
Pin Function Pin Function
1MCLR
2V
REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 16 RP7/OCM1A/CTED3/INT0/RB7
3V
REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 17 TCK/RP8/SCL1/OCM1B/CTED10/RB8
4 PGD1/AN2/CTCMP/C2INB/RP0/RB0 18 TDO/C1INC/C2INC/C3INC/TMPRN
5 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 19 V
6 AN4/C1INB/RP2/SDA2/CTED13/RB2 20 VCAP
7 AN5/C1INA/RP3/SCL2/CTED8/RB3 21 PGD2/TDI/RP10/OCM1C/CTED11/RB10
8V
SS 22 PGC2/TMS/REFI1/RP11/CTED9/RB11
9 OSCI/CLKI/C1IND/RA2 23 AN8/LVDIN/RP12/RB12
10 OSCO/CLKO/C2IND/RA3 24 AN7/C1INC/RP13/OCM1D/CTPLS/RB13
11 S OSCI /RP4/RB4 25 CV
12 SOSCO/PWRLCLK/RA4 26 AN9/C3INA/RP15/CTED6/RB15
13 V
DD 27 AVSS/VSS
14 PGD3/RP5/ASDA1/OCM1E/RB5 28 AVDD/VDD
Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.
15 PGC3/RP6/ASCL1/OCM1F/RB6
SS
REF/AN6/C3INB/RP14/CTED5/RB14
/RP9/SDA1/T1CK/CTED4/RB9
DS30010118E-page 4 2016-2020 Microchip Technology Inc.
Legend: See Table 4 for a complete description of pin functions.
Note: Gray shading indicates 5.5V tolerant input pins.
44-Pin TQFP
RB8
RB7
RB6
RB5
V
DD
RA9
RA4
VSS
RC5
RC4
RC3
RB12
RB11
RB10
V
CAP
VSS
RC9
RC8
RC7
RC6
RB9
RB13
RB2
RB3
RC0
RC1
RC2
RB4
V
DD
VSS
RA2
RA3
RA8
RB1
RB0
RA1
RA0
MCLR
RA10
AV
DD
AVSS
RB15
RB14
RA7
10
11
2
3
4
5
6
1
1819202122
121314
15
38
8
7
4443424140
39
16
17
29
30
31
32
33
23
24
25
26
27
28
363435
9
37
PIC24FJ256GA704
PIC24FJ256GA705 FAMILY
Pin Diagrams (PIC24FJ256GA704 Devices)
2016-2020 Microchip Technology Inc. DS30010118E-page 5
PIC24FJ256GA705 FAMILY
TABLE 4: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA704 TQFP)
Pin Function Pin Function
1 C1INC/C2INC/C3INC/TMPRN
2 RP22/PMA1/PMALH/RC6 24 AN5/C1INA/RP3/SCL2/CTED8/RB3
3 RP23/PMA0/PMALL/RC7 25 AN10/RP16/PMBE1/RC0
4 RP24/PMA5/RC8 26 AN11/RP17/PMA15/PMCS2/RC1
5 RP25/CTED7/PMA6/RC9 27 AN12/RP18/PMACK1/RC2
6Vss 28 V
7VCAP 29 VSS
8PGD2/RP10/OCM1C/CTED11/PMD2/RB10 30 OSCI/CLKI/C1IND/RA2
9PGC2/REFI1/RP11/CTED9/PMD1/RB11 31 OSCO/CLKO/C2IND/RA3
10 AN8/LVDIN/RP12/PMD0/RB12 32 TDO/PMA8/RA8
11 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR
12 TMS/RP28/PMA2/PMALU/RA10 34 SOSCO/PWRLCLK/RA4
13 TCK/PMA7/RA7 35 TDI/PMA9/RA9
14 CV
REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 36 AN13/RP19/PMBE0/RC3
15 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 37 RP20/PMA4/RC4
16 AV
SS 38 RP21/PMA3/RC5
17 AV
DD 39 VSS
18 MCLR 40 VDD
19 VREF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 41 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5
20 V
REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 42 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6
21 PGD1/AN2/CTCMP/C2INB/RP0/RB0 43 RP7/OCM1A/CTED3/PMD5/INT0/RB7
22 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 44 RP8/SCL1/OCM1B/CTED10/PMD4/RB8
Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.
/RP9/SDA1/T1CK/CTED4/PMD3/RB9 23 AN4/C1INB/RP2/SDA2/CTED13/RB2
DD
/RB13 33 SOSCI/RP4/RB4
DS30010118E-page 6 2016-2020 Microchip Technology Inc.
Legend: See Table 5 for a complete description of pin functions.
Note: Gray shading indicates 5.5V tolerant input pins.
48-Pin UQFN
48 47 46 45 43 42 41 40 39 38
13 14 15 16 17 18 19 21 22 23
3
33
31
30
29
28
27
26
25
4
5
7
9
10
11
12
1
2
35
34
6
24
36
37
VDD
VSS
RA8
RB4
VDD
VSS
RB13
RB12
RB11
RB10
V
CAP
VSS
RC9
RC8
RC7
RC6
RA10
RA7
RB14
AV
SS
AVDD
MCLR
PIC24FJ256GA705
8
RA11
20
RA12
32 RA13
44
RA14
RB15
RC1
RA9
RC3
RB8
RB5
RA4
RB7
RB6
RC5
RC4
RB9
RC2
RA3
RA2
RC0
RB3
RB2
RA1
RB1
RA0
RB0
PIC24FJ256GA705 FAMILY
Pin Diagrams (PIC24FJ256GA705 Devices)
2016-2020 Microchip Technology Inc. DS30010118E-page 7
PIC24FJ256GA705 FAMILY
TABLE 5: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA705 UQFN)
Pin Function Pin Function
1 C1INC/C2INC/C3INC/TMPRN
2 RP22/PMA1/PMALH/RC6 26 AN5/C1INA/RP3/SCL2/CTED8/RB3
3 RP23/PMA0/PMALL/RC7 27 AN10/RP16/PMBE1/RC0
4 RP24/PMA5/RC8 28 AN11/RP17/PMA15/PMCS2/RC1
5 RP25/CTED7/PMA6/RC9 29 AN12/RP18/PMACK1/RC2
6V
SS 30 VDD
7VCAP 31 VSS
8 RPI29/RA11 32 RPI31/RA13
9PGD2/RP10/OCM1C/CTED11/PMD2/RB10 33 OSCI/CLKI/C1IND/RA2
10 PGC2/REFI1/RP11/CTED9/PMD1/RB11 34 OSCO/CLKO/C2IND/RA3
11 AN 8/LV DIN/ RP12/PMD0/RB12 35 TDO/PMA8/RA8
12 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR
13 TMS/RP28/PMA2/PMALU/RA10 37 SOSCO/PWRLCLK/RA4
14 TCK/PMA7/RA7 38 TDI/PMA9/RA9
15 CV
REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 39 AN13/RP19/PMBE0/RC3
16 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 40 RP20/PMA4/RC4
17 AV
SS 41 RP21/PMA3/RC5
18 AV
DD 42 VSS
19 MCLR 43 VDD
20 RPI30/RA12 44 RPI32/RA14
21 V
REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 45 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5
22 V
REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 46 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6
23 PGD1/AN2/CTCMP/C2INB/RP0/RB0 47 RP7/OCM1A/CTED3/PMD5/INT0/RB7
24 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 48 RP8/SCL1/OCM1B/CTED10/PMD4/RB8
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
/RP9/SDA1/T1CK/CTED4/PMD3/RB9 25 AN4/C1INB/RP2/SDA2/CTED13/RB2
/RB13 36 SOSCI/RP4/RB4
DS30010118E-page 8 2016-2020 Microchip Technology Inc.
Legend: See Table 6 for a complete description of pin functions.
Note: Gray shading indicates 5.5V tolerant input pins.
48-Pin TQFP
RB8
RB7
RB6
RB5
RA14
RC3
RA9
VDDVSS
RC5
RC4
RB12
RB11
RB10
RA11
VCAP
VSS
RC9
RC8
RC7
RC6
RB13
RB3
RC0
RC1
RC2
V
DD
RB4
V
SS
RA13
RA2
RA3
RA8
RB1
RB0
RA1
RA0
RA12
RA7
MCLR
AVDD
AVSS
RB15
RB14
11
12
3
4
5
6
7
2
2021222324
141516
17
42
9
8
4847464544
4318
19
32
33
34
35
36
26
27
28
29
30
31
403839
10
41
RA4
37
RB2
25
RA10
13
RB9
1
PIC24FJ256GA705
PIC24FJ256GA705 FAMILY
Pin Diagrams (PIC24FJ256GA705 Devices)
2016-2020 Microchip Technology Inc. DS30010118E-page 9
PIC24FJ256GA705 FAMILY
TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA705 TQFP)
Pin Function Pin Function
1 C1INC/C2INC/C3INC/TMPRN
2 RP22/PMA1/PMALH/RC6 26 AN5/C1INA/RP3/SCL2/CTED8/RB3
3 RP23/PMA0/PMALL/RC7 27 AN10/RP16/PMBE1/RC0
4 RP24/PMA5/RC8 28 AN11/RP17/PMA15/PMCS2/RC1
5 RP25/CTED7/PMA6/RC9 29 AN12/RP18/PMACK1/RC2
6V
SS 30 VDD
7VCAP 31 VSS
8 RPI29/RA11 32 RPI31/RA13
9PGD2/RP10/OCM1C/CTED11/PMD2/RB10 33 OSCI/CLKI/C1IND/RA2
10 PGC2/REFI1/RP11/CTED9/PMD1/RB11 34 OSCO/CLKO/C2IND/RA3
11 AN 8/LV DIN/ RP12/PMD0//RB12 35 TDO/PMA8/RA8
12 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR
13 TMS/RP28/PMA2/PMALU/RA10 37 SOSCO/PWRLCLK/RA4
14 TCK/PMA7/RA7 38 TDI/PMA9/RA9
15 CV
REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 39 AN13/RP19/PMBE0/RC3
16 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 40 RP20/PMA4/RC4
17 AV
SS 41 RP21/PMA3/RC5
18 AV
DD 42 VSS
19 MCLR 43 VDD
20 RPI30/RA12 44 RPI32/RA14
21 V
REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 45 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5
22 V
REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 46 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6
23 PGD1/AN2/CTCMP/C2INB/RP0/RB0 47 RP7/OCM1A/CTED3/PMD5/INT0/RB7
24 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 48 RP8/SCL1/OCM1B/CTED10/PMD4/RB8
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
/RP9/SDA1/T1CK/CTED4/PMD3/RB9 25 AN4/C1INB/RP2/SDA2/CTED13/RB2
/RB13 36 SOSCI/RP4/RB4
DS30010118E-page 10 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 29
3.0 CPU ........................................................................................................................................................................................... 35
4.0 Memory Organization ................................................................................................................................................................. 41
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 63
6.0 Flash Program Memory.............................................................................................................................................................. 71
7.0 Resets ........................................................................................................................................................................................ 79
8.0 Interrupt Controller ..................................................................................................................................................................... 85
9.0 Oscillator Configuration.............................................................................................................................................................. 97
10.0 Power-Saving Features............................................................................................................................................................ 113
11.0 I/O Ports ................................................................................................................................................................................... 125
12.0 Timer1 ...................................................................................................................................................................................... 159
13.0 Timer2/3 .................................................................................................................................................................................. 161
14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 167
15.0 Output Compare with Dedicated Timers .................................................................................................................................. 173
16.0 Capture/Compare/PWM/Timer Modules (MCCP).................................................................................................................... 183
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 199
18.0 Inter-Integrated Circuit (I
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 227
20.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 237
21.0 Real-Time Clock and Calendar (RTCC) with Timestamp......................................................................................................... 249
22.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 269
23.0 Configurable Logic Cell (CLC) Generator ................................................................................................................................ 275
24.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 285
25.0 Triple Comparator Module........................................................................................................................................................ 307
26.0 Comparator Voltage Reference................................................................................................................................................ 313
27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 315
28.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 325
29.0 Special Features ...................................................................................................................................................................... 327
30.0 Development Support............................................................................................................................................................... 343
31.0 Instruction Set Summary.......................................................................................................................................................... 345
32.0 Electrical Characteristics.......................................................................................................................................................... 353
33.0 Packaging Information.............................................................................................................................................................. 387
Appendix A: Revision History............................................................................................................................................................. 411
Index ................................................................................................................................................................................................. 413
The Microchip Website ...................................................................................................................................................................... 419
Customer Change Notification Service .............................................................................................................................................. 419
Customer Support .............................................................................................................................................................................. 419
Product Identification System ............................................................................................................................................................ 421
2
C) ..................................................................................................................................................... 219
2016-2020 Microchip Technology Inc. DS30010118E-page 11
PIC24FJ256GA705 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our website at www.microchip.com to receive the most current information on all of our products.
DS30010118E-page 12 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of the
PIC24FJ256GA705 product page of the
Microchip website (www.microchip.com) or
select a family reference manual section
from the following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• “CPU with Extended Data Space (EDS)” (DS39732)
• “Direct Memory Access Controller (DMA)” (DS30009742)
• “PIC24F Flash Program Memory” (DS30009715)
• “Data Memory with Extended Data Space (EDS)” (DS39733)
• “Reset” (DS39712)
• “Interrupts” (DS70000600)
• “Oscillator” (DS39700)
• “Power-Saving Features with Deep Sleep” (DS39727)
• “I/O Ports with Peripheral Pin Select (PPS)” (DS30009711)
• “Timers” (DS39704)
• ”Input Capture with Dedicated Timer” (DS70000352)
• “Output Compare with Dedicated Timer” (DS70005159)
• “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS30003035)
• “Serial Peripheral Interface (SPI) with Audio Codec Support” (DS70005136)
• “Inter-Integrated Circuit (I
• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)
• “Enhanced Parallel Master Port (EPMP)” (DS39730)
• “RTCC with Timestamp” (DS70005193)
• “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS30009729)
• “Configurable Logic Cell (CLC)” (DS70005298)
• “12-Bit A/D Converter with Threshold Detect” (DS39739)
• “Scalable Comparator Module” (DS39734)
• “Dual Comparator Module” (DS39710)
• “Charge Time Measurement Unit (CTMU) and CTMU Operation with Threshold Detect” (DS30009743)
• “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725)
• “Watchdog Timer (WDT)” (DS39697)
• “CodeGuard™ Intermediate Security” (DS70005182)
• “High-Level Device Integration” (DS39719)
• “Programming and Diagnostics” (DS39716)
• “Comparator Voltage Reference Module” (DS39709)
2
C)” (DS70000195)
2016-2020 Microchip Technology Inc. DS30010118E-page 13
PIC24FJ256GA705 FAMILY
NOTES:
DS30010118E-page 14 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA705 • PIC24FJ256GA704
• PIC24FJ128GA705 • PIC24FJ64GA702
• PIC24FJ256GA705 • PIC24FJ128GA702
• PIC24FJ64GA704 • PIC24FJ256GA702
• PIC24FJ128GA704
The PIC24FJ256GA705 family introduces large Flash
and SRAM memory in smaller package sizes. This is a
16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
This family also offers a new migration option for those
high-performance applications which may be outgrowing their 8-bit platforms, but do not require the numerical
processing power of a Digital Signal Processor (DSP).
Table 1-3 lists the functions of the various pins shown
in the pinout diagrams.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements,
such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
The PIC24FJ256GA705 family of devices includes
Retention Sleep, a low-power mode with essential
circuits being powered from a separate low-voltage
regulator.
This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.
Aside from this new feature, PIC24FJ256GA705 family
devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and Sleep modes
1.1.3 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ256GA705 family offer
six different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes
• External Clock (EC) mode
• A Phase-Locked Loop (PLL) frequency multiplier,
which allows processor speeds up to 32 MHz
• An internal Fast RC Oscillator (FRC), a nominal
8 MHz output with multiple frequency divider
options
• A separate internal Low-Power RC Oscillator
(LPRC), 31 kHz nominal for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the internal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
2016-2020 Microchip Technology Inc. DS30010118E-page 15
PIC24FJ256GA705 FAMILY
1.2 DMA Controller
PIC24FJ256GA705 family devices have a Direct Memory
Access (DMA) Controller. This module acts in concert
with the CPU, allowing data to move between data
memory and peripherals without the intervention of the
CPU, increasing data throughput and decreasing execution time overhead. Six independently programmable
channels make it possible to service multiple peripherals
at virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
1.3 Other Special Features
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
• Configurable Logic Cell: The Configurable
Logic Cell (CLC) module allows the user to
specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins.
• Timing Modules: The PIC24FJ256GA705 family
provides three independent, general purpose,
16-bit timers (two of which can be combined
into a 32-bit timer). The devices also include
four multiple output advanced
Capture/Compare/PWM/Timer peripherals, and
three independent legacy Input Capture and
three independent legacy Output Compare modules.
• Communications: The PIC24FJ256GA705 family
incorporates a range of serial
communication peripherals to handle a range of
application requirements. There are two indepen-
2
C modules that support both Master and
dent I
Slave modes of operation. Devices also have,
through the PPS feature, two independent UARTs
with built-in IrDA
three SPI modules.
• Analog Features: All members of the
PIC24FJ256GA705 family include a 12-bit A/D
Converter (A/D) module and a triple comparator
module. The A/D module incorporates a range of
new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog
comparators that are configurable for a wide
range of operations.
• CTMU Interface: In addition to their other analog
features, members of the PIC24FJ256GA705
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can serve
as an interface for capacitive sensors.
®
encoders/decoders and
• Enhanced Parallel Master/Parallel Slave Port:
This module allows rapid and transparent access to
the microcontroller data bus, and enables the CPU
to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of four or eight bits and
address widths of up to ten bits in Master modes.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
1.4 Details on Individual Family Members
Devices in the PIC24FJ256GA705 family are available
in 28-pin, 44-pin and 48-pin packages. The general
block diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in
five ways:
1. Flash program memory (64 Kbytes for
PIC24FJ64GA70X devices, 128 Kbytes for
PIC24FJ128GA70X devices, 256 Kbytes for
PIC24FJ256GA70X devices).
2. Available I/O pins and ports (22 pins on two
ports for 28-pin devices, and 36 and 40 pins on
three ports for 44-pin/48-pin devices).
3. Enhanced Parallel Master Port (EPMP) is only
available on 44-pin/48-pin devices.
4. Analog input channels (10 channels for 28-pin
devices and 14 channels for 44-pin/48-pin
devices).
5. CTMU input channels (12 channels for 28-pin
devices and 13 channels for 44-pin/48-pin
devices)
All other features for devices in this family are identical.
These are summarized in Ta bl e 1 - 1 and Ta bl e 1- 2.
A list of the pin features available on the
PIC24FJ256GA705 family devices, sorted by function, is shown in Tab le 1 -3 . Note that this table shows
the pin location of individual peripheral features and not
how they are multiplexed on the same pin. This
information is provided in the pinout diagrams in the
beginning of this data sheet. Multiplexed features are
sorted by the priority given to a feature, with the highest
priority peripheral being listed first.
DS30010118E-page 16 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJXXXGA702: 28-PIN DEVICES
Features PIC24FJ64GA702 PIC24FJ128GA702 PIC24FJ256GA702
Operating Frequency DC – 32 MHz
Program Memory (bytes) 64K 128K 256K
Program Memory
(instruction words, 24 bits)
Data Memory (bytes) 16K
Interrupt Sources
(soft vectors/NMI traps)
I/O Ports Ports A, B
Total I/O Pins 22
Remappable Pins 18 (18 I/Os, 0 inputs only)
DMA 1 6-channel
16-Bit Timers 3
Real-Time Clock and Calendar
(RTCC)
Cyclic Redundancy Check (CRC) Yes
Input Capture Channels 3
Output Compare/PWM Channels 3
Input Change Notification Interrupt 21 (remappable pins)
Serial Communications:
UART 2
SPI (three-wire/four-wire) 3
I2C 2
Configurable Logic Cell (CLC) 2
Parallel Communications
(EPMP/PSP)
Capture/Compare/PWM/Timer
Modules
JTAG Boundary Scan Yes
10/12-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
Universal Serial Bus Controller No
Resets (and Delays) Core POR, V
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 28-Pin QFN, UQFN, SOIC, SSOP and SPDIP
Note 1: Some peripherals are accessible through remappable pins.
2: 28-Pin SPDIP is available only in the highest Flash variant.
22,528 45,056 88,064
124
(1)
Ye s
(1)
(1)
(1)
(1)
(1)
No
4 Multiple CCPs
1 (6-output), 3 (2-output)
10
DD POR, BOR, RESET Instruction,
MCLR
, WDT, Illegal Opcode, REPEAT Instruction,
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
(2)
2016-2020 Microchip Technology Inc. DS30010118E-page 17
PIC24FJ256GA705 FAMILY
TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJXXXGA70X: 44-PIN AND 48-PIN DEVICES
Features PIC24FJ64GA70X PIC24FJ128GA70X PIC24FJ256GA70X
Operating Frequency DC – 32 MHz
Program Memory (bytes) 64K 128K 256K
Program Memory
(instruction words, 24 bits)
Data Memory (bytes) 16K
Interrupt Sources
(soft vectors/NMI traps)
I/O Ports Ports A, B, C
Total I/O Pins:
44-pin 35 35 35
48-pin 39 39 39
Remappable Pins:
44-pin 29 (29 I/Os, 0 inputs only)
48-pin 33 (29 I/Os, 4 inputs only)
DMA (6-channel) 1
16-Bit Timers 3
Real-Time Clock and Calendar
(RTCC)
Cyclic Redundancy Check (CRC) Yes
Input Capture Channels 3
Output Compare/PWM Channels 3
Input Change Notification Interrupt 25 (remappable pins)
Serial Communications:
UART 2
SPI (three-wire/four-wire) 3
I2C 2
Configurable Logic Cell (CLC) 2
Parallel Communications
(EPMP/PSP)
Capture/Compare/PWM/Timer
Modules (MCCP)
JTAG Boundary Scan Yes
10/12-Bit Analog-to-Digital Converter
(A/D) Module (input channels)
Analog Comparators 3
CTMU Interface Yes
Universal Serial Bus Controller No
Resets (and delays) Core POR, VDD POR, BOR, RESET Instruction,
Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations
Packages 44-Pin TQFP, 48-Pin TQFP and UQFN
Note 1: Some peripherals are accessible through remappable pins.
22,528 45,056 88,064
124
(1)
Yes
(1)
(1)
(1)
(1)
(1)
Yes
4 Modules
1 (6-output), 3 (2-output)
14
, WDT, Illegal Opcode, REPEAT Instruction,
MCLR
Hardware Traps, Configuration Word Mismatch
(OST, PLL Lock)
DS30010118E-page 18 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
Instruction
Decode and
Control
16
PCH
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
16
16
8
Interrupt
Controller
EDS and
Stac k
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Extended Data
Data Latch
16
Address Bus
Literal
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
HLVD &
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulators
Voltage
VCAP
PORTA
(1)
PORTC
(1)
(12 I/Os)
(8 I/Os)
PORTB
(16 I/Os)
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Ta b le 1- 3 for specific implementations by pin count.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: Some peripheral I/Os are only accessible through remappable pins.
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC
A/D
12-Bit
OC/PWM
SPI
I2C1-2
EPMP/PSP
1-3
(3)
IOCs
(1)
UART
REFO
1-3
(3)
1-2
(3)
1-3
(3)
CTMU
Space
Program Memory/
CLC1-2
(1)
DMA
Controller
Data
DMA
Data Bus
16
Ta ble Da t a
Access Control
MCCP1/2/3
PCL
BOR
(2)
Read AGU
Write AGU
FIGURE 1-1: PIC24FJ256GA705 FAMILY GENERAL BLOCK DIAGRAM
2016-2020 Microchip Technology Inc. DS30010118E-page 19
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS
Pin
Function
AN0 2 27 19 21 I ANA A/D Analog Inputs
AN1 3 28 20 22 I ANA
AN2 4 1 21 23 I ANA
AN3 5 2 22 24 I ANA
AN4 6 3 23 25 I ANA
AN5 7 4 24 26 I ANA
AN6 25 22 14 15 I ANA
AN7 24 21 11 12 I ANA
AN8 23 20 10 11 I ANA
AN9 26 23 15 16 I ANA
AN10 — — 25 27 I ANA
AN11 — — 26 28 I ANA
AN12 — — 27 29 I ANA
AN13 — — 36 39 I ANA
DD 28 25 17 18 P — Positive Supply for Analog modules
AV
SS 27 24 16 17 P — Ground Reference for Analog modules
AV
C1INA 7 4 24 26 I ANA Comparator 1 Input A
C1INB 6 3 23 25 I ANA Comparator 1 Input B
C1INC 18, 24 15, 21 1, 11 1, 12 I ANA Comparator 1 Input C
C1IND 9 6 30 33 I ANA Comparator 1 Input D
C2INA 5 2 22 24 I ANA Comparator 2 Input A
C2INB 4 1 21 23 I ANA Comparator 2 Input B
C2INC 18 15 1 1 I ANA Comparator 2 Input C
C2IND 10 7 31 34 I ANA Comparator 2 Input D
C3INA 26 23 15 16 I ANA Comparator 3 Input A
C3INB 25 22 14 15 I ANA Comparator 3 Input B
C3INC 2, 18 15, 27 1, 19 1, 21 I ANA Comparator 3 Input C
C3IND 3 28 20 22 I ANA Comparator 3 Input D
CLKI 9 6 30 33 — — Main Clock Input Connection
CLKO 10 7 31 34 O DIG System Clock Output
CTCMP 4 1 21 23 O ANA CTMU Comparator 2 Input (Pulse mode)
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
44-Pin
TQFP
2
48-Pin
UQFN/TQFP
C = I2C/SMBus input buffer
I/O
Input
Buffer
Description
DS30010118E-page 20 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
CTED1 2 27 19 21 I ST CTMU External Edge Inputs
CTED2 3 28 20 22 I ST
CTED3 16 13 43 47 I ST
CTED4 18 15 1 1 I ST
CTED5 25 22 14 15 I ST
CTED6 26 23 15 16 I ST
CTED7 — — 5 5 I ST
CTED8 7 4 24 26 I ST
CTED9 22 19 9 10 I ST
CTED10 17 14 44 48 I ST
CTED11 21 18 8 9 I ST
CTED12 5 2 22 24 I ST
CTED13 6 3 23 25 I ST
CTPLS 24 21 11 12 O DIG CTMU Pulse Output
REF 25 22 14 15 O ANA Comparator Voltage Reference Output
CV
REF+ 2 27 19 21 I ANA Comparator Voltage Reference (high) Input
CV
CV
REF- 3 28 20 22 I ANA Comparator Voltage Reference (low) Input
INT0 16 13 43 47 I ST External Interrupt Input 0
IOCA0 2 27 19 21 I ST PORTA Interrupt-on-Change
IOCA1 3 28 20 22 I ST
IOCA2 9 6 30 33 I ST
IOCA3 10 7 31 34 I ST
IOCA4 12 9 34 37 I ST
IOCA7 — — 13 14 I ST
IOCA8 — — 32 35 I ST
IOCA9 — — 35 38 I ST
IOCA10 — — 12 13 I ST
IOCA11 — — — 8 I ST
IOCA12 — — — 20 I ST
IOCA13 — — — 32 I ST
IOCA14 — — — 44 I ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
44-Pin
TQFP
2
48-Pin
UQFN/TQFP
C = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2016-2020 Microchip Technology Inc. DS30010118E-page 21
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
IOCB0 4 1 21 23 I ST PORTB Interrupt-on-Change
IOCB1 5 2 22 24 I ST
IOCB2 6 3 23 25 I ST
IOCB3 7 4 24 26 I ST
IOCB4 11 8 33 36 I ST
IOCB5 14 11 41 45 I ST
IOCB6 15 12 42 46 I ST
IOCB7 16 13 43 47 I ST
IOCB8 17 14 44 48 I ST
IOCB9 18 15 1 1 I ST
IOCB10 21 18 8 9 I ST
IOCB11 22 19 9 10 I ST
IOCB12 23 20 10 11 I ST
IOCB13 24 21 11 12 I ST
IOCB14 25 22 14 15 I ST
IOCB15 26 23 15 16 I ST
IOCC1 — — 26 28 I ST PORTC Interrupt-on-Change
IOCC2 — — 27 29 I ST
IOCC3 — — 36 39 I ST
IOCC4 — — 37 40 I ST
IOCC5 — — 38 41 I ST
IOCC6 — — 2 2 I ST
IOCC7 — — 3 3 I ST
IOCC8 — — 4 4 I ST
IOCC9 — — 5 5 I ST
LVDIN 23 20 10 11 I ANA High/Low-Voltage Detect
MCLR
OCM1A 16 13 43 47 O DIG MCCP1 Outputs
OCM1B 17 14 44 48 O DIG
OCM1C 21 18 8 9 O DIG
OCM1D 24 21 11 12 O DIG
OCM1E 14 11 41 45 O DIG
OCM1F 15 12 42 46 O DIG
OSCI 9 6 30 33 I ANA/ST Main Oscillator Input Connection
OSCO 10 7 31 34 O ANA Main Oscillator Output Connection
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
1 26 18 19 I ST Master Clear (device Reset) Input. This line
44-Pin
TQFP
48-Pin
UQFN/TQFP
2
C = I2C/SMBus input buffer
I/O
Input
Buffer
Description
is brought low to cause a Reset.
DS30010118E-page 22 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
PGC1 5 2 22 24 I ST ICSP™ Programming Clock
PGC2 22 19 9 10 I ST
PGC3 15 12 42 46 I ST
PGD1 4 1 21 23 I/O DIG/ST ICSP Programming Data
PGD2 21 18 8 9 I/O DIG/ST
PGD3 14 11 41 45 I/O DIG/ST
PMA0 — — 3 3 I/O DIG/ST/
PMA1 — — 2 2 I/O DIG/ST/
PMA2 — — 12 13 I/O DIG/ST/
PMA3 — — 38 41 I/O DIG/ST/
PMA4 — — 37 40 I/O DIG/ST/
PMA5 — — 4 4 I/O DIG/ST/
PMA6 — — 5 5 I/O DIG/ST/
PMA7 — — 13 14 I/O DIG/ST/
PMA8 — — 32 35 I/O DIG/ST/
PMA9 — — 35 38 I/O DIG/ST/
PMA14/PMCS/
PMCS1
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
— — 15 16 I/O DIG/ST/
44-Pin
TQFP
48-Pin
UQFN/TQFP
2
C = I2C/SMBus input buffer
I/O
Input
Buffer
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
Parallel Master Port Address[0]/
Address Latch Low
Parallel Master Port Address[1]/
Address Latch High
Parallel Master Port Address[2]
Parallel Master Port Address[3]
Parallel Master Port Address[4]
Parallel Master Port Address[5]
Parallel Master Port Address[6]
Parallel Master Port Address[7]
Parallel Master Port Address[8]
Parallel Master Port Address[9]
Parallel Master Port Address[14]/
Slave Chip Select/Chip Select 1 Strobe
2016-2020 Microchip Technology Inc. DS30010118E-page 23
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
PMD0 — — 10 11 I/O DIG/ST/
PMD1 — — 9 10 I/O DIG/ST/
PMD2 — — 8 9 I/O DIG/ST/
PMD3 — — 1 1 I/O DIG/ST/
PMD4 — — 44 48 I/O DIG/ST/
PMD5 — — 43 47 I/O DIG/ST/
PMD6 — — 42 46 I/O DIG/ST/
PMD7 — — 41 45 I/O DIG/ST/
PMRD/PMWR
PMWR/PMENB — — 14 15 I/O DIG/ST/
PWRGT — — — — O DIG Real-Time Clock Power Control Output
PWRLCLK 12 9 34 37 I ST Real-Time Clock 50/60 Hz Clock Input
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
——1112I/ODIG/ST/
44-Pin
TQFP
48-Pin
UQFN/TQFP
2
C = I2C/SMBus input buffer
I/O
Input
Buffer
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Parallel Master Port Data (Demultiplexed
Master mode) or Address/Data
(Multiplexed Master modes)
Parallel Master Port Read Strobe/
Write Strobe
Parallel Master Port Write Strobe/
Enable Strobe
Description
DS30010118E-page 24 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RA0 2 27 19 21 I/O DIG/ST PORTA Digital I/Os
RA1 3 28 20 22 I/O DIG/ST
RA2 9 6 30 33 I/O DIG/ST
RA3 10 7 31 34 I/O DIG/ST
RA4 12 9 34 37 I/O DIG/ST
RA7 — — 13 14 I/O DIG/ST
RA8 — — 32 35 I/O DIG/ST
RA9 — — 35 38 I/O DIG/ST
RA10 — — 12 13 I/O DIG/ST
RA11 — — — 8 I/O DIG/ST
RA12 — — — 20 I/O DIG/ST
RA13 — — — 32 I/O DIG/ST
RA14 — — — 44 I/O DIG/ST
RB0 4 1 21 23 I/O DIG/ST PORTB Digital I/Os
RB1 5 2 22 24 I/O DIG/ST
RB2 6 3 23 25 I/O DIG/ST
RB3 7 4 24 26 I/O DIG/ST
RB4 11 8 33 36 I/O DIG/ST
RB5 14 11 41 45 I/O DIG/ST
RB6 15 12 42 46 I/O DIG/ST
RB7 16 13 43 47 I/O DIG/ST
RB8 17 14 44 48 I/O DIG/ST
RB9 18 15 1 1 I/O DIG/ST
RB10 21 18 8 9 I/O DIG/ST
RB11 22 19 9 10 I/O DIG/ST
RB12 23 20 10 11 I/O DIG/ST
RB13 24 21 11 12 I/O DIG/ST
RB14 25 22 14 15 I/O DIG/ST
RB15 26 23 15 16 I/O DIG/ST
RC0 — — 25 27 I/O DIG/ST PORTC Digital I/Os
RC1 — — 26 28 I/O DIG/ST
RC2 — — 27 29 I/O DIG/ST
RC3 — — 36 39 I/O DIG/ST
RC4 — — 37 40 I/O DIG/ST
RC5 — — 38 41 I/O DIG/ST
RC6 — — 2 2 I/O DIG/ST
RC7 — — 3 3 I/O DIG/ST
RC8 — — 4 4 I/O DIG/ST
RC9 — — 5 5 I/O DIG/ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
44-Pin
TQFP
2
48-Pin
UQFN/TQFP
C = I2C/SMBus input buffer
I/O
Input
Buffer
Description
2016-2020 Microchip Technology Inc. DS30010118E-page 25
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
RP0 4 1 21 23 I/O DIG/ST Remappable Peripherals
RP1 5 2 22 24 I/O DIG/ST
RP2 6 3 23 25 I/O DIG/ST
RP3 7 4 24 26 I/O DIG/ST
RP4 11 8 33 36 I/O DIG/ST
RP5 14 11 41 45 I/O DIG/ST
RP6 15 12 42 46 I/O DIG/ST
RP7 16 13 43 47 I/O DIG/ST
RP8 17 14 44 48 I/O DIG/ST
RP9 18 15 1 1 I/O DIG/ST
RP10 21 18 8 9 I/O DIG/ST
RP11 22 19 9 10 I/O DIG/ST
RP12 23 20 10 11 I/O DIG/ST
RP13 24 21 11 12 I/O DIG/ST
RP14 25 22 14 15 I/O DIG/ST
RP15 26 23 15 16 I/O DIG/ST
RP16 — — 25 27 I/O DIG/ST
RP17 — — 26 28 I/O DIG/ST
RP18 — — 27 29 I/O DIG/ST
RP19 — — 36 39 I/O DIG/ST
RP20 — — 37 40 I/O DIG/ST
RP21 — — 38 41 I/O DIG/ST
RP22 — — 2 2 I/O DIG/ST
RP23 — — 3 3 I/O DIG/ST
RP24 — — 4 4 I/O DIG/ST
RP25 — — 5 5 I/O DIG/ST
RP26 2 27 19 21 I/O DIG/ST
RP27 3 28 20 22 I/O DIG/ST
RP28 — — 12 13 I/O DIG/ST
RPI29 — — — 8 I DIG/ST Remappable Peripherals
RPI30 — — — 20 I DIG/ST
RPI31 — — — 32 I DIG/ST
RPI32 — — — 44 I DIG/ST
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
28-Pin SOIC,
SSOP, SPDIP
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
44-Pin
TQFP
2
48-Pin
UQFN/TQFP
C = I2C/SMBus input buffer
I/O
Input
Buffer
Description
(input or output)
(input only)
DS30010118E-page 26 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
28-Pin SOIC,
SSOP, SPDIP
SCL1 17 14 44 48 I/O I2C I2C1 Synchronous Serial Clock Input/Output
SCL2 7 4 24 26 I/O I
SDA1 18 15 1 1 I/O I
SDA2 6 3 23 25 I/O I
SOSCI 11 8 33 36 I ANA/ST Secondary Oscillator/Timer1 Clock Input
SOSCO 12 9 34 37 O ANA Secondary Oscillator/Timer1 Clock Output
T1CK 18 15 1 1 I ST Timer1 Clock
TCK 17 14 13 14 I ST JTAG Test Clock/Programming Clock Input
TDI 21 18 35 38 I ST JTAG Test Data/Programming Data Input
TDO 18 15 32 35 O DIG JTAG Test Data Output
TMPRN
TMS 22 19 12 13 I ST JTAG Test Mode Select Input
CAP 20 17 7 7 P — External Filter Capacitor
V
DD 13, 28 10, 25 28, 40 30, 43 P — Positive Supply for Peripheral Digital Logic
V
REF+ 2 27 19 21 I ANA Comparator and A/D Reference Voltage
V
REF- 3 28 20 22 I ANA Comparator and A/D Reference Voltage
V
SS 8, 19, 27 5, 16, 24 6, 29, 39 6, 31, 42 P — Ground Reference for
V
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver
Pin Number/Grid Locator
28-Pin QFN,
UQFN
44-Pin
TQFP
48-Pin
UQFN/TQFP
I/O
Buffer
2
C I2C2 Synchronous Serial Clock Input/Output
2
C I2C1 Data Input/Output
2
C I2C2 Data Input/Output
Description
Input
18 15 1 1 I ST Tamper Detect Input
Connection (regulator enabled)
and I/O Pins
(high) Input
(low) Input
Peripheral Digital Logic and I/O Pins
2
C = I2C/SMBus input buffer
2016-2020 Microchip Technology Inc. DS30010118E-page 27
PIC24FJ256GA705 FAMILY
NOTES:
DS30010118E-page 28 2016-2020 Microchip Technology Inc.
PIC24FJ256GA705 FAMILY
PIC24FJXXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
VDD
MCLR
VCAP
R2
C7
C2
(2)
C3
(2)
C4
(2)
C5
(2)
C6
(2)
Key (all values are recommendations):
C1 through C6: 0.1 µF, 50V ceramic
C7: 10 µF, 16V or greater, ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pin
(V
CAP)” for an explanation of voltage
regulator pin connections.
2: The example shown is for a PIC24F device
with five V
DD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)
2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC24FJ256GA705 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
The following pins must always be connected:
DD and VSS pins
•All V
(see Section 2.2 “Power Supply Pins”)
•All AV
•MCLR
•V
These pins must also be connected if they are being
used in the end application:
• PGCx/PGDx pins used for In-Circuit Serial
• OSCI and OSCO pins when an external oscillator
Additionally, the following pins may be required:
•V
The minimum mandatory connections are shown in
Figure 2-1.
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
CAP pin
(see Section 2.4 “Voltage Regulator Pin (V
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
REF+/VREF- pins used when external voltage
reference for analog modules is implemented
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
CAP)”)
2016-2020 Microchip Technology Inc. DS30010118E-page 29
PIC24FJ256GA705 FAMILY
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR
from the external capacitor, C, in the
event of a MCLR
pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin
V
IH and VIL specifications are met.
C1
R2
R1
V
DD
MCLR
PIC24FXXX
JP
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as V
SS, is required.
AV
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 µF (100 nF),
25V-50V capacitor is recommended. The
capacitor should be a low-ESR device with a
self-resonance frequency in the range of 200 MHz
and higher. Ceramic capacitors are
recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic-type
capacitor in parallel to the above described
decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 µF to
0.001 µF. Place this second capacitor next to
each primary decoupling capacitor. In high-speed
circuit designs, consider implementing a decade
pair of capacitances as close to the power and
ground pins as possible (e.g., 0.1 µF in parallel
with 0.001 µF).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
DD, VSS, AVDD and
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
device Reset, and device programming and debugging. If programming and debugging are not required
in the end application, a direct connection to V
may be all that is required. The addition of other
components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented
depending on the application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V
IH and VIL) and fast signal transitions must
pin. Consequently, specific voltage
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR
pin during programming and debugging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
DD
pin
2.2.2 BULK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a bulk
capacitance of 10 µF or greater located near the MCU.
The value of the capacitor should be determined based
on the trace resistance that connects the power supply
source to the device, and the maximum current drawn
by the device in the application. Typical values range
from 10 µF to 47 µF. The capacitor should be ceramic
and have a voltage rating of 25V or more to reduce DC
bias effects (see Section 2.4.1 “Considerations for
Ceramic Capacitors”).
DS30010118E-page 30 2016-2020 Microchip Technology Inc.
Loading...