Datasheet EV54Y39A Datasheet

PIC24FJ256GA705 FAMILY

16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and

16-Kbyte RAM in Low Pin Count Packages

High-Performance CPU

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Fast RC Internal Oscillator:

- 96 MHz PLL option

- Multiple clock divide options

- Fast start-up

• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16-Bit x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture

• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory

• Six-Channel DMA Controller

Analog Features

• Up to 14-Channel, Software-Selectable,
10/12-Bit Analog-to-Digital Converter:

- 12-bit, 200K samples/second conversion rate

(single Sample-and-Hold)

- Sleep mode operation

- Charge pump for operating at lower AV

- Band gap reference input feature

- Windowed threshold compare feature

- Auto-scan feature

• Three Analog Comparators with Input Multiplexing:

- Programmable reference voltage for

comparators

• LVD Interrupt Above/Below Programmable

LVD Level

V

• Charge Time Measurement Unit (CTMU):

- Allows measurement of capacitance and time

- Operational in Sleep

DD

Low-Power Features

• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up

• Doze mode allows CPU to Run at a Lower Clock
Speed than Peripherals

• Alternate Clock modes allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction

Special Microcontroller Features

• Supply Voltage Range of 2.0V to 3.6V

• Dual Voltage Regulators:

- 1.8V core regulator

- 1.2V regulator for Retention Sleep mode

• Operating Ambient Temperature Range of

-40°C to +125°C

• ECC Flash Memory (256 Kbytes):

- Single Error Correction (SEC)

- Double Error Detection (DED)

- 10,000 erase/write cycle endurance, typical

- Data retention: 20 years minimum

- Self-programmable under software control

• 16-Kbyte SRAM

• Programmable Reference Clock Output

• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins

• JTAG Boundary Scan Support

• Fail-Safe Clock Monitor Operation:

- Detects clock failure and switches to on-chip,

Low-Power RC (LPRC) Oscillator

• Power-on Reset (POR), Brown-out Reset (BOR)
and Oscillator Start-up Timer (OST)

• Programmable Low-Voltage Detect (LVD)

• Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1 -40°C to +125°C)

• Class B Safety Library, IEC 60730

 2016-2020 Microchip Technology Inc. DS30010118E-page 1

PIC24FJ256GA705 FAMILY

Peripheral Features

• High-Current Sink/Source 18 mA/18 mA on
All I/O Pins

• Independent, Low-Power 32 kHz Timer Oscillator

• Timer1: 16-Bit Timer/Counter with External Crystal
Oscillator; Timer1 can Provide an A/D Trigger

• Timer2,3: 16-Bit Timer/Counter, can Create 32-Bit
Timer; Timer3 can Provide an A/D Trigger

• Three Input Capture modules, Each with a
16-Bit Timer

• Three Output Compare/PWM modules, Each with
a 16-Bit Timer

• Four MCCP modules, Each with a Dedicated
16/32-Bit Timer:

- One 6-output MCCP module

- Three 2-output MCCP modules

• Three Variable Widths, Synchronous Peripheral
Interface (SPI) Ports on All Devices; Three
Operation modes:

- Three-wire SPI (supports all four SPI modes)

- 8 by 16-bit or 8 by 8-bit FIFO

2

-I

S mode

•Two I

2

C Masters and Slaves w/Address Masking,

and IPMI Support

• Two UART modules:

- LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect (ABD), Break character support)

- RS-232 and RS-485 support

®

-IrDA

mode (hardware encoder/decoder

functions)

• Five External Interrupt Pins

• Parallel Master Port/Enhanced Parallel Slave Port
(PMP/EPSP), 8-Bit Data with External
Programmable Control (polarity and protocol)

• Enhanced CRC module

• Reference Clock Output with Programmable
Divider

• Two Configurable Logic Cell (CLC) Blocks:

- Two inputs and one output, all mappable to

peripherals or I/O pins

- AND/OR/XOR logic and D/JK flip-flop

functions

• Peripheral Pin Select (PPS) with Independent I/O
Mapping of Many Peripherals

TABLE 1: PIC24FJ256GA705 FAMILY DEVICES

Memory

Pins

Device

PIC24FJ64GA705 64K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ128GA705 128K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ256GA705 256K 16K 48 40 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ64GA704 64K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ128GA704 128K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ256GA704 256K 16K 44 36 6 14 3 Yes 1/3 3/3 3 2 3 2 13 10/8 2 Yes Yes

PIC24FJ64GA702 64K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes

PIC24FJ128GA702 128K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes

PIC24FJ256GA702 256K 16K 28 22 6 10 3 Yes 1/3 3/3 3 2 3 2 12 No 2 Yes Yes

Program

(bytes)

SRAM

(bytes)

GPIO

DMA Channels

10/12-Bit A/D Channels

CRC

Comparators

MCCP 6-Output/2-Output

Peripherals

IC/OC/PWM

16-Bit Timers

®

C

2

I

CTMU Channels

LIN-USART/IrDA

Variab le Width SPI

CLC

RTCC

EPMP (Address/Data Line)

JTAG

DS30010118E-page 2  2016-2020 Microchip Technology Inc.

Pin Diagrams (PIC24FJ256GA702 Devices)

Legend: See Table 2 for a complete description of pin functions.

Note 1: Gray shading indicates 5.5V tolerant input pins.

2: The large center pad on the bottom of the package may be left floating or connected to V

SS.

28-Pin QFN, UQFN

(1,2)

MCLR

AVDD/VDD

AVSS/VSS

VSS

VDD

VSS

VCAP

RB12

RB0

RB1

RB2

RB3

RA2

RA3

RB4

RA4

RB5

RB6

RB7

RB8

RB9

RB10

RB11

RB13

RB14

RB15

RA0

RA1

10 11

2

3

6

1

18

19

12 13 14

15

8

7

16

17

232425262728

9

PIC24FJ256GA702

5

4

20

21

22

PIC24FJ256GA705 FAMILY

TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA702 QFN, UQFN)

Pin Function Pin Function

1 PGD1/AN2/CTCMP/C2INB/RP0/RB0 15 TDO/C1INC/C2INC/C3INC/TMPRN

2 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 16 Vss

3 AN4/C1INB/RP2/SDA2/CTED13/RB2 17 V

4 AN5/C1INA/RP3/SCL2/CTED8/RB3 18 PGD2/TDI/RP10/OCM1C/CTED11/RB10

5 Vss 19 PGC2/TMS/REFI1/RP11/CTED9/RB11

6 OSCI/CLKI/C1IND/RA2 20 AN8/LVDIN/RP12/RB12

7 OSCO/CLKO/C2IND/RA3 21 AN7/C1INC/RP13/OCM1D/CTPLS/RB13

8SOSCI/RP4/RB4 22 CV

9 SOSCO/PWRLCLK/RA4 23 AN9/C3INA/RP15/CTED6/RB15

10 V

11 PGD3 /RP5/ASDA1/OCM1E/RB5 25 AVDD/VDD

12 PGC3/RP6/ASCL1/OCM1F/RB6 26 MCLR

13 RP7/OCM1A/CTED3/INT0/RB7 27 VREF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0

14 TCK/RP8/SCL1/OCM1B/CTED10/RB8 28 V

Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.

CAP

REF/AN6/C3INB/RP14/CTED5/RB14

REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1

DD 24 AVSS/VSS

/RP9/SDA1/T1CK/CTED4/RB9

 2016-2020 Microchip Technology Inc. DS30010118E-page 3

PIC24FJ256GA705 FAMILY

Legend: See Table 3 for a complete description of pin functions.

Note: Gray shading indicates 5.5V tolerant input pins.

28-Pin SOIC, SSOP, SPDIP

MCLR

VSS

VDD

RA0
RA1

AVDD/VDD
AVSS/VSS

RB0

RB6

RA4

RB4

V

SS

RA3

RA2

V

CAP

RB7

RB9
RB8

RB3

RB2

RB1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB15
RB14
RB13
RB12

RB10

RB11

RB5

PIC24FJ256GA702

Pin Diagrams (PIC24FJ256GA702 Devices)

TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA702 SOIC, SSOP, SPDIP)

Pin Function Pin Function

1MCLR

2V

REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 16 RP7/OCM1A/CTED3/INT0/RB7

3V

REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 17 TCK/RP8/SCL1/OCM1B/CTED10/RB8

4 PGD1/AN2/CTCMP/C2INB/RP0/RB0 18 TDO/C1INC/C2INC/C3INC/TMPRN

5 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 19 V

6 AN4/C1INB/RP2/SDA2/CTED13/RB2 20 VCAP

7 AN5/C1INA/RP3/SCL2/CTED8/RB3 21 PGD2/TDI/RP10/OCM1C/CTED11/RB10

8V

SS 22 PGC2/TMS/REFI1/RP11/CTED9/RB11

9 OSCI/CLKI/C1IND/RA2 23 AN8/LVDIN/RP12/RB12

10 OSCO/CLKO/C2IND/RA3 24 AN7/C1INC/RP13/OCM1D/CTPLS/RB13

11 S OSCI /RP4/RB4 25 CV

12 SOSCO/PWRLCLK/RA4 26 AN9/C3INA/RP15/CTED6/RB15

13 V

DD 27 AVSS/VSS

14 PGD3/RP5/ASDA1/OCM1E/RB5 28 AVDD/VDD

Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.

15 PGC3/RP6/ASCL1/OCM1F/RB6

SS

REF/AN6/C3INB/RP14/CTED5/RB14

/RP9/SDA1/T1CK/CTED4/RB9

DS30010118E-page 4  2016-2020 Microchip Technology Inc.

Legend: See Table 4 for a complete description of pin functions.

Note: Gray shading indicates 5.5V tolerant input pins.

44-Pin TQFP

RB8

RB7

RB6

RB5

V

DD

RA9

RA4

VSS

RC5

RC4

RC3

RB12

RB11

RB10

V

CAP

VSS

RC9

RC8

RC7

RC6

RB9

RB13

RB2

RB3

RC0

RC1

RC2

RB4

V

DD

VSS

RA2

RA3

RA8

RB1

RB0

RA1

RA0

MCLR

RA10

AV

DD

AVSS

RB15

RB14

RA7

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

37

PIC24FJ256GA704

PIC24FJ256GA705 FAMILY

Pin Diagrams (PIC24FJ256GA704 Devices)

 2016-2020 Microchip Technology Inc. DS30010118E-page 5

PIC24FJ256GA705 FAMILY

TABLE 4: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA704 TQFP)

Pin Function Pin Function

1 C1INC/C2INC/C3INC/TMPRN

2 RP22/PMA1/PMALH/RC6 24 AN5/C1INA/RP3/SCL2/CTED8/RB3

3 RP23/PMA0/PMALL/RC7 25 AN10/RP16/PMBE1/RC0

4 RP24/PMA5/RC8 26 AN11/RP17/PMA15/PMCS2/RC1

5 RP25/CTED7/PMA6/RC9 27 AN12/RP18/PMACK1/RC2

6Vss 28 V

7VCAP 29 VSS

8PGD2/RP10/OCM1C/CTED11/PMD2/RB10 30 OSCI/CLKI/C1IND/RA2

9PGC2/REFI1/RP11/CTED9/PMD1/RB11 31 OSCO/CLKO/C2IND/RA3

10 AN8/LVDIN/RP12/PMD0/RB12 32 TDO/PMA8/RA8

11 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR

12 TMS/RP28/PMA2/PMALU/RA10 34 SOSCO/PWRLCLK/RA4

13 TCK/PMA7/RA7 35 TDI/PMA9/RA9

14 CV

REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 36 AN13/RP19/PMBE0/RC3

15 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 37 RP20/PMA4/RC4

16 AV

SS 38 RP21/PMA3/RC5

17 AV

DD 39 VSS

18 MCLR 40 VDD

19 VREF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 41 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5

20 V

REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 42 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6

21 PGD1/AN2/CTCMP/C2INB/RP0/RB0 43 RP7/OCM1A/CTED3/PMD5/INT0/RB7

22 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 44 RP8/SCL1/OCM1B/CTED10/PMD4/RB8

Legend: RPn represents remappable pins for Peripheral Pin Select (PPS) functions.

/RP9/SDA1/T1CK/CTED4/PMD3/RB9 23 AN4/C1INB/RP2/SDA2/CTED13/RB2

DD

/RB13 33 SOSCI/RP4/RB4

DS30010118E-page 6  2016-2020 Microchip Technology Inc.

Legend: See Table 5 for a complete description of pin functions.

Note: Gray shading indicates 5.5V tolerant input pins.

48-Pin UQFN

48 47 46 45 43 42 41 40 39 38

13 14 15 16 17 18 19 21 22 23

3

33

31

30

29

28

27

26

25

4

5

7

9

10

11

12

1

2

35

34

6

24

36

37

VDD

VSS

RA8

RB4

VDD

VSS

RB13

RB12

RB11

RB10

V

CAP

VSS

RC9

RC8

RC7

RC6

RA10

RA7

RB14

AV

SS

AVDD

MCLR

PIC24FJ256GA705

8

RA11

20

RA12

32 RA13

44

RA14

RB15

RC1

RA9

RC3

RB8

RB5

RA4

RB7

RB6

RC5

RC4

RB9

RC2

RA3

RA2

RC0

RB3

RB2

RA1

RB1

RA0

RB0

PIC24FJ256GA705 FAMILY

Pin Diagrams (PIC24FJ256GA705 Devices)

 2016-2020 Microchip Technology Inc. DS30010118E-page 7

PIC24FJ256GA705 FAMILY

TABLE 5: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA705 UQFN)

Pin Function Pin Function

1 C1INC/C2INC/C3INC/TMPRN

2 RP22/PMA1/PMALH/RC6 26 AN5/C1INA/RP3/SCL2/CTED8/RB3

3 RP23/PMA0/PMALL/RC7 27 AN10/RP16/PMBE1/RC0

4 RP24/PMA5/RC8 28 AN11/RP17/PMA15/PMCS2/RC1

5 RP25/CTED7/PMA6/RC9 29 AN12/RP18/PMACK1/RC2

6V

SS 30 VDD

7VCAP 31 VSS

8 RPI29/RA11 32 RPI31/RA13

9PGD2/RP10/OCM1C/CTED11/PMD2/RB10 33 OSCI/CLKI/C1IND/RA2

10 PGC2/REFI1/RP11/CTED9/PMD1/RB11 34 OSCO/CLKO/C2IND/RA3

11 AN 8/LV DIN/ RP12/PMD0/RB12 35 TDO/PMA8/RA8

12 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR

13 TMS/RP28/PMA2/PMALU/RA10 37 SOSCO/PWRLCLK/RA4

14 TCK/PMA7/RA7 38 TDI/PMA9/RA9

15 CV

REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 39 AN13/RP19/PMBE0/RC3

16 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 40 RP20/PMA4/RC4

17 AV

SS 41 RP21/PMA3/RC5

18 AV

DD 42 VSS

19 MCLR 43 VDD

20 RPI30/RA12 44 RPI32/RA14

21 V

REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 45 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5

22 V

REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 46 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6

23 PGD1/AN2/CTCMP/C2INB/RP0/RB0 47 RP7/OCM1A/CTED3/PMD5/INT0/RB7

24 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 48 RP8/SCL1/OCM1B/CTED10/PMD4/RB8

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.

/RP9/SDA1/T1CK/CTED4/PMD3/RB9 25 AN4/C1INB/RP2/SDA2/CTED13/RB2

/RB13 36 SOSCI/RP4/RB4

DS30010118E-page 8  2016-2020 Microchip Technology Inc.

Legend: See Table 6 for a complete description of pin functions.

Note: Gray shading indicates 5.5V tolerant input pins.

48-Pin TQFP

RB8

RB7

RB6

RB5

RA14

RC3

RA9

VDDVSS

RC5

RC4

RB12

RB11

RB10

RA11

VCAP

VSS

RC9

RC8

RC7

RC6

RB13

RB3

RC0

RC1

RC2

V

DD

RB4

V

SS

RA13

RA2

RA3

RA8

RB1

RB0

RA1

RA0

RA12

RA7

MCLR

AVDD

AVSS

RB15

RB14

11

12

3

4

5

6

7

2

2021222324

141516

17

42

9

8

4847464544

4318

19

32

33

34

35

36

26

27

28

29

30

31

403839

10

41

RA4

37

RB2

25

RA10

13

RB9

1

PIC24FJ256GA705

PIC24FJ256GA705 FAMILY

Pin Diagrams (PIC24FJ256GA705 Devices)

 2016-2020 Microchip Technology Inc. DS30010118E-page 9

PIC24FJ256GA705 FAMILY

TABLE 6: COMPLETE PIN FUNCTION DESCRIPTIONS (PIC24FJ256GA705 TQFP)

Pin Function Pin Function

1 C1INC/C2INC/C3INC/TMPRN

2 RP22/PMA1/PMALH/RC6 26 AN5/C1INA/RP3/SCL2/CTED8/RB3

3 RP23/PMA0/PMALL/RC7 27 AN10/RP16/PMBE1/RC0

4 RP24/PMA5/RC8 28 AN11/RP17/PMA15/PMCS2/RC1

5 RP25/CTED7/PMA6/RC9 29 AN12/RP18/PMACK1/RC2

6V

SS 30 VDD

7VCAP 31 VSS

8 RPI29/RA11 32 RPI31/RA13

9PGD2/RP10/OCM1C/CTED11/PMD2/RB10 33 OSCI/CLKI/C1IND/RA2

10 PGC2/REFI1/RP11/CTED9/PMD1/RB11 34 OSCO/CLKO/C2IND/RA3

11 AN 8/LV DIN/ RP12/PMD0//RB12 35 TDO/PMA8/RA8

12 AN7/C1INC/RP13/OCM1D/CTPLS/PMRD/PMWR

13 TMS/RP28/PMA2/PMALU/RA10 37 SOSCO/PWRLCLK/RA4

14 TCK/PMA7/RA7 38 TDI/PMA9/RA9

15 CV

REF/AN6/C3INB/RP14/CTED5/PMWR/PMENB/RB14 39 AN13/RP19/PMBE0/RC3

16 AN9/C3INA/RP15/CTED6/PMA14/PMCS/PMCS1/RB15 40 RP20/PMA4/RC4

17 AV

SS 41 RP21/PMA3/RC5

18 AV

DD 42 VSS

19 MCLR 43 VDD

20 RPI30/RA12 44 RPI32/RA14

21 V

REF+/CVREF+/AN0/C3INC/RP26/CTED1/RA0 45 PGD3/RP5/ASDA1/OCM1E/PMD7/RB5

22 V

REF-/CVREF-/AN1/C3IND/RP27/CTED2/RA1 46 PGC3/RP6/ASCL1/OCM1F/PMD6/RB6

23 PGD1/AN2/CTCMP/C2INB/RP0/RB0 47 RP7/OCM1A/CTED3/PMD5/INT0/RB7

24 PGC1/AN1-/AN3/C2INA/RP1/CTED12/RB1 48 RP8/SCL1/OCM1B/CTED10/PMD4/RB8

Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.

/RP9/SDA1/T1CK/CTED4/PMD3/RB9 25 AN4/C1INB/RP2/SDA2/CTED13/RB2

/RB13 36 SOSCI/RP4/RB4

DS30010118E-page 10  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 15

2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 29

3.0 CPU ........................................................................................................................................................................................... 35

4.0 Memory Organization ................................................................................................................................................................. 41

5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 63

6.0 Flash Program Memory.............................................................................................................................................................. 71

7.0 Resets ........................................................................................................................................................................................ 79

8.0 Interrupt Controller ..................................................................................................................................................................... 85

9.0 Oscillator Configuration.............................................................................................................................................................. 97

10.0 Power-Saving Features............................................................................................................................................................ 113

11.0 I/O Ports ................................................................................................................................................................................... 125

12.0 Timer1 ...................................................................................................................................................................................... 159

13.0 Timer2/3 .................................................................................................................................................................................. 161

14.0 Input Capture with Dedicated Timers ....................................................................................................................................... 167

15.0 Output Compare with Dedicated Timers .................................................................................................................................. 173

16.0 Capture/Compare/PWM/Timer Modules (MCCP).................................................................................................................... 183

17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 199

18.0 Inter-Integrated Circuit (I

19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 227

20.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 237

21.0 Real-Time Clock and Calendar (RTCC) with Timestamp......................................................................................................... 249

22.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 269

23.0 Configurable Logic Cell (CLC) Generator ................................................................................................................................ 275

24.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 285

25.0 Triple Comparator Module........................................................................................................................................................ 307

26.0 Comparator Voltage Reference................................................................................................................................................ 313

27.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 315

28.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 325

29.0 Special Features ...................................................................................................................................................................... 327

30.0 Development Support............................................................................................................................................................... 343

31.0 Instruction Set Summary.......................................................................................................................................................... 345

32.0 Electrical Characteristics.......................................................................................................................................................... 353

33.0 Packaging Information.............................................................................................................................................................. 387

Appendix A: Revision History............................................................................................................................................................. 411

Index ................................................................................................................................................................................................. 413

The Microchip Website ...................................................................................................................................................................... 419

Customer Change Notification Service .............................................................................................................................................. 419

Customer Support .............................................................................................................................................................................. 419

Product Identification System ............................................................................................................................................................ 421

2

C) ..................................................................................................................................................... 219

 2016-2020 Microchip Technology Inc. DS30010118E-page 11

PIC24FJ256GA705 FAMILY

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS30010118E-page 12  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

Referenced Sources

This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.

Note 1: To access the documents listed below,

browse to the documentation section of the

PIC24FJ256GA705 product page of the

Microchip website (www.microchip.com) or
select a family reference manual section
from the following list.

In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.

• “CPU with Extended Data Space (EDS)” (DS39732)

• “Direct Memory Access Controller (DMA)” (DS30009742)

• “PIC24F Flash Program Memory” (DS30009715)

• “Data Memory with Extended Data Space (EDS)” (DS39733)

• “Reset” (DS39712)

• “Interrupts” (DS70000600)

• “Oscillator” (DS39700)

• “Power-Saving Features with Deep Sleep” (DS39727)

• “I/O Ports with Peripheral Pin Select (PPS)” (DS30009711)

• “Timers” (DS39704)

• ”Input Capture with Dedicated Timer” (DS70000352)

• “Output Compare with Dedicated Timer” (DS70005159)

• “Capture/Compare/PWM/Timer (MCCP and SCCP)” (DS30003035)

• “Serial Peripheral Interface (SPI) with Audio Codec Support” (DS70005136)

• “Inter-Integrated Circuit (I

• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)

• “Enhanced Parallel Master Port (EPMP)” (DS39730)

• “RTCC with Timestamp” (DS70005193)

• “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS30009729)

• “Configurable Logic Cell (CLC)” (DS70005298)

• “12-Bit A/D Converter with Threshold Detect” (DS39739)

• “Scalable Comparator Module” (DS39734)

• “Dual Comparator Module” (DS39710)

• “Charge Time Measurement Unit (CTMU) and CTMU Operation with Threshold Detect” (DS30009743)

• “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725)

• “Watchdog Timer (WDT)” (DS39697)

• “CodeGuard™ Intermediate Security” (DS70005182)

• “High-Level Device Integration” (DS39719)

• “Programming and Diagnostics” (DS39716)

• “Comparator Voltage Reference Module” (DS39709)

2

C)” (DS70000195)

 2016-2020 Microchip Technology Inc. DS30010118E-page 13

PIC24FJ256GA705 FAMILY

NOTES:

DS30010118E-page 14  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for
the following devices:

• PIC24FJ64GA705 • PIC24FJ256GA704

• PIC24FJ128GA705 • PIC24FJ64GA702

• PIC24FJ256GA705 • PIC24FJ128GA702

• PIC24FJ64GA704 • PIC24FJ256GA702

• PIC24FJ128GA704

The PIC24FJ256GA705 family introduces large Flash
and SRAM memory in smaller package sizes. This is a
16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
This family also offers a new migration option for those
high-performance applications which may be outgrow­ing their 8-bit platforms, but do not require the numerical
processing power of a Digital Signal Processor (DSP).

Table 1-3 lists the functions of the various pins shown

in the pinout diagrams.

1.1 Core Features

1.1.1 16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements,
such as:

• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces

• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)

• A 16-element Working register array with built-in
software stack support

• A 17 x 17 hardware multiplier with support for
integer math

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’

• Operational performance up to 16 MIPS

1.1.2 POWER-SAVING TECHNOLOGY

The PIC24FJ256GA705 family of devices includes
Retention Sleep, a low-power mode with essential
circuits being powered from a separate low-voltage
regulator.

This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.

Aside from this new feature, PIC24FJ256GA705 family
devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:

• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time

• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock

• Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and Sleep modes

1.1.3 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC24FJ256GA705 family offer
six different oscillator options, allowing users a range of
choices in developing application hardware. These
include:

• Two Crystal modes

• External Clock (EC) mode

• A Phase-Locked Loop (PLL) frequency multiplier,
which allows processor speeds up to 32 MHz

• An internal Fast RC Oscillator (FRC), a nominal
8 MHz output with multiple frequency divider
options

• A separate internal Low-Power RC Oscillator
(LPRC), 31 kHz nominal for low-power,
timing-insensitive applications.

The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter­nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

1.1.4 EASY MIGRATION

Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device.

The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.

 2016-2020 Microchip Technology Inc. DS30010118E-page 15

PIC24FJ256GA705 FAMILY

1.2 DMA Controller

PIC24FJ256GA705 family devices have a Direct Memory
Access (DMA) Controller. This module acts in concert
with the CPU, allowing data to move between data
memory and peripherals without the intervention of the
CPU, increasing data throughput and decreasing execu­tion time overhead. Six independently programmable
channels make it possible to service multiple peripherals
at virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.

1.3 Other Special Features

• Peripheral Pin Select: The Peripheral Pin Select

(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.

• Configurable Logic Cell: The Configurable

Logic Cell (CLC) module allows the user to
specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins.

• Timing Modules: The PIC24FJ256GA705 family

provides three independent, general purpose,
16-bit timers (two of which can be combined
into a 32-bit timer). The devices also include
four multiple output advanced
Capture/Compare/PWM/Timer peripherals, and
three independent legacy Input Capture and
three independent legacy Output Compare modules.

• Communications: The PIC24FJ256GA705 family

incorporates a range of serial
communication peripherals to handle a range of
application requirements. There are two indepen-

2

C modules that support both Master and

dent I
Slave modes of operation. Devices also have,
through the PPS feature, two independent UARTs
with built-in IrDA
three SPI modules.

• Analog Features: All members of the

PIC24FJ256GA705 family include a 12-bit A/D
Converter (A/D) module and a triple comparator
module. The A/D module incorporates a range of
new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog
comparators that are configurable for a wide
range of operations.

• CTMU Interface: In addition to their other analog

features, members of the PIC24FJ256GA705
family include the CTMU interface module. This
provides a convenient method for precision time
measurement and pulse generation, and can serve
as an interface for capacitive sensors.

®

encoders/decoders and

• Enhanced Parallel Master/Parallel Slave Port:

This module allows rapid and transparent access to
the microcontroller data bus, and enables the CPU
to directly address external data memory. The
parallel port can function in Master or Slave mode,
accommodating data widths of four or eight bits and
address widths of up to ten bits in Master modes.

• Real-Time Clock and Calendar (RTCC): This

module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.

1.4 Details on Individual Family Members

Devices in the PIC24FJ256GA705 family are available
in 28-pin, 44-pin and 48-pin packages. The general
block diagram for all devices is shown in Figure 1-1.

The devices are differentiated from each other in
five ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA70X devices, 128 Kbytes for
PIC24FJ128GA70X devices, 256 Kbytes for
PIC24FJ256GA70X devices).

2. Available I/O pins and ports (22 pins on two

ports for 28-pin devices, and 36 and 40 pins on
three ports for 44-pin/48-pin devices).

3. Enhanced Parallel Master Port (EPMP) is only

available on 44-pin/48-pin devices.

4. Analog input channels (10 channels for 28-pin

devices and 14 channels for 44-pin/48-pin
devices).

5. CTMU input channels (12 channels for 28-pin

devices and 13 channels for 44-pin/48-pin
devices)

All other features for devices in this family are identical.
These are summarized in Ta bl e 1 - 1 and Ta bl e 1- 2.

A list of the pin features available on the
PIC24FJ256GA705 family devices, sorted by func­tion, is shown in Tab le 1 -3 . Note that this table shows
the pin location of individual peripheral features and not
how they are multiplexed on the same pin. This
information is provided in the pinout diagrams in the
beginning of this data sheet. Multiplexed features are
sorted by the priority given to a feature, with the highest
priority peripheral being listed first.

DS30010118E-page 16  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJXXXGA702: 28-PIN DEVICES

Features PIC24FJ64GA702 PIC24FJ128GA702 PIC24FJ256GA702

Operating Frequency DC – 32 MHz

Program Memory (bytes) 64K 128K 256K

Program Memory
(instruction words, 24 bits)

Data Memory (bytes) 16K

Interrupt Sources
(soft vectors/NMI traps)

I/O Ports Ports A, B

Total I/O Pins 22

Remappable Pins 18 (18 I/Os, 0 inputs only)

DMA 1 6-channel

16-Bit Timers 3

Real-Time Clock and Calendar
(RTCC)

Cyclic Redundancy Check (CRC) Yes

Input Capture Channels 3

Output Compare/PWM Channels 3

Input Change Notification Interrupt 21 (remappable pins)

Serial Communications:

UART 2

SPI (three-wire/four-wire) 3

I2C 2

Configurable Logic Cell (CLC) 2

Parallel Communications
(EPMP/PSP)

Capture/Compare/PWM/Timer
Modules

JTAG Boundary Scan Yes

10/12-Bit Analog-to-Digital Converter
(A/D) Module (input channels)

Analog Comparators 3

CTMU Interface Yes

Universal Serial Bus Controller No

Resets (and Delays) Core POR, V

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 28-Pin QFN, UQFN, SOIC, SSOP and SPDIP

Note 1: Some peripherals are accessible through remappable pins.

2: 28-Pin SPDIP is available only in the highest Flash variant.

22,528 45,056 88,064

124

(1)

Ye s

(1)

(1)

(1)

(1)

(1)

No

4 Multiple CCPs

1 (6-output), 3 (2-output)

10

DD POR, BOR, RESET Instruction,

MCLR

, WDT, Illegal Opcode, REPEAT Instruction,

Hardware Traps, Configuration Word Mismatch

(OST, PLL Lock)

(2)

 2016-2020 Microchip Technology Inc. DS30010118E-page 17

PIC24FJ256GA705 FAMILY

TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJXXXGA70X: 44-PIN AND 48-PIN DEVICES

Features PIC24FJ64GA70X PIC24FJ128GA70X PIC24FJ256GA70X

Operating Frequency DC – 32 MHz

Program Memory (bytes) 64K 128K 256K

Program Memory
(instruction words, 24 bits)

Data Memory (bytes) 16K

Interrupt Sources
(soft vectors/NMI traps)

I/O Ports Ports A, B, C

Total I/O Pins:

44-pin 35 35 35

48-pin 39 39 39

Remappable Pins:

44-pin 29 (29 I/Os, 0 inputs only)

48-pin 33 (29 I/Os, 4 inputs only)

DMA (6-channel) 1

16-Bit Timers 3

Real-Time Clock and Calendar
(RTCC)

Cyclic Redundancy Check (CRC) Yes

Input Capture Channels 3

Output Compare/PWM Channels 3

Input Change Notification Interrupt 25 (remappable pins)

Serial Communications:

UART 2

SPI (three-wire/four-wire) 3

I2C 2

Configurable Logic Cell (CLC) 2

Parallel Communications
(EPMP/PSP)

Capture/Compare/PWM/Timer
Modules (MCCP)

JTAG Boundary Scan Yes

10/12-Bit Analog-to-Digital Converter
(A/D) Module (input channels)

Analog Comparators 3

CTMU Interface Yes

Universal Serial Bus Controller No

Resets (and delays) Core POR, VDD POR, BOR, RESET Instruction,

Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations

Packages 44-Pin TQFP, 48-Pin TQFP and UQFN

Note 1: Some peripherals are accessible through remappable pins.

22,528 45,056 88,064

124

(1)

Yes

(1)

(1)

(1)

(1)

(1)

Yes

4 Modules

1 (6-output), 3 (2-output)

14

, WDT, Illegal Opcode, REPEAT Instruction,

MCLR

Hardware Traps, Configuration Word Mismatch

(OST, PLL Lock)

DS30010118E-page 18  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

Instruction

Decode and

Control

16

PCH

16

Program Counter

16-Bit ALU

23

24

Data Bus

Inst Register

16

Divide

Support

Inst Latch

16

EA MUX

16

16

8

Interrupt

Controller

EDS and

Stac k

Control

Logic

Repeat
Control

Logic

Data Latch

Data RAM

Address

Latch

Address Latch

Extended Data

Data Latch

16

Address Bus

Literal

23

Control Signals

16

16

16 x 16

W Reg Array

Multiplier

17x17

OSCI/CLKI

OSCO/CLKO

V

DD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

HLVD &

Precision

Reference

Band Gap

FRC/LPRC
Oscillators

Regulators

Voltage

VCAP

PORTA

(1)

PORTC

(1)

(12 I/Os)

(8 I/Os)

PORTB

(16 I/Os)

Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Ta b le 1- 3 for specific implementations by pin count.

2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: Some peripheral I/Os are only accessible through remappable pins.

Comparators

(3)

Timer2/3

(3)

Timer1

RTCC

IC

A/D

12-Bit

OC/PWM

SPI

I2C1-2

EPMP/PSP

1-3

(3)

IOCs

(1)

UART

REFO

1-3

(3)

1-2

(3)

1-3

(3)

CTMU

Space

Program Memory/

CLC1-2

(1)

DMA

Controller

Data

DMA

Data Bus

16

Ta ble Da t a

Access Control

MCCP1/2/3

PCL

BOR

(2)

Read AGU
Write AGU

FIGURE 1-1: PIC24FJ256GA705 FAMILY GENERAL BLOCK DIAGRAM

 2016-2020 Microchip Technology Inc. DS30010118E-page 19

PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS

Pin

Function

AN0 2 27 19 21 I ANA A/D Analog Inputs

AN1 3 28 20 22 I ANA

AN2 4 1 21 23 I ANA

AN3 5 2 22 24 I ANA

AN4 6 3 23 25 I ANA

AN5 7 4 24 26 I ANA

AN6 25 22 14 15 I ANA

AN7 24 21 11 12 I ANA

AN8 23 20 10 11 I ANA

AN9 26 23 15 16 I ANA

AN10 — — 25 27 I ANA

AN11 — — 26 28 I ANA

AN12 — — 27 29 I ANA

AN13 — — 36 39 I ANA

DD 28 25 17 18 P — Positive Supply for Analog modules

AV

SS 27 24 16 17 P — Ground Reference for Analog modules

AV

C1INA 7 4 24 26 I ANA Comparator 1 Input A

C1INB 6 3 23 25 I ANA Comparator 1 Input B

C1INC 18, 24 15, 21 1, 11 1, 12 I ANA Comparator 1 Input C

C1IND 9 6 30 33 I ANA Comparator 1 Input D

C2INA 5 2 22 24 I ANA Comparator 2 Input A

C2INB 4 1 21 23 I ANA Comparator 2 Input B

C2INC 18 15 1 1 I ANA Comparator 2 Input C

C2IND 10 7 31 34 I ANA Comparator 2 Input D

C3INA 26 23 15 16 I ANA Comparator 3 Input A

C3INB 25 22 14 15 I ANA Comparator 3 Input B

C3INC 2, 18 15, 27 1, 19 1, 21 I ANA Comparator 3 Input C

C3IND 3 28 20 22 I ANA Comparator 3 Input D

CLKI 9 6 30 33 — — Main Clock Input Connection

CLKO 10 7 31 34 O DIG System Clock Output

CTCMP 4 1 21 23 O ANA CTMU Comparator 2 Input (Pulse mode)

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,

SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

44-Pin

TQFP

2

48-Pin

UQFN/TQFP

C = I2C/SMBus input buffer

I/O

Input

Buffer

Description

DS30010118E-page 20  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

CTED1 2 27 19 21 I ST CTMU External Edge Inputs

CTED2 3 28 20 22 I ST

CTED3 16 13 43 47 I ST

CTED4 18 15 1 1 I ST

CTED5 25 22 14 15 I ST

CTED6 26 23 15 16 I ST

CTED7 — — 5 5 I ST

CTED8 7 4 24 26 I ST

CTED9 22 19 9 10 I ST

CTED10 17 14 44 48 I ST

CTED11 21 18 8 9 I ST

CTED12 5 2 22 24 I ST

CTED13 6 3 23 25 I ST

CTPLS 24 21 11 12 O DIG CTMU Pulse Output

REF 25 22 14 15 O ANA Comparator Voltage Reference Output

CV

REF+ 2 27 19 21 I ANA Comparator Voltage Reference (high) Input

CV

CV

REF- 3 28 20 22 I ANA Comparator Voltage Reference (low) Input

INT0 16 13 43 47 I ST External Interrupt Input 0

IOCA0 2 27 19 21 I ST PORTA Interrupt-on-Change

IOCA1 3 28 20 22 I ST

IOCA2 9 6 30 33 I ST

IOCA3 10 7 31 34 I ST

IOCA4 12 9 34 37 I ST

IOCA7 — — 13 14 I ST

IOCA8 — — 32 35 I ST

IOCA9 — — 35 38 I ST

IOCA10 — — 12 13 I ST

IOCA11 — — — 8 I ST

IOCA12 — — — 20 I ST

IOCA13 — — — 32 I ST

IOCA14 — — — 44 I ST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,
SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

44-Pin

TQFP

2

48-Pin

UQFN/TQFP

C = I2C/SMBus input buffer

I/O

Input

Buffer

Description

 2016-2020 Microchip Technology Inc. DS30010118E-page 21

PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

IOCB0 4 1 21 23 I ST PORTB Interrupt-on-Change

IOCB1 5 2 22 24 I ST

IOCB2 6 3 23 25 I ST

IOCB3 7 4 24 26 I ST

IOCB4 11 8 33 36 I ST

IOCB5 14 11 41 45 I ST

IOCB6 15 12 42 46 I ST

IOCB7 16 13 43 47 I ST

IOCB8 17 14 44 48 I ST

IOCB9 18 15 1 1 I ST

IOCB10 21 18 8 9 I ST

IOCB11 22 19 9 10 I ST

IOCB12 23 20 10 11 I ST

IOCB13 24 21 11 12 I ST

IOCB14 25 22 14 15 I ST

IOCB15 26 23 15 16 I ST

IOCC1 — — 26 28 I ST PORTC Interrupt-on-Change

IOCC2 — — 27 29 I ST

IOCC3 — — 36 39 I ST

IOCC4 — — 37 40 I ST

IOCC5 — — 38 41 I ST

IOCC6 — — 2 2 I ST

IOCC7 — — 3 3 I ST

IOCC8 — — 4 4 I ST

IOCC9 — — 5 5 I ST

LVDIN 23 20 10 11 I ANA High/Low-Voltage Detect

MCLR

OCM1A 16 13 43 47 O DIG MCCP1 Outputs

OCM1B 17 14 44 48 O DIG

OCM1C 21 18 8 9 O DIG

OCM1D 24 21 11 12 O DIG

OCM1E 14 11 41 45 O DIG

OCM1F 15 12 42 46 O DIG

OSCI 9 6 30 33 I ANA/ST Main Oscillator Input Connection

OSCO 10 7 31 34 O ANA Main Oscillator Output Connection

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,

SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

1 26 18 19 I ST Master Clear (device Reset) Input. This line

44-Pin

TQFP

48-Pin

UQFN/TQFP

2

C = I2C/SMBus input buffer

I/O

Input

Buffer

Description

is brought low to cause a Reset.

DS30010118E-page 22  2016-2020 Microchip Technology Inc.

PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

PGC1 5 2 22 24 I ST ICSP™ Programming Clock

PGC2 22 19 9 10 I ST

PGC3 15 12 42 46 I ST

PGD1 4 1 21 23 I/O DIG/ST ICSP Programming Data

PGD2 21 18 8 9 I/O DIG/ST

PGD3 14 11 41 45 I/O DIG/ST

PMA0 — — 3 3 I/O DIG/ST/

PMA1 — — 2 2 I/O DIG/ST/

PMA2 — — 12 13 I/O DIG/ST/

PMA3 — — 38 41 I/O DIG/ST/

PMA4 — — 37 40 I/O DIG/ST/

PMA5 — — 4 4 I/O DIG/ST/

PMA6 — — 5 5 I/O DIG/ST/

PMA7 — — 13 14 I/O DIG/ST/

PMA8 — — 32 35 I/O DIG/ST/

PMA9 — — 35 38 I/O DIG/ST/

PMA14/PMCS/
PMCS1

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,
SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

— — 15 16 I/O DIG/ST/

44-Pin

TQFP

48-Pin

UQFN/TQFP

2

C = I2C/SMBus input buffer

I/O

Input

Buffer

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

Description

Parallel Master Port Address[0]/
Address Latch Low

Parallel Master Port Address[1]/
Address Latch High

Parallel Master Port Address[2]

Parallel Master Port Address[3]

Parallel Master Port Address[4]

Parallel Master Port Address[5]

Parallel Master Port Address[6]

Parallel Master Port Address[7]

Parallel Master Port Address[8]

Parallel Master Port Address[9]

Parallel Master Port Address[14]/
Slave Chip Select/Chip Select 1 Strobe

 2016-2020 Microchip Technology Inc. DS30010118E-page 23

PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

PMD0 — — 10 11 I/O DIG/ST/

PMD1 — — 9 10 I/O DIG/ST/

PMD2 — — 8 9 I/O DIG/ST/

PMD3 — — 1 1 I/O DIG/ST/

PMD4 — — 44 48 I/O DIG/ST/

PMD5 — — 43 47 I/O DIG/ST/

PMD6 — — 42 46 I/O DIG/ST/

PMD7 — — 41 45 I/O DIG/ST/

PMRD/PMWR

PMWR/PMENB — — 14 15 I/O DIG/ST/

PWRGT — — — — O DIG Real-Time Clock Power Control Output

PWRLCLK 12 9 34 37 I ST Real-Time Clock 50/60 Hz Clock Input

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,

SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

——1112I/ODIG/ST/

44-Pin

TQFP

48-Pin

UQFN/TQFP

2

C = I2C/SMBus input buffer

I/O

Input

Buffer

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

Parallel Master Port Data (Demultiplexed
Master mode) or Address/Data
(Multiplexed Master modes)

Parallel Master Port Read Strobe/
Write Strobe

Parallel Master Port Write Strobe/
Enable Strobe

Description

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PIC24FJ256GA705 FAMILY

TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

RA0 2 27 19 21 I/O DIG/ST PORTA Digital I/Os

RA1 3 28 20 22 I/O DIG/ST

RA2 9 6 30 33 I/O DIG/ST

RA3 10 7 31 34 I/O DIG/ST

RA4 12 9 34 37 I/O DIG/ST

RA7 — — 13 14 I/O DIG/ST

RA8 — — 32 35 I/O DIG/ST

RA9 — — 35 38 I/O DIG/ST

RA10 — — 12 13 I/O DIG/ST

RA11 — — — 8 I/O DIG/ST

RA12 — — — 20 I/O DIG/ST

RA13 — — — 32 I/O DIG/ST

RA14 — — — 44 I/O DIG/ST

RB0 4 1 21 23 I/O DIG/ST PORTB Digital I/Os

RB1 5 2 22 24 I/O DIG/ST

RB2 6 3 23 25 I/O DIG/ST

RB3 7 4 24 26 I/O DIG/ST

RB4 11 8 33 36 I/O DIG/ST

RB5 14 11 41 45 I/O DIG/ST

RB6 15 12 42 46 I/O DIG/ST

RB7 16 13 43 47 I/O DIG/ST

RB8 17 14 44 48 I/O DIG/ST

RB9 18 15 1 1 I/O DIG/ST

RB10 21 18 8 9 I/O DIG/ST

RB11 22 19 9 10 I/O DIG/ST

RB12 23 20 10 11 I/O DIG/ST

RB13 24 21 11 12 I/O DIG/ST

RB14 25 22 14 15 I/O DIG/ST

RB15 26 23 15 16 I/O DIG/ST

RC0 — — 25 27 I/O DIG/ST PORTC Digital I/Os

RC1 — — 26 28 I/O DIG/ST

RC2 — — 27 29 I/O DIG/ST

RC3 — — 36 39 I/O DIG/ST

RC4 — — 37 40 I/O DIG/ST

RC5 — — 38 41 I/O DIG/ST

RC6 — — 2 2 I/O DIG/ST

RC7 — — 3 3 I/O DIG/ST

RC8 — — 4 4 I/O DIG/ST

RC9 — — 5 5 I/O DIG/ST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,
SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

44-Pin

TQFP

2

48-Pin

UQFN/TQFP

C = I2C/SMBus input buffer

I/O

Input

Buffer

Description

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TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

RP0 4 1 21 23 I/O DIG/ST Remappable Peripherals

RP1 5 2 22 24 I/O DIG/ST

RP2 6 3 23 25 I/O DIG/ST

RP3 7 4 24 26 I/O DIG/ST

RP4 11 8 33 36 I/O DIG/ST

RP5 14 11 41 45 I/O DIG/ST

RP6 15 12 42 46 I/O DIG/ST

RP7 16 13 43 47 I/O DIG/ST

RP8 17 14 44 48 I/O DIG/ST

RP9 18 15 1 1 I/O DIG/ST

RP10 21 18 8 9 I/O DIG/ST

RP11 22 19 9 10 I/O DIG/ST

RP12 23 20 10 11 I/O DIG/ST

RP13 24 21 11 12 I/O DIG/ST

RP14 25 22 14 15 I/O DIG/ST

RP15 26 23 15 16 I/O DIG/ST

RP16 — — 25 27 I/O DIG/ST

RP17 — — 26 28 I/O DIG/ST

RP18 — — 27 29 I/O DIG/ST

RP19 — — 36 39 I/O DIG/ST

RP20 — — 37 40 I/O DIG/ST

RP21 — — 38 41 I/O DIG/ST

RP22 — — 2 2 I/O DIG/ST

RP23 — — 3 3 I/O DIG/ST

RP24 — — 4 4 I/O DIG/ST

RP25 — — 5 5 I/O DIG/ST

RP26 2 27 19 21 I/O DIG/ST

RP27 3 28 20 22 I/O DIG/ST

RP28 — — 12 13 I/O DIG/ST

RPI29 — — — 8 I DIG/ST Remappable Peripherals

RPI30 — — — 20 I DIG/ST

RPI31 — — — 32 I DIG/ST

RPI32 — — — 44 I DIG/ST

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

28-Pin SOIC,

SSOP, SPDIP

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

44-Pin

TQFP

2

48-Pin

UQFN/TQFP

C = I2C/SMBus input buffer

I/O

Input

Buffer

Description

(input or output)

(input only)

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TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin

Function

28-Pin SOIC,
SSOP, SPDIP

SCL1 17 14 44 48 I/O I2C I2C1 Synchronous Serial Clock Input/Output

SCL2 7 4 24 26 I/O I

SDA1 18 15 1 1 I/O I

SDA2 6 3 23 25 I/O I

SOSCI 11 8 33 36 I ANA/ST Secondary Oscillator/Timer1 Clock Input

SOSCO 12 9 34 37 O ANA Secondary Oscillator/Timer1 Clock Output

T1CK 18 15 1 1 I ST Timer1 Clock

TCK 17 14 13 14 I ST JTAG Test Clock/Programming Clock Input

TDI 21 18 35 38 I ST JTAG Test Data/Programming Data Input

TDO 18 15 32 35 O DIG JTAG Test Data Output

TMPRN

TMS 22 19 12 13 I ST JTAG Test Mode Select Input

CAP 20 17 7 7 P — External Filter Capacitor

V

DD 13, 28 10, 25 28, 40 30, 43 P — Positive Supply for Peripheral Digital Logic

V

REF+ 2 27 19 21 I ANA Comparator and A/D Reference Voltage

V

REF- 3 28 20 22 I ANA Comparator and A/D Reference Voltage

V

SS 8, 19, 27 5, 16, 24 6, 29, 39 6, 31, 42 P — Ground Reference for

V

Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer

ANA = Analog level input/output I
DIG = Digital input/output XCVR = Dedicated Transceiver

Pin Number/Grid Locator

28-Pin QFN,

UQFN

44-Pin

TQFP

48-Pin

UQFN/TQFP

I/O

Buffer

2

C I2C2 Synchronous Serial Clock Input/Output

2

C I2C1 Data Input/Output

2

C I2C2 Data Input/Output

Description

Input

18 15 1 1 I ST Tamper Detect Input

Connection (regulator enabled)

and I/O Pins

(high) Input

(low) Input

Peripheral Digital Logic and I/O Pins

2

C = I2C/SMBus input buffer

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NOTES:

DS30010118E-page 28  2016-2020 Microchip Technology Inc.

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PIC24FJXXX

VDD

VSS

VDD

VSS

VSS

VDD

AVDD

AVSS

VDD

VSS

C1

R1

VDD

MCLR

VCAP

R2

C7

C2

(2)

C3

(2)

C4

(2)

C5

(2)

C6

(2)

Key (all values are recommendations):

C1 through C6: 0.1 µF, 50V ceramic

C7: 10 µF, 16V or greater, ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pin

(V

CAP)” for an explanation of voltage

regulator pin connections.

2: The example shown is for a PIC24F device

with five V

DD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.

(1)

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC24FJ256GA705 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.

The following pins must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Power Supply Pins”)

•All AV

•MCLR

•V

These pins must also be connected if they are being
used in the end application:

• PGCx/PGDx pins used for In-Circuit Serial

• OSCI and OSCO pins when an external oscillator

Additionally, the following pins may be required:

•V

The minimum mandatory connections are shown in

Figure 2-1.

DD and AVSS pins, regardless of whether or

not the analog device features are used
(see Section 2.2 “Power Supply Pins”)

pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

CAP pin

(see Section 2.4 “Voltage Regulator Pin (V

Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)

source is used
(see Section 2.6 “External Oscillator Pins”)

REF+/VREF- pins used when external voltage

reference for analog modules is implemented

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of
the analog modules are being used.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

CAP)”)

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Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR

from the external capacitor, C, in the

event of a MCLR

pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR

pin

V

IH and VIL specifications are met.

C1

R2

R1

V

DD

MCLR

PIC24FXXX

JP

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of
power supply pins, such as V

SS, is required.

AV

Consider the following criteria when using decoupling
capacitors:

• Value and type of capacitor: A 0.1 µF (100 nF),

25V-50V capacitor is recommended. The
capacitor should be a low-ESR device with a
self-resonance frequency in the range of 200 MHz
and higher. Ceramic capacitors are
recommended.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic-type
capacitor in parallel to the above described
decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 µF to

0.001 µF. Place this second capacitor next to
each primary decoupling capacitor. In high-speed
circuit designs, consider implementing a decade
pair of capacitances as close to the power and
ground pins as possible (e.g., 0.1 µF in parallel
with 0.001 µF).

• Maximizing performance: On the board layout

from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.

DD, VSS, AVDD and

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device functions:
device Reset, and device programming and debug­ging. If programming and debugging are not required
in the end application, a direct connection to V
may be all that is required. The addition of other
components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in

Figure 2-1. Other circuit designs may be implemented

depending on the application’s requirements.

During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR
levels (V

IH and VIL) and fast signal transitions must

pin. Consequently, specific voltage

not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR

pin during programming and debug­ging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.

Any components associated with the MCLR
should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

DD

pin

2.2.2 BULK CAPACITORS

On boards with power traces running longer than six
inches in length, it is suggested to use a bulk
capacitance of 10 µF or greater located near the MCU.
The value of the capacitor should be determined based
on the trace resistance that connects the power supply
source to the device, and the maximum current drawn
by the device in the application. Typical values range
from 10 µF to 47 µF. The capacitor should be ceramic
and have a voltage rating of 25V or more to reduce DC
bias effects (see Section 2.4.1 “Considerations for

Ceramic Capacitors”).

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10

1

0.1

0.01

0.001

0.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR ()

Note: Typical data measurement at +25°C, 0V DC bias.

2.4 Voltage Regulator Pin (VCAP)

FIGURE 2-3: FREQUENCY vs. ESR

Note: This section applies only to PIC24FJ

devices with an on-chip voltage regulator.

Refer to Section 29.3 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.

A low-ESR (< 5Ω) capacitor is required on the V

CAP pin

to stabilize the voltage regulator output voltage. The

CAP pin must not be connected to VDD and must use a

V
capacitor of 10 µF connected to ground. The type can be
ceramic or tantalum. Suitable examples of capacitors
are shown in Table 2-1. Capacitors with equivalent
specifications can be used.

Designers may use Figure 2-3 to evaluate the ESR
equivalence of candidate devices.

The placement of this capacitor should be close to V

CAP.

It is recommended that the trace length not exceed

0.25 inch (6 mm). Refer to Section 32.0 “Electrical

Characteristics” for additional information.

.

TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS (0805 CASE SIZE)

Make Part #

Nominal

Capacitance

Base Tolerance Rated Voltage

PERFORMANCE FOR
SUGGESTED V

CAP

TDK C2012X5R1E106K085AC 10 µF ±10% 25V

TDK C2012X5R1C106K085AC 10 µF ±10% 16V

Kemet C0805C106M4PACTU 10 µF ±10% 16V

Murata GRM21BR61E106KA3L 10 µF ±10% 25V

Murata GRM21BR61C106KE15 10 µF ±10% 16V

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-80

-70

-60

-50

-40

-30

-20

-10

0

10

5 1011121314151617

DC Bias Voltage (VDC)

Capacitance Change (%)

01234 6789

6.3V Capacitor

10V Capacitor

16V Capacitor

2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS

In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.

Ceramic capacitors are suitable for use with the inter­nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.

Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance
specifications for these types of capacitors are often
specified as ±10% to ±20% (X5R and X7R) or -20%/
+80% (Y5V). However, the effective capacitance that
these capacitors provide in an application circuit will
also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.

The X5R and X7R capacitors typically exhibit satisfac­tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci­tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.

In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi­cant, but is often overlooked or is not always
documented.

A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.

FIGURE 2-4: DC BIAS VOLTAGE vs.

CAPACITANCE
CHARACTERISTICS

When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating so that the operating voltage is a
small percentage of the maximum rated capacitor volt­age. For example, choose a ceramic capacitor rated at
a minimum of 16V for the 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.

2.5 ICSP Pins

The PGCx and PGDx pins are used for In-Circuit Serial
Programming (ICSP) and debugging purposes. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom­mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the
PGCx and PGDx pins are not recommended as they
will interfere with the programmer/debugger communi­cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits, and pin Voltage Input High

IH) and Voltage Input Low (VIL) requirements.

(V

For device emulation, ensure that the “Communication
Channel Select” pins (i.e., PGCx/PGDx) programmed
into the device match the physical connections for the
ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip
development tools connection requirements, refer to

Section 30.0 “Development Support”.

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GND

`

`

`

OSCI

OSCO

SOSCO

SOSC I

Copper Pour

Primary Oscillator

Crystal

Secondary

Crystal

DEVICE PINS

Primary

Oscillator

C1

C2

Sec Oscillator: C1

Sec Oscillator: C2

(tied to ground)

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

C2

C1

DEVICE PINS

(tied to ground)

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual Sided) Layouts:

Oscillator

2.6 External Oscillator Pins

Many microcontrollers have options for at least two
oscillators: a high-frequency Primary Oscillator and
a low-frequency Secondary Oscillator (refer to

Section 9.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.

Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.

Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com­pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.

In planning the application’s routing and I/O assign­ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).

For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):

• AN943, “Practical PICmicro
and Design”

• AN949, “Making Your Oscillator Work”

• AN1798, “Crystal Selection for Low-Power

Secondary Oscillator”

®

Oscillator Analysis

FIGURE 2-5: SUGGESTED

PLACEMENT OF THE
OSCILLATOR CIRCUIT

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2.7 Configuration of Analog and Digital Pins During ICSP Operations

If an ICSP compliant emulator is selected as a debugger,
it automatically initializes all of the A/D input pins (ANx)
as “digital” pins. This is done by clearing all bits in the
ANSx registers. Refer to Section 11.2 “Configuring

Analog Port Pins (ANSx)” for more specific information.

The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.

If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:

• Set the bits corresponding to the pin(s) to be

configured as analog. Do not change any other
bits, particularly those corresponding to the
PGCx/PGDx pair, at any time.

When a Microchip debugger/emulator is used as a
programmer, the user application firmware must
correctly configure the ANSx registers. Automatic
initialization of these registers is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.

2.8 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a Logic Low state. Alternatively, connect a
1kΩ to 10 kΩ resistor to V
the output to logic low.

SS on unused pins and drive

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3.0 CPU

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information on
the CPU, refer to “CPU with
Extended Data Space (EDS)”
(www.microchip.com/DS39732) in the

“dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet

supersedes the information in the FRM.

The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.

PIC24F devices have sixteen, 16-bit Working registers
in the programmer’s model. Each of the Working
registers can act as a Data, Address or Address Offset
register. The 16
a Software Stack Pointer (SSP) for interrupts and calls.

The lower 32 Kbytes of the Data Space (DS) can be
accessed linearly. The upper 32 Kbytes of the Data
Space are referred to as Extended Data Space (EDS),
to which the extended data RAM, EPMP memory
space or program memory can be mapped.

The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibil­ity. All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.

th

Working register (W15) operates as

The core supports Inherent (no operand), Relative,
Literal, Memory Direct Addressing modes along with
three groups of addressing modes. All modes support
Register Direct and various Register Indirect modes.
Each group offers up to seven addressing modes.
Instructions are associated with predefined addressing
modes depending upon their functional requirements.

For most instructions, the core is capable of executing
a data (or program data) memory read, a Working reg­ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (for example, A + B = C) to
be executed in a single cycle.

A high-speed, 17-bit x 17-bit multiplier has been included
to significantly enhance the core arithmetic capability and
throughput. The multiplier supports Signed, Unsigned
and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer
multiplication. All multiply instructions execute in a single
cycle.

The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or 16-bit),
divided by 16-bit, integer signed and unsigned division.
All divide operations require 19 cycles to complete but
are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.

A block diagram of the CPU is shown in Figure 3-1.

3.1 Programmer’s Model

The programmer’s model for the PIC24F is shown in

Figure 3-2. All registers in the programmer’s model are

memory-mapped and can be manipulated directly by
instructions.

A description of each register is provided in Tab le 3 -1 .
All registers associated with the programmer’s model
are memory-mapped.

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Instruction

Decode and

Control

PCH

16

Program Counter

16-Bit ALU

23

23

24

23

Data Bus

Instruction Reg

16

Divide

Support

16

EA MUX

RAGU

WAGU

16

16

8

Interrupt

Controller

Stac k

Control

Logic

Loop

Control

Logic

Data Latch

Data RAM

Address

Latch

Control Signals

to Various Blocks

Program Memory/

Data Latch

Address Bus

16

Literal Data

16

16

Hardware

Multiplier

16

To Peripheral Modules

Address Latch

Up to 0x7FFF

Extended Data

Spac e

PCL

16 x 16

W Register Array

EDS and Table

Data Access

Control Block

ROM Latch

FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM

TABLE 3-1: CPU CORE REGISTERS

Register(s) Name Description

W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
RCOUNT REPEAT Loop Counter Register
CORCON CPU Control Register
DISICNT Disable Interrupt Count Register
DSRPAG Data Space Read Page Register
DSWPAG Data Space Write Page Register

DS30010118E-page 36  2016-2020 Microchip Technology Inc.

FIGURE 3-2: PROGRAMMER’S MODEL

NOVZ C

TBLPAG

22

0

7

0

015

Program Counter

Table Memory Page

ALU STATUS Register (SR)

Working/Address
Registers

W0 (WREG)

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

Frame Pointer

Stack Pointer

RA

0

RCOUNT

15

0

REPEAT Loop Counter

SPLIM

Stack Pointer Limit

SRL

0

0

15

0

CPU Control Register (CORCON)

SRH

W14

W15

DC

IPL

210

PC

Divider Working Registers

Multiplier Registers

15

0

Value Register

Address Register

Register

Data Space Read Page Register

Data Space Write Page Register

Disable Interrupt Count Register

13 0

DISICNT

90

DSRPAG

80

DSWPAG

IPL3

———

Registers or bits are shadowed for PUSH.S and POP.S instructions.

————————————

———————

Note 1: For Information regarding Shadow registers, refer to “CPU with Extended Data Space (EDS)”

(www.microchip.com/DS39732) in the “dsPIC33/PIC24 Family Reference Manual”.

PIC24FJ256GA705 FAMILY

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3.2 CPU Control Registers

REGISTER 3-1: SR: ALU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

R/W-0

IPL2

(1)

(2)

R/W-0

IPL1

(2)

(1)

R/W-0

IPL0

(2)

(1)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’

bit 8 DC: ALU Half Carry/Borrow bit

th

1 = A carry out from the 4

low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry out from the 4th or 8th low-order bit of the result has occurred

bit 7-5 IPL[2:0]: CPU Interrupt Priority Level Status bits

(1,2)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress

bit 3 N: ALU Negative bit

1 = Result was negative
0 = Result was not negative (zero or positive)

bit 2 OV: ALU Overflow bit

1 = Overflow occurred for signed (two’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred

bit 1 Z: ALU Zero bit

1 = An operation, which affects the Z bit, has set it at some time in the past
0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)

bit 0

C: ALU Carry/Borrow

bit

1 = A carry out from the Most Significant bit (MSb) of the result occurred
0 = No carry out from the Most Significant bit of the result occurred

Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1.

2: The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt

Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

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REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0

— — — —IPL3

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit

1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Program Space Visibility (PSV) in Data Space Enable

1 = Program space is visible in Data Space
0 = Program space is not visible in Data Space

bit 1-0 Unimplemented: Read as ‘0’

(1)

(1)

(2)

PSV

(2)

— —

Note 1: The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see

Register 3-1 for bit description.

2: If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of

reading from the PSV section of program memory. This bit is not individually addressable.

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3.3 Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi­tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow
for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.

The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.

3.3.1 MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

and Digit Borrow bits, respectively,

3.3.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.

3.3.3 MULTIBIT SHIFT SUPPORT

The PIC24F ALU supports both single bit and single­cycle, multibit arithmetic and logic shifts. Multibit shifts
are implemented using a shifter block, capable of
performing up to a 15-bit arithmetic right shift, or up to
a 15-bit left shift, in a single cycle. All multibit shift
instructions only support Register Direct Addressing for
both the operand source and result destination.

A full summary of instructions that use the shift
operation is provided in Table 3-2.

TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTIBIT SHIFT OPERATION

Instruction Description

ASR Arithmetic Shift Right Source register by one or more bits.

SL Shift Left Source register by one or more bits.

LSR Logical Shift Right Source register by one or more bits.

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4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not
intended to be a comprehensive refer­ence source. For more information, refer
to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.

As Harvard architecture devices, PIC24F micro­controllers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space during
code execution.

4.1 Program Memory Space

The program address memory space of the
PIC24FJ256GA705 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro­gram execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing

Program and Data Memory Spaces”.

User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG[7] to permit access to
the Configuration bits and customer OTP sections of
the configuration memory space.

The memory map for the PIC24FJ256GA705 family of
devices is shown in Figure 4-1.

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000000h

FA0 0F Eh
FA0100h

FEFFFEh

FFFFFFh

Configuration Memory Space

User Memory Space

Flash Write Latches

DEVID (2)

Reserved

FF0000h

F9FFFEh
FA0000h

800000h

7FFFFFh

Reserved

Flash Config Words

0xxx00h

(1)

0xxxFEh

(1)

Unimplemented

Read ‘0’

User Flash Program Memory

801800h

Reserved

FF0004h

Reserved

Executive Code Memory

800FFEh

800100h

Customer OTP Memory

8017FEh

801700h

Reserved

801000h
8016FEh

Legend: Memory areas are not shown to scale.

Note 1: Exact boundary addresses are determined by the size of the implemented program memory (Table 4-1).

FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GA705 DEVICES

TABLE 4-1: PROGRAM MEMORY SIZES AND BOUNDARIES

Program Memory

Device

Upper Boundary

Write Blocks

(2)

(1)

Erase Blocks

(Instruction Words)

PIC24FJ256GA70X 02AFFEh (88,064 x 24) 688 86

PIC24FJ128GA70X 015FFEh (45,056 x 24) 352 44

PIC24FJ64GA70X 00AFFEh (22,528 x 24) 176 22

Note 1: One Write Block = 128 Instruction Words; One Erase Block (Page) = 1024 Instruction Words.

2: To maintain integer page sizes, the memory sizes are not exactly half of each other.

(1)

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4.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in word­addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).

Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.

4.1.2 HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execu­tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the PC
on a device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.

The PIC24FJ256GA705 family devices can have up to
two Interrupt Vector Tables (IVTs). The first is located
from addresses, 000004h to 0000FFh. The Alternate

Interrupt Vector Table (AIVT) can be enabled by the
AIVTDIS Configuration bit if the Boot Segment (BS) is
present and at least two pages in size. If the user has
configured a Boot Segment, the AIVT will be located at
the address, (BSLIM[12:0]
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs).

A more detailed discussion of the Interrupt Vector
Tables is provided in Section 8.1 “Interrupt Vector

Tabl e”.

– 1) x 0x800. These vector

4.1.3 CONFIGURATION BITS OVERVIEW

The Configuration bits are stored in the last page loca­tion of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system oper­ation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.

Table 4-2 lists all of the Configuration registers as well

as their Configuration register locations. Refer to

Section 29.0 “Special Features” for the full

Configuration register description for each specific
device.

TABLE 4-2: CONFIGURATION WORD ADDRESSES

Configuration

Registers

FSEC 02AF00h 015F00h 00AF00h

FBSLIM 02AF10h 015F10h 00AF10h

FSIGN 02AF14h 015F14h 00AF14h

FOSCSEL 02AF18h 015F18h 00AF18h

FOSC 02AF1Ch 015F1Ch 00AF1Ch

FWDT 02AF20h 015F20h 00AF20h

FPOR 02AF24h 015F24h 00AF24h

FICD 02AF28h 015F28h 00AF28h

FDEVOPT1 02AF2Ch 015F2Ch 00AF2Ch

PIC24FJ256GA70X PIC24FJ128GA70X PIC24FJ64GA70X

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4.1.4 CODE-PROTECT CONFIGURATION BITS

The device implements intermediate security features
defined by the FSEC register. The Boot Segment (BS)
is the higher privileged segment and the General Seg­ment (GS) is the lower privileged segment. The total
user code memory can be split into BS or GS. The size
of the segments is determined by the BSLIM[12:0] bits.
The relative location of the segments within user space
does not change, such that BS (if present) occupies the
memory area just after the Interrupt Vector Table (IVT)
and the GS occupies the space just after the BS (or if
the Alternate IVT is enabled, just after it).

The Configuration Segment (CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that are loaded by the NVM Controller during the
Reset sequence.

4.1.5 CUSTOMER OTP MEMORY

PIC24FJ256GA705 family devices provide 256 bytes of
One-Time-Programmable (OTP) memory, located at
addresses, 801700h through 8017FEh. This memory
can be used for persistent storage of application-specific
information that will not be erased by reprogramming the
device. This includes many types of information, such as
(but not limited to):

• Application Checksums

• Code Revision Information

• Product Information

• Serial Numbers

• System Manufacturing Dates

• Manufacturing Lot Numbers

Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data are not cleared by a chip erase.

Note: Do not write the OTP memory more than

one time. Writing to the OTP memory
more than once may result in a permanent
ECC Double-Bit Error (ECCDBE) trap.

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Note: Memory areas are not shown to scale.

0000h

07FEh

FFFEh

LSB

Address

LSBMSB

MSB

Address

0001h

07FFh

1FFFh

FFFFh

8001h

8000h

7FFFh

0801h

0800h

2001h

Near

1FFEh

SFR

2000h

7FFEh

EDS Window

Space

Data Space

Upper 32 Kbytes

Data Space

Lower 32 Kbytes

Data Space

16 Kbytes Data RAM

SFR Space

47FFh

4801h

47FEh
4800h

Unimplemented

4.2 Data Memory Space

The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to “Data Memory with
Extended Data Space (EDS)”
(www.microchip.com/DS39733) in the

“dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet

supersedes the information in the FRM.

The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-2.

gives a DS address range of 16 Kbytes or 8K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.

The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in

Section 4.2.5 “Extended Data Space (EDS)”.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte­addressable, 16-bit wide blocks. Data are aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.

FIGURE 4-2: DATA SPACE MEMORY MAP FOR PIC24FJ256GA705 DEVICES

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4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.

Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to deter­mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.

All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow­ing the system and/or user to examine the machine
state prior to execution of the address Fault.

All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.

®

MCUs and

A Sign-Extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register by executing a Zero-Extend
(ZE) instruction on the appropriate address.

Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.

4.2.3 NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the Data Space is addressable indirectly.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.

4.2.4 SPECIAL FUNCTION REGISTER (SFR) SPACE

The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.

SFRs are distributed among the modules that they con­trol and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where the SFRs are actually implemented, is
shown in Tab le 4 -3 . Each implemented area indicates
a 32-byte region where at least one address is
implemented as an SFR. A complete list of imple­mented SFRs, including their addresses, is shown in

Table 4-4 through 4-11.

TABLE 4-3: IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00 xx10 xx20 xx30 xx40 xx50 xx60 xx70 xx80 xx90 xxA0 xxB0 xxC0 xxD0 xxE0 xxF0

000h Core

100h OSC Reset

200h Capture Compare MCCP Comp ANCFG

300h MCCP

400h SPI

500h DMA

600h

700h

Legend: — = No implemented SFRs in this block

Note 1: Includes HLVD control.

DS30010118E-page 46  2016-2020 Microchip Technology Inc.

— — — — — I/O —

—A/DNVM — — PPS

2: Regions shown are approximate. Refer to Ta bl e 4 - 4 through Ta bl e 4 - 11 for exact addresses.

(1)

— — — — — — — — — — — — — — —

EPMP CRC REFO PMD Timers —CTMU RTCC

— — — — —UART— — — SPI

—CLC— —I

(2)

2

CDMA

PIC24FJ256GA705 FAMILY

TABLE 4-4: SFR MAP: 0000h BLOCK

File Name Address All Resets File Name Address All Resets

CPU CORE INTERRUPT CONTROLLER (CONTINUED)

WREG0 0000 0000 IEC1 009A 0000

WREG1 0002 0000 IEC2 009C 0000

WREG2 0004 0000 IEC3 009E 0000

WREG3 0006 0000 IEC4 00A0 0000

WREG4 0008 0000 IEC5 00A2 0000

WREG5 000A 0000 IEC6 00A4 0000

WREG6 000C 0000 IEC7 00A6 0000

WREG7 000E 0000 IPC0 00A8 4444

WREG8 0010 0000 IPC1 00AA 4444

WREG9 0012 0000 IPC2 00AC 4444

WREG10 0014 0000 IPC3 00AE 4444

WREG11 0016 0000 IPC4 00B0 4444

WREG12 0018 0000 IPC5 00B2 4404

WREG13 001A 0000 IPC6 00B4 4444

WREG14 001C 0000 IPC7 00B6 4444

WREG15 001E 0800 IPC8 00B8 0044

SPLIM 0020 xxxx IPC9 00BA 4444

PCL 002E 0000 IPC10 00BC 4444

PCH 0030 0000 IPC11 00BE 4444

DSRPAG 0032 0000 IPC12 00C0 4444

DSWPAG 0034 0000 IPC13 00C2 0440

RCOUNT 0036 xxxx IPC14 00C4 4400

SR 0042 0000 IPC15 00C6 4444

CORCON 0044 0004 IPC16 00C8 4444

DISICNT 0052 xxxx IPC17 00CA

TBLPAG 0054 0000 IPC18 00CC 0044

INTERRUPT CONTROLLER IPC19 00CE 0040

INTCON1 0080 0000 IPC20 00D0 4440

INTCON2 0082 8000 IPC21 00D2 4444

INTCON4 0086 0000 IPC22 00D4 4444

IFS0 0088 0000 IPC23 00D6 4400

IFS1 008A 0000 IPC24 00D8 4444

IFS2 008C 0000 IPC25 00DA 0440

IFS3 008E 0000 IPC26 00DC 0400

IFS4 0090 0000 IPC27 00DE 4440

IFS5 0092 0000 IPC28 00E0 4444

IFS6 0094 0000 IPC29 00E2 0044

IFS7 0096 0000 INTTREG 00E4 0000

IEC0 0098 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

4444

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TABLE 4-5: SFR MAP: 0100h BLOCK

File Name Address All Resets File Name Address All Resets

OSCILLATOR PMD (CONTINUED)

OSCCON 0100 xxx0 PMD3 017C 0000

CLKDIV 0102 30x0 PMD4 017E 0000

OSCTUN 0108 0000 PMD5 0180 0000

OSCDIV 010C 0001 PMD6 0182 0000

OSCFDIV 010E 0000 PMD7 0184 0000

RESET PMD8 0186 0000

RCON 0110 0003 TIMER

HLVD TMR1 0190 0000

HLVDCON 0114 0000 PR1 0192 FFFF

PMP T1CON 0194 0000

PMCON1 0128 0000 TMR2 0196 0000

PMCON2 012A 0000 TMR3HLD 0198 0000

PMCON3 012C 0000 TMR3 019A 0000

PMCON4 012E 0000 PR2 019C FFFF

PMCS1CF 0130 0000 PR3 019E FFFF

PMCS1BS 0132 0000 T2CON 01A0 0x00

PMCS1MD 0134 0000 T3CON 01A2 0x00

PMCS2CF 0136 0000 CTMU

PMCS2BS 0138 0000 CTMUCON1L 01C0 0000

PMCS2MD 013A 0000 CTMUCON1H 01C2 0000

PMDOUT1 013C xxxx CTMUCON2L 01C4 0000

PMDOUT2 013E xxxx REAL-TIME CLOCK AND CALENDAR (RTCC)

PMDIN1 0140 xxxx RTCCON1L 01CC xxxx

PMDIN2 0142 xxxx RTCCON1H 01CE xxxx

PMSTAT 0144 008F RTCCON2L 01D0 xxxx

CRC RTCCON2H 01D2 xxxx

CRCCON1 0158 00x0

CRCCON2 015A 0000 RTCSTATL 01D8 00xx

CRCXORL 015C 0000 TIMEL 01DC xx00

CRCXORH 015E 0000 TIMEH 01DE xxxx

CRCDATL 0160 xxxx DATEL 01E0 xx0x

CRCDATH 0162 xxxx DATEH 01E2 xxxx

CRCWDATL 0164 xxxx ALMTIMEL 01E4 xx00

CRCWDATH 0166 xxxx ALMTIMEH 01E6 xxxx

REFO ALMDATEL 01E8 xx0x

REFOCONL 0168 0000 ALMDATEH 01EA xxxx

REFOCONH 016A 0000 TSATIMEL 01EC xx00

PMD TSATIMEH 01EE xxxx

PMD1 0178 0000 TSADATEL 01F0 xx0x

PMD2 017A 0000 TSADATEH 01F2 xxxx

Legend: x = undefined. Reset values are shown in hexadecimal.

RTCCON3L 01D4 xxxx

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TABLE 4-6: SFR MAP: 0200h BLOCK

File Name Address All Resets File Name Address All Resets

INPUT CAPTURE MULTIPLE OUTPUT CAPTURE/COMPARE/PWM (CONTINUED)

IC1CON1 0200 0000 CCP1RAH 0286 0000

IC1CON2 0202 000D CCP1RBL 0288 0000

IC1BUF 0204 0000 CCP1RBH 028A 0000

IC1TMR 0206 0000 CCP1BUFL 028C 0000

IC2CON1 0208 0000 CCP1BUFH 028E 0000

IC2CON2 020A 000D CCP2CON1L 0290 0000

IC2BUF 020C 0000 CCP2CON1H 0292 0000

IC2TMR 020E 0000 CCP2CON2L 0294 0000

IC3CON1 0210 0000 CCP2CON2H 0296 0100

IC3CON2 0212 000D CCP2CON3L 0298 0000

IC3BUF 0214 0000 CCP2CON3H 029A 0000

IC3TMR 0216 0000 CCP2STATL 029C 00x0

OUTPUT COMPARE CCP2TMRL 02A0 0000

OC1CON1 0230 0000 CCP2TMRH 02A2 0000

OC1CON2 0232 000C CCP2PRL 02A4 FFFF

OC1RS 0234 xxxx CCP2PRH 02A6 FFFF

OC1R 0236 xxxx CCP2RAL 02A8 0000

OC1TMR 0238 xxxx CCP2RAH 02AA 0000

OC2CON1 023A 0000 CCP2RBL 02AC 0000

OC2CON2 023C 000C CCP2RBH 02AE 0000

OC2RS 023E xxxx CCP2BUFL 02B0 0000

OC2R 0240 xxxx CCP2BUFH 02B2 0000

OC2TMR 0242 xxxx CCP3CON1L 02B4 0000

OC3CON1 0244 0000 CCP3CON1H 02B6 0000

OC3CON2 0246 000C CCP3CON2L 02B8 0000

OC3RS 0248 xxxx CCP3CON2H 02BA 0100

OC3R 024A xxxx CCP3CON3L 02BC 0000

OC3TMR 024C xxxx CCP3CON3H 02BE 0000

MULTIPLE OUTPUT CAPTURE/COMPARE/PWM CCP3STATL 02C0 00x0

CCP1CON1L 026C 0000 CCP3TMRL 02C4 0000

CCP1CON1H 026E 0000 CCP3TMRH 02C6 0000

CCP1CON2L 0270 0000 CCP3PRL 02C8 FFFF

CCP1CON2H 0272 0100 CCP3PRH 02CA FFFF

CCP1CON3L 0274 0000 CCP3RAL 02CC 0000

CCP1CON3H 0276 0000 CCP3RAH 02CE 0000

CCP1STATL 0278 00x0 CCP3RBL 02D0 0000

CCP1TMRL 027C 0000 CCP3RBH 02D2 0000

CCP1TMRH 027E 0000 CCP3BUFL 02D4 0000

CCP1PRL 0280 FFFF CCP3BUFH 02D6 0000

CCP1PRH 0282 FFFF

CCP1RAL 0284 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

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TABLE 4-6: SFR MAP: 0200h BLOCK (CONTINUED)

File Name Address All Resets File Name Address All Resets

COMPARATORS COMPARATORS (CONTINUED)

CMSTAT 02E6 0000 CM3CON 02EE 0000

CVRCON 02E8 00xx ANALOG CONFIGURATION

CM1CON 02EA 0000 ANCFG 02F4 0000

CM2CON 02EC 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

TABLE 4-7: SFR MAP: 0300h BLOCK

File Name Address All Resets File Name Address All Resets

MULTIPLE OUTPUT CAPTURE/COMPARE/PWM UART

CCP4CON1L 0300 0000 U1MODE 0398 0000

CCP4CON1H 0302 0000 U1STA 039A 0110

CCP4CON2L 0304 0000 U1TXREG 039C x0xx

CCP4CON2H 0306 0100 U1RXREG 039E 0000

CCP4CON3L 0308 0000 U1BRG 03A0 0000

CCP4CON3H 030A 0000 U1ADMD 03A2 0000

CCP4STATL 030C 00x0 U2MODE 03AE 0000

CCP4TMRL 0310 0000 U2STA 03B0 0110

CCP4TMRH 0312 0000 U2TXREG 03B2 xxxx

CCP4PRL 0314 FFFF U2RXREG 03B4 0000

CCP4PRH 0316 FFFF U2BRG 03B6 0000

CCP4RAL 0318 0000 U2ADMD 03B8 0000

CCP4RAH 031A 0000 SPI

CCP4RBL 031C 0000 SPI1CON1L 03F4 0x00

CCP4RBH 031E 0000 SPI1CON1H 03F6 0000

CCP4BUFL 0320 0000 SPI1CON2L 03F8 0000

CCP4BUFH 0322 0000 SPI1STATL 03FC 0028

SPI1CON2H 03F8 0000

SPI1STATH 03FE 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

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TABLE 4-8: SFR MAP: 0400h BLOCK

File Name Address All Resets File Name Address All Resets

2

SPI (CONTINUED) I

SPI1BUFL 0400 0000 I2C1BRG 0498 0000

SPI1BUFH 0402 0000 I2C1CONL 049A 1000

SPI1BRGL 0404 xxxx I2C1CONH 049C 0000

SPI1IMSKL 0408 0000 I2C1STAT 049E 0000

SPI1IMSKH 040A 0000 I2C1ADD 04A0 0000

SPI1URDTL 040C 0000 I2C1MSK 04A2 0000

SPI1URDTH 040E 0000 I2C2RCV 04A4 0000

SPI2CON1L 0410 0x00 I2C2TRN 04A6 00FF

SPI2CON1H 0412 0000 I2C2BRG 04A8 0000

SPI2CON2L 0414 0000 I2C2CONL 04AA 1000

SPI2STATL 0418 0028 I2C2CONH 04AC 0000

SPI2STATH 041A 0000 I2C2STAT 04AE 0000

SPI2BUFL 041C 0000 I2C2ADD 04B0 0000

SPI2BUFH 041E 0000 I2C2MSK 04B2 0000

SPI2BRGL 0420 xxxx DMA

SPI2IMSKL 0424 0000 DMACON 04C4 0000

SPI2IMSKH 0426 0000 DMABUF 04C6 0000

SPI2URDTL 0428 0000 DMAL 04C8 0000

SPI2URDTH 042A 0000 DMAH 04CA 0000

SPI3CON1L 042C 0x00 DMACH0 04CC 0000

SPI3CON1H 042E 0000 DMAINT0 04CE 0000

SPI3CON2L 0430 0000 DMASRC0 04D0 0000

SPI3STATL 0434 0028 DMADST0 04D2 0000

SPI3STATH 0436 0000 DMACNT0 04D4 0001

SPI3BUFL 0438 0000 DMACH1 04D6

SPI3BUFH 043A 0000 DMAINT1 04D8 0000

SPI3BRGL 043C xxxx DMASRC1 04DA 0000

SPI3IMSKL 0440 0000 DMADST1 04DC 0000

SPI3IMSKH 0442 0000 DMACNT1 04DE 0001

SPI3URDTL 0444 0000 DMACH2 04E0 0000

SPI3URDTH 0446 0000 DMAINT2 04E2 0000

CONFIGURABLE LOGIC CELL (CLC) DMASRC2 04E4 0000

CLC1CONL 0464 0000 DMADST2 04E6 0000

CLC1CONH 0466 0000 DMACNT2 04E8 0001

CLC1SEL 0468 0000 DMACH3 04EA 0000

CLC1GLSL 046C 0000 DMAINT3 04EC 0000

CLC1GLSH 046E 0000 DMASRC3 04EE 0000

CLC2CONL 0470 0000 DMADST3 04F0 0000

CLC2CONH 0472 0000 DMACNT3 04F2 0001

CLC2SEL 0474 0000 DMACH4 04F4 0000

CLC2GLSL 0478 0000 DMAINT4 04F6 0000

CLC2GLSH 047A 0000 DMASRC4 04F8 0000

2

C DMADST4 04FA 0000

I

I2C1RCV 0494 0000 DMACNT4 04FC 0001

I2C1TRN 0496 00FF DMACH5 04FE 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

C (CONTINUED) 0498 0000

0000

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TABLE 4-9: SFR MAP: 0500h BLOCK

File Name Address All Resets File Name Address All Resets

DMA (CONTINUED) DMA (CONTINUED)

DMAINT5 0500 0000 DMADST5 0504 0000

DMASRC5 0502 0000 DMACNT5 0506 0001

Legend: x = undefined. Reset values are shown in hexadecimal.

TABLE 4-10: SFR MAP: 0600h BLOCK

File Name Address All Resets File Name Address All Resets

I/O PORTB (CONTINUED)

PADCON 065E 0000 ANSB 067E FFFF

IOCSTAT 0660 0000 IOCPB 0680 0000

PORTA IOCNB 0682 0000

TRISA 0662 FFFF IOCFB 0684 0000

PORTA 0664 0000 IOCPUB 0686 0000

LATA 0666 0000 IOCPDB 0688 0000

ODCA 0668 0000 PORTC

ANSA 066A FFFF TRISC 068A FFFF

IOCPA 066C 0000 PORTC 068C 0000

IOCNA 066E 0000 LATC 068E 0000

IOCFA 0670 0000 ODCC 0690 0000

IOCPUA 0672 0000 ANSC 0692 FFFF

IOCPDA 0674 0000 IOCPC 0694 0000

PORTB IOCNC 0696 0000

TRISB 0676 FFFF IOCFC 0698 0000

PORTB 0678 0000 IOCPUC 069A 0000

LATB 067A 0000 IOCPDC 069C 0000

ODCB 067C 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

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TABLE 4-11: SFR MAP: 0700h BLOCK

File Name Address All Resets File Name Address All Resets

A/D PERIPHERAL PIN SELECT

ADC1BUF0 0712 xxxx RPINR0 0790 3F3F

ADC1BUF1 0714 xxxx RPINR1 0792 3F3F

ADC1BUF2 0716 xxxx RPINR2 0794 3F3F

ADC1BUF3 0718 xxxx RPINR3 0796 3F3F

ADC1BUF4 071A xxxx RPINR5 079A 3F3F

ADC1BUF5 071C xxxx RPINR6 079C 3F3F

ADC1BUF6 071E xxxx RPINR7 079E 3F3F

ADC1BUF7 0720 xxxx RPINR8 07A0 003F

ADC1BUF8 0722 xxxx RPINR11 07A6 3F3F

ADC1BUF9 0724 xxxx RPINR12 07A8 3F3F

ADC1BUF10 0726 xxxx RPINR18 07B4 3F3F

ADC1BUF11 0728 xxxx RPINR19 07B6 3F3F

ADC1BUF12 072A xxxx RPINR20 07B8 3F3F

ADC1BUF13 072C xxxx RPINR21 07BA 3F3F

ADC1BUF14 072E xxxx RPINR22 07BC 3F3F

ADC1BUF15 0730 xxxx RPINR23 07BE 3F3F

AD1CON1 0746 xxxx RPINR25 07C2 3F3F

AD1CON2 0748 xxxx RPINR28 07C8 3F3F

AD1CON3 074A xxxx RPINR29 07CA 003F

AD1CHS 074C xxxx RPOR0 07D4 0000

AD1CSSH 074E xxxx RPOR1 07D6 0000

AD1CSSL 0750 xxxx RPOR2 07D8 0000

AD1CON4 0752 xxxx RPOR3 07DA 0000

AD1CON5 0754 xxxx RPOR4 07DC 0000

AD1CHITL 0758 xxxx RPOR5 07DE

AD1CTMENH 075A 0000 RPOR6 07E0 0000

AD1CTMENL 075C 0000 RPOR7 07E2 0000

AD1RESDMA 075E 0000 RPOR8 07E4 0000

NVM RPOR9 07E6 0000

NVMCON 0760 0000 RPOR10 07E8 0000

NVMADR 0762 xxxx RPOR11 07EA 0000

NVMADRU 0764 00xx RPOR12 07EC 0000

NVMKEY 0766 0000 RPOR13 07EE 0000

RPOR14 07F0 0000

Legend: x = undefined. Reset values are shown in hexadecimal.

0000

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0000h

Special

Registers

32-Kbyte

EDS

8000h

Program Memory

DSxPAG

= 002h

DSxPAG

= 1FFh

DSRPAG

= 200h

DSRPAG

= 3FFh

Function

018000h

01FFFEh

000000h 7F8001h

FFFFFEh 007FFEh 7FFFFFh

Program

Spac e

0800h

FFFEh

EDS Pages

EPMP Memory Space

(1)

External
Memory

Access

Using

EPMP

(1)

FF8000h

DSRPAG

= 2FFh

7F8000h

7FFFFEh

Access

Program

Space

Access

Program

Space

Access

DSRPAG

= 300h

000001h

007FFFh

Program

Space

Access

Note 1: The range of addressable memory available is dependent on the device pin count and EPMP implementation.

External

Memory

Access

Using

EPMP

(1)

Internal

Data

Memory

Space

(Lower

Word)

(Lower

Word)

(Upper

Word)

(Upper

Word)

Window

DSxPAG

= 001h

008000h

008800h

External
Memory

Access

Using

EPMP

(1)

047FEh
04800h

Unimplemented

4.2.5 EXTENDED DATA SPACE (EDS)

The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range. EDS includes any additional internal data
memory not directly accessible by the lower 32-Kbyte
data address space and any external memory through
EPMP.

In addition, EDS also allows read access to the
program memory space. This feature is called Program
Space Visibility (PSV) and is discussed in detail in

Section 4.3.3 “Reading Data from Program Memory
Using EDS”.

Figure 4-3 displays the entire EDS space. The EDS is

organized as pages, called EDS pages, with one page
equal to the size of the EDS window (32 Kbytes). A par­ticular EDS page is selected through the Data Space
Read Page register (DSRPAG) or the Data Space Write
Page register (DSWPAG). For PSV, only the DSRPAG
register is used. The combination of the DSRPAG
register value and the 16-bit wide data address forms a
24-bit Effective Address (EA).

FIGURE 4-3: EXTENDED DATA SPACE

The data addressing range of the PIC24FJ256GA705
family devices depends on the version of the Enhanced
Parallel Master Port implemented on a particular device;
this is, in turn, a function of device pin count. Table 4-12
lists the total memory accessible by each of the devices
in this family. For more details on accessing external
memory using EPMP, refer to “Enhanced Parallel
Master Port (EPMP)” (www.microchip.com/DS39730)
in the “dsPIC33/PIC24 Family Reference Manual”.

.

TABLE 4-12: TOTAL ACCESSIBLE DATA

MEMORY

Family

Internal

RAM

PIC24FJXXXGA70X 16K 1K

Note: Accessing Page 0 in the EDS window will

generate an address error trap as Page 0
is the base data memory (data locations,
0800h to 7FFFh, in the lower Data Space).

External RAM
Access Using

EPMP

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DSRPAG Reg

Select

Wn

98

15 Bits9 Bits

24-Bit EA

Wn[0] is Byte Select

0 = Extended SRAM and EPMP

1

0

; Set the EDS page from where the data to be read

mov #0x0002, w0
mov w0, DSRPAG ;page 2 is selected for read
mov #0x0800, w1 ;select the location (0x800) to be read
bset w1, #15 ;set the MSB of the base address, enable EDS mode

;Read a byte from the selected location

mov.b [w1++], w2 ;read Low byte
mov.b [w1++], w3 ;read High byte

;Read a word from the selected location

mov [w1], w2 ;

;Read Double - word from the selected location

mov.d [w1], w2 ;two word read, stored in w2 and w3

4.2.5.1 Data Read from EDS

In order to read the data from the EDS space, first, an
Address Pointer is set up by loading the required EDS
page number into the DSRPAG register and assigning
the offset address to one of the W registers. Once the
above assignment is done, the EDS window is enabled
by setting bit 15 of the Working register which is
assigned with the offset address; then, the contents of
the pointed EDS location can be read.

Figure 4-4 illustrates how the EDS space address is

Example 4-1 shows how to read a byte, word and

double word from EDS.

Note: All read operations from EDS space have

an overhead of one instruction cycle.
Therefore, a minimum of two instruction
cycles are required to complete an EDS
read. EDS reads under the REPEAT
instruction; the first two accesses take
three cycles and the subsequent
accesses take one cycle.

generated for read operations.

When the Most Significant bit (MSb) of EA is ‘1’ and
DSRPAG[9] = 0, the lower nine bits of DSRPAG are
concatenated to the lower 15 bits of EA to form a 24-bit
EDS space address for read operations.

FIGURE 4-4: EDS ADDRESS GENERATION FOR READ OPERATIONS

EXAMPLE 4-1: EDS READ CODE IN ASSEMBLY

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DSWPAG Reg

Select

Wn

8

15 Bits9 Bits

24-Bit EA

Wn[0] is Byte Select

1

0

; Set the EDS page where the data to be written

mov #0x0002, w0
mov w0, DSWPAG ;page 2 is selected for write
mov #0x0800, w1 ;select the location (0x800) to be written
bset w1, #15 ;set the MSB of the base address, enable EDS mode

;Write a byte to the selected location

mov #0x00A5, w2
mov #0x003C, w3
mov.b w2, [w1++] ;write Low byte
mov.b w3, [w1++] ;write High byte

;Write a word to the selected location

mov #0x1234, w2 ;
mov w2, [w1] ;

;Write a Double - word to the selected location

mov #0x1122, w2
mov #0x4455, w3
mov.d w2, [w1] ;2 EDS writes

4.2.5.2 Data Write into EDS

In order to write data to EDS, such as in EDS reads, an
Address Pointer is set up by loading the required EDS
page number into the DSWPAG register, and assigning
the offset address to one of the W registers. Once the
above assignment is done, then the EDS window is
enabled by setting bit 15 of the Working register,
assigned with the offset address, and the accessed
location can be written.

Figure 4-5 illustrates how the EDS address is generated

for write operations.

When the MSbs of EA are ‘1’, the lower nine bits of
DSWPAG are concatenated to the lower 15 bits of EA
to form a 24-bit EDS address for write operations.

Example 4-2 shows how to write a byte, word and

double word to EDS.

0x8000. While developing code in assembly, care must
be taken to update the Data Space Page registers when
an Address Pointer crosses the page boundary. The ‘C’
compiler keeps track of the addressing, and increments
or decrements the Page registers accordingly, while
accessing contiguous data memory locations.

Note 1: All write operations to EDS are executed

in a single cycle.

2: Use of Read-Modify-Write operation on

any EDS location under a REPEAT
instruction is not supported. For example:

BCLR, BSW, BTG, RLC f, RLNC f, RRC f,
RRNC f, ADD f, SUB f, SUBR f, AND f,
IOR f, XOR f, ASR f, ASL f.

3: Use the DSRPAG register while

performing Read-Modify-Write operations.

The Data Space Page registers (DSRPAG/DSWPAG)
do not update automatically while crossing a page
boundary, when the rollover happens, from 0xFFFF to

FIGURE 4-5: EDS ADDRESS GENERATION FOR WRITE OPERATIONS

EXAMPLE 4-2: EDS WRITE CODE IN ASSEMBLY

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[Free Word]

PC[15:0]

000000000

015

W15 (

before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

0000h

PC[22:16]

POP : [--W15]
PUSH : [W15++]

TABLE 4-13: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES

DSRPAG

(Data Space Read

Register)

(1)

x

001h 001h

002h 002h 010000h to

003h

•

•

•

•

•

1FFh

000h 000h Invalid Address Address Error Trap

Note 1: If the source/destination address is below 8000h, the DSRPAG and DSWPAG registers are not considered.

2: This Data Space can also be accessed by Direct Addressing.
3: When the source/destination address is above 8000h and DSRPAG/DSWPAG are ‘0’, an address error

trap will occur.

DSWPAG

(Data Space Write

Register)

(1)

x

003h

•

•

•

•

•

1FFh

Source/Destination

Address while

Indirect Addressing

24-Bit EA

Pointing to EDS

0000h to 1FFFh 000000h to

001FFFh

2000h to 7FFFh 002000h to

007FFFh

008000h to

00FFFEh

017FFEh

018000h to

0187FEh

8000h to FFFFh

FF8000h to

FFFFFEh

Comment

Near Data Space

(2)

EPMP Memory Space

•

•

•

•

(3)

4.2.6 SOFTWARE STACK

Apart from its use as a Working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer (SSP). The pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and post-

Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the SFR space.

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.
increments for stack pushes, as shown in Figure 4-6.
Note that for a PC push during any CALL instruction,

FIGURE 4-6: CALL STACK FRAME

the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.

Note: A PC push during exception processing

will concatenate the SRL register to the
MSB of the PC prior to the push.

The Stack Pointer Limit Value register (SPLIM), associ­ated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM[0] is forced
to ‘0’ as all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is com­pared with the value in SPLIM. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal,
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 2000h in RAM, initialize the
SPLIM with the value, 1FFEh.

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4.3 Interfacing Program and Data Memory Spaces

The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide Data Space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use these
data successfully, they must be accessed in a way that
preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the Data Space (Program Space Visibility)

Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word of the program word.

4.3.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.

For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the MSBs of TBLPAG are
used to determine if the operation occurs in the user
memory (TBLPAG[7] = 0) or the configuration memory
(TBLPAG[7] = 1).

For remapping operations, the 10-bit Extended Data
Space Read register (DSRPAG) is used to define a
16K word page in the program space. When the Most
Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9)
of DSRPAG is ‘1’, the lower eight bits of DSRPAG are
concatenated with the lower 15 bits of the EA to form a
23-bit program space address. The DSRPAG[8] bit
decides whether the lower word (when the bit is ‘0’) or
the higher word (when the bit is ‘1’) of program memory
is mapped. Unlike table operations, this strictly limits
remapping operations to the user memory area.

Table 4-14 and Figure 4-7 show how the program EA is

created for table operations and remapping accesses
from the data EA. Here, P[23:0] refers to a program
space word, whereas D[15:0] refers to a Data Space
word.

TABLE 4-14: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access
(Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility
(Block Remap/Read)

Note 1: Data EA[15] is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is DSRPAG[0].

2: DSRPAG[9] is always ‘1’ in this case. DSRPAG[8] decides whether the lower word or higher word of

program memory is read. When DSRPAG[8] is ‘0’, the lower word is read, and when it is ‘1’, the higher
word is read.

Access

Space

User 0 PC[22:1] 0

User TBLPAG[7:0] Data EA[15:0]

Configuration TBLPAG[7:0] Data EA[15:0]

User 0 DSRPAG[7:0]

[23] [22:16] [15] [14:1] [0]

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

Program Space Address

0xx xxxx xxxx xxxx xxxx xxx0

(2)

Data EA[14:0]

(1)

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0Program Counter

23 Bits

1

DSRPAG[7:0]

8 Bits

EA

15 Bits

Program Counter

Select

TBLPAG

8 Bits

EA

16 Bits

Byte Select

0

0

1/0

User/Configuration

Table Operations

(2)

Program Space Visibility

(1)

Space Select

24 Bits

23 Bits

(Remapping)

1/0

1/0

Note 1: DSRPAG[8] acts as word select. DSRPAG[9] should always be ‘1’ to map program memory to data memory.

2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is

accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the
lower word. Table Read operations are permitted in the configuration memory space.

1-Bit

FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

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081623

00000000

00000000

00000000

00000000

‘Phantom’ Byte

TBLRDH.B (Wn[0] = 0)

TBLRDL.W

TBLRDL.B (Wn[0] = 1)

TBLRDL.B (Wn[0] = 0)

23 15 0

TBLPAG

02

000000h

800000h

020000h

030000h

Program Space

Data EA[15:0]

The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.

4.3.2 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE
INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
Data Space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper eight bits of a
program space word as data.

The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.

Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space
location (P[15:0]) to a data address (D[15:0]).

In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.

2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P[23:16]) to a data address. Note that D[15:8],
the ‘phantom’ byte, will always be ‘0’.

In Byte mode, it maps the upper or lower byte of
the program word to D[7:0] of the data address,
as above. Note that the data will always be ‘0’
when the upper ‘phantom’ byte is selected (byte
select = 1).

In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are described in Section 6.0 “Flash

Program Memory”.

For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG[7] = 0, the table page is located in the user
memory space. When TBLPAG[7] = 1, the page is
located in configuration space.

Note: Only Table Read operations will execute

in the configuration memory space where
Device IDs are located. Table Write
operations are not allowed.

FIGURE 4-8: ACCESS PROGRAM MEMORY WITH TABLE INSTRUCTIONS

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; Set the EDS page from where the data to be read

mov #0x0202, w0
mov w0, DSRPAG ;page 0x202, consisting lower words, is selected for read
mov #0x000A, w1 ;select the location (0x0A) to be read
bset w1, #15 ;set the MSB of the base address, enable EDS mode

;Read a byte from the selected location

mov.b [w1++], w2 ;read Low byte
mov.b [w1++], w3 ;read High byte

;Read a word from the selected location

mov [w1], w2 ;

;Read Double - word from the selected location

mov.d [w1], w2 ;two word read, stored in w2 and w3

4.3.3 READING DATA FROM PROGRAM MEMORY USING EDS

The upper 32 Kbytes of Data Space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the Data Space without the need to use
special instructions (i.e., TBLRDL/H).

Program space access through the Data Space occurs
when the MSb of EA is ‘1’ and the DSRPAG[9] bit is
also ‘1’. The lower eight bits of DSRPAG are concate­nated to the Wn[14:0] bits to form a 23-bit EA to access
program memory. The DSRPAG[8] decides which word
should be addressed; when the bit is ‘0’, the lower
word, and when ‘1’, the upper word of the program
memory is accessed.

The entire program memory is divided into 512 EDS
pages, from 200h to 3FFh, each consisting of 16K words
of data. Pages, 200h to 2FFh, correspond to the lower
words of the program memory, while 300h to 3FFh
correspond to the upper words of the program memory.

Using this EDS technique, the entire program memory
can be accessed. Previously, the access to the upper

Table 4-15 provides the corresponding 23-bit EDS

address for program memory with EDS page and
source addresses.

For operations that use PSV and are executed outside a
REPEAT loop, the MOV and MOV.D instructions will require
one instruction cycle in addition to the specified execution
time. All other instructions will require two instruction
cycles in addition to the specified execution time.

For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an
interrupt

• Execution upon re-entering the loop after an
interrupt is serviced

Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.

word of the program memory was not supported.

TABLE 4-15: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES

DSRPAG

(Data Space Read Register)

Source Address while

Indirect Addressing

23-Bit EA Pointing

to EDS

Comment

200h

•

•

•

2FFh

300h

•

•

•

3FFh

8000h to FFFFh

000000h to 007FFEh

•

•

•

7F8000h to 7FFFFEh

000001h to 007FFFh

•

•

•

7F8001h to 7FFFFFh

000h Invalid Address Address error trap.

Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap

will occur.

EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY

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Lower words of 4M program
instructions (8 Mbytes) for
read operations only.

Upper words of 4M program
instructions (4 Mbytes remaining;
4 Mbytes are phantom bytes) for
read operations only.

(1)

PIC24FJ256GA705 FAMILY

23 15 0

DSRPAG

Data SpaceProgram Space

0000h

8000h

FFFFh

202h

000000h

7FFFFEh

010000h

017FFEh

When DSRPAG[9:8] = 10 and EA[15] = 1:

EDS Window

The data in the page
designated by DSRPAG
are mapped into the
upper half of the data

memory space....

Data EA[14:0]

...while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre­sponds exactly to the
same lower 15 bits of
the actual program
space address.

23 15 0DSRPAG

Data SpaceProgram Space

0000h

8000h

FFFFh

302h

000000h

7FFFFEh

010001h

017FFFh

When DSRPAG[9:8] = 11 and EA[15] = 1:

The data in the page
designated by DSRPAG
are mapped into the
upper half of the data

memory space....

Data EA[14:0]

...while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre­sponds exactly to the
same lower 15 bits of
the actual program
space address.

EDS Window

FIGURE 4-9: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD

FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD

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To I/O Ports

To DMA-Enabled

Peripherals

and Peripherals

DMACH0

DMAINT0
DMASRC0
DMADST0
DMACNT0

DMACH1

DMAINT1

DMASRC1

DMADST1

DMACNT1

DMACH4

DMAINT4
DMASRC4
DMADST4
DMACNT4

DMACH5

DMAINT5
DMASRC5
DMADST5
DMACNT5

DMACON

DMAH
DMAL

DMABUF

Channel 0 Channel 1 Channel 4 Channel 5

Data RAM

Address Generation

Data RAM

Control

Logic

Data

Bus

CPU Execution Monitoring

5.0 DIRECT MEMORY ACCESS CONTROLLER (DMA)

Note: This data sheet summarizes the features

of the PIC24FJ256GA705 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to “Direct Memory
Access Controller (DMA)”
(www.microchip.com/DS30009742) in the

“dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet

supersedes the information in the FRM.

The Direct Memory Access (DMA) Controller is designed
to service high throughput data peripherals operating on
the SFR bus, allowing them to access data memory
directly and alleviating the need for CPU-intensive man­agement. By allowing these data-intensive peripherals to
share their own data path, the main data bus is also
deloaded, resulting in additional power savings.

The DMA Controller functions both as a peripheral and a
direct extension of the CPU. It is located on the microcon­troller data bus between the CPU and DMA-enabled
peripherals, with direct access to SRAM. This partitions
the SFR bus into two buses, allowing the DMA Controller
access to the DMA-capable peripherals located on the
new DMA SFR bus. The controller serves as a Master
device on the DMA SFR bus, controlling data flow from
DMA-capable peripherals.

The controller also monitors CPU instruction process­ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor Stall. This makes the controller essentially
transparent to the user.

The DMA Controller has these features:

• Six Independent and Independently
Programmable Channels

• Concurrent Operation with the CPU (no DMA
caused Wait states)

• DMA Bus Arbitration

• Five Programmable Address modes

• Four Programmable Transfer modes

• Four Flexible Internal Data Transfer modes

• Byte or Word Support for Data Transfer

• 16-Bit Source and Destination Address Register
for Each Channel, Dynamically Updated and
Reloadable

• 16-Bit Transaction Count Register, Dynamically
Updated and Reloadable

• Upper and Lower Address Limit Registers

• Counter Half-Full Level Interrupt

• Software-Triggered Transfer

• Null Write mode for Symmetric Buffer Operations

A simplified block diagram of the DMA Controller is
shown in Figure 5-1.

FIGURE 5-1: DMA FUNCTIONAL BLOCK DIAGRAM

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5.1 Summary of DMA Operations

The DMA Controller is capable of moving data between
addresses according to a number of different parameters.
Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a differ­ent transaction at the same time. Transactions are
classified by these parameters:

• Source and destination (SFRs and data RAM)

• Data size (byte or word)

• Trigger source

• Transfer mode (One-Shot, Repeated or
Continuous)

• Addressing modes (Fixed Address or Address
Blocks, with or without Address Increment/
Decrement)

In addition, the DMA Controller provides channel priority
arbitration for all channels.

5.1.1 SOURCE AND DESTINATION

Using the DMA Controller, data may be moved between
any two addresses in the Data Space. The SFR space
(0000h to 07FFh), or the data RAM space (0800h to
FFFFh), can serve as either the source or the destina­tion. Data can be moved between these areas in either
direction or between addresses in either area. The four
different combinations are shown in Figure 5-2.

If it is necessary to protect areas of data RAM, the DMA
Controller allows the user to set upper and lower address
boundaries for operations in the Data Space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.

5.1.2 DATA SIZE

The DMA Controller can handle both 8-bit and 16-bit
transactions. Size is user-selectable using the SIZE bit
(DMACHn[1]). By default, each channel is configured
for word-sized transactions. When byte-sized transac­tions are chosen, the LSb of the source and/or
destination address determines if the data represent
the upper or lower byte of the data RAM location.

5.1.3 TRIGGER SOURCE

The DMA Controller can use any one of the device’s
interrupt sources to initiate a transaction. The DMA
Trigger sources are listed in reverse order of their
natural interrupt priority and are shown in Table 5-1.

Since the source and destination addresses for any
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.

5.1.4 TRANSFER MODE

The DMA Controller supports four types of data
transfers, based on the volume of data to be moved for
each trigger.

• One-Shot: A single transaction occurs for each
trigger.

• Continuous: A series of back-to-back transactions
occur for each trigger; the number of transactions
is determined by the DMACNTn transaction
counter.

• Repeated One-Shot: A single transaction is
performed repeatedly, once per trigger, until the
DMA channel is disabled.

• Repeated Continuous: A series of transactions
are performed repeatedly, one cycle per trigger,
until the DMA channel is disabled.

All transfer modes allow the option to have the source
and destination addresses, and counter value automat­ically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.

5.1.5 ADDRESSING MODES

The DMA Controller also supports transfers between
single addresses or address ranges. The four basic
options are:

• Fixed-to-Fixed: Between two constant addresses

• Fixed-to-Block: From a constant source address
to a range of destination addresses

• Block-to-Fixed: From a range of source addresses
to a single, constant destination address

• Block-to-Block: From a range to source
addresses to a range of destination addresses

The option to select auto-increment or auto-decrement
of source and/or destination addresses is available for
Block Addressing modes.

In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is gen­erated jointly by the DMA Controller and a PIA-capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed range offset address.

For PIC24FJ256GA705 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in

Section 24.0 “12-Bit A/D Converter with Threshold
Detect”.

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SFR Area

Data RAM

DMA RAM Area

SFR Area

Data RAM

DMA RAM Area

SFR Area

Data RAM

SFR Area

Data RAM

07FFh
0800h

DMASRCn

DMADSTn

DMA RAM Area

DMAL

DMAH

07FFh
0800h

DMASRCn

DMADSTn

DMAL

DMAH

07FFh
0800h

DMASRCn

DMADSTn

DMAL

DMAH

07FFh
0800h

DMASRCn

DMADSTn

DMAL

DMAH

DMA RAM Area

Peripheral to Memory Memory to Peripheral

Peripheral to Peripheral Memory to Memory

Note: Relative sizes of memory areas are not shown to scale.

FIGURE 5-2: TYPES OF DMA DATA TRANSFERS

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5.1.6 CHANNEL PRIORITY

Each DMA channel functions independently of the
others, but also competes with the others for access to
the data and DMA buses. When access collisions
occur, the DMA Controller arbitrates between the
channels using a user-selectable priority scheme. Two
schemes are available:

• Round-Robin: When two or more channels
collide, the lower numbered channel receives
priority on the first collision. On subsequent colli­sions, the higher numbered channels each
receive priority based on their channel number.

• Fixed: When two or more channels collide, the
lowest numbered channel always receives
priority, regardless of past history; however, any
channel being actively processed is not available
for an immediate retrigger. If a higher priority
channel is continually requesting service, it will be
scheduled for service after the next lower priority
channel with a pending request.

5.2 Typical Setup

To set up a DMA channel for a basic data transfer:

1. Enable the DMA Controller (DMAEN = 1) and

select an appropriate channel priority scheme
by setting or clearing PRSSEL.

2. Program DMAH and DMAL with the appropriate

upper and lower address boundaries for data
RAM operations.

3. Select the DMA channel to be used and disable

its operation (CHEN = 0).

4. Program the appropriate source and destination

addresses for the transaction into the channel’s
DMASRCn and DMADSTn registers. For PIA
mode addressing, use the base address value.

5. Program the DMACNTn register for the number

of triggers per transfer (One-Shot or Continuous
modes) or the number of words (bytes) to be
transferred (Repeated modes).

6. Set or clear the SIZE bit to select the data size.

7. Program the TRMODE[1:0] bits to select the

Data Transfer mode.

8. Program the SAMODE[1:0] and DAMODE[1:0]

bits to select the addressing mode.

9. Enable the DMA channel by setting CHEN.

10. Enable the trigger source interrupt.

5.3 Peripheral Module Disable

Unlike other peripheral modules, the channels of the
DMA Controller cannot be individually powered down
using the Peripheral Module Disable (PMD) registers.
Instead, the channels are controlled as two groups. The
DMA0MD bit (PMD7[4]) selectively controls DMACH0
through DMACH3. The DMA1MD bit (PMD7[5]) controls
DMACH4 and DMACH5. Setting both bits effectively
disables the DMA Controller.

5.4 DMA Registers

The DMA Controller uses a number of registers to con­trol its operation. The number of registers depends on
the number of channels implemented for a particular
device.

There are always four module-level registers (one
control and three buffer/address):

• DMACON: DMA Engine Control Register
(Register 5-1)

• DMAH and DMAL: DMA High and Low Address
Limit Registers

• DMABUF: DMA Data Buffer

Each of the DMA channels implements five registers
(two control and three buffer/address):

• DMACHn: DMA Channel n Control Register
(Register 5-2)

• DMAINTn: DMA Channel n Interrupt Register
(Register 5-3)

• DMASRCn: DMA Data Source Address Pointer
for Channel n

• DMADSTn: DMA Data Destination
for Channel n

• DMACNTn: DMA Transaction Counter for
Channel n

For PIC24FJ256GA705 family devices, there are a
total of 34 registers.

Address Pointer

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REGISTER 5-1: DMACON: DMA ENGINE CONTROL REGISTER

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

DMAEN

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — PRSSEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 DMAEN: DMA Module Enable bit

bit 14-1 Unimplemented: Read as ‘0’

bit 0 PRSSEL: Channel Priority Scheme Selection bit

— — — — — — —

1 = Enables module
0 = Disables module and terminates all active DMA operation(s)

1 = Round-robin scheme
0 = Fixed priority scheme

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REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER

U-0 U-0 U-0 r-0 U-0 R/W-0 R/W-0 R/W-0

— — — — —NULLWRELOAD

(1)

CHREQ

(3)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN

bit 7 bit 0

Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 Reserved: Maintain as ‘0’

bit 11 Unimplemented: Read as ‘0’

bit 10 NULLW: Null Write Mode bit

1 = A dummy write is initiated to DMASRCn for every write to DMADSTn
0 = No dummy write is initiated

bit 9 RELOAD: Address and Count Reload bit

(1)

1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the

start of the next operation

0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation

bit 8 CHREQ: DMA Channel Software Request bit

(3)

(2)

1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending

bit 7-6 SAMODE[1:0]: Source Address Mode Selection bits

11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRCn is decremented based on the SIZE bit after a transfer completion
01 = DMASRCn is incremented based on the SIZE bit after a transfer completion
00 = DMASRCn remains unchanged after a transfer completion

bit 5-4 DAMODE[1:0]: Destination Address Mode Selection bits

11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADSTn is decremented based on the SIZE bit after a transfer completion
01 = DMADSTn is incremented based on the SIZE bit after a transfer completion
00 = DMADSTn remains unchanged after a transfer completion

bit 3-2 TRMODE[1:0]: Transfer Mode Selection bits

11 = Repeated Continuous mode
10 = Continuous mode
01 = Repeated One-Shot mode
00 = One-Shot mode

bit 1 SIZE: Data Size Selection bit

1 = Byte (8-bit)
0 = Word (16-bit)

bit 0 CHEN: DMA Channel Enable bit

1 = The corresponding channel is enabled
0 = The corresponding channel is disabled

Note 1: Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn.

2: DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers

(DMACHn[2] = 1), regardless of the state of the RELOAD bit.

3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE[1:0].

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REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

DBUFWF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0

HIGHIF

(1,2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

CHSEL6 CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0

LOWIF

(1,2)

DONEIF

(1)

HALFIF

(1)

OVRUNIF

(1)

— —HALFEN

bit 15 DBUFWF: DMA Buffered Data Write Flag bit

(1)

1 = The content of the DMA buffer has not been written to the location specified in DMADSTn or

DMASRCn in Null Write mode

0 = The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn

in Null Write mode

bit 14-8 CHSEL[6:0]: DMA Channel Trigger Selection bits

See Table 5 -1 for a complete list.

bit 7 HIGHIF: DMA High Address Limit Interrupt Flag bit

(1,2)

1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the

data RAM space

0 = The DMA channel has not invoked the high address limit interrupt

bit 6 LOWIF: DMA Low Address Limit Interrupt Flag bit

(1,2)

1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above

the SFR range (07FFh)

0 = The DMA channel has not invoked the low address limit interrupt

bit 5 DONEIF: DMA Complete Operation Interrupt Flag bit

If CHEN = 1:

1 = The previous DMA session has ended with completion
0 = The current DMA session has not yet completed

If CHEN =

0:
1 = The previous DMA session has ended with completion
0 = The previous DMA session has ended without completion

bit 4 HALFIF: DMA 50% Watermark Level Interrupt Flag bit

1 = DMACNTn has reached the halfway point to 0000h
0 = DMACNTn has not reached the halfway point

bit 3 OVRUNIF: DMA Channel Overrun Flag bit

(1)

1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger
0 = The overrun condition has not occurred

bit 2-1 Unimplemented: Read as ‘0’

bit 0 HALFEN: Halfway Completion Watermark bit

1 = Interrupts are invoked when DMACNTn has reached its halfway point and at completion
0 = An interrupt is invoked only at the completion of the transfer

(1)

(1)

Note 1: Setting these flags in software does not generate an interrupt.

2: Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than

DMAL) is NOT done before the actual access.

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TABLE 5-1: DMA TRIGGER SOURCES

CHSEL[6:0] Trigger (Interrupt) CHSEL[6:0] Trigger (Interrupt)

0000000 Off 1000001 UART2 TX Interrupt

0001001 MCCP4 IC/OC Interrupt 1000010 UART2 RX Interrupt

0001010 MCCP4 Timer Interrupt 1000011 UART2 Error Interrupt

0001011 MCCP3 IC/OC Interrupt 1000100 UART1 TX Interrupt

0001100 MCCP3 Timer Interrupt 1000101 UART1 RX Interrupt

0001101 MCCP2 IC/OC Interrupt 1000110 UART1 Error Interrupt

0001110 MCCP2 Timer Interrupt 1001011 DMA Channel 5 Interrupt

0001111 MCCP1 IC/OC Interrupt 1001100 DMA Channel 4 Interrupt

0010000 MCCP1 Timer Interrupt 1001101 DMA Channel 3 Interrupt

0010100 OC3 Interrupt 1001110 DMA Channel 2 Interrupt

0010101 OC2 Interrupt 1001111 DMA Channel 1 Interrupt

0010110 OC1 Interrupt 1010000 DMA Channel 0 Interrupt

0011010 IC3 Interrupt 1010001 A/D Interrupt

0011011 IC2 Interrupt 1010011 PMP Interrupt

0011100 IC1 Interrupt 1010100 HLVD Interrupt

0100000 SPI3 Receive Interrupt 1010101 CRC Interrupt

0100001 SPI3 Transmit Interrupt 1011011 CLC2 Out

0100010 SPI3 General Interrupt 1011100 CLC1 Out

0100011 SPI2 Receive Interrupt 1011110 RTCC Alarm Interrupt

0100100 SPI2 Transmit Interrupt 1100001 TMR3 Interrupt

0100101 SPI2 General Interrupt 1100010 TMR2 Interrupt

0100110 SPI1 Receive Interrupt 1100011 TMR1 Interrupt

0100111 SPI1 Transmit Interrupt 1100110 CTMU Trigger

0101000 SPI1 General Interrupt 1100111 Comparator Interrupt

0101111 I2C2 Slave Interrupt 1101000 INT4 Interrupt

0110000 I2C2 Master Interrupt 1101001 INT3 Interrupt

0110001 I2C2 Bus Collision Interrupt 1101010 INT2 Interrupt

0110010 I2C1 Slave Interrupt 1101011 INT1 Interrupt

0110011 I2C1 Master Interrupt 1101100 INT0 Interrupt

0110100 I2C1 Bus Collision Interrupt 1101101 Interrupt-on-Change (IOC) Interrupt

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0

Program Counter

24 Bits

Program

TBLPAG Reg

8 Bits

Working Reg EA

16 Bits

Using

Byte

24-Bit EA

0

1/0

Select

Table
Instruction

Counter

Using

User/Configuration
Space Select

6.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
“PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.

The PIC24FJ256GA705 family of devices contains
internal Flash program memory for storing and execut­ing application code. The program memory is readable,
writable and erasable. The Flash memory can be
programmed in four ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self-Programming (RTSP)

•JTAG

• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)

ICSP allows a PIC24FJ256GA705 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (named PGCx and PGDx,
respectively), and three other lines for power (V
ground (V

SS) and Master Clear (MCLR). This allows

customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.

DD),

RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
may write program memory data in blocks of
128 instructions (384 bytes) at a time and erase
program memory in blocks of 1024 instructions
(3072 bytes) at a time.

The device implements a 7-bit Error Correcting Code
(ECC). The NVM block contains a logic to write and
read ECC bits to and from the Flash memory. The
Flash is programmed at the same time as the
corresponding ECC parity bits. The ECC provides
improved resistance to Flash errors. ECC single bit
errors can be transparently corrected; ECC double-bit
errors result in a trap.

6.1 Table Instructions and Flash Programming

Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG[7:0] bits and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 6-1.

The TBLRDL and the TBLWTL instructions are used to
read or write to bits[15:0] of program memory. TBLRDL
and TBLWTL can access program memory in both
Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read
or write to bits[23:16] of program memory. TBLRDH and
TBLWTH can also access program memory in Word or
Byte mode.

FIGURE 6-1: ADDRESSING FOR TABLE REGISTERS

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6.2 RTSP Operation

The PIC24F Flash program memory array is organized
into rows of 128 instructions or 384 bytes. RTSP allows
the user to erase blocks of eight rows (1024 instruc­tions) at a time and to program one row at a time. It is
also possible to program two instruction word blocks.

The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 3072 bytes and 384 bytes, respectively.

When data are written to program memory using
TBLWT instructions, the data are not written directly to
memory. Instead, data written using Table Writes are
stored in holding latches until the programming
sequence is executed.

Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
128 TBLWT instructions are required to write the full row
of memory.

To ensure that no data are corrupted during a write, any
unused address should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.

The basic sequence for RTSP programming is to set
the Table Pointer to point to the programming latches,
do a series of TBLWT instructions to load the buffers
and set the NVMADRU/NVMADR registers to point to
the destination. Programming is performed by setting
the control bits in the NVMCON register.

Data can be loaded in any order and the holding regis­ters can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.

Note: Writing to a location multiple times without

erasing is not recommended.

6.3 JTAG Operation

The PIC24F family supports JTAG boundary scan.
Boundary scan can improve the manufacturing
process by verifying pin to PCB connectivity.

6.4 Enhanced In-Circuit Serial Programming

Enhanced In-Circuit Serial Programming uses an on­board bootloader, known as the Program Executive
(PE), to manage the programming process. Using an
SPI data frame format, the Program Executive can
erase, program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.

Note: The PGD2/PGC2 port on 28-pin packages

supports ICSP™ only, so Enhanced ICSP
programming does not work.

6.5 Control Registers

There are four SFRs used to read and write the
program Flash memory: NVMCON, NVMADRU,
NVMADR and NVMKEY.

The NVMCON register (Register 6-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.

NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 6.6 “Programming

Operations” for further details.

The NVMADRU/NVMADR registers contain the upper
byte and lower word of the destination of the NVM write
or erase operation. Some operations (chip erase)
operate on fixed locations and do not require an address
value.

All of the Table Write operations are single-word writes
(two instruction cycles), because only the buffers
are written. A programming cycle is required for
programming each row.

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6.6 Programming Operations

A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON[15]) starts the operation
and the WR bit is automatically cleared when the
operation is finished.

PIC24FJ256GA705 FAMILY

REGISTER 6-1: NVMCON: FLASH MEMORY CONTROL REGISTER

HC/R/S-0

(1)

WR WREN WRERR NVMSIDL

bit 15 bit 8

R/W-0

(1)

HSC/R-0

(1)

R/W-0 r-0 r-0 U-0 U-0

— — — —

U-0 U-0 U-0 U-0 R/W-0

(1)

— — — — NVMOP[3:0]

R/W-0

(1)

R/W-0

(2)

(1)

R/W-0

(1)

bit 7 bit 0

Legend: S = Settable bit HC = Hardware Clearable bit r = Reserved bit

R = Readable bit W = Writable bit ‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’

HSC = Hardware Settable/Clearable bit

bit 15 WR: Write Control bit

(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is

cleared by hardware once the operation is complete

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

(1)

1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

(1)

1 = An improper program or erase sequence attempt, or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12 NVMSIDL: NVM Stop in Idle bit

1 = Removes power from the program memory when device enters Idle mode
0 = Powers program memory in Standby mode when the device enters Idle mode

bit 11-10 Reserved: Maintain as ‘0’

bit 9-4 Unimplemented: Read as ‘0’

bit 3-0 NVMOP[3:0]: NVM Operation Select bits

(1,2)

1110 = Chip erases user memory (does not erase Device ID, customer OTP or executive memory)
0100 = Unused
0011 = Erases a page of program or executive memory
0010 = Row programming operation
0001 = Double-word programming operation

Note 1: These bits can only be reset on a Power-on Reset.

2: All other combinations of NVMOP[3:0] are unimplemented.

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6.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:

1. Read eight rows of program memory

(1024 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 6-1):

a) Set the NVMOP[3:0] bits (NVMCON[3:0]) to

‘0011’ to configure for block erase. Set the
WREN (NVMCON[14]) bit.

b) Write the starting address of the block to

be erased into the NVMADRU/NVMADR

registers.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
e) Set the WR bit (NVMCON[15]). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Update the TBLPAG register to point to the pro­gramming latches on the device. Update the
NVMADRU/NVMADR registers to point to the
destination in the program memory.

5. Write the first 128 instructions from data RAM into
the program memory buffers (see Table 6-1).

6. Write the program block to Flash memory:
a) Set the NVMOPx bits to ‘0010’ to configure

for row programming. Set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration

of the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

7. Repeat Steps 4 through 6, using the next
available 128 instructions from the block in data
RAM, by incrementing the value in NVMADRU/
NVMADR until all 1024 instructions are written
back to Flash memory.

For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 6-2.

TABLE 6-1: EXAMPLE PAGE ERASE

Step 1: Set the NVMCON register to erase a page.

MOV #0x4003, W0
MOV W0, NVMCON

Step 2: Load the address of the page to be erased into the NVMADR register pair.

MOV #PAGE_ADDR_LO, W0
MOV W0, NVMADR
MOV #PAGE_ADDR_HI, W0
MOV W0, NVMADRU

Step 3: Set the WR bit.

MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
BSET NVMCON, #WR
NOP
NOP
NOP

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// C example using MPLAB XC16

unsigned long progAddr = 0xXXXXXX; // Address of row to write
unsigned int offset;

//Set up pointer to the first memory location to be written

NVMADRU = progAddr>>16; // Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF; // Initialize lower word of address
NVMCON = 0x4003; // Initialize NVMCON
asm("DISI #5"); // Block all interrupts with priority <7

// for next 5 instructions

__builtin_write_NVM(); // check function to perform unlock

// sequence and set WR

EXAMPLE 6-1: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE)

TABLE 6-2: CODE MEMORY PROGRAMMING EXAMPLE: ROW WRITES

Step 1: Set the NVMCON register to program 128 instruction words.

MOV #0x4002, W0
MOV W0, NVMCON

Step 2: Initialize the TBLPAG register for writing to the latches.

MOV #0xFA, W12
MOV W12, TBLPAG

Step 3: Load W0:W5 with the next four instruction words to program.

MOV #<LSW0>, W0
MOV #<MSB1:MSB0>, W1
MOV #<LSW1>, W2
MOV #<LSW2>, W3
MOV #<MSB3:MSB2>, W4
MOV #<LSW3>, W5

Step 4: Set the Read Pointer (W6) and load the (next set of) write latches.

CLR W6
CLR W7
TBLWTL [W6++], [W7]
TBLWTH.B [W6++], [W7++]
TBLWTH.B [W6++], [++W7]
TBLWTL [W6++], [W7++]
TBLWTL [W6++], [W7]
TBLWTH.B [W6++], [W7++]
TBLWTH.B [W6++], [++W7]
TBLWTL [W6++], [W7++]

Step 5: Repeat Steps 4 and 5, for a total of 32 times, to load the write latches with 128 instructions.

Step 6: Set the NVMADRU/NVMADR register pair to point to the correct address.

MOV #DestinationAddress<15:0>, W3
MOV #DestinationAddress<23:16>, W4
MOV W3, NVMADR
MOV W4, NVMADRU

Step 7: Execute the WR bit unlock sequence and initiate the write cycle.

MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
BSET NVMCON, #WR
NOP
NOP
NOP

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DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions
MOV.B #0x55, W0
MOV W0, NVMKEY ; Write the 0x55 key
MOV.B #0xAA, W1 ;
MOV W1, NVMKEY ; Write the 0xAA key
BSET NVMCON, #WR ; Start the programming sequence
NOP ; Required delays
NOP
BTSC NVMCON, #15 ; and wait for it to be
BRA $-2 ; completed

EXAMPLE 6-2: INITIATING A PROGRAMMING SEQUENCE

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6.6.2 PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY

If a Flash location has been erased, it can be
programmed using Table Write instructions to write two
instruction words (2 x 24-bit) into the write latch. The
TBLPAG register is loaded with the address of the write
latches and the NVMADRU/NVMADR registers are
loaded with the address of the first of the two instruction
words to be programmed. The TBLWTL and TBLWTH

instructions write the desired data into the write latches.
To configure the NVMCON register for a two-word write,
set the NVMOPx bits (NVMCON[3:0]) to ‘0001’. The
write is performed by executing the unlock sequence
and setting the WR bit. An equivalent procedure in ‘C’,
using the MPLAB
functions, is shown in Example 6-3.

®

XC16 compiler and built-in hardware

TABLE 6-3: PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY

Step 1: Initialize the TBLPAG register for writing to the latches.

MOV #0xFA, W12
MOV W12, TBLPAG

Step 2: Load W0:W2 with the next two packed instruction words to program.

MOV #<LSW0>, W0
MOV #<MSB1:MSB0>, W1
MOV #<LSW1>, W2

Step 3: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.

CLR W6
CLR W7
TBLWTL [W6++], [W7]
TBLWTH.B
TBLWTH.B
TBLWTL.W

Step 4: Set the NVMADRU/NVMADR register pair to point to the correct address.

MOV #DestinationAddress<15:0>, W3
MOV #DestinationAddress<23:16>, W4
MOV W3, NVMADR
MOV W4, NVMADRU

Step 5: Set the NVMCON register to program two instruction words.

MOV #0x4001, W10
MOV W10, NVMCON
NOP

Step 6: Initiate the write cycle.

MOV #0x55, W1
MOV W1, NVMKEY
MOV #0xAA, W1
MOV W1, NVMKEY
BSET NVMCON, #WR
NOP
NOP
NOP

[W6++], [W7++]
[W6++], [++W7]
[W6++], [W7++]

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// C example using MPLAB XC16
unsigned long progAddr = 0xXXXXXX; // Address of word to program
unsigned int progData1L = 0xXXXX; // Data to program lower word of word 1
unsigned char progData1H = 0xXX; // Data to program upper byte of word 1
unsigned int progData2L = 0xXXXX; // Data to program lower word of word 2
unsigned char progData2H = 0xXX; // Data to program upper byte of word 2

//Set up NVMCON for word programming
NVMCON = 0x4001; // Initialize NVMCON
TBLPAG = 0xFA; // Point TBLPAG to the write latches

//Set up pointer to the first memory location to be written
NVMADRU = progAddr>>16; // Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF; // Initialize lower word of address

//Perform TBLWT instructions to write latches
__builtin_tblwtl(0, progData1L); // Write word 1 to address low word
__builtin_tblwth(0, progData1H); // Write word 1 to upper byte
__builtin_tblwtl(1, progData2L); // Write word 2 to address low word
__builtin_tblwth(1, progData2H); // Write word 2 to upper byte
asm(“DISI #5”); // Block interrupts with priority <7 for next 5

// instructions

__builtin_write_NVM(); //

XC16 function to perform unlock sequence and set WR

EXAMPLE 6-3: PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY

(‘C’ LANGUAGE CODE)

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MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

Enable Voltage Regulator

RESET

Instruction

WDT

Module

Glitch Filter

BOR

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

Configuration Mismatch

7.0 RESETS

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more
information, refer to “Reset”
(www.microchip.com/DS39712) in the

“dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet

supersedes the information in the FRM.

The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST
following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR

: Master Clear Pin Reset

•SWR: RESET Instruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

A simplified block diagram of the Reset module is
shown in Figure 7-1.

. The

Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.

Note: Refer to the specific peripheral or CPU

section of this manual for register Reset
states.

All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A POR will clear all bits, except for
the BOR and POR (RCON[1:0]) bits, which are set. The
user may set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software will not
cause a device Reset to occur.

The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.

Note: The status bits in the RCON register

should be cleared after they are read so
that the next RCON register values after a
device Reset will be meaningful.

FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM

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REGISTER 7-1: RCON: RESET CONTROL REGISTER

R/W-0 R/W-0 R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0

TRAPR

(1)

IOPUWR

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

(1)

EXTR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

SWR

(1)

(1)

SBOREN

SWDTEN

(5)

(4)

RETEN

WDTO

(1)

(2)

BOR

(1)

(1)

— —CM

SLEEP

(1)

IDLE

(1)

VREGS

POR

(3)

(1)

bit 15 TRAPR: Trap Reset Flag bit

(1)

1 = A Trap Conflict Reset has occurred

0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an

Address Pointer and caused a Reset

0 = An illegal opcode or Uninitialized W register Reset has not occurred

bit 13 SBOREN: Software Control Over the BOR Function bit

(5)

1 = BOR is enabled
0 = BOR is disabled

bit 12 RETEN: Retention Mode Enable bit

(2)

1 = Retention mode is enabled while device is in Sleep mode (1.2V regulator supplies to the core)
0 = Retention mode is disabled; normal voltage levels are present

bit 11-10 Unimplemented: Read as ‘0’

bit 9 CM: Configuration Word Mismatch Reset Flag bit

(1)

1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred

bit 8 VREGS: Fast Wake-up from Sleep bit

(3)

1 = Fast wake-up is enabled (uses more power)
0 = Fast wake-up is disabled (uses less power)

bit 7 EXTR: External Reset (MCLR

) Pin bit

(1)

1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software RESET (Instruction) Flag bit

(1)

1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed

(1)

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN

bit has no effect. Retention mode preserves the SRAM contents during Sleep.

3: Re-enabling the regulator after it enters Standby mode will add a delay, T

VREG, when waking up from Sleep.

Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.

4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of

the SWDTEN bit setting.

5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.

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REGISTER 7-1: RCON: RESET CONTROL REGISTER (CONTINUED)

bit 5 SWDTEN: Software Enable/Disable of WDT bit

1 = WDT is enabled
0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred
0 = WDT time-out has not occurred

bit 3 SLEEP: Wake from Sleep Flag bit

(1)

1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

(1)

1 = Device has been in Idle mode
0 = Device has not been in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

(1)

1 = A Brown-out Reset has occurred (also set after a Power-on Reset)
0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

(1)

1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred

(4)

(1)

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the LPCFG

Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN

bit has no effect. Retention mode preserves the SRAM contents during Sleep.

3: Re-enabling the regulator after it enters Standby mode will add a delay, T

VREG, when waking up from Sleep.

Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.

4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of

the SWDTEN bit setting.

5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.

TABLE 7-1: RESET FLAG BIT OPERATION

Flag Bit Setting Event Clearing Event

TRAPR (RCON[15]) Trap Conflict Event POR

IOPUWR (RCON[14]) Illegal Opcode or Uninitialized W Register Access POR

CM (RCON[9]) Configuration Mismatch Reset POR

EXTR (RCON[7]) MCLR Reset POR

SWR (RCON[6]) RESET Instruction POR

WDTO (RCON[4]) WDT Time-out CLRWDT, PWRSAV Instruction, POR

SLEEP (RCON[3]) PWRSAV #0 Instruction POR

IDLE (RCON[2]) PWRSAV #1 Instruction POR

BOR (RCON[1]) POR, BOR —

POR (RCON[0]) POR —

Note: All Reset flag bits may be set or cleared by the user software.

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7.1 Special Function Register Reset States

Most of the Special Function Registers (SFRs) associ­ated with the PIC24F CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC[2:0] bits in the FOSCSEL Flash
Configuration Word (see Table 7-2). The RCFGCAL
and NVMCON registers are only affected by a POR.

7.2 Device Reset Times

The Reset times for various types of device Reset are
summarized in Tab le 7 -3 . Note that the Master Reset
Signal, SYSRST, is released after the POR delay time
expires.

The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST

The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the system
clock source after the SYSRST

signal is released.

delay times.

7.3 Brown-out Reset (BOR)

PIC24FJ256GA705 family devices implement a BOR
circuit that provides the user with several configuration
and power-saving options. The BOR is controlled by the
BOREN[1:0] (FPOR[1:0]) Configuration bits.

When BOR is enabled, any drop of V
threshold results in a device BOR. Threshold levels are
described in Section 32.1 “DC Characteristics”.

DD below the BOR

7.4 Clock Source Selection at Reset

If clock switching is enabled, the system clock source
at device Reset is chosen, as shown in Tab le 7 -2 . If
clock switching is disabled, the system clock source is
always selected according to the Oscillator Configura­tion bits. For more information, refer to “Oscillator”
(www.microchip.com/DS39700) in the “dsPIC33/PIC24
Family Reference Manual”.

TABLE 7-2: OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK
SWITCHING ENABLED)

Reset Type Clock Source Determinant

POR

BOR

MCLR

WDTO

SWR

FNOSC[2:0] Configuration bits
(FOSCSEL[2:0])

COSC[2:0] Control bits
(OSCCON[14:12])

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TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

Reset Type Clock Source SYSRST Delay

POR

POR EC T

+ TSTARTUP + TRST — 1, 2, 3

ECPLL TPOR + TSTARTUP + TRST TLOCK 1, 2, 3, 5

POR

XT, HS, SOSC T

+ TSTARTUP + TRST TOST 1, 2, 3, 4

XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5

FRC, OSCFDIV TPOR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7

POR

FRCPLL T

+ TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6

LPRC TPOR + TSTARTUP + TRST TLPRC 1, 2, 3, 6

BOR EC TSTARTUP + TRST — 2, 3

ECPLL T

STARTUP + TRST TLOCK 2, 3, 5

XT, HS, SOSC TSTARTUP + TRST TOST 2, 3, 4

XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK 2, 3, 4, 5

FRC, OSCFDIV T

FRCPLL T

STARTUP + TRST TFRC 2, 3, 6, 7

STARTUP + TRST TFRC + TLOCK 2, 3, 5, 6

LPRC TSTARTUP + TRST TLPRC 2, 3, 6

MCLR

WDT Any Clock T

Any Clock TRST — 3

RST — 3

Software Any clock TRST — 3

Illegal Opcode Any Clock TRST — 3

Uninitialized W Any Clock T

RST — 3

Trap Conflict Any Clock TRST — 3

Note 1: TPOR = Power-on Reset delay (10 µs nominal).

2: TSTARTUP = TVREG.
3: TRST = Internal State Reset Time (2 µs nominal).
4: T

OST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing

the oscillator clock to the system.

5: T

LOCK = PLL Lock Time.

6: TFRC and TLPRC = RC Oscillator Start-up Times.
7: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC

so the system clock delay is just T

FRC, and in such cases, FRC start-up time is valid; it switches to the

Primary Oscillator after its respective clock delay.

System Clock

Delay

Notes

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7.4.1 POR AND LONG OSCILLATOR

START-UP TIMES

The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially low­frequency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

is released:

The device will not begin to execute code until a valid
clock source has been released to the system. There­fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.

7.4.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST
valid clock source is not available at this time, the
device will automatically switch to the FRC Oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).

is released. If a

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8.0 INTERRUPT CONTROLLER

Note 1: This data sheet summarizes the

features of the PIC24FJ256GA705
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this
data sheet, refer to “Interrupts”
(www.microchip.com/DS70000600) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.

2: Some registers and associated bits

described in this section may not be
available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register
and bit information.

The PIC24FJ256GA705 family interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
PIC24FJ256GA705 family CPU.

The interrupt controller has the following features:

• Up to Eight Processor Exceptions and Software
Traps

• Seven User-Selectable Priority Levels

• Interrupt Vector Table (IVT) with a Unique Vector
for Each Interrupt or Exception Source

• Fixed Priority within a Specified User Priority Level

• Fixed Interrupt Entry and Return Latencies

8.1 Interrupt Vector Table

8.1.1 ALTERNATE INTERRUPT VECTOR TAB LE

The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. The AIVTEN
(INTCON2[8]) control bit provides access to the AIVT.
If the AIVTEN bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.

The AIVT supports emulation and debugging efforts by
providing a means to switch between an application,
and a support environment, without requiring the inter­rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.

8.2 Reset Sequence

A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24FJ256GA705 family devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.

The PIC24FJ256GA705 family Interrupt Vector Table
(IVT), shown in Figure 8-1, resides in program memory
starting at location, 000004h. The IVT contains six non­maskable trap vectors and up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.

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Legend: BOA: Base Offset Address for AIVT, which is the starting address of the last page of the Boot Segment.

All addresses are in hexadecimal.

Note 1: See Table 8-2 for the interrupt vector list.

2: AIVT is only available when a Boot Segment is implemented.

Reset – GOTO Instruction 000000h

Reset – GOTO Address 000002h
Oscillator Fail Trap Vector 000004h
Address Error Trap Vector
General Hard Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

General Soft Trap Vector

Reserved
Interrupt Vector 0 000014h
Interrupt Vector 1

—

—
Interrupt Vector 52 00007Ch
Interrupt Vector 53 00007Eh
Interrupt Vector 54 000080h

—

—

Interrupt Vector 116 0000FCh
Interrupt Vector 117 0000FEh

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)

(1)

Alternate Interrupt Vector Table (AIVT)

(1,2)

Reserved BOA+00h

Reserved BOA+02h
Oscillator Fail Trap Vector BOA+04h
Address Error Trap Vector
General Hard Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

General Soft Trap Vector

Reserved

Interrupt Vector 0 BOA+14h
Interrupt Vector 1

—

—
Interrupt Vector 52 BOA+7Ch
Interrupt Vector 53 BOA+7Eh
Interrupt Vector 54 BOA+80h

—

—

Interrupt Vector 116
Interrupt Vector 117 BOA+FEh

(Start of Code) (BOA+100h)

FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLES

TABLE 8-1: TRAP VECTOR DETAILS

Trap Description

Oscillator Failure _OscillatorFail 0 000004h BOA+04h INTCON1[1] 15

Address Error _AddressError 1 000006h BOA+06h INTCON1[3] 14

General Hardware Error – ECCBDE _NVMError 2 000008h BOA+08h INTCON4[1] 13

General Hardware Error – SGHT _NVMError 2 000008h BOA+08h INTCON4[0] INTCON2[13] 13

Stack Error _StackError 3 00000Ah BOA+0Ah INTCON1[3] 12

Math Error – DIV0ERR _MathError 4 00000Ch BOA+0Ch INTCON1[3] 11

Reserved _ReservedTrap5 5 00000Eh BOA+0Eh

Reserved _ReservedTrap6 6 000010h BOA+10h

Reserved _ReservedTrap7 7 000012h BOA+12h

Legend: BOA = Base Offset Address for AIVT segment, which is the starting address of the last page of the Boot Segment.

MPLAB

®

XC16

ISR Name

Vector #IVT

Address

AIVT

Address

Generic

Flag

Trap Bit Location

Source

Flag

Enable Priority

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TABLE 8-2: INTERRUPT VECTOR DETAILS

®

Interrupt Description

External Interrupt 0 _INT0Interrupt 8 0 000014h IFS0[0] IEC0[0] IPC0[2:0]

Input Capture 1 _IC1Interrupt 9 1 000016h IFS0[1] IEC0[1] IPC0[6:4]

Output Compare 1 _OC1Interrupt 10 2 000018h IFS0[2] IEC0[2] IPC0[10:8]

Timer1 _T1Interrupt 11 3 00001Ah IFS0[3] IEC0[3] IPC0[14:12]

Direct Memory Access 0 _DMA0Interrupt 12 4 00001Ch IFS0[4] IEC0[4] IPC1[2:0]

Input Capture 2 _IC2Interrupt 13 5 00001Eh IFS0[5] IEC0[5] IPC1[6:4]

Output Compare 2 _OC2Interrupt 14 6 000020h IFS0[6] IEC0[6] IPC1[10:8]

Timer2 _T2Interrupt 15 7 000022h IFS0[7] IEC0[7] IPC1[14:12]

Timer3 _T3Interrupt 16 8 000024h IFS0[8] IEC0[8] IPC2[2:0]

SPI1 General _SPI1Interrupt 17 9 000026h IFS0[9] IEC0[9] IPC2[6:4]

SPI1 Transfer Done _SPI1TXInterrupt 18 10 000028h IFS0[10] IEC0[10] IPC2[10:8]

UART1 Receiver _U1RXInterrupt 19 11 00002Ah IFS0[11] IEC0[11] IPC2[14:12]

UART1 Transmitter _U1TXInterrupt 20 12 00002Ch IFS0[12] IEC0[12] IPC3[2:0]

A/D Converter 1 _ADC1Interrupt 21 13 00002Eh IFS0[13] IEC0[13] IPC3[6:4]

Direct Memory Access 1 _DMA1Interrupt 22 14 000030h IFS0[14] IEC0[14] IPC3[10:8]

NVM Program/Erase
Complete

I2C1 Slave Events _SI2C1Interrupt 24 16 000034h IFS1[0] IEC1[0] IPC4[2:0]

I2C1 Master Events _MI2C1Interrupt 25 17 000036h IFS1[1] IEC1[1] IPC4[6:4]

Comparator _CompInterrupt 26 18 000038h IFS1[2] IEC1[2] IPC4[10:8]

Interrupt-on-Change
Interrupt

External Interrupt 1 _INT1Interrupt 28 20 00003Ch IFS1[4] IEC1[4] IPC5[2:0]

Reserved Reserved 29 21 — — — —

Reserved Reserved 30 22 — — — —

Reserved Reserved 31 23 — — — —

Direct Memory Access 2 _DMA2Interrupt 32 24 000044h IFS1[8] IEC1[8] IPC6[2:0]

Output Compare 3 _OC3Interrupt 33 25 000046h IFS1[9] IEC1[9] IPC6[6:4]

Reserved Reserved 34 26 — — — —

Reserved Reserved 35 27 — — — —

Reserved Reserved 36 28 — — — —

External Interrupt 2 _INT2Interrupt 37 29 00004Eh IFS1[13] IEC1[13] IPC7[6:4]

UART2 Receiver _U2RXInterrupt 38 30 000050h IFS1[14] IEC1[14] IPC7[10:8]

UART2 Transmitter _U2TXInterrupt 39 31 000052h IFS1[15] IEC1[15] IPC7[14:12]

SPI2 General _SPI2Interrupt 40 32 000054h IFS2[0] IEC2[0] IPC8[2:0]

SPI2 Transfer Done _SPI2TXInterrupt 41 33 000056h IFS2[1] IEC2[1] IPC8[6:4]

Reserved Reserved 42 34 — — — —

Reserved Reserved 43 35 — — — —

Direct Memory Access 3 _DMA3Interrupt 44 36 00005Ch IFS2[4] IEC2[4] IPC9[2:0]

Input Capture 3 _IC3Interrupt 45 37 00005Eh IFS2[5] IEC2[5] IPC9[6:4]

Reserved Reserved 46 38 — — — —

Reserved Reserved 47 39 — — — —

MPLAB

_NVMInterrupt 23 15 000032h IFS0[15] IEC0[15] IPC3[14:12]

_IOCInterrupt 27 19 00003Ah IFS1[3] IEC1[3] IPC4[14:12]

XC16 ISR

Name

Highest Natural Order Priority

Vector #IRQ

#

IVT

Address

Interrupt Bit Location

Flag Enable Priority

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TABLE 8-2: INTERRUPT VECTOR DETAILS (CONTINUED)

®

Interrupt Description

Reserved Reserved 48 40 — — — —

Capture/Compare Timer3 _CCT3Interrupt 51 43 00006Ah IFS2[11] IEC2[11] IPC10[14:12]

Capture/Compare Timer4 _CCT4Interrupt 52 44 00006Ch IFS2[12] IEC2[12] IPC11[2:0]

Parallel Master Port _PMPInterrupt 53 45 00006Eh IFS2[13] IEC2[13] IPC11[6:4]

Direct Memory Access 4 _DMA4Interrupt 54 46 000070h IFS2[14] IEC2[14] IPC11[10:8]

Reserved Reserved 55 47 — — — —

Reserved Reserved 56 48 — — — —

I2C2 Slave Events _SI2C2Interrupt 57 49 000076h IFS3[1] IEC3[1] IPC12[6:4]

I2C2 Master Events _MI2C2Interrupt 58 50 000078h IFS3[2] IEC3[2] IPC12[10:8]

Reserved Reserved 59 51 — — — —

Reserved Reserved 60 52 — — — —

External Interrupt 3 _INT3Interrupt 61 53 00007Eh IFS3[5] IEC3[5] IPC13[6:4]

External Interrupt 4 _INT4Interrupt 62 54 000080h IFS3[6] IEC3[6] IPC13[10:8]

Reserved Reserved 63 55 — — — —

Reserved Reserved 64 56 — — — —

Reserved Reserved 65 57 — — — —

SPI1 Receive Done _SPI1RXInterrupt 66 58 000088h IFS3[10] IEC3[10] IPC14[10:8]

SPI2 Receive Done _SPI2RXInterrupt 67 59 00008Ah IFS3[11] IEC3[11] IPC14[14:12]

SPI3 Receive Done _SPI3RXInterrupt 68 60 00008Ch IFS3[12] IEC3[12] IPC15[2:0]

Direct Memory Access 5 _DMA5Interrupt 69 61 00008Eh IFS3[13] IEC3[13] IPC15[6:4]

Real-Time Clock and
Calendar

Capture/Compare 1 _CCP1Interrupt 71 63 000092h IFS3[15] IEC3[15] IPC15[14:12]

Capture/Compare 2 _CCP2Interrupt 72 64 000094h IFS4[0] IEC4[0] IPC16[2:0]

UART1 Error _U1ErrInterrupt 73 65 000096h IFS4[1] IEC4[1] IPC16[6:4]

UART2 Error _U2ErrInterrupt 74 66 000098h IFS4[2] IEC4[2] IPC16[10:8]

Cyclic Redundancy
Check

Reserved Reserved 76 68 — — — —

Reserved Reserved 77 69 — — — —

Reserved Reserved 78 70 — — — —

Reserved Reserved 79 71 — — — —

HLVD –
High/Low-Voltage Detect

Reserved Reserved 81 73 — — — —

Reserved Reserved 82 74 — — — —

Reserved Reserved 83 75 — — — —

Reserved Reserved 84 76 — — — —

CTMU Interrupt _CTMUInterrupt 85 77 0000AEh IFS4[13] IEC4[13] IPC19[6:4]

Reserved Reserved 86 78 — — — —

Reserved Reserved 87 79 — — — —

Reserved Reserved 88 80 — — — —

Reserved Reserved 89 81 — — — —

MPLAB

_RTCCInterrupt 70 62 000090h IFS3[14] IEC3[14] IPC15[10:8]

_CRCInterrupt 75 67 00009Ah IFS4[3] IEC4[3] IPC16[14:12]

_LVDInterrupt 80 72 0000A4h IFS4[8] IEC4[8] IPC18[2:0]

XC16 ISR

Name

Vector #IRQ

#

IVT

Address

Interrupt Bit Location

Flag Enable Priority

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TABLE 8-2: INTERRUPT VECTOR DETAILS (CONTINUED)

®

Interrupt Description

Reserved Reserved 90 82 — — — —

Reserved Reserved 91 83 — — — —

I2C1 Bus Collision _I2C1BCInterrupt 92 84 0000BCh IFS5[4] IEC5[4] IPC21[2:0]

I2C2 Bus Collision _I2C2BCInterrupt 93 85 0000BEh IFS5[5] IEC5[5] IPC21[6:4]

Reserved Reserved 94 86 — — — —

Reserved Reserved 95 87 — — — —

Reserved Reserved 96 88 — — — —

Reserved Reserved 97 89 — — — —

SPI3 General _SPI3Interrupt 98 90 0000C8h IFS5[10] IEC5[10] IPC22[10:8]

SPI3 Transfer Done _SPI3TXInterrupt 99 91 0000CAh IFS5[11] IEC5[11] IPC22[14:12]

Reserved Reserved 100 92 92 — — —

Reserved Reserved 101 93 93 — — —

Capture/Compare 3 _CCP3Interrupt 102 94 0000D0h IFS5[14] IEC5[14] IPC23[10:8]

Capture/Compare 4 _CCP4Interrupt 103 95 0000D2h IFS5[15] IEC5[15] IPC23[14:12]

Configurable Logic Cell 1 _CLC1Interrupt 104 96 0000D4h IFS6[0] IEC6[0] IPC24[2:0]

Configurable Logic Cell 2 _CLC2Interrupt 105 97 0000D6h IFS6[1] IEC6[1] IPC24[6:4]

Reserved Reserved 106 98 — — — —

Reserved Reserved 107 99 — — — —

Reserved Reserved 108 100 — — — —

Capture/Compare Timer1 _CCT1Interrupt 109 101 0000DEh IFS6[5] IEC6[5] IPC25[6:4]

Capture/Compare Timer2 _CCT2Interrupt 110 102 0000E0h IFS6[6] IEC6[6] IPC25[10:8]

Reserved Reserved 111 103 — — — —

Reserved Reserved 112 104 — — — —

Reserved Reserved 113 105 — — — —

FRC Self-Tuning Interrupt _FSTInterrupt 114 106 0000E8h IFS6[10] IEC6[10] IPC26[10:8]

Reserved Reserved 115 107 — — — —

ECC Single Bit Error _ECCInterrupt 116 108 0000ECh IFS6[12] IEC6[12] IPC27[2:0]

Reserved Reserved 117 109 — — — —

Real-Time Clock
Timestamp

Reserved Reserved 119 111 — — — —

Reserved Reserved 120 112 — — — —

Reserved Reserved 121 113 — — — —

Reserved Reserved 122 114 — — — —

Reserved Reserved 123 115 — — — —

Reserved Reserved 124 116 — — — —

JTAG _JTAGInterrupt 125 117 0000FEh IFS7[5] IEC7[5] IPC29[6:4]

MPLAB

_RTCCTSInterrupt 118 110 0000F0h IFS6[14] IEC6[14] IPC27[10:8]

XC16 ISR

Name

Vector #IRQ

#

IVT

Address

Interrupt Bit Location

Flag Enable Priority

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8.3 Interrupt Resources

Many useful resources are provided on the main prod­uct page of the Microchip website for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.

Note: In the event you are not able to access the

product page using the link above, enter
this URL in your browser:

http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en555464

8.3.1 KEY RESOURCES

• “Interrupts” (www.microchip.com/DS70000600)

in the “dsPIC33/PIC24 Family Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

•Webinars

• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections

• Development Tools

8.4 Interrupt Control and Status

Registers

PIC24FJ256GA705 family devices implement the
following registers for the interrupt controller:

• INTCON1

• INTCON2

• INTCON4

• IFS0 through IFS7

• IEC0 through IEC7

• IPC0 through ICP29

• INTTREG

8.4.1 INTCON1-INTCON4

Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.

The INTCON2 register controls global interrupt gener­ation, the external interrupt request signal behavior and
the use of the Alternate Interrupt Vector Table (AIVT).

The INTCON4 register contains the Software­Generated Hard Trap bit (SGHT) and ECC Double-Bit
Error (ECCDBE) trap.

8.4.2 IFSx

The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal, and
is cleared via software.

8.4.3 IECx

The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.

8.4.4 IPCx

The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.

8.4.5 INTTREG

The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number bits (VECNUM[7:0]) and Interrupt Priority
Level bits (ILR[3:0]) fields in the INTTREG register. The
new Interrupt Priority Level is the priority of the pending
interrupt.

The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 8-2. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0[0], the INT0IE bit in IEC0[0] and the INT0IPx
bits in the first position of IPC0 (IPC0[2:0]).

8.4.6 STATUS/CONTROL REGISTERS

Although these registers are not specifically part of
the interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt
functionality. For more information on these registers,
refer to “CPU with Extended Data Space (EDS)”
(www.microchip.com/DS39732) in the “dsPIC33/PIC24
Family Reference Manual”.

• The CPU STATUS Register, SR, contains the
IPL[2:0] bits (SR[7:5]). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.

• The CORCON register contains the IPL3 bit,
which together with the IPL[2:0] bits, also indi­cates the current CPU Interrupt Priority Level.
IPL3 is a read-only bit so that trap events cannot
be masked by the user software.

All Interrupt registers are described in Register 8-3
through Register 8-6 in the following pages.

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REGISTER 8-1: SR: ALU STATUS REGISTER

(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — DC

bit 15 bit 8

R/W-0

IPL2

(3)

(2)

R/W-0

IPL1

(2)

(3)

R/W-0

IPL0

(2)

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL[2:0]: CPU Interrupt Priority Level Status bits

(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 3-1.

2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt

Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are
disabled when IPL3 = 1.

3: The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.

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REGISTER 8-2: CORCON: CPU CORE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-1 U-0 U-0

— — — —IPL3

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-4 Unimplemented: Read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit

1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Not used as part of the interrupt module

bit 1-0 Unimplemented: Read as ‘0’

Note 1: For complete register details, see Register 3-2.

2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt

Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are
disabled when IPL3 = 1.

(2)

(2)

(1)

PSV — —

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REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

NSTDIS

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — — MATHERR ADDRERR STKERR OSCFAIL —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

bit 14-5 Unimplemented: Read as ‘0’

bit 4 MATHERR: Math Error Status bit

bit 3 ADDRERR: Address Error Trap Status bit

bit 2 STKERR: Stack Error Trap Status bit

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

bit 0 Unimplemented: Read as ‘0’

— — — — — — —

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled

1 = Math error trap has occurred
0 = Math error trap has not occurred

1 = Address error trap has occurred
0 = Address error trap has not occurred

1 = Stack error trap has occurred
0 = Stack error trap has not occurred

1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred

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REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1 R-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0

GIE DISI SWTRAP

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — INT4EP INT3EP INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 GIE: Global Interrupt Enable bit

1 = Interrupts and associated interrupt enable bits are enabled
0 = Interrupts are disabled, but traps are still enabled

bit 14 DISI: DISI Instruction Status bit

1 = DISI instruction is active
0 = DISI instruction is not active

bit 13 SWTRAP: Software Trap Status bit

1 = Software trap is enabled
0 = Software trap is disabled

bit 12-9 Unimplemented: Read as ‘0’

bit 8 AIVTEN: Alternate Interrupt Vector Table Enable bit

1 = Uses Alternate Interrupt Vector Table (if enabled in Configuration bits)
0 = Uses standard Interrupt Vector Table (default)

bit 7-5 Unimplemented: Read as ‘0’

bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge

bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge

bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge
0 = Interrupt on positive edge

— — — —AIVTEN

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REGISTER 8-5: INTCON4: INTERRUPT CONTROL REGISTER 4

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/C-0 R/C-0

— — — — — — ECCDBE SGHT

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’

bit 1 ECCDBE: ECC Double-Bit Error Trap bit

1 = ECC Double-Bit Error trap has occurred
0 = ECC Double-Bit Error trap has not occurred

bit 0 SGHT: Software-Generated Hard Trap Status bit

1 = Software-generated hard trap has occurred
0 = Software-generated hard trap has not occurred

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REGISTER 8-6: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0

CPUIRQ

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CPUIRQ: Interrupt Request from Interrupt Controller to CPU bit

bit 14 Unimplemented: Read as ‘0’

bit 13 VHOLD: Vector Number Capture Configuration bit

bit 12 Unimplemented: Read as ‘0’

bit 11-8 ILR[3:0]: New CPU Interrupt Priority Level bits

bit 7-0 VECNUM[7:0]: Vector Number of Pending Interrupt bits

—VHOLD— ILR3 ILR2 ILR1 ILR0

VECNUM[7:0]

1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens

when the CPU priority is higher than the interrupt priority

0 = No interrupt request is unacknowledged

1 = The VECNUMx bits contain the value of the highest priority pending interrupt
0 = The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt

that has occurred with higher priority than the CPU, even if other interrupts are pending)

1111 = CPU Interrupt Priority Level is 15

•

•

•

0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0

11111111 = 255, Reserved; do not use

•

•

•

00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000111 = 7, Reserved; do not use
00000110 = 6, Generic soft error trap
00000101 = 5, Reserved; do not use
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap

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PIC24FJ256GA705 Family

Secondary Oscillator

SOSCEN
Enable
Oscillator

SOSCO

SOSCI

WDT, Other Modules

OSCI

OSCO

Primary Oscillator

XT, HS, EC

CPU

Peripherals

RCDIV[2:0]

Timer, CCP, RTCC, CLC, WDT, PWRT

OSCFDIV

SOSC

Clock Control Logic

FSCM

DOZE[14:12]

CLKO

XTPLL, HSPLL

ECPLL,FRCPLL

PLL &

DIV

PLLMODE[3:0] CPDIV[1:0]

PLL

CCP

LPRC

FRC

DIV[14:0]

LPRC

Oscillator

FRC Divider

÷ n

Postscaler

WDT, RTCC, CLC

9.0 OSCILLATOR CONFIGURATION

• Software-Controllable Postscaler for Selective
Clocking of CPU for System Power Savings

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more
information, refer to “Oscillator”
(www.microchip.com/DS39700) in the

“dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet

• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown

• A Separate and Independently Configurable System
Clock Output for Synchronizing External Hardware

A simplified diagram of the oscillator system is shown
in Figure 9-1.

supersedes the information in the FRM.

The oscillator system for the PIC24FJ256GA705 family
devices has the following features:

• An On-Chip PLL Block to provide a Range of
Frequency Options for the System Clock

• Software-Controllable Switching between Various
Clock Sources

FIGURE 9-1: PIC24FJ256GA705 FAMILY CLOCK DIAGRAM

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9.1 CPU Clocking Scheme

The system clock source can be provided by one of
four sources:

• Primary Oscillator (POSC) on the OSCI and
OSCO pins

• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

The Primary Oscillator and FRC sources have the
option of using the internal PLL block, which can
generate a 4x, 6x or 8x PLL clock. If the PLL is used,
the PLL clocks can then be postscaled, if necessary,
and used as the system clock. Refer to Section 9.5

“Oscillator Modes” for additional information. The

internal FRC provides an 8 MHz clock source.

Each clock source (PRIPLL, FRCPLL, PRI, FRC,
LPRC and SOSC) can be used as an input to an
additional divider, which can then be used to produce a
divided clock source for use as a system clock
(OSCFDIV).

The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc­tion cycle clock, F
cycle clock is also denoted by F
instruction cycle clock, F
OSCO I/O pin for some operating modes of the Primary
Oscillator.

CY. In this document, the instruction

OSC/2. The internal

OSC/2, can be provided on the

9.2 Initial Configuration on POR

The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using Con­figuration bit settings. The Oscillator Configuration bit
settings are located in the Configuration registers in the
program memory (refer to Section 29.1 “Configura-

tion Bits” for further details). The Primary Oscillator

Configuration bits, POSCMD[1:0] (FOSC[1:0]), and the
Oscillator Select Configuration bits, FNOSC[2:0]
(FOSCSEL[2:0]), select the oscillator source that is used
at a Power-on Reset. The OSCFDIV clock source is the
default (unprogrammed) selection; the default input
source to the OSCFDIV divider is the FRC clock source.
Other oscillators may be chosen by programming these
bit locations.

The Configuration bits allow users to choose between
the various Clock modes shown in Table 9-1.

9.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS

The FCKSM[1:0] Configuration bits (FOSC[7:6]) are
used to jointly configure device clock switching and the
Fail-Safe Clock Monitor (FSCM). Clock switching is
enabled only when FCKSM1 is programmed (‘0’). The
FSCM is enabled only when FCKSM[1:0] are both
programmed (‘00’).

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TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD[1:0] FNOSC[2:0] Notes

Oscillator with Frequency Division
(OSCFDIV)

Low-Power RC Oscillator (LPRC) Internal 11 101 3

Secondary (Timer1) Oscillator
(SOSC)

Primary Oscillator (XT) with PLL
Module (XTPLL)

Primary Oscillator (EC) with PLL
Module (ECPLL)

Primary Oscillator (HS) Primary 10 010

Primary Oscillator (XT) Primary 01 010

Primary Oscillator (EC) Primary 00 010

Fast RC Oscillator with PLL Module
(FRCPLL)

Fast RC Oscillator (FRC) Internal 11 000 3

Note 1: The input oscillator to the OSCFDIV Clock mode is determined by the RCDIV[2:0] (CLKDIV[10:8) bits. At

POR, the default value selects the FRC module.

2: This is the default Oscillator mode for an unprogrammed (erased) device.
3: OSCO pin function is determined by the OSCIOFCN Configuration bit.

Internal/External 11 111 1, 2, 3

Secondary 11 100 3

Primary 01 011

Primary 00 011

Internal 11 001 3

9.3 Control Registers

The operation of the oscillator is controlled by five
Special Function Registers:

• OSCCON

•CLKDIV

•OSCTUN

• OSCDIV

•OSCFDIV

The OSCCON register (Register 9-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
OSCCON is protected by a write lock to prevent
inadvertent clock switches. See Section 9.4 “Clock

Switching Operation” for more information.

The CLKDIV register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscalers for the OSCFDIV Clock mode and the PLL
module.

The OSCTUN register (Register 9-3) allows the user to
fine-tune the FRC Oscillator over a range of
approximately ±1.5%.

The OSCDIV and OSCFDIV registers provide control
for the system oscillator frequency divider.

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REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R-x

(2)

R-x

(2)

R-x

(2)

U-0 R/W-x

(1)

(2)

R/W-x

(2)

R/W-x

(2)

— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0

bit 15 bit 8

R/W-0 R/W-0 R-0

CLKLOCK IOLOCK

(3)

(4)

LOCK — CF POSCEN SOSCEN OSWEN

U-0 R/CO-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0

Legend: CO = Clearable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’

bit 14-12 COSC[2:0]: Current Oscillator Selection bits

(2)

111 = Oscillator with Frequency Divider (OSCFDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)

bit 11 Unimplemented: Read as ‘0’

(2)

bit 10-8 NOSC[2:0]: New Oscillator Selection bits

111 = Oscillator with Frequency Divider (OSCFDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If FSCM is Enabled (FCKSM[1:0] =

00):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is Disabled (FCKSM[1:0] =

1x):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6 IOLOCK: I/O Lock Enable bit

(3)

1 = I/O lock is active
0 = I/O lock is not active

bit 5 LOCK: PLL Lock Status bit

(4)

1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

Note 1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock

Switching Operation” for more information.

2: Reset values for these bits are determined by the FNOSCx Configuration bits.
3: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
4: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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