Datasheet EMC1183 Datasheet

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Page 1

EMC1183

Internal

Temp Diode

Switching

Current

Analog

Mux

Internal

Temperature

Digital Mux

Limit Comparator

Low Limit Registers High Limit Registers

Conversion Rate Register

Interupt Masking

Status Registers

Configuration Register

SMBus Interface

THERM / ADDR

SMCLK SMDATA

DP1 DN1

GND

External

Temperature

ΔΣADC

THERM Limit Register

THERM Hysteresis Register

SMBus Address Decode

ALERT / THERM2

EMC1183

DP2 DN2

CPU /

GPU

EMC1183

Host

DP1 DN1

SMDATA

Thermal Junction

SMCLK

SMBus

Interface

THERM / ADDR

ALERT / THERM2

Power

Control

VDD

GND

VDD =

3.3V

1.8V

DN2

DP2

1.8V-3.3V

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

PRODUCT FEATURES

General Description

The EMC1183 is a high accuracy, low cost, 1.8V System Management Bus (SMBus) compatible temperature sensor. Advanced features such as Resistance Error Correction (REC), Beta Compensation (to support CPU diodes requiring the BJT/transistor model including 65nm and lower geometry processors) and automatic diode type detection combine to provide a robust solution for complex environmental monitoring applications. The ability to communicate at 1.8V SMBus levels provides compatible I/O for the advanced processors found in today’s tablet and smartphone applications.

The EMC1183 monitors three temperature channels (two external and one internal), providing ±1°C accuracy for both external and internal diode temperatures.

REC automatically eliminates the temperature error caused by series resistance allowing greater flexibility in routing thermal diodes. Frequency hopping* and analog filters ensure remote diode traces can be as far as eight (8) inches without degrading the signal. Beta Compensation eliminates temperature errors caused by low, variable beta transistors common in today's fine geometry processors. The automatic beta detection feature monitors the external diode/transistor and determines the optimum sensor settings for accurate temperature measurements regardless of processor technology. This frees the user from providing unique sensor configurations for each temperature monitoring application. These advanced featu res plus ±1°C measurement accuracy provide a low-cost, highly flexible and accurate solution for critical temperature monitoring applications.

Datasheet

Applications

 Notebook Computers  Desktop Computers  Industrial  Embedded applications

Features

 Programmable SMBus address  Support for diodes requiring the BJT/transistor model

— Supports 65nm and lower geometry CPU thermal

diodes

 Pin and register compatible with EMC1413  Automatically determines external diode type and

optimal settings

 R esistance Error Correction  Frequency hops the remote sample frequency to reject

DC converter and other coherent noise sources*

 Consecutive Alert queue to further reduce false Alerts  Up to 2 External Temperature Monitors

— 25°C typ, ±1°C max accuracy (20°C < T — 0.125°C resolution — Supports up to 2.2nF diode filter capacitor

 Internal Temperature Monitor

— ±1°C accuracy — 0.125°C resolution

 3.3V Supply Voltage  1.8V SMBus operation  Programmable temperature limits for ALERT/THERM2

(85°C default high limit and 0°C default low limit) and THERM

 Available in small 10-pin 3mm x 3mm DFN RoHS

(85°C default)

compliant package

DIODE

< 110°C)

* Technology covered under the US patent 7,193,543.

SMSC EMC1183 Revision 1.0 (07-11-13)

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Ordering Information:

ORDERING NUMBER PACKAGE FEATURES

SMBUS

ADDRESS

EMC1183-A-AIA-TR 10-pin DFN 3mm x 3mm

(RoHS compliant)

Up to three temperature sensors, ALERT/

THERM2

and THERM pins, programmable

SMBus address

This product meets the halogen maximum concentration values per IEC 61249-2-21

For RoHS compliance and environmental information, please visit www.smsc.com/rohs

Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines.

Selectable via

THERM

pull-up

Copyright © 2013 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustr ating typical applications. Conse quently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMS C reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGAR DLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRAC T; TORT; NEGLIGENCE OF SMSC OR OTHERS; ST RICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ES SENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE P OSSIBILITY OF SUCH DAMAGES.

Revision 1.0 (07-11-13) 2 SMSC EMC1183

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

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Table of Contents

Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 SMBus Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 4 System Management Bus Interface Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1.2 SMBus Address and RD / WR

4.1.3 THERM

4.1.5 SMBus Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1.6 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1.7 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.8 SMBus Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1.9 SMBus and I

4.2 SMBus Protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pin Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4 THERM

5.5 ALERT / THERM2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.6 Temperature Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.7 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.8 Consecutive Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.9 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.10 Temperature Measurement Results and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4.1 THERM

5.5.1 ALERT

5.5.2 ALERT

5.6.1 Beta Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6.2 Resistance Error Correction (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.6.3 Programmable External Diode Ideality Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pin Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

/ THERM2 Pin InterruptALERT Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

/ THERM2 Pin ComparatorTHERM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1 Data Read Interlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3 Status Register 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SMSC EMC1183 3 Revision 1.0 (07-11-13)

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

6.4 Configuration Register 03h / 09h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5 Conversion Rate Register 04h / 0Ah. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.6 Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7 Scratchpad Registers 11h and 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8 One Shot Register 0Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.9 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.10 External Diode Fault Register 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.11 Channel Mask Register 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.12 Consecutive ALERT Register 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.13 Beta Configuration Registers 25h and 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.14 External Diode Ideality Factor Registers 27h to 31h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.15 High Limit Status Register 35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.16 Low Limit Status Register 36h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.17 Therm Limit Status Register 37h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.18 Filter Control Register 40h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.19 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.20 SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.21 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Chapter 7 Typical Operating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.1 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision 1.0 (07-11-13) 4 SMSC EMC1183

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List of Figures

Figure 1.1 EMC1183 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.1 EMC1183 Pin Diagram, DFN-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.1 SMBus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4.4 Isolating the THERM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.1 System Diagram for EMC1183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5.2 Isolating THERM Figure 5.3 Isolating ALERT

Figure 5.4 Temperature Filter Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 5.5 Temperature Filter Impulse Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8.1 10-Pin DFN Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 8.2 10-Pin DFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 8.3 10 Pin DFN PCB Footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 8.4 EMC1183-A 10-Pin DFN Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

and SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SMSC EMC1183 5 Revision 1.0 (07-11-13)

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

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List of Tables

Table 2.1 EMC1183 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4.1 SMBus Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5.1 Supply Curr en t vs. Co nve r sion Rat e for EMC11 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5.2 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 6.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 6.4 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6.5 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6.6 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6.7 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6.8 Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 6.9 One Shot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6.10 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6.11 External Diode Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6.12 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 6.13 Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 6.14 Consecutive Alert / Therm Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 6.15 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 6.16 CPU Beta Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 6.17 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 6.18 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.19 Substrate Diode Ideality Factor Look- Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6.20 High Limit Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6.21 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6.22 Therm Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 6.23 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 6.24 FILTER Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 6.25 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 6.26 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 6.27 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision 1.0 (07-11-13) 6 SMSC EMC1183

DATASHEET

Page 7

Internal Temp

Diode

Switching

Current

Analog

Mux

Internal

Temperature Register

Digital Mux

Limit Comparator

Low Limit Registers

High Limit Registers

Conversion Rate Register

Interupt Masking

Status Registers

Configuration Register

SMBus Interface

THERM / ADDR

SMCLK

SMDATA

DP1 DN1

GND

External Temperature

ΔΣ ADC

THERM Limit Register

THERM Hysteresis Register

SMBus Address Decode

ALERT / THERM2

EMC1183

DP2 DN2

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Chapter 1 Block Diagram

Datasheet

Figure 1.1 EMC1183 Block Diagram

SMSC EMC1183 7 Revision 1.0 (07-11-13)

DATASHEET

Page 8

EMC1183

SMDATA

SMCLK

ALERT / THERM2

VDD

DP1

DN1

DN2

DP2 THERM / ADDR

GND

Exposed

pad

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Chapter 2 Pin Description

Figure 2.1 EMC1183 Pin Diagram, DFN-10

Table 2.1 EMC1183 Pin Description

PIN NUMBER NAME FUNCTION TYPE

1 VDD Power supply Power 2 DP1 External diode 1 positive (anode) connection AIO 3 DN1 External diode 1 negative (cathode) connection AIO

4DP2 / DN3

5 DN2 / DP3

6 GND Ground Power

Revision 1.0 (07-11-13) 8 SMSC EMC1183

7 THERM

8ALERT / THERM2

9SMDATA

/ ADDR

External diode 2 positive (anode) connection / External Diode 3 negative (cathode) connection for anti-parallel diodes

External diode 2 negative (cathode) connection / External Diode 3 positive (anode) connection for anti-parallel diodes

THERM - Critical THERM pull-up resistor

ADDR - Selects SMBus address based on pullup resistor

Active low digital ALERT output signal - requires pull-up resist

SMBus Data input/output - requires pull-up resistor

DATASHEET

output signal - requires

AIO

OD (5V)

DIOD (5V)

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

T able 2.1 EMC1183 Pin Description (continued)

PIN NUMBER NAME FUNCTION TYPE

10 SMCLK SMBus Clock input - requires pull-up resistor DI (5V)

Datasheet

Bottom Pad Exposed Pad

Not internally connected, but recommend grounding.

The pin types are described Table 2.2.

Ta ble 2.2 Pin Typ es

PIN TYPE DESCRIPTION

Power This pin is used to supply power or ground to the device.

AIO Analog Input / Output -This pin is used as an I/O for analog signals.

DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant.

DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as

an output, it is open drain and requires a pull-up resi stor. This pin is 5V tolerant.

OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and

requires a pull-up resistor. This pin is 5V tolerant.

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DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Chapter 3 Electrical Specifications

3.1 Absolute Maximum Ratings

Table 3.1 Abso lute Maximum Ratings

DESCRIPTION RATING UNIT

Supply Voltage (V Voltage on 5V tolerant pins (V Voltage on 5V tolerant pins (|V Voltage on any other pin to Ground -0.3 to V

) -0.3 to 4.0 V

) -0.3 to 5.5 V

5VT_pin

- VDD|) (see Note 3.1)0 to 3.6 V

5VT_pin

+0.3 V

Operating Temperature Range -40 to +125 °C Storage Temperature Range -55 to +150 °C Lead Temperature Range Refer to JEDEC Spec. J-STD-020 Package Thermal Characteristics for DFN-10

Thermal Resistance (θ

)77.1°C/W

j-a

ESD Rating, All pins HBM 2000 V

Note: Stresses at or above those listed could cause permanent damage to the device. This is a stress

rating only and functional operation of the device at any other conditio n above those indicated in the operation sections of this specification is not implied.

Note 3.1 For the 5V tolerant pins that have a pull-up resistor (SMCLK, SMDATA, THERM

ALERT

/ THERM2), the pull-up voltage must not exceed 3.6V when the device is

unpowered.

, and

3.2 Electrical Specifications

Table 3.2 Electrical Specifications

= 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN T YP MAX UNITS CONDITIONS

DC Power Supply Voltage V Supply Current I

Revision 1.0 (07-11-13) 10 SMSC EMC1183

3.0 3.3 3.6 V 200 410 µA 0.0625 conversion / sec, dynamic

averaging disabled

215 425 µA 1 conversion / sec, dynamic

averaging disabled

DATASHEET

Page 11

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Table 3.2 Electrical Specifications (co ntinu ed)

= 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS

Datasheet

325 465 µA 4 conversions / sec, dynamic

averaging disabled

890 1050 µA 4 conversions / sec, dynamic

averaging enabled

1120 µA > 16 conversions / sec, dynamic

averaging enabled

Standby Supply Current I

170 230 µA Device in Standby mode, no SMBus

communications, ALERT and THERM pins not asserted.

Internal Temperature Monitor

Temperature Accuracy ±0.25 ±1 °C -5°C < TA < 100°C

±2 °C -40°C < T

< 125°C

Temperature Resolution 0.125 °C

External Temperature Monitor

Temperature Accuracy ±0.25 ±1 °C +20°C < T

0°C < TA < 100°C

±0.5 ±2 °C -40°C < T

DIODE

< +110°C

< 127°C Temperature Resolution 0.125 °C Conversion Time all

Channels

CONV

150 ms default settings

Capacitive Filter C

Output Low Voltage V Leakage Current I

FILTER

LEAK

ALERT

0.4 V I

2.2 2.7 nF Connected across external diode

/ THERM2 and THERM pins

= 8mA

SINK

±5 µA ALERT / THERM2 and THERM

pins Device powered or unpowered TA < 85°C pull-up voltage < 3.6V

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DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

3.3 SMBus Electrical Characteristics

Table 3.3 SMBus Electrical Specifications

= 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS

SMBus Interface

Input High Voltage V

Input Low Voltage V

Leakage Current I

LEAK

1.4 V

V 5V Tolerant. Voltage threshold

-0.3 0.8 V 5V Tolerant. Voltage threshold

±5 µA Powered or unpowered

Hysteresis 50 mV Input Capacitance C Output Low Sink Current I

8.2 15 mA SMDATA = 0.4V

5pF

SMBus Timing Clock Frequency f Spike Suppression t Bus Free Time Stop to

Start Hold Time: Start t Setup Time: Start t Setup Time: Stop t Data Hold Time t Data Hold Time t Data Setup Time t Clock Low Period t Clock High Period t Clock/Data Fall time t Clock/Data Rise time t Capacitive Load C Timeout t

SMB

BUF

HD:STA

SU:STA

SU:STO

HD:DAT

SU:DAT

LOW

HIGH

FALL

RISE

LOAD

TIMEOUT

10 400 kHz

50 ns

1.3 µs

0.6 µs

0.6 µs 0 µs When transmitting to the master

0.3 µs When receiving from the master 100 ns

1.3 µs

0.6 µs 300 ns Min = 20+0.1C 300 ns Min = 20+0.1C 400 pF per bus line

25 35 ms Disabled by default

based on 1.8V operation

TA < 85°C

LOAD

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DATASHEET

Page 13

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

HIGH

LOW

HD:STA

SU:STO

HD:STA

HD:DAT

SU:DAT

SU:STA

FALL

RISE

Datasheet

Chapter 4 System Management Bus Interface Protocol

4.1 Communications Protocol

The EMC1183 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in

For the first 15ms after power-up the device may not respond to SMBus communications.

Figure 4.1.

Figure 4.1 SMBus Timing Diagram

4.1.1 SMBu s Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state.

4.1.2 SMBus Add ress and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, the SMBus Host is writing da ta to the client device. If this RD / WR bit is a logic ‘1’, the SMBus Host is reading data from the client device.

The EMC118 3-A and EMC1184-A SMBus slave addre ss is determined by the pull-up resistor on the THERM pin as shown in Table 4.1, "SMBus Address Decod e".

The Address decode is performed by pulling known currents from VDD through the external resistor causing the pin voltage to drop based on the respective curre nt / resistor relationship. This pin voltage is compared against a threshold that determines the value of the pull-up resisto r.

T able 4.1 SMBus Address Decode

PULL UP RESISTOR ON

THERM

PIN (±5%) SMBUS ADDRESS

4.7k 1 111_100(r/w

6.8k 1011_100(r/w

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DATASHEET

)b )b

Page 14

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

EMC1183

SMDATA

SMCLK

ALERT / THERM2

VDD

DP1

DN1

THERM / ADDR

GND

+3.3V

Shared Therm

22K

4.7K – 33k

+2.5 - 5V

5 6

DP2 / DN3

DN2 / DP3

Datasheet

Ta ble 4.1 SMBus Add ress Decode (continued)

PULL UP RESISTOR ON

THERM

PIN (±5%) SMBUS ADDRESS

10k 1001_100(r/w)b 15k 1101_100(r/w 22k 0011_100(r/w 33k 01 11_100(r/w

4.1.3 THERM Pin Considerations

Because of the decode method used to determine the SMBus Address, it is important that the pull-up resistance on the THERM pin be within the tolerances shown in Table 4.1. Additionally, the pull-up resistor on the THERM pin must be connected to the same 3.3V suppl y that drives the VDD pin.

For 15ms after power up, the THERM pin must not be pulled low or the SMBus address will not be decoded properly. If the system requirements do not permit these conditions, the THERM pin must be isolated from its hard-wired OR’d bus during this time.

One method of isolating this pin is shown in Figure 4.4, "Isolating the THERM pi n".

)b )b )b

Figure 4.4 Isolating the THERM

4.1.5 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.1.6 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the cl ient device pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the Write Byte protocol.

The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent.

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

4.1.7 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will rese t its client interface and prepare to receive further communications.

4.1.8 SMBus Timeout

Datasheet

The EMC1183 supports SMBus Timeout. If the clock line is held low for longer than t device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see

Section 6.12, "Consecutive ALERT Register 22h").

4.1.9 SMBus and I2C Compatibility

The EMC1183 is compatible with SMBus and I2C. The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the EMC1183 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I

1. EMC1183 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz.

2. Minimum frequency for SMBus communications is 10kHz.

3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the EMC1183 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout.

4. I2C devices do not support the Alert Response Address functionality (which is op tiona l for SMBus).

Attempting to communicate with the EMC1183 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other devices on the SMBus control the timing.

C Systems.

4.2 SMBus Protocols

The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address as valid protocols as shown below.

All of the below protocols use the convention in Table 4.1.

TIMEOUT

, the

Ta ble 4.1 Protocol Format

DATA SENT TO DEVICE

# of bits sent # of bits sent

SMSC EMC1183 15 Revision 1.0 (07-11-13)

DATASHEET

DATA SENT TO

THE HOST

Page 16

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

4.2.1 Write Byte

The Write Byte is used to write one byte of data to the registers, as shown in Table 4.2.

Table 4.2 Write Byte Protocol

START

SLAVE

ADDRESS WR

ACK

ADDRESS ACK

DATA ACK STOP

1 -> 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1

4.2.2 Read Byte

The Read Byte protocol is used to read one byte of data from the registers as show n in Table 4.3.

Table 4.3 Read Byte Protocol

START SLAVE

ADDRESS

1 -> 0 YYYY_

YYY

WR ACK REGISTER

ADDRESS

ACK START SLAVE

ADDRESS

0 0 XXh 0 1 -> 0 YYYY_

YYY

RD ACK REGISTER

DATA

NACK STOP

10 XX 10 -> 1

4.2.3 Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4.

Table 4.4 Send Byte Protocol

ADDRESS ACK STOP

START

SLA VE

ADDRESS WR

ACK

1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1

4.2.4 Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in

SLA VE

START

ADDRESS RD ACK REGISTER DATA NACK STOP

1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1

Revision 1.0 (07-11-13) 16 SMSC EMC1183

Table 4.5.

Table 4.5 Receive Byte Protocol

DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

4.3 Alert Response Address

The ALERT output can be used as a processor interrupt or as an SMBus Alert. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)

to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in

ALERT

RESPONSE

START

ADDRESS RD

1 -> 0 0001_100 1 0 YYYY_YYY 1 0 -> 1

The EMC1183 will respond to the ARA in the following way:

1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event).

2. Set the MASK_ALL bit to clear the ALERT pin.

Table 4.6.

Ta ble 4.6 Alert Respo nse Address Protocol

DEVICE

ACK

ADDRESS NACK STOP

Datasheet

APPLICATION NOTE: The ARA does not clear the Status Register and if the MASK_ALL bit is cleared prior to the

Status Register being cleared, the ALERT

pin will be reasserted.

SMSC EMC1183 17 Revision 1.0 (07-11-13)

DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

CPU / GPU

EMC1183

Host

DP1

DN1

SMDATA

Thermal Junction

SMCLK

SMBus

Interface

THERM / ADDR

ALERT / THERM2

Power Control

VDD

GND

VDD = 3.3V

1.8V – 3.3V

DN2

DP2

1.8V

Datasheet

Chapter 5 Product Description

The is an SMBus temperature sensor. The EMC1183 monitor one internal diode and up to two externally connected temperature diodes.

Thermal management is performed in cooperation with a host device. This consists of the host reading the temperature data of both the external and internal temperature diodes of the EMC 1183 and using that data to control the speed of one or more fans.

The EMC1183 has two levels of monitoring. The first provides a maskable ALERT / THERM2 signal to the host when the measured temperatures exceeds user programmable limits. This allows the EMC1183 to be used as an independent therma l watchdog to warn the host of temperature hot spots without direct control by the host. The second level of monitoring provides a non-maskable interrupt

THERM pin if the measured temperatures meet or exceed a second programmable l imit.

on the For the EMC1183, the External Diode 2 channel is compatible with any diode type.

Figure 5.1 shows a system level block diagram of the EMC1183.

Figure 5.1 System Diagram for EMC1183

5.1 Modes of Operation

The EMC1183 has two modes of operation.

 Active (Run) - In this mode of operation, the ADC is converting on all temperature cha nnels at the

programmed conversion rate. The temperature data is updated at the end of every conversion and the limits are checked. In Active mode, writing to the one-shot register will do nothing.

 Standby (Stop) - In this mode of operation, the majority o f circuitry is powered down to reduce

supply current. The temperature data is not updated and the limits are not checked. In this mode of operation, the SMBus is fully active and the part will return requested data. Writing to the oneshot register will enable the device to up date all temperature channels. Once al l the channels are updated, the device will return to the Standby mode.

Revision 1.0 (07-11-13) 18 SMSC EMC1183

DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

5.2 Conversion Rates

The EMC1183 may be configured for different conversion rates based on the system requirements. The conversion rate is configured as described in conversions per second. Other available conversion rates are shown in Table 6.6, "Conversion Rate".

5.3 Dynamic Averaging

Dynamic averaging causes the EMC1183 to measure the external diode channels for an extended time based on the selected conversion rate. This functionality can be disabled for increased power savings at the lower conversion rates (see averaging is enabled, the device will automatically adjust the samp ling and measurement time for the external diode channels. This allows the device to average 2x or 16x longer tha n the normal 11 bit operation (nominally 21ms per channel) while still maintaining the selected conversion rate. The benefits of dynamic averaging are improved noise rejection due to the longer integration time as well as less random variation of the temperature measurement.

When enabled, the dynamic averaging applies when a one-sh ot command is issued. The device will perform the desired averaging during the one-shot operation according to the selected conversion rate.

When enabled, the dynamic averaging will affect the average supply current based on the chosen conversion rate as shown in Table 5.1.

Datasheet

Section 6.5. The default conversion rate is 4

Section 6.4, "Configuration Register 03h / 09h"). When dynamic

Ta ble 5.1 Supp ly Curr ent vs. Conversion Rate for EMC1183

AVERAGE SUPPLY CURRENT

(TYPICAL)

ENABLED

CONVERSION RATE

1 / 16 sec 230uA 220uA 16x 1x

1 / 8 sec 275uA 220uA 16x 1x 1 / 4 sec 350uA 220uA 16x 1x 1 / 2 sec 405uA 220uA 16x 1x

1 / sec 480uA 250uA 8x 1x 2 / sec 850uA 290uA 4x 1x

4 / sec (default) 890uA 370uA 2x 1x

8 / sec 970uA 525uA 1x 1x 16 / sec 990uA 690uA 0.5x 0.5x 32 / sec 1030uA 1050uA 0.25x 0.25x 64 / sec 1500uA 1100uA 0.125x 0.125x

(DEFAULT) DISABLED

AVERAGING FACTOR (BASED ON

11-BIT OPERATION)

ENABLED

(DEFAULT) DISABLED

5.4 THERM Output

The THERM output is asserted indepe ndently of the ALERT output and cannot be masked. Whenever any of the measured temperatures exceed the user programmed Therm Limit values for the programmed number of consecutive measurements, the

SMSC EMC1183 19 Revision 1.0 (07-11-13)

DATASHEET

THERM output is asserted. Once it has been

Page 20

Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

EMC1183

9 8 7

SMDATA

SMCLK

1 2 3 4

ALERT

VDD

DP1

DN1

THERM / ADDR GND

+3.3V

Shared THERM

4.7K 33

+2.5 - 5V

5 6

DP2

DN2

Datasheet

asserted, it will remain asserted until all measured temperatures drop below the Therm Limit minus the Therm Hysteresis (also programmable).

When the THERM pin is asserted, the THERM status bits will likewise be set. Reading these bits will not clear them until the status bits will be automatically cleared.

THERM pin is deasserted. Once the THERM pin is deasserted, the THERM

5.4.1 THERM Pin Considerations

Because of the decode method used to determine the SMBus Address, it is important that the pull-up resistance on THERM pin be within ±10% tolerance. Addi tionally, the pull-up resistor on the THERM pin must be connected to the same 3.3V supply that drives the VDD pi n.

For 15ms after power up, the THERM pin must not be pulled low or the SMBus Address will not be decoded properly. If the system requirements do not permit these conditions, the isolated from the bus during this time. One method of isolating this pin is shown in Figure 5.2.

THERM pin must be

5.5 ALERT / THERM2 Output

5.5.1 ALERT / THERM2 Pin InterruptALERT Mode

Revision 1.0 (07-11-13) 20 SMSC EMC1183

Figure 5.2 Isolating THERM Pin

The ALERT / THERM2 pin is an open dr ain output and requires a pull-up resistor to VDD and has two modes of operation: interrupt mode and comparator mode. The mode of the ALERT / THERM2 output is selected via the ALERT / COMPALERT/THERM bit in the Configuration Register (see

When configured to operate in interru pt mode, the ALERT / THERM2 pin asserts low when an out of limit measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected, functioning as any standard asserted as long as an out-of-limit condition remains. Once the out-of-limit condition has been removed, the

The ALERT/ THERM2 pin can be masked by setting the MASK_ALL bit. Once the ALERT / THERM2 pin has been masked, it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any interrupt conditions that occur while the the Status Register normally. There are also individual channel masks (see

The ALERT / THERM2 pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave to communicate an error condition to the master. One or more ALERT / THERM2 outputs can be hard-wired together.

ALERT / THERM2 pin will remain asserted until the appropri ate status bits are cleared.

ALERT in on the SMBus. The ALERT / THERM2 pin will remain

ALERT / THERM2 pin is masked will update

Section 6.11).

DATASHEET

Section 6.4).

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

5.5.2 ALERT / THERM2 Pin ComparatorTHERM Mode

When the ALERT / THERM2 pin is configured to operate in comparator mode, it will be asserted if any of the measured temperatures exceeds the respective high limit, acting as a second in. The high limit minus the Therm Hysteresis value.

When the ALERT / THERM2 pin is asserted in comparator mode, the corresponding high limit status bits will be set. Reading these bits will not clear them until the Once the ALERT pin is deasserted, the status bits will be automatically cleared.

The MASK_ALL bit will not block the ALERT / THERM2 pin in this mode; however, the individual channel masks (see Section 6.11) will prevent the respective channel from asserting the ALERT/ THERM2 pin.

ALERT / THERM2 pin will remain asserted until all temperatures drop below the corresponding

ALERT / THERM2 pin is deasserted.

5.6 Temperature Measurement

The EMC1183 can monitor the temperature of up to externally connected diodes. The device contains programmable High, Low, and Therm limits for all measured temperature

channels. If the measured temperature goes below the Lo w limit or above the High limit, the ALERT pin can be asserted (based on user settings). If the measured temperature meets or exceeds the Therm Limit, the THERM pin is asserted unconditionally, providing two tiers of temperature detection.

Datasheet

THERM function

5.6.1 Beta Compensation

The EMC1183 is configured to monitor the temperature of basic diodes (e.g., 2N3904) or CPU thermal diodes. It automatically detects the type of external diode (CPU diode or d iode connected transistor) and determines the optimal setting to reduce temperature errors introduced by beta variation. Compensating for this error is also known as implementing the transistor or BJT model for temperature measurement.

For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contri bute approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.

5.6.2 Resistance Error Correction (REC)

Parasitic resistance in series with the external diodes will limit the accuracy obtainable from temperature measurement devices. The voltage developed across this resistance by the switching diode currents cause the temperature measurement to read higher than the true temperature. Contributors to series resistance are PCB trace resistance, on die (i.e. on the processor) metal resistance, bulk resistance in the base and emitter of the temperature transisto r. Typically, the error caused by series resistance is +0.7°C per ohm. The EMC1183 automatically corrects up to 100 ohms of series resistance.

5.6.3 Programmable External Diode Ideality Factor

The EMC1183 is designed for external diodes with an ideality factor of 1.008. Not all external diodes, processor or discrete, will have this exact value. This variation of the ideal ity factor introduces error in the temperature measurement which must be corrected for. This correction is typically done using programmable offset registers. Since an ideality factor mismatch introduces an error that is a function of temperature, this correction is only accurate within a small range of temperatures. To provide

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

maximum flexibility to the user, the EMC1183 provides a 6-bit reg ister for each external diode where the ideality factor of the diode used is programmed to eliminate errors across all temperatures.

APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the

Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most ideality errors.

5.7 Diode Faults

The EMC1183 detects an open on the DP and DN pins, and a short across the DP and DN pins. For each temperature measurement made, the device checks for a diode fault on the external diode channel(s). When a diode fault is detected, the

Section 5.8) and the temperature data reads 00h in the MSB and LSB registers (note: the low limi t will

not be checked). A diode fault is defined as one of the followin g: an open betwee n DP and DN, a sho rt from VDD to DP, or a short from VDD to DN.

If a short occurs across DP and DN or a short occurs from DP to GND, the low limit status bit is set and the ALERT / THERM2 pin asserts (unless masked). This condition is indistinguishable from a temperature measurement of 0.000°C (-64°C in extended ran ge) resulting in temperature data of 00h in the MSB and LSB registers.

If a short from DN to GND occurs (with a diode connected), temperature measurements will continue as normal with no alerts.

ALERT / THERM2 pin asserts (unless masked, see

5.8 Consecutive Alerts

The EMC1183 contain multiple consecutive alert counters. One set of counters applies to the ALERT / THERM2 pin and the second set of counters applies to the THERM pin. Each temperature measurement channel has a separate consecutive alert counter for each of the THERM pins. All counters are user programmable and determine the number of consecutive measurements that a temperature channel(s) must be out-of-limi t or reporting a diode fault before the corresponding pin is asserted.

See Section 6.12, "Consecutive ALERT Register 22h" for more details on the consecutive alert function.

5.9 Digital Filter

To reduce the effect of noise and temperature spikes on the reported temperat ure, the External Diode 1 channel uses a programmable digital filter. This filter can be configured as Level 1, Level 2, or Disabled (default) (see

Figure 5.5.

Section 6.18). The typical filter performance is shown in Figure 5.4 and

ALERT / THERM2 and

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Filter Step Response

02468101214

Samples

Temperature (C)

Disabled

Level1

Level2

Filter Impulse Response

02468101214

Samples

Temperatu r e (C)

Disabled

Level1

Level2

Datasheet

Figure 5.4 Temperature Filter Step Response

SMSC EMC1183 23 Revision 1.0 (07-11-13)

Figure 5.5 Temperature Filter Impulse Response

DATASHEET

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

5.10 Temperature Measurement Results an d Data

The temperature measurement results are stored in the internal and external temperature registers. These are then compared with the values stored in the hi gh and low limit registers. Both external and internal temperature measurements are stored in 11-bit format with the eight (8) most significant bits stored in a high byte register and the three (3) least significant bits stored in the three (3) MSB positions of the low byte register. All other bits of the low byte register are set to zero.

The EMC1183 has two selectable temperature ranges. The default range is from 0°C to +127°C and the temperature is represented as binary number able to report a temper ature from 0°C to +127 .875°C in 0.125°C steps.

The extended range is an extended temperature ran ge from -64°C to +191°C. The data format is a binary number offset by 64°C. The extended range is used to measure temperature diodes with a la rge known offset (such as AMD processor diodes) where the diode temperature plus the offset would be equivalent to a temperature higher than +127°C.

Table 5.2 shows the default and extended range formats.

Table 5.2 Temperature Data Format

TEMPERATURE (°C) DEFAULT RANGE 0°C TO 127°C EXTENDED RANGE -64°C TO 191°C

Diode Fault 000 0000 0000 000 0000 0000

-64 000 0000 0000 000 0000 0000

-1 000 0000 0000 001 1111 1000 0 000 0000 0000 010 0000 0000

0.125 000 0000 0001 010 0000 0001 1 000 0000 1000 010 0000 1000 64 010 0000 0000 100 0000 0000 65 010 0000 1000 100 0000 1000 127 011 1111 1000 101 1111 1000 12 7 . 8 7 5 011 1111 1111 1 01 1111 1111 128 011 1111 1111 110 0000 0000 190 011 1111 1111 111 1111 0000 191 011 1111 1111 111 1111 1000 >= 1 9 1 . 8 7 5 0 11 1111 1111 111 1111 1111

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Chapter 6 Register Description

The registers shown in Table 6.1 are accessible through the SMBus. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’.

Table 6.1 Register Set in Hexad ecimal Ord er

Datasheet

ADDRESS R/W REGISTER NAME FUNCTION

00h R

01h R

02h R Status

03h R/W Configuration

04h R/W Conversion Rate

05h R/W

06h R/W

07h R/W

Internal Diode Data

High Byte

External Diode 1

Data High Byte

Internal Diode High

Limit

Internal Diode Low

Limit

External Diode 1

High Limit High Byte

Stores the integer data for the

Internal Diode

Stores the integer data for External

Diode 1

Stores the status bits for the

Internal Diode and External Diodes

Controls the general operation of

the device (mirrored at address

09h)

Controls the conversion rate for

updating temperature data

(mirrored at address 0Ah)

Stores the 8-bit high limit for the

Internal Diode (mirrored at address

0Bh)

Stores the 8-bit low limit for the

Internal Diode (mirrored at address

0Ch)

Stores the integer portion of the

high limit for External Diode 1

(mirrored at register 0Dh)

DEFAULT

VALUE PAGE

00h

Page 28

00h

00h Page 28

00h Page 29

06h

(4/sec)

55h

(85°C)

00h

(0°C)

55h

(85°C)

Page 30

Page 31

08h R/W

09h R/W Configuration

0Ah R/W Conversion Rate

SMSC EMC1183 25 Revision 1.0 (07-11-13)

External Diode 1 Low

Limit High Byte

Stores the integer portion of the

low limit for External Diode 1

(mirrored at register 0Eh)

Controls the general operation of

the device (mirrored at address

03h)

Controls the conversion rate for

updating temperature data

(mirrored at address 04h)

DATASHEET

00h

(0°C)

00h

06h

(4/sec)

Page 29

Page 30

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Tabl e 6.1 Register Set in Hexadecimal Order (continued)

ADDRESS R/W REGISTER NAME FUNCTION

0Bh R/W

0Ch R/W

0Dh R/W

0Eh R/W

Internal Diode High

Limit

Internal Diode Low

Limit

External Diode 1

High Limit High Byte

External Diode 1 Low

Limit High Byte

0Fh W One Shot

10h R

External Diode 1

Data Low Byte

11h R/W Scratchpad

12h R/W Scratchpad

Stores the 8-bit high limit for the

Internal Diode (mirrored at address

05h)

Stores the 8-bit low limit for the

Internal Diode (mirrored at address

06h)

Stores the integer portion of the

high limit for External Diode 1

(mirrored at register 07h)

Stores the integer portion of the

low limit for External Diode 1

(mirrored at register 08h)

A write to this register initiates a

one shot update.

Stores the fractional data for

External Diode 1

Scratchpad register for software

compatibility

Scratchpad register for software

compatibility

DEFAULT

VALUE PAGE

55h

(85°C)

00h

(0°C)

Page 31

55h

(85°C)

00h

(0°C)

00h Page 33

00h Page 28

00h Page 32

13h R/W

14h R/W

15h R/W

16h R/W

17h R/W

18h R/W

19h R/W

1Ah R/W

External Diode 1

High Limit Low Byte

External Diode 1 Low

Limit Low Byte

External Diode 2

High Limit High Byte

External DIode 2 Low

Limit High Byte

External Diode 2

High Limit Low Byte

External Diode 2 Low

Limit Low Byte

External Diode 1

Therm Limit

External Diode 2

Therm Limit

1Bh R-C External Diode Fault

1Fh R/W

Channel Mask

Stores the fractional portion of the

high limit for External Diode 1

Stores the fractional portion of the

low limit for External Diode 1

Stores the integer portion of the

high limit for External Diode 2

Stores the integer portion of the

low limit for External Diode 2

Stores the fractional portion of the

high limit External Diode 2

Stores the fractional portion of the

low limit for External Diode 2

Stores the 8-bit critical temperature

limit for External Diode 1

Stores the 8-bit critical temperature

limit for External Diode 2

Stores status bits indicating which

external diode detected a diode

fault

Controls the masking of individual

channels

00h

Page 31

00h

55h

(85°C)

Page 31

00h

(0°C)

00h

Page 31

00h

55h

(85°C)

55h

(85°C)

Page 33

00h Page 33

00h Page 34

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Tabl e 6.1 Register Set in Hexadecimal Order (continued)

ADDRESS R/W REGISTER NAME FUNCTION

20h R/W

21h R/W Therm Hysteresis

22h R/W Consecutive ALERT

23h R

24h R

25h R/W

26h R/W

27h R/W

Internal Diode Therm

Limit

External Diode 2

Data High Byte

External Diode 2

Data Low Byte

External Diode 1

Beta Configuration

External Diode 2

Beta Configuration

External Diode 1

Ideality Factor

Stores the 8-bit critical temperature

limit for the Internal Diode

Stores the 8-bit hysteresis value

that applies to all Therm limits

Controls the number of out-of-limit

conditions that must occur before

an interrupt is asserted

Stores the integer data for External

Diode 2

Stores the fractional data for

External Diode 2

Stores the Beta Compensation

circuitry settings for External Diode

Stores the Beta Compensation

circuitry settings for External Diode

Stores the ideality factor for

External Diode 1

DEFAULT

VALUE PAGE

55h

(85°C

0Ah

(10°C)

70h Page 34

00h

08h Page 37

08h

(EMC1183)

07h

12h

(1.008)

Page 33

Page 28

Page 37

28h R/W

29h R

35h R-C High Limit Status Status bits for the High Limits 00h Page 39 36h R-C Low Limit Status Status bits for the Low Limits 00h Page 39 37h R Therm Limit Status Status bits for the Therm Limits 00h Page 40

40h R/W Filter Control

FDh R

FEh R Manufacturer ID

FFh R Revision

External Diode 2

Ideality Factor

Internal Diode Data

Low Byte

Product ID

(EMC1 183)

Stores the ideality factor for

External Diode 2

Stores the fractional data for the

Internal Diode

Controls the digital filter setting for

the External Diode 1 channel

Stores a fixed value that identifies

the device

Stores a fixed value that

represents SMSC

Stores a fixed value that

represents the revision number

12h

(1.008)

00h Page 28

00h Page 40

21h Page 41

5Dh Page 41

07h Page 42

6.1 Data Read Interlock

When any temperature channel high byte register is read, the correspo nding low byte is copied into an internal ‘shadow’ register. The user is free to read the low byte at any time an d be guaranteed that

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Datasheet

it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading from the same high byte register again will automa tically refresh this stored low byte data.

6.2 Temperature Data Registers

T able 6.2 Temperature Data Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

00h R

29h R

01h R

10h R

23h R

24h R

2Ah R

2Bh R

As shown in Table 6.2, all temperature s are stored as an 11-bit value with the high byte representing the integer value and the low byte representing the fracti onal value left justified to occupy the MSBits.

Internal Diode

High Byte

Internal Diode

Low Byte

External Diode

1 High Byte

External Diode

1 Low Byte

External Diode

2 High Byte

External Diode

2 Low Byte

External Diode

3 High Byte

External Diode

3 Low Byte

128 64 32 16 8 4 2 1 00h

0.5 0.25 0.125 - - - - - 00h

128 64 32 16 8 4 2 1 00h

0.5 0.25 0.125 - - - - - 00h

128 64 32 16 8 4 2 1 00h

0.5 0.25 0.125 - - - - - 00h

128 64 32 16 8 4 2 1 00h

0.5 0.25 0.125 - - - - - 00h

6.3 Status Register 02h

Table 6.3 Status Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

02h R Status BUSY - - HIGH LOW FAULT THERM - 00h

The Status Register reports general error conditions. To identify specific channels, refer to

Section 6.10, Section 6.15, Section 6.16, and Section 6.17. The individual Status Register bits are

cleared when the appropriate High Limit, Low Limit, or Therm Limit register has been read or cle ared. Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either

ALERT / THERM2 or THERM pin to be asserted.

the Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.

See the High Limit Status Register for specific channel information (Section 6.15). When set, this bit will assert the ALERT / THERM2 pin.

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Datasheet

Bit 3 - LOW - This bit is set when any of the temperature channels dro ps below its programmed low limit. See the Low Limit Status Register for specific channel information (Section 6.16). When set, this bit will assert the ALERT / THERM2 pin.

Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode channels. See the External Diode Fault Register for specific channel information (

Section 6.10). When

set, this bit will assert the ALERT / THERM2 pin. Bit 1 - THERM - This bit is set when the any of the temperature chan nels exceeds its programmed

Therm Limit. See the Therm Limit Status Register for specific channel information (

Section 6.17).

When set, this bit will assert the THERM pin.

6.4 Configuration Register 03h / 09h

Ta ble 6.4 Configu ration Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

03h 09h

R/W Configuration

The Configuration Register controls the basic operation of the devic e. This register is fully accessible at either address.

Bit 7 - MASK_ALL - Masks the ALERT / THERM2 pin from asserting.

 ‘0’ - (default) - The ALERT / THERM2 pin is not masked. If any of the appropriate status bits are

set the ALERT

 ‘1’ - The ALERT/ THERM2 pin is masked. It will not be asserted for any interrupt condition unless

it is configured in comparator mode. The Status Registers will be updated normally.

Bit 5 - ALERT/THERM2 - Controls the operation of the ALERT / THERM2 pin.

 ‘0’ (default) - The ALERT / THERM2 acts as an Alert pin and has interrupt behavior as described

in Section 5.5.1.

 ‘1’ - The ALERT / THERM2 acts as a THERM pin and has comparator behavior as described in

Section 5.5.2. In this mode the MASK_ALL bit is ignored.

Bit 4 - RECD1 - Disables the Resistance Error Correction (REC) for External Diode 1.

 ‘0’ (default) - REC is enabled for External Diode 1.  ‘1’ - REC is disabled for External Diode 1.

Bit 3 - RECD2 - Disables the Resistance Error Correction (REC) for External Diode 2 and External Diode 3.

 ‘0’ (default) - REC is enabled for External Diode 2 and External Diode 3.  ‘1’ - REC is disabled for External Diode 2 and External Diode 3.

Bit 2 - RANGE - Configures the measurement range and data format of the temperature channels.

 ‘0’ (default) - The temperature measurement range is 0°C to +127.875°C and the data format is

binary.

 ‘1’ -The temperature measurement range is -64°C to +191.875°C and th e data format is offset

binary (see Table 5.2).

Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.

MASK_

ALL

-ALERT THERM2

/ THERM2 pin will be asserted.

RECD1 RECD2 RANGE

DAVG_

DIS

APDD 00h

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

 ‘0’ (default) - The dynamic averag ing feature is enabled. All temperature channels will be converted

with an averaging factor that is based on the conversion rate as shown in Table 6.6.

 ‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a

maximum averaging factor of 1x (equivalent to 11-bit conversion). For higher conversion rates, this averaging factor will be reduced as shown in Table 6.6.

6.5 Conversion Rate Register 04h / 0Ah

Tabl e 6.5 Conversion Rate Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

04h

R/W

0Ah

Conversion

Rate

- - - - CONV[3:0]

06h

(4/sec)

The Conversion Rate Register controls how often the temperature measurement cha nnels are updated and compared against the limits. This register is fully accessible at either address.

Bits 3-0 - CONV[3:0] - Determines the conversion rate as shown in Table 6.6.

Table 6.6 Conversion Rate

CONV[3:0]

CONVERSIONS / SECONDHEX 3 2 1 0

0h 0 0 0 0 1 / 16 1h 0 0 0 1 1 / 8 2h 0 0 1 0 1 / 4 3h 0 0 1 1 1 / 2 4h 0 1 0 0 1 5h 0 1 0 1 2 6h 0 1 1 0 4 (de fault) 7h 0 1 1 1 8 8h 1 0 0 0 16 9h 1 0 0 1 32 Ah 1 0 1 0 64

Bh - Fh All others 1

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6.6 Limit Registers

Table 6.7 Temperature Limit Registers

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

05h

R/W

0Bh 06h

R/W

0Ch 07h

R/W

0Dh

13h R/W

08h

R/W

0Eh

14h R/W

15h R/W

Internal Diode

High Limit

Internal Diode

Low Limit

External

Diode 1 High

Limit High

Byte

External

Diode 1 High

Limit Low

Byte

External

Diode 1 Low

Limit High

Byte

External

Diode 1 Low

Limit Low

Byte

External

Diode 2 High

Limit High

Byte

128643216 8 421

0.5 0.25 0.125 - - - - - 00h

128643216 8 421

0.5 0.25 0.125 - - - - - 00h

128643216 8 421

55h

(85°C)

00h

(0°C)

55h

(85°C)

00h

(0°C)

55h

(85°C)

External

16h R/W

17h R/W

18h R/W

2Ch R/W

SMSC EMC1183 31 Revision 1.0 (07-11-13)

Diode 2 Low

Limit High

Byte

External

Diode 2 High

Limit Low

Byte

External

Diode 2 Low

Limit Low

Byte

External

Diode 3 High

Limit High

Byte

128643216 8 421

0.5 0.25 0.125 - - - - - 00h

128643216 8 421

DATASHEET

00h

(0°C)

55h

(85°C)

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Triple Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

Tabl e 6.7 Tempe rature Limit Registers (continued)

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

External

2Dh R/W

Diode 3 Low

Limit High

128643216 8 421

(0°C)

Byte

External

2Eh R/W

Diode 3 High

Limit Low

0.5 0.25 0.125 - - - - - 00h

Byte

External

2Fh R/W

Diode 3 Low

Limit Low

0.5 0.25 0.125 - - - - - 00h

Byte

The device contains both high and low limi ts for all temperature channels. If the measured temp erature exceeds the high limit, then the corresponding status bit is set and the ALERT / THERM2 pin is asserted. Likewise, if the measured temperature is less than or equal to the low limit, the corresponding status bit is set and the

ALERT / THERM2 pin is asserted.

The data format for the limits must match the selected data format for the temperature so that if the extended temperature range is used, the limits must be programmed in the extended data format.

The limit registers with multiple addresses are fully accessible at eith er address. When the device is in Standby mode, updating the limit registers will have no effect until the next

conversion cycle occurs. This can be initiated via a write to the One Shot Register (see Section 6.8,

"One Shot Register 0Fh") or by clearing the RUN / STOP bit (see Secti on 6.4, "Configuration Register 03h / 09h").

00h

6.7 Scratchpad Registers 11h and 12h

Table 6.8 Scratchpad Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

11h R/W Scratchpad 7 6 5 4 3 2 1 0 00h

12h R/W Scratchpad 7 6 5 4 3 2 1 0 00h

The Scratchpad Registers are Read / Write registers that are used for place holders to be software compatible with legacy programs. Reading from the registers will return what is written to them.

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6.8 One Shot Register 0Fh

Table 6.9 One Shot Regis ter

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

0Fh W One Shot

The One Shot Register is used to initiate a one shot comman d. Writing to the one shot register when the device is in Standby mode and BUSY bit (in Status Register) is ‘0’, will immediate ly cause the ADC to update all temperature measurements. Writing to the One Shot Register while the device is in Active mode will have no effect.

Writing to this register initiates a single conversion cycle. Data

is not stored and always reads 00h

00h

6.9 Therm Limit Registers

Ta ble 6.10 Th erm Limit Registers

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

19h R/W

1Ah R/W

20h R/W

21h R/W

External Diode 1

Therm Limit

External Diode 2

Therm Limit

Internal Diode

Therm Limit

Therm

Hysteresis

128 64 32 16 8 4 2 1

55h

(85°C)

55h

(85°C)

55h

(85°C)

0Ah

(10°C)

The Therm Limit Registers are used to determine wheth er a critical thermal event has occurred. If the measured temperature exceeds the Therm Limit, the match the chosen data format of the temperature reading registers.

Unlike the ALERT / THERM2 pin, the THERM pin cannot be masked. Additionally, the THERM pin will be released once the temperature drops below the corresponding threshold minus the Therm Hysteresis.

THERM pin is asserted. The limit setting must

6.10 External Diode Fault Register 1Bh

Table 6.11 External Diode Fault Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

1Bh R-C

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External

Diode Fault

---- E2FLTE1FLT-00h

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The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the Status Register to be set. This register is cleared when it is read.

Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault. Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.

6.11 Channel Mask Register 1Fh

Table 6.1 2 Channel Mask Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

1Fh R/W

Channel

Mask

---- -

MASK

INT

MASK

00h

The Channel Mask Register controls individual channel masking. When a channel is masked, the ALERT / THERM2 pin will not be asserted when the masked channel reads a diode fault or out of limit error. The channel mask does not mask the

THERM pin.

Bit 2 - E2MASK - Masks the ALERT pin from asserting when the External Diode 2 channel is out of limit or reports a diode fault.

 ‘0’ (default) - The External Diode 2 channel will cause the ALERT / THERM2pin to be asserted if

it is out of limit or reports a diode fault.

 ‘1’ - The External Diode 2 channel will not cause the ALERT / THERM2 pin to be asserted if it is

out of limit or reports a diode fault.

Bit 1 - E1MASK - Masks the ALERT / THERM2 pin from asserting when the External Diode 1 channel is out of limit or reports a diode fault.

 ‘0’ (default) - The External Diode 1 channel will cause the ALERT / THERM2 pin to be asserted if

it is out of limit or reports a diode fault.

 ‘1’ - The External Diode 1 channel will not cause the ALERT / THERM2 pin to be asserted if it is

out of limit or reports a diode fault.

Bit 0 - INTMASK - Masks the ALERT / THERM2 pin from asserting when the Internal Diode temperature is out of limit.

 ‘0’ (default) - The Internal Diode channel will cause the ALERT / THERM2 pin to be asserted if it

is out of limit.

 ‘1’ - The Internal Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out

of limit.

6.12 Consecutive ALERT Register 22h

Table 6.13 Consecutive ALERT Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

22h R/W

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Consecutive

ALERT

TIME

OUT

CTHRM[2:0] CALRT[2:0] - 70h

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The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must be detected in consecutive measurements before the ALERT / THERM2 or THERM pin is asserted. Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.

An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in consecutive measurements will increment the consecutive alert counter. The counters will also be reset if no out-of-limit condition or diode fault conditio n occurs in a consecutive reading.

When the ALERT / THERM2 pin is configured as an interrupt, when the consecutive alert counter reaches its programmed value, the following will occur: the STATUS bit(s) for that chan nel and the last error condition(s) (i.e. E1HIGH, or E2LOW and/or E2FAULT) will be set to ‘1’, the

ALERT / THERM2

pin will be asserted, the consecutive alert counter will be cleared, and measurements will continue. When the ALERT / THERM2 pin is configured as a comparator, the consecutive alert counter will

ignore diode fault and low limit errors and only increment if the measured temperature exceeds the High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the

ALERT/ THERM2 pin will be asserted, but the counter will not be reset. It will remain set until the temperature drops below the High Limit minus the Therm Hysteresis value.

For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1183 device, the high limits are set at 70°C, and none of the channels are masked, the ALERT / THERM2 pin will be asserted after the following four measurements:

1. Internal Diode reads 71°C and external diodes read 69°C. Consecutive alert counter for INT is

incremented to 1.

2. Both the Internal Diode and External Diode 1 read 71°C and External Diode 2 reads 68°C.

Consecutive alert counter for INT is incremented to 2 and for EXT1 i s set to 1.

3. The External Diode 1 reads 71°C and both the Internal Diode and External Diode 2 read 69°C.

Consecutive alert counters for INT and EXT2 are cleared and EXT1 is incremented to 2.

4. The Internal Diode reads 71°C and external diodes read 71°C. Consecutive alert coun ter for INT

is set to 1, EXT2 is set to 1, and EXT1 is incremented to 3.

5. The Internal Diode reads 71°C and both the external diodes read 71°C. Consecutive alert counter

for INT is incremented to 2, EXT2 is set to 2, and EXT1 is incremented to 4. The appropriate status bits are set for EXT1 and the

ALERT / THERM2 pin is asserted. EXT1 counter is reset to 0 and

all other counters hold the last value until the next temperature measurement.

Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.

 ‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low in definitely

without the device resetting its SMBus protocol.

 ‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than t

TIMEOUT

the device will reset the SMBus protocol.

Once the SYS_SHDN pin is asserted, the consecutive Therm counter will not reset until the corresponding temperature drops below the appropriate limit minus the correspond ing hysteresis.

Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must e xceed the corresponding Therm Limit before the THERM pin is asserted. All temperature channels use this value to set the respective counters. The consecutive Therm counter is incremented whenever any measurement exceed the corresponding Therm Limit.

If the temperature drops below the Therm Limit, the counter is reset. If a number of consecutive measurements above the Therm Limit occurs, the THERM pin is asserted low.

Once the THERM pin has been asserted, the consecutive therm counter will not reset until the corresponding temperature drops below the Therm Limit minus the Therm Hysteresis value.

The bits are decoded as shown in Table 6.14. The default setting is 4 consecutive out of limit conversions.

Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of limit condition or diode fault before the

ALERT / THERM2 pin is asserted. All temperature channels

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use this value to set the respective counters. The bits are decoded as shown in Table 6.14. The default setting is 1 consecutive out of limit conversion.

Table 6.14 Consecutive Alert / Therm Settings

NUMBER OF CONSECUTIVE OUT OF LIMIT

210

MEASUREMENTS

000

(default for CALRT[2:0])

001 2 011 3

111

(default for CTHRM[2:0])

6.13 Beta Configuration Registers 25h and 26h

Table 6.15 Beta Configuration Registers

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

25h R/W

26h R

This register is used to set the Beta Compensation factor that is used for s. Bit 3 - ENABLE1X - Enables the Beta Compensation factor auto-detection function External Diode

2External Diode 1. beta compensation cannot be enabled for External Diode 2 or 3.

 ‘0’ - The Beta Compensation Factor auto-detection circuitry is disabl ed.  ‘1’ (default) - The Beta Compensation factor auto-detection circuitry is enabled. At the b eginning of

Bit 2-0 - BETAX[2:0] - These bits always reflect the current beta configuration settings. If auto-detection circuitry is enabled, these bits will be updated automatically and writing to these bits will have no effect. If the auto-detection circuitry is disabled, these bits will determine the beta configuration setting that is used for the respective channels. Care should be taken when setting the BETAX[2:0] bits when the auto-detection circuitry is disabled. If the Beta Compensation factor is set at a beta value that is higher than the transistor beta, the circuit may introduce measurement errors. When measuring a discrete thermal diode (such as 2N3904) or a CPU diode that fun ctions like a discrete thermal diode (such as an AMD processor diode), the BETAX[2:0] bits should be set to ‘111b’.

External

Diode 1 Beta

- - - - ENABLE1 BETA1[2:0] 08h

Configuration

External

Diode 2 Beta

- - - - ENABLE2 BETA2[2:0] 08h

Configuration

every conversion, the optimal Beta Compensation factor setting will be determi ned and applied. The BETA1X[2:0] bits will be automatically updated to indicate the current setting. This is the default for EMC1183; and cannot be enabled for External Diode 2 or 3.

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Table 6.16 CPU Beta Values

BETAX[2:0]

HEX ENABLEX

MINIMUM BETA21 0

0h 0 0 0 0 0.11 1h 0 0 0 1 0.18 2h 0 0 1 0 0.25 3h 0 0 1 1 0.33 4h 0 1 0 0 0.43 5h 0 1 0 1 1.00 6h 0 1 1 0 2.33 7h 0 1 1 1 Disabled

8h - Fh 1 X X X Auto-detection

6.14 External Diode Ideali ty Factor Registers 27h to 31h

Table 6.17 Ideality Configuration Registers

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

External

27h R/W

Diode 1

Ideality

Factor

- - IDEALITY1[5:0] 12h

External

28h R/W

Diode 2

Ideality

- - IDEALITY2[5:0] 12h

Factor

External

31h R/W

Diode 3

Ideality

- - IDEALITY3[5:0] 12h

Factor

These registers store the ideality factors that are applied to the external diodes. Table 6.18 defines each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction automatically correct for most diode ideality errors; therefore, it is not recommended that these settings be updated without consulting SMSC.

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Ta ble 6.18 Ideality Factor Look-Up Table (Diode Mode l)

SETTING FACTOR SETTING FACTOR SETTING FACTOR

08h 0.9949 18h 1.0159 28h 1.0371 09h 0.9962 19h 1.0172 29h 1.0384 0Ah 0.9975 1Ah 1.0185 2Ah 1.0397

0Bh 0.9988 1Bh 1.0200 2Bh 1.0410 0Ch 1.0001 1Ch 1.0212 2Ch 1.0423 0Dh 1.0014 1Dh 1.0226 2Dh 1.0436

0Eh 1.0027 1Eh 1.0239 2Eh 1.0449

0Fh 1.0040 1Fh 1.0253 2Fh 1.0462

10h 1.0053 20h 1.0267 30h 1.0475

11h 1.0066 21h 1.0280 31h 1.0488 12h 1.0080 22h 1.0293 32h 1.0501 13h 1.0093 23h 1.0306 33h 1.0514 14h 1.0106 24h 1.0319 34h 1.0527 15h 1.0119 25h 1.0332 35h 1.0540 16h 1.0133 26h 1.0345 36h 1.0553 17h 1.0146 27h 1.0358 37h 1.0566

For CPU substrate transistors that require the BJT transistor model, the ideal ity factor behaves slightly differently than for discrete diode-connected transistors. Refer to

Table 6.19 when using a CPU

substrate transistor.

Ta ble 6.19 Subs trate Diode Ideality Factor Look-Up Table (BJT Model)

SETTING FACTOR SETTING FACTOR SETTING FACTOR

08h 0.9869 18h 1.0079 28h 1.0291 09h 0.9882 19h 1.0092 29h 1.0304 0Ah 0.9895 1Ah 1.0105 2Ah 1.0317 0Bh 0.9908 1Bh 1.0120 2Bh 1.0330

0Ch 0.9921 1Ch 1.0132 2Ch 1.0343 0Dh 0.9934 1Dh 1.0146 2Dh 1.0356

0Eh 0.9947 1Eh 1.0159 2Eh 1.0369 0Fh 0.9960 1Fh 1.0173 2Fh 1.0382

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Ta ble 6.19 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued)

SETTING FACTOR SETTING FACTOR SETTING FACTOR

10h 0.9973 20h 1.0187 30h 1.0395

11h 0.9986 21h 1.0200 31h 1.0408 12h 1.0000 22h 1.0213 32h 1.0421 13h 1.0013 23h 1.0226 33h 1.0434 14h 1.0026 24h 1.0239 34h 1.0447 15h 1.0039 25h 1.0252 35h 1.0460 16h 1.0053 26h 1.0265 36h 1.0473 17h 1.0066 27h 1.0278 37h 1.0486

APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When

measuring a 45nm Intel CPU, the Ideality Settin g should be 15h.

6.15 High Limit Status Register 35h

Table 6.20 High Limit Status Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

35h R-C

High Limit

Status

The High Limit Status Register contains the status bits that are set when a temperature channel high limit is exceeded. If any of these bits are set, the HIGH status bit in the Status Register is set. Reading from the High Limit Status Register will clear all bits if. Reading from the register will also clear the HIGH status bit in the Status Register.

The ALERT / THERM2 pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set.

The status bits will remain set until read unless the ALERT / THERM2 pin is configured as a comparator output (see Section 5.5.2).

Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high l imit. Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit. Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.

- - - - - E2HIGH EHIGH IHIGH 00h

6.16 Low Limit Status Register 36h

Table 6.21 Low Limit Status Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

36h R-C

SMSC EMC1183 39 Revision 1.0 (07-11-13)

Low Limit

Status

- - - - - E2LOW ELOW ILOW 00h

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The Low Limit Status Register contains the status bits that are set when a temperature channel drops below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear the LOW status bit in the Status Register.

The ALERT / THERM2 pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set.

The status bits will remain set until read unless the ALERT / THERM2 pin is configured as a comparator output (see

Bit 2 - E2LOW - This bit is set when the External Diode 2 chann el drops below its programmed low limit.

Bit 1 - E1LOW - This bit is set when the External Diode 1 ch annel drops below its programmed low limit.

Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.

Section 5.5.2).

6.17 Therm Limit Status Register 37h

Table 6.22 Therm Limit Status Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

37h R-C

Therm

Limit

Status

The Therm Limit Status Register contains the status bits that are set when a temperature channel Therm Limit is exceeded. If any of these bits are set, the THERM status bit in the Status Register is set. Reading from the Therm Limit Status Register will not clear the status bits. Once the temperature drops below the Therm Limit minus the Therm Hysteresis, the corresponding status bits will be automatically cleared. The THERM bit in the Status Register will be cleared when all individual channel THERM bits are cleared.

Bit 2 - E2THERM - This bit is set when the External Diode 2 channel exceeds its programmed Therm Limit. When set, this bit will assert the

Bit 1 - E1THERM - This bit is set when the External Diode 1 channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin.

Bit 0- ITHERM - This bit is set when the Internal Diode channel exceeds its programmed Therm L imit. When set, this bit will assert the THERM pin.

--- -

THERM pin.

THERM

ITHERM 00h

6.18 Filter Control Register 40h

Table 6.23 Filter Configuration Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

40h R/W Filter Control - - - - - - FILTER[1:0] 00h

The Filter Configuration Register controls the digital filter on the External Diode 1 channel.

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Bits 1-0 - FILTER[1:0] - Control the level of digital filtering that is applied to the External Diode 1 temperature measurement as shown in Table 6.24. See Figure 5.4 a nd Figure 5.5 for examples on the filter behavior.

Table 6.24 FILTER Decode

FILTER[1:0]

0 0 Disabled (default) 0 1 Level 1 1 0 Level 1 1 1 Level 2

6.19 Prod uct ID Register

Datasheet

AVERAGING10

Table 6.25 Product ID Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

FDh R

Product ID

(EMC1 183)

The Product ID Register holds a unique value that ide ntifies the device.

00100001 21h

6.20 SMSC ID Register

Table 6.26 Manufacturer ID Register

ADDR.R/WREGISTERB7B6B5B4B3B2B1B0DEFAULT

FEh RSMSC ID01011101 5Dh

The Manufacturer ID register contains an 8-bit word that identifies th e SMSC as the manufacturer of the EMC1183.

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6.21 Revision Register

Table 6.27 Revision Register

ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

FFh R Revision00000111 07h

The Revision register contains an 8-bit word that identifies the die revision .

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Temperature Error vs. Filter Capacitor

(2N3904, TA = 27°C, T

DIODE

= 27°C, VDD = 3.3V)

-1.0

-0.8

-0.5

-0.3

0.0

0.3

0.5

0.8

1.0

0 1000 2000 3000 4000

Filter Capacitor (pF)

Temperature Error (°C)

Temperature Error vs. Ambient Temperature

(2N3904, T

DIODE

= 42.5°C, VDD = 3.3V)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ambient Temperature (°C)

Temperature Error (°C)

Temperature Error vs. External Diode Temperature

(2N3904, TA = 42.5°C, VDD = 3.3V)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

External Diode Temperature (°C)

Temperature Error (°C)

Temperature Error vs. CPU Temperature

Typical 65 nm CP U from major vendor

(TA = 27°C, VDD = 3.3V, BETA = 011, C

FILTER

= 470pF)

-1

20 40 60 80 100 120

CP U Temp erat u re (°C )

Temperature Error (°C)

Beta Compensation

Disabled

Beta Compensation Enabled

Chapter 7 Typical Operating Curves

Datasheet

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Temperature Error vs. Series R esistance

0.0

0.2

0.4

0.6

0.8

1.0

0 50 100 150 200

100

120

REC Enabled

REC Disabled

Series R (Ohm)

Temperature Err o r (°C)

REC Enabled

Temperature Error (°C)

REC Disabled

Temperature Error vs. Ambient Temperature

(2N3904, T

DIODE

= 27°C, VDD = 3.3V)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Ambient Temperature (°C)

Temperature Error (°C)

EXT2 - A PD EXT3 - A PD

Supply Current vs. Conversion Rate

200

300

400

500

600

700

800

900

1000

1100

1200

1248 163264

Conversion Rate

Dynamic Aver aging Enabled

Dynamic Aver aging Disabled

Datasheet

Supply Current (u

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Chapter 8 Package Information

Datasheet

Figure 8.1 10-Pin DFN Package Drawing

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Figure 8.2 10-Pin DF N Package Dimensions

Figure 8.3 10 Pin DFN PCB Footprint

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BOTTOM

LINE 1: Device code, first 2 of last 6

digits of lot number

LINE 2: Last 4 digits of lot number

TOP

PIN 1

BOTTOM MARKING IS NOT ALLOWED

3 E L L L L L L

8.1 Package Markings

Figure 8.4 EMC1183-A 10-Pin DFN Package Markings

Datasheet

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Chapter 9 Datasheet Revision History

T able 9.1 Customer Revision History

REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION

Rev. 1.0 (07-11-13) Formal document release

Revision 1.0 (07-11-13) 48 SMSC EMC1183

DATASHEET