Datasheet dsPIC33FJ16GP101, dsPIC33FJ16GP102, dsPIC33FJ16MC101, dsPIC33FJ16MC102 Datasheet
dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102
Data Sheet
High-Performance, Ultra Low Cost
16-bit Digital Signal Controllers
© 2011 Microchip Technology Inc. Preliminary DS70652C
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
K
EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC
logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-315-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
T empe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memo ry and
analog products. In addition, Microchip’s quality system for the desig n
and manufacture of development systems is ISO 9001:2000 certified.
®
MCUs and dsPIC® DSCs, KEELOQ
®
code hopping
DS70652C-page 2 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND
dsPIC33FJ16MC101/102
High-Performance, Ultra Low Cost
16-bit Digital Signal Controllers
Operating Range:
• Up to 16 MIPS operation (3.0V-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
On-Chip Flash and SRAM:
• Flash program memory (16 Kbytes)
• Data SRAM (1 Kbyte)
• Security for program Flash
System Management:
• Flexible clock options:
- External, crystal, resonator, internal FRC
- Phase-Locked Loop (PLL)
• High-accuracy internal FRC
- ±0.25% typical
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR)
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor (FSCM)
Motor Control PWM:
• 6-channel 16-bit Motor Control PWM:
- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- Up to two Fault inputs
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 16 MIPS) = 488 Hz for Edge-Aligned
mode, 244 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 16 MIPS) = 15.63 kHz for Edge-Aligned
mode, 7.81 kHz for Center-Aligned mode
Power Management:
• Single supply on-chip voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Analog Peripherals:
• 10-bit, 1.1 Msps Analog-to-Digital Converter (ADC):
- Two and four simultaneous samples
- Up to six input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Sleep mode conversion for low-power
applications
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
• Three Analog Comparators with programmable
input/output configuration:
- Up to four inputs per Comparator
- Blanking function
- Output digital filter
• Charge Time Measurement Unit (CTMU):
- Supports capacitive touch sensing for touch
screens and capacitive switches (mTouch™)
- Provides high-resolution time measurement
for advanced sensor applications
- 200 ps resolution for time measurement and
accurate temperature sensing
- On-chip high-resolution temperature
measurement capabili ty
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 3
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Timers/Capture/Compare/PWM:
• Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to three channels):
- Capture on up, down, or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
• Hardware Real-Time Clock and Calendar
(RTCC):
- Provides clock, calendar and alarm function
Digital I/O:
• Peripheral Pin Select functionality
• Up to 21 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5.5V output with open drain configuration on
5V tolerant pins
• All digital input pins are 5V tolerant
• Up to 8 mA sink on designated pins
Communication Modules:
• 4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
2
C™:
•I
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
•UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
®
-IrDA
- High-Speed mode
- Hardware Flow Control with CTS and RTS
encoding and decoding in hardware
Interrupt Controller:
• 5-cycle latency
• Up to 23 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Four processor exceptions
High-Performance MCU CPU Features:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit-wide data path
• 24-bit-wide instructions
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 73 base instructions: mostly one word/one cycle
• Flexible and powerful indirect addressing mode
• Software stack
• 16 x 16 integer multiply operations
• 32/16 and 16/16 integer divide operations
• Up to ±16-bit shifts
Additional High-Performance DSC CPU
Features:
• 11 additional instructions
• Two 40-bit accumulators with rounding and
saturation options
• Additional flexible and powerful addressing
modes:
- Modulo
- Bit-reversed
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
• Shifts for up to 40-bit data
• 16 x 16 fractional multiply/divide operations
Packaging:
• 18-pin PDIP/SOIC
• 20-pin PDIP/SOIC/SSOP
• 28-pin SPDIP/SOIC/SSOP/QFN
• 28-pin QFN: 6x6 mm
• 36-pin TLA: 5x5 mm
Note: See Table 1 for the list of peripheral
features per device.
DS70652C-page 4 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
dsPIC33FJ16GP101/102 AND
dsPIC33FJ16MC101/102 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed in
Table 1. The following pages show their pinout
diagrams.
TABLE 1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 CONTROLLER FAMILIES
Remappable Peri pherals
(2)
(1)
Device
Pins
Program Flash (Kbyte)
RAM (Kbytes)
Remappable Pins
16-bit Timer
Input Capture
UART
Output Compare
SPI
External Interrupts
Motor Control PWM
PWM Faults
10-Bit, 1.1 Msps ADC
C™
2
I
RTCC
Comparators
CTMU
I/O Pins
Packages
dsPIC33FJ16GP101 18 16 1 8 3 3 2 1 3 1 — — 1 ADC,
4-ch
20 16 1 8 3 3 2 1 3 1 — — 1 ADC,
4-ch
dsPIC33FJ16GP102 28 16 1 16 3 3 2 1 3 1 — — 1 ADC,
6-ch
36 16 1 16 3 3 2 1 3 1 — — 1 ADC,
6-ch
dsPIC33FJ16MC101 20 16 1 10 3 3 2 1 3 1 6-ch 1 1 ADC,
4-ch
dsPIC33FJ16MC102 28 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,
6-ch
36 16 1 16 3 3 2 1 3 1 6-ch 2 1 ADC,
6-ch
Note 1: Two out of three timers are remappable.
2: Two out of three interrupts are remappable.
Y 1 3 Y 13 PDIP,
Y1 3Y13
Y 1 3 Y 21 SPDIP,
Y1 3Y21TLA
Y1 3Y15PDIP,
Y 1 3 Y 21 SPDIP,
Y1 3Y21TLA
SOIC
SSOP
SOIC,
SSOP,
QFN
SOIC,
SSOP
SOIC,
SSOP,
QFN
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 5
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
18-Pin PDIP/SOIC
dsPIC33FJ16GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
V
DD
VSS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
SCK1/INT0/RP7
(1)
/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4
(1)
/CN1/RB4
V
CAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
SCL1/SDO1/RP8
(1)
/CN22/RB8
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RP15
(1)
/CN11/RB15
RTCC/RP14
(1)
/CN12/RB14
dsPIC33FJ16GP101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AV
DD
AVSS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
SCK1/INT0/RP7
(1)
/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4
(1)
/CN1/RB4
V
CAP
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
SCL1/SDO1/RP8
(1)
/CN22/RB8
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RP15
(1)
/CN11/RB15
RTCC/RP14
(1)
/CN12/RB14
V
DD
20-Pin SSOP
dsPIC33FJ16GP102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AV
DD
AVSS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
ASCL1/RP6
(1)
/CN24/RB6
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4
(1)
/CN1/RB4
V
SS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
V
CAP
SCK1/INT0/RP7
(1)
/CN23/RB7
SDA1/SDI1/RP9
(1)
/CN21/RB9
SCL1/SDO1/RP8
(1)
/CN22/RB8
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RP15
(1)
/CN11/RB15
RTCC/RP14
(1)
/CN12/RB14
RP13
(1)
/CN13/RB13
RP12
(1)
/CN14/RB12
RP10
(1)
/CN16/RB10
RP11
(1)
/CN15/RB11
ASDA1/RP5
(1)
/CN27/RB5
28-Pin SPDIP/SOIC/SSOP
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
= Pins are up to 5V tolerant
Pin Diagrams
DS70652C-page 6 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
dsPIC33FJ16MC101
MCLR
VSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
V
DD
VSS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
F
LTA1
(2)
/SCK1/INT0/RP7
(1)
/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4
(1)
/CN1/RB4
PWM1H2/RP12
(1)
/CN14/RB12
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
V
CAP
SDA1/SDI1/PWM1L3/RP9
(1)
/CN21/RB9
SCL1/SDO1/PWM1H3/RP8
(1)
/CN22/RB8
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
20-Pin PDIP/SOIC/SSOP
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The PWM Fau lt pins are enabled and asserted during any reset event. Refer to Section 15.2
“PWM Faults” for more information on the PWM faults.
dsPIC33FJ16MC102
MCLR
VSS
VDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
AV
DD
AVSS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
FLTA1
(2)
/ASCL1/RP6
(1)
/CN24/RB6
PGEC3/SOSCO/T1CK/CN0/RA4
PGED3/SOSCI/RP4
(1)
/CN1/RB4
V
SS
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
V
CAP
SCK1/INT0/RP7
(1)
/CN23/RB7
SDA1/SDI1/RP9
(1)
/CN21/RB9
SCL1/SDO1/RP8
(1)
/CN22/RB8
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1H3/RP10
(1)
/CN16/RB10
PWM1L3/RP11
(1)
/CN15/RB11
FLTB1
(2)
/ASDA1/RP5
(1)
/CN27/RB5
28-Pin SPDIP/SOIC/SSOP
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 7
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
28-Pin QFN
(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS externally.
= Pins are up to 5V tolerant
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ16GP102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/SDI1/RP9
(1)
/CN21/RB9
RP13
(1)
/CN13/RB13
RP12
(1)
/CN14/RB12
RP10
(1)
/CN16/RB10
RP11
(1)
/CN15/RB11
V
SS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
VDD
PGEC3/SOSCO/T1CK/CN0/RA4
ASDA1/RP5
(1)
/CN27/RB5
PGED3/SOSCI/RP4
(1)
/CN1/RB4
ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
SCL1/SDO1/RP8
(1)
/CN22/RB8
AV
DD
AVSS
RP15
(1)
/CN11/RB15
RTCC/RP14
(1)
/CN12/RB14
Pin Diagrams (Continued)
DS70652C-page 8 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
28-Pin QFN
(2)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS externally.
3: The PWM Fau lt pins are enabled and asserted during any reset event. Refer to Section 15.2
“PWM Faults” for more information on the PWM faults.
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ16MC102
5
4
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
VSS
VCAP
SDA1/SDI1/RP9
(1)
/CN21/RB9
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1H3/RP10
(1)
/CN16/RB10
PWM1L3/RP11
(1)
/CN15/RB11
V
SS
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
OSCO/CLKO/CN29/RA3
OSCI/CLKI/CN30/RA2
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
VDD
PGEC3/SOSCO/T1CK/CN0/RA4
FLTB1
(3)
/ASDA1/RP5
(1)
/CN27/RB5
PGED3/SOSCI/RP4
(1)
/CN1/RB4
FLTA1
(3)
/ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
SCL1/SDO1/RP8
(1)
/CN22/RB8
AV
DD
AVSS
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 9
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
36-Pin TLA
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS externally.
1
dsPIC33FJ16GP102
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
MCLR
AVDD
RP15
(1)
/CN11/RB15
RTCC/RP14
(1)
/CN12/RB14
AV
SS
N/C
N/C
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
RP13
(1)
/CN13/RB13
RP12
(1)
/CN14/RB12
RP10
(1)
/CN16/RB10
RP11
(1)
/CN15/RB11
V
DD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGED3/SOSCI/RP4
(1)
/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
V
SS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
ASDA1/RP5
(1)
/CN27/RB5
PGEC3/SOSCO/T1CK/CN0/RA4
ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
SCL1/SDO1/RP8
(1)
/CN22/RB8
V
DD
N/C (VDD)
7
8
9
34
35
36
16
17
18
27
26
25
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
DS70652C-page 10 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
36-Pin TLA
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be
connected to V
SS externally.
3: The PWM Fau lt pins are enabled and asserted during any reset event. Refer to Section 15.2
“PWM Faults” for more information on the PWM faults.
N/C
PGED2/AN0/C3INB/C1INA/CTED1/CN2/ RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/ RA1
MCLR
AVDD
PWM1L1/RP15
(1)
/CN11/RB15
PWM1H1/RTCC/RP14
(1)
/CN12/RB14
AV
SS
N/C
N/C
V
SS
SDA1/SDI1/RP9
(1)
/CN21/RB9
PWM1L2/RP13
(1)
/CN13/RB13
PWM1H2/RP12
(1)
/CN14/RB12
PWM1H3/RP10
(1)
/CN16/RB10
PWM1L3/RP11
(1)
/CN15/RB11
V
DD
VCAP
VDD
PGED1/AN2/C2INA/C1INC/RP0
(1)
/CN4/RB0
PGED3/SOSCI/RP4
(1)
/CN1/RB4
OSCO/CLKO/CN29/RA3
AN5/C3IND/C2IND/RP3
(1)
/CN7/RB3
AN4/C3INC/C2INC/RP2
(1)
/CN6/RB2
PGEC1/AN3/CV
REFIN/CVREFOUT/C2INB/C1IND/RP1
(1)
/CN5/RB1
V
SS
OSCI/CLKI/CN30/RA2
N/C (Vss)
N/C
FLTB1
(3)
/ASDA1/RP5
(1)
/CN27/RB5
PGEC3/SOSCO/T1CK/CN0/RA4
FLTA1
(3)
/ASCL1/RP6
(1)
/CN24/RB6
SCK1/INT0/RP7
(1)
/CN23/RB7
SCL1/SDO1/RP8
(1)
/CN22/RB8
V
DD
N/C (VDD)
dsPIC33FJ16MC102
= Pins are up to 5V tolerant
1
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
7
8
9
34
35
36
16
17
18
27
26
25
Pin Diagrams (Continued)
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 11
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Table of Contents
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 Product Families........................................................................................... 5
1.0 Device Overview........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers.......................................................................................... 21
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization................................................................................................................................................................. 37
5.0 Flash Program Memory.............................................................................................................................................................. 65
6.0 Resets ....................................................................................................................................................................................... 69
7.0 Interrupt Controller..................................................................................................................................................................... 77
8.0 Oscillator Configuration............................................................................................................................................................ 107
9.0 Power-Saving Features............................................................................................................................................................ 115
10.0 I/O Ports ................................................................................................................................................................................... 121
11.0 Timer1 ............................................................................................................................................................................... ....... 139
12.0 Timer2/3 Feature ..................................................................................................................................................................... 141
13.0 Input Capture............................................................................................................................................................................ 147
14.0 Output Compare....................................................................................................................................................................... 149
15.0 Motor Control PWM Module..................................................................................................................................................... 153
16.0 Serial Peripheral Interface (SPI) ............................................................................................................................................... 169
17.0 Inter-Integrated Circuit™ (I
18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 183
19.0 10-bit Analog-to-Digital Converter (ADC)................................................................................................................................. 189
20.0 Comparator Module.................................................................................................................................................................. 201
21.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 213
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 223
23.0 Special Features ...................................................................................................................................................................... 227
24.0 Instruction Set Summary.......................................................................................................................................................... 235
25.0 Development Support............................................................................................................................................................... 243
26.0 Electrical Characteristics.......................................................................................................................................................... 247
27.0 Packaging Information.............................................................................................................................................................. 289
Appendix A: Revision History............................................................................................................................................................. 311
Index ................................................................................................................................................................................................. 315
The Microchip Web Site..................................................................................................................................................................... 319
Customer Change Notification Service.............................................................................................................................................. 319
Customer Support.............................................................................................................................................................................. 319
Reader Response.............................................................................................................................................................................. 320
Product Identification System............................................................................................................................................................. 321
2
C™).............................................................................................................................................. 175
DS70652C-page 12 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
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Most Current Data Sheet
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2011 Microchip Technology Inc. Preliminary DS70652C-page 13
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
NOTES:
DS70652C-page 14 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes the features
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 devices. However, it is not intended to be a comprehensive reference source. T o complement the
information in this data sheet, refer to the
latest family reference sections of the
“dsPIC33F/PIC24H Family Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
This document contains device specific information for
the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 Digital Signal Controller
(DSC) Devices. The dsPIC33F devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the co re
and peripheral modules in the dsPIC33FJ16GP101/
102 and dsPIC33FJ16MC101/102 family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 15
16
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
IC1-IC3
I2C1
PORTA
Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins
and features present on each device.
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program Memory
Data Latch
Literal Data
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1
Timers
PORTB
Address Generator Units
1-3
CNx
UART1
OC/
PWM1-2
RTCC
PWM
6 Ch
Remappable
Pins
SPI1
CTMU
External
Interrupts
1-3
Comparators
1-3
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
FIGURE 1-1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 BLOCK DIAGRAM
DS70652C-page 16 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN5 I Analog No Analog input channels.
CLKI
CLKO
OSC1
OSC2
SOSCI
SOSCO
CN0-CN7
CN11-CN16
CN21-CN24
CN27
CN29-CN30
IC1-IC3 I ST Yes Capture inputs 1/2/3.
OCFA
OC1-OC2
INT0
INT1
INT2
RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.
T1CK
T2CK
T3CK
U1CTS
U1RTS
U1RX
U1TX
SCK1
SDI1
SDO1
SS1
SCL1
SDA1
ASCL1
ASDA1
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
Note 1: An external pull-down resistor is required for the FLT A1
2: The FLTB1
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
Pin
Type
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
information on the PWM faults.
Buffer
Type
I
O
I
I/O
I
O
IST
I
O
I
I
I
I
I
I
I
O
I
O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
ST/
CMOS
—
ST/
CMOS
—
ST/
CMOS
—
ST
ST
ST
ST
ST
—
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
—
ST
ST
ST
ST
ST
pin is not available on dsPIC33FJ16MC101 (20-pin) devices.
PPS Description
NoNoExternal clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
NoNoOscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
NoNo32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
No
Change notification inputs. Can be software programmed for internal weak
No
pull-ups on all inputs.
No
No
No
Yes
Compare Fault A input (for Compare Channels 1 and 2).
Yes
Compare outputs 1 through 2.
No
External interrupt 0.
Yes
External interrupt 1.
Yes
External interrupt 2.
No
Timer1 external clock input.
Yes
Timer2 external clock input.
Yes
Timer3 external clock input.
Yes
UART1 clear to send.
Yes
UART1 ready to send.
Yes
UART1 receive.
Yes
UART1 transmit.
Yes
Synchronous serial clock input/output for SPI1.
Yes
SPI1 data in.
Yes
SPI1 data out.
Yes
SPI1 slave synchronization or frame pulse I/O.
No
Synchronous serial clock input/output for I2C1.
No
Synchronous serial data input/output for I2C1.
No
Alternate synchronous serial clock input/output for I2C1.
No
Alternate synchronous serial data input/output for I2C1.
pin on dsPIC33FJ16MC101 (20-pin) devices.
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 17
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
(1,3)
FLTA1
(2,3)
FLTB1
Pin
Type
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
RTCC O Digital No RTCC Alarm output.
CTPLS
CTED1
CTED2
Buffer
Type
I
I
O
O
O
O
O
O
O
I
I
ST
ST
—
—
—
—
—
—
Digital
Digital
Digital
PPS Description
No
PWM1 Fault A input.
No
PWM1 Fault B input.
No
PWM1 Low output 1
No
PWM1 High output 1
No
PWM1 Low output 2
No
PWM1 High output 2
No
PWM1 Low output 3
No
PWM1 High output 3
Yes
CTMU Pulse Output.
No
CTMU External Edge Input 1.
No
CTMU External Edge Input 2.
REF
CV
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
MCLR
AV
DD P P No Positive supply for analog modules. This pin must be connected at all times.
AV
SS P P No Ground reference for analog modules. For devices without this pin, this signal
I
O
O
O
I/O
I/O
I/O
Analog
I
Analog
I
Analog
I
Analog
I
Analog
Digital
I
Analog
I
Analog
I
Analog
I
Analog
Digital
I
Analog
I
Analog
I
Analog
I
Analog
Digital
ST
I
ST
ST
I
ST
ST
I
ST
No
Comparator Voltage Positive Reference Input.
No
Comparator 1 Positive Input A.
No
Comparator 1 Negative Input B.
No
Comparator 1 Negative Input C.
No
Comparator 1 Negative Input D.
Yes
Comparator 1 Output.
No
Comparator 2 Positive Input A.
No
Comparator 2 Negative Input B.
No
Comparator 2 Negative Input C.
No
Comparator 2 Negative Input D.
Yes
Comparator 2 Output.
No
Comparator 3 Positive Input A.
No
Comparator 3 Negative Input B.
No
Comparator 3 Negative Input C.
No
Comparator 3 Negative Input D.
Yes
Comparator 3 Output.
No
Data I/O pin for programming/debugging communication channel 1.
No
Clock input pin for programming/debugging communication channel 1.
No
Data I/O pin for programming/debugging communication channel 2.
No
Clock input pin for programming/debugging communication channel 2.
No
Data I/O pin for programming/debugging communication channel 3.
No
Clock input pin for programming/debugging communication channel 3.
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.
For devices without this pin, this signal is connected to V
is connected to V
SS internally.
DD internally.
VDD P — No Positive supply for peripheral logic and I/O pins.
V
CAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1
2: The FLTB1
pin is not available on dsPIC33FJ16MC101 (20-pin) devices.
pin on dsPIC33FJ16MC101 (20-pin) devices.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM faults.
DS70652C-page 18 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
1.1 Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the primary reference for the operation
of a particular module or device feature.
Note: To access the documents listed below,
browse to the specific device product
page of the Microchip web site
(www.microchip.com).
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• Section 2. “CPU” (DS70204)
• Section 3. “Data Memory” (DS70202)
• Section 4. “Program Memory” (DS70203)
• Section 5. “Flash Programming” (DS70191)
• Section 8. “Reset” (DS70192)
• Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
• Section 11. “Timers” (DS70205)
• Section 12. “Input Capture” (DS70198)
• Section 13. “Output Compare” (DS70209)
• Section 14. “Motor Control PWM” (DS70187)
• Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
• Section 17. “UART” (DS70188)
• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
• Section 19. “Inter-Integrated Circuit™ (I
• Section 23. “CodeGuard Security” (DS70199)
• Section 24. “Programming and Diagnostics” (DS70207)
• Section 25. “Device Configuration” (DS70194)
• Section 26. “Development Tool Support” (DS70200)
• Section 30. “I/O Ports with Peripheral Pin Select (PPS)” (DS70190)
• Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301)
• Section 51. “Introduction (Part VI)” (DS70655)
• Section 52. “Oscillator (Part VI)” (DS70644)
• Section 53. “Interrupts (Part VI)” (DS70633)
• Section 54. “Comparator with Blanking” (DS70647)
• Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635)
2
C™)” (DS70195)
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 19
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
NOTES:
DS70652C-page 20 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the Microchip web site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1 Basic Connection Requirements
Getting started with the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 family of 16-bit Digital Signal
Controllers (DSCs) requires attention to a minimal set
of device pin connections before proceeding with
development. The following is a list of pin names, which
must always be connected:
DD and VSS pins
• All V
(see Section 2.2 “Decoupling Capacitors”)
• All AV
•V
•MCLR
• PGECx/PGEDx pins used for In-Circuit Serial
• OSC1 and OSC2 pins when external oscillator
DD and AVSS pins, if present on the device
(regardless if ADC module is not used)
(see Section 2.2 “Decoupling Capacitors”)
CAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (V
pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
CAP)”)
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as V
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10V – 20V. This capacitor
should be a low-ESR and have resonance
frequency in the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
DD, VSS, AVDD, and
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 21
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
dsPIC33F
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
VCAP
10 Ω
R1
10 µF
Tantalum
Note 1: R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1 ≤ 470Ω will limit any current flowing into
MCLR
from the external capacitor C, in the
event of MCLR
pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin
V
IH and VIL specifications are met.
C
R1
R
V
DD
MCLR
dsPIC33F
JP
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR
pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
pin. Consequently,
pin.
2.3 CPU Logic Filter Capacitor
CAP)
CAP pin must not be
Connection (V
A low-ESR (< 5 Ohms) capacitor is required on the
CAP pin, which is used to stabilize the voltage
V
regulator output voltage. The V
connected to V
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 26.0
“Electrical Characteristics” for additional
information.
The placement of this capacitor should be close to the
CAP. It is recommended that the trace length not
V
exceed one-quarter inch (6 mm). Refer to Section 23.2
“On-Chip Voltage Regulator” for details.
DS70652C-page 22 Preliminary © 2011 Microchip Technology Inc.
DD, and must have a capacitor between
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
13
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
14
15
16
17
18
19
20
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and timing requirements information in the “Flash Program-
ming Specification for dsPIC33F Families with Volatile
Configuration Bits” for information on capacitive load-
ing limits and pin input voltage high (V
IL) requirements.
(V
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
®
ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
®
• “MPLAB
ICD 2 In-Circuit Debugger User’s
Guide” (DS51331)
®
• “Using MPLAB
• “MPLAB
®
ICD 2” (poster) (DS51265)
ICD 2 Design Advisory” (DS51566)
• “Using MPLAB® ICD 3” (poster) (DS51765)
®
• “MPLAB
• “MPLAB
ICD 3 Design Advisory” (DS51764)
®
REAL ICE™ In-Circuit Debugger
User’s Guide” (DS51616)
®
• “Using MPLAB
REAL ICE™” (poster) (DS51749)
IH) and input low
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 23
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
2.7 Oscillator Value Conditions on Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
IN < 8 MHz (for ECPLL mode) to comply with device
F
PLL start-up conditions. HSPLL mode is not supported.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The fixed PLL settings of 4x after a
POR with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can enable the PLL, and then perform a clock switch to
the Oscillator + PLL clock source. Note that clock
switching must be enabled in the device Configuration
word.
2.8 Configuration of Analog and
IN < 8 MHz (for MSPLL mode) or 3 MHz <
Digital Pins During ICSP
Operations
If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE
in-circuit emulator is selected as a debugger, it
automatically initializes all of the analog-to-digital input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in the register that correspond to the
analog-to-digital pins that are initialized by MPLAB
ICD 2, MPLAB ICD 3, or MPLAB REAL ICE in-circuit
emulator, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain analog-to-digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE in-circuit emulator is used as a programmer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all analog-to-digital pins being recognized as analog
input pins, resulting in the port value being read as a
logic ‘0’, which may affect user application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outp uts and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between V
and unused pins.
DS70652C-page 24 Preliminary © 2011 Microchip Technology Inc.
SS
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
3.0 CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 CPU module has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented varies by device. A single-cycle
instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All
instructions execute in a single cycle, with the exception of instructions that change the program flow, the
double-word move (MOV.D) instruction and the table
instructions. Overhead-free program loop constructs
are supported using the DO and REPEAT instructions,
both of which are interruptible at any point.
The dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 devices have sixteen, 16-bit
working registers in the programmer’s model. Each of
the working registers can serve as a data, address, or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/
102 devices: MCU and DSP. These two instruction
classes are seamlessly integrated into a single CPU.
The instruction set includes many addressing modes
and is designed for optimum C compiler efficiency. For
most instructions, dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 devices are capable of executing a data (or program data) memory read, a working register (data) read, a data memory write, and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ16GP101/
102 and dsPIC33FJ16MC101/102 is shown in
Figure 3-2.
3.1 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space V isibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2 DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators, and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC instruction and other associated instructions
can concurrently fetch two data operands from memory, while multiplying two W registers and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM data
space be split for these instructions and linear for all
others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain
working registers to each address space.
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 25
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Instruction
Decode and
Control
PCH PCL
Program Counter
16-bit ALU
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
EA MUX
Interrupt
Controller
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
16
Program Memory
Data Latch
Address Latch
3.3 Special MCU Features
The dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 features a 17-bit by 17-bit
single-cycle multiplier that is shared by both the MCU
ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
The dsPIC33FJ16GP101/102 and
dsPIC33FJ16MC101/102 supports 16/16 and 32/16
divide operations, both fractional and integer. All divide
instructions are iterative operations. They must be
executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 CPU CORE BLOCK
DIAGRAM
DS70652C-page 26 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
PC22
PC0
7
0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators
ACCA
ACCB
7
0
Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15
0
REPEAT Loop Counter
DCOUNT
15
0
DO Loop Counter
DOSTART
22
0
DO Loop Start Address
IPL2 IPL1
SPLIM
Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15
0
Core Configuration Register
Legend
CORCON
DA DC
RA
N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
FIGURE 3-2: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 PROGRAMMER’S
MODEL
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 27
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
3.4 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA
(1)
bit 15 bit 8
SB
(1)
OAB SAB DA DC
R/W-0
(3)
IPL<2:0>
R/W-0
(3)
(2)
R/W-0
(3)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit 7 bit 0
Legend:
C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflo w Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘S t icky’ Stat us bi t
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow
bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
DS70652C-page 28 Preliminary © 2011 Microchip Technology Inc.
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
bit
(2)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
© 2011 Microchip Technology Inc. Preliminary DS70652C-page 29
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)
DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(2)
PSV RND IF
bit 7 bit 0
Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executi ng DO loop at end of current loop iteratio n
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70652C-page 30 Preliminary © 2011 Microchip Technology Inc.
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