Compal LA-9101P VAW01, Inspiron 15 3521, Inspiron 15R 5521 Schematic

A

M

ODEL NAME : VAW01

B

C

Z

Z

R

ZZ

1@

G

ZZ

CER3@

D

Z

T

ZZ

RIR3@

E

PROJECT CODE : ANRVAW0100

CB VAW01 LA-9101P LS-9101P/9102P/9103P

PCB NO : LA-9101P (Mars Pro)

1 1

DA60000UT00 LA-9101P M/B

P

DAZ0U500100

DA40001FO00 LS-9101P POWER BUTTON/B

CB VAW01 LA-9101P LS-9101P/9102P/9103P GOLD A31 !

P

DAZ0U500101

ZZ

ANNR3@

Z

H

CB VAW00 LA-9101P LS-9101P/9102P/9103P TRIPOD A31 !

P

DAZ0U500102

ZZ

DTR3@

Z

Z

DA40001FP00 LS-9102P USB/B
DA40001FQ00 LS-9103P TP BUTTON/B

PCB VAW00 LA-9101P LS-9101P/9102P/9103P HANNSTARB A31 !

DAZ0U500103

PCB VAW00 LA-9101P LS-9101P/9102P/9103P ZDT A31 !

DAZ0U500104

Dell / Compal Confidential

2 2

Schematic Document

Intel Chief River

Ivy Bridge(BGA) + Panther Point

OAK 15" UMA/DIS AMD Mars Pro

2012-08-22

3 3

46@ : for 46 level
@ : Nopop Component
CONN@ : Connector Component

R1@ : R1 P/N
R3@ : R3 P/N

KB9012@ : ENE KB9012 Implemented
UMA@ : Only for UMA
EMC@ : EMI/ESD parts

GCLK@ : Green CLK implemented

4 4

GCLKUMA@ : Green CLK for UMA

Rev: 0.4

i3R1@ : CPU i3-3217 1.8G
i3VOSR1@ : CPU i3-2365 1.4G
i5R1@ : CPU i5-3317 1.7G
i7R1@ : CPU i7-3517 1.9G
CELR1@ : CPU Celeron 887 1.5G
PENR1@ : CPU Pentium 997 1.6G

DIS@ : Only for Discrete
TH@/THR1@ : Thames-XT
MS@/MSR1@ : Mars Pro

X76@ :
SPI-ROM & VRAM Group

GCLKDIS@ : Green CLK for DIS
XTAL@ : X'tal implemented
XTALDIS@ : X'tal with DIS implemented

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Title

Title

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9101P

LA-9101P

LA-9101P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

1 57Wednesday, August 29, 2012

1 57Wednesday, August 29, 2012

1 57Wednesday, August 29, 2012

0.4

0.4

0.4

A

B

C

D

E

6

4M*16

VRAM * 4
D

DR3

1 1

6

4M*16

VRAM * 4
D

DR3

128M*16

VRAM * 4
DDR3

P

P.31

.31

64bit

AMD Mars Pro, 128b,
Radeon HD8650M,
P7000-P8000

1GB DDR3 (8-64Mx16),
2GB DDR3 (8-128Mx16)

LVDS Conn.

2 2

HDMI Conn.

P.21

P.22

P

.30

A

MD

Mars Pro

24-26 W

1

28M*16

VRAM * 4
D

DR3

6

4bit

P.24~29

P

.30

P

EG 2.0 x8

LVDS

HDMI

Intel
Ivy Bridge
P

rocessor

17W DC

BGA 1023

100MHz 100MHz

2.7GT/s

P.5~10

DMI x4FDI x8

5GB/s

Intel

Memory Bus (DDR3)

D

ual Channel

1

.5V DDR3 1333 MHz

SATA3.0

Port 0

Port 2

F

an Control

D

DRIII-DIMM X2

B

ANK 0, 1, 2, 3, 4 ,5 ,6 ,7

SATA HDD Conn.

SATA ODD Conn.

P

.40

8GB Max

CPU XDP
Conn.

P.11~12

P.41

P.41

P

.6

Panther Point

PCH HM76

USB 3.0

USB2.0

PCI-E x1

Port 2

Mini Card
WLAN/BT4.0
Half

3 3

P.38

Ethernet

RTL8105E

RJ45

Port 1

P.32

P.32

BGA 989 Balls

HD Audio

P13~20

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

P.44

P.40

P.35

SPI ROM

4MB

SPI ROM

2MB

P.13

P.13

SPI

SPI

LPC Bus

33MHz

ENE KBC
KB9012

P.39

Port 1,2

Port 0,1

Port 2,3

Port 11

Port 8

Port 10

Port 9

USB 3.0 Conn. 1
USB 3.0 Conn. 2

USB 3.0 Conn. 3
USB 2.0 Conn. 4

Digital Camera
(With Digital MIC)

Mini Card
WLAN (Half)

Card Reader
RTS5170/RTS5179

Touch Screen

Digital Mic.

Audio Codec

ALC3221

P.33

P.36

P.37

Daughter board

P.21

P.38

P.34

3 in 1 Socket

P.21

P.34

Headphone Jack / Mic. Jack combo

Int. Speaker R / L

P.33

P.33

4 4

PS/2

Int.KBD

A

B

P.40

Touch Pad

P.40

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block diagram

Block diagram

Block diagram

LA-9101P

LA-9101P

LA-9101P

E

2 57Wednesday, August 29, 2012

2 57Wednesday, August 29, 2012

2 57Wednesday, August 29, 2012

0.4

0.4

0.4

A

ompal Confidential

C

P

roject Code : VAW01

B

C

D

E

File Name : LA-9101P

S-9101P (PWR/B)

1 1

L

E5

U

L

id

(SA00003VQ00)

SW1
(SN100004Y00)

4 pin-Hot Bar

PBATT

Battery

PWR-BTN FFC

2 2

3 3

TP-MB FFC

6 pin

JHDMI

JLAN

JUSB1

JUSB2

JUSB3

JHP

4 pin

HDMI

RJ-45

USB

USB

USB

HP

JTOUCH
6 pin

JPWR
4 pin

JFAN
3 pin

RTC JRTC

2 pin

Led1

Led3

Led2

XDP

JXDP

Led4

JTP
6 pin

JMINI

MINI Card

PJPDC
5 pin

LA-9101P M/B

(OAK 15")

JSPK
4 pin

Top Side

Bottom Side

JLVDS
40 pin

JREAD

Card
Reader

JKB
30 pin

JDB
8 pin

JODD

JHDD

USB-DB FFC

8 pin

LS-9102P (USB/B)

USB

8 pin
Hot Bar

JUSB4

TP-Module

4 4

TP-BTN FFC

4 pin

A

4 pin
Hot Bar

SW2 SW3

B

LS-9103P (TP-BTN/B)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

DB block diagram

DB block diagram

DB block diagram

LA-9101P

LA-9101P

LA-9101P

E

3 57Wednesday, August 29, 2012

3 57Wednesday, August 29, 2012

3 57Wednesday, August 29, 2012

0.4

0.4

0.4

oard ID Table for AD channel

B

Vcc 3.3V +/- 5%

B

oard ID

0
1
2
3
4
5
6
7

SMBUS Control Table

100K +/- 5%Ra

R

b V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SOURCE

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CL K
PCH_SML1DA TA

MEM_SMBCLK
MEM_SMBDAT A

KB9012

KB9012

PCH

PCH

MINI1 BATT SODIMM

V

A

D_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

MINI2

typ

A

D_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

V

V

Express
Card

VV V

V

A

D_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

m

ax

Thermal
Sensor

EC AD3

0

x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal

FFS VGA

Sensor

V

V

V

A

B

OARD ID Table

I

D

PCB Revision

0

0

.1

1
2
3
4
5
6
7

XDP

0.1

0.2
0

0

.3

0.3

0.4

1.0

1.0

UMA THM

Charger

V

V

P

roject ID Table

P

roject Revision

I

D

0
1

.1

0

.2

0.2

0.3

0.4

1.0

MARS

2
3
4

UMA

5

DIS THAMES

6

DIS MARS PRO

7

PCH

Link

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

DESTINATION

USB conn.2

USB conn.1

USB conn.3

USB conn.4 (DB)

NC

NC

NC

NC

MINI CARD (WLAN)

Touch Screen

Card Reader

Camera

1 1

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

DESTINATIONDIFFERENTIAL

10/100 LAN

MINI CARD WLAN

None

None

None

None

None

CLKOUT_PCIE7 None

CLKOUT_PEG_B

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

CLKOUT

PCI0

PCI1

PCI2

PCI3

None

None

None

None

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

None

ODD

None

None

None None

Symbol Note :

PCI4

: means Digital Ground

: means Analog Ground

None

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

13

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

NC

NC

DESTINATION

10/100 LAN

MINI CARD (WLAN)

None

None

None

None

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-9101P

LA-9101P

LA-9101P

4 57Wednesday, August 29, 2012

4 57Wednesday, August 29, 2012

4 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

(1)PEG_RCOMPO (G4) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC1.

D D

(2)PEG_ICOMPO use 12mil connect to RC1

PEG_RCOMPO (G4)

PEG_ICOMPI (G3)

Trace length
Max is 500 mils

DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N1<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>
DMI_CRX_PTX_P1<15>
DMI_CRX_PTX_P2<15>
DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>
DMI_CTX_PRX_N1<15>

C C

B B

eDP_COMPIO and ICOMPO signals should be short ed near
balls and route d with typical impedance <25 m ohms

DMI_CTX_PRX_N2<15>
DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>
DMI_CTX_PRX_P1<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15>
FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15>
FDI_LSYNC1<15>

+VCCP

RC36 24.9_0402_1%

RC158 10K_0402_5%

1 2

@

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

12

PEG_ICOMPO (G1)

UC1A

i5R1@

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

4

R_COMP place close to CPU

width 4 mils

width 12 mils

SA00005K63L

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

eDP

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

R_COMP

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

VCC_IO

PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

PEG_COMP

CC9 220nF_0402_16V7KDIS@
CC10 220nF_0402_16V7KDIS@
CC11 220nF_0402_16V7KDIS@
CC12 220nF_0402_16V7KDIS@
CC13 220nF_0402_16V7KDIS@
CC14 220nF_0402_16V7KDIS@
CC15 220nF_0402_16V7KDIS@
CC16 220nF_0402_16V7KDIS@

CC25 220nF_0402_16V7KDIS@
CC26 220nF_0402_16V7KDIS@
CC27 220nF_0402_16V7KDIS@
CC28 220nF_0402_16V7KDIS@
CC29 220nF_0402_16V7KDIS@
CC30 220nF_0402_16V7KDIS@
CC31 220nF_0402_16V7KDIS@
CC32 220nF_0402_16V7KDIS@

+VCCP

12

RC2

24.9_0402_1%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

3

U

i

C1

3R1@

SA00005L52L

A

V8063801058401-SR0N9-L1-1.8G_BGA1023~D

U

i

C1

5R3@

U

i

C1

3R3@

SA00005L53L

A

V8063801058401-SR0N9-L1-1.8G_BGA1023~D

SA00005K62L

A

V8063801058002-SR0N8-L1-1.7G_BGA1023~D

C1

ELR1@

U

C

SA00006021L

A

V8062701085401-SR0VA-Q0-1.5G_BGA1023~D

UC1

PENR1@

SA00005ZZ1L

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

PEG_ICOMPI and RCOMPO signals should be shor ted and routed
with - max leng th = 500 mils - typical impeda nce = 43 mohms
PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils

- typical imped ance = 14.5 moh ms

PEG_GTX_C_HRX_N7 <24>
PEG_GTX_C_HRX_N6 <24>
PEG_GTX_C_HRX_N5 <24>
PEG_GTX_C_HRX_N4 <24>
PEG_GTX_C_HRX_N3 <24>
PEG_GTX_C_HRX_N2 <24>
PEG_GTX_C_HRX_N1 <24>
PEG_GTX_C_HRX_N0 <24>

PEG_GTX_C_HRX_P7 <24>
PEG_GTX_C_HRX_P6 <24>
PEG_GTX_C_HRX_P5 <24>
PEG_GTX_C_HRX_P4 <24>
PEG_GTX_C_HRX_P3 <24>
PEG_GTX_C_HRX_P2 <24>
PEG_GTX_C_HRX_P1 <24>
PEG_GTX_C_HRX_P0 <24>

PEG_HTX_C_GRX_N7 <24>
PEG_HTX_C_GRX_N6 <24>
PEG_HTX_C_GRX_N5 <24>
PEG_HTX_C_GRX_N4 <24>
PEG_HTX_C_GRX_N3 <24>
PEG_HTX_C_GRX_N2 <24>
PEG_HTX_C_GRX_N1 <24>
PEG_HTX_C_GRX_N0 <24>

PEG_HTX_C_GRX_P7 <24>
PEG_HTX_C_GRX_P6 <24>
PEG_HTX_C_GRX_P5 <24>
PEG_HTX_C_GRX_P4 <24>
PEG_HTX_C_GRX_P3 <24>
PEG_HTX_C_GRX_P2 <24>
PEG_HTX_C_GRX_P1 <24>
PEG_HTX_C_GRX_P0 <24>

C1

ELR3@

U

C

SA00006022L

A

V8062701085401-SR0VA-Q0-1.5G_BGA1023~D

UC1

PENR3@

SA00005ZZ2L

AV8062701084801-SR0V5-Q0-1.6G_BGA1023~D

2

U

i

C1

3VOSR1@

A

V8062701313000-SR0U3-J1-1.4G_BGA1023~D

U

i

C1

7R1@

A

V8063801057605-SR0N6-L1-1.9G_BGA1023~D

UC1I

i5R1@

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46
D50
D54
D58

D6
E25
E29

E3
E35
E40
F13
F15
F19
F29
F35
F40
F55

G51

G6

G61
H10
H14
H17
H21

H4

H53
H58

J1
J49
J55
K11
K21
K51

K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

M11
M15

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

VSS

SA00005UH1L

SA00005K53L

VSS_NCTF_10
VSS_NCTF_11

NCTF

VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

1

U

i

C1

3VOSR3@

SA00005UH2L

A

V8062701313000-SR0U3-J1-1.4G_BGA1023~D

U

i

C1

7R3@

SA00005K52L

A

V8063801057605-SR0N6-L1-1.9G_BGA1023~D

@

RC20

1 2

1K_0402_5%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

LA-9101P

LA-9101P

LA-9101P

1

5 57Wednesday, August 29, 2012

5 57Wednesday, August 29, 2012

5 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

4

3

2

1

+

DP_PREQ#_R
DP_PRDY#_R

DP_BPM#0
DP_BPM#1

12

VR1 TOPOLOGY

1 2

1 2

@

1 2

RC64

1 2

130_0402_1%

VCCP

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#_R

H_PM_SYNC

VCCPWRGOOD_0_R

VDDPWRGOOD_RVDDPWRGOOD

BUF_CPU_RST#

J

XDP

G

ND0
BSFN_A0

O
O

BSFN_A1
ND2

G
O

BSDATA_A0
BSDATA_A1

O
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01-L-D-A

CONN@

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

SP02000L900

UC1B

i5R1@

F49

PROC_SELECT #

C57

PROC_DETEC T#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPW RGOOD

BE45

SM_DRAMPWR OK

D44

RESET#

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

O
O

O

BSDATA_C0
BSDATA_C1

O

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

DBR#/HOOK7

+

3VALW

12

D D

CFG10<8>
CFG11<8>

H_CPUPWRGD H_CPUPWRGD_XDP

CFG0<8>

VGATE<15,52>

PCH_JTAG_TCK<13>

The resistor
for HOOK2 shoul d be
placed such tha t the
stub is very sm all

C C

B B

Place on BOTTOM(-4059,5169) area.

VDDPWRGOOD_R

Place close to CPU

A A

on CFG0 net

+VCCP

RC127 56_0402_1%

RC128 49.9_0402_1%~D

RC44 62_0402_5%~D

PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this
signal to determine if the processor is present

H_PECI

0.1U_0402_10V7K~D

0.1U_0402_25V6K

CC142

1

CC151

@

2

1

@

2

@

C49

R
1K_0402_5%

SYS_PWROK_XDP

1 2
1 2

1 2
1 2

PCH_SMBDATA<11,12,14,38>
PCH_SMBCLK<11,12,14,38>

@

1 2

@

1 2

1 2

1 2

0_0402_5% @

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

H_PROCHOT#<40,46>

place RC57 near CPU 300mils ~ 1530mils

H_THERMTRIP#<17>

place RC129 ne ar CPU 250mils ~2530 mils

H_CPUPWRGD<17>

1

CC141

0.1U_0402_25V6K

2

ESD request to reserve CC141

X
X

X
X

XDP_BPM#2
XDP_BPM#3

12

CFG10_R

RC130_0402_5% @

12

CFG11_R

RC150_0402_5% @

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

RC221K_0402_5% @

CFD_PWRBTN#_XDP

RC310_0402_5% @

RC381K_0402_5% @

SYS_PWROK_XDP

RC340_0402_5% @

XDP_TCK1

RC30

XDP_TCK_R

H_SNB_IVB#<17>

RC124 10K_0402_5%@

H_PECI<17,40>

RC57 56_0402_1%

RC130 0_0402_1%

H_PM_SYNC<15>

RC25 1K_0402_5%

@

G
BSFN_C0
BSFN_C1

G

GND5

GND7

GND9

GND11

GND13

GND15

TRST#

GND17

+

VCCP

2

ND1

4
6
8

ND3

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

CLK_CPU_ITP

42

CLK_CPU_ITP#

44
46

XDP_RST#_RXDP_HOOK2

48

XDP_DBRESET#

50
52

TD0

TDI

TMS

XDP_TDO

54

XDP_TRST#_R

56

XDP_TDI

58

XDP_TMS_R

60

MISC THERMAL PWR MANAGEMENT

CLOCKS

MISC

DDR3

JTAG & BPM

+

VCCP

Place near JXDP1

1 2

@

RC55 1K_0402_5%

1 2

RC33 0_0402_5%@

1 2

RC37 0_0402_5%@

1 2

RC39 0_0402_5%@

BCLK

BCLK#

DPLL_REF_CL K

DPLL_REF_CL K#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

0.1U_0402_16V7K

0.1U_0402_16V7K

1

1

CC36

CC35

2

2

CLK_CPU_ITP <14>
CLK_CPU_ITP# <14>PBTN_OUT#<15,40>

PLT_RST#

PCH_JTAG_TDO <13>

PCH_JTAG_TDI <13>
PCH_JTAG_TMS <13>

J3
H2

AG3

CLK_CPU_DPLL_R

AG1

CLK_CPU_DPLL#_R

Remove DPLL Ref clock (for eDP only)

N59
N58

AT30

H_DRAMRST#

BF44

SM_RCOMP0

BE43

SM_RCOMP1

BG43

SM_RCOMP2

CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>

1 2

RC65 1K_0402_1%

1 2

RC77 1K_0402_1%

H_DRAMRST# <7>

1 2

RC86140_0402_1%

1 2

RC8325.5_0402_1%

1 2

RC85200_0402_1%

DDR3 Compensation Signals

TCK
TMS

TDI

TDO

N53
N55

L56
L55
J58

M60
L59

K58

XDP_DBRESET#_R

G58
E55
E59
G55
G59
H60
J59
J61

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

1 2

RC125 0_0402_5%@

1 2

RC135 0_0402_5%@

1 2

RC136 0_0402_5%@

1 2

RC137 0_0402_5%@

1 2

RC126 0_0402_5%@

1 2

RC50 0_0402_5%@

1 2

RC92 0_0402_5%@

1 2

RC89 0_0402_5%

1 2

RC95 0_0402_5%@

1 2

RC91 0_0402_5%@

1 2

RC101 0_0402_5%@

1 2

RC102 0_0402_5%@

1 2

RC103 0_0402_5%@

1 2

RC97 0_0402_5%@

1 2

RC88 0_0402_5%@

1 2

RC87 0_0402_5%@

1 2

RC90 0_0402_5%@

1 2

RC96 0_0402_5%@

1 2

RC93 0_0402_5%@

1 2

RC94 0_0402_5%@

PM_DRAM_PWRGD<15>

+3V_PCH

XDP_PRDY#_R
XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

XDP_TDI
XDP_TDO

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

CFG12 <8>
CFG13 <8>
CFG14 <8>
CFG15 <8>

CH_PWROK<15,40>

P

S

YS_PWROK<15>

RC5

1 2

200_0402_1%

+VCCP

H_DRAMRST#

1

@

CC143

0.1U_0402_25V6K

2

Place close to CPU

C132

R

0_0402_1%

@

1 2

1 2

RC11 0_0402_1%

RUN_ON_CPU1.5VS3#<10,35>

PLT_RST#<16,32,38,40>

XDP_DBRESET# <15>

+

3VS

R

C129

@

1 2

0_0402_5%

D_PWG

@

XDP_DBRESET#_R

0.1U_0402_25V6K

Place close to CPU

12

@

C6

R

10K_0402_5%

U

1
2

74AHC1G09GW TSSOP 5P

RUN_ON_CPU1.5VS3#

CC144

+

3V_PCH

0.1U_0402_16V7K

CC33

1

C2

B

VCC
A
GND3Y

UC3

1

NC

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

2

5

4

@

1 2

13

D

2

G

S

+3VALW

1

2

5

VCC

4

BUFO_CPU_RST# BUF_CPU_RST#

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

XDP_DBRESET#_R

1

VCCPWRGOOD_0_R

2

Avoid stub in the PWRGD path
while placing r esistors RC25 & RC130

+

1.5V_CPU_VDDQ

12

C8

R
200_0402_1%

VDDPWRGOOD

RC8
CRB 1.1K
CHECK LIST 0.7 --> 4.75K

RC28

INTEL recommand 1.1K

39_0402_1%

PDG 0.71 rev -- >200

QC1

@

2N7002K_SOT23-3

0.1U_0402_16V7K

+VCCP

CC34

12

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1K_0402_5%

1 2

RC59
75_0402_5%

RC58

1 2

43_0402_1%

RC42

0.1U_0402_16V7K

12

@

1

@

RC4751_0402_5%

RC4651_0402_5%

RC4851_0402_5% @

RC10651_0402_5%

RC10551_0402_5%

RC10451_0402_5%

RC4510K_0402_5%

RC62

CC63

0_0402_5%

2

+VCCP

+3VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

LA-9101P

LA-9101P

LA-9101P

1

6 57Wednesday, August 29, 2012

6 57Wednesday, August 29, 2012

6 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

4

3

2

1

BD13
BF12

BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54

BA58
AW59
AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58
AG58
AG59
AM60

AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

U

C1D

i5R1@

AL4

S

B_DQ[0]

AL1

B_DQ[1]

S

AN3

S

B_DQ[2]

AR4

B_DQ[3]

S

AK4

S

B_DQ[4]

AK3

B_DQ[5]

S

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]
SB_DQ[18]
SB_DQ[19]

BF8

SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

B_CK[0]

S

S

B_CK#[0]
B_CKE[0]

S

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

_CLK_DDR2

M
M

_CLK_DDR#2

D

DR_CKE2_DIMMB

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

_CLK_DDR2 <12>

M
M

_CLK_DDR#2 <12>

DR_CKE2_DIMMB <12>

D

M_CLK_DDR3 <12>
M_CLK_DDR#3 <12>
DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12>
DDR_CS3_DIMMB# <12>

M_ODT2 <12>
M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

U

C1C

AP11

AJ10

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

i5R1@

AG6

S

A_DQ[0]

AJ6

A_DQ[1]

S
S

A_DQ[2]

AL6

A_DQ[3]

S
S

A_DQ[4]

AJ8

A_DQ[5]

S

AL8

SA_DQ[6]

AL7

SA_DQ[7]
SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]
SA_DQ[14]
SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

A_CK[0]

S

S

A_CK#[0]
A_CKE[0]

S

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AT40
AU40
BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

_CLK_DDR0

M
M

_CLK_DDR#0

D

DR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

_CLK_DDR0 <11>

M
M

_CLK_DDR#0 <11>
DR_CKE0_DIMMA <11>

D

M_CLK_DDR1 <11>
M_CLK_DDR#1 <11>
DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>
DDR_CS1_DIMMA# <11>

M_ODT0 <11>
M_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

D

DR_B_D[0..63]<12>

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>

D

DR_B_D0
DR_B_D1

D
D

DR_B_D2

D

DR_B_D3

D

DR_B_D4

D

DR_B_D5
DR_B_D6

D
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

D

DR_A_D[0..63]<11>

D D

C C

DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>

B B

DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>

D

DR_A_D0
DR_A_D1

D
D

DR_A_D2

D

DR_A_D3

D

DR_A_D4

D

DR_A_D5
DR_A_D6

D
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

+1.5V

4

12

RC108
1K_0402_5%

1 2

RC110 1K_0402_5%

1 2

@

RC111 0_0402_1%

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <14>

DRAMRST_CNTRL <11>

Place close to RC110

3

DDR3_DRAMRST#

1

@

CC145

0.1U_0402_25V6K

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

@

RC107 0_0402_5%

QC2

BSS138_SOT23

D

S

13

H_DRAMRST#<6>

A A

5

H_DRAMRST#

4.99K_0402_1%

RC109

12

G

2

1

CC37
.047U_0402_16V7K

2

DDR3_DRAMRST#_R

DRAMRST_CNTRL

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

Compal Secret Data

Compal Secret Data

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

LA-9101P

LA-9101P

LA-9101P

1

7 57Wednesday, August 29, 2012

7 57Wednesday, August 29, 2012

7 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

D D

CFG0<6>

+VCC_CORE

CFG10<6>
CFG11<6>

1 2

1 2

@

RC123
50_0402_1%

CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>

VCC_VAL_SENSE
VSS_VAL_SENSE

1 2

+VCC_GFXCORE_AXG

C C

@

RC120

50_0402_1%

B B

1 2

1 2

@

RC119
50_0402_1%

@

RC121
50_0402_1%

VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE

4

CFG0

T91PAD~D @

CFG2

T92PAD~D @

CFG4
CFG5
CFG6

CFG7

T66PAD~D @
T41PAD~D @

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

T69PAD~D @
T89PAD~D @

@

TP_VCC_DIESENSE

RC21 1K_0402_5%

T46PAD~D @
T36PAD~D @

T32PAD~D @

T34PAD~D @
T35PAD~D @

T40PAD~D @

T42PAD~D @

T47PAD~D @
T71PAD~D @

T72PAD~D @
T51PAD~D @
T68PAD~D @
T49PAD~D @

UC1E

i5R1@

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

RESERVED

DC_TEST_A4
DC_TEST_C 4
DC_TEST_D 3

DC_TEST_D 1
DC_TEST_A58
DC_TEST_A59

DC_TEST_C 59

DC_TEST_A61

DC_TEST_C 61

DC_TEST_D 61
DC_TEST_B D61
DC_TEST_B E61
DC_TEST_B E59
DC_TEST_B G61
DC_TEST_B G59
DC_TEST_B G58

DC_TEST_B G4

DC_TEST_B G3

DC_TEST_B E3

DC_TEST_B G1

DC_TEST_B E1

DC_TEST_B D1

RSVD28
RSVD29

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RSVD45

BE7

+SA_DIMM_VREFDQ

BG7

+SB_DIMM_VREFDQ

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4

TP_DC_TEST_A4

C4
D3

DC_TEST_C4_D3

D1

TP_DC_TEST_D1

A58

TP_DC_TEST_A58

A59
C59

DC_TEST_A59_C59

A61
C61

DC_TEST_A61_C61

D61

TP_DC_TEST_D61

BD61

TP_DC_TEST_BD61

BE61
BE59

DC_TEST_BE59_BE61

BG61
BG59

DC_TEST_BG59_BG61

BG58

TP_DC_TEST_BG58

BG4

TP_DC_TEST_BG4

BG3
BE3

DC_TEST_BE3_BG3

BG1
BE1

DC_TEST_BE1_BG1

BD1

TP_DC_TEST_BD1

3

+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ

2

FG Straps for Processor

C

C

FG2

12

RC116
1K_0402_1%

1

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

12

@

definition matches socket pin map definition

0:Lane Reversed

*

Display Port Presence Strap

*

CFG4

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2

*

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG4

12

RC112
1K_0402_1%@

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6

CFG5

1K_0402_1%

RC114

12

12

RC113
1K_0402_1%

@

T14 PAD~D@
T15 PAD~D@
T16 PAD~D@
T17 PAD~D@

T22 PAD~D@
T21 PAD~D@
T19 PAD~D@
T20 PAD~D@
T18 PAD~D@

T23 PAD~D@

T28 PAD~D@
T27 PAD~D@
T25 PAD~D@
T26 PAD~D@

T29 PAD~D@

RC117

1K_0402_1%

T121 PAD~D@

T118 PAD~D@
T119 PAD~D@

T120 PAD~D@
T122 PAD~D@

T132 PAD~D@
T123 PAD~D@

T124 PAD~D@

12

@

RC115

1K_0402_1%

CFG7

12

@

RC118
1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediately

*

CFG7

following xxRESETB de assertion

0: PEG Wait for BIOS for training

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

LA-9101P

LA-9101P

LA-9101P

1

8 57Wednesday, August 29, 2012

8 57Wednesday, August 29, 2012

8 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

U

C1F

VCC_CORE

D D

ULV 17W , Max Current
in Turbo Mode or HFM

C C

B B

A A

+

3

3A

i5R1@

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

P

OWER

CORE SUPPLY

4

CCIO[1]

V
V

CCIO[3]
CCIO[4]

V
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]

VCCIO[30]
VCCIO[31]
VCCIO[32]

PEG IO AND DDR IO

VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50

VCCIO51

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

RAILS

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

8.5A

+

VCCP

+VCCP

1 2

RC140 0_0402_5%@

+VCCP

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VCCSENSE_R
VSSSENSE_R

+3VS

RC141
10K_0402_5%@

1 2

VCCP_PWRCTRL

1U_0402_6.3V6K

CC573

1

2

RC147 close to CPU

12

RC147
130_0402_1%

1 2

RC142 43_0402_1%<BOM Structure>

1 2

RC146 0_0402_1%@

1 2

RC144 0_0402_1%@

CAD Note: Place the PU
resistors close to CPU
RC147 close to CPU 300~1500mil s

1 2

RC139 0_0402_1%@

1 2

RC122 0_0402_1%@

12

RC98 10_0402_1%

1 2

RC133 10_0402_1%

Place RC98 close to CPU

3

VCCP_PWRCTRL Pull high on power side

+VCCP

Note: Place th e PU resistors close to CPU
RC145 close to CPU 300~1500mil s

12

RC145
75_0402_5%

VR_SVID_ALRT# <52>
VR_SVID_CLK <52>
VR_SVID_DAT <52>

+VCC_CORE

12

RC138
100_0402_1%

+VCCP

VCCIO_SENSE <49>
VSSIO_SENSE_R <49>

12

RC131
100_0402_1%

VCCSENSE <52>
VSSSENSE <52>

2

I

ccmax current c hanged for PDDG Rev0.7

CPU Power Rail Table

Voltage Rail

VCC

VCCIO

VAXG

VCCPLL

VDDQ

VCCSA

+1.5V_MEM 1.5

Description

*

5A to Mem cont roller(+1.5V_CP U_VDDQ)
5-6A to 2 DIMMs /channel
2-5A to +1.5V_R UN & +0.75V_DDR _VTT

Voltage

0.65-1.3

0.0-1.1

0.65-0.9

1.05/1

1.8

1.5

S0 Iccmax
Current (A)

53

8.5

33

1.2

5

6

12-16

1

*

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

LA-9101P

LA-9101P

LA-9101P

1

9 57Wednesday, August 29, 2012

9 57Wednesday, August 29, 2012

9 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+

RC76

100_0402_1%

1U_0402_6.3V6K

1

CC174

2

1U_0402_6.3V6K

1

2

B

Q

C7B

5

@

12

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CC261

1

2

+_BIAS

12

R

C151

470K_0402_5%

R

UN_ON_CPU1.5VS3

3

4

RUN_ON_CPU1.5VS3# <35,6>

33A

+VCC_GFXCORE_AXG

1.2A

CC175

6A

1U_0402_6.3V6K

CC260

4

3VALW

+

12

C143

R
100K_0402_5%

CC264

1

2

+1.8VS

330U_D2_2.5VM_R6M~D

1U_0402_6.3V6K

1U_0402_6.3V6K

CC263

1

2

2N7002DW-7-F_SOT363-6

1

CC176

+

2

CC262

1

2

D D

RC149

0_0402_5%

+VCCSA

C
C172

1 2

@

1 2

@

RC148

0_0402_1%

VCC_AXG_SENSE<52>
VSS_AXG_SENSE<52>

330U_D2_2VM_R6M~D

10U_0603_6.3V6M

1

C

+

C171

2

5

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC170

CC169

2

2

SUSP#<35,40,48,49,50>

CPU1.5V_S3_GATE<40>

C C

B B

A A

61

2

1

@

CC40

0.1U_0402_10V7K~D

2

+VCC_GFXCORE_AXG

RC99

100_0402_1%

RC100

100_0402_1%

10U_0603_6.3V6M

1

1

CC168

CC183

2

2

R

UN_ON_CPU1.5VS3#

QC7A
2N7002DW-7-F_SOT363-6

12

12

10U_0603_6.3V6M

1

2

Q

1.5V

C3

AO4304L_SO8

8
7
6
5

4

12

i5R1@

1

2

POWER

C150

R

2M_0402_5%~D

UC1G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

+

1.5V_CPU_VDDQ

1
2
3

1

CC38

2

0.1U_0603_50V_X7R
10U_0805_10V6K

CC39

VREF

DDR3 - 1.5V RAILS

GRAPHICS

LINES

SENSE

QUIET RAILS

1.8V RAIL

VSS_SENSE_VDDQ

SENSE LINES

SA RAIL

lines

VCCSA VID

12

RC152

20K_0402_5%

SM_VREF

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]

VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

VCCDQ[1]
VCCDQ[2]

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

+V_SM_VREF_CNT

AY43

+V_SM_VREF should
have 10 mil trace width

5A

+1.5V_CPU_VDDQ

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

1

2

1

2

+1.5V_CPU_VDDQ

1U_0402_6.3V6K

1

2

3

10U_0603_6.3V6M

CC250

CC574

V_DDR_SMREF

1.5V

+

+

12

R

C80

1K_0402_1%@

12

R

C81

1K_0402_1%@

RUN_ON_CPU1.5VS3

12

CC178 0.1U_0402_10V7K~D

12

CC179 0.1U_0402_10V7K~D

12

CC149 0.1U_0402_10V7K~D

12

CC150 0.1U_0402_10V7K~D

10U_0603_6.3V6M

10U_0603_6.3V6M

CC161

CC252

1

2

1

CC162

2

1U_0402_6.3V6K

CC253

1

2

VCCSA_VID0 <51>
VCCSA_VID1 <51>

10U_0603_6.3V6M

1

CC163

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

1

1

CC181

CC180

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC251

1

2

VCCSA_SENSE <51>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6A

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC164

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC254

CC255

1

2

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

330U_D2_2VM_R6M~D

10U_0603_6.3V6M

1

1

CC165

CC256

1

2

CC166

2

1U_0402_6.3V6K

CC257

1

2

CC167

+

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC258

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

R

C134 0_0402_5%@

NTR4503NT1G_SOT23-3~D

1U_0402_6.3V6K

CC259

1

2

Deciphered Date

Deciphered Date

Deciphered Date

2

1 2

Q

C5

@

1

3

2

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

A9

AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AC6
AD17
AD20

AD4
AD61
AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7
AH4

AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

AM13
AM20
AM22
AM26
AM30
AM34

1.5V_CPU_VDDQ

+

12

R

C84

1K_0402_1%

+

V_SM_VREF_CNT

12

R

C78

1K_0402_1%

UC1H

i5R1@

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

AV8063801058002-SR0N8-L1-1.7G_BGA1023~D

VSS

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

LA-9101P

LA-9101P

LA-9101P

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

1

0.4

0.4

10 57Wednesday, August 29, 2012

10 57Wednesday, August 29, 2012

10 57Wednesday, August 29, 2012

0.4

5

4

3

2

1

+

1.5V

DIMM1

J

+

CD21

1

2

2.2U_0603_6.3V6K

1

2

V_DDR_REFA

DR_A_D0

D
D

DR_A_D1

CD2

D

DR_A_D2

D

DR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

RD6 10K_0402_5%

1 2

RD7 10K_0402_5%

CD22

+0.75VS

+

V_DDR_REFA

+

@

CD13

V_DDR_REFA

220U_2V_D2

1

CD14

+

2

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

CD1

2

DDR_CKE0_DIMMA<7> DDR_CKE1_DIMMA <7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7>
DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

0.1U_0402_16V7K

+3VS

1

2

D

DR_A_DQS#[0..7]<7>

D

D D

C C

B B

A A

DR_A_DQS[0..7]<7>

DR_A_D[0..63]<7>

D

DR_A_MA[0..15]<7>

D

Layout Note:
Place near JDIMM1

+1.5V

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.5V

10U_0603_6.3V6M

+0.75VS

CD4

C

1

1

D3

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD8

C

1

1

D7

2

2

Layout Note:
Place near JDIMM1.203,204

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD18

C
D17

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD5

1

2

10U_0603_6.3V6M

CD9

CD10

1

1

2

2

1U_0402_6.3V6K

1

CD19

2

+

1.5V

12

R

D1

1K_0402_1%

12

RD3
1K_0402_1%

All VREF traces should
have 10 mil trace width

CD6

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD11

CD12

1

2

1U_0402_6.3V6K

1

2

1

1

2

2

CD20

1

V

REF_DQ

3

V

SS2

5

D

Q0

7

D

Q1

9

SS4

V

11

D

M0

13

SS5

V

15

D

Q2

17

Q3

D

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

BELLW_80001-5021
CONN@

SP07000LZ00

V

V

QS#0

D

D

V

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+

1.5V

2

SS1

4

D

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DR_A_D4
DR_A_D5

D

DR_A_DQS#0

D
D

DR_A_DQS0

D

DR_A_D6

D

DR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

+VREF_CA

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1

CD15

2

PCH_SMBDATA <12,14,38,6>
PCH_SMBCLK <12,14,38,6>

DDR3_DRAMRST# <12,7>

+1.5V

12

12

1

CD16

2

RD4
1K_0402_1%

RD5
1K_0402_1%

M3

DRAMRST_CNTRL<7>

+SA_DIMM_VREFDQ

DRAMRST_CNTRL

+SB_DIMM_VREFDQ

DRAMRST_CNTRL

RD8 0_0402_5%@

RD9 0_0402_5%@

1 2

S

G

2

1 2

S

G

2

QD1

D

13

BSS138_NL_SOT23-3

QD2

D

13

BSS138_NL_SOT23-3

+V_DDR_REFA

+V_DDR_REFB

D

Q4

D

Q5

SS3

QS0
SS6
D

Q6
Q7

D

DM1

DM2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

LA-9101P

LA-9101P

LA-9101P

1

11 57Wednesday, August 29, 2012

11 57Wednesday, August 29, 2012

11 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

4

3

2

1

+

1.5V

J

+

1.5V

D D

DDR_B_DQS#[0..7]<7>

DDR_B_DQS[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_MA[0..15]<7>

Layout Note:
Place near JDIMMB

C C

B B

A A

+1.5V

1U_0402_6.3V6K

1

2

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

CD32

1

2

Layout Note:
Place near JDIMMB.203,204

+0.75VS

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD28

CD29

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD33

CD34

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD42

CD43

2

1U_0402_6.3V6K

CD30

CD31

1

1

2

2

10U_0603_6.3V6M

CD35

1

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

@

1

CD36

1

2

CD44

CD38

CD37

1

1

2

1U_0402_6.3V6K

1

CD45

2

+

2

2

12

D15

R
1K_0402_1%

V_DDR_REFB

+

12

RD16
1K_0402_1%

220U_2V_D2

CD39

V_DDR_REFB

+

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

2.2U_0603_6.3V6K

12

RD19

10K_0402_5%

0.1U_0402_16V7K

1

CD27

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

+3VS

10K_0402_5%

+

V_DDR_REFB

D

DR_B_D0
DR_B_D1

D

1

CD26

D

DR_B_D2

2

DR_B_D3

D

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

2.2U_0603_6.3V6K

0.1U_0402_16V7K

12

RD20

+0.75VS

CD46

CD47

1

1

2

2

DIMM2

1

V

REF_DQ

3

V

SS

5

D

Q0

7

Q1

D

9

V

SS

11

M0

D

13

V

SS

15

Q2

D

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

CONN@

SP07000P700

D

QS0#
D

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

+

1.5V

2

V

SS

4

DR_B_D4

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

D
D

DR_B_D5

D

DR_B_DQS#0

D

DR_B_DQS0

D

DR_B_D6
DR_B_D7

D

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31DDR_B_D27

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DDR3_DRAMRST# <11,7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

0.1U_0402_16V7K

2.2U_0603_6.3V6K

1

CD40

2

PCH_SMBDATA <11,14,38,6>
PCH_SMBCLK <11,14,38,6>

RD17
1K_0402_1%

1

CD41

2

+1.5V

12

12

RD18
1K_0402_1%

D

Q4

D

Q5
SS

V

QS0
V

SS
Q6

D
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2

A0
VDD
CK1

VDD
BA1

VDD
S0#

VDD

NC

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

LA-9101P

LA-9101P

LA-9101P

1

12 57Wednesday, August 29, 2012

12 57Wednesday, August 29, 2012

12 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

CH_RTCX1

1

C

H4

18P_0402_50V8J

2

1 2

RH5 33_0402_5%

1 2

RH6 33_0402_5%

1 2

RH7 33_0402_5%

1 2

RH8 1M_0402_5%

ME_EN<40>

+3V_PCH +3V_PCH+3V_PCH

12

@

RH19
200_0402_1%

PCH_JTAG_TMS_R PCH_JTAG_TDI_RPCH_JTAG_TDO_R

12

RH25
100_0402_1%

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

RH35 51_0402_5%

PCH_SPI_WP#

PCH_SPI_HOLD#

P

P

CH_RTCX2

XTAL@

+RTCVCC

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

1 2

RH11 1K_0402_1%

1 2

RH15 33_0402_5%

12

RH20
200_0402_1%

12

100_0402_1%

1 2

RH44 0_0402_5%

1 2

RH48 0_0402_5%

1 2

RH70 0_0402_5%

1 2

CH_RTCX1_R<23>

P

+RTCVCC

1U_0603_10V6K

1 2

RH3 20K_0402_5%

1 2

RH4 20K_0402_5%

1U_0603_10V6K

@

RH26

@

@

@

H30 0_0402_5%

R

1 2

RH2

1

CH5

2

1

CH6

2

+5VS

G

2

13

D

S

QH1BSS138_SOT23

1 2

@

RH9 0_0402_5%

HDA_SDOUT

HDA_SDOUT

PCH_JTAG_TMS_R

PCH_JTAG_TDI_R

PCH_JTAG_TDO_R

close to YH1

GCLK@

1 2

1M_0402_5%

12

CMOS

CLRP1

SHORT PADS

12

CLRP2

SHORT PADS

ME CMOS

CLP1 & CLP2 place near DIMM

HDA_SYNC

3.3K_0402_5%

PCH_SPI_SO

CH_RTCX1

P

SM_INTRUDER#

HDA_SPKR<33>

HDA_SDIN0<33>

NEC flash issu e.

+3V_PCH

@

RH262

1 2

@

1 2

RH36 0_0402_1%
RH37 33_0402_5%

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS_R

PCH_JTAG_TDI_R

PCH_JTAG_TDO_R

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

3.3K_0402_5%

12

XTAL@

1 2

H1 10M_0402_5%

R

Y

H1

1 2

32.768KHZ_12.5PF_9H03200019

D D

XTAL@

1
8P_0402_50V8J

1

C

H3

XTAL@

2

keep away hot s pot

HDA_BITCLK_AUDIO<33>

HDA_RST_AUDIO#<33>

C C

HDA_SYNC_AUDIO<33>

HDA_SDOUT_AUDIO<33>

12

@

RH18
200_0402_1%

12

RH24
100_0402_1%

B B

PCH_JTAG_TCK<6>

PCH_JTAG_TMS<6>

PCH_JTAG_TDI<6>

PCH_JTAG_TDO<6>

PCH_JTAG_TCK

+3V_PCH

1 2

RH38 3.3K_0402_5%

1 2

A A

RH40 3.3K_0402_5%

4

C

H1 10P_0402_50V8J

C

H2 10P_0402_50V8J

Reserve for RF please close t o UH1

R1@

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82HM76-SLJ8E-C1_BGA989~D

+3V_PCH

@

RH33

SPI ROM FOR WIN8( 2MByte )

1 2

PCH_SPI_CS1#_RPCH_SPI_CS1#

PCH_SPI_WP#

EON
EN25QH16-104HIP_SO8

@

12

@

12

SA00005FH1L

RTCIHDA

JTAG

SPI

UH2

X76@

1

CS#

VCC

2

SO

HOLD#

3

WP#

SCLK

4

GND

EN25QH16-104HIP_SO8

H

DA_SDOUT

H

DA_BIT_CLK

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

8
7

PCH_SPI_HOLD#PCH_SPI_SO_R

6

PCH_SPI_CLK_R

5

PCH_SPI_SI_R

SI

LDRQ0#

SERIRQ

+3V_PCH

CH11

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

U

R

H1

BD82HM76-SLJ8E-C1_BGA989~D

SA00005FH2L

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

RH268 0_0402_1%

BBS_BIT0_R

0.1U_0402_16V7K

1

2

12

RH27 33_0402_5%

12

RH39 33_0402_5%

1

CH99

@

10P_0402_50V8J

2

3

3@

LPC_AD0 <40>
LPC_AD1 <40>
LPC_AD2 <40>
LPC_AD3 <40>

LPC_FRAME# <40>

SERIRQ <40>

1 2

CH7 0.01U_0402_16V7K

1 2

CH8 0.01U_0402_16V7K

PCH_SATALED# <38>

@

12

10K_0402_5%

PCH_SPI_CLK
PCH_SPI_SI

+1.05VS_VCC_SATA

+1.05VS_SATA3

1 2

RH21 37.4_0402_1%

1 2

RH22 49.9_0402_1%

1 2

RH28 750_0402_1%~D

1 2

RH29

HDD_DET#HDD_DET#_R

+3VS

SATA_PRX_DTX_N0 <41>
SATA_PRX_DTX_P0 <41>
SATA_PTX_DRX_N0_C <41>
SATA_PTX_DRX_P0_C <41>

SATA_PRX_DTX_N2 <41>
SATA_PRX_DTX_P2 <41>
SATA_PTX_DRX_N2 <41>
SATA_PTX_DRX_P2 <41>

HDD_DET# <41>

PCH_SPI_CS0#

3.3K_0402_5%

@

1 2

RH264 0_0402_1%

12

RH265 33_0402_5%

2

+

330K_0402_5%

P

CH_INTVRMEN

H13

R

P

CH_INTVRMEN

H16

R

INTVRMEN

ntegrated VRM e nable

H：I

*

L

：

Integrated VRM disable

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

12

12

@

330K_0402_5%

RTCVCC

H=>Flash Descriptor Security will be overridden

HDD

ODD

JP12

+CHGRTC

+3V_PCH

2

JUMP_43X39

SPI ROM FOR ME

PCH_SPI_CS0#_R

1 2

PCH_SPI_SO_LPCH_SPI_SO

( 4MByte )

UH6

X76@

1

CS#

2
3
4

EON
EN25Q32B-104HIP_SO8

VCC

SO/SIO1

HOLD#

WP#

SCLK

GND

SI/SIO0

EN25Q32B-104HIP_SO8

8
7

PCH_SPI_HOLD#

6

PCH_SPI_CLK_L

5

PCH_SPI_SI_L PCH_SPI_SI

@

RH263

1

S

ERIRQ

H10 10K_0402_5%

R

H

DD_DET#

R

H12 10K_0402_5%

P

CH_SATALED#

H14 10K_0402_5%

R

HDA_SPKR

RH17 1K_0402_5%@

LOW=Default
HIGH=No Reboot

*

HDA_SDOUT

RH23 1K_0402_5%@

Low = Disabled

*

High = Enabled

HDA_SYNC

This signal has a weak interna l pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for Hu ron River platf rom

HDA_SYNC

RH32 1K_0402_5%

+3V_PCH

12

RTC Battery

+RTCBATT

+CHGRTC

3

1 2

2

1

1

CH12
1U_0603_10V6K

2

112

+3V_PCH

CH98

+3VLP

0.1U_0402_16V7K

1

2

12

RH266 33_0402_5%

12

RH267 33_0402_5%

W=20mils

W=20mils

PCH_SPI_CLKPCH_SPI_WP#

12

12

12

12

+3V_PCH

12

RH34
1K_0402_5%

W=20mils

DH1
BAT54CW_SOT323-3

+RTCVCC

+

3VS

3VS

+

ZZZ9

SPIEON@

X7644031L07

5

4

ZZZ10

SPIWB@

X7644031L08

ZZZ11

SPIMXIC@

X7644031L09

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA/HDA/SPI/LPC

PCH (1/8) SATA/HDA/SPI/LPC

PCH (1/8) SATA/HDA/SPI/LPC

LA-9101P

LA-9101P

LA-9101P

1

13 57Wednesday, August 29, 2012

13 57Wednesday, August 29, 2012

13 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

4

3

2

1

MBCLK

6 1

QH2A

RH78

1 2

@

0_0402_5%

DMN66D0LDW-7_SOT363-6

6 1

@

QH7A

DMN66D0LDW-7_SOT363-6

SML1CLK

SML1DATA

S

S

MBDATA

S

ML0CLK

S

ML0DATA

S

ML1CLK

S

ML1DATA

S

MBALERT#

CH_HOT#

P

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH

2

3

QH2B

RH82

1 2

@

0_0402_5%

2

3

@

QH7B

+3V_PCH

2

DMN66D0LDW-7_SOT363-6

QH3A

U

H1B

P

12

12

12

12

CIE_PRX_LANTX_N1

P

CIE_PRX_LANTX_P1

P

CIE_PTX_LANRX_N1_C
CIE_PTX_LANRX_P1_C

P

CIE_PRX_WLANTX_N2

P
P

CIE_PRX_WLANTX_P2

P

CIE_PTX_WLANRX_N2_C

P

CIE_PTX_WLANRX_P2_C

PCIE_LAN#
PCIE_LAN

LAN_CLKREQ#

PCIE_WLAN#
PCIE_WLAN

WLAN_CLKREQ#

GPIO20

GPIO25

GPIO26

GPIO44

GPIO56

GPIO45

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITPCLK_BCLK_ITP

4

P

CIE_PRX_LANTX_N1<32>

P

1

0/100 LAN --->

D D

WLAN (Mini Card)--->

C C

10/100 LAN --->

WLAN (Mini Card)--->

B B

XTAL@

RH89 1M_0402_5%

A A

12P_0402_50V8J

CH27

XTAL@

1

2

5MHZ_10PF_7V25000014
2

5

CIE_PRX_LANTX_P1<32>

P

CIE_PTX_LANRX_N1<32>

P

CIE_PTX_LANRX_P1<32>

P

CIE_PRX_WLANTX_N2<38>

P

CIE_PRX_WLANTX_P2<38>
CIE_PTX_WLANRX_N2<38>

P
P

CIE_PTX_WLANRX_P2<38>

*PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2

CLK_CPU_ITP#<6>
CLK_CPU_ITP<6>

XTAL25_IN

12

XTAL25_OUT

1

3

SC
O

ND
G

2

1

CH28

YH2

OSC

12P_0402_50V8J

XTAL@

XTAL@

2

GND

4

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

LAN_CLKREQ#<32>

CLK_PCIE_WLAN#<38>
CLK_PCIE_WLAN<38>

WLAN_CLKREQ#<38>

CLK_CPU_ITP#
CLK_CPU_ITP

PCH_X1<23>

1 2

C

H19 0.1U_0402_10V7K~D

1 2

C

H20 0.1U_0402_10V7K~D

1 2

C

H21 0.1U_0402_10V7K~D

1 2

H22 0.1U_0402_10V7K~D

C

RH67 0_0402_1%@
RH68 0_0402_1%@

RH69 10K_0402_5%

+3V_PCH

RH75 0_0402_1%@
RH76 0_0402_1%@
RH77 10K_0402_5%

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

RH79 10K_0402_5%

RH74 10K_0402_5%

RH66 10K_0402_5%

RH83 10K_0402_5%

RH84 10K_0402_5%

RH88 10K_0402_5%

RH90 10K_0402_5%

1 2

RH91 0_0402_1%@

1 2

RH92 0_0402_1%@

close to YH2

1 2

RH41 0_0402_5%

GCLK@

1 2
1 2

1 2
1 2

1 2

1 2

1 2

1 2

1 2

XTAL25_IN

BG34

P

ERN1

BJ34

P

ERP1

AV32

P

ETN1

AU32

P

ETP1

BE34

ERN2

P

BF34

P

ERP2

BB32

ETN2

P

AY32

P

ETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_ B_N

AB40

CLKOUT_PEG_ B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82HM76-SLJ8E-C1_BGA989~D

R1@

@

@

CH25

RH63

22P_0402_50V8J

12

RH65

@

1 2

CH26

22P_0402_50V8J

1 2

12

@

CLK_PCH_14M

33_0402_5%

CLK_PCI_LPBACK

33_0402_5%

Reserve for EM I please close to
UH1

SMBUSController

SML1ALERT# / PCH HOT# / GPIO74

PCI-E*

CLOCKS

S

MBALERT# / GPIO11

ML0ALERT# / GPIO60

S

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_ N
CLKOUT_DP_ P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

3

E12

S

MBALERT#

H14

MBCLK

S

MBCLK

MBDATA

S

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

S

C9

MBDATA

S

A12

D

RAMRST_CNTRL_PCH

C8

SML0CLK

G12

SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

M7

T11

No support iAMT

P10

M10

PEG_A_CLKRQ#

AB37

CLK_PEG_VGA#

AB38

CLK_PEG_VGA

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12
AM13

BF18

CLKIN_DMI#

BE18

CLKIN_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLKIN_DOT96#

E24

CLKIN_DOT96

AK7

CLKIN_SATA#

AK5

CLKIN_SATA

K45

CLK_PCH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_14M_R

H47

CLK_LAN_25M_R

K49

DGPU_PRSNT#

LAN_X1<23>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Total device

1 2

RH125

22_0402_5%

RH270 22_0402_5%

RH269 10K_0402_5%

RH261
10K_0402_5%DIS@

1 2

MEMORY

RAMRST_CNTRL_PCH <7>

D

PCH_HOT# <40>

20090512
add double mosfet prevent
ATI M92 electric leakage

+3V_PCH

RH64
10K_0402_5%

1 2

CLK_PEG_VGA# <24>
CLK_PEG_VGA <24>

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1 2

RH85 90.9_0402_1%

12

@

12

UMA@

close to RH270

1 2

RH31 0_0402_5%

GCLK@

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

PEG_A_CLKRQ# <25>

CLK_PCI_LPBACK <16>

+1.05VS_VCCDIFFCLKN

T53 PAD~D@

T54 PAD~D@

CLK_LAN_25M <32>

+3VS

CLK_LAN_25M

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

SMBCLK

DMN66D0LDW-7_SOT363-6

SMBDATA

SMBCLK

DMN66D0LDW-7_SOT363-6

SMBDATA

1 2

R

H45 2.2K_0402_5%

1 2

H46 2.2K_0402_5%

R

1 2

R

H47 2.2K_0402_5%

1 2

R

H49 2.2K_0402_5%

1 2

R

H50 2.2K_0402_5%

1 2

R

H51 2.2K_0402_5%

1 2

R

H52 10K_0402_5%

1 2

RH86 10K_0402_5%

1 2

RH53 1K_0402_5%

1 2

RH54 10K_0402_5%

1 2

RH55 10K_0402_5%

1 2

RH56 10K_0402_5%

1 2

RH57 10K_0402_5%

1 2

RH58 10K_0402_5%

1 2

RH59 10K_0402_5%

1 2

RH60 10K_0402_5%

1 2

RH61 10K_0402_5%

1 2

RH62 10K_0402_5%

+3VS

+3VS +3VS

+3VS

RH71

2.2K_0402_5%

5

4

PCH_SMBCLK

PCH_SMBDATA

RH80

2.2K_0402_5%

@

5

4

61

5

4

DMN66D0LDW-7_SOT363-6

QH3B

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

1 2

1 2

RH87 0_0402_1%

1 2

RH93 0_0402_1%

1 2

1 2

3

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH (2/8) PCIE/SMBUS/CLK

PCH (2/8) PCIE/SMBUS/CLK

PCH (2/8) PCIE/SMBUS/CLK

LA-9101P

LA-9101P

LA-9101P

RH72

2.2K_0402_5%

PCH_SMBCLK <11,12,38,6>

PCH_SMBDATA <11,12,38,6>

@

@

RH81

2.2K_0402_5%

@

TP_SMBCLK <39>

TP_SMBDATA <39>

PCH_SMLCLK <40>

PCH_SMLDATA <40>

1

+

3V_PCH

TP_SMBCLK

TP_SMBDATA

0.4

0.4

14 57Wednesday, August 29, 2012

14 57Wednesday, August 29, 2012

14 57Wednesday, August 29, 2012

0.4

5

U

H1C

MI_CTX_PRX_N0

D D

Reserve for ESD

CH105

12

0.1U_0402_16V7K

SYS_PWROK_R

Please close to PCH

C C

PM_DRAM_PWRGD<6>

Reserve for ESD

PBTN_OUT#

1

@

CH103

0.1U_0402_16V7K

Place close to PCH

B B

A A

2

GPIO72

RI#

PCIE_WAKE#

AC_PRESENT_R

SUSWARN#

WAKE#

EC_RSMRST#

D

MI_CTX_PRX_N0<5>

D

MI_CTX_PRX_N1<5>

D

MI_CTX_PRX_N2<5>

D

MI_CTX_PRX_N3<5>

D

MI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

+1.05VS

XDP_DBRESET#<6>

PCH_PWROK

EC_RSMRST#<40>

PBTN_OUT#<40,6>

ACIN<25,40,45,46>

1 2

RH116 10K_0402_5%

1 2

RH117 10K_0402_5%

1 2

RH118 10K_0402_5%@

1 2

RH121 200K_0402_5%

1 2

RH124 10K_0402_5%

1 2

RH126 10K_0402_5%

1 2

RH127 10K_0402_5%

PCH_PWROK<40,6>

VGATE<52,6>

RH99 49.9_0402_1%

RH100 750_0402_1%~D

4mil width and place
within 500mil of the PCH

T57PAD~D

SYS_PWROK

PCH_PWROK

D
D

MI_CTX_PRX_N1

D

MI_CTX_PRX_N2

D

MI_CTX_PRX_N3

MI_CTX_PRX_P0

D
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

RH104 0_0402_1%

RH105 0_0402_1%

RH106 0_0402_1%

RH108 0_0402_1%

RH110 0_0402_1%

1 2

XDP_DBRESET#

1 2

@

1 2

@

1 2

@

PM_DRAM_PWRGD

1 2

@

1 2

@

DH4

1 2

RB751V-40_SOD323-2

+3V_PCH

1

CH30

0.1U_0402_16V7K

2

1

IN1

2

IN2

DMI_IRCOMP

RBIAS_CPY

PCH_RSMRST#_R

GPIO72

+3VS

BC24
BE20
BG18
BG20

BE24
BC20
BJ18
BJ20

AW24
AW20

BB18
AV18

AY24
AY20
AY18
AU18

BJ24

BG25

BH21

C12

K3

SYS_PWROK_R

SUSWARN#

AC_PRESENT_R

RI#

P12

L22

L10

B13

C21

K16

E20

H20

E10

A10

DSWODVREN

DSWODVREN

5

UH3

VCC

4

SYS_PWROK

OUT

GND

MC74VHC1G08DFT2G_SC70-5

3

MI0RXN

D
D

MI1RXN
MI2RXN

D
D

MI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SU SPWRDNACK/GPIO30

PWRBTN#

ACPRESENT / GPIO31

BATLOW# / GPIO72

RI#

BD82HM76-SLJ8E-C1_BGA989~D

R1@

DSWODVREN - On Die DSW VR Enab le

H：Enable

*

L：Disable

4

DI_RXN0

F
F

DI_RXN1
DI_RXN2

F
F

DI_RXN3
DI_RXN4

F
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

DMI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

System Power Management

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

SYS_PWROK <6>

12

12

RH119 330K_0402_5%

RH122 330K_0402_5%@

WAKE#

+RTCVCC

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DI_CTX_PRX_N0

F
F

DI_CTX_PRX_N1

F

DI_CTX_PRX_N2

F

DI_CTX_PRX_N3

F

DI_CTX_PRX_N4
DI_CTX_PRX_N5

F
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

1 2

@

RH128

1 2

WAKE#

RH103 0_0402_5%

PM_CLKRUN#

SUS_STAT#

1 2

SUSCLK

@

RH107 0_0402_1%

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

If not using i ntegrated
LAN,signal may be left as NC.

@

3

F

DI_CTX_PRX_N0 <5>

F

DI_CTX_PRX_N1 <5>

F

DI_CTX_PRX_N2 <5>

F

DI_CTX_PRX_N3 <5>
DI_CTX_PRX_N4 <5>

F
F

DI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

PCH_RSMRST#_RPCH_DPWROK

0_0402_1%

T58 PAD~D

T59 PAD~D

PCIE_WAKE# <32,40>

SUSCLK_R <40>

PM_SLP_S5# <40>

PM_SLP_S4# <40>

PM_SLP_S3# <40>

H_PM_SYNC <6>

Can be left NC when IAMT is
not support on the platfrom

SUSCLK

Reserve for RF please close t o UH1

CH29

@

10P_0402_50V8J

PCH_ENVDD<21>

LVDS_DDC_CLK<21>

LVDS_DDC_DATA<21>

LVDS_ACLK-<21>
LVDS_ACLK+<21>

LVDS_A0-<21>
LVDS_A1-<21>
LVDS_A2-<21>

LVDS_A0+<21>
LVDS_A1+<21>
LVDS_A2+<21>

LVDS_BCLK-<21>
LVDS_BCLK+<21>

LVDS_B0-<21>
LVDS_B1-<21>
LVDS_B2-<21>

LVDS_B0+<21>
LVDS_B1+<21>
LVDS_B2+<21>

12

+3VS

1 2

RH133 2.2K_0402_5%

1 2

RH135 2.2K_0402_5%

1 2

RH136 8.2K_0402_5%@

1 2

RH137 2.2K_0402_5%

1 2

RH138 2.2K_0402_5%

1 2

RH233 2.2K_0402_5%

1 2

RH234 2.2K_0402_5%

1 2

RH238 2.2K_0402_5%

1 2

RH239 2.2K_0402_5%

2

H1D

U

CRT_IREF

J47

_BKLTEN

L

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_C LK

P39

L_CTRL_D ATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_ CLK

M40

CRT_DDC_ DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82HM76-SLJ8E-C1_BGA989~D

R1@

DVO_TVCLKINN

S

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTR LCLK

DDPC_CTR LDATA

mDP

Digital Display Interface

DDPD_CTR LCLK

DDPD_CTR LDATA

CRT

DMC

E

T56PAD~D

1K_0402_0.5%

NBKL
CH_ENVDD

P

LVDS_DDC_CLK
LVDS_DDC_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVDS_ACLK­LVDS_ACLK+

LVDS_A0­LVDS_A1­LVDS_A2-

LVDS_A0+
LVDS_A1+
LVDS_A2+

LVDS_BCLK­LVDS_BCLK+

LVDS_B0­LVDS_B1­LVDS_B2-

LVDS_B0+
LVDS_B1+
LVDS_B2+

CRT_DDC_CLK
CRT_DDC_DATA

12

RH115

CTRL_CLK

CTRL_DATA

PM_CLKRUN#

LVDS_DDC_CLK

LVDS_DDC_DATA

PCH_SDVO_CTRLCLK

PCH_SDVO_CTRLDATA

CRT_DDC_CLK

CRT_DDC_DATA

NBKL<40>

E

VGA_PWM<21>

@

@

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

1 2

1 2

1 2

1 2

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

HDMI_DET

HDMI_A2N_VGA
HDMI_A2P_VGA
HDMI_A1N_VGA
HDMI_A1P_VGA
HDMI_A0N_VGA
HDMI_A0P_VGA
HDMI_A3N_VGA
HDMI_A3P_VGA

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

RH120 10K_0402_5%

RH123 2.37K_0402_1%

RH132 100K_0402_5%

RH134 100K_0402_5%

PCH_SDVO_CTRLCLK <22>

PCH_SDVO_CTRLDATA <22>

HDMI_DET <22>

HDMI_A2N_VGA <22>

HDMI_A2P_VGA <22>

HDMI_A1N_VGA <22>

HDMI_A1P_VGA <22>

HDMI_A0N_VGA <22>

HDMI_A0P_VGA <22>

HDMI_A3N_VGA <22>

HDMI_A3P_VGA <22>

PM_CLKRUN#

LVDS_IBG

PCH_ENVDD

ENBKL

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI/FDI/PM/GFX/DP

PCH (3/8) DMI/FDI/PM/GFX/DP

PCH (3/8) DMI/FDI/PM/GFX/DP

LA-9101P

LA-9101P

LA-9101P

1

15 57Wednesday, August 29, 2012

15 57Wednesday, August 29, 2012

15 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

+

3VS

1 2

R

H129 8.2K_0402_5%

1 2

H130 8.2K_0402_5%

+3VS

12

PCH_PLTRST#

12

CLK_PCI1

R

1 2

H131 8.2K_0402_5%

R

1 2

H141 8.2K_0402_5%

R

1 2

R

H142 8.2K_0402_5%

1 2

RH146 8.2K_0402_5%

1 2

RH147 8.2K_0402_5%

1 2

RH148 8.2K_0402_5%

1 2

RH151 8.2K_0402_5%

1 2

RH153 8.2K_0402_5%

1 2

RH154 8.2K_0402_5%

RH140 10K_0402_5%

PT:
Port 1 USB Conn JUSB2
Port 2 USB Conn JUSB1
Port 3 Cancel

CLK_PCI_LPBACK<14>

CLK_PCI_LPC<40>

D D

C C

B B

SSI:
Port 1 USB Conn 1
Port 2 USB Conn 2
Port 3 USB Conn 3

Reserve for ESD

CH104

0.1U_0402_16V7K

Please close to PCH

CH31

@

10P_0402_50V8J

Reserve for RF please close t o PCH

@

RH150

10K_0402_5%

PLT_RST#<32,38,40,6>

A A

12

+3VS

1 2

4

CLK_PCI_LPBACK
CLK_PCI_LPC

12

RH155
100K_0402_5%

P

CI_PIRQA#

P

CI_PIRQD#

P

CI_PIRQB#

P

CI_PIRQC#

PIO51

G

GPIO5

GPIO52

WL_OFF#

ODD_DA#

GPIO4

PXS_PWREN

DGPU_HOLD_RST#

USB3RN1_JUSB2<36>
USB3RN2_JUSB1<36>

USB3RP1_JUSB2<36>
USB3RP2_JUSB1<36>

USB3TN1_JUSB2<36>
USB3TN2_JUSB1<36>

USB3TP1_JUSB2<36>
USB3TP2_JUSB1<36>

DGPU_HOLD_RST#<24>

PXS_PWREN<26,53>

PCH_PLTRST#<24>

RH144 22_0402_5%

1 2

RH145 22_0402_5%

1 2

@

RH149 0_0402_5%

+3VS

5

UH5

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

@

WL_OFF#<38>

ODD_DA#<41>

1 2

T60PAD~D @

12

T61PAD~D @
T62PAD~D @
T63PAD~D @

CH101

1 2

PCH_PLTRST#

RH157
10K_0402_5%

USB3RN1_JUSB2
USB3RN2_JUSB1

USB3RP1_JUSB2
USB3RP2_JUSB1

USB3TN1_JUSB2
USB3TN2_JUSB1

USB3TP1_JUSB2
USB3TP2_JUSB1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#
GPIO52
PXS_PWREN

GPIO51

WL_OFF#

ODD_DA#
GPIO4
GPIO5

PCH_PLTRST#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

0.1U_0402_25V6K

U

H1E

BG26

P1

T

BJ26

T

P2

BH25

P3

T

BJ16

T

P4

BG16

P5

T

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM76-SLJ8E-C1_BGA989~D

R1@

RSVD

3

AY7

R

SVD1

AV7

R

SVD2

AU3

SVD3

R

BG4

R

SVD4

AT10

R

SVD5

BC8

SVD6

R

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USB

USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

PCI

Intel Anti-The ft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

USB20_JUSB2_N0
USB20_JUSB2_P0
USB20_JUSB1_N1
USB20_JUSB1_P1
USB20_JUSB3_N2
USB20_JUSB3_P2
USB20_USBDB_N3
USB20_USBDB_P3

USB20_MINI1_N8
USB20_MINI1_P8
USB20_TOUCH_N9
USB20_TOUCH_P9
USB20_CR_N10
USB20_CR_P10
USB20_CAM_N11
USB20_CAM_P11

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

RH139 1K_0402_5%@

Within 500 mils

1 2

RH143 22.6_0402_1%

1 2

USB20_JUSB2_N0 <36>
USB20_JUSB2_P0 <36>
USB20_JUSB1_N1 <36>
USB20_JUSB1_P1 <36>
USB20_JUSB3_N2 <37>
USB20_JUSB3_P2 <37>
USB20_USBDB_N3 <37>
USB20_USBDB_P3 <37>

USB20_MINI1_N8 <38>
USB20_MINI1_P8 <38>
USB20_TOUCH_N9 <41>
USB20_TOUCH_P9 <41>
USB20_CR_N10 <34>
USB20_CR_P10 <34>
USB20_CAM_N11 <21>
USB20_CAM_P11 <21>

2

*

+1.8VS

USB Conn JUSB2

USB Conn JUSB1

USB Conn JUSB3

USB Conn 4 (DB)

Mini Card (WLAN)

Touch panel

Touch panel

Card Reader

Camera

USB_OC0# <36>
USB_OC1# <36>
USB_OC2# <37>
USB_OC3# <37>

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB_OC6#

USB_OC5#

USB_OC4#

USB_OC7#

SSI:
Port 0 USB Conn 1
Port 1 USB Conn 4 (DB)
Port 2 USB Conn 2
Port 3 USB Conn 3
Port 4 Mini Card (WLAN)
Port 6 Card Reader
Port 12 Camera

PT:
Port 0 USB Conn JUSB2
Port 1 USB Conn JUSB1
Port 2 USB Conn JUSB3
Port 3 USB Conn 4 (DB)
Port 8 Mini Card (WLAN)
Port 9 Touch panel
Port 10 Card Reader
Port 11 Camera

+3V_PCH

12

RH15610K_0402_5%

12

RH15810K_0402_5%

12

RH16010K_0402_5%

12

RH16610K_0402_5%

12

RH16710K_0402_5%

12

RH17010K_0402_5%

12

RH18910K_0402_5%

12

RH21110K_0402_5%

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI/USB/NVRAM

PCH (4/8) PCI/USB/NVRAM

PCH (4/8) PCI/USB/NVRAM

LA-9101P

LA-9101P

LA-9101P

1

16 57Wednesday, August 29, 2012

16 57Wednesday, August 29, 2012

16 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

+

D D

C C

B B

A A

3V_PCH

12

P

R

H240 1K_0402_5%

RH241 10K_0402_5%

RH245 10K_0402_5%

+3V_PCH +3V_PCH+3V_PCH

12

@

RH244
10K_0402_5%

12

@

RH179
10K_0402_5%

System ID

LOW Entry

HIGH VOSTROVAW10 17''

+3VS

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage regulator enab le

*

L：On-Die PLL Vol tage Regulator disable

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx te rminated

*

to same voltage
(DC Coupling Mo de)

+3VS

RH168 1K_0402_5%@

1 2

RH169

CH_LID_SW_IN#

12

PCH_GPIO28

12

PCH_GPIO48

12

GPIO1

PCH_GPIO28

10K_0402_5%

12

@

RH181
10K_0402_5%

12

@

RH225
10K_0402_5%

INSPIRON

PCH_GPIO37

PCH_GPIO37

12

@

RH182
10K_0402_5%

PCH_GPIO39PCH_GPIO57 PCH_GPIO38

12

@

RH202
10K_0402_5%

PCH_GPIO57 PCH_GPIO39

VAW00 15''

RH16410K_0402_5%

1 2

RH165 1K_0402_5%@

12

EC_LID_OUT#<40>

PCH_GPIO38

Mainstream

4

EC_SCI#<40>

EC_SMI#<40>

1 2

RH73 0_0402_1%

VGA_PWRGD<53>

KB_DET#

BT_ON#<38>

ODD_DETECT#<41>

U

H1F

T7

B

MBUSY# / GPIO0

RH173 10K_0402_5%@

A42

T

ACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR _CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM76-SLJ8E-C1_BGA989~D

R1@

1 2

PCH_GPIO27

GPIO

G

PIO1

PIO6

G

EC_SCI#

EC_SMI#

PCH_LID_SW_IN#EC_LID_OUT#

@

GPIO16

VGA_PWRGD

PCH_GPIO22

KB_DET#

PCH_GPIO27

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

GPIO49

PCH_GPIO57

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

NCTF

3

T

ACH4 / GPIO68

T

ACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PECI

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

O

DD_EN#

G

PIO69

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

DF_TVS

ODD_EN#

EC_SMI#

O

DD_EN# <41>

64 PAD~D@

T

KB_RST# <40>

H_CPUPWRGD <6>

1 2

RH162390_0402_5%

1 2

RH178

1 2

RH183

2

3VS

+

RH159
10K_0402_5%

1 2

H_THERMTRIP#

12

@

RH163
10K_0402_5%

H_THERMTRIP# <6>

INIT3_3V

This signal has weak internal
PU, can't pull low

Due to remove VCCDFERM
jumper(PJP66), need to
change the power rail to
+1.8V_RUN for D12" only

H_SNB_IVB#<6>

+3V_PCH

10K_0402_5%

10K_0402_5%

GATEA20 <40>

PLACE RH150 CL OSE TO THE BRAN CHING POINT
( TO CPU and NV RAM CONNECTOR)

+1.8VS

12

RH152

2.2K_0402_5%

PCH_PECI_RPCH_PECI_R

RH149 need to close to CPU

1 2

RH358 1K_0402_1%

DMI & FDI Termination Voltage

Set to Vss when LOW

Set to Vcc when HIGH

1 2

RH171

1 2

RH172

1 2

RH174

1 2

RH175

1 2

RH242

1 2

RH176

1 2

RH177

1 2

RH180

1 2

RH184

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

VGA_PWRGD

PCH_GPIO22

GPIO35

GPIO49

GPIO6

DF_TVS

200K_0402_5%

10K_0402_5%

8.2K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

1 2

@

RH1610_0402_5%

1

@

CH102

0.1U_0402_10V7K~D

2

Place CH102 close to RH161
& PCH.

DF_TVS

+3VS

1

H_PECI <40,6>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO/CPU/MISC

PCH (5/8) GPIO/CPU/MISC

PCH (5/8) GPIO/CPU/MISC

LA-9101P

LA-9101P

LA-9101P

1

17 57Wednesday, August 29, 2012

17 57Wednesday, August 29, 2012

17 57Wednesday, August 29, 2012

0.4

0.4

0.4

5

D D

+1.05VS

1

1

1

CH37

CH36

CH35

2

+1.05VS

+1.05VS

C C

@

12

+VCCAPLLEXP_R

RH187 0_0603_5%~D

1 2

RH186 0_0603_1%@

@

1 2

1UH_LB2012T1R0M_20%~D

Place CH40 Near BJ22 pin

+1.05VS

1

+3VS

12

RH192

0_0805_1% @

+3VS_VCCA3GBG

1

+1.05VS

B B

CH51

0.1U_0402_10V7K~D

2

@

Place CH53 Near BG6 pin

12

RH194 0_0603_5%~D

1

CH45

2

2

10U_0805_4VAM~D

1

CH53

2

@

1U_0402_6.3V6K

10U_0805_4VAM~D

LH3

CH46

+1.05VS

1U_0402_6.3V6K

2

1

CH47

2

2

1U_0402_6.3V6K

1

CH48

2

1U_0402_6.3V6K

1U_0402_6.3V6K

RH195

@

1 2

0_0805_1%

+VCCP_VCCDMI

1U_0402_6.3V6K

+1.05VS_VCCDPLLEXP

1

2

@

1

2

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

1

CH38

2

1U_0402_6.3V6K

+VCCAPLLEXP

CH42

10U_0805_4VAM~D

CH49

1U_0402_6.3V6K

+VCCAFDI_VRM

4

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

BD82HM76-SLJ8E-C1_BGA989~D

R1@

UH1G

1300mA

2925mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

60mA

DMI

20mA

190mA

DFT / SPI HVCMOS

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

VCCSPI

20mA

U48

+VCCADAC

U47

AK36

+VCCA_LVDS

AK37

AM37

AM38

AP36

AP37

V33

+3VS_VCC3_3_6

V34

AT16

+VCCAFDI_VRM

AT20

+VCCP_VCCDMI

AB36

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

+3V_VCCPSPI

3

R

eserve for LVDS issue

1

CH32

2

0.01U_0402_16V7K

+VCCTX_LVDS

CH39

0.01U_0402_16V7K

@

1 2

1

CH43

0.1U_0402_10V7K~D

2

1

CH52

2

0.1U_0402_10V7K~D

1

CH54
1U_0402_6.3V6K

2

+

VCCA_LVDS

1

C

H106

@

1U_0402_6.3V6K

2

1

1

CH34
10U_0805_4VAM~D

CH33

2

2

RH185 0_0805_5%

0.1U_0402_10V7K~D

Near AP43

1

CH40

0.01U_0402_16V7K

2

RH188

0_0805_1%

+VCCP_VCCDMI

RH191

@

1 2

1

0_0805_1%
CH50
1U_0402_6.3V6K

2

+VCCPNAND

1 2

@

1 2

RH196 0_0805_1%

@

RH243 0_0603_5%~D

LH1

4.7UH_LQM18FN4R7M00D_20%

1 2

CH41

1

1

22U_0805_6.3V6M

2

2

+3VS

+1.05VS

RH193

0_0805_1%@

12

+3VS

12

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

RH190

@

1 2

1

0_0805_1%

CH44

2

1U_0402_6.3V6K

+1.8VS

+3V_PCH

+3VS

2

PCH Power Rail Table

Voltage Rail

V_PROC_IO

+1.8VS

V5REF

V5REF_Sus

Vcc3_3

VccADAC

+3VS

LH2

12

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

0.001

0.001

5

0.266

0.001

0.08

0.08

1.3

0.042

1

1.05VccIO 2.9 25

1.05VccASW 1.01

3.3VccSPI 0.02

+VCCP

3.3VccDSW 0.003

1.8 0. 19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3 _3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1 .05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3 .3

0.001

1.8VccTX_L VDS 0.06

+1.5VS +VCCAFDI_VRM

RH197

@

1 2

A A

5

4

0_0603_1%

+VCCAFDI_VRM

1

CH100
1U_0402_6.3V6K

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/08/22 2013/08/31

2012/08/22 2013/08/31

2012/08/22 2013/08/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR

PCH (6/8) PWR

LA-9101P

LA-9101P

LA-9101P

1

18 57Wednesday, August 29, 2012

18 57Wednesday, August 29, 2012

18 57Wednesday, August 29, 2012

0.4

0.4

0.4