Compal LA-9063P VIWZ1 DIS, IdeaPad Z400, IdeaPad Z500, LA-9063P VIWZ2 DIS Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

VIWZ1/VIWZ2 DIS M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

nVIDIA N14P-GV2

2012-12-26

3 3

LA-9063P

REV:1.0

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-9603P

LA-9603P

LA-9603P

E

1 62Wednesday, January 09, 2013

1 62Wednesday, January 09, 2013

1 62Wednesday, January 09, 2013

1.0

1.0

1.0

A

Compal confidential

File Name : VIWZ1/VIWZ2

Page23-32

1 1

nVIDIA N14P-GV2

VRAM 128Mb*16

DDR3*4 1GB

VRAM 256Mb*16

DDR3*4 2GB

HDMI

Page35

Connector
CRT

2 2

Connector
LVDS

Connector

Page34

Page33

Page45

LVDS

eDP

USB 3.0
USB2.0

USB3.0 *1(Left)
include USB2.0*1

B

PCI-E x8

PCI-E x1 *6

100MHz

2.7GT/s

Intel

Ivy Bridge

Socket-rPGA988B

37.5mm*37.5mm

Page5-11

FDI *8

Intel

Panther Point

HM70 / HM76

FCBGA 989

25mm*25mm

Page14-22

C

Dual Channel
DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
DDR3 1600MHz(1.5V)

DMI *4

AZALIA

USB2.0 *14

SATA *6

HM76@

D

U4

PCH-HM70

SA00005MQ80

U4

PCH-HM76

SA00005FH70

DDR3 SO-DIMM *2

BANK 0, 1, 2, 3

Up to 8GB

Page12-13

Audio Codec
Realtek

ALC259-VC2

Page41

Camera Conn.
BlueTooth Conn.

HM70@ ZZZ

LA9063

DA_PCB

DA8000XJ000

ZZZ6

LA9063

DA_PCB

DA8000XJ100

14@

LS9061P PWR/B
LS9062P USB/B

15@

LS9065P PWR/B
LS9062P USB/B
LS9063P ODD/B
LS9064P LED/B

2 channel speaker
Int. Digital MIC array

Page41

Page41

(Combine with webcam)
Combo Jack*1

Page33

Page40

Page43

E

VIWZ1

VIWZ2

SPIROM

3 3

BIOS

Realtek

RTL8111F(GLAN)
RTL8105E-VD(10/100)

Page37

Page14

LPC BUS

EC

ENE KB9012

Page42

Card Reader
Reltek

RTS5178 for SDR50
SDXC/MMC

Page44

RJ-45
Connector

Mini PCIE Half size Slot *1
WLAN

4 4

A

Page38

Page36

PCI-E(WLAN)

Touch Pad Int. KBD

Page43

Thermal Sensor

EMC1403

B

Page39

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

C

Page43

Compal Secret Data

Compal Secret Data

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

USB2.0 *2(Right)

Page 43

Mini PCIE Full size Slot *1

SSD

SATA HDD
SATA ODD

D

Page36

Page40

Page40

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-9603P

LA-9603P

LA-9603P

E

2 62Wednesday, January 09, 2013

2 62Wednesday, January 09, 2013

2 62Wednesday, January 09, 2013

1.0

1.0

1.0

A

Voltage Rails

power
plane

1 1

State

S0

S3

S5 S4/AC

2 2

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

EC SM Bus1 address

Device

Smart Battery
USB Charger

0001 011X b
1010 111X b

+B

O

O
O
O

X

Address

+5VALW

+3VALW

O

O
O

X
X X X

EC SM Bus2 address

Device

Thermal Sensor EMC1403

PCH SM Bus address

Device Address

DDR DIMM0
DDR DIMM2

1001 000Xb
1001 010Xb

NV-GPU SM Bus address

3 3

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK

4 4

SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

X

X

X

V

+3VS

+3VALW

X

X

X

X

X

+3VS

X

V

X

+3VS

X

X

V

B

+1.5V

+VCC_GFXCORE_AXG

O

X X
X

Address

1001_101xb

Thermal

WLAN

Sensor

WWAN

X

XX

V

+3VS

X

+5VS
+3VS
+1.5VS
+V1.05S_VCCP
+VCC_CORE
+VGA_CORE

+1.8VS

+0.75VS
+1.05VS

OO

X

X

X

X

X

XX

V

+3VS

PCH

X

V

+3VS

X

X

XX X

Board ID

0
1
2
3
4
5
6

PCB Revision

LA-9061P
LA-9061P
LA-9061P
LA-9061P
LA-9063P 0.2
LA-9063P

7

USB Port Table

EHCI1

USB3.0

EHCI1

EHCI2

GPU BOM Structure Table

TP

X

BOM Structure

OPT@
OPTNOGCLK@
GV2@
GC6@ Select

X

V

+3VS

X

X

C

USB 2.0

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

1.0

0.3

0.2

0.1

0.2 15_TS

Port

0
1
2
3
4
5
6
7
8

9
10
11
12
13

N14P-GV2

V
V
V

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

Board ID / SKU ID Table for AD channelBOARD ID Table

Vcc 3.3V +/- 5%

Ra/Rc/Re

Board ID

USB Port (Left Side)
Touch Screen

Blue Tooth
Camera

USB Port (Right Side USB-BD)
USB Port (Right Side USB-BD)

Mini Card(WLAN)
Card Reader

100K +/- 5%

Rb / Rd / Rf V min

0
1

8.2K +/- 5%

2

18K +/- 5%

3

33K +/- 5%

4

56K +/- 5%

5

100K +/- 5%

6

200K +/- 5%

7

3 External
USB Port

D

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

ON

0 V 0 V

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

HIGH

LOWLOWLOW

LOW LOW LOW LOW

0

AD_BID

0 V

E

ONONON ON

ON

ON

OFF

OFF

OFF

OFF

OFF

V

max

AD_BID

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

NC

2.500 V

1.935 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

USB3.0

OPTIMUS part

integrate Graphic part UMA@
GPU:N14P-GV2 Strap
GPU:N14P-GV2 GC6 function

Support Green CLK GCLK@

not Support Green CLK NOGCLK@

Support Green CLK 244

Support Green CLK 304

Cardreader CR@

Support HP Woofer woofer@

EC RESET function RESET@

HDMI HDMI@

BlueTooth BT@

Connector ME@

45 LEVEL 45@

10/100 LAN 8105@

GIGA LAN

Deep Sleep S3 DS3@

Not Support Deep Sleep S3 NODS3@

ISCT AOAC@

ISCT not support NOAOAC@

Camera CMOS@

For Z490 (14") 14@

For Z590 (15") 15@

Unpop

USB Charger CHG@

not USBCharger NOCHG@

Keyboard Back Light KBL@

Touch Screen TS@

HM76 by PCH HM76@

HM70 by PCH HM70@

LOW

OFF

OFF

OFF

Porject Phase

Z-series

Z-series

Z-series

Z-series

Re-flash

Reserved

Reserved

Reserved

GV2@ GPU:N14P-GV2
OPT@

GV2@
GC6@
OPTNOGCLK@OPTIMUS no support GCLK
OPTGCLK@OPTIMUS support GCLK

GCLK244@
GCLK304@

Gastube@Gastube

GIGA@

@

RTS5178@Cardreader RTS5178
RTS5170@Cardreader RTS5170

MP
PVT
DVT
EVT
EVT
DVT
PVT
MP

TS_14@for 14" Touch Screen

for 15" Touch Screen

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LA-9603P

LA-9603P

LA-9603P

Notes List

Notes List

Notes List

TS_15@

1.0

1.0

3 62Wednesday, January 09, 2013

3 62Wednesday, January 09, 2013

3 62Wednesday, January 09, 2013

E

1.0

5

4

3

2

1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO)

GPIO I/O ACTIVE Function Description
GPIO0

D D

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10

C C

GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

I GC6_FB_CLAMPH

OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT

IN
OUT
OUT
IN
OUT
IN
IN
IN

-

MEM_VDD_CTLOUT
Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)

H

RESERVED

­GC6_FB_REQ

L

-

3DVision
Thermal Catastrophic Over Temperature

L

Thermal Alert

L

Memory VREF Control

­PWM_VID-OUT
AC Power Detect Input
PSI-

N/A

N/A
N/A

N/A

(10K pull low)

Performance Mode P0 TDP at Tj = 102 C* (GDDR3)

GPU Mem NVCLK

Products

N13P-GL
64bit
1GB
GDDR3

Physical
Strapping pin

ROM_SCLK

(4) (1,5) (6)
(W) (W) (MHz)

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

/MCLK NVVDD

TBD TBD

Power Rail

+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA

(V) (A) (W) (A) (W)

Logical
Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED

RESERVED PCIE_SPEED_

FBVDD

Logical
Strapping Bit2

SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(1.05V)

Logical
Strapping Bit1

SLOT_CLK_CFG/PCI_DEVID[5]

PLLVDD

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

I/O and
PLLVDD

Other
(3.3V)(1.05V)(1.8V)

Logical
Strapping Bit0

PEX_PLL_EN_TERM
RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

SOR0_EXPOSED

PCIE_MAX_SPEED DP_PLL_VDD33V

B B

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

+1.05VS_VGA

A A

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Compal Electronics, Inc.

VGA Notes List

VGA Notes List

VGA Notes List
LA-9603P

LA-9603P

LA-9603P

4 62Wednesday, January 09, 2013

4 62Wednesday, January 09, 2013

4 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

D D

DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>

C C

eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms

+V1.05S_VCCP

12

R7

24.9_0402_1%

B B

FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16>
FDI_FSYNC1<16>

FDI_LSYNC0<16>
FDI_LSYNC1<16>

4

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

FDI_INT<16>

EDP_COMP

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

3

+V1.05S_VCCP

R1

24.9_0402_1%

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_COMP

PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N10

PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0

PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0

PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0

PCIE_CRX_GTX_N[0..15] <23>

PCIE_CRX_GTX_P[0..15] <23>

C1 0.22U_0402_6.3V K@
C2 0.22U_0402_6.3V K@
C3 0.22U_0402_6.3V K@
C4 0.22U_0402_6.3V K@
C5 0.22U_0402_6.3V K@
C6 0.22U_0402_6.3V K@
C7 0.22U_0402_6.3V K@
C8 0.22U_0402_6.3V K@
C9 0.22U_0402_6.3V KOPT@
C10 0.22U_0402_6.3V KOPT@
C11 0.22U_0402_6.3V KOPT@
C12 0.22U_0402_6.3V KOPT@
C13 0.22U_0402_6.3V KOPT@
C14 0.22U_0402_6.3V KOPT@
C15 0.22U_0402_6.3V KOPT@
C16 0.22U_0402_6.3V KOPT@

C17 0.22U_0402_6.3V K@
C18 0.22U_0402_6.3V K@
C19 0.22U_0402_6.3V K@
C20 0.22U_0402_6.3V K@
C21 0.22U_0402_6.3V K@
C22 0.22U_0402_6.3V K@
C23 0.22U_0402_6.3V K@
C24 0.22U_0402_6.3V K@
C25 0.22U_0402_6.3V KOPT@
C26 0.22U_0402_6.3V KOPT@
C27 0.22U_0402_6.3V KOPT@
C28 0.22U_0402_6.3V KOPT@
C29 0.22U_0402_6.3V KOPT@
C30 0.22U_0402_6.3V KOPT@
C31 0.22U_0402_6.3V KOPT@
C32 0.22U_0402_6.3V KOPT@

2

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

12

max length = 500 mils

- typical impedance = 14.5 mohms

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

*

PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

1

PCIE_CTX_GRX_N[0..15] <23>

PCIE_CTX_GRX_P[0..15] <23>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

3

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

5 62Wednesday, January 09, 2013

5 62Wednesday, January 09, 2013

5 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

4

3

2

1

D D

H_SNB_IVB#<19>

+V1.05S_VCCP

H_CATERR#

H_PROCHOT#_R

H_PM_SYNC_R

H_CPUPWRGD_R

PM_DRAM_PWRGD_R

BUF_CPU_RST#

BUF_CPU_RST#

H_THRMTRIP#<19>

1 2

R30
200_0402_5%

T48

H_PECI<42>

R15

56_0402_5%

1 2

R29

1 2

130_0402_5%

12

R9

62_0402_5%

H_PROCHOT#<42,48>

C C

H_CPUPWRGD<19>

B B

SYS_PWROK<16>

+3VS

PM_DRAM_PWRGD<16>

H_PROCHOT#

1 2

R26 0_0402_5%@

0.1U_0402_16V7K

1 2

@

R880 0_0402_5%

1 2

R161

10K_0402_5%

R02

H_PM_SYNC<16>

R27
10K_0402_5%

1 2

+3VALW

1

C33

2

U1

5

1

P

B

4

PM_SYS_PWRGD_BUF

O

2

A

G

74AHC1G09GW_TSSOP5

3

R22 0_0402_5%@

+1.5V_CPU_VDDQ

12

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

75_0402_5%

43_0402_1%

1 2

MISCTHERMALPWR MANAGEMENT

+V1.05S_VCCP

0.1U_0402_16V7K

12

R32

R34

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3

MISC

JTAG & BPM

Buffered reset to CPU

+3VS

1

C34

2

5

U2

4

1

P

NC

Y

2

A

G

3

A28

BCLK

BCLK#

CLK_CPU_DMI_R

A27

CLK_CPU_DMI#_R

A16

R12 1K_0402_5%

A15

R13 1K_0402_5%

R8

H_DRAMRST#

AK1

SM_RCOMP0

A5

SM_RCOMP1

A4

SM_RCOMP2

DDR3 Compensation Signals

AP29

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

XDP_PRDY#

AP27

XDP_PREQ#

AR26

XDP_TCK

TCK

AR27

XDP_TMS XDP_TDO

TMS

AP30

XDP_TRST#

AR28

XDP_TDI

TDI

AP26

XDP_TDO

TDO

AL35

XDP_DBRESET#

AT28

XDP_BPM#0

AR29

XDP_BPM#1

AR30

XDP_BPM#2

AT30

XDP_BPM#3

AP32

XDP_BPM#4

AR31

XDP_BPM#5

AT31

XDP_BPM#6

AR32

XDP_BPM#7

PCH_PLTRST#

3V

PCH_PLTRST# <18>

R10;R11 put on U4 side

R02

1 2

R10 0_0402_5%@

1 2

R11 0_0402_5%@

R02

12
12

H_DRAMRST# <7>

12

R16 140_0402_1%

12

R17 25.5_0402_1%

12

R18 200_0402_1%

T97
T98

R28 1K_0402_5%

T49
T90
T91
T92
T93
T94
T95
T96

12

+V1.05S_VCCP

XDP_TMS
XDP_TDI

XDP_TCK
XDP_TRST#

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>

R20 51_0402_5%
R21 51_0402_5%
R23 51_0402_5%@

R24 51_0402_5%
R25 51_0402_5%

+3VS

+V1.05S_VCCP

12
12
12

12
12

PU/PD for JTAG signals

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

6 62Wednesday, January 09, 2013

6 62Wednesday, January 09, 2013

6 62Wednesday, January 09, 2013

1.0

1.0

1.0

5

4

3

2

1

D10

AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9

AJ11

AT8
AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

JCPU1D

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

C9

SB_DQ[0]

A7

SB_DQ[1]
SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]

R6

SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

RSVD_TP[17]
RSVD_TP[18]

RSVD_TP[19]
RSVD_TP[20]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2 <13>
M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

JCPU1C

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8
AK9

AH8
AH9

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10
AF10

AE8
AD9
AF9

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]
SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]
SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]
SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]
SA_DQ[41]

AJ9

SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

RSVD_TP[10]

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]
SA_ODT[1]

RSVD_TP[9]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0 <12>
M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>

Deciphered Date

Deciphered Date

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

LA-9603P

LA-9603P

LA-9603P

1

7 62Wednesday, January 09, 2013

7 62Wednesday, January 09, 2013

7 62Wednesday, January 09, 2013

1.0

1.0

1.0

TYCO_2013620-2_IVY BRIDGE

+1.5V

12

R37

1K_0402_5%

D

S

13

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

DRAMRST_CNTRL_PCH<15>

DRAMRST_CNTRL<10>

DRAMRST_CNTRL_EC<42>

NODS3@

1 2

R40 0_0402_5%

R02

1 2

@

R92 0_0402_5%

1 2

R65 0_0402_5%DS3@

1 2

DRAMRST_CNTRL_R

For Deep S3

5

DDR3_DRAMRST#_RH_DRAMRST#

Q2

G

LBSS138LT1G_SOT-23-3

2

1

C35

0.047U 16V K X7R 0402

2

R38
1K_0402_5%

1 2

Eiffel used 0.01u
Module design used 0.047u

4

DDR3_DRAMRST# <12,13>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

5

4

3

2

1

CFG Straps for Processor

CFG2

12

R41

D D

1K_0402_1%

JCPU1E

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF10

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

AK28

CFG[0]

AK29

CFG[1]

CFG2
CFG4

CFG5
CFG6
CFG7

+VCC_GFXCORE_AXG

+VCC_CORE

R252

R253

C C

49.9_0402_1%

49.9_0402_1%

1 2

1 2

1 2

R82 100_0402_1%@

1 2

R88 100_0402_1%@

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

Need PWR add new circuit on 1.05V(refer CRB)

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

R255

49.9_0402_1%

INTEL 12/28 recommand
to add RC120, RC121, RC122, RC123

B B

Please place as close as JCPU1

R257

49.9_0402_1%

1 2

1 2

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CFG

Interl request AH26 short GND
check on EVT phase

AH27

R02

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

1 2

R93 0_0402_5%@

PEG Static Lane Reversal - CFG2 is for the 16x

T13PAD

CFG2

*

Display Port Presence Strap

CFG4

*

for N14P_GV2 GPU 11/13

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

CFG4

12

R42

@

1K_0402_1%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6
CFG5

12

12

GV2@

1K_0402_1%

CFG7

@

R43

R44
1K_0402_1%

12

R45

@

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0: PEG Wait for BIOS for training

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

LA-9603P

LA-9603P

LA-9603P

1

8 62Wednesday, January 09, 2013

8 62Wednesday, January 09, 2013

8 62Wednesday, January 09, 2013

1.0

1.0

1.0

5

4

3

2

1

+VCC_CORE

JCPU1F

QC=94A
DC=53A

D D

C C

B B

A A

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26

AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27

AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

POWER

CORE SUPPLY

PEG AND DDR

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

+V1.05S_VCCP

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

0.1U_0402_16V7K

+V1.05S_VCCP

1

C99

12

2

R46
75_0402_5%

VR_SVID_CLK

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

1 2

R47 43_0402_5%

R02

1 2

R48 0_0402_5%@

R02

1 2

R49 0_0402_5%@

R50 130_0402_5%

12

+V1.05S_VCCP

VR_SVID_ALRT# <55>
VR_SVID_CLK <55>
VR_SVID_DAT <55>

0.1uF on power side

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

Trace Impedance =27-33 ohm
Trace Length Matc < 25 mils

AJ35

VCCSENSE_R

AJ34

VSSSENSE_R

B10
A10

VSS_SENCE 100ohm +-1% pull-down to GND near processor

R02

1 2

R52 0_0402_5%@

R02

1 2

R53 0_0402_5%@

1 2

VSSIO_SENSEVSSIO_SENSE_L

R74

10_0402_1%

R74 & R79 put together

@

VSSIO_SENSE_L <53>

R79

10_0402_1%

VCCIO_SENSE <53>

+V1.05S_VCCP

12

series-resistors close to VR

+VCC_CORE

12

R51
100_0402_1%

12

R54
100_0402_1%

VCCSENSE <55>
VSSSENSE <55>

Security Classification

Security Classification

TYCO_2013620-2_IVY BRIDGE

5

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

9 62Wednesday, January 09, 2013

9 62Wednesday, January 09, 2013

9 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

4

3

2

1

+1.5V +1.5V_CPU_VDDQ

R02

1 2

R668 0_0402_5%@

SUSP<25,46,51,54>

D D

C C

B B

+VSB

12

R56
82K_0402_5%

13

D

Q4

2

G

2N7002K_SOT23-3

S

+VCC_GFXCORE_AXG

RUN_ON_CPU1.5VS3

J1

@

1 2

PAD-OPEN 4x4m

U3

AP4800BGM-HF_SO-8

8
7

5

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

4

1

AP4800

2

Id=9.6A

36

R885

1 2

15K_0402_1%

POWER

GRAPHICS

1

C97

0.047U_0603_25V7M

2

VSSAXG_SENSE

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

+VCC_GFXCORE_AXG

AK35
AK34

AL1

+V_SM_VREF_CNT

B4

+V_DDR_REFA_R

D1

+V_DDR_REFB_R

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27

+VCCSA

M26
L26
J26
J25
J24
H26
H25

12

12

R616
10_0402_1%

R626
10_0402_1%

VCC_AXG_SENSE <55>

VSS_AXG_SENSE <55>

+V_SM_VREF should
have 20 mil trace width

C117

10U_0603_6.3V6M

C118

10U_0603_6.3V6M

1

1

2

2

C125

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

1

1

2

2

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

DRAMRST_CNTRL

LBSS138LT1G_SOT-23-3

1 2
1 2

13

D

2

G

S

Q9

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

+1.5V_CPU_VDDQ

12

R67
1K_0402_1%

12

1

0.1U_0402_16V7K

C119

10U_0603_6.3V6M

1

2

C126

10U_0603_6.3V6M

1

2

C98

C120

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

2

+VCCSA

C127

10U_0603_6.3V6M

1

2

2

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C121

1

+

2

2

1

+

C128

@

330U_D2_2.5VY_R9M

2

R78
1K_0402_1%

C123

330U_2.5V_M

Q6

13

D

LBSS138LT1G_SOT-23-3

2

@

@

G

S

0_0402_5%~D
0_0402_5%~D

R353

1K_0402_1%

@

R670

R671

Q5-orignal part
AP2302GN-HF_SOT23-3
SB523020210

+1.5V +1.5V_CPU_VDDQ

DRAMRST_CNTRL

+V_DDR_REFA_R

+V_DDR_REFB_R

12

12

R64
1K_0402_1%

@

C96

0.1U_0402_16V7K

1 2

C95

0.1U_0402_16V7K

1 2

DRAMRST_CNTRL <7>

SA RAIL

10K_0402_5%

+3VS

R75

1 2

+1.8VS

R20

@

112

JUMP_43X79

80mil

J14

VCCIO_SEL

H23

C22
C24

A19

H_VCCSA_VID0 <52>
H_VCCSA_VID1 <52>

H_VCCP_SEL

R02

1 2

R77 0_0402_5%@

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

2

C130

10U_0603_6.3V6M

1

2

1

2

C131

1U_0402_6.3V6K

1.5A

+1.8VS_VCCPLL

1U_0402_6.3V6K

1

2

B6

VCCPLL1

A6

C132

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

1.8V RAIL

+VCCSA_SENSE <52>

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

10 62Wednesday, January 09, 2013

10 62Wednesday, January 09, 2013

10 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

JCPU1H

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13

D D

C C

B B

A A

5

AT10

AT7
AT4

AT3
AR25
AR22
AR19
AR16
AR13
AR10

AR7

AR4

AR2

AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AL7
AL4

AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7

AK4
AJ25

TYCO_2013620-2_IVY BRIDGE

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

4

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

VSS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

Compal Secret Data

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

3

Deciphered Date

Deciphered Date

Deciphered Date

VSS

2

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

2

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

1

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

Date: Sheet of

11 62Wednesday, January 09, 2013

11 62Wednesday, January 09, 2013

11 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

R70
1K_0402_1%

5

+1.5V +1.5V

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

R83

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

ME@

VREF_CA

EVENT#

2.2U_0603_6.3V6K
C134

1

1

2

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7>
M_CLK_DDR#0<7>

DDR_A_BS0<7>
DDR_A_WE#<7>

DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

5

DDR_A_D0

C133

DDR_A_D1
DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS# M_ODT0
DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

R81

10K_0402_5%

0.1U_0402_16V7K

2.2U_0603_6.3V6K
C156

C155

1

1

2

2

10K_0402_5%

12

+VREF_DQ_DIMMA

0.1U_0402_16V7K

1K_0402_1%

+1.5V

12

12

R71

+VREF_DQ_DIMMA

D D

C C

B B

A A

VSS3

DQS#0

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1
VDD18
VSS28

DQ36

DQ37
VSS30

DM4

VSS31

DQ38

DQ39
VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

DM6

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

SDA

VTT2

4

DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>

1

2

+VREF_CA

2.2U_0603_6.3V6K
C136

DDR_A_DQS#[0..7]<7>
DDR_A_MA[0..15]<7>

R72

1K_0402_1%

1K_0402_1%

4*0402 1uf

1*0402 2.2uf

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

SMB_DATA_S3
SMB_CLK_S3

4

+0.75VS

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7>
M_ODT0 <7>

M_ODT1 <7>

0.1U_0402_16V7K
C135

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <13,15,36,43>
SMB_CLK_S3 <13,15,36,43>

DQ4
DQ5

DQ6
DQ7

A15
A14

A11

A7
A6

A4
A2

A0

CK1

BA1

S0#

NC2

SCL

G2

3

2

1

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN

+1.5V

12

12

R73

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Layout Note:
Place near DIMM

+1.5V

C139

10U_0603_6.3V6M

1

1

2

2

Layout Note:
Place near DIMM

+0.75VS

C152

1U_0402_6.3V6K

1

2

Compal Secret Data

Compal Secret Data

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4

C140

10U_0603_6.3V6M

C141

10U_0603_6.3V6M

1

1

2

2

7/28 Update connect GND directly

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

Deciphered Date

Deciphered Date

Deciphered Date

2

C143

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

1

2

Layout Note:
Place near DIMM

C146

0.1U_0402_16V7K

C147

C144

10U_0603_6.3V6M

C145

0.1U_0402_16V7K

1

1

2

2

0.1U_0402_16V7K

1

1

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

EVT Check

C148

0.1U_0402_16V7K

1

1

+

C149

@

220U_6.3V_M

2

2

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

LA-9603P

LA-9603P

LA-9603P

1

12 62Wednesday, January 09, 2013

12 62Wednesday, January 09, 2013

12 62Wednesday, January 09, 2013

1.0

1.0

1.0

R84

1K_0402_1%

1K_0402_1%

5

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDIMM2

+VREF_DQ_DIMMB
DDR_B_D0

2.2U_0603_6.3V6K

0.1U_0402_16V7K

C158

R85

1

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7>
M_CLK_DDR#2<7>

DDR_B_BS0<7>
DDR_B_WE#<7>

DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V6K

+3VS

1

2

5

DDR_B_D1
DDR_B_DM0

1

C157

DDR_B_D2
DDR_B_D3

2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

1 2

R95

10K_0402_5%

1 2

0.1U_0402_16V7K
R97 10K_0402_5%

C178

C177

1

2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

+VREF_DQ_DIMMB

D D

For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.

C C

B B

A A

+1.5V

12

12

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0
ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

4

+1.5V+1.5V

2

VSS

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

SMB_DATA_S3
SMB_CLK_S3

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7>
M_ODT2 <7>

M_ODT3 <7>

+VREF_CB

0.1U_0402_16V7K

2.2U_0603_6.3V6K
C160

C159

1

1

2

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf

SMB_DATA_S3 <12,15,36,43>
SMB_CLK_S3 <12,15,36,43>
+0.75VS

DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

VDD

A15
A14

VDD

A11

A7

VDD

A6
A4

VDD

A2

A0
VDD
CK1

VDD
BA1

VDD

S0#

VDD

NC

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SDA

SCL
VTT

4

3

DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_DQS#[0..7]<7>
DDR_B_MA[0..15]<7>

+1.5V

12

R86

1K_0402_1%

12

R87

1K_0402_1%

4*0402 1uf

1*0402 2.2uf

1*0402 2.2uf

3

2

Layout Note:
Place near DIMM

C163

1

2

Layout Note:
Place near DIMM

+0.75VS

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

C164

C165

1

1

2

2

C176

1

2

Deciphered Date

Deciphered Date

Deciphered Date

2

10U_0603_6.3V6M

C166

1

2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

Layout Note:
Place near DIMM

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C168

C167

1

1

2

2

1

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
C170

C169

1

1

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

0.1U_0402_16V7K

C171

C172

1

1

2

2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

LA-9603P

LA-9603P

LA-9603P

1

13 62Wednesday, January 09, 2013

13 62Wednesday, January 09, 2013

13 62Wednesday, January 09, 2013

1.0

1.0

1.0

5

W=20milsW=20mils

+RTCBATT+RTCVCC

R99

1K_0402_5%

1 2

1

C179
1U_0402_6.3V6K

2

D D

+RTCVCC

1 2

R101 1M_0402_5%

1 2

R102 330K_0402_5%

INTVRMEN

H󶁪󶁪󶁪󶁪Integrated VRM enable

*

L󶁪󶁪󶁪󶁪Integrated VRM disable

12

SHORT PADS

SM_INTRUDER#
PCH_INTVRMEN

CLRP1

C180
18P_0402_50V8J

NOGCLK@

+RTCVCC

(INTVRMEN should always be pull high.)

+3VS

1 2

R105 1K_0402_5%@

HIGH= Enable ( No Reboot )
LOW= Disable (Default)

*

C C

+3V_PCH

R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%

This signal has a weak internal pull-down
On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low

*

Needs to be pulled High for Chief River platfrom

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO<41>

B B

HDA_RST_AUDIO#<41>

HDA_SDOUT_AUDIO

A A

12

12

R112

33_0402_5%

1 2

R114

33_0402_5%

1 2

R116

33_0402_5%

1 2

R118

33_0402_5%

1 2

HDA_SPKR

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

ME_FLASH<42>

R878

1M_0402_5%

1 2

check with vender

Del Q10 check with codec
VDDIO using 3VALW

1 2

R98 10M_0402_5%

NOGCLK@

1 2

1

2

C183

1U_0402_6.3V6K

1 2

R103 20K_0402_5%

1 2

R100 20K_0402_5%

C182

1U_0402_6.3V6K

ME_FLASH

1 2

R107 1K_0402_1%@

+3V_PCH

+5VS

G

2

S

22P_0402_50V8J

Y1

NOGCLK@

HDA_SPKR<41>

HDA_SDIN0<41>

Q10
LBSS138LT1G_SOT-23-3

13

D

33_0402_5%

4

PCH_RTCX1
PCH_RTCX2

32.768KHZ_12.5PF_CM31532768DZFT

R03R03

1

C181
18P_0402_50V8J

NOGCLK@

2

CMOS

CLRP2

SHORT PADS

1

2

1

2

51_0402_5%

HDA_SYNC

R124

@

@

PCH_RTCX1

12

PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#

CLRP3

SHORT PADS

12

SM_INTRUDER#
PCH_INTVRMEN

HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#

HDA_SDIN0

R02

R109
0_0402_5%

1 2

HDA_SDOUT

@

12

R26410K_0402_5% @

12

PCH_JTAG_TCK

R110

SPI_CLK_PCH_R
SPI_SB_CS0#
SPI_SB_CS1#

SPI_SI
SPI_SO_R

SPI_CLK_PCH_R

12

R124;c190 close to U4.T3 pin

C190

R02

Remove R176

close to Y1

R182

GCLK@

PCH_GPIO33

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

1 2

0_0402_5%

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

GCLK_32K

RTCIHDA

JTAG

SPI

3

GCLK_32K <44>

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11
Y10

AB12
AB13

AH1

P3
V14
P1

R104 10K_0402_5%

SERIRQ

SERIRQ

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

SATA_DTX_R_IRX_P1
SATA_ITX_R_DRX_N1
SATA_ITX_R_DRX_P1

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2

HM70 Disable SATA Port 1,3

SATA_DTX_R_IRX_N4
SATA_DTX_R_IRX_P4
SATA_ITX_R_DRX_N4
SATA_ITX_R_DRX_P4

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATALED#
PCH_GPIO21
BBS_BIT0_R

LPC_AD0 <36,42>
LPC_AD1 <36,42>
LPC_AD2 <36,42>
LPC_AD3 <36,42>

LPC_FRAME# <36,42>

12

R111

37.4_0402_1%

1 2

R113

49.9_0402_1%

1 2

1 2

R115

750_0402_1%

12

R117 10K_0402_5%

12

R119 10K_0402_5%

12

R187 10K_0402_5%

+3VS

1 2

R266

1 2

R221

1 2

R127

1 2

R129

EC and Mini card debug port

SERIRQ <42>

12
12

1 2
1 2

12
12

1 2
1 2

12
12

+1.05VS_VCC_SATA

+1.05VS_SATA3

+3VS
+3VS
+3VS

SPI_WP#1

3.3K_0402_5%

SPI_HOLD#1

3.3K_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

2

+3VS

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

SATA_ITX_DRX_N0

C1840.01U_0402_16V7K@

SATA_ITX_DRX_P0

C1850.01U_0402_16V7K@

CAP on Conn, side

R3110_0402_5% HM76@
R3120_0402_5% HM76@

SATA_ITX_C_DRX_N1

C1980.01U_0402_16V7K

SATA_ITX_C_DRX_P1

C1990.01U_0402_16V7K

R3180_0402_5% HM70@
R3150_0402_5% HM70@

C2290.01U_0402_16V7K
C2370.01U_0402_16V7K

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

SPI_SB_CS1#
SPI_SO_R

SPI_SB_CS0#
SPI_SO_R SPI_SO_L

R02

R291
0_0402_5%

1 2

@

1 2

R188

33_0402_5%

R02

R130
0_0402_5%

1 2

@

1 2

33_0402_5%

R131

SATA_DTX_C_IRX_N0 <36>

SATA_DTX_C_IRX_P0 <36>
SATA_ITX_DRX_N0 <36>
SATA_ITX_DRX_P0 <36>

12
12

SATA_DTX_C_IRX_N2 <40>

SATA_DTX_C_IRX_P2 <40>
SATA_ITX_C_DRX_N2 <40>
SATA_ITX_C_DRX_P2 <40>

CAP on Conn, side

SATA_DTX_C_IRX_N1SATA_DTX_R_IRX_N1

SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N1

R55930_0402_5% @

SATA_ITX_DRX_P1

R55940_0402_5% @

SSD

ODD

HDD

8MB SPI ROM FOR ME
& Non-share ROM.

+3VS

U6

1

CS1#
SPI_SO1

SPI_WP#1

CS#

2

SO

3

WP#

4

GND

16M W25Q16BVSSIG SOIC 8P

U6 Rersver 4M+2M Solution

U5

1

CS#

SPI_WP#

CS#

2

SO

3

WP#

4

GND

W25Q32BVSSIG_SO8

VCC

HOLD#

SCLK

HOLD#

8
7

SPI_HOLD#1

6

SPI_CLK1

5

SPI_SI1

SI

+3VS

8

VCC

7

SPI_HOLD#

6

SPI_CLK_PCH SPI_CLK_PCH_R

SCLK

5

SPI_SI_R

SI

1

SATA_DTX_C_IRX_N1 <40>
SATA_DTX_C_IRX_P1 <40>
SATA_ITX_DRX_N1 <40>
SATA_ITX_DRX_P1 <40>

R02

R199
0_0402_5%

1 2

SPI_CLK_PCH_R

@

1 2

SPI_SI

R196
33_0402_5%

C191 0.1U_0402_16V7K

1 2

R02

R132
0_0402_5%

1 2

@

1 2

R133
33_0402_5%

HDD

SPI_SI

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet

14 62Wednesday, January 09, 2013

14 62Wednesday, January 09, 2013

14 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

of

5

LAN

WLAN

D D

C C

LAN

WLAN

B B

A A

PCIE_PRX_DTX_N1<37>

PCIE_PRX_DTX_P1<37>
PCIE_PTX_C_DRX_N1<37>
PCIE_PTX_C_DRX_P1<37>

PCIE_PRX_DTX_N2<36>

PCIE_PRX_DTX_P2<36>
PCIE_PTX_C_DRX_N2<36>
PCIE_PTX_C_DRX_P2<36>

CLK_PCIE_LAN#<37>
CLK_PCIE_LAN<37>

CLKREQ_LAN#<37>

CLK_PCIE_WLAN1#<36>
CLK_PCIE_WLAN1<36>

CLKREQ_WLAN#<36>

+3V_PCH

+3VS

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

1 2

C192 0.1U_0402_16V7K

1 2

C193 0.1U_0402_16V7K

1 2

C194 0.1U_0402_16V7K

1 2

C195 0.1U_0402_16V7K

HM70 not support
PCIE port 5-8

R02

1 2

R153 0_0402_5%@

1 2

R154 0_0402_5%@

R02

1 2

R151 0_0402_5%@
R152 10K_0402_5%

R02

R149 0_0402_5%@
R150 0_0402_5%@

R02

R156 0_0402_5%@
R158 10K_0402_5%

R147 10K_0402_5%

R301 10K_0402_5%

R165 10K_0402_5%

R168 10K_0402_5%

R170 10K_0402_5%

R172 10K_0402_5%

R174 10K_0402_5%

1 2
1 2

1 2

12

12

12

12

12

12

12

12

12

T52
T53

4

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

CLKREQ_LAN#_R

CLK_PCIE_WLAN1#_R
CLK_PCIE_WLAN1_R

CLKREQ_WLAN#_R

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_DATA1

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

E12
H14

SMBCLK

C9

SMBDATA

A12
C8

SML0CLK

G12

C13
E14
M16

M7

CL_CLK1

T11

P10

CL_RST1#

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

Y47

K43
F47
H47
K49

BIOS Request SKU ID

2

PCH_GPI011
PCH_SMBCLK
PCH_SMBDATA

DRAMRST_CNTRL_PCH

PCH_SML0CLK
PCH_SML0DATA

SML1CLK
SML1DATA

+3V_PCH

PEG_CLKREQ#_R

CLK_PCIE_VGA#_R CLK_PCIE_VGA#

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

CLKIN_DMI2#
CLKIN_DMI2

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

XTAL25_OUT

XCLK_RCOMP

27M_SSC

PCH_GPIO67

12

R134

10K_0402_5%

R140 10K_0402_5%

R143
10K_0402_5%

1 2

R02

R146 0_0402_5%@
R148 0_0402_5%@

R02

R155 10K_0402_5%
R157 10K_0402_5%

R159 10K_0402_5%
R160 10K_0402_5%

R162 10K_0402_5%
R163 10K_0402_5%

R164 10K_0402_5%
R166 10K_0402_5%

R167 10K_0402_5%

R171

90.9_0402_1%

1 2

12

R02

R144 0_0402_5%

1 2

@

1 2
1 2

CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

CLK_PCI_LPBACK <18>

PCH_GPIO67 <19>

+3V_PCH

+1.05VS_VCCDIFFCLKN

+3V_PCH

DRAMRST_CNTRL_PCH <7>

12

R139

1K_0402_5%

+3V_PCH

+3V_PCH

+3V_PCH +3VS

CLK_PCIE_VGACLK_PCIE_VGA_R

2.2K_0402_5%

1 2

R136

1 2

R135

2.2K_0402_5%

2.2K_0402_5%

1 2

R141

1 2

R142

2.2K_0402_5%

CLK_REQ_VGA# <23>

CLK_PCIE_VGA# <23>

R02

Remove R1381

close to Y2

GCLK@

XTAL25_IN
XTAL25_OUT

12P_0402_50V8J

Q60A
2N7002KDWH_SOT363-6

6 1

2
5

3

2N7002KDWH_SOT363-6
Q60B

Q61A
2N7002KDWH_SOT363-6

6 1

2
5

3

2N7002KDWH_SOT363-6
Q61B

CLK_PCIE_VGA <23>

12

GCLK_PCH_25MHZXTAL25_IN

R13820_0402_5%

25MHZ_10PF_7V25000014

1

C196

NOGCLK@

2

SMB_CLK_S3

2.2K_0402_5%

1 2

+3VS

1 2

2.2K_0402_5%

4

SMB_DATA_S3

EC_SMB_CK2

4

EC_SMB_DA2

1 2

NOGCLK@

R169 1M_0402_5%

3

OSC

2

NC

Y2

NOGCLK@

1

SMB_CLK_S3 <12,13,36,43>

DIMM1

R137

DIMM2

R138

MINI CARD

SMB_DATA_S3 <12,13,36,43>

EC_SMB_CK2 <23,39,42>

VGA
EC
thermal sensor

EC_SMB_DA2 <23,39,42>

2.2K_0402_5%

PCH_SML0CLK
PCH_SML0DATA

GCLK_PCH_25MHZ <44>

4

NC

1

OSC

1

12P_0402_50V8J

NOGCLK@

2

R544

C197

+3V_PCH

1 2

R545

2.2K_0402_5%

1 2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

PCH (2/9) PCIE, SMBUS, CLK

LA-9603P

LA-9603P

LA-9603P

1

15 62Wednesday, January 09, 2013

15 62Wednesday, January 09, 2013

15 62Wednesday, January 09, 2013

1.0

1.0

1.0

of

5

D D

U15
MC74VHC1G08DFT2G_SC70-5

3

1

VGATE<55>

PCH_PWROK

C C

G

A

4

SYS_PWROK

Y

2

B

P

5

+3VS

12

R180

@

100K_0402_1%

SYS_PWROK <6>

For Deep S3

AEPWROK can be connect to
PWROK if iAMT disable

R02

PCH_POK

+3V_PCH

B B

1 2

@

R191 0_0402_5%

R192 300_0402_5%

R194 10K_0402_5%
R5574 200K_0402_5%NODS3@
R197 10K_0402_5%

12

12
12
12

APWROK

PM_DRAM_PWRGD

SUSWARN#_R
AC_PRESENT_R
PCH_RSMRST#_R

PCH_PWROK<42>

PCH_APWROK<42>

PM_DRAM_PWRGD<6>

EC_RSMRST#<42>

SUSWARN#<42>

For Deep S3

PBTN_OUT#<42>

ACIN<42,49>

+V1.05S_VCCP

SUSACK#<42>

+3VS

PCH_PWROK

D29

CH751H-40PT_SOD323-2

+3V_PCH

4

DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>

1 2

R177 49.9_0402_1%

1 2

R178 750_0402_1%

4mil width and place
within 500mil of the PCH

R20

1 2

R304 0_0402_5%@

12

R18410K_0402_5%

R02

1 2

@

R190 0_0402_5%

1 2

@

R302 0_0402_5%

R02

1 2

@

R193 0_0402_5%

R20

R1455 0_0402_5%@

12

R02

1 2

@

R198 0_0402_5%

21

12

R200
10K_0402_5%

12

R201

10K_0402_5%

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP
RBIAS_CPY

SUSACK#_R

SYS_RST#

SYS_PWROK

PCH_POK

APWROK

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

3

DMI

System Power Management

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

FDI

FDI_RXP7

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

2

BJ14

FDI_CTX_PRX_N0

AY14

FDI_CTX_PRX_N1

BE14

FDI_CTX_PRX_N2

BH13

FDI_CTX_PRX_N3

BC12

FDI_CTX_PRX_N4

BJ12

FDI_CTX_PRX_N5

BG10

FDI_CTX_PRX_N6

BG9

FDI_CTX_PRX_N7

BG14

FDI_CTX_PRX_P0

BB14

FDI_CTX_PRX_P1

BF14

FDI_CTX_PRX_P2

BG13

FDI_CTX_PRX_P3

BE12

FDI_CTX_PRX_P4

BG12

FDI_CTX_PRX_P5

BJ10

FDI_CTX_PRX_P6

BH9

FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

A18

DSWODVREN

E22

PCH_DPWROK DPWROK_EC

R02

WAKE#

R185 0_0402_5%@

PM_CLKRUN#

SUS_STAT#

SLP_A#

SLP_SUS#_R

H_PM_SYNC

PCH_GPIO29

1 2

1 2

R186

R20

R1447 0_0402_5%

1 2

R261

10K_0402_5%

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>

FDI_INT <5>
FDI_FSYNC0 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>

1 2

R181 0_0402_5%NODS3@

1 2

R267 0_0402_5%

DS3@

10K_0402_5%

T74

T99

12

@

H_PM_SYNC <6>

+3V_PCH

@

PCIE_WAKE# <36,37>

+3V_PCH

SUSCLK <42>

PM_SLP_S5# <42>

PM_SLP_S4# <42>

PM_SLP_S3# <42>

SLP_SUS# <42,46>

*

DSWODVREN - On Die DSW VR Enable
H󶁪Enable
L󶁪Disable

PCH_RSMRST#_R

For Deep S3

DPWROK_EC <42>

For Deep S3

R189 8.2K_0402_5%@

1 2

R299 10K_0402_5%

Can be left NC
when IAMT is not
support on the
platfrom

12

1

+RTCVCC

12

R179
330K_0402_5%

12

R183

+3VS

330K_0402_5%

@

Can be left NC if no use
integrated LAN.

For Deep S3

+3VALW

1 2

R195 200K_0402_5%DS3@

AC_PRESENT_R

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

PCH (3/9) DMI,FDI,PM,

LA-9603P

LA-9603P

LA-9603P

1

1.0

1.0

16 62Wednesday, January 09, 2013

16 62Wednesday, January 09, 2013

16 62Wednesday, January 09, 2013

1.0

5

+3VS

4

3

2

1

12

D D

C C

B B

2.2K_0402_5%

R559

2.2K_0402_5%

+3VS

12

12

12

R523

R524

2.2K_0402_5%

CRT_DDC_CLK
CRT_DDC_DATA

R234

2.2K_0402_5%

EDID_CLK
EDID_DATA

DAC_BLU<34>
DAC_GRN<34>
DAC_RED<34>

+3VS

PCH_ENBKL<33>

PCH_ENVDD<33>

PCH_PWM<33>

EDID_CLK<33>

EDID_DATA<33>

1 2

R2042.2K_0402_5%

1 2

R2052.2K_0402_5%

12

R2062.37K_0402_1%

LVDS_ACLK#<33>
LVDS_ACLK<33>

LVDS_A0#<33>
LVDS_A1#<33>
LVDS_A2#<33>

LVDS_A0<33>
LVDS_A1<33>
LVDS_A2<33>

LVDS_BCLK#<33>
LVDS_BCLK<33>

LVDS_B0#<33>
LVDS_B1#<33>
LVDS_B2#<33>

LVDS_B0<33>
LVDS_B1<33>
LVDS_B2<33>

R208 150_0402_1%
R209 150_0402_1%
R210 150_0402_1%

CRT_DDC_CLK<34>
CRT_DDC_DATA<34>

CRT_HSYNC<34>
CRT_VSYNC<34>

12
12
12

DAC_BLU
DAC_GRN
DAC_RED

1K_0402_1%

EDID_CLK
EDID_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

LVD_VREF

CRT_DDC_CLK
CRT_DDC_DATA

CRT_IREF

12

R211

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0P
DDPC_1P
DDPC_2P
DDPC_3P

DDPD_0P
DDPD_1P
DDPD_2P
DDPD_3P

AP43
AP45

AM42
AM40

AP39

HDMI@

AP40

2.2K_0402_5%

P38

HDMICLK_NB

M39

HDMIDAT_NB

AT49
AT47
AT40

AV42

TMDS_B_DATA2#_PCH

AV40

TMDS_B_DATA2_PCH

AV45

TMDS_B_DATA1#_PCH

AV46

TMDS_B_DATA1_PCH

AU48

TMDS_B_DATA0#_PCH

AU47

TMDS_B_DATA0_PCH

AV47

TMDS_B_CLK#_PCH

AV49

TMDS_B_CLK_PCH

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

+3VS

12

R202

TMDS_B_HPD# <35>

12

R203

HDMI@

2.2K_0402_5%

HDMICLK_NB <35>
HDMIDAT_NB <35>

1 2

C200 0.1U_0402_16V7KHDMI@

1 2

C201 0.1U_0402_16V7KHDMI@

1 2

C202 0.1U_0402_16V7KHDMI@

1 2

C203 0.1U_0402_16V7KHDMI@

1 2

C204 0.1U_0402_16V7KHDMI@

1 2

C205 0.1U_0402_16V7KHDMI@

1 2

C206 0.1U_0402_16V7KHDMI@

1 2

C207 0.1U_0402_16V7KHDMI@

CAP move on Conn, side

HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_CLK-_CK <35>
HDMI_CLK+_CK <35>

HDMI

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_1N
DDPC_2N
DDPC_3N

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

CRT

DDPD_HPD

DDPD_0N
DDPD_1N
DDPD_2N
DDPD_3N

A A

Security Classification

Security Classification

Security Classification

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

2012/12/26 2012/07/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

17 62Wednesday, January 09, 2013

17 62Wednesday, January 09, 2013

17 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

+3VS

RP2

18

PCI_PIRQA#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

PCI_PIRQB#

8.2K_8P4R_5%

D D

C C

GNT1#/
GPIO51

B B

PCH_WL_OFF#

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

RP1

18

PCH_GPIO2

27

DGPU_PWR_EN_R

36

PCH_GPIO4

45

ODD_DA#_R

8.2K_8P4R_5%

1 2

R213 8.2K_0402_5%

1 2

R225 8.2K_0402_5%

1 2

R292 8.2K_0402_5%@

1 2

R557 8.2K_0402_5%@

1 2

R259 8.2K_0402_5%

1 2

R212 8.2K_0402_5%

1 2

R214 8.2K_0402_5%@

PCH_GPIO5
PCH_WL_OFF#
PCH_GPIO51
PCH_GPIO53
DGPU_PWR_EN1
DGPU_HOLD_RST#_R
DGPU_HOLD_RST#_R

Boot BIOS Strap bit1 BBS1

Boot BIOS

Bit10

0
1
0

@

Destination

Reserved
Reserved
SPI

*

LPC

NVDD_PWR_ENDGPU_PWR_EN_R

*

Bit11

0 1
1
1
0

1 2

R319 0_0402_5%

1 2

R215 1K_0402_5%@

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

NVDD_PWR_EN<54>

(Default)

GPIO55

1 2

R692 0_0402_5%@

PPT EDS DOC#474146

DGPU_HOLD_RST#<23>

CLK_PCI_LPBACK<15>

1 2

@

R222 0_0402_5%

4

HM70 not support USB3 port 3,4

DGPU_PWR_EN<23,25,42>

PCH_WL_OFF#<36>

CLK_PCI_EC<42>

CLK_PCI_DB<36>

USB30_RX_N1<45>

USB30_RX_P1<45>

USB30_TX_N1<45>

USB30_TX_P1<45>

ODD_DA#<40>

DGPU_PWR_EN1

T1833
T1829
T1825

T1834
T1832
T1826

T1835
T1831
T1827

T1836
T1830
T1828

R02

1 2

@

R553 0_0402_5%

R02

1 2

@

R691 0_0402_5%

1 2

R715 0_0402_5%@

PCH_PLTRST#<6>

1 2
1 2

3

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

USB30_RX_N1
USB30_RX_N2
USB30_RX_N3
USB30_RX_N4
USB30_RX_P1
USB30_RX_P2
USB30_RX_P3
USB30_RX_P4
USB30_TX_N1
USB30_TX_N2
USB30_TX_N3
USB30_TX_N4
USB30_TX_P1
USB30_TX_P2
USB30_TX_P3
USB30_TX_P4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#_R
DGPU_PWR_EN1
DGPU_PWR_EN_R

PCH_GPIO51
PCH_GPIO53
PCH_WL_OFF#

PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5

PCI_PME#<42>

R21922_0402_5%
R22022_0402_5%

12

R17322_0402_5% @

PCH_PLTRST#

CLK_PCI_LPBACK_R
CLK_PCI_EC_R
CLK_PCI_DB_R

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

RSVD

PCI

USB

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25
RSVD26

RSVD27
RSVD28

RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

2

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8
AY5

BA2
AT12

BF3

USB DEBUG=PORT1 AND PORT9

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

HM70 not support USB port 4,5,6,7,12,13

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

USBRBIAS

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB20_N0 <45>
USB20_P0 <45>
USB20_N1 <43>
USB20_P1 <43>
USB20_N2 <40>
USB20_P2 <40>
USB20_N3 <33>
USB20_P3 <33>

USB20_N8 <43>
USB20_P8 <43>
USB20_N9 <43>
USB20_P9 <43>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <44>
USB20_P11 <44>

1 2

R218

22.6_0402_1%

Within 500 mils

LEFT USB

(USB 3.0)
Touch Screen
Bluetooth
USB Camera

(CR-B/D USB)
(CR-B/D USB)
WLAN
CARD READER

USB_OC0# Share with USB_OC4#
due to same power switch

USB_OC0# <45>

USB_OC4# <43>

USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#

USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#

1

RP310K_1206_8P4R_5%

4 5
3 6
2 7
1 8

4 5
3 6
2 7
1 8

RP410K_1206_8P4R_5%

+3V_PCH

A A

PLT_RST#<23,36,37,42>

12

1

C208

0.1U_0402_16V7K

5

@

2

R223
100K_0402_5%

3

G

A

4

Y

B

P

5

MC74VHC1G08DFT2G_SC70-5

+3VS

1

PCH_PLTRST#

2

U7

@

4

Security Classification

Security Classification

Security Classification

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/12/26 2012/07/11

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

PCH (5/9) PCI, USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

Date: Sheet of

18 62Wednesday, January 09, 2013

18 62Wednesday, January 09, 2013

18 62Wednesday, January 09, 2013

1

1.0

1.0

1.0

5

D D

+3V_PCH

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

*

Deep S4,S5 wake event signal

*

RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)

C C

Deep S4,S5 wake event signal

+3VALW

B B

Weak internal pull-high

1 2

R235 10K_0402_5%

H󶁪On-Die voltage regulator enable
L󶁪On-Die PLL Voltage Regulator disable

+3VS

12

12

1 2

R240 1K_0402_5%@

For DS3

DS3@

R5530 10K_0402_5%

R245 10K_0402_5%@

R244
10K_0402_5%

R881
10K_0402_5%

12

1 2

@

PCH_GPIO37

R250

@

10K_0402_5%

R547
10K_0402_5%

EC_SMI#

PCH_GPIO27

+3VS

12

12

INTEL_BT_OFF#

+3VS

+3VS

+3V_PCH

EC_LID_OUT#<42>

R231 10K_0402_5%

+3VS

DGPU_PWROK<46,54>

PU on power side

BT_DISABLE<36>

PCH_BT_ON#<36,40>

+3VS

+3VS

+3VS

+3V_PCH

1 2

+3V_PCH

1 2

BIOS Request SKU ID

+3VS

12

R246

R711

UMA@

1 2

R708

OPT@

A A

1 2

UMA@

10K_0402_5%

10K_0402_5%

PCH_GPIO38
PCH_GPIO67

12

R298

OPT@

PCH_GPIO38 PCH_GPIO67

10K_0402_5%

10K_0402_5%

PCH_GPIO67 <15>

Function

4

1 2

R233 10K_0402_5%

1 2

R227 10K_0402_5%

1 2

R228 10K_0402_5%

1 2

R229 10K_0402_5%@

1 2

R230 1K_0402_5%

R02

1 2

R297 0_0402_5%@

1 2

R232 10K_0402_1%@

+3VS

1 2

R238 10K_0402_5%

+3VS

1 2

R241 10K_0402_5%

1 2

R243 10K_0402_5%

R242 10K_0402_5%

R03

1 2

R247 10K_0402_5%

1 2

R248 10K_0402_5%

1 2

R249 10K_0402_5%

1 2

R251 10K_0402_5%

3

PCH_GPIO69

0
1

U4F

PCH_GPIO0
PCH_GPIO1
PCH_GPIO6

EC_SCI#<42>
EC_SMI#<42>

mSATA_DET#<36>

ODD_EN<40>

INTEL_BT_OFF#<36>

EC_SCI#
EC_SMI#
PCH_GPIO12PCH_GPIO28
EC_LID_OUT#
mSATA_DET#

DGPU_PWROK_R
BT_DISABLE
ODD_EN
PCH_GPIO27
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
INTEL_BT_OFF#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
PCH_GPIO49
PCH_GPIO57

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

GPIO

Function

HM76 by PCH
HM70 by PCH

TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

NCTF

VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32

PECI

C40

PCH_GPIO68

B41

PCH_GPIO69

C41

PCH_GPIO70

A40

PCH_GPIO71

P4
AU16
P5

KBRST#

AY11
AY10

PCH_THRMTRIP#_R

T14
AY1

AH8
AK11
AH10
AK10

P37

BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

NV_CLE

2

+3VS +3VS

1 2

1 2

+3VS

+3VS

10K_0402_5%

+3VS

PCH_GPIO70

0
1

R236
10K_0402_5%

1 2

GATEA20 <42>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <23>

HM70@

R702

1 2

R707

HM76@

1 2

1 2

R239 390_0402_5%

INIT3_3V

This signal has weak internal PU,can't pull low

10K_0402_5%

10K_0402_5%

1 2

GV2@

R703

PCH_GPIO70PCH_GPIO69

R705

200K_0402_5%

UMA@

R22410K_0402_5%

12

R70410K_0402_5%

KBRST# <42>
H_CPUPWRGD <6>

H_THRMTRIP#

DMI Termination Voltage

NV_CLE

Set to Vcc when HIGH
Set to Vss when LOW

Weak internal
PU,Do not pull low

R217 1K_0402_5%

1

Function

UMA
N14P-GV2

KBRST#

12

CLOSE TO THE BRANCHING POINT

1 2

R226 10K_0402_5%

+1.8VS

12

R216

2.2K_0402_5%

H_SNB_IVB# <6>

+3VS

0 0 Optimus

Security Classification

Security Classification

5

1 1

UMA

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/12/26 2012/07/11

2012/12/26 2012/07/11

2012/12/26 2012/07/11

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-9603P

LA-9603P

LA-9603P

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

1

19 62Wednesday, January 09, 2013

19 62Wednesday, January 09, 2013

19 62Wednesday, January 09, 2013

1.0

1.0

1.0