Compal LA-9001P VIUS5, IdeaPad S405 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

VIUS5 LA-9001P M/B Schematics Document

AMD FP2 Processor with DDRIII + Husdon M3 FCH

AMD VGA Seymour XT

3 3

2012-05-31

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VAUS5 LA9001P M/B

E

1 50Thursday, May 31, 2012

0.3

A

Compal confidential

File Name :

AMD Seymour XT

B

C

D

E

1 1

VRAM 128x16, 64x16 DDR3 x 4

page 15,~21

LVDS

ranslator

t

RTD2132S

page 22 page 24

HDMI Conn.

4 * x1 PCI-E 2.0

LVDS Conn.

page 23

2 2

PCI Express Mini card Slot 1

WLAN

3 3

page 25

PCI Express Mini card Slot 2

page 25

USB(reserve for WiMAX)

PCI-E(WLAN)

SATA(SSD)

GPP0

LAN(10/100/Giga)

Realtek 8105E-VD (10/100) 8111F-CGT (Giga)

page 26

RJ45 CONN

page 27

SPI ROM

Gen2PCIE x 8

DP Port0

DP Port2

page 11

AMD FP2 APU

Trinity BGA 813 pin 27mm x 30mm

page 5,~8

x4 UMI Gen. 1

2.5GT/s per lane

Hudson M3

uFCBGA-656

24.5mm x 24.5mm

page 10,~14

LPC BUS

EC

ENE KB9012

page 31

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1333MT/s Upgradeable to 4G Memory

AZALIA

1*USB3.0,6*USB2.0

1*SATA serial

204pin DDRIII-SO-DIMM X 1

BANK 0, 1

page 9

2Channel Speaker

Single Digital MIC

IO Board page 32

Audio Codec

RealTek ALC259-VC2

CMOS Camera

page 30

page 23

USB PORT 3.0 x1(Left)

Audio Combo Jack (APPLE type)

Stereo HeadPhone Output Microphone Input

IO Board

page 33

Card Reader RTS 5178 (2in1)

USB PORT 2.0 x2(Right)

page 32

IO Board

page 30

page 32

IO Board

Sub-borad

OWER Board

P

LED Board

IO Board

4 4

A

B

Touch Pad

page 32

Thermal Sensor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

Int.KBD

page 32

SATA1

page 28

Compal Secret Data

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

SATA2.0 HDD CONN

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

page 29

Compal Electronics, Inc.

MB Block Diagram

VAUS5 LA9001P M/B

2 50Friday, May 25, 2012

E

0.3

A

Voltage Rails

power plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery d

on't exist

O

X

+5VALW

+3VALW

+1.1VALW

O

X

X X X

+1.5V

+1.5V_APU

O

X X

X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2_SUS SMB_EC_DA2_SUS

FCH_SCLK0 FCH_SDATA0

3 3

SMB_EC_CK2 SMB_EC_DA2

KB9012

+3VALW

KB9012

+3VALW

FCH

+3VS

KB9012

+3VS (LV shifter)

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

FCH SM Bus address

Device Address

DDR DIMM1

4 4

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V V V

1001 000Xb

X

X X

X

X X

EC SM Bus2 address

Device

Thermal Sen sor

SB-TSI(default)

VGA(thermal)

RTD2132S

WLAN WWAN

X X

V

+3VS +3VS

X XX

V

1001_101xb

1001_100xb

1000_001xb

1010_1000b

B

+5VS

+3VS

+2.5VS

+1.5VS

+1.2VS

+1.1VS

+0.75VS

+APU_CORE

+APU_CORE_NB

+VGA_CORE

+3.3VGS

+1.8VGS

+1.5VGS

+1.0VGS

Thermal Sensor

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

C

SLP_S3# SLP_S5# +VALW +V +VS Clock

ON

ONONON ON

ON

OFF

HIGH HIGH

HIGHHIGH

HIGH

LOW

HIGH

LOW LOW

LOW

OFF

D

E

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0 1 2 3

OO

4 5 6

X

7

PCB Revision

0.3

ID BRD ID R a Rb Vab

x

0

0V

0.25V

0.5V

0.82VR01 EVT

1

2

3

R10 MP0

R03 PVT

R02 DVT

1

00K

100K

8.2K

18K

33K

Ra = R1562 Rb = R1564

USB Port Table

X

SB 2.0 Port

USB 3.0U

0 1 2 3

4 External USB Port

USB Port (Right Side 1) USB Port (Right Side 2) Mini Card(WLAN) Camera

4 5

FCH

X

XX

X

APU RTD2132

X X

V

+1.5V

XX

X X

X

0 1

XHCI

2 3

USB OC MAPPING

CardReader

6 7 8 9

10

USB Port (Left Side)

11 12 13

OC# USB Port

0 1

USB20 port10

USB20 port0 port1

USB30 port0

2 3

APU PCIE PORT LIST

Port Device

1

LAN

2

WLAN

3 4

FCH PCIE PORT LIST

Port Device

1 2 3 4

BOM Structure Table

BTO ItemBOM Structure

A4R1@ A4R3@ A6R1@ A6R3@ A8R1@ A8R3@ A10R1@ A10R3@ SXTR1@ SXTR3@ A70MR1@ A70MR3@ PX@ CMOS@ UMA@ GAS@ 8105@ GIGA@ HDMI@ NONAOAC@ AOAC@ ME@ DEBUG@ @ SSD@

A4 BGA APU (R1 compal part)

A4 BGA APU (R3 compal part)

A6 BGA APU (R1 compal part)

A6 BGA APU (R3 compal part)

A8 BGA APU (R1 compal part)

A8 BGA APU (R3 compal part)

A10 BGA APU (R1 compal part)

A10 BGA APU (R3 compal part)

Seymour XT GPU (R1 compal part)

Seymour XT GPU (R3 compal part)

A70 Hudson M3 FCH (R1 compal part)

A70 Hudson M3 FCH (R3 compal part)

Common VGA circuit

CMOS Camera part

UMA strap pin

Gastube

RTL8105E

RTL8111F

HDMI part

No AOAC function

support AOAC function

ME part

Debug Switch (MP will remove)

Unpop

SSD part

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

VAUS5 LA9001P M/B

E

3 50Tuesday, May 29, 2012

0.3

A

B

C

D

E

Power-Up/Down Sequence

"Thames" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies, except for VDDR3, must fully reach their respective

‧

nominal voltages within 20 ms of the start of the ramp-up sequence, though a

1 1

shorter ramp-up duration is preferred. There is no timing requirement on the ramp up of VDDR3 relative to other power rails.

The external pull-up resistors on the DDC/AUX signals (if applicable) should

‧

ramp up before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO enabled designs, VDDC must ramp up before VDD_CT at system power up.

For power down, reversing the ramp-up sequence is recommended

‧

VDDR3(3.3VGS)

Without BACO option :

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode) PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10

PCIE_VDDC

VDDR3

BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode)

VDDR1

VDDC/VDDCI

Voltage

1.8V

1.0V

3.3V

Same as VDDC

1.5V

TBD

PX 3.0

OFF

BACO Mode

ON

ON Same as PCIE_VDDC

OFF

1679mA

775mA

1.1A

60mA

70mA

1.2A

28

PCIE_VDDC(1.0V)

2 2

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

PERSTb

REFCLK

Straps Reset

Straps Valid

3 3

Global ASIC Reset

PX5.0

less than 20ms (Seymour)

4 4

A

T4+16clock

B

iGPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

PE_GPIO0(PXS_RST#)

PE_GPIO1(PXS_PWREN)

+3.3VALW

+1.5V_IO

+5VLAW

Compal Secret Data

Deciphered Date

D

MOS

PWM

Regulator

dGPU

1

2

5

+3.3VGS

+1.0VGS

+1.8VGS

+VGA_CORE

BIF_VDDC

Short PX_MODE and PX_PWREN

B+

egulator

R

+B

Regulator

Title

Size Document Number Rev

Date: Sheet of

+1.5VGS

3

+VGA_CORE

4

Compal Electronics, Inc.

VGA Notes List

VAUS5 LA9001P M/B

E

0.3

4 50Friday, May 25, 2012

0.3

A

B

C

D

E

PCIE_CRX_GTX_P[0..7]<15>

UCPU1A

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

1 1

PCIE_CRX_DTX_P0<26> PCIE_CRX_DTX_N0<26> PCIE_CRX_DTX_P1<25>

2 2

PCIE_CRX_DTX_N1<25>

UMI_RXP0<10> UMI_RXN0<10> UMI_RXP1<10> UMI_RXN1<10> UMI_RXP2<10> UMI_RXN2<10> UMI_RXP3<10> UMI_RXN3<10>

+1.2VS

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0402_ 1%R1 196_0402_ 1%

P_ZVDDP

AP1

P_GFX_RXP[0]

AP2

P_GFX_RXN[0]

AM1

P_GFX_RXP[1]

AM2

P_GFX_RXN[1]

AK3

P_GFX_RXP[2]

AK4

P_GFX_RXN[2]

AJ1

P_GFX_RXP[3]

AJ2

P_GFX_RXN[3]

AH4

P_GFX_RXP[4]

AH3

P_GFX_RXN[4]

AF2

P_GFX_RXP[5]

AF1

P_GFX_RXN[5]

AD1

P_GFX_RXP[6]

AD2

P_GFX_RXN[6]

AB3

P_GFX_RXP[7]

AB4

P_GFX_RXN[7]

AA1

P_GFX_RXP[8]

AA2

P_GFX_RXN[8]

Y4

P_GFX_RXP[9]

Y3

P_GFX_RXN[9]

V2

P_GFX_RXP[10]

V1

P_GFX_RXN[10]

T1

P_GFX_RXP[11]

T2

P_GFX_RXN[11]

P3

P_GFX_RXP[12]

P4

P_GFX_RXN[12]

N1

P_GFX_RXP[13]

N2

P_GFX_RXN[13]

M4

P_GFX_RXP[14]

M3

P_GFX_RXN[14]

K2

P_GFX_RXP[15]

K1

P_GFX_RXN[15]

AH5

P_GPP_RXP[0]

AH6

P_GPP_RXN[0]

AG5

P_GPP_RXP[1]

AG6

P_GPP_RXN[1]

AE6

P_GPP_RXP[2]

AE5

P_GPP_RXN[2]

AD6

P_GPP_RXP[3]

AD5

P_GPP_RXN[3]

AM10

P_UMI_RXP[0]

AN10

P_UMI_RXN[0]

AN8

P_UMI_RXP[1]

AM8

P_UMI_RXN[1]

AP8

P_UMI_RXP[2]

AR8

P_UMI_RXN[2]

AR7

P_UMI_RXP[3]

AP7

P_UMI_RXN[3]

AR11

P_ZVDDP

TRINITY-A8-SERIES_BGA813

A8R3@

P_GFX_TXP[0] P_GFX_TXN[0] P_GFX_TXP[1] P_GFX_TXN[1] P_GFX_TXP[2] P_GFX_TXN[2] P_GFX_TXP[3] P_GFX_TXN[3] P_GFX_TXP[4] P_GFX_TXN[4] P_GFX_TXP[5] P_GFX_TXN[5] P_GFX_TXP[6] P_GFX_TXN[6] P_GFX_TXP[7] P_GFX_TXN[7] P_GFX_TXP[8]

GRAPHICSGPPUMI

P_GFX_TXN[8] P_GFX_TXP[9]

P_GFX_TXN[9] P_GFX_TXP[10] P_GFX_TXN[10] P_GFX_TXP[11] P_GFX_TXN[11] P_GFX_TXP[12] P_GFX_TXN[12] P_GFX_TXP[13] P_GFX_TXN[13] P_GFX_TXP[14] P_GFX_TXN[14] P_GFX_TXP[15] P_GFX_TXN[15]

P_GPP_TXP[0]

P_GPP_TXN[0]

P_GPP_TXP[1]

P_GPP_TXN[1]

P_GPP_TXP[2]

P_GPP_TXN[2]

P_GPP_TXP[3]

P_GPP_TXN[3]

P_UMI_TXP[0]

P_UMI_TXN[0]

P_UMI_TXP[1]

P_UMI_TXN[1]

P_UMI_TXP[2]

P_UMI_TXN[2]

P_UMI_TXP[3]

P_UMI_TXN[3]

P_ZVSS

AN1 AN2 AM4 AM3 AK2 AK1 AH1 AH2 AF3 AF4 AE1 AE2 AD4 AD3 AB2 AB1 Y1 Y2 V3 V4 U1 U2 T4 T3 P2 P1 M1 M2 K3 K4 J1 J2

AG7 AG8 AE7 AE8 AD7 AD8 AB6 AB5

AN6 AM6 AP6 AR6 AP4 AR4 AP3 AR3

AP11

Compensation Resistor to VSS Compensation Resistor to VDDP

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

PCIE_CTX_C_DRX_P0 PCIE_CTX_C_DRX_N0 PCIE_CTX_C_DRX_P1 PCIE_CTX_C_DRX_N1

UMI_TXP0_C UMI_TXN0_C UMI_TXP1_C UMI_TXN1_C UMI_TXP2_C UMI_TXN2_C UMI_TXP3_C UMI_TXN3_C

1 2

P_ZVSS

R2 196_0402_ 1%R2 196_0402_ 1%

1 2

C1 0.1U_0402_16V7KPX@C1 0.1U_0402_16V7KPX@

1 2

C2 0.1U_0402_16V7KPX@C2 0.1U_0402_16V7KPX@

1 2

C3 0.1U_0402_16V7KPX@C3 0.1U_0402_16V7KPX@

1 2

C4 0.1U_0402_16V7KPX@C4 0.1U_0402_16V7KPX@

1 2

C5 0.1U_0402_16V7KPX@C5 0.1U_0402_16V7KPX@

1 2

C6 0.1U_0402_16V7KPX@C6 0.1U_0402_16V7KPX@

1 2

C7 0.1U_0402_16V7KPX@C7 0.1U_0402_16V7KPX@

1 2

C8 0.1U_0402_16V7KPX@C8 0.1U_0402_16V7KPX@

1 2

C9 0.1U_0402_16V7KPX@C9 0.1U_0402_16V7KPX@

1 2

C10 0.1U_0402_16V7KPX@C10 0.1U_0402_16V7KPX@

1 2

C11 0.1U_0402_16V7KPX@C11 0.1U_0402_16V7KPX@

1 2

C12 0.1U_0402_16V7KPX@C12 0.1U_0402_16V7KPX@

1 2

C13 0.1U_0402_16V7KPX@C13 0.1U_0402_16V7KPX@

1 2

C14 0.1U_0402_16V7KPX@C14 0.1U_0402_16V7KPX@

1 2

C15 0.1U_0402_16V7KPX@C15 0.1U_0402_16V7KPX@

1 2

C16 0.1U_0402_16V7KPX@C16 0.1U_0402_16V7KPX@

1 2

C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K

1 2

C34 0.1U_0402_16V7KC34 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C39 0.1U_0402_16V7KC39 0.1U_0402_16V7K

1 2

C40 0.1U_0402_16V7KC40 0.1U_0402_16V7K

1 2

C41 0.1U_0402_16V7KC41 0.1U_0402_16V7K

1 2

C42 0.1U_0402_16V7KC42 0.1U_0402_16V7K

1 2

C43 0.1U_0402_16V7KC43 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KC44 0.1U_0402_16V7K

PCIE_CTX_GRX_P[0..7] < 15>

PCIE_CTX_GRX_N[0..7] <15>PCIE_CRX_GTX_N[0..7]<15>

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_CTX_DRX_P0 <26> PCIE_CTX_DRX_N0 <26> PCIE_CTX_DRX_P1 <25> PCIE_CTX_DRX_N1 <25>

UMI_TXP0 <10> UMI_TXN0 <10> UMI_TXP1 <10> UMI_TXN1 <10> UMI_TXP2 <10> UMI_TXN2 <10> UMI_TXP3 <10> UMI_TXN3 <10>

LAN

WLAN

All power supplies in Power Sequencing Group A must be stable and within specification before any power supply in Power Sequencing Group B is greater than 10 percent of its specified typical operating value.

3 3

All power supplies in Power Sequencing Group B must be stable and within specification one ms before the assertion of PWROK.

No sequencing relationships are required between the power sequencing groups during S3 entry. DDR3 compatible processors require VDDIO to remain powered and within specification during the S3 sleep state. All other processor power supply planes are powered down during S3.

Power Sequence of APU

+1.5V (+1.5V_APU)

UCPU1

A4R3@UCPU1

A4R3@

UCPU1

A6R3@UCPU1

A6R3@

UCPU1

A10R3@UCPU1

A10R3@

ZZZ1

+2.5VS (+APU_VDDA)

+1.5VS

A6 SERIES ZM212169E2451 2.1G BGA813

A4 SERIES ZM198169E2351 1.9G BGA813

UCPU1

4 4

A4 SERIES AM4355SHE23HJ 1.9G BGA813

UCPU1

A8 SERIES AM4555SHE44HJ 1.6G BGA813

A

A4R1@UCPU1

A4R1@

A8R1@UCPU1

A8R1@

B

A6 SERIES ZM212169E2451 2.1G BGA813

UCPU1

A6R1@UCPU1

A6R1@

A6 SERIES AM4455SHE24HJ 2.1G BGA813

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A10 SERIES ZM202268E4451 2G BGA813P

A10 SERIES AM4655SIE44HJ 2G BGA813P

Issued Date

C

LA9001P

DA60000TW00

UCPU1

A10R1@UCPU1

A10R1@

2012/01/15 2013/01/15

DA60000TW00

Compal Secret Data

Deciphered Date

+APU_CORE

+APU_CORE_NB

+1.2VS

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FP2 PCIE/UMI

VAUS5 LA9001P M/B

E

5 50Tuesday, May 29, 2012

Group A

Group B

0.3

A

B

C

D

E

1 1

2 2

3 3

DDRA_SMA[15..0]<9>

DDRA_SBS0#<9> DDRA_SBS1#<9> DDRA_SBS2#<9> DDRA_SDM[7..0]<9>

DDRA_SDQS0<9> DDRA_SDQS0#<9> DDRA_SDQS1<9> DDRA_SDQS1#<9> DDRA_SDQS2<9> DDRA_SDQS2#<9> DDRA_SDQS3<9> DDRA_SDQS3#<9> DDRA_SDQS4<9> DDRA_SDQS4#<9> DDRA_SDQS5<9> DDRA_SDQS5#<9> DDRA_SDQS6<9> DDRA_SDQS6#<9> DDRA_SDQS7<9> DDRA_SDQS7#<9>

DDRA_CLK0<9> DDRA_CLK0#<9> DDRA_CLK1<9> DDRA_CLK1#<9>

DDRA_CKE0<9> DDRA_CKE1<9>

DDRA_ODT0<9> DDRA_ODT1<9>

DDRA_SCS0#<9> DDRA_SCS1#<9>

DDRA_SRAS#<9> DDRA_SCAS#<9> DDRA_SWE#<9>

MEM_MA_RST#<9> MEM_MA_EVENT#<9>

+MEM_VREF

+1.5V_APU

Place them close to APU within 1"

Place them close to APU within 1"Place them close to APU within 1"

15mil

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

UCPU1B

AA28

MA_ADD[0]

R29

MA_ADD[1]

T30

MA_ADD[2]

R28

MA_ADD[3]

R26

MA_ADD[4]

P26

MA_ADD[5]

P27

MA_ADD[6]

P30

MA_ADD[7]

P29

MA_ADD[8]

M28

MA_ADD[9]

AB26

MA_ADD[10]

M26

MA_ADD[11]

M29

MA_ADD[12]

AE27

MA_ADD[13]

L26

MA_ADD[14]

L27

MA_ADD[15]

AB27

MA_BANK[0]

AA29

MA_BANK[1]

M30

MA_BANK[2]

D16

MA_DM[0]

D20

MA_DM[1]

E25

MA_DM[2]

F30

MA_DM[3]

AK29

MA_DM[4]

AL25

MA_DM[5]

AM20

MA_DM[6]

AM16

MA_DM[7]

G17

MA_DQS_H[0]

H17

MA_DQS_L[0]

F22

MA_DQS_H[1]

G22

MA_DQS_L[1]

E26

MA_DQS_H[2]

F26

MA_DQS_L[2]

H30

MA_DQS_H[3]

G30

MA_DQS_L[3]

AL29

MA_DQS_H[4]

AL30

MA_DQS_L[4]

AH25

MA_DQS_H[5]

AJ25

MA_DQS_L[5]

AK20

MA_DQS_H[6]

AL20

MA_DQS_L[6]

AK15

MA_DQS_H[7]

AL15

MA_DQS_L[7]

W29

MA_CLK_H[0]

Y30

MA_CLK_L[0]

W26

MA_CLK_H[1]

W27

MA_CLK_L[1]

U29

MA_CLK_H[2]

V30

MA_CLK_L[2]

U26

MA_CLK_H[3]

U27

MA_CLK_L[3]

L29

MA_CKE[0]

K30

MA_CKE[1]

AD30

MA0_ODT[0]

AG28

MA0_ODT[1]

AE26

MA1_ODT[0]

AG29

MA1_ODT[1]

AD26

MA0_CS_L[0]

AE29

MA0_CS_L[1]

AB30

MA1_CS_L[0]

AF30

MA1_CS_L[1]

AB29

MA_RAS_L

AD29

MA_CAS_L

AD28

MA_WE_L

J28

MA_RESET_L

AA26

MA_EVENT_L

G32

M_VREF

AJ32

M_ZVDDIO

TRINITY-A8-SERIES_BGA813

A8R3@

MA_DATA[0] MA_DATA[1] MA_DATA[2] MA_DATA[3] MA_DATA[4] MA_DATA[5] MA_DATA[6] MA_DATA[7]

MA_DATA[8]

MA_DATA[9] MA_DATA[10] MA_DATA[11] MA_DATA[12] MA_DATA[13] MA_DATA[14] MA_DATA[15]

MA_DATA[16] MA_DATA[17] MA_DATA[18] MA_DATA[19] MA_DATA[20] MA_DATA[21] MA_DATA[22] MA_DATA[23]

MA_DATA[24] MA_DATA[25] MA_DATA[26] MA_DATA[27] MA_DATA[28] MA_DATA[29] MA_DATA[30] MA_DATA[31]

MA_DATA[32] MA_DATA[33] MA_DATA[34] MA_DATA[35] MA_DATA[36] MA_DATA[37] MA_DATA[38] MA_DATA[39]

MA_DATA[40] MA_DATA[41] MA_DATA[42] MA_DATA[43] MA_DATA[44] MA_DATA[45] MA_DATA[46] MA_DATA[47]

MA_DATA[48] MA_DATA[49] MA_DATA[50] MA_DATA[51] MA_DATA[52] MA_DATA[53] MA_DATA[54] MA_DATA[55]

MA_DATA[56] MA_DATA[57] MA_DATA[58] MA_DATA[59] MA_DATA[60] MA_DATA[61] MA_DATA[62] MA_DATA[63]

F15 E15 H19 F19 E14 H15 E17 D18

G20 E20 H23 G23 E19 H20 E22 D22

H25 F25 D28 D29 E23 D24 D26 D27

G28 G29 H27 J29 E28 F27 H29 H28

AH29 AJ30 AM28 AM27 AH27 AH28 AJ29 AK27

AK26 AJ26 AK23 AJ23 AM26 AL26 AM24 AL23

AK22 AH22 AK19 AH19 AM22 AL22 AJ20 AL19

AK17 AJ17 AK14 AH14 AM18 AL17 AH15 AL14

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] <9>

MEM_MB_EVENT#

UCPU1C

Y33

MB_ADD[0]

R32

MB_ADD[1]

T31

MB_ADD[2]

P33

MB_ADD[3]

P32

MB_ADD[4]

P31

MB_ADD[5]

N32

MB_ADD[6]

M33

MB_ADD[7]

M32

MB_ADD[8]

L32

MB_ADD[9]

AB31

MB_ADD[10]

M31

MB_ADD[11]

K32

MB_ADD[12]

AF33

MB_ADD[13]

K33

MB_ADD[14]

J32

MB_ADD[15]

AB33

MB_BANK[0]

AA32

MB_BANK[1]

K31

MB_BANK[2]

C18

MB_DM[0]

B23

MB_DM[1]

C28

MB_DM[2]

D31

MB_DM[3]

AM31

MB_DM[4]

AN30

MB_DM[5]

AR24

MB_DM[6]

AN18

MB_DM[7]

B18

MB_DQS_H[0]

A18

MB_DQS_L[0]

B24

MB_DQS_H[1]

A24

MB_DQS_L[1]

B30

MB_DQS_H[2]

B29

MB_DQS_L[2]

D32

MB_DQS_H[3]

D33

MB_DQS_L[3]

AM32

MB_DQS_H[4]

AM33

MB_DQS_L[4]

AN28

MB_DQS_H[5]

AP29

MB_DQS_L[5]

AP23

MB_DQS_H[6]

AP24

MB_DQS_L[6]

AR18

MB_DQS_H[7]

AP18

MB_DQS_L[7]

W32

MB_CLK_H[0]

Y32

MB_CLK_L[0]

V33

MB_CLK_H[1]

V32

MB_CLK_L[1]

U32

MB_CLK_H[2]

V31

MB_CLK_L[2]

T33

MB_CLK_H[3]

T32

MB_CLK_L[3]

H32

MB_CKE[0]

H33

MB_CKE[1]

AF31

MB0_ODT[0]

AH31

MB0_ODT[1]

AE32

MB1_ODT[0]

AH33

MB1_ODT[1]

AD31

MB0_CS_L[0]

AF32

MB0_CS_L[1]

AC32

MB1_CS_L[0]

AG32

MB1_CS_L[1]

AB32

MB_RAS_L

AD32

MB_CAS_L

AD33

MB_WE_L

H31

MB_RESET_L

Y31

MB_EVENT_L

TRINITY-A8-SERIES_BGA813

A8R3@

MB_DATA[0] MB_DATA[1] MB_DATA[2] MB_DATA[3] MB_DATA[4] MB_DATA[5] MB_DATA[6] MB_DATA[7]

MB_DATA[8]

MB_DATA[9] MB_DATA[10] MB_DATA[11] MB_DATA[12] MB_DATA[13] MB_DATA[14] MB_DATA[15]

MB_DATA[16] MB_DATA[17] MB_DATA[18] MB_DATA[19] MB_DATA[20] MB_DATA[21] MB_DATA[22] MB_DATA[23]

MB_DATA[24] MB_DATA[25] MB_DATA[26] MB_DATA[27] MB_DATA[28] MB_DATA[29] MB_DATA[30] MB_DATA[31]

MB_DATA[32] MB_DATA[33] MB_DATA[34] MB_DATA[35] MB_DATA[36] MB_DATA[37] MB_DATA[38] MB_DATA[39]

MB_DATA[40] MB_DATA[41] MB_DATA[42] MB_DATA[43] MB_DATA[44] MB_DATA[45] MB_DATA[46] MB_DATA[47]

MB_DATA[48] MB_DATA[49] MB_DATA[50] MB_DATA[51] MB_DATA[52] MB_DATA[53] MB_DATA[54] MB_DATA[55]

MB_DATA[56] MB_DATA[57] MB_DATA[58] MB_DATA[59] MB_DATA[60] MB_DATA[61] MB_DATA[62] MB_DATA[63]

C16 B17 B20 C20 A16 B16 B19 A20

B22 C22 A26 B26 B21 A22 C24 B25

A28 B28 B31 A32 C26 B27 A30 C30

B33 C32 F33 F32 B32 C31 E32 F31

AK32 AL32 AP32 AN31 AK31 AK33 AN32 AP33

AP30 AR30 AP27 AN26 AR32 AP31 AR28 AP28

AP25 AN24 AR22 AP21 AP26 AR26 AN22 AP22

AR20 AP19 AP16 AR16 AN20 AP20 AP17 AN16

EVENT# pull high 0.75V reference voltage

+1.5V_APU

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT#

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V_APU

1 2

B

1

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

+MEM_VREF

2

C46

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FP2 DDRIII Memory I/F

VAUS5 LA9001P M/B

6 50Tuesday, May 29, 2012

E

0.3

A

Place near APU

1 2

LVDS

1 1

DP0_TXP0_C<22> DP0_TXN0_C<22>

HDMI

2 2

3 3

C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K

1 2

C4888 0.1U_0402_16V7KC4888 0.1U_0402_16V7K

DP2_TXP0<24> DP2_TXN0<24>

DP2_TXP1<24> DP2_TXN1<24>

DP2_TXP2<24> DP2_TXN2<24>

DP2_TXP3<24> DP2_TXN3<24>

APU_CLK<10> APU_CLK#<10>

APU_DISP_CLK<10> APU_DISP_CLK#<10>

APU_SVC<43> APU_SVD<43>

APU_SVT<43>

APU_RST#<10> APU_PWRGD<10,43>

APU_PROCHOT#<10>

APU_VDD_SEN_L<43>

APU_VDDNB_SEN_H<43>

APU_VDD_SEN_H<43>

Route as differential w

ith APU_VDD_SEN_L

APU_SIC APU_SID

APU_PWRGD

APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

DP0_TXP0 DP0_TXN0

B

UCPU1D

H2

DP0_TXP[0]

H1

DP0_TXN[0]

H3

DP0_TXP[1]

H4

DP0_TXN[1]

F4

DP0_TXP[2]

F3

DP0_TXN[2]

F1

DP0_TXP[3]

F2

DP0_TXN[3]

E2

DP1_TXP[0]

E1

DP1_TXN[0]

D4

DP1_TXP[1]

D3

DP1_TXN[1]

D1

DP1_TXP[2]

D2

DP1_TXN[2]

C1

DP1_TXP[3]

C2

DP1_TXN[3]

B2

DP2_TXP[0]

A2

DP2_TXN[0]

B3

DP2_TXP[1]

A3

DP2_TXN[1]

B4

DP2_TXP[2]

A4

DP2_TXN[2]

B5

DP2_TXP[3]

A5

DP2_TXN[3]

AL9

CLKIN_H

AK9

CLKIN_L

AL7

DISP_CLKIN_H

AK7

DISP_CLKIN_L

E5

SVC

E6

SVD

D6

SVT

AJ11

SIC

AH11

SID

AK11

RESET_L

AH9

PWROK

AL12

PROCHOT_L

AK5

THERMTRIP_L

AR10

ALERT_L

E11

TDI

G11

TDO

H12

TCK

F11

TMS

H11

TRST_L

E8

DBRDY

E7

DBREQ_L

G6

VSS_SENSE

H6

VDDP_SENSE

H5

VDDNB_SENSE

G7

VDDIO_SENSE

G5

VDD_SENSE

H7

VDDR_SENSE

TRINITY-A8-SERIES_BGA813

A8R3@

DISPLAY PORT 0DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD

DISPLAY PORT MISC.RSVD TEST

DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST6

TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

TEST4

TEST5

RSVD RSVD RSVD RSVD RSVD

M5 M6

L5 L6

J5 J6

P5 P6

R5 R6

U5 U6

M7 L7 J7 P7 R7 U7

C6 D7 A6

B6

AL6 Y23 V23 G9 F9 E9 G8 F12 E12 F14 G12 AJ8 AH8 G14 H14 V25 Y25 AH32 R25 T25 AL5

AP10

T23 R23

L8 P8 AH12 AJ12 AK12

DP0_AUXP DP0_AUXN

DP_AUX_ZVSS

APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 TEST25_H TEST25_L

APU_TEST31

APU_TEST35

C

1 2

C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K

1 2

C5088 0.1U_0402_16V7KC5088 0.1U_0402_16V7K

LVDS_HPD <22>

HDMI_DET <24>

DP_INT_PWM <22>

1 2

R15 150_0402_1%R15 150_0402_1%

T1T1 T2T2 T3T3 T4T4 T5T5 T6T6

1 2

R17 510_0402_1%R17 510_0402_1%

1 2

R18 510_0402_1%R18 510_0402_1%

T7T7 T8T8 T17T17 T18T18

T19T19 T20T20

T9T9 T10T10

1 2

R21 39.2_0402_1%R21 39.2_0402_1%

1 2

R22 300_0402_5%HDMI@R22 300_0402_5%HDMI@

1 2

R23 300_0402_5%@R23 300_0402_5%@

ALLOW_STOP <10>

DP0_AUXP_C <22> DP0_AUXN_C <22>

HDMI_CLK <2 4> HDMI_DATA <24>

+1.2VS

+1.5V_APU

D

To LVDS Translater

To HDMI

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

THERMTRIP shutdown temperature: 125 degree

1K_0402_5%

APU_THERMTRIP#

DP0_AUXP

DP0_AUXN

R12

1K_0402_5%

1 2

+1.5V_APU

R19

12

1 2

B

2

E

3 1

MMBT3904_NL_SOT23-3

R10 1.8K_0402_5%R10 1.8K_0402_5%

R11 1.8K_0402_5%R11 1.8K_0402_5%

10K_0402_5%

MMBT3904_NL_SOT23-3

R16 0_0402_5%R16 0_0402_5%

R20

R20 10K_0402_5%

10K_0402_5%

Q2

C

12

+3VS+1.5V_APU

12

R14

@

2

B

Q1

@

Q1

@

E

31

C

1 2

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the FCH to transition the system to S5 immediately

1 2

R24 0_0402_5%R24 0_0402_5%

1 2

R25 0_0402_5%@R25 0_0402_5%@

R13

R13 10K_0402_5%

10K_0402_5%

@

E

H_PROCHOT# <31,36,43>

H_THERMTRIP# <12>

MAINPWON < 31,36,38>

+1.5V_APU

1 2

R215 1K_0402_5%R215 1K_0402_5%

1 2

R26 1K_0402_5%R26 1K_0402_5%

1 2

R28 1K_0402_5%R28 1K_0402_5%

1 2

R31 1K_0402_5%R31 1K_0402_5%

+1.5VS

1 2

R36 1K_0402_5%@R36 1K_0402_5%@

1 2

R38 300_0402_5%R38 300_0402_5%

1 2

R40 300_0402_5%R40 300_0402_5%

@

1 2

R45 1K_0402_5%

@

1 2

R48 1K_0402_5%

@

1 2

R50 1K_0402_5%

4 4

A

ALLOW_STOP

APU_SIC

APU_SID

ALERT_L

ALLOW_STOP

APU_RST#

APU_PWRGD

APU_SVT

APU_SVC

APU_SVD

CPU TSI interface level shift

1 2

R32

+3VS

31.6K_0402_1%

APU_SID

BSH111 1N_SOT23-3

APU_SIC

BSH111 1N_SOT23-3

1 2

C5988 0.1U_0402_16V4ZC5988 0.1U_0402_16V4Z

1 2

R33

30K_0402_1%

G

2

Q3

13

D

S

D

S

G

2

Q4

13

D

S

D

S

B

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2_SUS <31>

EC_SMB_CK2_SUS <31>

+1.5V_APU

APU_TRST#

1 2

To EC

R42 10K_0402_5%R42 10K_0402_5%

1 2

R46 10K_0402_5%R46 10K_0402_5%

1 2

R49 10K_0402_5%R49 10K_0402_5%

To EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

@

D

2

4

6

8

10

12

14

16

18

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

APU_RST#

APU_DBRDY

APU_DBREQ#

R51 0_0402_5%@R51 0_0402_5%@

R52 0_0402_5%@R52 0_0402_5%@

12

Custom

Date: Sheet of

HDT Debug conn

APU_DBREQ# APU_TCK APU_TMS APU_TDI APU_TDO APU_TRST#

APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 APU_DBRDY

APU_TEST19

APU_TEST18

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FP2 Display/MISC/HDT

VAUS5 LA9001P M/B

1 2

R27 1K_0402_5%R27 1K_0402_5%

1 2

R29 1K_0402_5%R29 1K_0402_5%

1 2

R30 1K_0402_5%R30 1K_0402_5%

1 2

R34 1K_0402_5%R34 1K_0402_5%

1 2

R35 1K_0402_5%@R35 1K_0402_5%@

1 2

R37 1K_0402_5%R37 1K_0402_5%

1 2

R39 1K_0402_5%R39 1K_0402_5%

1 2

R41 1K_0402_5%R41 1K_0402_5%

1 2

R43 1K_0402_5%R43 1K_0402_5%

1 2

R44 1K_0402_5%R44 1K_0402_5%

1 2

R47 1K_0402_5%@R47 1K_0402_5%@

E

+1.5V_APU

7 50Tuesday, May 29, 2012

0.3

A

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDDR VDDR VDDR VDDR VDDR

V17 V19 V20 V22 W8 AA8 AA9 AA11 AA12 AA14 AA15 AA17 AA19 AA20 AA22 AD9 AD11 AD12 AD14 AD15 AD17 AD19 AD20 AD22 AG12 AG14 AG15 AG17 AG19 AG20 AG22

B11 B12 B13 B14 B15 C8 C10 C12 C14 D8 D10 D12 D14

M9 N9

W33 AA23 AA25 AA27 AA30 AA33 AB28 AC30 AC33 AD23 AD25 AD27 AE28 AE30 AE33 AG23 AG25 AG27 AG30 AG33

AN14 AP14 AP15 AR14 AR15

+APU_CORE

+APU_CORE_NB

+VDDNB_CAP

+1.5V_APU

+1.2VS

+APU_CORE

1 1

+APU_CORE_NB

2 2

+1.5V_APU

3 3

+1.2VS

+VDDP_CAP

+APU_VDDA

4 4

UCPU1E

J12

VDD

J14

VDD

J15

VDD

J17

VDD

J19

VDD

J20

VDD

J22

VDD

M11

VDD

M12

VDD

M14

VDD

M15

VDD

M17

VDD

M19

VDD

M20

VDD

M22

VDD

R8

VDD

R9

VDD

R11

VDD

R12

VDD

R14

VDD

R15

VDD

R17

VDD

R19

VDD

R20

VDD

R22

VDD

U8

VDD

V9

VDD

V11

VDD

V12

VDD

V14

VDD

V15

VDD

A7

VDDNB

A8

VDDNB

A9

VDDNB

A10

VDDNB

A11

VDDNB

A12

VDDNB

A13

VDDNB

A14

VDDNB

A15

VDDNB

B7

VDDNB

B8

VDDNB

B9

VDDNB

B10

VDDNB

J33

VDDIO

K23

VDDIO

K25

VDDIO

L28

VDDIO

L30

VDDIO

L33

VDDIO

M27

VDDIO

N23

VDDIO

N25

VDDIO

N30

VDDIO

N33

VDDIO

P28

VDDIO

R27

VDDIO

R30

VDDIO

R33

VDDIO

U28

VDDIO

U30

VDDIO

U33

VDDIO

W28

VDDIO

W30

VDDIO

AM12

VDDP

AN12

VDDP

AP12

VDDP

AP13

VDDP

AR12

VDDP

AR13

VDDP

AA6

VDDP_CAP

AA7

VDDP_CAP

AM13

VDDA

AM14

VDDA

TRINITY-A8-SERIES_BGA813

A8R3@

VDDNB_CAP VDDNB_CAP

B

+1.5V_APU

+1.2VS

C121 22U_0603_6.3V6MC121 22U_0603_6.3V6M

C122 22U_0603_6.3V6MC122 22U_0603_6.3V6M

1

2

Northbridge Power Pins for Remote Decoupling

+VDDP_CAP

close to APU

C

Decoupling betwe en CPU and DIMM s across VDDIO and VSS split

C69 0.22U_0402_10V4ZC69 0.22U_0402_10V4Z

C71 0.22U_0402_10V4ZC71 0.22U_0402_10V4Z

C64 4.7U_0603_6.3V6KC64 4.7U_0603_6.3V6K

C62 22U_0805_6.3V6MC62 22U_0805_6.3V6M

C63 22U_0805_6.3V6MC63 22U_0805_6.3V6M

1

2

C66 4.7U_0603_6.3V6KC66 4.7U_0603_6.3V6K

C65 4.7U_0603_6.3V6KC65 4.7U_0603_6.3V6K

C67 4.7U_0603_6.3V6KC67 4.7U_0603_6.3V6K

1

2

C68 0.22U_0402_10V4ZC68 0.22U_0402_10V4Z

1

2

C72 0.22U_0402_10V4ZC72 0.22U_0402_10V4Z

C70 0.22U_0402_10V4ZC70 0.22U_0402_10V4Z

1

2

C73 0.22U_0402_10V4ZC73 0.22U_0402_10V4Z

1

2

C77 0.22U_0402_10V4ZC77 0.22U_0402_10V4Z

C74 0.22U_0402_10V4ZC74 0.22U_0402_10V4Z

C75 0.22U_0402_10V4ZC75 0.22U_0402_10V4Z

C76 0.22U_0402_10V4ZC76 0.22U_0402_10V4Z

1

2

C81 180P_0402_50V8JC81 180P_0402_50V8J

C78 180P_0402_50V8JC78 180P_0402_50V8J

C79 180P_0402_50V8JC79 180P_0402_50V8J

C80 180P_0402_50V8JC80 180P_0402_50V8J

330U_B2_2.5VM_R15M

1

2

+1.5V

C82

1

+

@

2

C99 4.7U_0603_6.3V6KC99 4.7U_0603_6.3V6K

1

2

VDDR VDDP

C87 4.7U_0603_6.3V6KC87 4.7U_0603_6.3V6K

C85 0.01U_0402_16V7KC85 0.01U_0402_16V7K

C86 0.01U_0402_16V7KC86 0.01U_0402_16V7K

1

2

C124 22U_0603_6.3V6MC124 22U_0603_6.3V6M

C125 180P_0402_50V8JC125 180P_0402_50V8J

C123 22U_0603_6.3V6MC123 22U_0603_6.3V6M

1

2

C90 0.22U_0402_10V4ZC90 0.22U_0402_10V4Z

C89 0.22U_0402_10V4ZC89 0.22U_0402_10V4Z

C88 4.7U_0603_6.3V6KC88 4.7U_0603_6.3V6K

1

2

1

2

FBMA-L11-201209-221LMA30T_0805

L1

+2.5VS

C91 1000P_0402_50V7 KC91 1000P_0402_50V7 K

C94 180P_0402_50V8JC94 180P_0402_50V8J

C93 180P_0402_50V8JC93 180P_0402_50V8J

C92 1000P_0402_50V7 KC92 1000P_0402_50V7 K

1

2

12

C128 3300P_0402_50V7-KC128 3300P_0402_50V7-K

C127 0.22U_0402_10V4ZC127 0.22U_0402_10V4Z

C126 4.7U_0603_6.3V6KC126 4.7U_0603_6.3V6K

1

2

+APU_VDDA

C129 1000P_0402_50V7KC12 9 1 000P_0402_50V7K

1

2

+1.2VS

C113 0.22U_0402_10V4ZC113 0.22U_0402_10V4Z

C114 0.22U_0402_10V4ZC114 0.22U_0402_10V4Z

C115 1000P_0402_50V7KC11 5 1000P_04 02_50V7K

1

2

J5

@J5

@

+1.5V +1.5V_APU

1 2

PAD-OPEN 4x4m

Need Short

C130 22U_0603_6.3V6MC130 22U_0603_6.3V6M

C131 22U_0603_6.3V6MC131 22U_0603_6.3V6M

1

2

D

A17 A19 A21 A23 A25 A27 A29 A31

B1 C3 C4

C33

D5

D9 D11 D13

M23 M25

D15 D17 D19 D21 D23 D25 D30

E4 E27 E29 E30 E33

F5

F6

F7

F8

F17 F20 F23 F28 F29

G1 G2

G4 G15 G19 G25 G26 G27 G33

H8

H9 H22 H26

J4 J8

J9 J11 J23 J25 J26 J27 J30

K9 K11 K12 K14 K15 K17 K19 K20 K22

L1 L2 L4

M8

N4 N11 N12 N14 N15 N17 N19 N20 N22

R1

R2

R4

T9

T11 T12 T14 T15 T17 T19 T20 T22

U4

W1 W2 W4 W5 W6 W7

Y9

C100 4.7U_0603_6.3V6KC100 4.7U_0603_6.3V6K

C101 4.7U_0603_6.3V6KC101 4.7U_0603_6.3V6K

1

2

C116 1000P_0402_50V7KC11 6 1000P_04 02_50V7K

1

2

C104 0.22U_0402_10V4ZC104 0.22U_0402_10V4Z

C102 4.7U_0603_6.3V6KC102 4.7U_0603_6.3V6K

1

2

C117 180P_0402_50V8JC117 180P_0402_50V8J

C105 0.22U_0402_10V4ZC105 0.22U_0402_10V4Z

C103 0.22U_0402_10V4ZC103 0.22U_0402_10V4Z

1

2

C118 180P_0402_50V8JC118 180P_0402_50V8J

1

2

C108 180P_0402_50V8JC108 180P_0402_50V8J

C106 0.22U_0402_10V4ZC106 0.22U_0402_10V4Z

C107 180P_0402_50V8JC107 180P_0402_50V8J

1

2

1

2

E

UCPU1F

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TRINITY-A8-SERIES_BGA813

A8R3@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Y11 Y12 Y14 Y15 Y17 Y19 Y20 Y22 AA4 AA5 AB7 AB8 AC1 AC2 AC4 AC9 AC11 AC12 AC14 AC15 AC17 AC19 AC20 AC22 AC23 AC25 AE4 AF9 AF11 AF12 AF14 AF15 AF17 AF19 AF20 AF22 AF23 AF25 AG1 AG2 AG4 AG9 AG11 AG26 AH7 AH17 AH20 AH23 AH26 AH30 AJ4 AJ5 AJ6 AJ7 AJ9 AJ14 AJ15 AJ19 AJ22 AJ27 AJ28 AJ33 AK6 AK8 AK25 AK28 AK30 AL1 AL2 AL4 AL8 AL11 AL27 AL28 AL33 AM5 AM7 AM9 AM11 AM15 AM17 AM19 AM21 AM23 AM25 AM29 AM30 AN3 AN4 AN33 AP5 AP9 AR2 AR5 AR9 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

FP2 PW R / GND

VAUS5 LA9001P M/B

E

of

8 50Tuesday, May 29, 2012

0.3

A

B

C

D

E

+VREF_DQ

DDRA_SDQ0 DDRA_SDQ1

DDRA_SDM0

DDRA_SDQ2

1 1

DDRA_SDQS1#<6> DDRA_SDQS1<6>

DDRA_SDQS2#<6> DDRA_SDQS2<6>

DDRA_CKE0<6>

C145

DDRA_SDQS4#<6> DDRA_SDQS4<6>

DDRA_SDQS6#<6> DDRA_SDQS6<6>

DDRA_SBS2#<6>

DDRA_CLK0<6> DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6>

DDRA_SCS1#<6>

1

2

1

C146

0.1U_0402_16V4Z

2

A

2 2

3 3

+3VS

4 4

2.2U_0603_6.3V6K

DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

1 2

R57 10K_0402_5%R57 10K_0402_5%

+1.5V +1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

12

R58

R58 10K_0402_5%

10K_0402_5%

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

Reverse Type H:4mm

<Address: 00>

DQS0#

DQS0

DQ12 DQ13

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

GND2

BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

A15 A14

A11

CK1

BA1

S0#

SCL VTT

2 4

DDRA_SDQ4

6

DDRA_SDQ5

8 10

DDRA_SDQS0#

12

DDRA_SDQS0

14 16

DDRA_SDQ6

18

DDRA_SDQ7

20 22

DDRA_SDQ12

24

DDRA_SDQ13

26 28

DDRA_SDM1

30

MEM_MA_RST#

32 34

DDRA_SDQ14

36

DDRA_SDQ15

38 40

DDRA_SDQ20

42

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23DDRA_SDQ18

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

DDRA_SMA15

80

DDRA_SMA14

82 84

DDRA_SMA11

86

A7

A6 A4

A2 A0

NC

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94 96

DDRA_SMA2

98

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116

DDRA_ODT0

118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

+0.75VS

206 208

B

DDRA_SDQS0# <6> DDRA_SDQS0 <6>

MEM_MA_RST# <6>

DDRA_SDQS3# <6> DDRA_SDQS3 <6>

DDRA_CKE1 <6>

DDRA_CLK1 <6> DDRA_CLK1# <6>

DDRA_SBS1# <6> DDRA_SRAS# <6>

DDRA_SCS0# <6> DDRA_ODT0 < 6>

DDRA_ODT1 < 6>

+VREF_CA

DDRA_SDQS5# <6> DDRA_SDQS5 <6>

DDRA_SDQS7# <6> DDRA_SDQS7 <6>

MEM_MA_EVENT# <6>

FCH_SDATA0 <12,25> FCH_SCLK0 <12,25>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

DDRA_SMA[0..15]

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

0.1U_0402_16V4Z

2012/01/15 2013/01/15

DDRA_SDQ[0..63] <6>

DDRA_SDM[0..7] <6>

DDRA_SMA[0..15] <6>

Place near DIMM1

0.1U_0402_16V4Z

2

C132

C133

1

+VREF_DQ +VREF_CA

1

C138

2

0.1U_0402_16V4Z

2

C142

1

Compal Secret Data

2

C134

1

0.1U_0402_16V4Z

1

C139

2

1000P_0402_50V7K

1

2

Deciphered Date

0.1U_0402_16V4Z

2

C135

1

0.1U_0402_16V4Z

+1.5V

R53

R53 1K_0402_1%

1K_0402_1%

1 2

R55

R55 1K_0402_1%

1K_0402_1%

1 2

C143

4.7U_0603_6.3V6K

2

C136

1

D

0.1U_0402_16V4Z

2

C137

1

+VREF_CA

15mil15mil

1

C140

2

0.1U_0402_16V4Z

SGA00001700

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.5V

R54

R54 1K_0402_1%

1K_0402_1%

1 2

1

C141

R56

R56 1K_0402_1%

2

1000P_0402_50V7K

+1.5V+0.75VS

1

+

2

1K_0402_1%

1 2

C243

220U_B2_2.5VM_R35+C243

220U_B2_2.5VM_R35

Compal Electronics, Inc.

DDRIII SO-DIMM 1

VAUS5 LA9001P M/B

0.3

9 50Friday, May 25, 2012

E

0.3

A

R59/ C147 close to FCH

1 2

C147

X1

C147

PLT_RST#

C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K

+1.1VS_CKVDD

APU

R67 0_0402_5%R67 0_0402_5% R68 0_0402_5%R68 0_0402_5%

R69 0_0402_5%R69 0_0402_5% R70 0_0402_5%R70 0_0402_5%

R72 0_0402_5%R72 0_0402_5% R74 0_0402_5%R74 0_0402_5%

4

1

NC

OSC

OSC3NC

2

A

1 2

R59 33_0402_5%R59 33_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

R61 590_0402_1%R61 590_0402_1%

1 2

R63 2K_0402_1%R63 2K_0402_1%

1 2

R66 2K_04 02_1%R66 2K_0402_1%

APU_DISP_CLK<7> APU_DISP_CLK#<7>

1 2 1 2

@

1 2

R77 22_0402_5%

25M_X1

R80

R80 1M_0402_5%

1M_0402_5%

25M_X2

150P_0402_50V8J

UMI_RXP0<5> UMI_RXN0<5> UMI_RXP1<5> UMI_RXN1<5> UMI_RXP2<5> UMI_RXN2<5> UMI_RXP3<5>

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

CLK_PCIE_WLAN<25> CLK_PCIE_WLAN#<25>

CLK_PCIE_LAN<26> CLK_PCIE_LAN#<26>

CLK_LAN_25M<26>

C160

1 2

10P_0402_50V8J

C162

1 2

10P_0402_50V8J

UMI_RXN3<5>

UMI_TXP0<5> UMI_TXN0<5> UMI_TXP1<5> UMI_TXN1<5> UMI_TXP2<5> UMI_TXN2<5> UMI_TXP3<5> UMI_TXN3<5>

+VDDAN_11_PCIE

1 1

2 2

VGA

WLAN

LAN

3 3

LAN

4 4

25MHZ_10PF_X3G025000DC1H

APU_CLK<7>

APU_CLK#<7>

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

APU_PCIE_RST#_C

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

CLK_CALRN

CLK_LAN_25M_R

25M_X1

25M_X2

B

U2A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

B

HUDSON-2

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

C

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28

APU_PROCHOT#_R

E26

APU_PWRGD_R

G26 F26

H7 F1 F3 E6

+RTCBATT_R

G2

32K_X1

G4

32K_X2

GPIO31

T11T11

T12T12

PCI_CLK1 <14>

PCI_CLK3 <14> PCI_CLK4 <14>

@

R218

10K_0402_5%

@

R217

10K_0402_5%

1 2 1 2

1U_0402_6.3V6K

APU_PCIE_RST#_C

BT_OFF# <25>

W=20mils

1

C159

2

+3VS

12

PCI_AD23 <14> PCI_AD24 <14> PCI_AD25 <14> PCI_AD26 <14> PCI_AD27 <14>

R71 22_0402_5%R 71 22_0402_5% R73 0_0402_5%@R73 0_0402_5%@

LPC_CLK1 <14> LPC_AD0 <25,31> LPC_AD1 <25,31> LPC_AD2 <25,31> LPC_AD3 <25,31> LPC_FRAME# <25,31>

SERIRQ <31>

R75 0_0402_5%@R75 0_0402_5%@ R76 0_0402_5%R76 0_0402_5%

APU_RST# <7>

RTC_CLK <14,31>

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

APU_PCIE_RST #: Reset PCIE device on APU

+3VS

12

D

MC74VHC1G08DFT2G SC70 5P

R60

1 2

33_0402_5%

@

C157

@

UMA@

R146

R146 10K_0402_5%

10K_0402_5%

BOARD Config.

PX@

R152

R152 10K_0402_5%

10K_0402_5%

CLK_PCI_EC <14,31> CLK_PCI_DB <25>

ALLOW_STOP <7> APU_PROCHOT# <7> APU_PWRGD <43,7>

1 2

R78 510_0402_5%R78 510_0402_5%

Need OPEN

1

2

150P_0402_50V8J

GPIO31

+RTCBATT

12

R64

@

1 2

8.2K_0402_5%

0

1

CLRP1

@CLRP1

@

SHORT PADS

2

1

1 2

@ R65

@

0_0402_5%

Function

for Clear CMOS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/15 2013/01/15

C

Compal Secret Data

Deciphered Date

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

E

+3VALW

C156

@C156

@

1 2

0.1U_0402_16V4Z

5

P

B

4

Y

A

G

U1

3

@

R65

APU_PCIE_RST# < 15,25>

VGA,LAN,WLAN,Cardreader

12

R62

R62 0_0402_5%

0_0402_5%

PLT_RST# <26,31>

EC

PX5

UMA

18P_0402_50V8J

32K_X1

32.768KHZ_12.5PF_CM31532768DZFT

32K_X2

12

Y1

Close to HUDSON-M3

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RT C

VAUS5 LA9001P M/B

1 2

C158

12

R79

20M_0402_5%

1 2

C161

18P_0402_50V8J

of

10 50Friday, May 25, 2012

E

0.3

A

U2B

SATA_FTX_C_DRX_P0<25>

SSD

1 1

2 2

3 3

4 4

HDD

+AVDD_SATA

SATA_FTX_C_DRX_N0<25>

SATA_FRX_C_DTX_N0<25> SATA_FRX_C_DTX_P0<25>

SATA_FTX_C_DRX_P1<29> SATA_FTX_C_DRX_N1<29>

SATA_FRX_C_DTX_N1<29> SATA_FRX_C_DTX_P1<29>

1 2

R94 1K_0402_1%R 94 1K_0402_1%

1 2

R95 931_0402_1%R95 931_0402_1%

1 2

R97 10K_0402_5%R97 10K_0402_5%

+3VS

BT_DISABLE#<25>

WL_OFF#<25>

SATA_CALRP

SATA_CALRN

BT_DISABLE# WL_OFF#

1 2

R214 10K_0402_5%R214 10K_0402_5%

1 2

R105 10K_0402_5%R105 10K_0402_5%

1 2

R108 10K_0402_5%R108 10K_0402_5%

1 2

R109 10K_0402_5%R109 10K_0402_5%

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

T13T13

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

B

HUDSON-2

SERIAL ATA

HW MONITOR

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD/GPIO75

SD_WP/GPIO76

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_PHY_PD

VGA_RED

VGA_GREEN

VGA_BLUE

AUXCAL

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

VIN0/GPIO175

VIN1/GPIO176

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

GBE_PHY_INTR

V6

SPI_SO

V5

SPI_SI

V3

SPI_CLK_FCH

T6

SPI_SB_CS0#

V1

SPI_WP#

L30

L32

M29

M28 N30

M33 N32

K31

R96 715_0402_1%@R96 715_0402_1%@

V28 V29

U28

AUXCAL

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

R99 10K_0402_5%R99 10K_ 0402_5%

M3

R100 10K_0402_5%R100 10K_0402_5%

L2

R101 10K_0402_5%

N4

R102 10K_0402_5%

P1

R103 10K_0402_5%

P3

R104 10K_0402_5%

M1

R106 10K_0402_5%

M5

R107 10K_0402_5%R107 10K_0402_5%

AG16 AH10 A28 G27 L4

C

1 2

R93 10K_0402_5%R93 10K_0402_5%

1 2

R98 100_0402_1%

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

Need to enable i nternal pull down to lea ve unconnected

+3VALW

+VDDAN_11_ML

D

+3VALW

1 2

R92

@R92

@

1 2

R81

@R81

@

1 2

R83

SPI_SB_CS0# SPI_SO SPI_WP#

Mount R92, R81 if support FCH share ROM

Place them close to ball within 1"

4MB SPI ROM

SPI_SB_CS0#

10K_0402_5%

SPI_WP#

10K_0402_5%

SPI_HOLD#

10K_0402_5%

U3

1

CS#

2

SO/SIO1

3

WP#

4

GND

W25Q32BVSSIG SOIC 8P SPI ROM

VCC

HOLD#

SCLK

SI/SIO0

8 7 6 5

+3VALW

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_FCH SPI_SI

C164

1 2

E

22P_0402_50V8J

SPI_CLK_FCH

R82

33_0402_5%

@

C163

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

VAUS5 LA9001P M/B

11 50Friday, May 25, 2012

E

0.3

A

+3VALW

R110

R110 10K_0402_5%

10K_0402_5%

@

1 2

SYS_RESET#

1 1

2 2

3 3

4 4

+3VALW

For FCH internal debug use

1 2

R114 2.2K_0402_5%@R114 2.2K_0402_5%@

1 2

R115 2.2K_0402_5%@R115 2.2K_0402_5%@

1 2

R116 2.2K_0402_5%@R116 2.2K_0402_5%@

+3VALW

1 2

R119 10K_0402_5%R119 10K_0402_5%

1 2

R121 10K_0402_5%R121 10K_0402_5%

1 2

R122 10K_0402_5%@R122 10K_0402_5%@

1 2

R123 10K_0402_5%@R123 10K_0402_5%@

1 2

R124 10K_0402_5%@R124 10K_0402_5%@

1 2

R127 10K_0402_5%@R127 10K_0402_5%@

1 2

R128 10K_0402_5%@R128 10K_0402_5%@

1 2

R130 10K_0402_5%@R130 10K_0402_5%@

1 2

R132 10K_0402_5%@R132 10K_0402_5%@

1 2

R133 100K_0402_5%@R133 100K_0402_5%@

1 2

R134 10K_0402_5%@R134 10K_0402_5%@

1 2

R148 2.2K_0402_5%R148 2.2K_0402_5%

1 2

R149 2.2K_0402_5%R149 2.2K_0402_5%

+3VS

1 2

R141 2.2K_0402_5%R141 2.2K_0402_5%

1 2

R142 2.2K_0402_5%R142 2.2K_0402_5%

1 2

R143 10K_0402_5%R143 10K_0402_5%

1 2

R144 8.2K_0402_5%R144 8.2K_0402_5%

1 2

R145 8.2K_0402_5%R145 8.2K_0402_5%

1 2

R150 2.2K_0402_5%R150 2.2K_0402_5%

1 2

R151 10K_0402_5%@R151 10K_0402_5%@

1 2

R154 10K_0402_5%@R154 10K_0402_5%@

1 2

R155 10K_0402_5%R155 10K_0402_5%

change back to always mount

FCH Chip FCH_SEL

A

60M2

Low

TEST0

TEST1

TEST2

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB_OC5#

USB_OC4#

USB_OC6#

USB_OC7#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SCLK1

FCH_SDATA1

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

PEG_CLKREQ#_R

VGA_GATE#<31>

DDR3L_EN#<40>

PXS_RST#<15> PXS_PWREN<17,39,42>

PEG_CLKREQ#<16>

HDA_BITCLK_AUDIO<30> HDA_SDOUT_AUDIO<30>

HDA_SDIN0<30>

HDA_SYNC_AUDIO<30>

HDA_RST_AUDIO#<30>

13

D

2

G

S

AMD only support FP2 + A70M3, @ FCH_SEL function

A70M3 High

Before setting (for reference)

A

B

PCIE_RST2 : Reset PCIE device on Hudson2/3

EC_LID_OUT#<31>

PM_SLP_S3#<31> PM_SLP_S5#<31> PBTN_OUT#<31> FCH_PWRGD<31,43>

GATEA20<31>

KBRST#<31> EC_SCI#< 31> EC_SMI#<31>

FCH_PCIE_WAKE#<25,26>

H_THERMTRIP#<7>

EC_RSMRST#<31>

LAN_CLKREQ#<26>

FCH_SPKR<30> FCH_SCLK0<25,9> FCH_SDATA0<25,9> FCH_SCLK1<32> FCH_SDATA1<32>

WLAN_CLKREQ#<25>

VGA_PWRGD<15,42>

R117 0_0402_5%@R117 0_0402_5%@

12

change back to @

USB_OC1#<32> USB_OC0#<33>

1 2

R125 33_0402_5%R 125 33_0402_5%

1 2

R126 33_0402_5%R 126 33_0402_5%

1 2

R129 33_0402_5%R 129 33_0402_5%

1 2

R131 33_0402_5%R 131 33_0402_5%

PX@

12

R1360_0402_5%

12

R1380_0402_5%

PX@

Q6

2N7002K_SOT23-3

R112

10K_0402_5%

R113

10K_0402_5%

B

+3VALW

@

12

FCH_SEL

12

T14T14

FCH_PWRGD

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1

PEG_CLKREQ#_R

USB_OC7# USB_OC6# USB_OC5# USB_OC4# USB_OC3# USB_OC2# USB_OC1# USB_OC0#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

T15T15 T16T16

12

R1530_0402_5% R1530_0402_5%

12

R1470_0402_5% @ R1470_0402_5% @

C

U2D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT1 2#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/01/15 2013/01/15

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

USB_RCOMP

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12

USB30_P10

K13

USB30_N10

B11 D11

E10 F10

C10

USB20_P7

A10

USB20_N7

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

J16

USB30_TX_P0

H16

USB30_TX_N0

J15

USB30_RX_P0

K15

USB30_RX_N0

H19

1 2

R135 10K_0402_5%R135 10K_0402_5%

G19

1 2

R137 10K_0402_5%R137 10K_0402_5%

G22

1 2

R139 10K_0402_5%R139 10K_0402_5%

G21

1 2

R140 10K_0402_5%R140 10K_0402_5%

E22 H22 J22

EC_PWM2

H21

K21

FCH_SEL

K22 F22 F24 E24 B23

Left USB port 3.0 & 2.0 co-lay

C24 F18

USB20_N7

USB20_P7

USB30_N10

USB30_P10

D

E

1 2

R111 11.8K_0402_1%R111 11.8K_0402_1%

Hudson-M3 OHCI(DEV-20,FUN-5)

Hudson-M3

USB30-Left1

USB20-Left1

USB20_P5 <32> USB20_N5 <32>

USB20_P3 <23> USB20_N3 <23>

USB20_P2 <25> USB20_N2 <25>

USB20_P1 <32> USB20_N1 <32>

USB20_P0 <32> USB20_N0 <32>

1 2

R118 1K_0402_1%R118 1K_0402_1%

1 2

R120 1K_0402_1%R120 1K_0402_1%

USB30_TX_P0 <33> USB30_TX_N0 <33>

USB30_RX_P0 <33> USB30_RX_N0 <33>

@

R1606 0_0402_5%

@

R1607 0_0402_5%

R1610 0_0402_5%R1610 0_0402_5%

R1611 0_0402_5%R1611 0_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

Card Reader

Int. Camera

WLAN

USB20-Right2

USB20-Right1

USB30-Left1

USB3.0 and USB2.0 Option

EC_PWM2 <14>

12

strap pin

USB20_LN

USB20_LP

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

VAUS5 LA9001P M/B

XHCI(DEV-16,FUN-0) XHCI(DEV-16,FUN-1)

Hudson-M3 OHCI(DEV-19,FUN-0) EHCI(DEV-19,FUN-2)

Hudson-M3 OHCI(DEV-18,FUN-0) EHCI(DEV-18,FUN-2)

+FCH_VDD_11_SSUSB_S

Hudson-M3 XHCI(DEV-16,FUN-0) XHCI(DEV-16,FUN-1)

USB20_LN <33>

USB20_LP <33>

E

0.3

12 50Friday, May 25, 2012

0.3

A

B

C

D

E

+3VS

1 1

+FCH_VDDAN_33_DAC

+3VS +FCH_VDDAN_33_DAC

FBMA-L11-201209-221LMA30T_0805

2 2

+3VALW

+VDDAN_33_USB

3 3

+3VS

4 4

L2

1 2

MBK1608221YZF_2P

220 ohm

1 2

R158 0_0402_5%@R158 0_0402_5%@

L4

1 2

220 ohm

L6

1 2

MBK1608221YZF_2P

220 ohm

L91

1 2

MBK1608221YZF_2P

220 ohm

L12

1 2

MBK1608221YZF_2P

220 ohm

L13

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SYS

C165

1

2

+VDDPL_33_MLDAC

C175

1

2

30mA

C194

2.2U_0603_6.3V6K

C194

2.2U_0603_6.3V6K

1

2

+VDDPL_33_SSUSB_S

C204

2.2U_0402_6.3V6M

C204

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C211

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

A

C166

0.1U_0402_16V7K

C166

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

0.1U_0402_16V7K

C176

1

2

LDO_CAP: Internally generated 1.8V

upply for the RGB outputs

s

+1.1VS

C195

0.1U_0402_16V4Z

C195

0.1U_0402_16V4Z

1

2

+3VALW

C205

0.1U_0402_16V7K

C205

0.1U_0402_16V7K

1

2

C212

0.1U_0402_16V7K

C212

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

C218

2.2U_0402_6.3V6M

C218

2.2U_0402_6.3V6M

1

2

C225

2.2U_0402_6.3V6M

C225

2.2U_0402_6.3V6M

1

2

+1.1VALW

1 2

R157 0_0603_5%@R157 0_0603_5%@

+3VS

L5

R160 0_0402_5%@R160 0_0402_5%@

R161 0_0402_5%@R161 0_0402_5%@

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

R163 0_0402_5%@R163 0_0402_5%@

R164 0_0603_5%@R164 0_0603_5%@

+VDDPL_33_MLDAC

L3

1 2

MBK1608221YZF_2P

220 ohm/2A

1 2

FBMA-L11-201209-221LMA30T_0805

220 ohm/2A

AMD strong recommended

L81

1 2

MBK1608221YZF_2P

220 ohm

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L101

1 2

MBK1608221YZF_2P

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

L141

12

42 ohm/4A

R170 0_0603_5%@R170 0_0603_5%@

R172 0_0603_5%@R172 0_0603_5%@

1 2

C199

1

2

C207

1

2

C213

1

2

1 2

B

22U_0603_6.3V6M

C172

C171

1

2

+VDDPL_33_SYS

C187

1

2

R167 0_0402_5%@R167 0_0402_5%@

10U_0603_6.3V6M

C200

1

2

C208

0.1U_0402_16V7K

C208

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

C214

0.1U_0402_16V7K

C214

0.1U_0402_16V7K

10U_0603_6.3V6M

1

2

C219

1

2

C226

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

+FCH_VDDAN_33_DAC

+VDDPL_33_SSUSB_S

C183 2.2U_0603_6.3V6K

4.7U_0402_6.3V6M

C188

+VDDAN_33_USB

C201

1

2

+VDDAN_11_USB_S+VDDAN_11_USB_S

C244

1

2

+VDDCR_11V_USB

C215

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

+VDDCR_11_SSUSB

10U_0603_6.3V6M

0.1U_0402_16V7K

C173

1

2

+VDDPL_33_SYS

+VDDPL_33_DAC

+VDDPL_33_ML

@

1 2

C189

0.1U_0402_16V7K

1

2

1U_0402_6.3V6K

C202

0.1U_0402_16V7K

C220

1

2

C227

1

2

0.1U_0402_16V7K

C174

1

2

+VDDPL_11_DAC

+VDDAN_11_ML

0.1U_0402_16V7K

1

2

12

C203

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

C221

0.1U_0402_16V7K

C221

0.1U_0402_16V7K

1

2

C228

1U_0402_6.3V6K

1

2

U2C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

1

2mA

U22

VDDPL_33_ML

3

0mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21807-A13-HUDSON-M3_FCBGA656

0.1U_0402_16V7K

C229

0.1U_0402_16V7K

C229

0.1U_0402_16V7K

A70MR1@

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2012/01/15 2013/01/15

1007mA

C177

T14 T17

1

T20 U16 U18

2

V14 V17 V20 Y17

40mA

3

H26 J25

C178

K24 L22

1

M22 N21 N22

2

P22

1088mA

AB24 Y21 AE25

C184

AD24 AB23

1

AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C190

AB22 AC22

1

AC21 AA20 AA18

2

AB20 AC19

59mA

N18 L19

C196

M18 V12

1

V13 Y12 Y13

2

W11

5mA

G24

C206

1

2

187mA

N20 M20

C209

1

2

70mA

J24

C216

1

2

12mA

M8

C222

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

1

2

+1.1VS_CKVDD

C179

0.1U_0402_16V7K

C179

0.1U_0402_16V7K

1

2

+VDDAN_11_PCIE

C185

1U_0402_6.3V6K

C185

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

C191

1U_0402_6.3V6K

C191

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

+VDDIO_33_S

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

1

2

+VDDXL_3.3V

2.2U_0402_6.3V6M

+VDDCR_1.1V

C210

1U_0402_6.3V6K

C210

1U_0402_6.3V6K

1

2

+VDDPL_11_SYS_S

0.1U_0402_16V7K

C217

2.2U_0402_6.3V6M

1

2

+VDDAN_33_HWM

C223

0.1U_0402_16V7K@C223

0.1U_0402_16V7K

2.2U_0402_6.3V6M@C222

2.2U_0402_6.3V6M

1

@

2

+VDDIO_AZ

C168

1U_0402_6.3V6K

C168

1U_0402_6.3V6K

C169

1

2

C180

1U_0402_6.3V6K

C180

1U_0402_6.3V6K

C181

1

2

+VDDAN_11_PCIE

C186

22U_0603_6.3V6M

C186

22U_0603_6.3V6M

1

2

C192

1U_0402_6.3V6K

C192

1U_0402_6.3V6K

C193

1

2

C198

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

1

2

1 2

C224 2.2U_040 2_6.3V6MC 224 2.2U_0402_6.3V6M

D

C170

1U_0402_6.3V6K

1

2

+1.1VS_CKVDD

C182

1U_0402_6.3V6K

1

2

+AVDD_SATA

22U_0603_6.3V6M

1

2

R166 0_0402_5%@R166 0_0402_5%@

R168 0_0603_5%@R168 0_0603_5%@

R169 0_0402_5%@R169 0_0402_5%@

R171 0_0402_5%@R171 0_0402_5%@

1 2

R156 0_0805_5%R156 0_0805_5%

10U_0603_6.3V6M

42ohm @ 100MHz

1 2

R159 0_0603_5%@R159 0_0603_5%@

22U_0603_6.3V6M

42ohm @ 100MHz

1 2

R162 0_0805_5%@R162 0_0805_5%@

42ohm @ 100MHz

1 2

R165 0_0805_5%@R165 0_0805_5%@

1 2

L7

1 2

MBK1608221YZF_2P

220 ohm

1 2

L111

1 2

MBK1608221YZF_2P

220 ohm

1 2

+1.1VS

+3VALW

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wa ke is supported; ot herwise, tie to +3.3V_S0 rail. Hudson-2 designs : Tie to +3.3V_ S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

FCH PWR

VAUS5 LA9001P M/B

13 50Friday, May 25, 2012

E

of

0.3

A

B

C

D

E

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

U2E

1 1

2 2

3 3

U2E

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

M13 M16 M21 M25

N11 N13 N23 N24

R11 R25 R28

H25

A3

A33

B7

B13

D9

D13

E5 E12 E16 E29

F7

F9 F11 F13 F16 F17 F19 F23 F25 F29

G6 G16 G32 H12 H15 H29

J6

J9

J10 J13 J28 J32

K7 K16 K27 K28

L6 L12 L13 L15 L16 L21

N6

P12 P18 P20 P21 P31 P33

R4

T11 T16 T18

N8

K25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<10>

PCI_CLK3<10>

PCI_CLK4<10>

CLK_PCI_EC<10,31>

LPC_CLK1<10 >

EC_PWM2<12>

RTC_CLK<10,31>

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

USE PCI

PULL

PLL

HIGH

DEFAULT

BYPASS

PULL

PCI PLL

LOW

PCI_AD27<10>

PCI_AD26<10>

PCI_AD25<10>

PCI_AD24<10>

PCI_AD23<10>

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

12

@

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R180 2.2K_0402_5%@R180 2.2K_0402_5%

12

@

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R173 10K_0402_5%R173 10K_0402_5%

R174 10K_0402_5%@R174 10K_0402_5%

R175 10K_0402_5%@R175 10K_0402_5%

12

@

R186 10K_0402_5%R186 10K_0402_5%

R185 10K_0402_5%@R185 10K_0402_5%

R187 10K_0402_5%R187 10K_0402_5%

12

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

R182 2.2K_0402_5%@R182 2.2K_0402_5%

R181 2.2K_0402_5%@R181 2.2K_0402_5%

12

@

EC ENABLED

EC DISABLED

DEFAULT

R176 10K_0402_5%@R176 10K_0402_5%

12

@

R188 10K_0402_5%R188 10K_0402_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

R183 2.2K_0402_5%@R183 2.2K_0402_5%

12

@

12

@

R184 2.2K_0402_5%@R184 2.2K_0402_5%

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

R177 10K_0402_5%R177 10K_0402_5%

R189 10K_0402_5%@R189 10K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

+3VALW+3VALW+3VALW+ 3VALW+3V S+3VS+3VS

R179 10K_0402_5%R179 10K_0402_5%

R178 10K_0402_5%@R178 10K_0402_5%

12

@

R191 2.2K_0402_5%@R191 2.2K_0402_5%

R190 2.2K_0402_5%R190 2.2K_0402_5%

12

@

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

VAUS5 LA9001P M/B

14 50Friday, May 25, 2012

E

0.3

A

B

C

D

E

PCIE_CTX_GRX_P[7..0]<5>

PCIE_CTX_GRX_N[7..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<10> CLK_PCIE_VGA#<10>

VGA_PWRGD<12,42>

PCIE_CTX_GRX_P[7..0]

PCIE_CTX_GRX_N[7..0]

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 0_0402_5%

@

12

R299

PX@R299

PX@

10K_0402_5%

GPU_RST#

12

PX@

R399

R399 100K_0402_5%

100K_0402_5%

U8A

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

12

N10

PWRGOOD

AL27

PERSTB

216-0774207-A11ROB_FCBGA631

SXTR1@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

AH30

PCIE_CRX_C_GTX_P0

AG31

PCIE_CRX_C_GTX_N0

AG29

PCIE_CRX_C_GTX_P1

AF28

PCIE_CRX_C_GTX_N1 PC IE_CRX_GTX_N1

AF27

PCIE_CRX_C_GTX_P2

AF26

PCIE_CRX_C_GTX_N2

AD27

PCIE_CRX_C_GTX_P3

AD26

PCIE_CRX_C_GTX_N3 PC IE_CRX_GTX_N3

AC25

PCIE_CRX_C_GTX_P4

AB25

PCIE_CRX_C_GTX_N4 PC IE_CRX_GTX_N4

Y23

PCIE_CRX_C_GTX_P5

Y24

PCIE_CRX_C_GTX_N5 PC IE_CRX_GTX_N5

AB27

PCIE_CRX_C_GTX_P6

AB26

PCIE_CRX_C_GTX_N6

Y27

PCIE_CRX_C_GTX_P7

Y26

PCIE_CRX_C_GTX_N7 PC IE_CRX_GTX_N7

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

PX@

Y22

AA22

PX@

1 2

PCIE_CRX_GTX_P[7..0] <5>

PCIE_CRX_GTX_N[7..0] <5>

R2981.27K_0402_1%

R3002K_0 402_1% PX@ R3002K_0402_1% PX@

+1.0VGS

12

C2580.1U_0402_16V7K PX@C 2580.1U_0402_16V7K PX@

12

C2590.1U_0402_16V7K PX@C 2590.1U_0402_16V7K PX@

12

C2770.1U_0402_16V7K

12

C2760.1U_0402_16V7K PX@C 2760.1U_0402_16V7K PX@

12

C2560.1U_0402_16V7K

12

C2570.1U_0402_16V7K PX@C 2570.1U_0402_16V7K PX@

12

C2750.1U_0402_16V7K

12

C2740.1U_0402_16V7K PX@C 2740.1U_0402_16V7K PX@

12

C2550.1U_0402_16V7K

12

C2540.1U_0402_16V7K PX@C 2540.1U_0402_16V7K PX@

12

C2730.1U_0402_16V7K

12

C2720.1U_0402_16V7K PX@C 2720.1U_0402_16V7K PX@

12

C2530.1U_0402_16V7K

12

C2520.1U_0402_16V7K PX@C 2520.1U_0402_16V7K PX@

12

C2710.1U_0402_16V7K

12

C2700.1U_0402_16V7K PX@C 2700.1U_0402_16V7K PX@

PX@

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7

U8F

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

216-0774207-A11ROB_FCBGA631

SXTR1@

VARY_BL

DIGON

TXOUT_U3P

TXOUT_L3P TXOUT_L3N

AB11 AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

LVDS

R395 0_0402_5%@R395 0_0402_5%@

PXS_RST#<12>

APU_PCIE_RST#<10,25>

2

1

12

+3VGS

5

U16

P

B

4

Y

A

G

PX@

3

MC74VHC1G08DFT2G SC70 5P

GPU_RST#

PCIE LANE

4 4

U8

SXTR3@U8

SXTR3@

S IC 216-0809024 A11 SEYMOUR XT S3 C38!

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

SeymourXT-S3 PCIE/LVDS

VAUS5 LA9001P M/B

15 50Friday, May 25, 2012

E

0.3

A

+1.8VGS

L8

BLM15BD121SN1D_0402

1 1

2 2

+3VGS

3 3

4 4

XTALIN

1

2

BLM15BD121SN1D_0402

+1.0VGS

BLM15BD121SN1D_0402

1 2

R321 10K_0402_5%PX@ R321 10K_0402_5%PX@

1 2

R322 10K_0402_5%PX@ R322 10K_0402_5%PX@

1 2

R323 10K_0402_5%PX@ R323 10K_0402_5%PX@

1 2

R324 10K_0402_5%PX@ R324 10K_0402_5%PX@

+1.8VGS +DPLL_PVDD

BLM15BD121SN1D_0402

+1.8VGS

BLM18AG121SN1D_0603

Had confirm with I+A & A+A FAE & check list is to use 1M

R337 1M_0402_5%PX@R337 1M_0402_5%PX@

Y6

4

NC

1

OSC

27MHZ 10PF 20PPM X3G027000DA1H

PX@

C341

8.2P_0402_50V8D

12

PX@

L14

PX@

L49

PX@

OSC

NC

L9

PX@

12

L17

3

2

1

C304

@

2

12

1

C307

@

2

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS

GPIO26_TCK

1

C323

PX@

2

10U_0603_6.3V6M

12

1

C330

PX@

2

12

1

C334

PX@

2

XTALOUT

10U_0603_6.3V6M

PX@

10U_0603_6.3V6M

+DPC_VDD18

1

C305

@

2

+DPC_VDD10

1

C346

@

2

+DPLL_PVDD

1

C324

2

1U_0402_6.3V4Z

+DPLL_VDDC

1

C331

PX@

2

+TSVDD

1

C335

2

1

PX@

C350

8.2P_0402_50V8D

2

+DPC_VDD18

1

C306

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+DPC_VDD10

1

C347

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

CH751H-40PT_SOD323-2 @

ACIN<31,37>

+3VGS

12

R331

10K_0402_5%

@

PEG_CLKREQ#<12>

1

C325

PX@

2

0.1U_0402_10V6K

+DPLL_VDDC+1.0VGS

1

C332

PX@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+TSVDD

1

C336

PX@

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

change Y6 follow QAWYA (SJ10000FH00)

A

GPU_VID0<42>

GPU_VID1<42>

+1.8VGS

PX@

R329 499_0402_1%

R332 249_0402_1%

C322 0.1U_0402_10V6K

PX@

+3VGS

+TSVDD

B

VRAM_ID2<20> VRAM_ID1<20> VRAM_ID0<20>

+DPC_VDD18

+DPC_VDD10

D4

21

R319 10K_0402_5%

T64T64

1 2

R326

5.11K_0402_1%PX@

1 2

R613

4.7K_0402_5%

@

12

PX@

12

+DPLL_PVDD

+DPLL_VDDC

PX@

R335 0_0402_5%

R333 0_0402_5%

PX@

1 2

R334 2.61K_0402_5%

+TSVDD

B

VRAM_ID2 VRAM_ID1 VRAM_ID0

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

GPU_VID0

T63T63

PX@

1 2

GPU_VID1

T70T70

PEG_CLKREQ#

GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO

TEST_EN

+VREFG_GPU

+DPLL_PVDD

+DPLL_VDDC

XTALIN XTALOUT

12 12

U8B

Y11

DVCLK

AE9

DVCNTL_0

L9

DVCNTL_1

N9

DVCNTL_2

AE8

DVDATA_12

AD9

DVDATA_11

AC10

DVDATA_10

AD7

DVDATA_9

AC8

DVDATA_8

AC7

DVDATA_7

AB9

DVDATA_6

AB8

DVDATA_5

AB7

DVDATA_4

AB4

DVDATA_3

AB2

DVDATA_2

Y8

DVDATA_1

Y7

DVDATA_0

W6

DPC_PVDD

V6

DPC_PVSS

AC6

DPC_VDD18#1

AC5

DPC_VDD18#2

AA5

DPC_VDD10#1

AA6

DPC_VDD10#2

U1

DPC_VSSR#1

W1

DPC_VSSR#2

U3

DPC_VSSR#3

Y6

DPC_VSSR#4

AA1

DPC_VSSR#5

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

TESTEN_LEGACY

T65T65

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AB16

PX_EN

AC16

VREFG

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

216-0774207-A11ROB_FCBGA631

SXTR1@

PLL/CLOCK

THERMAL

C

AF2

TXCAP_DPA3P

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TX0P_DPC2P

TX0M_DPC2N

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

DPC_CALR

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

COMP

H2SYNC V2SYNC

VDD2DI

VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDC6CLK

DDC6DATA

C

AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

1 2

J8

R307

150_0402_1%

PX@

AM26

T55T55

R

AK26

RB

AL25

T56T56

G

AJ25

GB

AH24

T57T57

B

AG25

BB

AH26

VGA_HSYNC

AJ27

VGA_VSYNC

PX@

1 2

AD22

R318

R318 499_0402_1%

499_0402_1%

AG24

+AVDD

AE22

AE23

+VDD1DI

AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13

T53T53

AJ13

T54T54

AD19 AC19

AE20

AE17

AE19

@

1 2

AG13

R330

R330 715_0402_1%

715_0402_1%

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AD20 AC20

AE16 AD16

AC1

T58T58

AC3

T59T59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/01/15 2013/01/15

Compal Secret Data

TXCAM_DPA3N

DPA

DVO

DPA

DVO

TXCBM_DPB3N

DPB

DPC

TXCCP_DPC3P TXCCM_DPC3N

DAC1

DAC2

DDC/AUX

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX5P

DDCDATA_AUX5N

D

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

VGA_HSYNC VGA_VSYNC

+AVDD

+VDD1DI

PX@R327

PX@

10K_0402_5%

VGA_SMB_CK2_R

VGA_SMB_DA2_R

Deciphered Date

D

+AVDD

R327

PX@

R339 10K_0402_5%@R 339 10K_0402_5%@ R338 10K_0402_5%PX@R338 10K_0402_5%PX@ R325 10K_0402_5%PX@R325 10K_0402_5%PX@ R320 10K_0402_5%PX@R320 10K_0402_5%PX@

R313 10K_0402_5%@R 313 10K_0402_5%@ R314 10K_0402_5%@R 314 10K_0402_5%@

R315 10K_0402_5%PX@R315 10K_0402_5%PX@ R316 10K_0402_5%@R 316 10K_0402_5%@ R317 10K_0402_5%@R 317 10K_0402_5%@

R548 10K_0402_5%@R 548 10K_0402_5%@ R549 10K_0402_5%@R 549 10K_0402_5%@

1

C397

PX@

2

0.1U_0402_10V6K

1

C313

2

0.1U_0402_10V6K

12

1 2 1 2

1 2

BLM15BD121SN1D_0402

1

C401

C400

PX@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

1 2

BLM15BD121SN1D_0402

1

C396

C315

PX@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

12

R328

PX@R328

PX@

10K_0402_5%

1

DMN66D0LDW-7_SOT363-6

12 12 12 12

12 12

12 12 12

PX@

2

PX@Q64A

PX@

L10

L11

Q64A

E

+3VGS

+1.8VGS

+3VGS+3VGS

6

5

34

Q64B

PX@Q64B

PX@

DMN66D0LDW-7_SOT363-6

Title

Size Document Number Rev

C

Date: Sheet of

Date: Sheet

EC_SMB_CK2 <28,31>

EC_SMB_DA2 <28,31>

Compal Electronics, Inc.

SeymourXT-S3 Main Gen/MSIC

VAUS5 LA9001P M/B

E

0.3

of

16 50Friday, May 25, 2012