COMPAL LA-9001P Schematics

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1 1

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D

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Compal Confidential

2 2

VIUS5 LA-9001P M/B Schematics Document

AMD FP2 Processor with DDRIII + Husdon M3 FCH

AMD VGA Seymour XT

3 3

2012-05-31

REV:0.3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

VAUS5 LA9001P M/B

E

1 50Thursday, May 31, 2012

0.3

www.qdzbwx.com

A

Compal confidential

File Name :

AMD Seymour XT

B

C

D

E

1 1

VRAM 128x16, 64x16 DDR3 x 4

page 15,~21

LVDS translator

RTD2132S

page 22 page 24

HDMI Conn.

4 * x1 PCI-E 2.0

LVDS Conn.

page 23

2 2

PCI Express Mini card Slot 1

WLAN

3 3

page 25

PCI Express Mini card Slot 2

page 25

USB(reserve for WiMAX)

PCI-E(WLAN)

SATA(SSD)

GPP0

LAN(10/100/Giga)

Realtek 8105E-VD (10/100) 8111F-CGT (Giga)

page 26

RJ45 CONN

page 27

SPI ROM

Gen2PCIE x 8

DP Port0

DP Port2

page 11

AMD FP2 APU

Trinity BGA 813 pin 27mm x 30mm

page 5,~8

x4 UMI Gen. 1

2.5GT/s per lane

Hudson M3

uFCBGA-656

24.5mm x 24.5mm

page 10,~14

LPC BUS

EC

ENE KB9012

page 31

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1333MT/s Upgradeable to 4G Memory

AZALIA

1*USB3.0,6*USB2.0

1*SATA serial

204pin DDRIII-SO-DIMM X 1

BANK 0, 1

page 9

2Channel Speaker

Single Digital MIC

IO Board page 32

Audio Codec

RealTek ALC259-VC2

CMOS Camera

page 30

page 23

USB PORT 3.0 x1(Left)

Audio Combo Jack (APPLE type)

Stereo HeadPhone Output Microphone Input

IO Board

page 33

Card Reader RTS 5178 (2in1)

USB PORT 2.0 x2(Right)

page 32

IO Board

page 30

page 32

IO Board

www.qdzbwx.com

Sub-borad

POWER Board

LED Board

IO Board

4 4

A

B

Touch Pad

page 32

Thermal Sensor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

Int.KBD

page 32

SATA1

page 28

Compal Secret Data

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

SATA2.0 HDD CONN

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

page 29

Compal Electronics, Inc.

MB Block Diagram

VAUS5 LA9001P M/B

2 50Friday, May 25, 2012

E

0.3

A

Voltage Rails

power plane

1 1

+B

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

+5VALW

+3VALW

+1.1VALW

O

X

X X X

+1.5V

+1.5V_APU

O

X X

X

SMBUS Control Table

SOURCE

SMB_EC_CK1 SMB_EC_DA1

SMB_EC_CK2_SUS SMB_EC_DA2_SUS

FCH_SCLK0 FCH_SDATA0

3 3

SMB_EC_CK2 SMB_EC_DA2

KB9012

+3VALW

KB9012

+3VALW

FCH

+3VS

KB9012

+3VS (LV shifter)

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

FCH SM Bus address

Device Address

DDR DIMM1

4 4

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V V V

1001 000Xb

X

X X

X

X X

EC SM Bus2 address

Device

Thermal Sen sor

SB-TSI(default)

VGA(thermal)

RTD2132S

WLAN WWAN

X X

V

+3VS +3VS

X XX

V

1001_101xb

1001_100xb

1000_001xb

1010_1000b

B

+5VS

+3VS

+2.5VS

+1.5VS

+1.2VS

+1.1VS

+0.75VS

+APU_CORE

+APU_CORE_NB

+VGA_CORE

+3.3VGS

+1.8VGS

+1.5VGS

+1.0VGS

Thermal Sensor

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

C

SLP_S3# SLP_S5# +VALW +V +VS Clock

ON

ONONON ON

ON

OFF

HIGH HIGH

HIGHHIGH

HIGH

LOW

HIGH

LOW LOW

LOW

OFF

D

E

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0 1 2 3

OO

4 5 6

X

7

PCB Revision

0.3

ID BRD ID R a Rb Vab

x

0

0V

0.25V

0.5V

0.82VR01 EVT

1

2

3

R10 MP0

R03 PVT

R02 DVT

100K

8.2K

18K

33K

Ra = R1562 Rb = R1564

USB Port Table

X

USB 3.0USB 2.0 Port

0 1 2 3

4 External USB Port

USB Port (Right Side 1) USB Port (Right Side 2) Mini Card(WLAN) Camera

4 5

FCH

X

XX XX

X

APU RTD2132

X X

V

+1.5V

X X

X

0 1

XHCI

2 3

USB OC MAPPING

CardReader

6 7 8 9

10

USB Port (Left Side)

11 12 13

OC# USB Port

0 1

USB20 port10

USB20 port0 port1

USB30 port0

2 3

APU PCIE PORT LIST

Port Device

1

LAN

2

WLAN

3 4

FCH PCIE PORT LIST

Port Device

1 2 3 4

BOM Structure Table

BTO ItemBOM Structure

A4R1@ A4R3@ A6R1@ A6R3@ A8R1@ A8R3@ A10R1@ A10R3@ SXTR1@ SXTR3@ A70MR1@ A70MR3@ PX@ CMOS@ UMA@ GAS@ 8105@ GIGA@ HDMI@ NONAOAC@ AOAC@ ME@ DEBUG@ @ SSD@

A4 BGA APU (R1 compal part)

A4 BGA APU (R3 compal part)

A6 BGA APU (R1 compal part)

A6 BGA APU (R3 compal part)

A8 BGA APU (R1 compal part)

A8 BGA APU (R3 compal part)

A10 BGA APU (R1 compal part)

A10 BGA APU (R3 compal part)

Seymour XT GPU (R1 compal part)

Seymour XT GPU (R3 compal part)

A70 Hudson M3 FCH (R1 compal part)

A70 Hudson M3 FCH (R3 compal part)

Common VGA circuit

CMOS Camera part

UMA strap pin

Gastube

RTL8105E

RTL8111F

HDMI part

No AOAC function

support AOAC function

ME part

Debug Switch (MP will remove)

Unpop

SSD part

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

VAUS5 LA9001P M/B

E

3 50Tuesday, May 29, 2012

0.3

A

B

C

D

E

Power-Up/Down Sequence

"Thames" has the following requirements with regards to power-supply sequencing to avoid damaging the ASIC:

All the ASIC supplies, except for VDDR3, must fully reach their respective

‧

nominal voltages within 20 ms of the start of the ramp-up sequence, though a

1 1

shorter ramp-up duration is preferred. There is no timing requirement on the ramp up of VDDR3 relative to other power rails.

The external pull-up resistors on the DDC/AUX signals (if applicable) should

‧

ramp up before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

‧

should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO enabled designs, VDDC must ramp up before VDD_CT at system power up.

For power down, reversing the ramp-up sequence is recommended

‧

VDDR3(3.3VGS)

Without BACO option :

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode) PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10

PCIE_VDDC

VDDR3

BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode)

VDDR1

VDDC/VDDCI

Voltage

1.8V

1.0V

3.3V

Same as VDDC

1.5V

TBD

PX 3.0

OFF

BACO Mode

ON

ON Same as PCIE_VDDC

OFF

1679mA

775mA

1.1A

60mA

70mA

1.2A

28

PCIE_VDDC(1.0V)

2 2

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

PERSTb

REFCLK

Straps Reset

Straps Valid

3 3

Global ASIC Reset

PX5.0

less than 20ms (Seymour)

4 4

A

T4+16clock

B

iGPU

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

PE_GPIO0(PXS_RST#)

PE_GPIO1(PXS_PWREN)

+3.3VALW

+1.5V_IO

+5VLAW

Compal Secret Data

Deciphered Date

D

MOS

PWM

Regulator

dGPU

1

2

5

+3.3VGS

+1.0VGS

+1.8VGS

+VGA_CORE

BIF_VDDC

Short PX_MODE and PX_PWREN

B+

Regulator

+B

Regulator

Title

Size Document Number Rev

Date: Sheet of

+1.5VGS

3

+VGA_CORE

4

Compal Electronics, Inc.

VGA Notes List

VAUS5 LA9001P M/B

E

www.qdzbwx.com

0.3

4 50Friday, May 25, 2012

0.3

A

B

C

D

E

PCIE_CRX_GTX_P[0..7]<15>

UCPU1A

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

1 1

PCIE_CRX_DTX_P0<26> PCIE_CRX_DTX_N0<26> PCIE_CRX_DTX_P1<25>

2 2

PCIE_CRX_DTX_N1<25>

UMI_RXP0<10> UMI_RXN0<10> UMI_RXP1<10> UMI_RXN1<10> UMI_RXP2<10> UMI_RXN2<10> UMI_RXP3<10> UMI_RXN3<10>

+1.2VS

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0 402_1%R1 196_0 402_1%

P_ZVDDP

AP1

P_GFX_RXP[0]

AP2

P_GFX_RXN[0]

AM1

P_GFX_RXP[1]

AM2

P_GFX_RXN[1]

AK3

P_GFX_RXP[2]

AK4

P_GFX_RXN[2]

AJ1

P_GFX_RXP[3]

AJ2

P_GFX_RXN[3]

AH4

P_GFX_RXP[4]

AH3

P_GFX_RXN[4]

AF2

P_GFX_RXP[5]

AF1

P_GFX_RXN[5]

AD1

P_GFX_RXP[6]

AD2

P_GFX_RXN[6]

AB3

P_GFX_RXP[7]

AB4

P_GFX_RXN[7]

AA1

P_GFX_RXP[8]

AA2

P_GFX_RXN[8]

Y4

P_GFX_RXP[9]

Y3

P_GFX_RXN[9]

V2

P_GFX_RXP[10]

V1

P_GFX_RXN[10]

T1

P_GFX_RXP[11]

T2

P_GFX_RXN[11]

P3

P_GFX_RXP[12]

P4

P_GFX_RXN[12]

N1

P_GFX_RXP[13]

N2

P_GFX_RXN[13]

M4

P_GFX_RXP[14]

M3

P_GFX_RXN[14]

K2

P_GFX_RXP[15]

K1

P_GFX_RXN[15]

AH5

P_GPP_RXP[0]

AH6

P_GPP_RXN[0]

AG5

P_GPP_RXP[1]

AG6

P_GPP_RXN[1]

AE6

P_GPP_RXP[2]

AE5

P_GPP_RXN[2]

AD6

P_GPP_RXP[3]

AD5

P_GPP_RXN[3]

AM10

P_UMI_RXP[0]

AN10

P_UMI_RXN[0]

AN8

P_UMI_RXP[1]

AM8

P_UMI_RXN[1]

AP8

P_UMI_RXP[2]

AR8

P_UMI_RXN[2]

AR7

P_UMI_RXP[3]

AP7

P_UMI_RXN[3]

AR11

P_ZVDDP

TRINITY-A8-SERIES_BGA813

A8R3@

P_GFX_TXP[0] P_GFX_TXN[0] P_GFX_TXP[1] P_GFX_TXN[1] P_GFX_TXP[2] P_GFX_TXN[2] P_GFX_TXP[3] P_GFX_TXN[3] P_GFX_TXP[4] P_GFX_TXN[4] P_GFX_TXP[5] P_GFX_TXN[5] P_GFX_TXP[6] P_GFX_TXN[6] P_GFX_TXP[7] P_GFX_TXN[7] P_GFX_TXP[8]

GRAPHICSGPPUMI

P_GFX_TXN[8] P_GFX_TXP[9]

P_GFX_TXN[9] P_GFX_TXP[10] P_GFX_TXN[10] P_GFX_TXP[11] P_GFX_TXN[11] P_GFX_TXP[12] P_GFX_TXN[12] P_GFX_TXP[13] P_GFX_TXN[13] P_GFX_TXP[14] P_GFX_TXN[14] P_GFX_TXP[15] P_GFX_TXN[15]

P_GPP_TXP[0]

P_GPP_TXN[0]

P_GPP_TXP[1]

P_GPP_TXN[1]

P_GPP_TXP[2]

P_GPP_TXN[2]

P_GPP_TXP[3]

P_GPP_TXN[3]

P_UMI_TXP[0]

P_UMI_TXN[0]

P_UMI_TXP[1]

P_UMI_TXN[1]

P_UMI_TXP[2]

P_UMI_TXN[2]

P_UMI_TXP[3]

P_UMI_TXN[3]

P_ZVSS

AN1 AN2 AM4 AM3 AK2 AK1 AH1 AH2 AF3 AF4 AE1 AE2 AD4 AD3 AB2 AB1 Y1 Y2 V3 V4 U1 U2 T4 T3 P2 P1 M1 M2 K3 K4 J1 J2

AG7 AG8 AE7 AE8 AD7 AD8 AB6 AB5

AN6 AM6 AP6 AR6 AP4 AR4 AP3 AR3

AP11

Compensation Resistor to VSS Compensation Resistor to VDDP

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

PCIE_CTX_C_DRX_P0 PCIE_CTX_C_DRX_N0 PCIE_CTX_C_DRX_P1 PCIE_CTX_C_DRX_N1

UMI_TXP0_C UMI_TXN0_C UMI_TXP1_C UMI_TXN1_C UMI_TXP2_C UMI_TXN2_C UMI_TXP3_C UMI_TXN3_C

1 2

P_ZVSS

R2 196_0 402_1%R2 196_0 402_1%

1 2

C1 0.1U_0402_16V7KPX@C1 0.1U_0402_16V7KPX@

1 2

C2 0.1U_0402_16V7KPX@C2 0.1U_0402_16V7KPX@

1 2

C3 0.1U_0402_16V7KPX@C3 0.1U_0402_16V7KPX@

1 2

C4 0.1U_0402_16V7KPX@C4 0.1U_0402_16V7KPX@

1 2

C5 0.1U_0402_16V7KPX@C5 0.1U_0402_16V7KPX@

1 2

C6 0.1U_0402_16V7KPX@C6 0.1U_0402_16V7KPX@

1 2

C7 0.1U_0402_16V7KPX@C7 0.1U_0402_16V7KPX@

1 2

C8 0.1U_0402_16V7KPX@C8 0.1U_0402_16V7KPX@

1 2

C9 0.1U_0402_16V7KPX@C9 0.1U_0402_16V7KPX@

1 2

C10 0.1U_0402_16V7KPX@C10 0.1U_0402_16V7KPX@

1 2

C11 0.1U_0402_16V7KPX@C11 0.1U_0402_16V7KPX@

1 2

C12 0.1U_0402_16V7KPX@C12 0.1U_0402_16V7KPX@

1 2

C13 0.1U_0402_16V7KPX@C13 0.1U_0402_16V7KPX@

1 2

C14 0.1U_0402_16V7KPX@C14 0.1U_0402_16V7KPX@

1 2

C15 0.1U_0402_16V7KPX@C15 0.1U_0402_16V7KPX@

1 2

C16 0.1U_0402_16V7KPX@C16 0.1U_0402_16V7KPX@

1 2

C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K

1 2

C34 0.1U_0402_16V7KC34 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C39 0.1U_0402_16V7KC39 0.1U_0402_16V7K

1 2

C40 0.1U_0402_16V7KC40 0.1U_0402_16V7K

1 2

C41 0.1U_0402_16V7KC41 0.1U_0402_16V7K

1 2

C42 0.1U_0402_16V7KC42 0.1U_0402_16V7K

1 2

C43 0.1U_0402_16V7KC43 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KC44 0.1U_0402_16V7K

PCIE_CTX_GRX_P[0..7] < 15>

PCIE_CTX_GRX_N[0..7] <15>PCIE_CRX_GTX_N[0..7]<15>

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_CTX_DRX_P0 <26> PCIE_CTX_DRX_N0 <26> PCIE_CTX_DRX_P1 <25> PCIE_CTX_DRX_N1 <25>

UMI_TXP0 <10> UMI_TXN0 <10> UMI_TXP1 <10> UMI_TXN1 <10> UMI_TXP2 <10> UMI_TXN2 <10> UMI_TXP3 <10> UMI_TXN3 <10>

LAN

WLAN

All power supplies in Power Sequencing Group A must be stable and within specification before any power supply in Power Sequencing Group B is greater than 10 percent of its specified typical operating value.

3 3

All power supplies in Power Sequencing Group B must be stable and within specification one ms before the assertion of PWROK.

No sequencing relationships are required between the power sequencing groups during S3 entry. DDR3 compatible processors require VDDIO to remain powered and within specification during the S3 sleep state. All other processor power supply planes are powered down during S3.

Power Sequence of APU

+1.5V (+1.5V_APU)

UCPU1

A4R3@UCPU1

A4R3@

UCPU1

A6R3@UCPU1

A6R3@

UCPU1

A10R3@UCPU1

A10R3@

ZZZ1

+2.5VS (+APU_VDDA)

+1.5VS

A6 SERIES ZM212169E2451 2.1G BGA813

A4 SERIES ZM198169E2351 1.9G BGA813

UCPU1

4 4

A4 SERIES AM4355SHE23HJ 1.9G BGA813

UCPU1

A8 SERIES AM4555SHE44HJ 1.6G BGA813

A

A4R1@UCPU1

A4R1@

A8R1@UCPU1

A8R1@

B

A6 SERIES ZM212169E2451 2.1G BGA813

UCPU1

A6R1@UCPU1

A6R1@

A6 SERIES AM4455SHE24HJ 2.1G BGA813

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A10 SERIES ZM202268E4451 2G BGA813P

A10 SERIES AM4655SIE44HJ 2G BGA813P

Issued Date

C

LA9001P

DA60000TW00

UCPU1

A10R1@UCPU1

A10R1@

2012/01/15 2013/01/15

DA60000TW00

Compal Secret Data

Deciphered Date

+APU_CORE

+APU_CORE_NB

+1.2VS

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FP2 PCIE/UMI

VAUS5 LA9001P M/B

E

5 50Tuesday, May 29, 2012

Group A

Group B

0.3

www.qdzbwx.com

A

B

C

D

E

1 1

2 2

3 3

DDRA_SMA[15..0]<9>

DDRA_SBS0#<9> DDRA_SBS1#<9> DDRA_SBS2#<9> DDRA_SDM[7..0]<9>

DDRA_SDQS0<9> DDRA_SDQS0#<9> DDRA_SDQS1<9> DDRA_SDQS1#<9> DDRA_SDQS2<9> DDRA_SDQS2#<9> DDRA_SDQS3<9> DDRA_SDQS3#<9> DDRA_SDQS4<9> DDRA_SDQS4#<9> DDRA_SDQS5<9> DDRA_SDQS5#<9> DDRA_SDQS6<9> DDRA_SDQS6#<9> DDRA_SDQS7<9> DDRA_SDQS7#<9>

DDRA_CLK0<9> DDRA_CLK0#<9> DDRA_CLK1<9> DDRA_CLK1#<9>

DDRA_CKE0<9> DDRA_CKE1<9>

DDRA_ODT0<9> DDRA_ODT1<9>

DDRA_SCS0#<9> DDRA_SCS1#<9>

DDRA_SRAS#<9> DDRA_SCAS#<9> DDRA_SWE#<9>

MEM_MA_RST#<9> MEM_MA_EVENT#<9>

+MEM_VREF

+1.5V_APU

Place them close to APU within 1"

Place them close to APU within 1"Place them close to APU within 1"

15mil

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

UCPU1B

AA28

MA_ADD[0]

R29

MA_ADD[1]

T30

MA_ADD[2]

R28

MA_ADD[3]

R26

MA_ADD[4]

P26

MA_ADD[5]

P27

MA_ADD[6]

P30

MA_ADD[7]

P29

MA_ADD[8]

M28

MA_ADD[9]

AB26

MA_ADD[10]

M26

MA_ADD[11]

M29

MA_ADD[12]

AE27

MA_ADD[13]

L26

MA_ADD[14]

L27

MA_ADD[15]

AB27

MA_BANK[0]

AA29

MA_BANK[1]

M30

MA_BANK[2]

D16

MA_DM[0]

D20

MA_DM[1]

E25

MA_DM[2]

F30

MA_DM[3]

AK29

MA_DM[4]

AL25

MA_DM[5]

AM20

MA_DM[6]

AM16

MA_DM[7]

G17

MA_DQS_H[0]

H17

MA_DQS_L[0]

F22

MA_DQS_H[1]

G22

MA_DQS_L[1]

E26

MA_DQS_H[2]

F26

MA_DQS_L[2]

H30

MA_DQS_H[3]

G30

MA_DQS_L[3]

AL29

MA_DQS_H[4]

AL30

MA_DQS_L[4]

AH25

MA_DQS_H[5]

AJ25

MA_DQS_L[5]

AK20

MA_DQS_H[6]

AL20

MA_DQS_L[6]

AK15

MA_DQS_H[7]

AL15

MA_DQS_L[7]

W29

MA_CLK_H[0]

Y30

MA_CLK_L[0]

W26

MA_CLK_H[1]

W27

MA_CLK_L[1]

U29

MA_CLK_H[2]

V30

MA_CLK_L[2]

U26

MA_CLK_H[3]

U27

MA_CLK_L[3]

L29

MA_CKE[0]

K30

MA_CKE[1]

AD30

MA0_ODT[0]

AG28

MA0_ODT[1]

AE26

MA1_ODT[0]

AG29

MA1_ODT[1]

AD26

MA0_CS_L[0]

AE29

MA0_CS_L[1]

AB30

MA1_CS_L[0]

AF30

MA1_CS_L[1]

AB29

MA_RAS_L

AD29

MA_CAS_L

AD28

MA_WE_L

J28

MA_RESET_L

AA26

MA_EVENT_L

G32

M_VREF

AJ32

M_ZVDDIO

TRINITY-A8-SERIES_BGA813

A8R3@

MA_DATA[0] MA_DATA[1] MA_DATA[2] MA_DATA[3] MA_DATA[4] MA_DATA[5] MA_DATA[6] MA_DATA[7]

MA_DATA[8]

MA_DATA[9] MA_DATA[10] MA_DATA[11] MA_DATA[12] MA_DATA[13] MA_DATA[14] MA_DATA[15]

MA_DATA[16] MA_DATA[17] MA_DATA[18] MA_DATA[19] MA_DATA[20] MA_DATA[21] MA_DATA[22] MA_DATA[23]

MA_DATA[24] MA_DATA[25] MA_DATA[26] MA_DATA[27] MA_DATA[28] MA_DATA[29] MA_DATA[30] MA_DATA[31]

MA_DATA[32] MA_DATA[33] MA_DATA[34] MA_DATA[35] MA_DATA[36] MA_DATA[37] MA_DATA[38] MA_DATA[39]

MA_DATA[40] MA_DATA[41] MA_DATA[42] MA_DATA[43] MA_DATA[44] MA_DATA[45] MA_DATA[46] MA_DATA[47]

MA_DATA[48] MA_DATA[49] MA_DATA[50] MA_DATA[51] MA_DATA[52] MA_DATA[53] MA_DATA[54] MA_DATA[55]

MA_DATA[56] MA_DATA[57] MA_DATA[58] MA_DATA[59] MA_DATA[60] MA_DATA[61] MA_DATA[62] MA_DATA[63]

F15 E15 H19 F19 E14 H15 E17 D18

G20 E20 H23 G23 E19 H20 E22 D22

H25 F25 D28 D29 E23 D24 D26 D27

G28 G29 H27 J29 E28 F27 H29 H28

AH29 AJ30 AM28 AM27 AH27 AH28 AJ29 AK27

AK26 AJ26 AK23 AJ23 AM26 AL26 AM24 AL23

AK22 AH22 AK19 AH19 AM22 AL22 AJ20 AL19

AK17 AJ17 AK14 AH14 AM18 AL17 AH15 AL14

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] <9>

MEM_MB_EVENT#

UCPU1C

Y33

MB_ADD[0]

R32

MB_ADD[1]

T31

MB_ADD[2]

P33

MB_ADD[3]

P32

MB_ADD[4]

P31

MB_ADD[5]

N32

MB_ADD[6]

M33

MB_ADD[7]

M32

MB_ADD[8]

L32

MB_ADD[9]

AB31

MB_ADD[10]

M31

MB_ADD[11]

K32

MB_ADD[12]

AF33

MB_ADD[13]

K33

MB_ADD[14]

J32

MB_ADD[15]

AB33

MB_BANK[0]

AA32

MB_BANK[1]

K31

MB_BANK[2]

C18

MB_DM[0]

B23

MB_DM[1]

C28

MB_DM[2]

D31

MB_DM[3]

AM31

MB_DM[4]

AN30

MB_DM[5]

AR24

MB_DM[6]

AN18

MB_DM[7]

B18

MB_DQS_H[0]

A18

MB_DQS_L[0]

B24

MB_DQS_H[1]

A24

MB_DQS_L[1]

B30

MB_DQS_H[2]

B29

MB_DQS_L[2]

D32

MB_DQS_H[3]

D33

MB_DQS_L[3]

AM32

MB_DQS_H[4]

AM33

MB_DQS_L[4]

AN28

MB_DQS_H[5]

AP29

MB_DQS_L[5]

AP23

MB_DQS_H[6]

AP24

MB_DQS_L[6]

AR18

MB_DQS_H[7]

AP18

MB_DQS_L[7]

W32

MB_CLK_H[0]

Y32

MB_CLK_L[0]

V33

MB_CLK_H[1]

V32

MB_CLK_L[1]

U32

MB_CLK_H[2]

V31

MB_CLK_L[2]

T33

MB_CLK_H[3]

T32

MB_CLK_L[3]

H32

MB_CKE[0]

H33

MB_CKE[1]

AF31

MB0_ODT[0]

AH31

MB0_ODT[1]

AE32

MB1_ODT[0]

AH33

MB1_ODT[1]

AD31

MB0_CS_L[0]

AF32

MB0_CS_L[1]

AC32

MB1_CS_L[0]

AG32

MB1_CS_L[1]

AB32

MB_RAS_L

AD32

MB_CAS_L

AD33

MB_WE_L

H31

MB_RESET_L

Y31

MB_EVENT_L

TRINITY-A8-SERIES_BGA813

A8R3@

MB_DATA[0] MB_DATA[1] MB_DATA[2] MB_DATA[3] MB_DATA[4] MB_DATA[5] MB_DATA[6] MB_DATA[7]

MB_DATA[8]

MB_DATA[9] MB_DATA[10] MB_DATA[11] MB_DATA[12] MB_DATA[13] MB_DATA[14] MB_DATA[15]

MB_DATA[16] MB_DATA[17] MB_DATA[18] MB_DATA[19] MB_DATA[20] MB_DATA[21] MB_DATA[22] MB_DATA[23]

MB_DATA[24] MB_DATA[25] MB_DATA[26] MB_DATA[27] MB_DATA[28] MB_DATA[29] MB_DATA[30] MB_DATA[31]

MB_DATA[32] MB_DATA[33] MB_DATA[34] MB_DATA[35] MB_DATA[36] MB_DATA[37] MB_DATA[38] MB_DATA[39]

MB_DATA[40] MB_DATA[41] MB_DATA[42] MB_DATA[43] MB_DATA[44] MB_DATA[45] MB_DATA[46] MB_DATA[47]

MB_DATA[48] MB_DATA[49] MB_DATA[50] MB_DATA[51] MB_DATA[52] MB_DATA[53] MB_DATA[54] MB_DATA[55]

MB_DATA[56] MB_DATA[57] MB_DATA[58] MB_DATA[59] MB_DATA[60] MB_DATA[61] MB_DATA[62] MB_DATA[63]

C16 B17 B20 C20 A16 B16 B19 A20

B22 C22 A26 B26 B21 A22 C24 B25

A28 B28 B31 A32 C26 B27 A30 C30

B33 C32 F33 F32 B32 C31 E32 F31

AK32 AL32 AP32 AN31 AK31 AK33 AN32 AP33

AP30 AR30 AP27 AN26 AR32 AP31 AR28 AP28

AP25 AN24 AR22 AP21 AP26 AR26 AN22 AP22

AR20 AP19 AP16 AR16 AN20 AP20 AP17 AN16

www.qdzbwx.com

EVENT# pull high 0.75V reference voltage

+1.5V_APU

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT#

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V_APU

1 2

B

1

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

+MEM_VREF

2

C46

0.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FP2 DDRIII Memory I/F

VAUS5 LA9001P M/B

6 50Tuesday, May 29, 2012

E

0.3

A

Place near APU

1 2

LVDS

1 1

DP0_TXP0_C<22> DP0_TXN0_C<22>

HDMI

2 2

3 3

C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K

1 2

C4888 0.1U_0402_16V7KC4888 0.1U_0402_16V7K

DP2_TXP0<24> DP2_TXN0<24>

DP2_TXP1<24> DP2_TXN1<24>

DP2_TXP2<24> DP2_TXN2<24>

DP2_TXP3<24> DP2_TXN3<24>

APU_CLK<10> APU_CLK#<10>

APU_DISP_CLK<10> APU_DISP_CLK#<10>

APU_SVC<43> APU_SVD<43>

APU_SVT<43>

APU_RST#<10> APU_PWRGD<10,43>

APU_PROCHOT#<10>

APU_VDD_SEN_L<43>

APU_VDDNB_SEN_H<43>

APU_VDD_SEN_H<43>

Route as differential with APU_VDD_SEN_L

APU_SIC APU_SID

APU_PWRGD

APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

DP0_TXP0 DP0_TXN0

B

UCPU1D

H2

DP0_TXP[0]

H1

DP0_TXN[0]

H3

DP0_TXP[1]

H4

DP0_TXN[1]

F4

DP0_TXP[2]

F3

DP0_TXN[2]

F1

DP0_TXP[3]

F2

DP0_TXN[3]

E2

DP1_TXP[0]

E1

DP1_TXN[0]

D4

DP1_TXP[1]

D3

DP1_TXN[1]

D1

DP1_TXP[2]

D2

DP1_TXN[2]

C1

DP1_TXP[3]

C2

DP1_TXN[3]

B2

DP2_TXP[0]

A2

DP2_TXN[0]

B3

DP2_TXP[1]

A3

DP2_TXN[1]

B4

DP2_TXP[2]

A4

DP2_TXN[2]

B5

DP2_TXP[3]

A5

DP2_TXN[3]

AL9

CLKIN_H

AK9

CLKIN_L

AL7

DISP_CLKIN_H

AK7

DISP_CLKIN_L

E5

SVC

E6

SVD

D6

SVT

AJ11

SIC

AH11

SID

AK11

RESET_L

AH9

PWROK

AL12

PROCHOT_L

AK5

THERMTRIP_L

AR10

ALERT_L

E11

TDI

G11

TDO

H12

TCK

F11

TMS

H11

TRST_L

E8

DBRDY

E7

DBREQ_L

G6

VSS_SENSE

H6

VDDP_SENSE

H5

VDDNB_SENSE

G7

VDDIO_SENSE

G5

VDD_SENSE

H7

VDDR_SENSE

TRINITY-A8-SERIES_BGA813

A8R3@

DISPLAY PORT 0DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD

DISPLAY PORT MISC.RSVD TEST

DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST6

TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

TEST4

TEST5

RSVD RSVD RSVD RSVD RSVD

M5 M6

L5 L6

J5 J6

P5 P6

R5 R6

U5 U6

M7 L7 J7 P7 R7 U7

C6 D7 A6

B6

AL6 Y23 V23 G9 F9 E9 G8 F12 E12 F14 G12 AJ8 AH8 G14 H14 V25 Y25 AH32 R25 T25 AL5

AP10

T23 R23

L8 P8 AH12 AJ12 AK12

DP0_AUXP DP0_AUXN

DP_AUX_ZVSS

APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 TEST25_H TEST25_L

APU_TEST31

APU_TEST35

C

1 2

C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K

1 2

C5088 0.1U_0402_16V7KC5088 0.1U_0402_16V7K

LVDS_HPD <22>

HDMI_DET <24>

DP_INT_PWM <22>

1 2

R15 150_0402_1%R15 150_0402_1%

T1T1 T2T2 T3T3 T4T4 T5T5 T6T6

1 2

R17 510_0402_1%R17 510_0402_1%

1 2

R18 510_0402_1%R18 510_0402_1%

T7T7 T8T8 T17T17 T18T18

T19T19 T20T20

T9T9 T10T10

1 2

R21 39.2_0402_1%R21 39.2_0402_1%

1 2

R22 300_0402_5%HDMI@R22 300_0402_5%HDMI@

1 2

R23 300_0402_5%@R23 300_0402_5%@

ALLOW_STOP <10>

DP0_AUXP_C <22> DP0_AUXN_C <22>

HDMI_CLK < 24> HDMI_DATA <24>

+1.2VS

+1.5V_APU

D

To LVDS Translater

To HDMI

Asserted as an input to force the processor into the HTC-active state

APU_PROCHOT#

THERMTRIP shutdown temperature: 125 degree

1K_0402_5%

APU_THERMTRIP#

DP0_AUXP

DP0_AUXN

R12

1K_0402_5%

1 2

+1.5V_APU

R19

12

1 2

B

2

E

3 1

MMBT3904_NL_SOT23-3

R10 1.8K_0402_5%R10 1.8K_0402_5%

R11 1.8K_0402_5%R11 1.8K_0402_5%

10K_0402_5%

MMBT3904_NL_SOT23-3

R16 0_0402_5%R16 0_0402_5%

R20

R20 10K_0402_5%

10K_0402_5%

Q2

C

12

+3VS+1.5V_APU

12

R14

@

2

B

Q1

@

Q1

@

E

31

C

1 2

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the FCH to transition the system to S5 immediately

1 2

R24 0_0402_5%R24 0_0402_5%

1 2

R25 0_0402_5%@R25 0_0402_5%@

R13

R13 10K_0402_5%

10K_0402_5%

@

E

H_PROCHOT# <31,36,43>

H_THERMTRIP# <12>

MAINPWON <31,36,38>

+1.5V_APU

1 2

R215 1K_0402_5%R215 1K_0402_5%

1 2

R26 1K_0402_5%R26 1K_0402_5%

1 2

R28 1K_0402_5%R28 1K_0402_5%

1 2

R31 1K_0402_5%R31 1K_0402_5%

+1.5VS

1 2

R36 1K_0402_5%@R36 1K_0402_5%@

1 2

R38 300_0402_5%R38 300_0402_5%

1 2

R40 300_0402_5%R40 300_0402_5%

@

1 2

R45 1K_0402_5%

@

1 2

R48 1K_0402_5%

@

1 2

R50 1K_0402_5%

4 4

A

ALLOW_STOP

APU_SIC

APU_SID

ALERT_L

ALLOW_STOP

APU_RST#

APU_PWRGD

APU_SVT

APU_SVC

APU_SVD

CPU TSI interface level shift

1 2

R32

+3VS

31.6K_0402_1%

APU_SID

BSH111 1N_SOT23-3

APU_SIC

BSH111 1N_SOT23-3

1 2

C5988 0.1U_0402_16V4ZC5988 0.1U_0402_16V4Z

1 2

R33

30K_0402_1%

G

2

Q3

13

D

S

D

S

G

2

Q4

13

D

S

D

S

B

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2_SUS <31>

EC_SMB_CK2_SUS <31>

+1.5V_APU

APU_TRST#

1 2

To EC

R42 10K_0402_5%R42 10K_0402_5%

1 2

R46 10K_0402_5%R46 10K_0402_5%

1 2

R49 10K_0402_5%R49 10K_0402_5%

To EC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

@

D

2

4

6

8

10

12

14

16

18

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

APU_RST#

APU_DBRDY

APU_DBREQ#

R51 0_0402_5%@R51 0_0402_5%@

R52 0_0402_5%@R52 0_0402_5%@

12

Custom

Date: Sheet of

HDT Debug conn

APU_DBREQ# APU_TCK APU_TMS APU_TDI APU_TDO APU_TRST#

APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 APU_DBRDY

APU_TEST19

APU_TEST18

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

FP2 Display/MISC/HDT

VAUS5 LA9001P M/B

1 2

R27 1K_0402_5%R27 1K_0402_5%

1 2

R29 1K_0402_5%R29 1K_0402_5%

1 2

R30 1K_0402_5%R30 1K_0402_5%

1 2

R34 1K_0402_5%R34 1K_0402_5%

1 2

R35 1K_0402_5%@R35 1K_0402_5%@

1 2

R37 1K_0402_5%R37 1K_0402_5%

1 2

R39 1K_0402_5%R39 1K_0402_5%

1 2

R41 1K_0402_5%R41 1K_0402_5%

1 2

R43 1K_0402_5%R43 1K_0402_5%

1 2

R44 1K_0402_5%R44 1K_0402_5%

1 2

R47 1K_0402_5%@R47 1K_0402_5%@

E

+1.5V_APU

7 50Tuesday, May 29, 2012

0.3

www.qdzbwx.com

A

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDDR VDDR VDDR VDDR VDDR

V17 V19 V20 V22 W8 AA8 AA9 AA11 AA12 AA14 AA15 AA17 AA19 AA20 AA22 AD9 AD11 AD12 AD14 AD15 AD17 AD19 AD20 AD22 AG12 AG14 AG15 AG17 AG19 AG20 AG22

B11 B12 B13 B14 B15 C8 C10 C12 C14 D8 D10 D12 D14

M9 N9

W33 AA23 AA25 AA27 AA30 AA33 AB28 AC30 AC33 AD23 AD25 AD27 AE28 AE30 AE33 AG23 AG25 AG27 AG30 AG33

AN14 AP14 AP15 AR14 AR15

+APU_CORE

+APU_CORE_NB

+VDDNB_CAP

+1.5V_APU

+1.2VS

+APU_CORE

1 1

+APU_CORE_NB

2 2

+1.5V_APU

3 3

+1.2VS

+VDDP_CAP

+APU_VDDA

4 4

UCPU1E

J12

VDD

J14

VDD

J15

VDD

J17

VDD

J19

VDD

J20

VDD

J22

VDD

M11

VDD

M12

VDD

M14

VDD

M15

VDD

M17

VDD

M19

VDD

M20

VDD

M22

VDD

R8

VDD

R9

VDD

R11

VDD

R12

VDD

R14

VDD

R15

VDD

R17

VDD

R19

VDD

R20

VDD

R22

VDD

U8

VDD

V9

VDD

V11

VDD

V12

VDD

V14

VDD

V15

VDD

A7

VDDNB

A8

VDDNB

A9

VDDNB

A10

VDDNB

A11

VDDNB

A12

VDDNB

A13

VDDNB

A14

VDDNB

A15

VDDNB

B7

VDDNB

B8

VDDNB

B9

VDDNB

B10

VDDNB

J33

VDDIO

K23

VDDIO

K25

VDDIO

L28

VDDIO

L30

VDDIO

L33

VDDIO

M27

VDDIO

N23

VDDIO

N25

VDDIO

N30

VDDIO

N33

VDDIO

P28

VDDIO

R27

VDDIO

R30

VDDIO

R33

VDDIO

U28

VDDIO

U30

VDDIO

U33

VDDIO

W28

VDDIO

W30

VDDIO

AM12

VDDP

AN12

VDDP

AP12

VDDP

AP13

VDDP

AR12

VDDP

AR13

VDDP

AA6

VDDP_CAP

AA7

VDDP_CAP

AM13

VDDA

AM14

VDDA

TRINITY-A8-SERIES_BGA813

A8R3@

VDDNB_CAP VDDNB_CAP

B

+1.5V_APU

+1.2VS

C121 22U_0603_6.3V6MC121 22U_0603_6.3V6M

C122 22U_0603_6.3V6MC122 22U_0603_6.3V6M

1

2

Northbridge Power Pins for Remote Decoupling

+VDDP_CAP

close to APU

C

Decoupling betw een CPU and DI MMs across VDDIO an d VSS split

C69 0.22U_0402_10V4ZC69 0.22U_0402_10V4Z

C71 0.22U_0402_10V4ZC71 0.22U_0402_10V4Z

C64 4.7U_0603_6.3V6KC64 4.7U_0603_6.3V6K

C62 22U_0805_6.3V6MC62 22U_0805_6.3V6M

C63 22U_0805_6.3V6MC63 22U_0805_6.3V6M

1

2

C66 4.7U_0603_6.3V6KC66 4.7U_0603_6.3V6K

C65 4.7U_0603_6.3V6KC65 4.7U_0603_6.3V6K

C67 4.7U_0603_6.3V6KC67 4.7U_0603_6.3V6K

1

2

C68 0.22U_0402_10V4ZC68 0.22U_0402_10V4Z

1

2

C72 0.22U_0402_10V4ZC72 0.22U_0402_10V4Z

C70 0.22U_0402_10V4ZC70 0.22U_0402_10V4Z

1

2

C73 0.22U_0402_10V4ZC73 0.22U_0402_10V4Z

1

2

C77 0.22U_0402_10V4ZC77 0.22U_0402_10V4Z

C74 0.22U_0402_10V4ZC74 0.22U_0402_10V4Z

C75 0.22U_0402_10V4ZC75 0.22U_0402_10V4Z

C76 0.22U_0402_10V4ZC76 0.22U_0402_10V4Z

1

2

C81 180P_0402_50V8JC81 180P_0402_50V8J

C78 180P_0402_50V8JC78 180P_0402_50V8J

C79 180P_0402_50V8JC79 180P_0402_50V8J

C80 180P_0402_50V8JC80 180P_0402_50V8J

330U_B2_2.5VM_R15M

1

2

+1.5V

C82

1

+

@

2

C99 4.7U_0603_6.3V6KC99 4.7U_0603_6.3V6K

1

2

VDDR VDDP

C87 4.7U_0603_6.3V6KC87 4.7U_0603_6.3V6K

C85 0.01U_0402_16V7KC85 0.01U_0402_16V7K

C86 0.01U_0402_16V7KC86 0.01U_0402_16V7K

1

2

C124 22U_0603_6.3V6MC124 22U_0603_6.3V6M

C125 180P_0402_50V8JC125 180P_0402_50V8J

C123 22U_0603_6.3V6MC123 22U_0603_6.3V6M

1

2

C90 0.22U_0402_10V4ZC90 0.22U_0402_10V4Z

C89 0.22U_0402_10V4ZC89 0.22U_0402_10V4Z

C88 4.7U_0603_6.3V6KC88 4.7U_0603_6.3V6K

1

2

1

2

FBMA-L11-201209-221LMA30T_0805

L1

+2.5VS

C91 1000P_0402_50V7 KC91 1000P_0402_50V7 K

C94 180P_0402_50V8JC94 180P_0402_50V8J

C93 180P_0402_50V8JC93 180P_0402_50V8J

C92 1000P_0402_50V7 KC92 1000P_0402_50V7 K

1

2

12

C128 3300P_0402_50V7-KC128 3300P_0402_50V7-K

C127 0.22U_0402_10V4ZC127 0.22U_0402_10V4Z

C126 4.7U_0603_6.3V6KC126 4.7U_0603_6.3V6K

1

2

+APU_VDDA

C129 1000P_0402_50V7KC12 9 10 00P_0402_50V7K

1

2

+1.2VS

C113 0.22U_0402_10V4ZC113 0.22U_0402_10V4Z

C114 0.22U_0402_10V4ZC114 0.22U_0402_10V4Z

C115 1000P_0402_50V7KC11 5 1000P_040 2_50V7K

1

2

J5

@J5

@

+1.5V +1.5V_APU

1 2

PAD-OPEN 4x4m

Need Short

C130 22U_0603_6.3V6MC130 22U_0603_6.3V6M

C131 22U_0603_6.3V6MC131 22U_0603_6.3V6M

1

2

D

A17 A19 A21 A23 A25 A27 A29 A31

B1 C3 C4

C33

D5

D9 D11 D13

M23 M25

D15 D17 D19 D21 D23 D25 D30

E4 E27 E29 E30 E33

F5

F6

F7

F8

F17 F20 F23 F28 F29

G1 G2

G4 G15 G19 G25 G26 G27 G33

H8

H9 H22 H26

J4 J8

J9 J11 J23 J25 J26 J27 J30

K9 K11 K12 K14 K15 K17 K19 K20 K22

L1 L2 L4

M8

N4 N11 N12 N14 N15 N17 N19 N20 N22

R1

R2

R4

T9

T11 T12 T14 T15 T17 T19 T20 T22

U4

W1 W2 W4 W5 W6 W7

Y9

C100 4.7U_0603_6.3V6KC100 4.7U_0603_6.3V6K

C101 4.7U_0603_6.3V6KC101 4.7U_0603_6.3V6K

1

2

C116 1000P_0402_50V7KC11 6 1000P_040 2_50V7K

1

2

C104 0.22U_0402_10V4ZC104 0.22U_0402_10V4Z

C102 4.7U_0603_6.3V6KC102 4.7U_0603_6.3V6K

1

2

C117 180P_0402_50V8JC117 180P_0402_50V8J

C105 0.22U_0402_10V4ZC105 0.22U_0402_10V4Z

C103 0.22U_0402_10V4ZC103 0.22U_0402_10V4Z

1

2

C118 180P_0402_50V8JC118 180P_0402_50V8J

1

2

C108 180P_0402_50V8JC108 180P_0402_50V8J

C106 0.22U_0402_10V4ZC106 0.22U_0402_10V4Z

C107 180P_0402_50V8JC107 180P_0402_50V8J

1

2

1

2

E

UCPU1F

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TRINITY-A8-SERIES_BGA813

A8R3@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

Y11 Y12 Y14 Y15 Y17 Y19 Y20 Y22 AA4 AA5 AB7 AB8 AC1 AC2 AC4 AC9 AC11 AC12 AC14 AC15 AC17 AC19 AC20 AC22 AC23 AC25 AE4 AF9 AF11 AF12 AF14 AF15 AF17 AF19 AF20 AF22 AF23 AF25 AG1 AG2 AG4 AG9 AG11 AG26 AH7 AH17 AH20 AH23 AH26 AH30 AJ4 AJ5 AJ6 AJ7 AJ9 AJ14 AJ15 AJ19 AJ22 AJ27 AJ28 AJ33 AK6 AK8 AK25 AK28 AK30 AL1 AL2 AL4 AL8 AL11 AL27 AL28 AL33 AM5 AM7 AM9 AM11 AM15 AM17 AM19 AM21 AM23 AM25 AM29 AM30 AN3 AN4 AN33 AP5 AP9 AR2 AR5 AR9 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FP2 PW R / GND

VAUS5 LA9001P M/B

8 50Tuesday, May 29, 2012

E

0.3

A

B

C

D

E

+VREF_DQ

DDRA_SDQ0 DDRA_SDQ1

DDRA_SDM0

DDRA_SDQ2

1 1

DDRA_SDQS1#<6> DDRA_SDQS1<6>

DDRA_SDQS2#<6> DDRA_SDQS2<6>

DDRA_CKE0<6>

C145

DDRA_SDQS4#<6> DDRA_SDQS4<6>

DDRA_SDQS6#<6> DDRA_SDQS6<6>

DDRA_SBS2#<6>

DDRA_CLK0<6> DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6>

DDRA_SCS1#<6>

1

2

1

C146

0.1U_0402_16V4Z

2

A

2 2

3 3

+3VS

4 4

2.2U_0603_6.3V6K

DDRA_SDQ3

DDRA_SDQ8 DDRA_SDQ9

DDRA_SDQS1# DDRA_SDQS1

DDRA_SDQ10 DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

1 2

R57 10K_0402_5%R57 10K_0402_5%

+1.5V +1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

12

R58

R58 10K_0402_5%

10K_0402_5%

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

ME@

Reverse Type H:4mm

<Address: 00>

DQS0#

DQS0

DQ12 DQ13

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

GND2

BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

A15 A14

A11

CK1

BA1

S0#

SCL VTT

2 4

DDRA_SDQ4

6

DDRA_SDQ5

8 10

DDRA_SDQS0#

12

DDRA_SDQS0

14 16

DDRA_SDQ6

18

DDRA_SDQ7

20 22

DDRA_SDQ12

24

DDRA_SDQ13

26 28

DDRA_SDM1

30

MEM_MA_RST#

32 34

DDRA_SDQ14

36

DDRA_SDQ15

38 40

DDRA_SDQ20

42

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23DDRA_SDQ18

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

DDRA_SMA15

80

DDRA_SMA14

82 84

DDRA_SMA11

86

A7

A6 A4

A2 A0

NC

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94 96

DDRA_SMA2

98

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116

DDRA_ODT0

118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

+0.75VS

206 208

B

DDRA_SDQS0# <6> DDRA_SDQS0 <6>

MEM_MA_RST# <6>

DDRA_SDQS3# <6> DDRA_SDQS3 <6>

DDRA_CKE1 <6>

DDRA_CLK1 <6> DDRA_CLK1# <6>

DDRA_SBS1# <6 > DDRA_SRAS# <6>

DDRA_SCS0# <6> DDRA_ODT0 < 6>

DDRA_ODT1 < 6>

+VREF_CA

DDRA_SDQS5# <6> DDRA_SDQS5 <6>

DDRA_SDQS7# <6> DDRA_SDQS7 <6>

MEM_MA_EVENT# <6>

FCH_SDATA0 <12,25> FCH_SCLK0 <12,25>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

DDRA_SMA[0..15]

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

0.1U_0402_16V4Z

2012/01/15 2013/01/15

DDRA_SDQ[0..63] <6>

DDRA_SDM[0..7] <6>

DDRA_SMA[0..15] <6>

Place near DIMM1

0.1U_0402_16V4Z

2

C132

C133

1

+VREF_DQ +VREF_CA

1

C138

2

0.1U_0402_16V4Z

2

C142

1

Compal Secret Data

2

C134

1

0.1U_0402_16V4Z

1

C139

2

1000P_0402_50V7K

1

2

Deciphered Date

0.1U_0402_16V4Z

2

C135

1

0.1U_0402_16V4Z

+1.5V

R53

R53 1K_0402_1%

1K_0402_1%

1 2

R55

R55 1K_0402_1%

1K_0402_1%

1 2

C143

4.7U_0603_6.3V6K

2

C136

1

D

0.1U_0402_16V4Z

2

C137

1

+VREF_CA

15mil15mil

1

C140

2

0.1U_0402_16V4Z

SGA00001700

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.5V

R54

R54 1K_0402_1%

1K_0402_1%

1 2

1

C141

R56

R56 1K_0402_1%

2

1000P_0402_50V7K

+1.5V+0.75VS

1

+

2

1K_0402_1%

1 2

C243

220U_B2_2.5VM_R35+C243

220U_B2_2.5VM_R35

Compal Electronics, Inc.

DDRIII SO-DIMM 1

VAUS5 LA9001P M/B

0.3

9 50Friday, May 25, 2012

E

0.3

www.qdzbwx.com

A

R59/ C147 close to FCH

1 2

C147

X1

C147

PLT_RST#

C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K

+1.1VS_CKVDD

APU

R67 0_0402_5%R67 0_0402_5% R68 0_0402_5%R68 0_0402_5%

R69 0_0402_5%R69 0_0402_5% R70 0_0402_5%R70 0_0402_5%

R72 0_0402_5%R72 0_0402_5% R74 0_0402_5%R74 0_0402_5%

4

1

NC

OSC

OSC3NC

2

A

1 2

R59 33_0402_5%R59 33_0402_5%

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

R61 590_0402_1%R61 590_0402_1%

1 2

R63 2K_0402_1%R63 2K_0402_1%

1 2

R66 2K_04 02_1%R66 2K_0402_1%

APU_DISP_CLK<7> APU_DISP_CLK#<7>

1 2 1 2

@

1 2

R77 22_0402_5%

25M_X1

R80

R80 1M_0402_5%

1M_0402_5%

25M_X2

150P_0402_50V8J

UMI_RXP0<5> UMI_RXN0<5> UMI_RXP1<5> UMI_RXN1<5> UMI_RXP2<5> UMI_RXN2<5> UMI_RXP3<5>

CLK_PCIE_VGA<15> CLK_PCIE_VGA#<15>

CLK_PCIE_WLAN<25> CLK_PCIE_WLAN#<25>

CLK_PCIE_LAN<26> CLK_PCIE_LAN#<26>

CLK_LAN_25M<26>

C160

1 2

10P_0402_50V8J

C162

1 2

10P_0402_50V8J

UMI_RXN3<5>

UMI_TXP0<5> UMI_TXN0<5> UMI_TXP1<5> UMI_TXN1<5> UMI_TXP2<5> UMI_TXN2<5> UMI_TXP3<5> UMI_TXN3<5>

+VDDAN_11_PCIE

1 1

2 2

VGA

WLAN

LAN

3 3

LAN

4 4

25MHZ_10PF_X3G025000DC1H

APU_CLK<7>

APU_CLK#<7>

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

APU_PCIE_RST#_C

A_RST#

UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C

PCIE_CALRP PCIE_CALRN

CLK_CALRN

CLK_LAN_25M_R

25M_X1

25M_X2

B

U2A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

B

C

HUDSON-2

PCICLK1/GPO36 PCICLK2/GPO37

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACE

CLOCK GENERATOR

LPCAPUS5 PLUS

PCICLK3/GPO38

PCICLK4/14M_OSC/GPO39

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT1#/GPO44

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LDRQ1#/CLK_REQ6#/GPIO49

SERIRQ/GPIO48

DMA_ACTIVE#

S5_CORE_EN

INTRUDER_ALERT#

VDDBT_RTC_G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

PCICLK0

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

GNT0#

CLKRUN#

LOCK#

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

RTCCLK

32K_X1

32K_X2

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28

APU_PROCHOT#_R

E26

APU_PWRGD_R

G26 F26

H7 F1 F3 E6

+RTCBATT_R

G2

32K_X1

G4

32K_X2

C

GPIO31

PCI_CLK1 <14>

PCI_CLK3 <14> PCI_CLK4 <14>

+3VS

12

@

R218

10K_0402_5%

12

@

R217

10K_0402_5%

PCI_AD23 <14> PCI_AD24 <14> PCI_AD25 <14> PCI_AD26 <14> PCI_AD27 <14>

T11T11

T12T12

1 2

R71 22_0402_5%R 71 22_0402_5%

1 2

R73 0_0402_5%@R73 0_0402_5%@

LPC_CLK1 <14> LPC_AD0 <25,31> LPC_AD1 <25,31> LPC_AD2 <25,31> LPC_AD3 <25,31> LPC_FRAME# <25,31>

SERIRQ <31>

1 2

R75 0_0402_5%@R75 0_0402_5%@

1 2

R76 0_0402_5%R76 0_0402_5%

APU_RST# <7>

RTC_CLK <14,31>

Compal Secret Data

2012/01/15 2013/01/15

Compal Secret Data

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

APU_PCIE_RST #: Reset PCIE device on APU

APU_PCIE_RST#_C

BT_OFF# <25>

+3VS

12

W=20mils

1

C159

2

1U_0402_6.3V6K

Deciphered Date

D

MC74VHC1G08DFT2G SC70 5P

R60

1 2

33_0402_5%

@

C157

@

UMA@

R146

R146 10K_0402_5%

10K_0402_5%

BOARD Config.

PX@

R152

R152 10K_0402_5%

10K_0402_5%

CLK_PCI_EC <14,31> CLK_PCI_DB <25>

ALLOW_STOP <7> APU_PROCHOT# <7> APU_PWRGD <43,7>

1 2

R78 510_0402_5%R78 510_0402_5%

Need OPEN

for Clear CMOS

D

1

2

150P_0402_50V8J

GPIO31

+RTCBATT

12

R64

@

1 2

8.2K_0402_5%

0

1

CLRP1

@CLRP1

@

SHORT PADS

E

+3VALW

C156

@C156

@

1 2

0.1U_0402_16V4Z

5

2

P

B

Y

1

A

G

3

@

1 2

@ R65

@

0_0402_5%

4

U1

R65

APU_PCIE_RST# < 15,25>

VGA,LAN,WLAN,Cardreader

12

R62

R62 0_0402_5%

0_0402_5%

PLT_RST# <26,31>

EC

Function

PX5

UMA

18P_0402_50V8J

32K_X1

32.768KHZ_12.5PF_CM31532768DZFT

32K_X2

12

Y1

Close to HUDSON-M3

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RT C

VAUS5 LA9001P M/B

1 2

C158

12

R79

20M_0402_5%

1 2

C161

18P_0402_50V8J

of

10 50Friday, May 25, 2012

E

0.3

www.qdzbwx.com

A

U2B

SATA_FTX_C_DRX_P0<25>

SSD

1 1

2 2

3 3

4 4

HDD

+AVDD_SATA

SATA_FTX_C_DRX_N0<25>

SATA_FRX_C_DTX_N0<25> SATA_FRX_C_DTX_P0<25>

SATA_FTX_C_DRX_P1<29> SATA_FTX_C_DRX_N1<29>

SATA_FRX_C_DTX_N1<29> SATA_FRX_C_DTX_P1<29>

1 2

R94 1K_0402_1%R 94 1K_0402_1%

1 2

R95 931_0402_1%R95 931_0402_1%

1 2

R97 10K_0402_5%R97 10K_0402_5%

+3VS

BT_DISABLE#<25>

WL_OFF#<25>

SATA_CALRP

SATA_CALRN

BT_DISABLE# WL_OFF#

1 2

R214 10K_0402_5%R214 10K_0402_5%

1 2

R105 10K_0402_5%R105 10K_0402_5%

1 2

R108 10K_0402_5%R108 10K_0402_5%

1 2

R109 10K_0402_5%R109 10K_0402_5%

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

T13T13

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

B

HUDSON-2

SERIAL ATA

HW MONITOR

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_RXCTL/RXDV

GBE_TXCTL/TXEN

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD/GPIO75

SD_WP/GPIO76

GBE_RXCLK

GBE_RXERR

GBE_PHY_PD

VGA_GREEN

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

VIN0/GPIO175

VIN1/GPIO176

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

VGA_RED

VGA_BLUE

AUXCAL

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

V6 V5 V3 T6 V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

GBE_PHY_INTR

SPI_SO SPI_SI SPI_CLK_FCH SPI_SB_CS0# SPI_WP#

AUXCAL

C

1 2

R93 10K_0402_5%R93 10K_0402_5%

1 2

R96 715_0402_1%@R96 715_0402_1%@

1 2

R98 100_0402_1%

@

1 2

R99 10K_0402_5%R99 10K_ 0402_5%

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

@

R101 10K_0402_5%

1 2

@

R102 10K_0402_5%

1 2

@

R103 10K_0402_5%

1 2

@

R104 10K_0402_5%

1 2

@

R106 10K_0402_5%

1 2

R107 10K_0402_5%R107 10K_0402_5%

Need to enable internal pull down to le ave unconnected

+3VALW

+VDDAN_11_ML

D

+3VALW

1 2

R92

@R92

@

1 2

R81

@R81

@

1 2

R83

SPI_SB_CS0# SPI_SO SPI_WP#

Mount R92, R81 if support FCH share ROM

Place them close to ball within 1"

4MB SPI ROM

SPI_SB_CS0#

10K_0402_5%

SPI_WP#

10K_0402_5%

SPI_HOLD#

10K_0402_5%

U3

1

CS#

2

SO/SIO1

3

WP#

4

GND

W25Q32BVSSIG SOIC 8P SPI ROM

VCC

HOLD#

SCLK

SI/SIO0

8 7 6 5

+3VALW

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_FCH SPI_SI

C164

1 2

E

22P_0402_50V8J

SPI_CLK_FCH

R82

33_0402_5%

@

C163

12

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

VAUS5 LA9001P M/B

11 50Friday, May 25, 2012

E

0.3

A

+3VALW

R110

R110 10K_0402_5%

10K_0402_5%

@

1 2

SYS_RESET#

1 1

2 2

3 3

4 4

+3VALW

For FCH internal debug use

1 2

R114 2.2K_0402_5%@R114 2.2K_0402_5%@

1 2

R115 2.2K_0402_5%@R115 2.2K_0402_5%@

1 2

R116 2.2K_0402_5%@R116 2.2K_0402_5%@

+3VALW

1 2

R119 10K_0402_5%R119 10K_0402_5%

1 2

R121 10K_0402_5%R121 10K_0402_5%

1 2

R122 10K_0402_5%@R122 10K_0402_5%@

1 2

R123 10K_0402_5%@R123 10K_0402_5%@

1 2

R124 10K_0402_5%@R124 10K_0402_5%@

1 2

R127 10K_0402_5%@R127 10K_0402_5%@

1 2

R128 10K_0402_5%@R128 10K_0402_5%@

1 2

R130 10K_0402_5%@R130 10K_0402_5%@

1 2

R132 10K_0402_5%@R132 10K_0402_5%@

1 2

R133 100K_0402_5%@R133 100K_0402_5%@

1 2

R134 10K_0402_5%@R134 10K_0402_5%@

1 2

R148 2.2K_0402_5%R148 2.2K_0402_5%

1 2

R149 2.2K_0402_5%R149 2.2K_0402_5%

+3VS

1 2

R141 2.2K_0402_5%R141 2.2K_0402_5%

1 2

R142 2.2K_0402_5%R142 2.2K_0402_5%

1 2

R143 10K_0402_5%R143 10K_0402_5%

1 2

R144 8.2K_0402_5%R144 8.2K_0402_5%

1 2

R145 8.2K_0402_5%R145 8.2K_0402_5%

1 2

R150 2.2K_0402_5%R150 2.2K_0402_5%

1 2

R151 10K_0402_5%@R151 10K_0402_5%@

1 2

R154 10K_0402_5%@R154 10K_0402_5%@

1 2

R155 10K_0402_5%R155 10K_0402_5%

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB_OC5#

USB_OC4#

USB_OC6#

USB_OC7#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SCLK1

FCH_SDATA1

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

PEG_CLKREQ#_R

change back to always mount

FCH Chip FCH_SEL

A60M2

Low

TEST0

TEST1

TEST2

PEG_CLKREQ#<16>

HDA_BITCLK_AUDIO<30> HDA_SDOUT_AUDIO<30>

HDA_SDIN0<30>

HDA_SYNC_AUDIO<30>

HDA_RST_AUDIO#<30>

DDR3L_EN#<40>

PXS_RST#<15> PXS_PWREN<17,39,42>

13

D

VGA_GATE#<31>

2

G

S

AMD only support FP2 + A70M3, @ FCH_SEL function

A70M3 High

Before setting (for reference)

A

B

PCIE_RST2 : Reset PCIE device on Hudson2/3

EC_LID_OUT#<31>

PM_SLP_S3#<31> PM_SLP_S5#<31> PBTN_OUT#<31> FCH_PWRGD<31,43>

GATEA20<31>

KBRST#<31> EC_SCI#< 31> EC_SMI#<31>

FCH_PCIE_WAKE#<25,26>

H_THERMTRIP#<7>

EC_RSMRST#<31>

LAN_CLKREQ#<26>

FCH_SPKR<30> FCH_SCLK0<25,9> FCH_SDATA0<25,9> FCH_SCLK1<32> FCH_SDATA1<32>

WLAN_CLKREQ#<25>

VGA_PWRGD<15,42>

R117 0_0402_5%@R117 0_0402_5%@

12

change back to @

USB_OC1#<32> USB_OC0#<33>

1 2

R125 33_0402_5%R 125 33_0402_5%

1 2

R126 33_0402_5%R 126 33_0402_5%

1 2

R129 33_0402_5%R 129 33_0402_5%

1 2

R131 33_0402_5%R 131 33_0402_5%

PX@

12

R1360_0402_5%

12

R1380_0402_5%

PX@

Q6

2N7002K_SOT23-3

R112

10K_0402_5%

R113

10K_0402_5%

B

+3VALW

@

12

FCH_SEL

12

T14T14

FCH_PWRGD

TEST0 TEST1 TEST2

SYS_RESET#

WD_PWRGD

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1

PEG_CLKREQ#_R

USB_OC7# USB_OC6# USB_OC5# USB_OC4# USB_OC3# USB_OC2# USB_OC1# USB_OC0#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

T15T15 T16T16

12

R1530_0402_5% R1530_0402_5%

12

R1470_0402_5% @ R1470_0402_5% @

C

U2D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/01/15 2013/01/15

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196 EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

D

G8

B9

USB_RCOMP

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12

USB30_P10

K13

USB30_N10

B11 D11

E10 F10

C10

USB20_P7

A10

USB20_N7

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

J16

USB30_TX_P0

H16

USB30_TX_N0

J15

USB30_RX_P0

K15

USB30_RX_N0

H19

1 2

R135 10K_0402_5%R135 10K_0402_5%

G19

1 2

R137 10K_0402_5%R137 10K_0402_5%

G22

1 2

R139 10K_0402_5%R139 10K_0402_5%

G21

1 2

R140 10K_0402_5%R140 10K_0402_5%

E22 H22 J22

EC_PWM2

H21

K21

FCH_SEL

K22 F22 F24 E24 B23

Left USB port 3.0 & 2.0 co-lay

C24 F18

USB20_N7

USB20_P7

USB30_N10

USB30_P10

D

E

1 2

R111 11.8K_0402_1%R111 11.8K_0402_1%

Hudson-M3 OHCI(DEV-20,FUN-5)

Hudson-M3

USB30-Left1

USB20-Left1

USB20_P5 <32> USB20_N5 <32>

USB20_P3 <23> USB20_N3 <23>

USB20_P2 <25> USB20_N2 <25>

USB20_P1 <32> USB20_N1 <32>

USB20_P0 <32> USB20_N0 <32>

1 2

R118 1K_0402_1%R118 1K_0402_1%

1 2

R120 1K_0402_1%R120 1K_0402_1%

USB30_TX_P0 <33> USB30_TX_N0 <33>

USB30_RX_P0 <33> USB30_RX_N0 <33>

@

R1606 0_0402_5%

@

R1607 0_0402_5%

R1610 0_0402_5%R1610 0_0402_5%

R1611 0_0402_5%R1611 0_0402_5%

Title

Size Document Number Rev

Custom

Date: Sheet of

Card Reader

Int. Camera

WLAN

USB20-Right2

USB20-Right1

USB30-Left1

USB3.0 and USB2.0 Option

EC_PWM2 <14>

12

strap pin

USB20_LN

USB20_LP

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

VAUS5 LA9001P M/B

XHCI(DEV-16,FUN-0) XHCI(DEV-16,FUN-1)

Hudson-M3 OHCI(DEV-19,FUN-0) EHCI(DEV-19,FUN-2)

Hudson-M3 OHCI(DEV-18,FUN-0) EHCI(DEV-18,FUN-2)

+FCH_VDD_11_SSUSB_S

Hudson-M3 XHCI(DEV-16,FUN-0) XHCI(DEV-16,FUN-1)

USB20_LN <33>

USB20_LP <33>

E

0.3

12 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

B

C

D

E

+3VS

1 1

+FCH_VDDAN_33_DAC

+3VS +FCH_VDDAN_33_DAC

FBMA-L11-201209-221LMA30T_0805

2 2

+3VALW

+VDDAN_33_USB

3 3

+3VS

4 4

L2

1 2

MBK1608221YZF_2P

220 ohm

1 2

R158 0_0402_5%@R158 0_0402_5%@

L4

1 2

220 ohm

L6

1 2

MBK1608221YZF_2P

220 ohm

L91

1 2

MBK1608221YZF_2P

220 ohm

L12

1 2

MBK1608221YZF_2P

220 ohm

L13

1 2

MBK1608221YZF_2P

220 ohm

+VDDPL_33_SYS

C165

1

2

+VDDPL_33_MLDAC

C175

1

2

30mA

C194

2.2U_0603_6.3V6K

C194

2.2U_0603_6.3V6K

1

2

+VDDPL_33_SSUSB_S

C204

2.2U_0402_6.3V6M

C204

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C211

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

A

C166

0.1U_0402_16V7K

C166

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

0.1U_0402_16V7K

C176

1

2

LDO_CAP: Internally generated 1.8V supply for the RGB outputs

+1.1VS

C195

0.1U_0402_16V4Z

C195

0.1U_0402_16V4Z

1

2

+3VALW

C205

0.1U_0402_16V7K

C205

0.1U_0402_16V7K

1

2

C212

0.1U_0402_16V7K

C212

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

C218

2.2U_0402_6.3V6M

C218

2.2U_0402_6.3V6M

1

2

C225

2.2U_0402_6.3V6M

C225

2.2U_0402_6.3V6M

1

2

+1.1VALW

1 2

R157 0_0603_5%@R157 0_0603_5%@

+3VS

L5

R160 0_0402_5%@R160 0_0402_5%@

R161 0_0402_5%@R161 0_0402_5%@

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

R163 0_0402_5%@R163 0_0402_5%@

R164 0_0603_5%@R164 0_0603_5%@

+VDDPL_33_MLDAC

L3

1 2

MBK1608221YZF_2P

220 ohm/2A

1 2

FBMA-L11-201209-221LMA30T_0805

220 ohm/2A

AMD strong recommended

L81

1 2

MBK1608221YZF_2P

220 ohm

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

L101

1 2

MBK1608221YZF_2P

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

L141

12

42 ohm/4A

R170 0_0603_5%@R170 0_0603_5%@

R172 0_0603_5%@R172 0_0603_5%@

1 2

C199

1

2

C207

1

2

C213

1

2

1 2

B

22U_0603_6.3V6M

C172

C171

1

2

+VDDPL_33_SYS

C187

1

2

R167 0_0402_5%@R167 0_0402_5%@

10U_0603_6.3V6M

C200

1

2

C208

0.1U_0402_16V7K

C208

0.1U_0402_16V7K

2.2U_0402_6.3V6M

1

2

C214

0.1U_0402_16V7K

C214

0.1U_0402_16V7K

10U_0603_6.3V6M

1

2

C219

1

2

C226

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

+FCH_VDDAN_33_DAC

+VDDPL_33_SSUSB_S

C183 2.2U_0603_6.3V6K

4.7U_0402_6.3V6M

C188

+VDDAN_33_USB

C201

1

2

+VDDAN_11_USB_S+VDDAN_11_USB_S

C244

1

2

+VDDCR_11V_USB

C215

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

+VDDCR_11_SSUSB

10U_0603_6.3V6M

0.1U_0402_16V7K

C173

1

2

+VDDPL_33_SYS

+VDDPL_33_DAC

+VDDPL_33_ML

@

1 2

C189

0.1U_0402_16V7K

1

2

1U_0402_6.3V6K

C202

0.1U_0402_16V7K

C220

1

2

C227

1

2

0.1U_0402_16V7K

C174

1

2

+VDDPL_11_DAC

+VDDAN_11_ML

0.1U_0402_16V7K

1

2

12

C203

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

C221

0.1U_0402_16V7K

C221

0.1U_0402_16V7K

1

2

C228

1U_0402_6.3V6K

1

2

U2C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21807-A13-HUDSON-M3_FCBGA656

0.1U_0402_16V7K

C229

0.1U_0402_16V7K

C229

0.1U_0402_16V7K

A70MR1@

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM _S

VDDIO_AZ_S

2012/01/15 2013/01/15

1007mA

C177

T14 T17

1

T20 U16 U18

2

V14 V17 V20 Y17

340mA

H26 J25

C178

K24 L22

1

M22 N21 N22

2

P22

1088mA

AB24 Y21 AE25

C184

AD24 AB23

1

AA22 AF26 AG27

2

1337mA

AA21 Y20 AB21

C190

AB22 AC22

1

AC21 AA20 AA18

2

AB20 AC19

59mA

N18 L19

C196

M18 V12

1

V13 Y12 Y13

2

W11

5mA

G24

C206

1

2

187mA

N20 M20

C209

1

2

70mA

J24

C216

1

2

12mA

M8

C222

1

@

2

26mA

AA4

Compal Secret Data

Deciphered Date

+VCC_VDDCR_11

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

C167

0.1U_0402_16V7K

1

2

+1.1VS_CKVDD

C179

0.1U_0402_16V7K

C179

0.1U_0402_16V7K

1

2

+VDDAN_11_PCIE

C185

1U_0402_6.3V6K

C185

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

C191

1U_0402_6.3V6K

C191

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

+VDDIO_33_S

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

C197

1U_0402_6.3V6K

1

2

+VDDXL_3.3V

2.2U_0402_6.3V6M

+VDDCR_1.1V

C210

1U_0402_6.3V6K

C210

1U_0402_6.3V6K

1

2

+VDDPL_11_SYS_S

0.1U_0402_16V7K

C217

2.2U_0402_6.3V6M

1

2

+VDDAN_33_HWM

C223

0.1U_0402_16V7K@C223

0.1U_0402_16V7K

2.2U_0402_6.3V6M@C222

2.2U_0402_6.3V6M

1

@

2

+VDDIO_AZ

C168

1U_0402_6.3V6K

C168

1U_0402_6.3V6K

C169

1

2

C180

1U_0402_6.3V6K

C180

1U_0402_6.3V6K

C181

1

2

+VDDAN_11_PCIE

C186

22U_0603_6.3V6M

C186

22U_0603_6.3V6M

1

2

C192

1U_0402_6.3V6K

C192

1U_0402_6.3V6K

C193

1

2

C198

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

1

2

1 2

C224 2.2U_ 0402_6.3V6MC224 2.2U_0402_6.3V6M

D

C170

1U_0402_6.3V6K

1

2

+1.1VS_CKVDD

C182

1U_0402_6.3V6K

1

2

+AVDD_SATA

22U_0603_6.3V6M

1

2

R166 0_0402_5%@R166 0_0402_5%@

R168 0_0603_5%@R168 0_0603_5%@

R169 0_0402_5%@R169 0_0402_5%@

R171 0_0402_5%@R171 0_0402_5%@

1 2

R156 0_0805_5%R156 0_0805_5%

10U_0603_6.3V6M

42ohm @ 100MHz

1 2

R159 0_0603_5%@R159 0_0603_5%@

22U_0603_6.3V6M

42ohm @ 100MHz

1 2

R162 0_0805_5%@R162 0_0805_5%@

42ohm @ 100MHz

1 2

R165 0_0805_5%@R165 0_0805_5%@

1 2

L7

1 2

MBK1608221YZF_2P

220 ohm

1 2

L111

1 2

MBK1608221YZF_2P

220 ohm

1 2

+1.1VS

+3VALW

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wake is supported; o therwise, tie to +3.3V_S0 rail. Hudson-2 design s: Tie to +3.3 V_S0 rail.

+1.1VALW

+3VALW

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to +3.3/1.5V_S5 rail if Wake on Ring is supported

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

VAUS5 LA9001P M/B

13 50Friday, May 25, 2012

E

0.3

www.qdzbwx.com

A

B

C

D

E

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

U2E

1 1

2 2

3 3

U2E

HUDSON-2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

21807-A13-HUDSON-M3_FCBGA656

A70MR1@

M13 M16 M21 M25

N11 N13 N23 N24

R11 R25 R28

H25

A3

A33

B7

B13

D9

D13

E5 E12 E16 E29

F7

F9 F11 F13 F16 F17 F19 F23 F25 F29

G6 G16 G32 H12 H15 H29

J6

J9

J10 J13 J28 J32

K7 K16 K27 K28

L6 L12 L13 L15 L16 L21

N6

P12 P18 P20 P21 P31 P33

R4

T11 T16 T18

N8

K25

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<10>

PCI_CLK3<10>

PCI_CLK4<10>

CLK_PCI_EC<10,31>

LPC_CLK1<10 >

EC_PWM2<12>

RTC_CLK<10,31>

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

USE PCI

PULL

PLL

HIGH

DEFAULT

BYPASS

PULL

PCI PLL

LOW

PCI_AD27<10>

PCI_AD26<10>

PCI_AD25<10>

PCI_AD24<10>

PCI_AD23<10>

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

12

@

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

R180 2.2K_0402_5%@R180 2.2K_0402_5%

12

@

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R173 10K_0402_5%R173 10K_0402_5%

R174 10K_0402_5%@R174 10K_0402_5%

R175 10K_0402_5%@R175 10K_0402_5%

12

@

R186 10K_0402_5%R186 10K_0402_5%

R185 10K_0402_5%@R185 10K_0402_5%

R187 10K_0402_5%R187 10K_0402_5%

12

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

R182 2.2K_0402_5%@R182 2.2K_0402_5%

R181 2.2K_0402_5%@R181 2.2K_0402_5%

12

@

EC ENABLED

EC DISABLED

DEFAULT

R176 10K_0402_5%@R176 10K_0402_5%

12

@

R188 10K_0402_5%R188 10K_0402_5%

12

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

R183 2.2K_0402_5%@R183 2.2K_0402_5%

12

@

12

@

R184 2.2K_0402_5%@R184 2.2K_0402_5%

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

R177 10K_0402_5%R177 10K_0402_5%

R189 10K_0402_5%@R189 10K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

+3VALW+3VALW+3VALW+ 3VALW+3V S+3VS+3VS

R179 10K_0402_5%R179 10K_0402_5%

R178 10K_0402_5%@R178 10K_0402_5%

12

@

R191 2.2K_0402_5%@R191 2.2K_0402_5%

R190 2.2K_0402_5%R190 2.2K_0402_5%

12

@

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

www.qdzbwx.com

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

VAUS5 LA9001P M/B

14 50Friday, May 25, 2012

E

0.3

A

B

C

D

E

PCIE_CTX_GRX_P[7..0]<5>

PCIE_CTX_GRX_N[7..0]<5>

1 1

2 2

3 3

CLK_PCIE_VGA<10> CLK_PCIE_VGA#<10>

VGA_PWRGD<12,42>

PCIE_CTX_GRX_P[7..0]

PCIE_CTX_GRX_N[7..0]

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 0_0402_5%

@

12

R299

PX@R299

PX@

10K_0402_5%

GPU_RST#

12

PX@

R399

R399 100K_0402_5%

100K_0402_5%

U8A

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

PCIE_RX8P

U31

PCIE_RX8N

U29

PCIE_RX9P

T28

PCIE_RX9N

T30

PCIE_RX10P

R31

PCIE_RX10N

R29

PCIE_RX11P

P28

PCIE_RX11N

P30

PCIE_RX12P

N31

PCIE_RX12N

N29

PCIE_RX13P

M28

PCIE_RX13N

M30

PCIE_RX14P

L31

PCIE_RX14N

L29

PCIE_RX15P

K30

PCIE_RX15N

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

12

N10

PWRGOOD

AL27

PERSTB

216-0774207-A11ROB_FCBGA631

SXTR1@

PCI EXPRESS INTERFACE

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

CALIBRATION

PCIE_CALRP

PCIE_CALRN

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

AH30

PCIE_CRX_C_GTX_P0

AG31

PCIE_CRX_C_GTX_N0

AG29

PCIE_CRX_C_GTX_P1

AF28

PCIE_CRX_C_GTX_N1 PC IE_CRX_GTX_N1

AF27

PCIE_CRX_C_GTX_P2

AF26

PCIE_CRX_C_GTX_N2

AD27

PCIE_CRX_C_GTX_P3

AD26

PCIE_CRX_C_GTX_N3 PC IE_CRX_GTX_N3

AC25

PCIE_CRX_C_GTX_P4

AB25

PCIE_CRX_C_GTX_N4 PC IE_CRX_GTX_N4

Y23

PCIE_CRX_C_GTX_P5

Y24

PCIE_CRX_C_GTX_N5 PC IE_CRX_GTX_N5

AB27

PCIE_CRX_C_GTX_P6

AB26

PCIE_CRX_C_GTX_N6

Y27

PCIE_CRX_C_GTX_P7

Y26

PCIE_CRX_C_GTX_N7 PC IE_CRX_GTX_N7

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

PX@

Y22

AA22

PX@

1 2

PCIE_CRX_GTX_P[7..0] <5>

PCIE_CRX_GTX_N[7..0] <5>

R2981.27K_0402_1%

R3002K_0 402_1% PX@ R3002K_0402_1% PX@

+1.0VGS

12

C2580.1U_0402_16V7K PX@C 2580.1U_0402_16V7K PX@

12

C2590.1U_0402_16V7K PX@C 2590.1U_0402_16V7K PX@

12

C2770.1U_0402_16V7K

12

C2760.1U_0402_16V7K PX@C 2760.1U_0402_16V7K PX@

12

C2560.1U_0402_16V7K

12

C2570.1U_0402_16V7K PX@C 2570.1U_0402_16V7K PX@

12

C2750.1U_0402_16V7K

12

C2740.1U_0402_16V7K PX@C 2740.1U_0402_16V7K PX@

12

C2550.1U_0402_16V7K

12

C2540.1U_0402_16V7K PX@C 2540.1U_0402_16V7K PX@

12

C2730.1U_0402_16V7K

12

C2720.1U_0402_16V7K PX@C 2720.1U_0402_16V7K PX@

12

C2530.1U_0402_16V7K

12

C2520.1U_0402_16V7K PX@C 2520.1U_0402_16V7K PX@

12

C2710.1U_0402_16V7K

12

C2700.1U_0402_16V7K PX@C 2700.1U_0402_16V7K PX@

PX@

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_P4

PCIE_CRX_GTX_P5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7

U8F

LVDS CONTROL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3N

LVTMDP

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

216-0774207-A11ROB_FCBGA631

SXTR1@

VARY_BL

DIGON

TXOUT_U3P

TXOUT_L3P TXOUT_L3N

AB11 AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

LVDS

R395 0_0402_5%@R395 0_0402_5%@

PXS_RST#<12>

APU_PCIE_RST#<10,25>

2

1

12

+3VGS

5

U16

P

B

4

Y

A

G

PX@

3

MC74VHC1G08DFT2G SC70 5P

GPU_RST#

PCIE LANE

www.qdzbwx.com

4 4

U8

SXTR3@U8

SXTR3@

S IC 216-0809024 A11 SEYMOUR XT S3 C38!

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

SeymourXT-S3 PCIE/LVDS

VAUS5 LA9001P M/B

15 50Friday, May 25, 2012

E

0.3

A

+1.8VGS

L8

BLM15BD121SN1D_0402

1 1

2 2

+3VGS

3 3

4 4

XTALIN

1

2

BLM15BD121SN1D_0402

+1.0VGS

BLM15BD121SN1D_0402

1 2

R321 10K_0402_5%PX@ R321 10K_0402_5%PX@

1 2

R322 10K_0402_5%PX@ R322 10K_0402_5%PX@

1 2

R323 10K_0402_5%PX@ R323 10K_0402_5%PX@

1 2

R324 10K_0402_5%PX@ R324 10K_0402_5%PX@

+1.8VGS +DPLL_PVDD

BLM15BD121SN1D_0402

+1.8VGS

BLM18AG121SN1D_0603

Had confirm with I+A & A+A FAE & check list is to use 1M

R337 1M_0402_5%PX@R337 1M_0402_5%PX@

Y6

4

NC

1

OSC

27MHZ 10PF 20PPM X3G027000DA1H

PX@

C341

8.2P_0402_50V8D

12

PX@

L14

PX@

L49

PX@

OSC

NC

L9

PX@

12

L17

3

2

1

C304

@

2

12

1

C307

@

2

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS

GPIO26_TCK

1

C323

PX@

2

10U_0603_6.3V6M

12

1

C330

PX@

2

12

1

C334

PX@

2

XTALOUT

10U_0603_6.3V6M

PX@

10U_0603_6.3V6M

+DPC_VDD18

1

C305

@

2

+DPC_VDD10

1

C346

@

2

+DPLL_PVDD

1

C324

2

1U_0402_6.3V4Z

+DPLL_VDDC

1

C331

PX@

2

+TSVDD

1

C335

2

1

PX@

C350

8.2P_0402_50V8D

2

+DPC_VDD18

1

C306

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+DPC_VDD10

1

C347

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

CH751H-40PT_SOD323-2 @

ACIN<31,37>

+3VGS

12

R331

10K_0402_5%

@

PEG_CLKREQ#<12>

1

C325

PX@

2

0.1U_0402_10V6K

+DPLL_VDDC+1.0VGS

1

C332

PX@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+TSVDD

1

C336

PX@

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

change Y6 follow QAWYA (SJ10000FH00)

A

GPU_VID0<42>

GPU_VID1<42>

+1.8VGS

PX@

R329 499_0402_1%

R332 249_0402_1%

C322 0.1U_0402_10V6K

PX@

+3VGS

+TSVDD

B

VRAM_ID2<20> VRAM_ID1<20> VRAM_ID0<20>

+DPC_VDD18

+DPC_VDD10

D4

21

R319 10K_0402_5%

T64T64

1 2

R326

5.11K_0402_1%PX@

1 2

R613

4.7K_0402_5%

@

12

PX@

12

+DPLL_PVDD

+DPLL_VDDC

PX@

R335 0_0402_5%

R333 0_0402_5%

PX@

1 2

R334 2.61K_0402_5%

+TSVDD

B

VRAM_ID2 VRAM_ID1 VRAM_ID0

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

GPU_VID0

T63T63

PX@

1 2

GPU_VID1

T70T70

PEG_CLKREQ#

GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO

TEST_EN

+VREFG_GPU

+DPLL_PVDD

+DPLL_VDDC

XTALIN XTALOUT

12 12

U8B

Y11

DVCLK

AE9

DVCNTL_0

L9

DVCNTL_1

N9

DVCNTL_2

AE8

DVDATA_12

AD9

DVDATA_11

AC10

DVDATA_10

AD7

DVDATA_9

AC8

DVDATA_8

AC7

DVDATA_7

AB9

DVDATA_6

AB8

DVDATA_5

AB7

DVDATA_4

AB4

DVDATA_3

AB2

DVDATA_2

Y8

DVDATA_1

Y7

DVDATA_0

W6

DPC_PVDD

V6

DPC_PVSS

AC6

DPC_VDD18#1

AC5

DPC_VDD18#2

AA5

DPC_VDD10#1

AA6

DPC_VDD10#2

U1

DPC_VSSR#1

W1

DPC_VSSR#2

U3

DPC_VSSR#3

Y6

DPC_VSSR#4

AA1

DPC_VSSR#5

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

TESTEN_LEGACY

T65T65

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AB16

PX_EN

AC16

VREFG

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

216-0774207-A11ROB_FCBGA631

SXTR1@

PLL/CLOCK

THERMAL

C

AF2

TXCAP_DPA3P

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TX0P_DPC2P

TX0M_DPC2N

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

DPC_CALR

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI

VSS1DI

COMP

H2SYNC V2SYNC

VDD2DI

VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDC6CLK

DDC6DATA

C

AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

1 2

J8

R307

150_0402_1%

PX@

AM26

T55T55

R

AK26

RB

AL25

T56T56

G

AJ25

GB

AH24

T57T57

B

AG25

BB

AH26

VGA_HSYNC

AJ27

VGA_VSYNC

PX@

1 2

AD22

R318

R318 499_0402_1%

499_0402_1%

AG24

+AVDD

AE22

AE23

+VDD1DI

AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13

T53T53

AJ13

T54T54

AD19 AC19

AE20

AE17

AE19

@

1 2

AG13

R330

R330 715_0402_1%

715_0402_1%

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AD20 AC20

AE16 AD16

AC1

T58T58

AC3

T59T59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/01/15 2013/01/15

Compal Secret Data

TXCAM_DPA3N

DPA

DVO

DPA

DVO

TXCBM_DPB3N

DPB

DPC

TXCCP_DPC3P TXCCM_DPC3N

DAC1

DAC2

DDC/AUX

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX5P

DDCDATA_AUX5N

D

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

VGA_HSYNC VGA_VSYNC

+AVDD

+VDD1DI

PX@R327

PX@

10K_0402_5%

VGA_SMB_CK2_R

VGA_SMB_DA2_R

Deciphered Date

D

+AVDD

R327

PX@

R339 10K_0402_5%@R 339 10K_0402_5%@ R338 10K_0402_5%PX@R338 10K_0402_5%PX@ R325 10K_0402_5%PX@R325 10K_0402_5%PX@ R320 10K_0402_5%PX@R320 10K_0402_5%PX@

R313 10K_0402_5%@R 313 10K_0402_5%@ R314 10K_0402_5%@R 314 10K_0402_5%@

R315 10K_0402_5%PX@R315 10K_0402_5%PX@ R316 10K_0402_5%@R 316 10K_0402_5%@ R317 10K_0402_5%@R 317 10K_0402_5%@

R548 10K_0402_5%@R 548 10K_0402_5%@ R549 10K_0402_5%@R 549 10K_0402_5%@

1

C397

PX@

2

0.1U_0402_10V6K

1

C313

2

0.1U_0402_10V6K

12

1 2 1 2

1 2

BLM15BD121SN1D_0402

1

C401

C400

PX@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

1 2

BLM15BD121SN1D_0402

1

C396

C315

PX@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

12

R328

PX@R328

PX@

10K_0402_5%

1

DMN66D0LDW-7_SOT363-6

12 12 12 12

12 12

12 12 12

PX@

2

PX@Q64A

PX@

L10

L11

Q64A

E

+3VGS

+1.8VGS

+3VGS+3VGS

6

5

34

Q64B

PX@Q64B

PX@

DMN66D0LDW-7_SOT363-6

Title

Size Document Number Rev

C

Date: Sheet of

EC_SMB_CK2 <28,31>

EC_SMB_DA2 <28,31>

Compal Electronics, Inc.

SeymourXT-S3 Main Gen/MSIC

VAUS5 LA9001P M/B

E

0.3

16 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

1 1

B

C

D

E

+3.3VS TO +3.3VGS

2 2

PX@

1

C1139

10U_0603_6.3V6M

+5VALW

PXS_PWREN<12,39,42>

3 3

4 4

PXS_PWREN

+1.5V_IO TO +1.5VGS

100K_0402_5%

PXS_PWREN

R276

PX@ R276

PX@

100K_0402_5%

PX@

R270

20K_0402_5%

PX@

R286

5

12

2

13

D

2

G

2N7002K_SOT23-3

S

+3VALW

12

34

PX@

Q69B

Q69B DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

Q27

+3VS +3VGS

PMV65XP_SOT23-3

D

S

D

S

13

G

PX@

2

PX@

R271

20K_0402_5%

1

C1143

0.1U_0402_16V4Z

PX@

10U_0603_6.3V6M

0.1U_0402_16V4Z

2

C1145

PX@

+VSB

2

Q30

PXS_PWREN#

PX@C344

PX@

10U_0603_6.3V6M

PXS_PWREN#

PX@C1143

PX@

+1.5V_IO

U12 AO4430L_SO8

AO4430L_SO8

8 7

1

6 5

2

PX@

R275

R275 20K_0402_5%

20K_0402_5%

R278

1 2

6

43K_0402_5%

PX@

Q69A

Q69A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

1

PX@U12

PX@

2

1 2

R283

@ R283

@

0_0402_5%

4

R280

R280 0_0402_5%

0_0402_5%

@

1 2

12

+1.5VGS

1 2 3

C344

C345

PX@C345

PX@

1U_0402_6.3V6K

1

PX@

C1146

C1146 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PXS_PWREN#

12

C1149

0.1U_0402_25V6

2

G

PX@C1149

PX@

12

R284

@R284

@

470_0603_5%

Q35

@

Q35

@

13

D

S

2N7002K_SOT23-3

12

R285

@ R285

@ 1 2

0_0402_5%

C1147

PX@C1147

PX@

1U_0402_6.3V6K

2

G

12

@

R274

R274 470_0603_5%

470_0603_5%

13

D

@

Q31

Q31 2N7002K_SOT23-3

2N7002K_SOT23-3

S

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

SeymourXT-S3 BACO Power

VAUS5 LA9001P M/B

E

17 50Friday, May 25, 2012

0.3

A

B

C

D

E

+1.8VGS

@

L18

L18 0_0603_5%

0_0603_5%

PX@

1 1

2 2

3 3

PX@

L20

L20 0_0603_5%

0_0603_5%

PX@

MBK1608121YZF_0603

@

+1.0VGS

MBK1608121YZF_0603

total:440mA@LVDS

L18

total:300mA@DP

12

total:240mA@LVDS

L20

@

total:220mA@DP

12

@

1

C367

2

10U_0603_6.3V6M

1

C356

2

10U_0603_6.3V6M

1

C368

@

2

1U_0402_6.3V4Z

1

C360

@

2

1U_0402_6.3V4Z

+DPEF_VDD18

@

1

C355

2

0.1U_0402_10V6K

1

C361

2

0.1U_0402_10V6K

+DPEF_VDD18

+DPEF_VDD10

+DPEF_VDD18

+DPEF_VDD10

R463

150_0402_1%

+DPEF_VDD18

PX@R463

PX@

total:300mA

1

C357

U8G

DP A/B POWERDP E/F POWER

AG15

DPE_VDD18#1

AG16

DPE_VDD18#2

AG20

DPE_VDD10#1

AG21

DPE_VDD10#2

AG14

DPE_VSSR#1

AH14

DPE_VSSR#2

AM14

DPE_VSSR#3

AM16

DPE_VSSR#4

AM18

DPE_VSSR#5

AF16

DPF_VDD18#1

AG17

DPF_VDD18#2

AF22

DPF_VDD10#1

AG22

DPF_VDD10#2

AF23

DPF_VSSR#1

AG23

DPF_VSSR#2

AM20

DPF_VSSR#3

AM22

DPF_VSSR#4

AM24

DPF_VSSR#5

AF17

12

20mA

AG18

AF19

AG19

AF20

DPEF_CALR

DPE_PVDD DPE_PVSS

DPF_PVDD DPF_PVSS

DP PLL POWER

DPA_VDD18#1 DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

DPB_VDD18#1 DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPAB_CALR

DPA_PVDD

DPA_PVSS

DPB_PVDD

DPB_PVSS

130mA

AE11 AF11

110mA

AF6 AF7

AE1 AE3 AG1 AG6 AH5

130mA

AE13 AF13

110mA

AF8 AF9

AF10 AG9 AH8 AM6 AM8

AE10

20mA

AG8 AG7

20mA20mA

AG10 AG11

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

+DPAB_VDD10

1 2

R464

150_0402_1%

PX@

C357

@

total:220mA

C362

@

+DPAB_VDD18+DPEF_VDD18

+DPAB_VDD18

2

1

2

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

1

C358

C359

MBK1608121YZF_0603

@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

1

C364

@

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

MBK1608121YZF_0603

1 2

MBK1608121YZF_0603

@

2

0.1U_0402_10V6K

1

C363

@

2

0.1U_0402_10V6K

@

L21

L19

@

+1.8VGS+DPAB_VDD18

12

+1.0VGS

L19

L19 0_0603_5%

0_0603_5%

PX@

L21

L21 0_0603_5%

0_0603_5%

PX@

216-0774207-A11ROB_ FCBGA631

SXTR1@

www.qdzbwx.com

4 4

Security Classification

2012/01/15 2013/01/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/15 2013/01/15

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Numb er Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SeymourXT-S3 DPX Power

VAUS5 LA9001P M/B

18 50Friday, May 25, 2012

E

0.3

A

+1.5VGS

B

C

D

E

0.9A(RMS)/1.3A(Peak)

1

C365

C366

2

10U_0603_6.3V6M

PX@

L46

L46 0_0402_5%

0_0402_5%

PX@

L46

@ L46

@

1 2

L24

L24 0_0402_5%

0_0402_5%

PX@

L24

@ L24

@

1 2

L47

1 2

PX@

L48

1 2

PX@

219mA

1

C404

2

PX@

1

C429

PX@

2

1

C446

2

PX@

1

C462

2

PX@

1 1

+1.8VGS +VDDC_CT

BLM15BD121SN1D_0402

2 2

3 3

BLM15BD121SN1D_0402

1

C369

2

10U_0603_6.3V6M

1

C405

2

10U_0603_6.3V6M

PX@

1

C430

PX@

2

1U_0402_6.3V4Z

1

C447

2

10U_0603_6.3V6M

PX@

1

C454

2

10U_0603_6.3V6M

PX@

1

C370

C371

2

1U_0402_6.3V4Z

PX@

1

C422

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

0.1U_0402_10V6K

1

C449

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C463

+1.0VGS

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C374

C372

C373

2

1U_0402_6.3V4Z

PX@

+3VGS

1

C427

2

PX@

L28

1 2

BLM15BD121SN1D_0402

PX@

1

C389

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C410

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

PX@

For Seymour, PCIE_PVDD is PCIE_VDDR.

1

C456

PX@

2

1

C390

2

0.1U_0402_10V6K

PX@

1

C428

2

1U_0402_6.3V4Z

1

C464

2

10U_0603_6.3V6M

PX@

1

C381

C392

C391

2

0.1U_0402_10V6K

PX@

@

17mA

60mA

170mA

+PCIE_VDDR

+MPV18

+SPV18

+SPV10

1

C458

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

U8D

H13

VDDR1#1

H16

VDDR1#2

H19

VDDR1#3

J10

VDDR1#4

J23

VDDR1#5

J24

VDDR1#6

J9

VDDR1#7

K10

VDDR1#8

K23

VDDR1#9

K24

VDDR1#10

K9

VDDR1#11

L11

VDDR1#12

L12

VDDR1#13

L13

VDDR1#14

L20

VDDR1#15

L21

VDDR1#16

L22

VDDR1#17

LEVEL

LEVEL TRANSLATION

TRANSLATION

AA20

VDD_CT#1

AA21

VDD_CT#2

AB20

VDD_CT#3

AB21

VDD_CT#4

AA17

VDDR3#1

AA18

VDDR3#2

AB17

VDDR3#3

AB18

VDDR3#4

V12

VDDR4#1

Y12

VDDR4#2

U12

VDDR4#3

AA11

NC#1

AA12

NC#2

V11

NC#3

U11

NC#4

MEM CLK

L17

NC_VDDRHA

L16

NC_VSSRHA

PLL

AM30

PCIE_PVDD

L8

75mA

NC_MPV18

H7

50mA

SPV18

H8

100mA

SPV10

J7

SPVSS

216-0774207-A11ROB_FCBGA631

SXTR1@

MEM I/O

I/O

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

VDDC#1

CORE

VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12

POWER

VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23

BIF_VDDC#1 BIF_VDDC#2

ISOLATED

ISOLATED CORE I/O

CORE I/O

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

+PCIE_VDDR

1

C385

C387

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 M11 M12

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

C387

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C398

C399

2

1U_0402_6.3V4Z

PX@

14.1A(RMS)/19.1A(Peak)

1

C432

C431

2

1U_0402_6.3V4Z

PX@

1

C470

PX@

2

1U_0402_6.3V4Z

+VDDCI

1

C465

C460

2

PX@

1U_0402_6.3V4Z

PX@

440mA

1

C388

2

1U_0402_6.3V4Z

PX@

2000mA

1

C383

2

1U_0402_6.3V4Z

PX@

1

C415

2

1U_0402_6.3V4Z

PX@

1

C516

2

1U_0402_6.3V4Z

1

C461

2

1U_0402_6.3V4Z

PX@

1

C380

2

10U_0603_6.3V6M

PX@

1

C403

2

1U_0402_6.3V4Z

PX@

1

C416

2

1U_0402_6.3V4Z

PX@

1

C466

2

10U_0603_6.3V6M

PX@

L22

@

MBK1608121YZF_0603

1

C384

2

10U_0603_6.3V6M

PX@

1

C417

C418

2

1U_0402_6.3V4Z

PX@

PX5 only

+VGA_CORE

12

PX@

C343

C343 22U_0603_6.3V6K

22U_0603_6.3V6K

+1.0VGS

C419

PX@

+1.8VGS

12

1

2

1U_0402_6.3V4Z

PX@

1

C420

2

1U_0402_6.3V4Z

L22

L22 0_0603_5%

0_0603_5%

PX@

R745

0_0603_5%

1 2

PX@

9/28 Reserved for VGA_CORE 02/07 change to S3 size

+VGA_CORE

PX@

+VGA_CORE

1

C423

2

10U_0603_6.3V6M

1

C426

C425

C424

2

10U_0603_6.3V6M

PX@

U8E

AA27

PCIE_VSS#1

AB24

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

M6

GND#56

N11

GND#57

N12

GND#58

N13

GND#59

N16

GND#60

N18

GND#61

N21

GND#62

P6

GND#63

P9

GND#64

R12

GND#65

R15

GND#66

R17

GND#67

R20

GND#68

T13

GND#69

T16

GND#70

T18

GND#71

T21

GND#72

T6

GND#73

U15

GND#74

U17

GND#75

U20

GND#76

U9

GND#77

V13

GND#78

V16

GND#79

V18

GND#80

Y10

GND#81

Y15

GND#82

Y17

GND#83

Y20

GND#84

R11

GND#85

T11

GND#86

216-0774207-A11ROB_FCBGA631

SXTR1@

GND

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

www.qdzbwx.com

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

SeymourXT-S3 Power/GND

VAUS5 LA9001P M/B

E

19 50Friday, May 25, 2012

0.3

A

M_DA[63..0]<21>

M_MA[13..0]<21 >

M_DQM[7..0]<21>

M_DQS[7..0]<21>

1 1

M_DQS#[7..0]<21>

M_DA[63..0]

M_MA[13..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

PARK SCL has different recommand

DRAM_RST#<21>

120P_0402_50V8J

2 2

3 3

4 4

+1.5VGS

R363

40.2_0402_1%

PX@

R364

100_0402_1%

PX@

12

1

C467

0.1U_0402_16V4Z

PX@

2

9/28 change P/N to SD034100A80

1 2

R366

51.1_0402_1%

PX@

C469

40.2_0402_1%

100_0402_1%

R455

10_0402_1%PX@

1

R456

PX@

2

+1.5VGS

12

R365

PX@

+MVREFSA+MVREFDA

12

R457

PX@

1

2

@

R460 51.1_0402_1%

1 2 1 2

R373 51.1_0402_1%

@

12

DRAM_RST

12

4.99K_0402_1%

PX@

C514

0.1U_0402_16V4Z

PX@

+1.5VGS

C515 0.1U_0 402_16V4Z@C515 0.1U_0402_16V4Z@

1 2 1 2

C517 0.1U_0 402_16V4Z@C517 0.1U_0402_16V4Z@

Route 50ohms single-ended/100ohm diff and keep short debug only, for clock

observation,if not need, DNI.

A

B

M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

+MVREFDA +MVREFSA

1 2

R458 240_0402_1%PX@R458 240_0402_1%PX@

1 2

R459 240_0402_1%PX@R459 240_0402_1%PX@

B

C

U8C

GDDR5/DDR3

K27

DQA0_0/DQA_0

J29

DQA0_1/DQA_1

H30

DQA0_2/DQA_2

H32

DQA0_3/DQA_3

G29

DQA0_4/DQA_4

F28

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

F30

DQA0_7/DQA_7

C30

DQA0_8/DQA_8

F27

DQA0_9/DQA_9

A28

DQA0_10/DQA_10

C28

DQA0_11/DQA_11

E27

DQA0_12/DQA_12

G26

DQA0_13/DQA_13

D26

DQA0_14/DQA_14

F25

DQA0_15/DQA_15

A25

DQA0_16/DQA_16

C25

DQA0_17/DQA_17

E25

DQA0_18/DQA_18

D24

DQA0_19/DQA_19

E23

DQA0_20/DQA_20

F23

DQA0_21/DQA_21

D22

DQA0_22/DQA_22

F21

DQA0_23/DQA_23

E21

DQA0_24/DQA_24

D20

DQA0_25/DQA_25

F19

DQA0_26/DQA_26

A19

DQA0_27/DQA_27

D18

DQA0_28/DQA_28

F17

DQA0_29/DQA_29

A17

DQA0_30/DQA_30

C17

DQA0_31/DQA_31

E17

DQA1_0/DQA_32

D16

DQA1_1/DQA_33

F15

DQA1_2/DQA_34

A15

DQA1_3/DQA_35

D14

DQA1_4/DQA_36

F13

DQA1_5/DQA_37

A13

DQA1_6/DQA_38

C13

DQA1_7/DQA_39

E11

DQA1_8/DQA_40

A11

DQA1_9/DQA_41

C11

DQA1_10/DQA_42

F11

DQA1_11/DQA_43

A9

DQA1_12/DQA_44

C9

DQA1_13/DQA_45

F9

DQA1_14/DQA_46

D8

DQA1_15/DQA_47

E7

DQA1_16/DQA_48

A7

DQA1_17/DQA_49

C7

DQA1_18/DQA_50

F7

DQA1_19/DQA_51

A5

DQA1_20/DQA_52

E5

DQA1_21/DQA_53

C3

DQA1_22/DQA_54

E1

DQA1_23/DQA_55

G7

DQA1_24/DQA_56

G6

DQA1_25/DQA_57

G1

DQA1_26/DQA_58

G3

DQA1_27/DQA_59

J6

DQA1_28/DQA_60

J1

DQA1_29/DQA_61

J3

DQA1_30/DQA_62

J5

DQA1_31/DQA_63

K26

MVREFDA

J26

MVREFSA

J25

MEM_CALRN0

K25

MEM_CALRP0

DRAM_RST

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

216-0774207-A11ROB_ FCBGA631

SXTR1@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GDDR5/DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4

MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7

MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13/BA2 MAA1_6/MAA_14/BA0 MAA1_7/MAA_15/BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

MEMORY INTERFACE

EDCA0_0/RDQSA_0 EDCA0_1/RDQSA_1 EDCA0_2/RDQSA_2 EDCA0_3/RDQSA_3 EDCA1_0/RDQSA_4 EDCA1_1/RDQSA_5 EDCA1_2/RDQSA_6 EDCA1_3/RDQSA_7

DDBIA0_0/WDQSA_0 DDBIA0_1/WDQSA_1 DDBIA0_2/WDQSA_2 DDBIA0_3/WDQSA_3 DDBIA1_0/WDQSA_4 DDBIA1_1/WDQSA_5 DDBIA1_2/WDQSA_6 DDBIA1_3/WDQSA_7

ADBIA0/ODTA0

ADBIA1/ODTA1

GDDR5

2012/01/15 2013/01/15

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA1_8 MAA0_8

C

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

G14 G20

M_MA13

Compal Secret Data

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1

M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7

VRAM_ODT0 VRAM_ODT1

M_CLK0 M_CLK#0

M_CLK1 M_CLK#1

M_RAS#0 M_RAS#1

M_CAS#0 M_CAS#1

M_CS#0

M_CS#1

M_CKE0 M_CKE1

M_WE#0 M_WE#1

Deciphered Date

M_BA2 <21> M_BA0 <21> M_BA1 <21>

64MX16 (512MB)

128M16 (1GB)

VRAM_ODT0 <21> VRAM_ODT1 <21>

M_CLK0 <21> M_CLK#0 <21>

M_CLK1 <21> M_CLK#1 <21>

M_RAS#0 <21> M_RAS#1 <21>

M_CAS#0 <21> M_CAS#1 <21>

M_CS#0 <21>

M_CS#1 <21>

M_CKE0 <21> M_CKE1 <21>

M_WE#0 <21> M_WE#1 <21>

D

+1.8VGS

1 2

R461 10K_0402_5%X76@R461 10K_0402_5%X76@

1 2

R462 10K_0402_5%X76@R462 10K_0402_5%X76@

1 2

R359 10K_0402_5%X76@R359 10K_0402_5%X76@

1 2

R360 10K_0402_5%X76@R360 10K_0402_5%X76@

1 2

R361 10K_0402_5%X76@R361 10K_0402_5%X76@

1 2

R362 10K_0402_5%X76@R362 10K_0402_5%X76@

K4W1G1646G-BC11

R1 PN:SA00004GS00 R3 PN:SA00004GS40

H5TQ1G63DFR-11C

Hynix 128MB R1 PN:SA000041S20 R3 PN:SA000041S30

K4W2G1646C-HC11

Samsung 256MB R1 PN:SA000047Q00 R3 PN:SA000047Q10

H5TQ2G63DFR-11C

Hynix 256MB R1 PN:SA00003YOA0 R3 PN:SA00003YOI0

K4W2G1646E-BC11

R1 PN:SA00005SH00 R3 PN:SA00005SH30

Title

Size Doc ument Numb er Rev

B

Date: Sheet of

D

Date: Sheet of

E

VRAM_ID0

VRAM_ID1

VRAM_ID2

VRAM_ID0 < 16>

VRAM_ID1 < 16>

VRAM_ID2 < 16>

VRAM_ID1VRAM_ID0Vendor

R461

R461 R360

R462

R461

Compal Electronics, Inc.

SeymourXT-S3 MEM Interface

VAUS5 LA9001P M/B

R360

1

0

1

0

1

0

R359

1

R359 R361Samsung 256MB

1 1

20 50Friday, May 25, 2012

E

VRAM_ID2

R362Samsung 128MB

0

R362R462 R359

0

R361

1

R361

10

www.qdzbwx.com

0.3

A

M_DA[63..0]<20>

M_MA[13..0]<20>

M_DQM[7..0]<20>

M_DQS[7..0]<20>

M_DQS#[7..0]<20>

1 1

2 2

M_DA[63..0]

M_MA[13..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

M_BA0<20> M_BA1<20> M_BA2<20>

M_CLK0<20> M_CLK#0<20> M_CKE0<20>

VRAM_ODT0<20>

M_CS#0<20> M_RAS#0<20> M_CAS#0<20> M_WE#0<20>

DRAM_RST#<20>

R454

243_0402_1% PX@

+VREFC_A1 +VREFD_Q1

M_DQS2 M_DQS0

M_DQM2 M_DQM0

M_DQS#2 M_DQS#0

12

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

U19

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

B

U20

E3

M_DA22

F7

M_DA20

F2

M_DA19

F8

M_DA18

H3

M_DA21

H8

M_DA17

G2

M_DA23

H7

M_DA16

D7

M_DA3

C3

M_DA1

C8

M_DA0

C2

M_DA5

A7

M_DA6

A2

M_DA7

B8

M_DA2

A3

M_DA4

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R451

243_0402_1% PX@

+VREFC_A2 +VREFD_Q2

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

M_DQS3 M_DQS1

M_DQM3 M_DQM1

M_DQS#3 M_DQS#1

DRAM_RST#

12

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

C

U18

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

U18

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

E3

M_DA25

F7

M_DA28

F2

M_DA27

F8

M_DA31

H3

M_DA24

H8

M_DA29

G2

M_DA26

H7

M_DA30

D7

M_DA14

C3

M_DA10

C8

M_DA15

C2

M_DA11

A7

M_DA12

A2

M_DA8

B8

M_DA13

A3

M_DA9

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

X76@

M_CLK1<20> M_CLK#1<20> M_CKE1<20>

VRAM_ODT1<20>

M_CS#1<20> M_RAS#1<20> M_CAS#1<20> M_WE#1<20>

R410

243_0402_1% PX@

+VREFC_A3 +VREFD_Q3

M_DQS4 M_DQS5

M_DQM4 M_DQM5

M_DQS#4 M_DQS#5

DRAM_RST# DRAM_RST#

12

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

D

U21

E3

M_DA35

F7

M_DA34

F2

M_DA36

F8

M_DA37

H3

M_DA32

H8

M_DA38

G2

M_DA33

H7

M_DA39

D7

M_DA47

C3

M_DA42

C8

M_DA45

C2

M_DA40

A7

M_DA44

A2

M_DA43

B8

M_DA46

A3

M_DA41

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R444

243_0402_1% PX@

+VREFC_A4 +VREFD_Q4

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M_DQS6 M_DQS7

M_DQM6 M_DQM7

M_DQS#6 M_DQS#7

12

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

E

E3

M_DA52

F7

M_DA48

F2

M_DA54

F8

M_DA50

H3

M_DA53

H8

M_DA49

G2

M_DA55

H7

M_DA51

D7

M_DA60

C3

M_DA58

C8

M_DA56

C2

M_DA61

A7

M_DA63

A2

M_DA62

B8

M_DA57

A3

M_DA59

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

3 3

1 2

M_CLK0

R443 56_0402_1%PX@R443 56_0402_1%PX@

1 2

M_CLK#0

R396 56_0402_1%PX@R396 56_0402_1%PX@

1 2

M_CLK1

4 4

ref 139-02 recommand add off page Park SCL recommand pu

60.4 ohm to 1.5VGS

M_CLK#1

R422 56_0402_1%PX@R422 56_0402_1%PX@

1 2

R436 56_0402_1%PX@R436 56_0402_1%PX@

0619 update

A

1

C506

0.01U_0402_16V7K

PX@

2

1

C507

0.01U_0402_16V7K

PX@

2

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

12

R450

4.99K_0402_1%

PX@

+VREFD_Q1

12

0.1U_0402_10V6K

R386

4.99K_0402_1%

PX@

1

C472

PX@

2

VRAM P/N :

Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )

Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )

R379

4.99K_0402_1%

PX@

R387

4.99K_0402_1%

PX@

12

+VREFC_A1

12

0.1U_0402_10V6K

1

C473

PX@

2

10U_0603_6.3V6M

+1.5VGS

C488

1

2

10U_0603_6.3V6M

PX@

update VRAM PN 0619 update

B

C489

PX@

R380

4.99K_0402_1%

PX@

R388

4.99K_0402_1%

PX@

10U_0603_6.3V6M

1

C490

2

PX@

12

1

C512

2

10U_0603_6.3V6M

PX@

12

R381

4.99K_0402_1%

PX@

+VREFC_A2 +VREFD_Q2 +VREFD_Q3+VREFC_A3 +VREFC_A4 +VREFD_Q4

0.1U_0402_10V6K

1

C474

PX@

2

10U_0603_6.3V6M

1

C491

2

10U_0603_6.3V6M

PX@

4.99K_0402_1%

1

C511

2

12

0.1U_0402_10V6K

R449

PX@

1

2

PX@

1

C475

PX@

2

+1.5VGS

1U_0402_6.3V4Z

C510

C493

1

2

1U_0402_6.3V4Z

PX@

C483

1

2

PX@

C493

1U_0402_6.3V4Z

PX@

C492

1

2

1U_0402_6.3V4Z

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

12

R382

4.99K_0402_1%

PX@

12

0.1U_0402_10V6K

1U_0402_6.3V4Z

C497

C496

1

2

1U_0402_6.3V4Z

PX@

@

1

C476

PX@

2

1U_0402_6.3V4Z

C498

1

2

PX@

Compal Secret Data

Deciphered Date

R448

4.99K_0402_1%

PX@

1U_0402_6.3V4Z

C494

C495

1

2

1U_0402_6.3V4Z

PX@

2012/01/15 2013/01/15

4.99K_0402_1%

C499

1U_0402_6.3V4Z

R383

PX@

R447

PX@

+1.5VGS

1U_0402_6.3V4Z

C500

1

2

PX@

D

12

PX@

1U_0402_6.3V4Z

C501

1

2

1U_0402_6.3V4Z

PX@

0.1U_0402_10V6K

1

C477

2

C484

1

2

PX@

1U_0402_6.3V4Z

C509

C508

1

2

1U_0402_6.3V4Z

PX@

1U_0402_6.3V4Z

C502

1

2

1U_0402_6.3V4Z

PX@

12

R384

4.99K_0402_1%

PX@

12

R446

4.99K_0402_1%

C503

1

2

1U_0402_6.3V4Z

@

PX@

1U_0402_6.3V4Z

C505

C487

C504

1

2

PX@

@

Title

Size Document Number Rev

C

Date: Sheet of

12

R385

4.99K_0402_1%

PX@

0.1U_0402_10V6K

1

C513

2

Compal Electronics, Inc.

R445

4.99K_0402_1%

PX@

SeymourXT-S3 DDR3 VRAM

VAUS5 LA9001P M/B

E

0.1U_0402_10V6K

12

1

C479

PX@

2

21 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

+3VS +3VS_PS

30mil 30mil

R192 0_0603_5%R192 0_0603_5%

Close to Pin3

0.1U_0402_16V4Z

10U_0603_6.3V6M

1 1

1

C230

2

0.1U_0402_16V4Z

1

C231

2

Close to L15

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

C233

2

22U_0603_6.3V6M

1

C234

2

+DP_V33

1

C232

2

Close to Pin18

0.1U_0402_16V4Z

1

C236

C235

2

0.1U_0402_16V4Z

+SWR_VDD

1

C237

2

Reserved for EC programming ROM Need EC confirm

LVDS_HPD<7>

Close to Pin13

Close to L171

2 2

0.1U_0402_16V4Z

22U_0603_6.3V6M

0.1U_0402_16V4Z

@

1

C238

2

0.1U_0402_16V4Z

@

1

C239

2

Close to Pin27

1

2

C240

0.1U_0402_16V4Z

1

C241

2

Close to Pin7

1 2

+SWR_V12

R200 0_0805_5%R200 0_0805_5%

Will mount R200, @ L171, C238, C239 after DVT

Will mount R200, @ L171, C238, C239 after DVTWill mount R200, @ L171, C238, C239 after DVT

+1.2VS

20110124 Modify

DP0_TXP0_C<7> DP0_TXN0_C<7>

B

+3VS_PS

R198

100K_0402_5%

L16

FBMA-L11-201209-221LMA30T_0805

L15

FBMA-L11-201209-221LMA30T_0805

1 2

L171

4.7UH_PG031B-4R7MS_1.1A_20%

@

DP0_AUXP_C<7> DP0_AUXN_C<7>

R197

1 2

1K_0402_5%

12

+DP_V33

12

+SWR_VDD

+SWR_LX+SWR_V12

CSCL CSDA

LVDS_HPD_R

R199

12K_0402_1%

Change to 12Kohm 1% (DG ref.) 20101114

1 2

40mil

60mil

60mil 60mil60mil

3

13 18

12 11 27

7

2 1

5 6

9

10

32

8 4

U5

DP_V33

SWR_VDD PVCC

SWR_LX SWR_VCCK VCCK DP_V12

AUX_P AUX_N

LANE0P LANE0N

CIICSCL1 CIICSDA1

HPD

DP_REXT DP_GND

RTD2132S

C

TXEC+

LVDS

GPIO(PWM OUT)

GPIO(Panel_VCC)

GPIO(PWM IN)

GPIO

GPIO(BL_EN)

LVDS

MIICSCL1

EDID

ROM

MIICSCL0

MIICSDA0

TXEC-

TXE2+

TXE2-

TXE1+

TXE1-

TXE0+

TXE0-

MIICDA1

Power

DP-IN

Other

RTD2132S-VE-CG_QFN32_5X5

GND

19 20

21 22

23 24

25 26

14 15 16

APU_INVT_PWM

17

ENBKL_R

29 28

31 30

33

MIIC_SCL MIIC_SDA

D

LVDS_ACLK <23> LVDS_ACLK# <23>

LVDS_A2 <23> LVDS_A2# <23>

LVDS_A1 <23> LVDS_A1# <23>

LVDS_A0 <23> LVDS_A0# <23>

TL_INVT_PWM <23>

TL_ENVDD <23>

EDID_CLK <23> EDID_DATA <23>

EEROM

EEROMEEROM

Will @ U4 after DVT

Will @ U4 after DVTWill @ U4 after DVT

@

0_0402_5%

R193

R193 R194

R194

1 2 1 2

0_0402_5%

@

1:RevD W EEPROM 0:RevE W/O EEPROM

EDID_DATA

EDID_CLK

MIIC_SDA

MIIC_SCL MIIC_SDA

E

+SWR_VDD

8

VCC

7

WP

MIIC_SCL_R MIIC_SDA_R

6

SCL

5

SDA

CAT24C64WI-GT3_SO8

MIIC_SCL

1 2

R201 4.7K_0402_5%R201 4.7K_0402_5%

1 2

R202 4.7K_0402_5%R202 4.7K_0402_5%

1 2

R203 4.7K_0402_5%R203 4.7K_0402_5%

U4

+3VS_PS

@

GND

R195

4.7K_0402_5%

1 2

R196

4.7K_0402_5%

1 2

1

A0

2

A1

3

A2

4

+3VS_PS

Vendor advise reserve it (We delete the 0ohm path between ENBKL_R & TL_BKOFF#)

+3VS

Panel PWM

3 3

DP_INT_PWM<7>

4 4

Panel PWMPanel PWM

12

R210

4.7K_0402_5%

A

1 2

R209 2.2K_0402_5%R209 2.2K_0402_5%

12

R207

R207 47K_0402_5%

47K_0402_5%

C

Q8

2

B

E

3 1

12

R208

4.7K_0402_5%

APU_INVT_PWM

13

D

2

G

Q7

G

Q7 2N7002K_SOT23-3

2N7002K_SOT23-3

S

MMBT3904_NL_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

ENBKL_R

12

R206

100K_0402_5%

BKOFF#<23,31>

CSDA CSCL

2012/01/15 2013/01/15

+3VS_PS

R212 0_0402_5%R212 0_0402_5% R213 0_0402_5%R213 0_0402_5%

Compal Secret Data

1 2

R204 0_0402_5%R204 0_0402_5%

C242

0.1U_0402_16V7K

1 2

5

2

P

B

4

Y

1

A

G

@

3

MC74VHC1G08DFT2G SC70 5PU6@MC74VHC1G08DFT2G SC70 5PU6

1 2 1 2

Deciphered Date

ENBKL <31>

@

TL_BKOFF# <23>

TL_DATA <31>

TL_CLK <31 >

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LVDS Translator - RTD2132S

VAUS5 LA9001P M/B

E

22 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

B

C

D

E

LCD POWER CIRCUIT

CMOS Camera

+LCDVDD

12

R1454

1 1

2N7002K_SOT23-3

TL_ENVDD<22>

2 2

3 3

4 4

R1454 150_0603_5%

150_0603_5%

13

D

2

G

Q71

S

R1459

100K_0402_5%

TL_BKOFF#<22>

LCD_ENVDD#

DTC124EK

2

12

@R1459

@

BKOFF#<22,31>

+5VALW

12

R1455

R1455 100K_0402_5%

100K_0402_5%

1

OUT

IN

GND

DTC124EKAT146_SC59-3

3

TL_BKOFF#

R1457 220K_0402_5%R 1457 220K_0402_5%

1 2

Q73

1 2

R1202 0_0402_5%

1 2

R1201 0_0402_5%R12 01 0_0402_5%

G

2

1

C1154

0.1U_0402_16V4Z

2

FBMA-L11-201209-221LMA30T_0805

@

+3VS

S

D

1 3

+LCDVDD

RB751V_SOD323

W=60mils

1

C1150

4.7U_0603_6.3V6K

2

Q72

Q72 PMV65XP_SOT23-3

PMV65XP_SOT23-3

L29

1 2

4.7U_0805_10V4Z

R891

1 2

0_0402_5%

D33

2 1

@

+LCDVDD_CONN

C1156

12

R890

R890 10K_0402_5%

10K_0402_5%

W=60mils

1

2

DISPOFF#BKOFF#

1

C1157

0.1U_0402_16V4Z

2

R1458

CMOS@R1458

CMOS@

150K_0402_5%

CMOS_ON#<31>

change to EC contorl , due to FCH only 16 level

TL_INVT_PWM<22>

EC_INVT_PWM<31>

150K_0402_5%

1 2

R1463 0_0402_5%@R1463 0_0402 _5%@

1 2

R1465 0_0402_5%R14 65 0_0402_5%

100K_0402_5%

+3VS

(40 MIL)

CMOS@

Q70

Q70 PMV65XP_SOT23-3

PMV65XP_SOT23-3

D

S

D

S

13

+3VS_CMOS_R

G

2

1

C1155

CMOS@C1155

CMOS@

0.1U_0402_16V4Z

2

Add for protect DISPOFF# damage

LVDS_ACLK<22>

+3VS

LVDS_ACLK#<22>

1

@C1160

@

2

12

R825

680P_0402_50V7K

C1160

follow AMD interlock suggestion

1

CMOS@

C1152

0.1U_0402_16V4Z

2

R1466 0_0402_5%@ R1466 0_0402_5%@

LVDS_A2<22> LVDS_A2#<22> LVDS_A1<22> LVDS_A1#<22> LVDS_A0<22>

LVDS_A0#<22> EDID_DATA<22> EDID_CLK<22>

+LCDVDD_CONN

+3VS_CMOS USB20_P3<12> USB20_N3<12>

CMOS

+3VS_CMOS

CMOS@

(40 MIL)

R1456

R1456 0_0603_5%

0_0603_5%

R02

12

10U

1

C1153

@C1153

@

10U_0603_6.3V6M

2

VGA LCD/PANEL BD. Conn.

1

C1158

680P_0402_50V7K

1 2

+3VS

(60 MIL)

USB20_P3

USB20_N3

680P_0402_50V7K

DISPOFF# INVT_PWM

R85

R85 300_0402_5%

300_0402_5%

1 2

2

C8244

C8244 15P_0402_50V8J

15P_0402_50V8J

1

@

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

STARC_107K30-000001-G2

SP010011S00

JLVDS1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

2

ME@

GND1 GND2 GND3 GND4 GND5 GND6

C1159

4.7U_0805_25V6-K

31 32 33 34 35 36

1 2

R1460

R1460 0_0805_5%

0_0805_5%

B++LEDVDD

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LVDS/CAMERA

VAUS5 LA9001P M/B

23 50Thursday, May 31, 2012

E

0.3

A

B

C

D

E

FOR EMI

1 2

R1473 0_0402_5%@R1473 0_0402_ 5%@

1 2

R1474 0_0402_5%@R1474 0_0402_ 5%@

1 2

R1475 0_0402_5%@R1475 0_0402_ 5%@

1 2

R1476 0_0402_5%@R1476 0_0402_ 5%@

1 2

R1477 0_0402_5%@R1477 0_0402_ 5%@

1 2

R1478 0_0402_5%@R1478 0_0402_ 5%@

1 2

R1480 0_0402_5%@R1480 0_0402_ 5%@

1 2

R1481 0_0402_5%@R1481 0_0402_ 5%@

+5VS

RB491D_SC59-3

RB491D_SC59-3 D31

2 1

1

C1223

C1223 1000P_0402_50V7K

1000P_0402_50V7K

2

HDMI@ R1470

HDMI@

2.2K_0402_5%

HDMI@D31

HDMI@

R1470

1 2

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

+HDMI_5V

+3VS

1 1

HDMI_DET<7>

2

3

2

3

2

3

2

3

1 2 1 2

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

+3VS

R242

R241

1 2

4.7K_0402_5% HDMI@

HDMI_TX2P HDMI_TX2N

HDMI_TX1P HDMI_TX1N

HDMI_TX0P HDMI_TX0N

HDMI_CLKP HDMI_CLKN

+3VS

1 2

4.7K_0402_5% HDMI@

4

DP2_TXP0

DP2_TXP0<7> DP2_TXN0<7>

DP2_TXP1<7> DP2_TXN1<7>

DP2_TXP2<7> DP2_TXN2<7>

DP2_TXP3<7> DP2_TXN3<7>

2 2

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

HDMI_TX1N

3 3

4 4

HDMI_TX2P

HDMI_TX2N

HDMI_CLK<7>

HDMI_DATA<7>

DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

L30

1

4

WCM-2012HS-900T

L31

1

4

WCM-2012HS-900T

L32

1

4

WCM-2012HS-900T

L33

1

4

WCM-2012HS-900T

HDMI_CLK

HDMI_DATA

C51 0.1U_0402_16V7KH DMI@C51 0.1U_0402_16V7KH DMI@ C52 0.1U_0402_16V7KHDMI@C52 0.1U_0402_16V7KHDMI@

C53 0.1U_0402_16V7KH DMI@C53 0.1U_0402_16V7KH DMI@ C54 0.1U_0402_16V7KH DMI@C54 0.1U_0402_16V7KH DMI@

C55 0.1U_0402_16V7KH DMI@C55 0.1U_0402_16V7KH DMI@ C56 0.1U_0402_16V7KH DMI@C56 0.1U_0402_16V7KH DMI@

C57 0.1U_0402_16V7KH DMI@C57 0.1U_0402_16V7KH DMI@ C5888 0.1U_0402_16V7KHDMI@C5888 0.1U_0402_16V 7KHDMI@

HDMI@L30

HDMI@

HDMI@L31

HDMI@

HDMI@L32

HDMI@

HDMI@L33

HDMI@

R84

1K_0402_5% @

1 2

Q75A

HDMI@

2

2N7002DW-T/R7_SOT363-6

5

3

Q75B

HDMI@

2N7002DW-T/R7_SOT363-6

HDMI@

MMBT3904_NL_SOT23-3

61

HDMICLK_R

HDMIDAT_R

C

Q87

E

3 1

12

HDMI@

R859

R859 100K_0402_5%

100K_0402_5%

HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMICLK_R

HDMIDAT_R

HDMI@

R434

1 2

2

B

150K_0402_5%

R864

200K_0402_5%

Close to HDMI connector

D1

@D1

@

1

2

4

5

3

TVWDF1004AD0_DFN 9

D2

@

1

2

4

5

3

TVWDF1004AD0_DFN 9

3

+5VS

@

1 2

9

8

7

6

9

8

7

6

2

D69

D69 L30ESDL5V0C3-2_SOT23-3

L30ESDL5V0C3-2_SOT23-3

HDMI@

1

2

3

D32

@D32

@

BAT54S-7-F_SOT23-3

1

HDMI_CLKN

HDMI_CLKP HDMI_TX0N

HDMI_TX0P HDMI_TX1N

HDMI_TX1P HDMI_TX2N

HDMI_TX2P

HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_CLK-_CONN

HDMI_CLK+_CONN

W=40mils

F1

1.1A_6VDC_FUSE

R1471

HDMI@R 1471

HDMI@

2.2K_0402_5%

1 2

HDMI_DET_R

+5VS_HDMI

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI@F1

HDMI@

+5VS_HDMI

21

+5VS_HDMI

C1161

HDMI@

0.1U_0402_16V4Z

1

2

JHDMI1

@JHDMI1

@

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11 10

9 8 7 6 5 4 3 2 1

GND

CK_shield

GND

CK+

GND

D0-

GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

CONCR_099ATAC19NBLCNF

20 21 22 23

Change Symbol to main source 02/24

1 2

R243 604_0402_1%HDMI@R243 604_0402_1%HDMI@

1 2

R244 604_0402_1%HDMI@R244 604_0402_1%HDMI@

1 2

R245 604_0402_1%HDMI@R245 604_0402_1%HDMI@

1 2

R246 604_0402_1%HDMI@R246 604_0402_1%HDMI@

1 2

R247 604_0402_1%HDMI@R247 604_0402_1%HDMI@

1 2

R248 604_0402_1%HDMI@R248 604_0402_1%HDMI@

1 2

R249 604_0402_1%HDMI@R249 604_0402_1%HDMI@

1 2

R250 604_0402_1%HDMI@R250 604_0402_1%HDMI@

13

2

+5VS

G

D

Q76

2N7002K_SOT23-3

HDMI@

S

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

HDMI CONN

VAUS5 LA9001P M/B

E

0.3

24 50Friday, May 25, 2012

0.3

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half)

+1.5VS

1 1

BT_DISABLE#<11>

2 2

BT_OFF#<10>

Mini-Express Card(WLAN/WiMAX)

0_0402_5%

1 2

R1498

1 2

R1499

R1499 0_0402_5%

0_0402_5%

FCH_PCIE_WAKE#

WLAN_CLKREQ#

PCI_RST#_R CLK_PCI_DB

+3VS_WLAN

BT_DISABLE_R

R1501

R1501 100K_0402_5%

100K_0402_5%

1 2

FCH_PCIE_WAKE#<12,26>

R1491 0_0402_5%R1491 0_0402_5%

WLAN_CLKREQ#<12>

CLK_PCIE_WLAN#<10>

CLK_PCIE_WLAN< 10>

PCIE_CRX_DTX_N1<5> PCIE_CRX_DTX_P1<5>

PCIE_CTX_DRX_N1<5> PCIE_CTX_DRX_P1<5>

EC_TX

EC_TX<31>

EC_RX

EC_RX<31>

BT_DISABLE#

R1493 1K_0402_5%

@

R1493 1K_0402_5%

@

R1520 1K_0402_5%

@

R1520 1K_0402_5%

@

For EC to detect debug card insert.

1 2

JWLAN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

BELLW_80019-1021

DC040004X00

ME@

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_DUSB_D+

LED_WWAN#

LED_WLAN# LED_WPAN#

+1.5V

+3.3V

+3VS_WLAN

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22 24 26

GND

28 30 32 34

GND

36 38 40

GND

42 44 46 48 50

GND

52

54

GND

12

R1488

R1488 0_0402_5%

0_0402_5%

+1.5VS_WLAN

1 2

R1492 0_0402_5%@R 1492 0_0402_5%@

R1494 0_0402_5%@R 1494 0_0402_5%@ R1495 0_0402_5%R1495 0_0402_5%

R1496 0_0402_5%@R 1496 0_0402_5%@ R1497 0_0402_5%@R 1497 0_0402_5%@

1 2 1 2

R87

R87 300_0402_5%

300_0402_5%

1 2

2

C8246

C8246 15P_0402_50V8J

15P_0402_50V8J

1

APU_PCIE_RST#

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

USB20_N2_WLAN USB20_P2_WLAN

follow AMD interlock suggestion

+1.5VS_WLAN

1

C1172

0.1U_0402_16V4Z@

2

WL_OFF# <11>

APU_PCIE_RST# <10,15> +3VALW +3VS_WLAN

FCH_SCLK0 <12,9> FCH_SDATA0 <12,9>

1

C1173

0.1U_0402_16V4Z

2

@

USB20_N2_WLAN

USB20_P2_WLAN

R1518 0_0603_5%

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

NONAOAC@

R1503

R1503 0_0402_5%

0_0402_5%

1 2

0_0402_5%

0_0402_5% R1504

R1504

NONAOAC@

12

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

USB20_N2

USB20_P2

+3VS_WLAN+3VS

1

C1170

0.1U_0402_16V4Z

2

R251 0_0402_5%@R 251 0_0402_5%@ R252 0_0402_5%@R 252 0_0402_5%@ R253 0_0402_5%@R 253 0_0402_5%@ R254 0_0402_5%@R 254 0_0402_5%@ R255 0_0402_5%@R 255 0_0402_5%@ R2561 0_0402_5%@R2561 0_0402_5%@

USB20_N2_WLAN

USB20_P2_WLAN

USB20_N2 <12>

USB20_P2 <12>

1

C1171

0.1U_0402_16V4Z

2

AOAC_ON#<31>

1 2 1 2 1 2 1 2 1 2 1 2

R1502

R1502 150K_0402_5%

150K_0402_5%

AOAC@

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 APU_PCIE_RST#

U56

7

5

4

TS3USB31RSER_QFN8_1P5X1P5

+3VALW

8

NC

VCC

HSD-6D-

2

D+3HSD+

1

GND

OE#

AOAC@

R1500 0_0603_5%

AOAC@

Q77 AO3413_SOT23-3

S

G

2

1

AOAC@

C1175

0.1U_0402_16V4Z

2

LPC_FRAME# <10,31> LPC_AD3 <10,31> LPC_AD2 <10,31> LPC_AD1 <10,31> LPC_AD0 <10,31>

CLK_PCI_DB <10>

+3VALW

AOAC@

C1185 0.1U_0402_16V4Z

1 2

USB20_N2

USB20_P2

WLAN_USB_ON#

R1505

@

0_0402_5%

1 2

+3VS_WLAN_AOAC

12

D

13

AOAC@

1

AOAC@

C1174

0.1U_0402_16V4Z

2

WLAN_USB_ON# <31>

Mini-Express Card for SSD(Full)

Mini-Express Card(WWAN/SSD)

0.1U_0402_16V4Z

1

SSD@

C1176

3 3

SATA_FRX_C_DTX_P0<11> SATA_FRX_C_DTX_N0<11>

SATA_FTX_C_DRX_N0<11> SATA_FTX_C_DRX_P0<11>

4 4

2

0.01U_0402_16V7K

SSD@

C1180 0.01U_0402_16V7K

SATA_FRX_C_DTX_N0 SATA_FRX_DTX_N0

SATA_FTX_C_DRX_N0 SATA_FTX_DRX_N0 SATA_FTX_C_DRX_P0 SATA_FTX_DRX_P0

A

C1180 0.01U_0402_16V7K C1181 0.01U_0402_16V7K

C1181 0.01U_0402_16V7K

SSD@

SSD@ SSD@

SSD@

C278 0.01U_0402_16V7K

C278 0.01U_0402_16V7K C2758 0.01U_0402_16V7K

C2758 0.01U_0402_16V7K

SSD@

+3VS_SSD +3VS_SSD

1

SSD@

C1177

2

10U_0603_6.3V6M

1 2 1 2

10U_0603_6.3V6M

1

SSD@

C1178

2

1

@

C1179

2

11/07 Change type to 0603

SATA_FRX_DTX_P0SATA_FRX_C_DTX_P0

+3VS_SSD

B

SSD Active:4.5W(1.5A)

+3VS

JSSD1

ME@

JSSD1

ME@

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND PERn0 PERp0 GND GND

SMB_CLK

PETn0

SMB_DATA PETp0 GND NC NC NC

LED_WWAN#

NC

LED_WLAN#

NC

LED_WPAN# NC NC NC

GND

BELLW_80019-1021

DC040004X00

PERST#

+3.3Vaux

+1.5V

USB_D-

USB_D+

+1.5V

+3.3V

23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

J14

@

JUMP_43X79

3.3V GND

1.5V NC NC NC NC NC

GND

NC

GND

112

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

Need SHORT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Mini-Card

VAUS5 LA9001P M/B

E

25 50Thursday, May 31, 2012

0.3

www.qdzbwx.com

A

B

C

D

E

Layout Notice : Place as close chip as possible.

+3VALW

R211

0_0805_5%

1 2

Layout Notice : Place as close chip as possible.

+3V_LAN

1 2

C11890.1U_0402_16V4Z C11890.1U_0402_16V4Z

1 2

C11900.1U_0402_16V 4Z C11900.1U_0402_16V4Z

1 2

C11910.1U_0402_16V 4Z C11910.1U_0402_16V4Z

1 2

C11920.1U_0402_16V 4ZGIGA@ C11920.1U_0402_16V4ZGIGA@

1 2

C11930.1U_0402_16V 4ZGIGA@ C11930.1U_0402_16V4ZGIGA@

1 2

C11940.1U_0402_16V 4ZGIGA@ C11940.1U_0402_16V4ZGIGA@

+LAN_VDD10

1 2

C12030.1U_0402_16V4Z C12030.1U_0402_16V4Z

1 2

C12000.1U_0402_16V4Z C12000.1U_0402_16V4Z

1 2

C11990.1U_0402_16V4Z C11990.1U_0402_16V4Z

1 2

C11970.1U_0402_16V4ZGIGA@ C11970.1U_0402_16V4ZGIGA@

1 2

C12010.1U_0402_16V4ZGIGA@ C12010.1U_0402_16V4ZGIGA@

1 2

C12020.1U_0402_16V4ZGIGA@ C12020.1U_0402_16V4ZGIGA@

1 2

C11980.1U_0402_16V4ZGIGA@ C11980.1U_0402_16V4ZGIGA@

+3V_LAN

www.qdzbwx.com

12

C1188

0.1U_0402_16V4Z

1 2

+LAN_VDDREG+3V_LAN

1 2

+LAN_VDD10

C1182

0.1U_0402_16V4Z

1 2

C1196

0.1U_0402_16V4Z

+3V_LAN

12

R1515

R1515 0_0402_5%

0_0402_5%

@

R1517

R1517 0_0402_5%

0_0402_5%

@

R211 for power consumption easily rework

11/08 Increase for LAN S5 pow er saving

Rising time (10%~90%)1mS <Rising time <100mS

Close to Pin 12,27,39,42,47,48

Close to Pin 3,6,9,13,29,41,45

U47

ISOLATEB

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAK EB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWR EG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111F-CGT_QFN48_6x6

GIGA@

1 2

PCIE_CRX_DTX_P0<5>

1 1

PCIE_CRX_DTX_N0<5>

PCIE_CTX_DRX_P0<5> PCIE_CTX_DRX_N0<5>

Pin 16 and Pin 28 are OD pins

LAN_WAKE#<31>

FCH_PCIE_WAKE#<12,25>

+3V_LAN

12

R1512

2 2

R1512 10K_0402_5%

10K_0402_5%

@

LAN_CLKREQ#

C1183 0.1U_0402_16V7KC1183 0.1U_0402_16V7K

1 2

C1186 0.1U_0402_16V7KC1186 0.1U_0402_16V7K

R1508 0_04 02_5%@R1508 0_0402_5%@

1 2

R1509

@

+3V_LAN

CLK_PCIE_LAN<10> CLK_PCIE_LAN#<10>

12

0_0402_5%R 1509

0_0402_5%

R1510 10K_0402_5%@R1510 10K_0402_5%@ R1511 1K_0402_5%@R1511 1K_0402_5%@

+LAN_VDDREG

LAN_CLKREQ#<12>

PLT_RST#<10,31>

1 2

R1513 2.49K_0402_1%R 1513 2.49K_0402_1%

PCIE_CRX_DTX_C_P0

PCIE_CRX_DTX_C_N0

LAN_XTALI

LAN_XTALO

PCIE_WAKE#_R

12

ENSWREG

1 2

LED3/EEDO

LED1/EESK

LED0

EECS

EEDI

MDIP0

MDIN0

MDIP1

MDIN1

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10

AVDD10 AVDD10 AVDD10 AVDD10

REGOUT

31 37 40

30 32

1 2 4 5 7 8 10 11

13 29 41

27 39

12 42 47 48

21

3 6 9 45

36

R1506 10K_0402_5%@R1506 10K_0402_5%@ R1507 10K_0402_5%@R1507 10K_0402_5%@

MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-

+LAN_VDD10

+3V_LAN

+LAN_EVDD10

+LAN_VDD10

+LAN_REGOUT

12 12

MDI0+ <27> MDI0- <27> MDI1+ <27> MDI1- <27> MDI2+ <27> MDI2- <27> MDI3+ <27> MDI3- <27>

+LAN_REGOUT

Layout Note: L34 must be within 200mil to Pin36, C1184,C1182 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

+LAN_VDD10

SA00004Y700

R1514

1K_0402_5%

R1516

15K_0402_5%

3 3

15K_0402_5%

Follow Vendor tunning value

1 2

RL1 0_0402 _5%@RL1 0_0402_5%@

CLK_LAN_25M <10>

U47

RTL8105E-VL-CGT

SA00003PO40

C1204

15P_0402_50V8J

Y4

4

NC

OSC

1

OSC

25MHZ_10PF_X3G025000DC1H

1

2

NC

R02

15P_0402_50V8J

C1205

3

2

LAN_XTALI

LAN_XTALO

1

2

L34

1 2

2.2UH +-5% NLC252018T-2R2J-N

4.7U_0603_6.3V6K

X5R

1 2

L35 0_0603_5%@ L35 0_0603_5%@

C1187

1U_0402_6.3V4Z

Close to Pin 21

1 2

L36 0_0603_5%@L36 0_0603_5%@

C1195

4.7U_0603_6.3V6K

X5R

+3VS

12

8105@

C1184

+LAN_EVDD10

12

ENSWREGISOLATEB

H: Enable internal Regular L: Disable

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LAN-RTL8111F/8105E

VAUS5 LA9001P M/B

Tuesday, May 29, 2012

E

26 50

0.3

A

B

C

D

E

Reserve gas tube for EMI go rural solution

T71

MDI3+<26>

@

1 1

MDI2+ MDI3+

MDI3- MDI2-

AZC099-04S.R7G_SOT23- 6

@

D34

1

I/O1

2

GND

3

I/O2

I/O3

VDD

I/O4

4

5

6

Place Close to T71

@

D35

AZC099-04S.R7G_SOT23- 6

2 2

MDI1+ MDI0+

AZC099-04S.R7G_SOT23- 6

1

I/O1

I/O3

4

1

C1207

0.01U_0402_16V7K

2

MDI3-<26>

MDI2+<26> MDI2-<26>

MDI0+<26> MDI0-<26>

MDI1+<26> MDI1-<26>

MDI3+ MDI3-

MDI2+ MDI2-

MDI0+ MDI0-

MDI1+ MDI1-

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

BOTHHAND_NS0013L F

GIGA@

T72

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

BOTHHAND_NS0013L F

TX+

TX-

RX+

TX+

TX-

RX+

16

MDO3+

15

MDO3-

14

MCT

CT

13

NC

12

NC

11

MCT

CT

10

MDO2+

9

MDO2-

16

MDO0+

15

MDO0-

14

MCT

CT

13

NC

12

NC

11

MCT

CT

10

MDO1+

9

MDO1-

R1521

1 2

75_0805_5%

DL2

DL2 BS4200N-C-LV_SMB-F2

BS4200N-C-LV_SMB-F2

GAS@

C1206

1 2

10P_0603_50V

12

CHASSIS1_GND

2

GND

MDI0- MDI1-

3

I/O2

Place Close to T72

D34/D35 1'S PN:SC300001G00

3 3

4 4

2'S PN:SC300002E00

A

VDD

I/O4

5

6

JRJ1

ME@

JRJ1

ME@

12

GND

11

GND

10

1

MDO0+

MDO0-

MDO1+

MDO2+

MDO2-

MDO1-

MDO3+

MDO3-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

SANTA_130460-3

DC231112261

GND

9

GND

CHASSIS1_GND

Compal Secret Data

2012/01/15 2013/01/15

C

Compal Secret Data

Deciphered Date

D

Place Close to T71,T72

Compal Electronics, Inc.

Title

Size Doc ument Numb er Rev

B

Date: Sheet of

Compal Electronics, Inc.

LAN_Transformer

VAUS5 LA9001P M/B

27 50Friday, May 25, 2012

E

www.qdzbwx.com

0.3

A

B

C

D

E

SMSC thermal sensor

Close U49

REMOTE1+

1

C1211

1 1

C1211

2200P_0402_50V7K

C1213

@C12 13

@

2200P_0402_50V7K

2

1

2

REMOTE1-

REMOTE2+

REMOTE2-

0.1U_0402_16V4Z

C1212

+3VS

REMOTE1+

2

REMOTE1-

REMOTE2+

1

REMOTE2-

placed near by VRAM

U49

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403-2-AIZL-TR_MSOP10

SMCLK

SMDATA

ALERT#

THERM#

GND

10

9

8

7

6

+3VS

12

R1524

R1524 10K_0402_5%

10K_0402_5%

@

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <16,31>

EC_SMB_DA2 <16,31>

Address 1001_101xb

REMOTE1+

C1210

@ C1210

@

100P_0402_50V8J

REMOTE1-

REMOTE2+

C1214

@ C1214

@

100P_0402_50V8J

REMOTE2-

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

2 2

Screw Hole

FAN1 Conn

+5VS

JFAN1

ME@

JFAN1

12

R1525

R1525 0_0603_5%

0_0603_5%

2

C1215

C1215 10U_0603_6.3V6M

10U_0603_6.3V6M

1

10U

3 3

EC_FAN_PWM<31>

+FAN1

EC_TACH<31>

ME@

1

2

3

4

5

G1

6

G2

ACES_85204-04001

SP02000CW00

H6

H6 HOLEA

HOLEA

A

CHASSIS1_GND

H_3P0

H18

H18 HOLEA

HOLEA

B

CPU

H_4P0

H21

H21 HOLEA

HOLEA

C

GPU

H_3P3

H14

H14 HOLEA

HOLEA

H15

H7

H7 HOLEA

HOLEA

1

H_2P5

H19

H19 HOLEA

HOLEA

1

H_4P0

H22

H22 HOLEA

HOLEA

H8

H8 HOLEA

HOLEA

1

H_2P5

H20

H20 HOLEA

HOLEA

1

H_4P0

H9

H9 HOLEA

HOLEA

1

H_2P5

H29

H29 HOLEA

HOLEA

1

H_4P0

D

1

H_3P3

H16

H16 HOLEA

HOLEA

LAN

H10

H10 HOLEA

HOLEA

1

H_2P5

H17

H17 HOLEA

HOLEA

H11

H11 HOLEA

HOLEA

1

H_2P5

H24

H24 HOLEA

HOLEA

1

H_3P3

H12

H12 HOLEA

HOLEA

1

H_5P4X2P5

H23

H23 HOLEA

HOLEA

CHASSIS1_GND

H_3P3

H25

H25 HOLEA

HOLEA

1

H13

H13 HOLEA

HOLEA

1

H_2P5

H15 HOLEA

HOLEA

1

H_2P5N

H26

H26 HOLEA

HOLEA

1

H_1P5N

H27

H27 HOLEA

HOLEA

1

H_1P5N

PCB Fedical Mark PAD

FD1FD1

FD2FD21FD3FD3

R

1

H_5P4X2P5

1

H_5P9X3P0

1

H_2P5X3P1N

1

H_2P5X3P1N

1

2

B

2

E

1

2

B

2

E

FD4FD4

1

Close to DDR

C

Q79

MMST3904-7-F_SOT323-3

3 1

Under WWAN

C

Q80

MMST3904-7-F_SOT323-3

3 1

1

www.qdzbwx.com

4 4

Security Classification

2012/01/15 2013/01/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/01/15 2013/01/15

C

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Doc ument Numb er Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics,Ltd.

Fintek-Thermal IC/FAN/screw

VAUS5 LA9001P M/B

28 50Friday, May 25, 2012

E

0.3

A

1 1

B

C

D

E

SATA HDD Conn.

JHDD1

ME@

JHDD1

ME@

1

SATA_FTX_C_DRX_P1<11> SATA_FTX_C_DRX_N1<11>

SATA_FRX_C_DTX_N1<11> SATA_FRX_C_DTX_P1<11>

2 2

+5V_HDD +3V_HDD

R02

1

C1218

C1218 1000P_0402_50V7K

1000P_0402_50V7K

2

SATA_FTX_C_DRX_P1 SATA_FTX_C_DRX_N1 SATA_FTX_DRX_N1

SATA_FRX_C_DTX_P1

1

C1219

0.1U_0402_16V4Z

2

12

C1220 1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

C318 0.01U_0402_16V7KC318 0.01U_0402_16V7K

1 2

C317 0.01U_0402_16V7KC317 0.01U_0402_16V7K

1 2

C319 0.01U_0402_16V7KC319 0.01U_0402_16V7K

1 2

C320 0.01U_0402_16V7KC320 0.01U_0402_16V7K

+3VS

+5VS

R02

@C1220

@

1

C1221

C1221 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SATA_FTX_DRX_P1

SATA_FRX_DTX_N1SATA_FRX_C_DTX_N1 SATA_FRX_DTX_P1

@

R1527

12

+3V_HDD

0_0805_5%

1 2

+5V_HDD

R1526 0_0805_5%R1526 0_0805_5%

1

@

C1222

0.1U_0402_16V4Z

2

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RSVD

19

GND

20

V12

21

V12

22

V12

SANTA_192701-1

DC010006J00

PTH PTH

NPTH NPTH

23 24

25 26

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

HDD Connector

VAUS5 LA9001P M/B

29 50Friday, May 25, 2012

E

0.3

www.qdzbwx.com

A

600ohms @100MHz 2A

1 1

Power down (PD#) power stage for save power 0V: Power down power stage

3.3V: Power up power stage

HDA_SDOUT_AUDIO<12>

HDA_BITCLK_AUDIO<12>

HDA_RST_AUDIO#<12>

2 2

MIC Sense R939 place near pin13

Capless HP Sense R940 place near pin34

3 3

wide 25MIL

SPK_R2+ SPK_R1SPK_L2+ SPK_L1-

4 4

1 2

R1553 0_0603_5%R1553 0_0603_5%

1 2

R1555 0_0603_5%R1555 0_0603_5%

1 2

R1554 0_0603_5%R1554 0_0603_5%

1 2

R1556 0_0603_5%R1556 0_0603_5%

SPK_R2+_CONN SPK_R1-_CONN SPK_L2+_CONN SPK_L1-_CONN

SPK_R1-_CONN

SPK_R2+_CONN

2

3

@

D38

PACDN042Y3R_SOT23-3

1

HDA_SYNC_AUDIO<12>

1

C1248

2

@

1000P_0402_50V7K

3

+5VS

EC_MUTE#<31>

HDA_SDIN0<12>

PLUG_IN#<32>

+MIC1_VREFO_L

1

C1249

C1250

2

@

1000P_0402_50V7K

SPK_L1-_CONN

SPK_L2+_CONN

2

@

D39

PACDN042Y3R_SOT23-3

1

P/N: SM01000EE00

MIC_JD COMBOJACK

EC_MUTE#

HDA_BITCLK_AUDIO

C1251

@

1000P_0402_50V7K

Reserve for ESD request.

A

1 2

R1531 0_0805_5%@R 1531 0_0805_5%@

R1533 0_0402_5%R 1533 0_0402_5%

R1538 0_0402_5%R 1538 0_0402_5%

HDA_SDOUT_AUDIO

HDA_RST_AUDIO#

PC_BEEP

C1239 2.2U_0402_6.3V6MC1239 2.2U _0402_6.3V6M

C1240 2.2U_0402_6.3V6MC1240 2.2U _0402_6.3V6M

C1241 4.7U_0603_6.3V6KC1241 4.7U_0603_6.3V6K

1

ACES_88266-04001

2

SE074102K80

1000P_0402_50V7K

B

600ohms @100MHz 1A P/N: SM01000BU00

+5VS +5VDDA_CODEC

L37

1 2

FBMA-L11160808601LMA10T_2P

4.7U_0603_6.3V6K

Place near Pin25

1 2

12

2

C1234

1

12

R153622_0402_5% R153622_0402_5%

12

R154120K_0402_1% R 154120K_0402_1%

12

R154339.2K_0402_1% R154339.2K_0402_1%

SDATA_INHDA_SDIN0

4.7U_0603_6.3V6K

1

C1235

2

EC_MUTE#_R

JDREF

SENSEA

CBN

CBP

1

C1236

2

0.1U_0402_16V4Z

Pin Assignment

SPK-OUT (Pin40/41/44/45)

Capless HP-OUT (Pin32/33)

JSPK1

4

6

4

G2

3

5

3

G1

2

1

ME@

SP02000K200

B

1

2

C1230

+5VS_PVDD

0.1U_0402_16V4Z

47

DAPD/COMB_JACK

4

PD#

5

SDATA-OUT

6

BIT-CLK

8

SDATA-IN

10

SYNC

11

RESET#

12

PCBEEP

19

JDREF

20

MONO-OUT(PORT-H)

13

Sense A

18

Sense-B

35

CBN

36

CBP

34

CPVEE

28

LDO-CAP

29

MIC2-VREFO

30

MIC1-VREFO-R

31

MIC1-VREFO-L

42

PVSS1

43

PVSS2

7

DVSS

C

+5VDDA_CODEC

2

9

DVDD-IO

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

SPDIF-OUT

Thermal PAD

1

C1232

2

0.1U_0402_16V4Z

Place near Pin38

24

23

22

21

17

16

15

14

40

41

44

45

33

32

48

3

2

27

VREF

26

AVSS1

37

AVSS2

49

C1233

1

4.7U_0603_6.3V6K

MIC_EXTR_C

MIC_EXTL_C

HPOUT_R

HPOUT_L

DMIC_CLK_R

DMIC_DATA_R

1

C1231

2

0.1U_0402_16V4Z

U50

39

46

PVDD1

PVDD2

S IC ALC259-VC2-CG MQFN 48P CODEC

1

25

38

AVDD1

AVDD2

DVDD1

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-R(PORT-E-R)

LINE2-L(PORT-E-L)

HPOUT-R(PORT-A-R)

HPOUT-L(PORT-A-L)

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

FunctionLocation

Internal

External

Int Speaker

Headphone out

Mic inExternalMIC1(Pin21/22)

Combo Jack detect (normal open)

R1123 47K_0402_5%R1123 47K_0402_5%

MIC_JD

1 2

2

1

C1134

4.7U_0603_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

EXT_MIC

D

1 2

R1529 0_0603_5%@R 1529 0_0603_5%@

Place near Pin1 Place near Pin9

+3VDD_CODEC

+IOVDD_CODEC

Vendor recommend. 2.2u

1 2

C1237 2.2U_0402_6.3V6MC1237 2.2U_0402_6.3V6M

1 2

C1238 2.2U_0402_6.3V6MC1238 2.2U_0402_6.3V6M

L172 FBMA-10-100505-301T_2PL172 FBMA-10-100505-301T_2P

L173 FBMA-10-100505-301T_2PL173 FBMA-10-100505-301T_2P

12

SPK_L2+

SPK_L1-

SPK_R1-

SPK_R2+

R154475_0402_5% R154475_0402_5%

R154575_0402_5% R154575_0402_5%

1

12

C1226

C1227

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

2.2K_0402_5%

12

R1534 1K_0402_5%R1534 1K_0402_5%

HP_OUTR <32>

HP_OUTL <32>

DMIC_CLK <32>

DMIC_DATA <32>

C1228

@

+MIC1_VREFO_L

R1537

Internal Speaker

Headphone

Place next to pin 27

1

12

C1242

C1243

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

R1549

1 2

0_0402_5%

R1550

1 2

@

0_0402_5%

R1551

1 2

0_0402_5%

GND GNDA

PC Beep

EC Beep

PCH Beep

Compal Secret Data

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

BEEP#<31>

FCH_SPKR<12>

D

1

C1229

2

0.1U_0402_16V4Z

1 2

R1530

1 2

BLM15BD121SN1D_0402

@

10U_0603_6.3V6M

Vendor recommend. 2.2K

EXT_MIC <32>

1

2

C1244

C1245

@

22P_0402_50V8J

1 2

C1252 0. 1U_0402_16V4ZC1252 0.1U_0402_16V4Z

1 2

PC_BEEP1

C1253 0. 1U_0402_16V4ZC1253 0.1U_0402_16V4Z

C

E

R1530

R1530 0_0402_5%

0_0402_5%

@

+3VDD_CODEC+IOVDD_CODEC+3VDD_CODEC+3VS

external MIC

0525 EMI request to add C83 and C84. Close to U50 Audio IC

DMIC_CLK

DMIC_DATA

1

C83

@ C83

@

100P_0402_50V8J

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

1 2

R1552 27_0402_5%@R1552 27_0402_5%@

1

C1247

C1247 33P_0402_50V8J

33P_0402_50V8J

@

2

C1246

R1557

1 2

33_0402_5%

12

@

R1558

R1558 10K_0402_5%

10K_0402_5%

Title

HD Audio Codec_ALC269Q-VC

Size Document Number Rev

Date: Sheet of

C84

@C84

@

100P_0402_50V8J

2

EMI

HDA_BITCLK_AUDIO

1 2

PC_BEEP

C1319 0.1U_0402_16V4ZC1319 0.1U_0402_16V4Z

Compal Electronics,Ltd.

VAUS5 LA9001P M/B

E

30 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

L38

FBM-11-160808-601-T_0603

+3VALW +EC_VCCA

1 1

2 2

3 3

4 4

1 2

C1262

0.1U_0402_16V4Z

1 2

L39

FBM-11-160808-601-T_0603

@

12

C1263 22P_0402_50V8J

+3VALW

LAN_WAKE#<26>

FCH_PWRGD<12,43>

RTC_CLK<10,14>

A

1

C1260

C1260 1000P_0402_50V7K

1000P_0402_50V7K

2

ECAGND

R1560 10_0402_5%@R1560 10_0402_5%@

1 2

R1563 47K_0402_5%R1563 47K_0402_5%

C1264

0.1U_0402_16V4Z

KSO[0..15]<32>

KSI[0..7]<32>

1 2

R1588 0_0402_5%R1588 0_0402_5%

12

R1582

@ R1582

@

10K_0402_5%

12

2

1

EC_SMB_CK2_SUS<7> EC_SMB_DA2_SUS<7>

R1586 0_0402_5%@R1586 0_0402_5%@

EC_SMB_CK1<36,37> EC_SMB_DA1<36,37>

EC_INVT_PWM<23>

EC_TACH<28>

EC_SMB_DA2_SUS

EC_SMB_CK2_SUS

EC_FAN_PWM<28>

0.1U_0402_16V4Z

12

C1255

LPC_FRAME#<10,25>

CLK_PCI_EC<10,14>

PLT_RST#<10,26>

EC_SCI#<12> BATT_LEN#<36>

KSO[0..15]

KSI[0..7]

PM_SLP_S3#<12> PM_SLP_S5#<12>

EC_SMI#<12>

CMOS_ON#<23>

EC_TX<25> EC_RX<25>

C1256

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

1

2

GATEA20<12>

KBRST#<12>

SERIRQ<10>

LPC_AD3<10,25> LPC_AD2<10,25> LPC_AD1<10,25> LPC_AD0<10,25>

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2_SUS EC_SMB_DA2_SUS

EC_INVT_PWM EC_TACH EC_PME# EC_TX EC_RX FCH_PWRGD EC_FAN_PWM

NUM_LED#: NC

XCLKO

100K_0402_5%

6 1

DMN66D0LDW-7 2N_SOT363-6

Q143A

C1257

0.1U_0402_16V4Z

C1257

0.1U_0402_16V4Z

1

2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

EC_RST# EC_SCI# BATT_LEN#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

PM_SLP_S3# PM_SLP_S5# EC_SMI#

12

R1587

+3VS

2

3

DMN66D0LDW-7 2N_SOT363-6

0.1U_0402_16V4Z

Q143B

B

C1258

12

B

C1261

1000P_0402_50V7K

C1261

1000P_0402_50V7K

1

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

C1271

C1271 20P_0402_50V8

20P_0402_50V8

2.2K_0402_5%

EC_SMB_DA2

5

4

C1259

1000P_0402_50V7K

C1259

1000P_0402_50V7K

1

2

LPC & MISC

R1578

EC_SMB_CK2

1

2

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

+3VS

+3VLP

+3VALW

9

22

33

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

GPIO

GND/GND

11

24

R1579

2.2K_0402_5%

1

C1254

C1254 100P_0402_50V8J

100P_0402_50V8J

2

+3VALW

+EC_VCCA

67

96

111

125

EC_VDD0

EC_VDD/VCC

EC_VDD/AVCC

BATT_TEMP/GPIO38

AD Input

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

EC_MUTE#/GPIO4A

CPU1.5V_S3_GATE/GPXIOA00

WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

SPI Flash ROM

PECI_KB930/GPIO41

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

GPIO

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

GPI

LID_SW#/GPXIOD04

PECI_KB9012/GPXIOD07

GND/GND

AGND/AGND

GND/GND

GND0

35

69

94

113

ECAGND

EC_SMB_DA2 <16,28>

EC_SMB_CK2 <16,28>

U51

21

GPIO0F

GPIO12

GPIO39

GPIO3B GPIO42

IMON/GPIO43

IREF/GPIO3E

SPIDI/GPIO5B

GPXIOD06

V18R

23 26 27

63 64 65 66 75 76

68 70 71 72

83 84 85 86 87 88

97 98 99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

BEEP#/GPIO10

ACOFF/GPIO13

ADP_I/GPIO3A

CHGVADJ/GPIO3F

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

FSTCHG/GPIO50

SYSON/GPIO56

VR_ON/GPIO57

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

SUSP#/GPXIOD05

KB9012QF A3 LQFP 128P_14X14

C

+5VALW

R1266

1 2

USB_ON#

10K_0402_5%

BEEP# NOVO# ACOFF

BATT_TEMP

BRDID

EC_MUTE# USB_ON# TL_CLK TL_DATA TP_CLK TP_DATA

VGATE

VLDT_EN NTC_V_R

PCH_PWR_EN

AOAC_ON#

WLAN_USB_ON#_R WLAN_USB_ON# BATT_CHG_LED# CAP_LED#

BATT_LOW_LED# SYSON

VSB_ON_R

EC_LID_OUT# Turbo_V H_PROCHOT#_EC MAINPWON_R BKOFF# PBTN_OUT#

ACIN EC_ON

LID_SW# SUSP#

+V18R

1

C1270

4.7U_0603_6.3V6K

2

C

BEEP# <30> NOVO# <32> ACOFF <37>

ADP_I <36,37>

APU_IMON <43>

12

R1571 0_0402_5%R1571 0_0402_5%

AOAC@

R1519 0_0402_5%

CAP_LED# <32> PWR_LED# <32> BATT_LOW_LED# <32>

SYSON <34,39,40> VR_ON <43>

EC_RSMRST# <12> EC_LID_OUT# <12>

R1580 0_0402_5%@R1580 0_0402_5%@

R1591 0_0402_5%R1591 0_0402_5%

BKOFF# <22,23>

PBTN_OUT# <12>

VGA_GATE# <12>

H_PROCHOT#_EC

2N7002H_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATT_TEMP <36>

EC_MUTE# <30> USB_ON# <32,33>

TL_CLK <22>

TL_DATA <22>

TP_CLK <32>

TP_DATA <32>

VGATE <43>

VLDT_EN <41> NTC_V <36>

PCH_PWR_EN <36>

AOAC_ON# <25>

12

1 2

R216 1K_0402_1%R216 1K_0402_1%

2

G

Q82

ENBKL <22>

BATT_CHG_LED# <32>

VSB_ON <36>

12 12

ACIN <16,37> EC_ON <38>

ON/OFF <32>

LID_SW# <32>

SUSP# <34,39,40,41,42>

13

D

1

C1269

S

C1269 47P_0402_50V8J

47P_0402_50V8J

2

Compal Secret Data

2012/01/15 2013/01/15

Compal Secret Data

D

3.3V +/- 5%

Vcc

100K +/- 5%

R1562

Board ID

0 1 2 3

PVT

+3VLP

@

12

R343

R343 47K_0402_5%

47K_0402_5%

H_PROCHOT# <36,43,7>

Deciphered Date

D

0

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

BRDID

WLAN_USB_ON# <25>

KB9012A2 work around

Turbo_V <36>

PROCHOT <36> MAINPWON <36,38,7>

VR1564

AD_BID

0 V

0.436 V

0.712 V

+3VALW

12

R1562

R1562 100K_0402_5%

100K_0402_5%

12

R1564

8.2K_0402_5%

E

min

typ

V

AD_BID

0.503 V

0.819 V

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

V

max

AD_BID

0 V0 V

0.289 V0.250 V0.216 V

0.538 V

0.875 V

TP_CLK

TP_DATA

TL_CLK

TL_DATA

EC_FAN_PWM

EC_TACH

EC_SMB_DA2_SUS

EC_SMB_CK2_SUS

EC_SMB_DA1

EC_SMB_CK1

EC_MUTE#

EC_PME#

VGA_GATE#

LID_SW#

WLAN_USB_ON#

PCH_PWR_EN

EMC Request

SYSON

EC_SMB_CK2_SUS

EC_SMB_DA2_SUS

BATT_TEMP

ACIN

PCH_PWR_EN

VSB_ON

Compal Electronics, Inc.

BIOS & EC I/O Port

VAUS5 LA9001P M/B

MP PVT DVT EVT

1 2

R1567 4.7K_0402_5%R1567 4.7K_0402_5%

1 2

R1569 4.7K_0402_5%R1569 4.7K_0402_5%

1 2

R341 2.2K_0402_5%R341 2.2K_0402_5%

1 2

R342 2.2K_0402_5%R342 2.2K_0402_5%

1 2

R1561 10K_0402_5%@R1561 10K_0402_5%@

1 2

R1581 10K_0402_5%R1581 10K_0402_5%

1 2

R1575 2.2K_0402_5%R1575 2.2K_0402_5%

1 2

R1576 2.2K_0402_5%R1576 2.2K_0402_5%

1 2

R1577 2.2K_0402_5%R1577 2.2K_0402_5%

1 2

R1574 2.2K_0402_5%R1574 2.2K_0402_5%

1 2

R1565 10K_0402_5%R1565 10K_0402_5%

1 2

R1585 10K_0402_5%R1585 10K_0402_5%

1 2

R1566 10K_0402_5%@R1566 10K_0402_5%@

1 2

R344 47K_0402_5%R344 47K_0402_5%

1 2

R1583 100K_0402_5%AOAC@R1583 100K_0402_5%AOAC@

1 2

R1572 100K_0402_5%@R1572 100K_0402_5%@

@

1 2

C1272 0.1U_0402_10V6K

@

1 2

C1268 100P_0402_50V8J

@

1 2

C1267 100P_0402_50V8J

1 2

C1265 100P_0402_50V8JC1265 100P_0402_50V8J

1 2

C1266 100P_0402_50V8JC1266 100P_0402_50V8J

1 2

@

R1573 4.7K_0402_5%

1 2

R1634 100K_0402_5%R1634 100K_0402_5%

1 2

@

R336 100K_0402_5%

E

+3VS

+3VALW

www.qdzbwx.com

0.3

of

31 50Friday, May 25, 2012

A

INT_KBD Conn.

KSI[0..7]

KSO[0..15]

KSO2

C1275 10 0P_0402_50V8 J@C1275 100P_ 0402_50V8J@

KSO15

1 1

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

C1280 10 0P_0402_50V8 J@C1280 100P_ 0402_50V8J@

C1281 10 0P_0402_50V8 J@C1281 100P_ 0402_50V8J@

C1283 10 0P_0402_50V8 J@C1283 100P_ 0402_50V8J@

C1285 10 0P_0402_50V8 J@C1285 100P_ 0402_50V8J@

C1287 10 0P_0402_50V8 J@C1287 100P_ 0402_50V8J@

C1289 10 0P_0402_50V8 J@C1289 100P_ 0402_50V8J@

C1291 10 0P_0402_50V8 J@C1291 100P_ 0402_50V8J@

C1293 10 0P_0402_50V8 J@C1293 100P_ 0402_50V8J@

C1295 10 0P_0402_50V8 J@C1295 100P_ 0402_50V8J@

C1297 10 0P_0402_50V8 J@C1297 100P_ 0402_50V8J@

C1299 10 0P_0402_50V8 J@C1299 100P_ 0402_50V8J@

1 2

KSI[0..7] <31>

KSO[0..15] <31>

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

C1279 10 0P_0402_50V8 J@C1279 100P_ 0402_50V8J@

C1276 10 0P_0402_50V8 J@C1276 100P_ 0402_50V8J@

C1282 10 0P_0402_50V8 J@C1282 100P_ 0402_50V8J@

C1284 10 0P_0402_50V8 J@C1284 100P_ 0402_50V8J@

C1286 10 0P_0402_50V8 J@C1286 100P_ 0402_50V8J@

C1288 10 0P_0402_50V8 J@C1288 100P_ 0402_50V8J@

C1290 10 0P_0402_50V8 J@C1290 100P_ 0402_50V8J@

C1292 10 0P_0402_50V8 J@C1292 100P_ 0402_50V8J@

C1294 10 0P_0402_50V8 J@C1294 100P_ 0402_50V8J@

C1296 10 0P_0402_50V8 J@C1296 100P_ 0402_50V8J@

C1298 10 0P_0402_50V8 J@C1298 100P_ 0402_50V8J@

C1300 10 0P_0402_50V8 J@C1300 100P_ 0402_50V8J@

1 2

B

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10

1 2

R91 3 00_0402_5%R91 300_0402 _5%

+5VS

CAP_LED #< 31>

KSO15

CAP_LED #

C

ME@

JKB1

GND1 GND2

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_88 514-02601-071

D

+3VALW

R1592

28 27

NOVO#<31 >

ON/OFF<31>

NOVO#

ON/OFF

For debug

SW4

1

3

2

4

G

NTC017-D A1J-D160T_4P

5

6

DEBUG@

J16

1 2

SHORT PA DS

R1592 100K_04 02_5%

100K_04 02_5%

1 2

D40

2

3

1

DAN202U T106_SC70-3

+3VLP

1 2

R1593

R1593 100K_04 02_5%

100K_04 02_5%

E

NOVO_BT N#

ON/OFF

2 2

12

R1625

L52

4

1

WCM-2 012-900T_4P

R1626 0_0402 _5%@R1626 0_0402_5 %@

R1614

1 2

L50

4

1

WCM-2 012-900T_4P

1 2

R1615 0_0402 _5%@R1615 0_0402_5 %@

BATT_LO W_LED#<3 1> BATT_CH G_LED#<31>

2A/Active Low

R02

U55

1

GND

VOUT

2

VOUT

VIN VIN3VOUT

4

FLG

EN

G547I2P81 U_MSOP8

470P_04 02_50V7K

USB20_N 5

1 2

@

0_0402_ 5%

3

USB20_N 5_R

3

2

USB20_P 5_R

2

1 2

@

0_0402_ 5%

3

2

+5VALW

8 7 6 5

C1324

R90

12

300_040 2_5%

PWR_ LED# BATT_LO W_LED# BATT_CH G_LED#

W=80mils

1

2

C8249

12

15P_040 2_50V8J

USB20_N 1<12 >

USB20_P 1<12>

JLED1

6

G2

5

G1

4

3

2

1

ACES_51 524-0060N-001

SP01001 4M10

ME@

USB20_P 1

8 7

B

IO Board

0.1U_040 2_16V7K

R88

USB20_N 0

USB20_N 1

3 3

4 4

R88

300_040 2_5%

R89

300_040 2_5%

USB20_N 5<12 >

USB20_P 5<12>

USB20_N 0<12 >

USB20_P 0<12>

+5VALW +USB2_VCCA

C1321

1 2

USB_ON#<31,3 3> USB_OC1 # <12>

C8247

12

15P_040 2_50V8J

C8248

12

15P_040 2_50V8J

USB20_N 5

USB20_P 5

USB20_N 0 USB20_N0_ R USB20_N1

USB20_P 0 USB20_P 0_R

LED Board

A

12

@

C1306 0.1U_0 402_10V6K

12

@

C1307 0.1U_0 402_10V6K

DMIC_CLK<30> DMIC_DATA<30>

PLUG_IN#<30> HP_OUTL<30> HP_OUTR<30 >

EXT_MIC<30>

R1619

1 2

0_0402_ 5%

L51

4

1

WCM-2 012-900T_4P

1 2

R1624 0_0402 _5%@R1624 0_0402_5 %@

+USB2_V CCA

USB20_P 0_R USB20_N 0_R

USB20_P 1_R USB20_N 1_R

USB20_P 5_R USB20_N 5_R

DMIC_CLK DMIC_DATA

PLUG_IN# HP_OUTL HP_OUTR

EXT_MIC

USB20_N 1_R

USB20_P 1_R

+3VS

JCR1

ME@

JCR1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND1

26

GND2

ACES_88 514-02401-071

SP01001 5W00

2012/01/ 15 2013/01/ 15

C

TouchPAD Module

TP_CLK<31> TP_DATA<31>

100P_04 02_50V8J

Compal Secret Data

Deciphered Date

0.1U_040 2_16V4Z

C1302

@C 1302

@

+3VS

C1301

1

C1303

@C1303

@

100P_04 02_50V8J

2

D42

@D 42

@

PSOT24C _SOT23-3

D

3

+3VS

@

3

2

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PWR_ LED#< 31> LID_SW #<31>

FCH_SCL K1<12> FCH_SDA TA1<12 >

2

1

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

KB /SW /LPC Debug Conn.

+5VALW+3VALW

JPW R1

8

7

6

TP_CLK TP_DATA

FCH_SCL K1 FCH_SDA TA1

@

0.1U_0402_10V6K

5

4

3

2

1

ACES_51 524-0080N-001

SP01001 A900

1

C1304

@

2

0.1U_0402_10V6K

E

NOVO_BT N# PWR_ LED# LID_SW # ON/OFF

VAUS5 LA9001P M/B

G2 G1

1

C1305

2

ME@

10 9

JTP1

ME@

JTP1

ME@

8

GND

7

GND

6

5

4

3

2

1

ACES_88 514-00601-071

SP01001 4M00

32 50Thursday, May 31, 2012

0.3

Power Board

www.qdzbwx.com

A

1 1

USB20_LN_R

USB30_RX_R_N0 USB30_RX_R_N0

USB30_TX_R_N0

USB30_TX_R_P0

2 2

D45

@

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

D44

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

@

I/O4

VDD

I/O3

1

2

4

3

8

6

5

4

1

2

USB30_RX_R_P0USB30_RX_R_P0

4

USB30_TX_R_N0

5

USB30_TX_R_P0

3

+USB3_VCCA

USB20_LP_R

B

follow AMD interlock suggestion

C

R1605

1 2

@

0_0402_5%

WCM-2012-900T_4P

USB20_LN<12>

USB20_LP<12>

USB30_RX_N0<12>

USB30_RX_P0<12>

USB30_TX_N0<12>

USB30_TX_P0<12>

USB20_LN USB20_LN_R

USB20_LP

R86

R86 300_0402_5%

300_0402_5%

1 2

2

C8245

C8245 15P_0402_50V8J

15P_0402_50V8J

1

USB30_RX_N0

USB30_RX_P0

C1309

0.1U_0402_16V7K

1 2

USB30_TX_C_N0

1 2

USB30_TX_C_P0

C1310

0.1U_0402_16V7K

Place TX AC coupling Cap (C1309,C1310). Close to connector

1

4

L43

1 2

R1608 0_0402_5%@R1608 0_0402_5%@

R1609

1 2

@

0_0402_5%

WCM-2012-900T_4P

1

4

L44

1 2

R1612 0_0402_5%

R1613

1

4

R1616 0_0402_5%

@

1 2

@R1613

@

0_0402_5%

WCM-2012-900T_4P

1

4

L45

1 2

@

2

3

2

3

2

3

2

3

USB20_LP_R

2

USB30_RX_R_N0

3

USB30_RX_R_P0

2

USB30_TX_R_N0

3

USB30_TX_R_P0

D

+USB3_VCCA

USB30_TX_R_P0

USB30_TX_R_N0 USB20_LP_R

USB20_LN_R USB30_RX_R_P0

USB30_RX_R_N0

W=80mils

TAITW_PUBAU1-09FNLSCNN4H0

9 1 8 3 7 2 6 4 5

JUSB1

SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX-

ME@

LP2

GND GND GND GND

E

10 11 12 13

+5VALW +USB3_VCCA

C1308

0.1U_0402_16V7K

1 2

USB_ON#<31,32> USB_OC0# <12>

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R02

U52

1

GND

2

VIN VIN3VOUT

4

EN

G547I2P81U_MSOP8

2012/01/15 2013/01/15

VOUT VOUT

FLG

220U_6.3V_M

8 7 6 5

C1311

C

W=80mils

1

C1312

1

+

470P_0402_50V7K

2

Compal Secret Data

Deciphered Date

For EMI request

FOR EMI

1

C1224

C1224 1000P_0402_50V7K

1000P_0402_50V7K

2

For EMI request

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

USB3.0 ports

VAUS5 LA9001P M/B

33 50Thursday, May 31, 2012

E

0.3

2A/Active Low

www.qdzbwx.com

A

B

C

D

E

+3VALW TO +3VS+5VALW TO +5VS +1.5V_IO to +1.5VS

+5VALW

U53

DMN3030LSS-13_SOP8L- 8

8

1

C1313

C1313 10U_0603_6.3V6M

1 1

10U_0603_6.3V6M

2

+VSB

2

G

+1.1VALW to +1.1VS

SUSP

1

2

+VSB

2

G

2 2

7

5

12

R1620

R1620 150K_0402_5%

150K_0402_5%

5VS_GATE

13

D

Q88

Q88 2N7002K_SOT23-3

2N7002K_SOT23-3

S

C4261

C4261 10U_0603_6.3V6M

10U_0603_6.3V6M

12

R390

R390 270K_0402_5%

270K_0402_5%

1.1VS_GATE

13

D

Q32

2N7002K_SOT23-3

S

12

5VS_GATE_R

R1622

82K_0402_5%

+1.1VALW +1.1VS

U15

DMN3030LSS-13_SOP8L- 8

8 7

5

1 2

R391

82K_0402_5%

4

1.1VS_GATE_R

+5VS

1 2 36

1

2

1 2 36

1

C1314

C1314 10U_0603_6.3V6M

10U_0603_6.3V6M

2

C1322

0.01U_0603_25V7K

1

C4271

C4271 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C4291

0.1U_0402_25V6

2

1

C1315

C1315 1U_0603_10V6K

1U_0603_10V6K

2

1

C4281

C4281 1U_0603_10V6K

1U_0603_10V6K

2

12

R1617

R1617 470_0603_5%

470_0603_5%

@

13

D

Q85

S

2N7002K_SOT23-3

@

12

R3861

R3861 470_0603_5%

470_0603_5%

@

13

D

Q29

S

2N7002K_SOT23-3

@

2

SUSP

G

SUSP

2

SUSP

G

+3VALW

U54

DMN3030LSS-13_SOP8L- 8

8

1

C1316

C1316 10U_0603_6.3V6M

10U_0603_6.3V6M

2

G

7

5

+VSB

12

R1621

R1621 270K_0402_5%

270K_0402_5%

R1623

1 2

3VS_GATE 3VS_GATE_R

270K_0402_5%

13

D

Q89

2N7002K_SOT23-3

S

+3VS

1 2

1

36

C1317

C1317 10U_0603_6.3V6M

10U_0603_6.3V6M

4

SUSP<39,40>

SUSP#<31,39,40,41,42> SYSON<31,39,40>

2

1

2

SUSP

DTC124EKAT146_SC59-3

C1323

0.01U_0603_25V7K

R1636

R1636 100K_0402_5%

100K_0402_5%

1 2

2

12

R1639

@R1639

@

100K_0402_5%

1

C1318

C1318 1U_0603_10V6K

1U_0603_10V6K

2

+5VALW+RTCBATT

Q99

IN

12

@

R1637

R1637 100K_0402_5%

100K_0402_5%

1

OUT

GND

3

12

R1618

R1618 470_0603_5%

470_0603_5%

@

13

D

Q86

S

2N7002K_SOT23-3

@

2

SUSP

G

+1.5V_IO

C1325

10U_0603_6.3V6M

2

SUSP#SUSP

G

PMV65XP_SOT23-3

1

2

+5VALW

12

100K_0402_5%

100K_0402_5% R1633

R1633

1.5VS_GATE

13

D

Q98

Q98 2N7002K_SOT23-3

2N7002K_SOT23-3

S

SYSON#

SYSON

R205 for power consumption easily rework

Q91

S

G

2

1 2

R1635

22K_0402_5%

12

R1640

R1640 100K_0402_5%

100K_0402_5%

D

13

+1.5VS_Q

100K_0402_5%

1 2

1.5VS_GATE_R

R1638

2

IN

R205

0_0805_5%

+5VALW

12

@

1

3

OUT

GND

+1.5VS

1

@

C1326

C1326 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C1329

0.1U_0402_16V4Z

2

Q100

Q100 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

@

1

2

C1327

C1327 1U_0603_10V6K

1U_0603_10V6K

12

R1631

R1631 470_0603_5%

470_0603_5%

@

13

D

2

G

Q96

S

2N7002K_SOT23-3

@

SUSP

3 3

+1.5V +0.75VS

12

R1627

R1627 470_0603_5%

470_0603_5%

@

13

D

2

SYSON# SUSP

G

Q93

S

2N7002K_SOT23-3

@

4 4

12

R1629

R1629 470_0603_5%

470_0603_5%

@

13

D

2

G

Q95

S

2N7002K_SOT23-3

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/30 2013/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sh eet of

D

Date: Sh eet of

Compal Electronics, Inc.

DC-DC INTERFACE

VAUS5 LA9001P M/B

34 50Fr iday, May 25, 2012

E

www.qdzbwx.com

0.3

5

4

3

2

1

12

PC103

+RTCBATT

VIN

100P_0402_50V8J

12

PC104

1000P_0402_50V7K

+3VLP

PR127

PR127 0_0402_5%

0_0402_5%

1 2

RTCVREF

D D

JDCIN1

ACES_87302-0401-003

C C

GND

1

2

3

4

5

6

PF101

7A_24VDC_429007.WRML

21

APDIN1APDIN

12

PC101

SMB3025500YA_2P

12

1000P_0402_50V7K

PL101

1 2

100P_0402_50V8J

PC102

+CHGRTC

JRTC2

- +

MAXEL_ML1220T10@

PR131

560_0603_5%

12

1 2

PR132

560_0603_5%

1 2

PD109

RB751V-40_SOD323-2

12

1 2

PD108

RB751V-40_SOD323-2

RTC Battery

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR DCIN / Vin Detector /Pre-charge

LA9001P

1

35 48Friday, May 25, 2012

0.1

www.qdzbwx.com

5

4

3

2

1

JBATT2

@ JBATT2

@

SUYIN_200082GR007G201ZR

D D

C C

GND GND

JBATT3

@ JBATT3

@

SUYIN_200082GR007G201ZR

GND GND

VMB2

1

2

3

3 4 5 6 7

1 2 3 4 5 6 7

EC_SMCA

4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

EC_SMDA

12

PR201

100_0402_1%

PR201

100_0402_1%

12

PR202

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

100_0402_1%

1 2

PR203

6.49K_0402_1%

1 2

PR204

PR204 10K_0402_5%

10K_0402_5%

21

VMB

PL201

SMB3025500YA_2P

1 2

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <31,37>

EC_SMB_DA1 <31,37>

+3VALW

BATT_TEMP <31>

A/D

BATT+

12

PC202

0.01U_0402_25V7K

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

VL

12

PC203

@PC203

@

0.1U_0603_16V7K

PR213

@PR213

@

0_0402_5%

MAINPWON<3 1,38,7>

H_PROCHOT#<31,43,7>

PROCHOT<31>

1 2

13

D

2

G

PQ201

@

PQ201

@

S

SSM3K7002FU_SC70-3

1 2

PR208

100K_0402_1%

OTP_N_003

ADP_OCP_1

PR212

@PR212

@

0_0402_5%

+3VS

1 2

90W(DIS) : PR205=4.42K PR210=27.4K 65W(UMA) : PR205=402(SD034020080)

PU201

@PU201

@

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1U_SOT23-8

8

7

6

5

For KB930 --> Keep PU201 circuit (Vth = 1.25V)

For KB9012 (Red circle) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212

OTP_N_002

ADP_OCP_2

+EC_VCCA

PR209

@PR209

@

10K_0402_1%

1 2

PR210

@PR210

@

27.4K_0402_1%

12

12.7K_0402_1%

12

@PR232

@

PR206

Turbo_V_2

PR227

0_0402_5%

PR232

0_0402_5%

12

PR205

1.65K_0402_1%

1 2

Turbo_V

ADP_I <31,37>

PR211

10K_0402_1%

1 2

<31>

12

PR207

@PR207

@

21.5K_0402_1%

PR231

0_0402_5%

1 2

PR230

@PR230

@

47K_0402_1%

PR233

@PR233

@

47K_0402_1%

+3VLP

12

PH201

100K_0402_1%_NCP15WF104F0 3RC

12

PR235

0_0402_5%

PR234

@PR234

@

0_0402_5%

1 2

+3VALW

ECAGND

PR210=5.11K

<31>

NTC_V

PR214

PQ202

12

2

G

+3VALW+3VLPP2

PR215

100K_0402_1%

1 2

13

D

S

2

G

4

13

D

PQ203

2N7002KW_SOT323-3

S

BATT_OUT <37>

SPOK<38,41>

PCH_PWR_EN< 31>

VSB_ON<31>

PR222

100K_0402_1%

PQ205

TP0610K-T1-E3_SOT23-3

B+

VL

PR224

1 2

PR229

@PR229

@

0_0402_5%

PR228

@PR228

@

0_0402_5%

PR236

0_0402_5%

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

12

Issued Date

PR224 1K_0402_5%

1K_0402_5%

1 2

3

12

22K_0402_1%

13

D

2

G

2N7002W-T/R7_SOT323-3

G

2N7002W-T/R7_SOT323-3

S

PC207

1U_0402_6.3V6K

2011/10/12 2013/10/12

12

PR220

1 2

PQ204

Compal Secret Data

12

PC205

PR216

100K_0402_1%

Deciphered Date

0.22U_0603_25V7K

13

2

12

PC206

0.1U_0603_25V7K

+VSBP

PJ201

@PJ201

@

JUMP_43X39

2

112

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PWR-BATTERY CONN/OTP

+VSB

LA9001P

1

36 48Friday, May 25, 2012

0.1

B B

PR223

PR225

12

PC204

0.01U_0402_25V7K

3

+

2

-

8

P

O

G

LM393DG_SO8

4

10M_0402_5%

1 2

1

PU202A

PR218

+3VLP

BATT_LEN#<31>

100K_0402_1%

1 2

2N7002KW_SOT323-3

PR226

100K_0402_1%

VMB2

PR217

887K_0402_1%

1 2

PR221

180K_0402_1%

1 2

A A

10K_0402_1%

1 2

2VREF_8205

RTCVREF

PR219

1 2

10K_0402_1%

1 2

@ PR225

@

10K_0402_1%

5

www.qdzbwx.com

5

PQ301

PQ301 AO4407A_SO8

AO4407A_SO8

VIN

D D

C C

B B

PACIN

ACON

ACOFF<31>

12

DTA144EUA_SC70-3

PR301

47K_0402_5%

2

61

2

PQ307A

PQ307A 2N7002KDW -2N_SOT363-6

2N7002KDW -2N_SOT363-6

PACINPACIN

PR321

1 2

10K_0402_5%

BATT_OUT<36,3 7>

8 7

5

PQ304

2

13

1 3

PQ305

DTC115EUA_SC70-3

PR318

47K_0402_1%

1 2

PQ311

DTC115EUA_SC70-3

2

ACOFF-1

12

PR325

PR325 0_0402_5%

0_0402_5%

13

D

2

G

S

4

PR308

150K_0402_1%

13

PQ313

2N7002KW_S OT323-3

P2

PQ302

AO4423_SO8

1 2 36

12

P2-1

12

P2-2

34

5

1 2 3 6

12

PC301

PR303

200K_0402_1%

0.1U_0603_25V7K

PQ307B

2N7002KDW-2N_SOT363-6

AO4423_SO8

4

12

20K_0402_1%

13

D

S

PR317

1 2

64.9K_0603_1%

5600P_0402_25V7K

PR307

PQ308

2N7002KW_S OT323-3

2

G

PR314

EC_SMB_DA1<31,36>

EC_SMB_CK1<31,36>

CHGVADJ=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

A A

CHGVADJ

0V

1.882V

3.2935V

BQ24727VDD

12

PR335

47K_0402_1%

PQ316

ACPRN<37>

2

G

8 7

5

1 2

PC304

BATT_OUT <36,37>

VIN

12

390K_0603_1%

12

PC370

0.1U_0603_25V7K

+3VALW

12

PR336

PR336 10K_0402_1%

10K_0402_1%

13

D

S

2N7002KW_SOT323-3

@

4

P3

PR315

2.2K_0402_5%

+3VALW

@

1 2

PR323

316K_0402_1%

100K_0402_1%

PR337

10K_0402_1%

1 2

PACINPACIN

12

PR339

12K_0402_1%

<37>

PR316

2.2K_0402_5%

ADP_I<31,36>

1 2

PC312

100P_0603_50V8

PR326

ACPRN

PR312

@PR3 12

@

39.2K_0402_1%

6

7

8

9

10

12

ACIN <16,31>

B+

PR302

0.01_1206_1%

1

2

ACDET

IOUT

SDA

SCL

ILIM

4

3

ACP

PC308

0.1U_0603_25V7K

1 2

+3VALW

12

PR309

@

100K_0402_1%

1 2

@

1 2

5

ACOK

4

PU301

CMPIN

@

@PR3 13

@

4.7M_0603_1%

3

12

BQ24727RGRR_VQFN20_ 3P5X3P5

SA000051W00

SRN12BM

11

13 12

12

PR327

6.8_0603_5%

12

PC373

0.1U_0603_25V7K

12

0.1U_0603_25V7K

CMPOUT

SRP

PR310

PR313

PR328

PC374

3

SH00000Q100

PL301

1UH_MNR-4018-1R0N -F_3A_30%

1 2

ACN

PC309

0.1U_0603_25V7K

12

10K_0603_1%

10_0603_5%

2

ACP

GND

14

PC310

0.1U_0603_25V7K

1

ACN

TP

VCC

PHASE

HIDRV

BTST

REGN

LODRV

15

DL_CHG

12

PL301

1 2

PC302

@ PC302

@

10U_0805_25V6K

12

21

20

BQ24727VCC

19

LX_CHG LX_C HG

18

DH_CHG

17

BST_CHG

16

12

PC376

1U_0603_25V6K

PC375

@ PC375

@

0.1U_0603_25V7K

PC315

1 2

@ PC315

@

10U_0805_25V6K

P2

PR319

10_1206_5%

1 2

PC313

1U_0603_25V6K

1 2

PR324

2.2_0603_5%

1 2

12

PD303

RB751V-40_SOD323-2

1 2

0.047U_0603_16V7M

BQ24727VDD

PC303

4.7U_0805_25V6-K

PC314

2

CHG_B+

PQ303

AO4407A_SO8

1 2 3 6

PD301

ACOFF-1

1 2

CHG

1SS355_SOD323-2

1 2

4

PD302

PD302 1SS355_SOD323-2

1SS355_SOD323-2

PC307

1 2

PC305

4.7U_0805_25V6-K

12

PC307

1 2

PC306

2200P_0402_50V7K

4.7U_0805_25V6-K

6

578

4

6

578

4

DISCHG_G

PR304

200K_0402_1%

1 2

PR305

PR305 47K_0402_1%

47K_0402_1%

1 2

DISCHG_G-1

PQ306

13

DTC115EUA_SC70-3

2

PQ310

AO4466L_SO8

PL302

10UH_PCMB063T-100MS _4A_20%

123

PQ312

AO4466L_SO8

1 2

12

PR322

@PR3 22

@

4.7_1206_5%

6251_SN

12

PC377

@PC3 77

@

680P_0603_50V7K

8 7

5

1 2

12

PC311

0.1U_0603_25V7K

PR320

0.01_1206_1%

1

2

SRPS RP

1

VIN

PR306

PR306 200K_0402_1%

200K_0402_1%

PQ309

2N7002W- T/R7_SOT323-3

13

D

2

PACINPACIN

G

S

4

3

SRNSRN

12

PC371

10U_0805_25V6K

BATT+

12

PC372

10U_0805_25V6K

www.qdzbwx.com

For disable pre -charge circui t.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2013/10/122011/10/12

2

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

LA9001P

37 48Fr iday, May 25, 2012

1

0.1

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

2VREF_8205

3

2

PJ402

@P J402

@

JUMP_43 X118

+3VALW P +3VALW

2

1

112

D D

PR401

13K_040 2_1%

1 2

PR403

RT8205_B+

PJ401

@P J401

B+

C C

B B

A A

@

JUMP_43 X118

2

12

PC405

0.1U_0603_25V7K

112

12

PC402

0.1U_0603_25V7K

12

PC403

+3VALWP

5

4.7U_0805_25V6-K

PC415

PC415 150U_B2 _6.3VM_R35M

150U_B2 _6.3VM_R35M

MAINPWON<31,36,7>

12

6

PR414

578

4

123

578

PQ403

PQ403 AO4712_ SO8

AO4712_ SO8

3 6

241

61

2

12

13

2

PC423

4.7U_0603_6.3V6M

4

PC406

PC404

PQ401

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

1

+

2

2N7002K DW-2N_SOT3 63-6

EC_ON<31>

PR418

2.2K_040 2_5%

PR413

PR413 0_0402_ 5%

0_0402_ 5%

1 2

12

AO4466L _SO8

PL401

VL

12

@

PQ401

12

PR409

@

4.7_1206_5%

12

PC418

@

680P_0603_50V7K

PQ405A

100K_04 02_1%

12

PR417

40.2K_0402_1%

Typ: 175mA

PC411

34

PQ405B

PQ405B 2N7002K DW-2N_SOT3 63-6

2N7002K DW-2N_SOT3 63-6

5

PQ406

PQ406 DTC115E UA_SC70-3

DTC115E UA_SC70-3

12

4.7U_0805_10V6K

1 2

PC412

0.1U_060 3_25V7K

B+

ENTRIP2ENT RIP1

+3VLP

PR407

1 2

2.2_0603 _5%

PR411

499K_04 02_1%

1 2

12

PR412

100K_0402_1%

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR403

20K_040 2_1%

1 2

PR405

130K_04 02_1%

1 2

25

7

8

9

BST_3V

10

UG_3V

11

LX_3V

12

LG_3V

12

PC420

1U_0603_10V6K

2VREF_8205

PU401

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

12

PC401

1U_0603_10V6K

PR402

30K_040 2_1%

1 2

PR404

19.6K_04 02_1%

1 2

PR406

66.5K_04 02_1%

ENTRIP2

3

4

5

6

FB2

TONSEL

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

15

13

RT8205_ B+

2011/10/ 12 2013/10/ 12

3

12

1 2

ENTRIP1

2

1

FB1

REF

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

VIN16GND

17

12

PC422

0.1U_0603_25V7K

Typ: 175mA

PC421

4.7U_0805_10V6K

Compal Secret Data

Deciphered Date

24

23

22

BST_5V

21

UG_5V

20

LX_5V

19

LG_5V

RT8205E GQW_W QFN24_4X4

VL

PC407

4.7U_0805_25V6-K

PR408

2.2_0603 _5%

1 2

RT8205_ B+

12

PC408

4.7U_0805_25V6-K

SPOK <36,41>

PC413

0.1U_060 3_25V7K

1 2

PJ403

@P J403

@

JUMP_43 X118

+5VALW P +5VALW

12

PC409

2

12

PC410

0.1U_0603_25V7K

2200P_0402_50V7K

5

PQ404

4

AO4456_SO8

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

Title

Size Do cument Number Rev

Custom

Date: Sheet of

2

112

678

PQ402

AO4406AL_SO8

35241

AO4406AL_SO8

PL402

12

@

12

@

PL402

1 2

PR410

4.7_1206_5%

PC419

680P_0603_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

786

123

Compal Electronics, Inc.

3VALWP/5VALWP

LA9001P

1

+5VALWP

1

+

PC417

PC417 150U_B2 _6.3VM_R35M

150U_B2 _6.3VM_R35M

2

38 48Friday, May 25, 2012

0.1

www.qdzbwx.com

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

1 1

S4/S5

HiLo

Lo Lo

On

Off

On

Off (Hi-Z)

Off Off

Note: S3 - sleep ; S5 - power off

+0.75VSP

12

PC506

PC504

10U_0805_25V6K

+VTT_REFP

2 2

PR503

0_0402_5%

SUSP#<31,34,40,41,42>

1 2

SYSON<31,34,40>

1U_0402_16V6K

@

2N7002KW_S OT323-3

12

PC512

1U_0402_16V6K

SUSP<34,40>

3 3

PJ504

@PJ 504

@

JUMP_43X118

+3VALW

2

112

PXS_PWREN<12,17,42>

4 4

1.8VSP_VIN

12

PC513

PC513 22U_0805_6.3VAM

22U_0805_6.3VAM

1 2

PR513

100K_0402_1%

PD501

1 2

RB751V-40_SOD323-2

EN_1.8VSP

1M_0402_5%

PQ501

PR514

2

G

+1.5VP

12

PC507

0.033U_0402_16V7K

0_0402_5%

1 2

0.1U_0402_16V7K

13

D

S

SY8033BDBC_DFN10_3X3

12

PC518

1 2

PR504

0.22U_0402_10V5K

10

9

8

5

PC508

@PC5 08

@

5.76K_0402_1%

PU502

21

1

2

3

4

5

PVIN

SVIN

EN

11

PU501

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

12

PR508

4

PG

TP

NC

7

12

@ PC532

@

0.1U_0402_10V7K

B

+1.5VP

PJ5025

@PJ 5025

@

1

JUMP_43X39

1

2

18

20

19

VTT

BOOT

VLDOIN

RT8207MZQW _WQFN20_3X3

FB

S5

S3

6

8

7

S5_1.5V

S3_1.5V

5.9K_0402_1%

FB=0.75V

12

To GND = 1.5V To VDD = 1.8V

2

1.8VSP_LX

LX

3

LX

6

FB

NC

1

PC532

UG_1.5V

LX_1.5V

PR507

2.2_0603_5%

1 2

BST_1.5V BST_1.5V-1

16

17

PHASE

PR510

UGATE

TON

9

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

+3VALW

PGOOD

10

PR501

887K_0402_1%

12

1.5V_B+

12

1UH_PH041H-1R0MS_3. 8A_20%

1 2

12

PR511

4.7_1206_5%

@

12

PC515

@

680P_0603_50V7K

1.8VSP_FB

PR505

8.66K_0402_1%

12

PR509

@

PGOOD_1.5V

10K_0402_5%

PL501

20K_0402_1%

FB=0.6Volt

10K_0402_1%

12

PC503

1U_0603_10V6K

PR512

PR515

PC502

0.1U_0603_25V7K

1 2

LG_1.5V

12

1U_0603_10V6K

12

PR502

5.1_0603_5%

PC511

12

PC514

68P_0402_50V8J

4

12

C

5

PQ503

TPCA8065-H_PPAK56-8 -5

123

5

PQ502

123

+5VALW

12

PC516

22U_0805_6.3VAM

D

PJ501

@PJ501

@

1.5V_B+

12

PC509

4.7U_0805_25V6-K

PL502

1UH_PCMC063T-1R0M N_11A_20%

12

PR506

@PR5 06

@

4.7_1206_5%

12

PC510

@PC5 10

@

680P_0402_50V7K

TPCA8057-H_PPAK56-8-5

PL502

1 2

JUMP_43X118

PC501

4.7U_0805_25V6-K

+1.5VP +1.5V_IO

2

112

1

+

2

+1.5VP OCP(min) =18.7A +1.5VP OCP(max) =23.2A

2

B+

PC505

PC505 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

PJ505

@PJ 505

@

JUMP_43X118

112

PJ506

@PJ 506

@

JUMP_43X118

112

PJ507

@PJ 507

@

JUMP_43X39

2

112

+1.5VP

+1.5V

+0.75VS+0.75VSP

+1.8VSP

PJ503

@PJ 503

@

JUMP_43X118

2

112

PC517

22U_0805_6.3VAM

1.8VSP max current=4A

+1.8VGS+1.8VSP

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

C

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PWR-+1.5VP/+0.75VSP/+1.8VSP

LA9001P

D

39 48Friday, May 25, 2012

0.1

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

1 1

S0

S3

S4/S5

Hi Hi

HiLo

Lo Lo

On

Off

On

Off (Hi-Z)

Off Off

Note: S3 - sleep ; S5 - power off

+0.75VSP_DDR3L

12

PC523

PC522

2 2

10U_0805_25V6K

+VTT_REFP_DDR3L

12

+1.5VP_DDR3L

PC526

0.033U_0402_16V7K

PR521

@PR5 21

@

0_0402_5%

SUSP#<31,34,39,41,42>

SYSON<31,34,39,40>

3 3

1 2

PC529

1U_0402_16V6K

SYSON<31,34,39,40>

DDR3L_EN#<12>

12

2N7002KW_S OT323-3

SUSP<34,39>

@

PQ506

2

G

13

D

S

PR528

@PR5 28

@

0_0402_5%

1 2

0_0402_5%

PR527

@PR5 27

@

0.1U_0402_16V7K

PR522

@PR5 22

@

0_0402_5%

1 2

@PC5 30

@

0.1U_0402_16V7K

49.9K_0402_1%

2N7002KW_S OT323-3

PC531

@PC5 31

@

PC530

21

1

2

3

4

5

PQ507

12

PU503

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

12

PR525

2

G

B

+1.5VP_DDR3L

PJ508

@

1

JUMP_43X39

1

2

BST_1.5V_DDR3L BST _1.5V-1_DDR3LBST_1.5V -1_DDR3L

18

19

VLDOIN

S3

7

S3_1.5V_DDR3L

12

PR526

12.7K_0402_1%

17

BOOT

UGATE

S5

TON

8

9

S5_1.5V_DDR3L

PR524

10K_0402_1%

FB=0.75V To GND = 1.5V To VDD = 1.8V

20

VTT

RT8207MZQW _WQFN20_3X3

FB

6

12

13

D

S

PR516

2.2_0603_5%

1 2

16

PHASE LGATE

PGND

CS

VDDP

VDD

PGOOD

10

PR523

887K_0402_1%

12

UG_1.5V_DDR3L

LX_1.5V_DDR3L

15

14

PR518

11K_0402_1%

13

12

11

+3VALW

12

PR520

@

12

1.5V_B+_DDR3L1. 5V_B+_DDR3L

PC521

0.1U_0603_25V7K

1 2

LG_1.5V_DDR3L

12

PC527

1U_0603_10V6K

PGOOD_1.5V_DDR3L

10K_0402_5%

5.1_0603_5%

PC528

1U_0603_10V6K

PR519

4

12

C

5

PQ504

TPCA8065-H_PPAK56-8 -5

123

5

PQ505

123

+5VALW

D

PJ509

@PJ509

@

1.5V_B+_DDR3L

12

PC520

4.7U_0805_25V6-K

PL1

1UH_PCMC063T-1R0M N_11A_20%

12

PR517

@PR517

@

4.7_1206_5%

12

PC525

@PC525

@

680P_0402_50V7K

TPCA8057-H_PPAK56-8-5

PL1

1 2

+1.5VP_DDR3L

JUMP_43X118

PC519

4.7U_0805_25V6-K

112

2

1

+

2

B+

PC524

PC524 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

PJ510

112

JUMP_43X118@

PJ511

112

JUMP_43X118@

PJ512

2

112

JUMP_43X39

@

+1.5VP_DDR3L

+1.5V

+0.75VS+0.75VSP_DDR3L

www.qdzbwx.com

DDR3L_EN#=high => 1.5V DDR3L_EN#=low => 1.35V

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

PWR-+1.5VP/+1.8VSP

Size D ocument Number Rev

Custom

Date: Sheet of

LA9001P

D

40 48Friday, May 25, 2012

0.1

5

PR601

SPOK<36,38>

D D

+5VALW

+3VALW

C C

PR606

@PR606

@

0_0402_5%

VLDT_EN<31>

SUSP#<31,34,39,40,42>

B B

1 2

PR609

300K_0402_1%

1 2

@

1 2

0_0402_5%

1M_0402_5%

PJ601

2

JUMP_43X118@

PJ607

2

JUMP_43X118

@

PR607

1 2

75K_0402_1%

12

PC614

PR610

47K_0402_1%

0.1U_0402_16V7K

PR602

1 2

112

TRIP_+1.2VSP

EN_+1.2VSP

FB_+1.2VSP

RF_+1.2VSP

12

PR612

470K_0402_1%

4

@PC601

@

12

PC601

0.1U_0402_10V7K

1.1V_LX 1.1V_LX

12

PC602

22U_0603_6.3V6K

PU602

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51212DSCR_SON10_3X3

PR613

7.15K_0402_1%

12

PU601

PU601 SY8809DFC_DFN8_2X2

SY8809DFC_DFN8_2X2

1

EN

FB

2

IN

PG

3

LX

4

GND

10

VBST

9

DRVH

8

SW

7

V5IN

6

DRVL

11

TP

8

7

6

5

10K_0402_1%

BST_+1.2VSP

UG_+1.2VSP

SW_+1.2VSP

+1.2VSP_5V

LG_+1.2VSP

PR605

0.47UH_PCMC063T-R47MN_17.5A_20%

12

PR603

@

12

PC606

@

12

PR608

1 2

2.2_0603_5%

1 2

4.7_1206_5%

680P_0603_50V7K

12

3

PL601

PR604

8.45K_0402_1%

1 2

PC607

1 2

220P_0402_50V

PC612

0.1U_0603_25V7K

1 2

+5VALW

PC613

PC613 1U_0603_6.3V6M

1U_0603_6.3V6M

2

1

12

+

PC620

2

PC603

@

PQ601

PQ602

4

PC603

47U_0805_6.3V6M

150U_B2_6.3VM_R45M

678

35241

786

5

47U_0805_6.3V6M

+1.2VSP_B+

AO4406AL_SO8

@

AO4456_SO8

123

@

12

PC605

PC604

@

47U_0805_6.3V6M

12

PC608

0.1U_0402_25V6

PL602

1UH_PCMC063T-1R0MN_11A_20%

1 2

12

PR611

4.7_1206_5%

12

PC617

680P_0603_50V7K

12

PC622

PC621

22U_0603_6.3V6K

12

PC609

2200P_0402_50V7K

12

PJ602

2

JUMP_43X118

@

12

PC610

4.7U_0805_25V6-K

112

PC611

4.7U_0805_25V6-K

+1.1VALWP

1

+

PC615

2

220U_D2_4VY_R15M

+1.1VALW+1.1VALWP

PJ603

@PJ603

@

2

JUMP_43X118

PC616

112

B+

+1.2VSP

12

1U_0603_10V6K

1

PJ604

@PJ604

@

2

JUMP_43X118

+1.2VS+1.2VSP

112

+1.2VSP OCP(min)=15.34A

PR614

PR614 10K_0402_1%

10K_0402_1%

1 2

PU603

APL5508-25DC-TRL_SOT89-3

PJ605

+3VS

A A

5

4

112

JUMP_43X39@

2

1U_0603_10V6K

PC618

APL5508-25DC-TRL_SOT89-3

2

12

PJ606

IN

3

OUT

GND

1

12

PC619

4.7U_0805_6.3V6K

3

+2.5VSP

PR615

@PR615

@

10K_1206_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/10/12 2013/10/12

(0.38A,20mils ,Via NO.=1)

PJ606

2

112

JUMP_43X39@

Compal Secret Data

Deciphered Date

2

+2.5VS+2.5VSP

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

PWR +1.1VALWP/+1.2VSP/+2.5VSP

LA9001P

1

41 48Friday, May 25, 2012

0.1

www.qdzbwx.com

A

+VGA_COREP

12

PR802

12

20

21

PAD

GSNS

V3

V2

TPS51518RUKR_QFN20_3X3

V1

V0

VREF

6

12

PC817

PR824

0_0402_5%

1 2

PR825

0_0402_5%

1 2

PR802 0_0402_5%

0_0402_5%

4700P_0402_25V7K

VSNS

7

0.1U_0402_10V7K

PXS_PWREN<12,17,39,42>

PR803

41.2K_0402_1%

1 2

PC807

19

18

TRIP

SLEW

VID08PGOOD

VID19EN

1 1

PC806

10P_0402_25V8J

1 2

PC801

PR805

10.7K_0402_1%

PR809

6.04K_0402_1%

GPU_VID0

GPU_VID1

1 2

PC818

0.1U_0402_16V7K

PC801

10P_0402_25V8J

PU801

1

2

1 2

3

PR807

10.7K_0402_1%

4

1 2

5

1 2 12

PR810

93.1K_0402_1%

+3VS

12

PR811

10K_0402_1%

VRON_VGA

PR801

0_0402_5%

1 2

PR804

12

100K_0402_1%

2 2

PR812

0_0402_5%

1 2

PR814

PR814 0_0402_5%@

0_0402_5%@

1 2

GPU_VID0

GPU_VID1

GPU_VID0<16>

GPU_VID1<16>

PR813

16K_0402_1%

1 2

PR822

PR822 10K_0402_5%

10K_0402_5%

1 2

PR823

PR823 10K_0402_5%

10K_0402_5%

1 2

VGA_PWRGD<12,15>

PXS_PWREN<12,17,39,42>

SUSP#<31,34,39,40,41>

3 3

PR820

@ PR820

@

10k_0402_5%

@

1 2

PR821

PR821 10k_0402_5%

10k_0402_5%

1 2

+3VS

17

GND

10

PXS_PWREN

DRVL

DRVH

B

5

4

16

MODE

15

V5IN

14

13

12

SW

11

BST

12

PR808

2.2_0603_5%

+5VALW

PC808

1U_0603_10V6K

UGATE2_VGA

12

BOOT2_2_VGABOOT2_VGA

LGATE2_VGA

PC816

0.1U_0603_25V7K

1 2

123

4

123 5

Seymour

GPU_VID1

GPU_VID0

Core Voltage Level

1

0

PD801

@ PD801

@

RB751V-40_SOD323-2

1 2

PR816

40.2K_0402_1%

1

0

1

0

@

0.9V

1.0V

1.1V

1.15V

+5VALW

12

PC819

PC819 1U_0402_6.3V6K

1U_0402_6.3V6K

6

PU802

7

POK

8

EN

12

PR818

PC822

20K_0402_1%

0.1U_0603_25V7K

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

APL5912-KAC-TRL_SO8

1

PQ801

TPCA8065-H_SOP-ADV8-5

PQ802

TPCA8057-H 1N PPAK56-8

+1.5V_IO

@

1

PJ804

1

JUMP_43X79

2

12

1.15K_0402_1%

4.53K_0402_1%

C

VGA_CORE_B+

PC820

4.7U_0805_6.3V6K

12

PR817

12

PR819

12

PC803

PC802

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

PL801

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1 2

12

PR806

@ PR806

@

4.7_1206_5%

12

PC815

@ PC815

@

680P_0603_50V7K

+VGA_COREP +VGA_CORE

+VGA_PCIEP +1.0VGS

12

PC823

22U_0603_6.3V6K

PC821

0.01U_0402_25V7K

12

PC804

4.7U_0805_25V6-K

+VGA_PCIEP

PC805

1

+

2

PJ801

@ PJ801

@

2

112

JUMP_43X118

4.7U_0805_25V6-K

1

+

PC809

PC810

2

@

330U_D2_2VM_R9M

+VGA_COREP Iocp=32.5A

PJ802

2

JUMP_43X118@

PJ803

2

JUMP_43X118@

PJ805

2

JUMP_43X79

@

PC811

2

330U_D2_2VM_R9M

112

1.0VVGA_PCIE

PR819 4.53K

D

B+

+VGA_COREP

1

PC812

PC813

PC814

2

10U_0603_6.3V6M

1.1 V

3K

PC814

2

10U_0603_6.3V6M

www.qdzbwx.com

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/10/12 2013/10/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-VGA_CORE/VGA_PCIE

Size Document Number Rev

Date: Sheet of

LA9001P

D

42 48Friday, May 25, 2012

0.1

5

PC901

PR901

PC903

12

PR902

2.87K_0 402_1%

12

PR901

2K_0402 _1%

12

PR907

301_040 2_1%

PR914

10K_040 2_1%

12

137K_04 02_1%

12

PR903

330P_04 02_50V7K

PR906

0_0402_ 5%

PC905

@ PC90 5

@

1000P_0 402_50V7 K

PR910

649_040 2_1%

@

220P_04 02_50V7K

12

330P_04 02_50V7K

1000P_0 402_50V7 K

12

12

PC914

12

APU_VDDNB _SEN_H<7 >

PR905

10_0402 _5%

+APU_CORE_NB

VSUMP_NB

D D

VSUMN_NB

12

PH901

10K_0402_5%_ERTJ0ER103J

12

PR908

2.61K_0402_1%

PR909

1 2

11K_0402_1%

PC913

0.1U_060 3_25V7K

1 2

12

1 2

PC906

PC907

0.1U_0402_25V6

0.047U_0402_25V6

PR913

@PR 913

@

100_040 2_1%

After rev1.1 mu st change to 1 33k

PU901

PR915

PC915

+3VS

12

1000P_0 402_25V6 K

1 2

PR927

@PR 927

@

100K_04 02_5%

PR961

@PR9 61

@

0_0402_ 5%

PC915

PR916

0_0402_ 5%

+5VS

+1.5VS

VR_ON<31>

PR939

0_0402_ 5%

PR941

0_0402_ 5%

PR918 0_ 0402_5%PR918 0_ 0402_5%

PR924 0_ 0402_5%PR924 0_ 0402_5%

PR926 0_ 0402_5%PR926 0_ 0402_5%

PR928 0_ 0402_5%PR928 0_ 0402_5%

PR930 0_ 0402_5%PR930 0_ 0402_5%

PR933 0_ 0402_5%PR933 0_ 0402_5%

PR935 0_ 0402_5%PR935 0_ 0402_5%

PR937 0_ 0402_5%@PR9 37 0_0402 _5%@

12

PR944

2.61K_0402_1%

12

PH904

10K_0402_5%_ERTJ0ER103J

12

PC935

0.1U_060 3_25V7K

APU_SVC<7>H_PRO CHOT#<31 ,36,7>

APU_SVD<7>

1 2

APU_SVT<7>

12

APU_PW RGD<10 ,7>

FCH_PWR GD<12 ,31>

+5VS

VSUM+

VSUM-

133K_04 02_1%

PR922 27.4K_040 2_1%PR922 27.4K_0 402_1%

12

PH902

470K_04 02_5%_TSM0B 474J4702R E

C C

APU_IMON

After rev1.1 mu st change to 1 33k

B B

12

PR925

10.5K_0402_1%

10.5K_0402_1% PR934

PR934

0_0402_ 5%

PR936

133K_04 02_1%

1 2

PC921

1000P_0 402_25V6 K

1 2

PR938 27 .4K_0402_ 1%PR938 2 7.4K_0402 _1%

PH903

470K_04 02_5%_TSM0B 474J4702R E

12

PR942

10.5K_0 402_1%

12

PU901

1

12

ISEN2_NB

2

NTC_NB

3

IMON_NB

4

12

SVC

5

12

VR_HOT_L

12

6

SVD

7

12

VDDIO

12

8

SVT

9

12

ENABLE

10

12

PWROK

11

IMON

12

NTC

12

ISEN3

ISEN2

PR943

PR943 10K_040 2_1%

10K_040 2_1%

1 2

PC928

PR947

1 2

11K_0402_1%

0.047U_0402_25V6

PR957

@ PR95 7

@

100_040 2_1%

PC929

0.1U_0402_25V6

0.1U_0402_25V6 698_040 2_1%

698_040 2_1%

12

PC902

390P_04 02_50V7K

12

PC904

100P_04 02_50V8J

12

46

47

48

ISEN1_NB

ISUMP_NB

ISUMN_NB

ISL6277 HRTZ-T_TQFN48_6X6

ISEN3

15

14

13

12

PR954

12

PC936

@ PC93 6

@

820P_04 02_50V7K

12

4

PR904

@ PR90 4

@

32.4K_0 402_1%

43

COMP_NB

18

1 2

41

42

FCCM_NB

PGOOD_NB

RTN19ISUMN17ISEN1

FB220VSEN

PC930

330P_0402_50V7K

1 2

PC937

12

FCCM_NB

38

39

40

LGATEX

PHASEX

PWM2_NB

COMP

FB21PGOOD

22

23

PC926

1000P_0 402_25V6 K

12

1.62K_0 402_1%

0.01U_0402_25V7K

37

UGATEX

UGATE2

PHASE2

LGATE2

LGATE1

PHASE1

UGATE1

BOOT1

24

BOOT1

301_040 2_1%

PR949

LGATE_NB1

PHASE_NB 1

UGATE_NB1

BOOTX

VIN

BOOT2

VDDP

VDD

PWM_Y

TP

49

PR945

12

PR956

10_0402 _5%

PR958

0_0402_ 5%

PR959

0_0402_ 5%

PR960

10_0402 _5%

12

36

35

34

33

32

31

30

29

28

27

26

25

12

PR912

@

BOOT_NB1

LGATE1

PHASE1

UGATE1

PR940

100K_04 02_5%

100P_04 02_50V8J

PR950

137K_04 02_1%

PR953

2K_0402 _1%

12

0_0402_5%

PR923

0_0603_ 5%

12

PC918

0.22U_06 03_25V7K

PR931

1_0603_ 5%

12

PC919

1U_0603_16V6K

+3VS

12

PC927

12

PC932

390P_04 02_50V7K

12

PC933

680P_04 02_50V7K

12

+APU_CORE

APU_VDD_ SEN_H <7>

APU_VDD_ SEN_L <7>

12

44

45

FB_NB

VSEN_NB

ISUMP16ISEN2

CPU_B+

12

PC920

VGATE <3 1>

PR946

@ PR9 46

@

32.4K_0 402_1%

1U_0603_16V6K

3

PR929

0_0402_ 5%

PR932

0_0402_ 5%@

12

2

B+

1

+

PC939

PC938

2

15U_D2_25VM_R90

33U_D2_25VM_R60

CPU_B+

5

PQ901

PC916

0.22U_06 03_25V7K

12

PQ902

PQ903

PC931

0.22U_06 03_25V7K

12

PQ905

4

123

TPCA8065-H_PPAK56-8-5

5

4

123

5

4

123

5

4

123

5

PQ904

4

TPCA8065-H_PPAK56-8-5

123

5

PQ906

4

TPCA8057-H_PPAK56-8-5

123

UGATE_NB1

PHASE_NB 1

PR919

UGATE1

PHASE1

BOOT1

LGATE1

1 2

2.2_060 3_5%

LGATE_NB1

TPCA8057-H_ PPAK56-8-5

PR948

1 2

2.2_060 3_5%

BOOT_NB1

12

+5VALW

12

+5VS

PC908

12

PR920

12

PC917

TPCA8057-H_PPAK56-8-5

12

PC909

10U_0805_25V6K

4.7_1206_5%

680P_0603_50V7K

12

PC923

PC922

10U_0805_25V6K

TPCA8065-H_PPAK56-8-5

12

P R951

4.7_120 6_5%

P C934

12

680P_06 03_50V7K

12

CPU_B+

12

10U_0805_25V6K

PR951

PC934

PC910

VSUM+

VSUM-

0.01U_0402_25V7K

PC924

12

0.01U_0402_25V7K

12

PC912

2200P_0402_50V7K

PR921

3.65K_0 402_1%

VSUMP_NB

VSUMN_NB

PR917

1_0402_ 1%

12

PC925

2200P_0402_50V7K

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

1

2

PR952

3.65K_0 402_1%

12

PR955

1_0402_ 1%

12

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

1

2

12

PL903

4

3

PL901

HCB4532K F-800T90_181 2

1 2

PL902

4

3

1

+APU_CORE_NB Iocp=39A

+APU_CORE

CPU_B+

1

+

PC940

PC941

2

33U_D2_25VM_R60

15U_D2_25VM_R90

@

+APU_CORE_NB

www.qdzbwx.com

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PWR-CPU_CORE/CPU_CORE_NB

LA9001P

1

43 48Friday, May 25, 20 12

0.1

5

4

3

2

1

+CPU_CORE +CPU_CORE_NB

D D

+APU_CORE

12

PC1001

22U_0603_6.3V6K

12

PC1009

22U_0603_6.3V6K

12

PC1002

22U_0603_6.3V6K

12

PC1010

22U_0603_6.3V6K

12

PC1003

22U_0603_6.3V6K

12

PC1011

22U_0603_6.3V6K

12

PC1005

PC1004

22U_0603_6.3V6K

PC1012

22U_0603_6.3V6K

12

PC1013

22U_0603_6.3V6K

12

PC1006

22U_0603_6.3V6K

12

PC1014

22U_0603_6.3V6K

12

PC1007

22U_0603_6.3V6K

12

PC1015

22U_0603_6.3V6K

12

PC1008

22U_0603_6.3V6K

+APU_CORE_NB

12

PC1018

PC1017

PC1016

22U_0603_6.3V6K

12

PC1019

PC1020

PC1021

22U_0603_6.3V6K

10U_0603_6.3V6K

12

22U_0603_6.3V6K

12

PC1022

PC1023

0.22U_0402_10V4Z

12

PC1025

PC1024

180P_0402_50V8J

12

PC1026

180P_0402_50V8J

1

+

1 2

PC1027

C C

B B

PC1027

12

1 2

PC1028

0.22U_0402_10V6K

PC1033

0.01U_0402_25V7K

PC1045

180P_0402_50V8J

PC1028

0.22U_0402_10V6K

12

PC1034

12

PC1046

1 2

PC1029

0.22U_0402_10V6K

12

PC1035

0.01U_0402_25V7K

180P_0402_50V8J

PC1035

12

PC1047

1 2

PC1030

0.22U_0402_10V6K

12

PC1036

0.01U_0402_25V7K

180P_0402_50V8J

0.01U_0402_25V7K

12

PC1048

180P_0402_50V8J

12

PC1037

0.01U_0402_25V7K

2

PC1038

PC1031

330U_D2_2VM_R9M

+1.2VS

12

10U_0603_6.3V6K

1

+

PC1032

2

330U_D2_2VM_R9M

12

PC1041

PC1039

22U_0603_6.3V6K

PC1041

PC1040

10U_0603_6.3V6K

12

PC1042

10U_0603_6.3V6K

12

PC1044

PC1043

10U_0603_6.3V6K

+APU_CORE

1

+

PC1049

2

330U_D2_2VM_R9M

1

+

PC1050

2

330U_D2_2VM_R9M

1

+

PC1051

2

330U_D2_2VM_R9M

1

+

PC1052

2

@

330U_D2_2VM_R9M

www.qdzbwx.com

A A

Security Class ification

2011/10/ 12 2013/10/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/ 12 2013/10/ 12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR - PROCESSOR DECOUPLING

LA9001P

44 48Friday, May 25, 2012

1

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

3

4

5

6

7

8

C C

9

10

11

12

13

14

B B

15

16

17

A A

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

LA9001P

45 48Friday, May 25, 2012

1

0.1

5

4

3

2

1

VAUS5 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE

1 2 3/22 27 Modify DL2 from @ to GAS@ For Gastube BOM control

D D

26 Change C1204, C1205 from SE071120JN0 to SE071120J80 SE071120JN0 is for A58 only3/22

SDV TO SIV

NOTE

3 3/22 12 Delete FCH_SEL BOM control AMD formal announce FP2 only support A70M3

10 Delete U2 A60MR1 BOM control AMD formal announce FP2 only support A70M34 3/22 5 3/22 12 Change R117 from PX@ to @, change R155 from @ to always mount Clock request from GPU will not meet power sequence 6 3/22 12 Change R1606, R1607 from USBL2@ to @, change R1610, R1611 from USBL3@ to always mount AMD formal announce FP2 only support A70M3 7 3/26 10 Change GPIO31 pull high from +3VALW to +3VS This GPIO pin is Core power rail 8 4/2 07 Add R215 to pull high +1.5V_APU & @ R36 AMD suggest 9 4/6 24 Add C1223 1000p For EMI 10 4/6 33 Add C1224 1000p For EMI 11 4/6 26 Change C1204, C1205 from 12p to 15p For Vendor tunning value 12 4/6 16 Change C341, C350 from 15p to 8.2p For Vendor tunning value

C C

13 4/6 33 Swap D45 For layout 14 4/9 31 Change R1564 from 33k to 18k DVT Board ID 15 4/9 30 Swap JSPK1 For swap speaker cable 16 4/9 31 Add VSB_ON on GPIO127 For S5 power saving 17 4/11 29 Change R1527 to R-short For cost down 18 4/11 31 Change R1580, R1586 to R-short For cost down 19 4/11 13 Change R167 to R-short For cost down 20 4/11 31 Change R1591 to always mount For MainPowerON power control 21 4/11 7 Change R51, R52 to R-short For cost down 22 4/11 12 Change R1610, R1611 to R-short For cost down

B B

174/1123 For cost downChange R400 to R-short 24 4/11 22 For LVDS Translator 1.2 power railMount R200, @ L171, C238, C239 25 4/11 26 Change R1515, R1508 to R-short For cost down 26 4/11 27 For LAN surge solution changeDelete J17, J19 27 4/12 5 Change A6, A10 APU R1 PN From PC sample to PR sample 28 4/13 17,19 Change BIF_VDDC to VGA_CORE and move C343 to Page 19 For PX5 only

27 Change CHASSIS2_GND to GND & CHASSIS1_GND For common LAN surge solution29 4/16

3330 4/17 Mount L43, L44, L45, @ R1605, R1608, R1609, R1612, R1613, R1616 For EMI (USB3.0 choke)

3231 4/17 Add L50, L51, L52 @ R1614, R1615, R1619, R1624, R1625, R1626 For EMI (USB2.0 choke from SB to MB) 32 4/17 30 Change R937, R1548 from 0 ohm to L172, L173 300ohm Bead For EMI (DMIC DATA , CLK) 33 4/17 7 Change R26,R28 from 1k to 10k For APU_SIC, SID 0'C shut down issue workaround

A A

34 4/18 7 Change back R26,R28 from 10k to 1k, and mount C5988 For APU_SIC, SID 0'C shut down issue

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/15 2013/01/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW-PIR

VAUS5 LA9001P M/B

46 50Friday, May 25, 2012

1

0.3

5

4

3

2

1

VAUS5 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE

1

D D

Reserve R1466232 5/11 For factory requirement to prevent DISPOFF# damage

For BOM reduceChange Q64 from SB00000EO10 to SB00000DH00165/11

SIV TO SIT

NOTE

For BOM optionAdd BOM structure SSD@ for SSD function253 5/11

Reserve ESD component D1,D2 for HDMI signal244 5/14 For HDMI hot-plug protection

5/21 For BOM reduce0402 R-Shot modify

5

7

R24,R160,R161,R158,R163,R171,R169,R166,R1491,R1492

13

0603 R-Shot modify

25

R157,R164,R170,R172,R168,R159,R1529,L35,L36

26

0805 R-Shot modify

30

R162,R165,R1531

6 5/21 For Board ID changeChange R1564 from 18K to 8.2K

31

77 5/22 Change back R24 from R-shot to 0ohm

248 5/22 For APU damage when HDMI hot-plugReserve ESD component D69 for HDMI SMBus

C C

25 For Intel 2230 WLAN Card SupportReserve R1493 5/249

20 For customer requestAdd VRAM Samsung 1G K4W2G1646E-BC11 strap setting5/2410

24 Un-mount D1, D25/2411

12 Change back R1610, R1611 footprint to 0ohm5/2412

30 Add C83, C84 for DMIC noise issue5/2513 For EMI request

27 Change DL2 PN to SCV00001D005/2514 For customer request

10 Add BT_OFF# for other BT combo card5/2515 For customer request

25

26 Un-mount C1197. C1198 and mount C1200,C12035/29 For LAN power trace rounting16

7 Change Q3,Q4 PN from SB501110010 to SB5013800505/29 For PUR request17

30 Change R1530 PN from SM01000DI00 to SM010005X005/29 For PUR request18

23

B B

Change C8244,C8245,C8246,C8247,C8248 and C8249 from 10p to 15p5/31 For AMD suggest19 25 32 33

www.qdzbwx.com

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/01/15 2013/01/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW-SIT PIR

VAUS5 LA9001P M/B

47 50Thursday, May 31, 2012

1

0.3

5

4

3

2

1

SYSTEM

D D

C C

VGA

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2012/01/15 2013/01/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Power sequence

VAUS5 LA9001P M/B

1

0.3

48 50Friday, May 25, 2012

0.3

www.qdzbwx.com

A

B+

SUSP

N-CHANNEL

DMN3030LSS-13

1 1

Jump

RT8205LZQW

SY8033BDBC

SY8809DFC

SUSP

N-CHANNEL

DMN3030LSS-13

2 2

SUSP#

TPS51212DSCR

VR_ON

ISL6277HRTZ

SYSON

RT8207MZQW

3 3

Internal LDO

RT8207MZQW

Jump

SYSON

SUSP

P-CHANNEL

PMV65XP

PXS_PWREN

N-CHANNEL

AO4430L

PXS_PWREN

APL5912

RT8207MZQW

4 4

PXS_PWREN

Internal LDO

RT8207MZQW

TPS51518RUKR

PXS_PWREN

B

SPOK

SUSP

N-CHANNEL

DMN3030LSS-13

TL_ENVDD (LCD_ENVDD#)

P-CHANNEL

PMV65XP

PXS_PWREN

P-CHANNEL

AP2301GN-HF

LDO

APL5508-25DC

DESIGN CURRENT 0.1A

DESIGN CURRENT 6A

DESIGN CURRENT 4.5A

DESIGN CURRENT 1A

DESIGN CURRENT 1.9A

DESIGN CURRENT 1.2A

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.75A

DESIGN CURRENT 8.5A

DESIGN CURRENT 60A

DESIGN CURRENT 44A

Direct out Net Name

DESIGN CURRENT 1.3A

DESIGN CURRENT 3A

DESIGN CURRENT 3.2A

For translate N et Name

DESIGN CURRENT 1.2A

DESIGN CURRENT 4.5A

DESIGN CURRENT 3A

Direct out Net Name

DESIGN CURRENT 19A

C

+3VLP +EC_VCCA +5VALW

+5VS

+3VALW

+3V_LAN

+1.8VGS

+1.1VALW

+1.1VS

+3VS

+LCD_VDD

+3VGS

+2.5VS

+1.2VS

+APU_CORE

+APU_CORE_NB

+1.5VP

+0.75VS

+1.5V +1.5V_APU

+1.5V_IO

+1.5VS

+1.5VGS

+1.0VGS

+1.5VP_DDR3L

+0.75VSP_DDR3L

+VGA_CORE

D

E

www.qdzbwx.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/12/30 2013/10/05

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Power Map

VAUS5 LA9001P M/B

E

0.3

49 50Friday, May 25, 2012

0.3

A

+RTCBATT

5.74ms

+5/3VALW

SPOK

+1.1VALW

1 1

EC_ON

ON/OFF

RSMRST#

RTCCLK

PBTN_OUT#

SLP_S5#

SLP_S3#

SYSON

+1.5V

SUSP#

+0.75VS

+5VS

2 2

+3VS

+2.5VS

+1.5VS

+1.1VS

+1.2VS

VR_ON

+APU_CORE

+APU_CORE_NB

VGATE

FCH_POK (FCH_PWRGD)

APU_CLK/ DISP_CLK

APU_PWRGD (From FCH to APU)

3 3

KB_RST#

PLT_RST# (A_RST#)

APU_RST# (From FCH to APU)

11.58ms

39.90ms

10ms (EC)

9ms

120ms (EC)

RTCCLK will be issued out from FCH after RSMRST# deasserted

25.4ms

120ms (EC)

131ms 200ms

140ms (EC), PBTN_OUT# high edge issued out first, then mornitor SLP_S5# signal and count for 140ms to pull high SYSON

121ms

686us

20ms (EC)

20ms

344us

756us

1.57ms

1.25ms

3.08ms

4.580ms

14.85ms

210ms (EC)

299ms

10ms (EC)

20.79ms

B

C

6.06ms

VAUS5 Power on / off sequence (AC mode)

10ms (EC)

6.76ms

37.6ms

99.2ms

102ms

2ms

D

S5 - S0 -S5

+RTCBATT

+5/3VALW

SPOK

+1.1VALW

EC_ON

ON/OFF

RSMRST#

RTCCLK

PBTN_OUT#

SLP_S5#

SLP_S3#

SYSON

+1.5V

SUSP#

+0.75VS

+5VS

+3VS

+2.5VS

+1.5VS

+1.1VS

+1.2VS

+VR_ON

+APU_CORE

+APU_CORE_NB

VGATE

FCH_POK (FCH_PWRGD)

APU_CLK/ DISP_CLK

APU_PWRGD (From FCH to APU)

KB_RST#

PLT_RST# (A_RST#)

APU_RST# (From FCH to APU)

E

26.904ms

F

203ms

40ms

51ms

8.83ms

1.2ms

4.8ms

35.16ms

2.756ms

17.56ms

38.4ms

124ms

85.8ms

123.8ms

240ns

5.28us

145.6ms

26.9ms

125.2ms

G

+APU_CORE_NB

FCH_POK (FCH_PWRGD)

APU_PWRGD (From FCH to APU)

PLT_RST# (A_RST#)

APU_RST# (From FCH to APU)

+RTCBATT

+5/3VALW

SPOK

+1.1VALW

EC_ON

ON/OFF

RSMRST#

RTCCLK

PBTN_OUT#

SLP_S5#

SLP_S3#

SYSON

+1.5V

SUSP#

+0.75VS

+5VS

+3VS

+2.5VS

+1.5VS

+1.1VS

+1.2VS

+VR_ON

+APU_CORE

VGATE

APU_CLK/ DISP_CLK

KB_RST#

H

www.qdzbwx.com

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

D

E

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

F

Compal Secret Data

2009/10/02 2010/10/02

Deciphered Date

G

Compal Electronics, Inc.

Title

S5_Power Sequence

Size Document Numbe r Rev

Date: Sheet of

50 50Friday, May 25, 20 12

H

0.3

COMPAL LA-9001P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual