Compal LA-8981P V0JET (A210) Schematic

A

ZZZ

PCB

MB

DA80000TI10

ZZZ1

1 1

DDR

Samsung

X76-S@

X76418BOL01

ZZZ1

DDR

Hynix

X76-H@

X76418BOL02

S1

FrameS1Frame

2 2

Compal Confidential

B

C

D

E

Nvdia(T30L) + DDRIIIL

V0JET (A210)_ LA8981P

2012-06-11

3 3

4 4

A

※The content in this document contains confidential information of Compal Electronics, Inc. that is protected under all applicable trade secrets laws and regulations. If you are not the intended recipient or otherwise authorized to receive such information, please do not copy, distribute or otherwise use the information contained herein and please destroy this communication accordingly.

B

REV: 1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

2012/01/092012/05/20

Title

Size Document Number Rev

C

Date: Sheet of

Cover Page

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

1

E

35

1.0

A

B

C

D

E

Compal Confidential

Model Name : NVIDIA T30L System Block Diagram

32KHz

1 1

Touch Panel Control

GEN2_I2C

CORE_PWR_REQPMU

CPU_PWR_REQ

SYS_RESET_N

PMU_32K_IN

PWR_I2S

BATTERY

GEN2_I2C

LCD

Power ON

TPS6591104

VIN

LVDS

TPS62361

LVDS Transmitter SN75LVDS83

2 2

10.1" LCD 1280*800

12MHz

Nvidia

T30L

DDR3L 1GB

JTAG

Debug Test Point

PWR_I2C

UART4 Audience

UART2

eS305

Broadcom BCM47511

Audio Codec WM8903

MIC & HP Jack

GPS Antenna

Audio AMP APA2010

EEPROM AT24C02C

Speaker x 2 (1W)

Thermal NCT72

IME

BT/WLAN AntennaUART3

G-Sensor KXTF9-4100

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/01/092012/05/20

D

Title

Size Document Number Rev

C

Date: Sheet of

SYSTEM BLOCK

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

2

E

35

Micro USB

3 3

4 4

A

Standard USB

CAMERA 2M

Client

Host

CIS(MIPI) CAM_I2C

B

eMMC

SDMMC4 (1.8V)

SDMMC1 (3.3V)

HS uSD slot

SDMMC3

C

AzureWave AW-NH660

GEN1_I2C

GYRO Sensor MPU-3050

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1.0

5

4

3

2

1

Voltage Rails

Power Plane

VIN

D D

C C

B B

B+ VDD_5V0_SBY VDD_1V8_PMU_VRTC

VDD_1V2_MEM

VDD_1V35_DDR3_MEM

VDD_1V0_GEN VDD_1V2_SOC VDD_1V35_DDR3_MEM VDD_PMU_LDO1 VDD_PMU_LDO2 VDD_PMU_LDO3

VDD_PMU_LDO4 (VDD_1V2_RTC_TEGRA) VDD_PMU_LDO5 (+VDD_3V3_SDMMC1_TEGRA) VDD_PMU_LDO6 (+AVDD_1V2_DSI_CSI_TEGRA) VDD_PMU_LDO7 (+AVDD_1V1_PLL_TEGRA)

VDD_PMU_LDO8 (+VDD_1V0_DDR_HS_TEGRA)

+5VS

+3VS VDD_1V8_GEN

+AVDD_1V8_USB_PLL_TEGRA

+T30S_USB1 +VDD_2V85_EMMC

+LEDVDD +LCDVDD

+VDD_1V8_AUDIO_LDO +2.8V_2M_AVDD_R +VDD_3V3_SDCARD +VDD_CAM_1V8 +VDD_3V3_FUSE_TEGRA +VDD_1V8_SENSOR +VDD_3V3_SENSOR

Adapter power supply (12V)

AC or battery power rail for power circuit.

Power for always-on

Power for RTC and always-on core logic

DDR RX power rail T30 VDD_CPU Power T30 VDD_CORE Power DDR power rail

T30 VDD_RTC power rail

T30 VDDIO_SDMMC1 power rail

T30 AVDD_DSI power rail

T30 AVDD_PLL power rail

T30 VDD_DDR_HS power rail

5V System power rail

3.3V System power rail+3VALW

3.3V power rail for standby mode

1.8V System power rail T30 USB power rail USB power rail

Core voltage for EMMC

LCD power rail LCD power rail Audio power rail CAMERA power rail Micro SD power rail CAMERA power rail

T30 VPP_Fuse power rail

3.3V Sensor power rail

ACIN DCIN ON

ON

OFF

OFF OFF OFF OFF

OFF OFF

OFF

OFF OFF

OFF

OFF OFF

OFF

Standby

IDLE ON

ON

ON ON ON ON ON ON ON

ON

V0JET EVT DVT PVT MP

H

PCB_ID0

PCB_ID1

PCB_ID2

PCB_ID3

V0JET

K4B2G0846D-HYH9 (Samaung)

DDR3L

H5TC2G83CFR-H9A (Hynix)

EDJ2108EDBG-DJ-FEl (Elpida)

V0JET

Board ID0

Board ID1

H

Vender PN Acer PN

H

KN.2GB0B.038

KN.2GB0G.003

KN.2GB09.001

EVT DVT PVT

0

0001111

A211 A210

L:

NAND_D4 NAND_D5

00

MP

H:

A210/A211

H:

A210/A211

H:H

NH660

01

10

V0JET (A210)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/01/092012/05/20

2

Title

Size Document Number Rev

C

Date: Sheet of

Notes List

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

3

1

35

1.0

5

R453

NV_LCD_PCLK LCD_PCLK_R

47_0402_5%

+VDD_3V3_LCD_TEGRA

D D

C C

B B

A A

+3VS

C1

0.1U_0402_10V7KC10.1U_0402_10V7K

PN:SA00004KS00 2k bit

1 2 3

U1I

8/22 LCD

20mA

AB13

VDDIO_LCD_1

AC13

VDDIO_LCD_2

(1.8 ~ 3.3V)

1

2

U54

A0 A1 A2 GND4SDA

AT24C02C-XHM-T_TSSOP8

need check with SW Roger

(1.8 ~ 3.3V)

2

C2

1

0.1U_0402_10V7KC20.1U_0402_10V7K

U54

8

VCC

7

WP

6

SCL

5

L49 27NH_LQG15HS27NJ02D_5%_0402L49 27NH_LQG15HS27NJ02D_5%_0402

12

1 2

1

C165

12P_0402_50V4Z

2

T30L-P-A3-1.2G_FCBGA728

+VDD_1V8_SYS_TEGRA

C115

BOARD_ID_WP (7) PWR_I2C_SCL (16,17,29,31,33,7) PWR_I2C_SDA (16,17,29,31,33,7)

need check with WC of GPIO

1

C164

12P_0402_50V4Z

2

LCD_PCLK

LCD_WR*

LCD_DE LCD_HSYNC LCD_VSYNC

LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23

LCD_M1

LCD_PWR0 LCD_PWR1 LCD_PWR2

LCD_SCK LCD_CS0* LCD_CS1*

LCD_SDOUT

LCD_SDIN

LCD_DC0 LCD_DC1

CRT_HSYNC CRT_VSYNC

DDC_SCL DDC_SDA

HDMI_INT

2

C115

1

0.1U_0402_10V6K

4

LCD_PCLK (15)

RF

PD

AG11

NV_LCD_PCLK

PU

AH16

PD

AG9

PU

AF16

PU

AF10

PD

AE8

PD

AF12

PD

AD10

PD

AK15

PD

AK16

PD

AK10

PD

AK12

PD

AG16

PD

AG8

PD

AD15

PD

AK9

PD

AJ12

PD

AF9

PD

AC12

PD

AD12

PD

AE18

PD

AF13

PD

AH15

PD

AE9

PD

AE10

PD

AH13

PD

AH9

PD

AE13

PD

AK13

PD

AG12

PD

AJ9

PD

AG10

PD

AH12

PU

AG15

PU

AJ15

PU

AC10

PU

AJ13

PU

AH10

PD

AE15

PD

AE12

PU

AD13

PU

AJ16

Z

AG14

Z

AJ10

Z

AG13

LCD_DE (15) LCD_HSYNC (15) LCD_VSYNC (15)

LCD_D00 (15) LCD_D01 (15) LCD_D02 (15) LCD_D03 (15) LCD_D04 (15) LCD_D05 (15) LCD_D06 (15) LCD_D07 (15) LCD_D08 (15) LCD_D09 (15) LCD_D10 (15) LCD_D11 (15) LCD_D12 (15) LCD_D13 (15) LCD_D14 (15) LCD_D15 (15) LCD_D16 (15) LCD_D17 (15)

EN_3V3_EMMC1 (14) EN_3V3_SDCARD (21)

9/29 Leakage Issue

Modify R10&R11 from mount to unmount

U1K

10/22 HDMI

AE4

AVDD_HDMI_1

AF4

AVDD_HDMI_2

(3.3V)

R420

@R420

@

0_0402_5%

R425

@R425

@

0_0402_5%

4

AK6

AF7

U1J

(3.3V)

AVDD_HDMI_PLL

(1.8V)

9/22 VDAC

AVDD_VDAC

(2.8V)

12

+VDD_3V3_GMI_TEGRA

110mA

+3VS

2

C147

1

3300P_0402_50V7K

1

C4

C3

2

4.7U_0402_6.3V6MC34.7U_0402_6.3V6M

T30L-P-A3-1.2G_FCBGA728

C1 C2 D1

2

1

0.1U_0402_10V7KC40.1U_0402_10V7K

HDMI_TXCN HDMI_TXCP

HDMI_TXD0N

HDMI_TXD0P

HDMI_TXD1N

HDMI_TXD1P

HDMI_TXD2N

HDMI_TXD2P

HDMI_PROBE

HDMI_RSET

VDAC_R VDAC_G VDAC_B

VDAC_VREF

VDAC_RSET

U1D

4/22 GMI

(1.8/3.3V)

VDDIO_GMI_1 VDDIO_GMI_2 VDDIO_GMI_3

AB7 AA9 AA7

AA5

AA6

3

Z

F8

Z

G6

Z

D3

Z

E4

Z

G2

Z

D2

Z

B3

Z

G1

PD

H6

PD

F4

PD

E7

PD

F3

Z

F5

Z

F7

Z

J2

Z

F1

H4 J6 C4 J3

10K_0402_5%

PU

J4

PU

K7

1

F6

BOARD_ID0

1

A3

BOARD_ID1

D6

PU

J5 J7

1

E6

0

A4 D4

B4 D5

0_0402_5%

R403

1 2

C3

1

F2

FORCE_RECOVERY#

1

G4

NOR_BOOT

1 2

R14 100K_0402_5%R14 100K_0402_5%

Z

G3

+VDD_3V3_GMI_TEGRA

12

R11

2.2K_0402_1%

Z

G5

Z

G7

T30L-P-A3-1.2G_FCBGA728

NAND_D0 BOOT_PD

NAND_D4 NAND_D5 NAND_D6 NAND_D7

PCB_ID0 PCB_ID1 PCB_ID2

R1411

BOOT_PD

4.7U_0402_6.3V6M

GMI_AD00 GMI_AD01 GMI_AD02 GMI_AD03 GMI_AD04 GMI_AD05 GMI_AD06 GMI_AD07 GMI_AD08 GMI_AD09 GMI_AD10 GMI_AD11 GMI_AD12 GMI_AD13 GMI_AD14 GMI_AD15

GMI_A16 GMI_A17 GMI_A18 GMI_A19

GMI_CS0* GMI_CS1* GMI_CS2* GMI_CS3* GMI_CS4* GMI_CS6* GMI_CS7*

GMI_ADV*

GMI_CLK

GMI_RST* GMI_WAIT

GMI_WP*

GMI_IORDY

GMI_OE*

GMI_WR*

GMI_DQS

GEN2_I2C_SCL GEN2_I2C_SDA

AK3 AK4

AJ4 AH4

AH6 AJ6

AK7 AJ7

AG1

AH3

HDMI_RSET

12

R26

@ R26

@

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LCD_PWM_OUT (15)

DISPOFF# (15) EN_T30S_FUSE_3V3 (23) IMG_EN (15)

EN_SENSOR_3V3 (23)

VIB_EN_T30S (22) TS_PWR_EN (15)

EN_VDDLCD_T30S (15) EN_WIFI_VDD (25)

1 2

@R1411

@

TS_INT# (15) CHARGER_STAT (27)

TEMP_ALERT# (7)

100K_0402_5%

R22 100K_0402_5%R22 100K_0402_5%

12

R10

2.2K_0402_1%

GEN2_I2C_SCL (15)

GEN2_I2C_SDA (15)

VOL_UP#(22,7) VOL_DOWN#(22,7)

+VDD_1V8_SDMMC4_TEGRA

VDD_1V8_GEN

1

C5

2

Compal Secret Data

Deciphered Date

2

NAND[D0:D3] -- boot strap EMMC 0001 NAND[D4:D7] -- ram code For Boost Strap

20mA

2

+VDD_3V3_GMI_TEGRA

12

R24

+VDD_3V3_GMI_TEGRA

SD_DET# (21,7)

12

+VDD_3V3_GMI_TEGRA

TS_RST# (15)LVDS_SHTDN# (15)

D8

2

C6

1

0.1U_0402_10V7KC60.1U_0402_10V7K

EN_SENSOR_3V3

R18

@ R18

@

100K_0402_5%

TS_PWR_EN

+VDD_3V3_GMI_TEGRA

EN_WIFI_VDD

R17

+VDD_1V8_SYS_TEGRA

1

B

2

A

74AUP1G02GW_TSSOP5

U1E

5/22 SDMMC4

(1.2/1.8V)

VDDIO_SDMMC4

2012/01/092012/05/20

1

NAND_D0

R1 100K_0402_5%R1 100K_0402_5%

BOOT_PD

R2 100K_0402_5%R2 100K_0402_5%

Change BOM structure to DDR3L

K4B2G0846D-HYH9 [7..4] -->0000 H5TC2G83CFR-H9A [7..4] -->0001

12

R12

12

100K_0402_5%

12

5

U55

4

Vcc

Y

G

3

NAND_D4 NAND_D5 NAND_D6 NAND_D7

Change BOM structure

PCB_ID0 PCB_ID1 PCB_ID2 BOARD_ID0 BOARD_ID1

12

R54

R54 1M_0402_1%

1M_0402_1%

X76@

R38 100K_0402_5%

R38 100K_0402_5% R43 100K_0402_5%X76@R43 100K_0402_5%X76@ R84 100K_0402_5%@R84 100K_0402_5%@ R85 100K_0402_5%@R85 100K_0402_5%@

R5 100K_0402_5%X76@R5 100K_0402_5%X76@ R6 100K_0402_5%

R6 100K_0402_5%

X76@

R7 100K_0402_5%R7 100K_0402_5% R8 100K_0402_5%R8 100K_0402_5%

R63 100K_0402_5%

A210@

R87 100K_0402_5%

NH660@

R100 100K_0402_5%

A210@

R78 100K_0402_5%R78 100K_0402_5%

V10 M

R88 100K_0402_5%R88 100K_0402_5%

R152 100K_0402_5%

A211@

R153 100K_0402_5%

A211@

R154 100K_0402_5%

A211@

R79 100K_0402_5%

@

R89 100K_0402_5%

@

V10 M

DVT BOARD_ID[1..0] -->0..1

DVT PCB_ID[3..00] --> 1111

+VDD_3V3_GMI_TEGRA

12

R23

R23 47K_0402_1%

47K_0402_1%

R90 47K_0402_1%

1 2

13

D

2

Q44

G

S TR DMN3150LW-7 1N SOT-323-3

S

Vth=1.4V

SDMMC4 : eMMC

B9

SDMMC4_DAT0

B6

SDMMC4_DAT1

C6

SDMMC4_DAT2

A6

SDMMC4_DAT3

B7

SDMMC4_DAT4

A7

SDMMC4_DAT5

D7

SDMMC4_DAT6

D9

SDMMC4_DAT7

A9

SDMMC4_CLK

C7

SDMMC4_CMD

C9

SDMMC4_RST*

T30L-P-A3-1.2G_FCBGA728

Compal Electronics, Inc.

Title

T30L-LCD/CRT/HDMI/NAND

Size Document Number Rev

C

Date: Sheet of

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

1

12 12

12 12 12 12

12 12 12 12 12

Z Z Z Z Z Z Z Z

PU PU

Z

+VDD_3V3_GMI_TEGRA

FORCE_RECOVERY#

EMMC_DA0 (14) EMMC_DA1 (14) EMMC_DA2 (14) EMMC_DA3 (14) EMMC_DA4 (14) EMMC_DA5 (14) EMMC_DA6 (14) EMMC_DA7 (14)

EMMC_CLK (14) EMMC_CMD (14)

EMMC_RST# (14)

4

35

1.0

5

4

3

2

1

+VDD_1V35_MEM_TEGRA

1

D D

C10

SDMMC1 : SD card

+VDD_3V3_SDMMC1_TEGRA

VDD_PMU_LDO5

C C

U1P

17/22 SDMMC1

(1.8/2.8 ~ 3.3V)

20mA

J1

C17

VDDIO_SDMMC1

4.7U_0402_6.3V6M

1

2

SDMMC1_DAT0

SDMMC1_DAT1

SDMMC1_DAT2

SDMMC1_DAT3

SDMMC1_CLK

SDMMC1_CMD

PU

K1 K3 K2 K4

M6 N6

SDMMC_DAT0 (21)

PU

SDMMC_DAT1 (21)

PU

SDMMC_DAT2 (21)

PU

SDMMC_DAT3 (21)

PU

SDMMC_CLK (21)

PU

SDMMC_CMD (21)

C14

+VDD_3V3_SDMMC1_TEGRA

33.2_0402_1%

SDMMC1_COMP_PU SDMMC1_COMP_PD

GPIO_PV2 GPIO_PV3

CLK2_OUT CLK2_REQ

L4

SDMMC1_COMP_PU

K6

SDMMC1_COMP_PD

Z

M5

Z

M1

PD

K5

Z

N5

T30L-P-A3-1.2G_FCBGA728

33.2_0402_1% R29

R29 R30

R30

33.2_0402_1%

CP_GPIO (27)

1 2 1 2

C18

C30

1

C11

C13

C12

2

1

2

1

2

1

2

4.7U_0402_6.3V6M

0.1U_0402_10V7K

1U_0402_10V6K

4.7U_0402_6.3V6M

1U_0402_10V6K

C21

1

2

1U_0402_10V6K

C110

1

2

VDD_1V35_DDR3_MEM

4.7U_0402_6.3V6M

1

C22

C15

2

0.1U_0402_10V7K

1U_0402_10V6K

C19

C20

1

2

1U_0402_10V6K

C111

C109

1

2

+VDD_1V35_MEM_TEGRA

+VDD_3V3_DDR_RX_TEGRA

+3VS

+VDD_1V0_DDR_HS_TEGRA

VDD_PMU_LDO8

SDMMC3 : WIFI

+VDD_1V8_SDMMC3_TEGRA

VDD_1V8_GEN

C26

4.7U_0402_6.3V6M

B B

A A

U1O

6/22 SDMMC3

(1.8/2.8 ~ 3.3V)

24mA

G24

VDDIO_SDMMC3

1

C25

2

0.1U_0402_10V7K

SDMMC3_COMP_PU SDMMC3_COMP_PD

U1M

15/22 HSIC

(1.2V)

W7

VDDIO_HSIC

U1N

16/22 IC_USB

V9

AVDD_IC_USB

(1.8V)

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 SDMMC3_DAT4 SDMMC3_DAT5 SDMMC3_DAT6 SDMMC3_DAT7

SDMMC3_CLK

SDMMC3_CMD

HSIC_DATA

HSIC_STROBE

HSIC_REXT

IC_USB_DN IC_USB_DP

IC_USB_REXT

PU

L27

PU

J26

PU

J28

PU

K26

PU

J27

PU

K25

PU

K24

R64 100K_0402_5%@R64 100K_0402_5%@

PU

K28

PU

G30

PU

J29

J25

SDMMC3_COMP_PU

K27

SDMMC3_COMP_PD

T30L-P-A3-1.2G_FCBGA728

V6 V7

W6

T30L-P-A3-1.2G_FCBGA728

W8 W9

V8

WFMMC_DAT0 (25) WFMMC_DAT1 (25) WFMMC_DAT2 (25) WFMMC_DAT3 (25)

EN_3V3_EMMC (14)

12

WFMMC_CLK (25) WFMMC_CMD (25)

33.2_0402_1%

1 2

R31

1 2

R32

33.2_0402_1%

+VDD_1V8_SDMMC3_TEGRA

NV DG V1.1

2.2P_0402_50V8

2.2P_0402_50V8 C2674

C2674

1 2

DDR_CLKN DDR_CLKP

12

R21

R20

45.3_0402_1%

0.01U_0402_25V7

R20

45.3_0402_1%

1

C482

2

Note:Place at the T-point

U1C

3/22 DDR3/LPDDR2

(1.2/1.25/1.35/1.5)

740mA

G16

VDDIO_DDR_01

G19

VDDIO_DDR_02

H15

VDDIO_DDR_03

H16

VDDIO_DDR_04

H18

VDDIO_DDR_05

H19

VDDIO_DDR_06

H21

VDDIO_DDR_07

H22

VDDIO_DDR_08

J15

VDDIO_DDR_09

J16

VDDIO_DDR_10

J18

VDDIO_DDR_11

J19

VDDIO_DDR_12

J21

VDDIO_DDR_13

J23

VDDIO_DDR_14

K22

VDDIO_DDR_15

K23

VDDIO_DDR_16

(2.8/3.3V)

50mA

A27

VDD_DDR_RX

1

C23

2

4.7U_0402_6.3V6M

(1.00V)

30mA

E10

VDD_DDR_HS_1

H9

VDD_DDR_HS_2

1

C24

2

4.7U_0402_6.3V6M

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31

DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3

DDR_DQS0N DDR_DQS0P

DDR_DQS1N DDR_DQS1P

DDR_DQS2N DDR_DQS2P

DDR_DQS3N DDR_DQS3P

DDR_A00 DDR_A01 DDR_A02 DDR_A03 DDR_A04 DDR_A05 DDR_A06 DDR_A07 DDR_A08 DDR_A09 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

DDR_RAS_N DDR_CAS_N

DDR_WE_N

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS0_N DDR_CS1_N

DDR_ODT0 DDR_ODT1

DDR_CKE0 DDR_CKE1

DDR_CLK_N

DDR_CLK

DDR_RESET DDR_QUSE0

DDR_QUSE1 DDR_QUSE2 DDR_QUSE3

DDR_COMP_PU DDR_COMP_PD

D24

DDR_DQ0

B25

DDR_DQ1

A25

DDR_DQ2

D21

DDR_DQ3

A24

DDR_DQ4

A21

DDR_DQ5

A22

DDR_DQ6

B22

DDR_DQ7

C15

DDR_DQ8

A13

DDR_DQ9

C12

DDR_DQ10

B13

DDR_DQ11

C13

DDR_DQ12

A10

DDR_DQ13

B10

DDR_DQ14

C10

DDR_DQ15

G22

DDR_DQ16

D22

DDR_DQ17

D25

DDR_DQ18

F23

DDR_DQ19

G21

DDR_DQ20

E25

DDR_DQ21

F24

DDR_DQ22

F22

DDR_DQ23

F13

DDR_DQ24

G13

DDR_DQ25

G10

DDR_DQ26

D13

DDR_DQ27

G9

DDR_DQ28

F10

DDR_DQ29

D10

DDR_DQ30

F12

DDR_DQ31

C22

50OHM_NETCLASS2

D12

50OHM_NETCLASS2

E22

50OHM_NETCLASS2

G12

50OHM_NETCLASS2

DDR_DQS0_PAIR

B24

DDR_DQS0_PAIR

C24

DDR_DQS1_PAIR

B12

DDR_DQS1_PAIR

A12

DDR_DQS2_PAIR

E24

DDR_DQS2_PAIR

D23 E12

D11 D20

DDR_A0

G15

DDR_A1

A18

DDR_A2

D14

DDR_A3

B19

DDR_A4

A16

DDR_A5

C21

DDR_A6

A15

DDR_A7

D15

DDR_A8

C16

DDR_A9

E16

DDR_A10

D18

DDR_A11

E15

DDR_A12

A19

DDR_A13

B16

DDR_A14

Trace 50ohm

G18

Trace 50ohm

D17

Trace 50ohm

D19

Trace 50ohm

F15

Trace 50ohm

E21

Trace 50ohm

F21

Trace 50ohm

F16

Trace 50ohm

E19

Trace 50ohm

D16 F18

Trace 50ohm

F19 E18

B18

DDR_CLKN

C18

DDR_CLKP

10K_0402_5%

C19 D27

QUSE0

D26

QUSE1

E9

QUSE2

F9

QUSE3

B21

DDR_COMP_PU

B15

DDR_COMP_PD

T30L-P-A3-1.2G_FCBGA728

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

1 2

R55

R33 0_0402_5%R33 0_0402_5% R34 0_0402_5%R34 0_0402_5%

50OHM_NETCLASS2

DDR_DQ[31..0] (11,12)

DDR_DM0 (11) DDR_DM1 (12) DDR_DM2 (11) DDR_DM3 (12)

DDR_DQS0N (11) DDR_DQS0P (11)

DDR_DQS1N (12) DDR_DQS1P (12)

DDR_DQS2N (11) DDR_DQS2P (11)

DDR_DQS3N (12) DDR_DQS3P (12)

50OHM_NETCLASS2

DDR_RAS# (11,12) DDR_CAS# (11,12)

DDR_WE# (11,12)

DDR_BA0 (11,12) DDR_BA1 (11,12) DDR_BA2 (11,12)

DDR_CS0# (11,12)

DDR_A15 (11,12)

DDR_ODT0 (11,12)

DDR_CKE0 (11,12)

DDR_CLKN (11,12) DDR_CLKP (11,12)

+VDD_1V35_MEM_TEGRA

DDR_RESET# (11,12)

1 2 1 2

+VDD_1V35_MEM_TEGRA

1 2

R35 40.2_0402_1%R35 40.2_0402_1%

1 2

R36 40.2_0402_1%R36 40.2_0402_1%

DDR_A[14..0] (11,12)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/01/092012/05/20

2

Title

T30SL-OSC/PLL/SYS/DDR

Size Document Number Rev

C

Date: Sheet of

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

5

1

35

1.0

A

U1Q is not place on grid , need check connection

1 1

2 2

3 3

4 4

+VDD_1V8_AUDIO_TEGRA

VDD_1V8_GEN

VDD_PMU_LDO6

U1Q

13/22 AUDIO

20mA

C30

VDDIO_AUDIO

(1.8/3.3V)

1

C28

2

0.1U_0402_10V7K

+AVDD_1V2_DSI_CSI_TEGRA

56mA

C32

1

C31

2

0.1U_0402_10V7K

4.7U_0402_6.3V6M

A

AB6

7/22 DSI & CSI

(1.2V)

AVDD_DSI_CSI

U1H

T30L-P-A3-1.2G_FCBGA728

CLK1_OUT CLK1_REQ

DAP1_SCLK

DAP1_FS

DAP1_DOUT

DAP1_DIN

DAP2_SCLK

DAP2_FS

DAP2_DOUT

DAP2_DIN

SPDIF_IN

SPDIF_OUT

SPI1_SCK SPI1_CS0* SPI1_MOSI SPI1_MISO

SPI2_SCK SPI2_CS0* SPI2_CS1* SPI2_CS2* SPI2_MOSI SPI2_MISO

CSI_CLKAN CSI_CLKAP

CSI_CLKBN CSI_CLKBP

DSI_CLKAN DSI_CLKAP

DSI_CSI_RUP DSI_CSI_RDN

DSI_CSI_TEST_OUT

C27 F26

G29 D28 G26 G25

C28 C29 G27 F27

H27 A28

B28 J24 F29 F28

D29 G28 F25 E27 B27 D30

T30L-P-A3-1.2G_FCBGA728

CSI_D1AN CSI_D1AP

CSI_D2AN CSI_D2AP

CSI_D1BN CSI_D1BP

CSI_D2BN CSI_D2BP

DSI_D1AN DSI_D1AP

DSI_D2AN DSI_D2AP

AUDIO_CLK

PD PD PD

PD PD PD PD

PU PU

PU PU PU PD

PU PU PU PU PD PD

AC4 AD4

AD3 AD2

AE2 AE3

AG3 AG2

AD1 AE1

AH2 AH1

AA1 AB1

AB2 AB3

AA2 AA3

AG4 AJ3

AB4

B

1 2

R37 0_0402_5%R37 0_0402_5%

AUDIO_SEL (16)

AUDIO_RST# (16) ES305_INT_R (16)

AUDIO_SCLK2 (16) AUDIO_FS2 (16) AUDIO_DOUT2 (16)

AUDIO_DIN2 (16)

BATT_LEARN (27)

COMPASS_DRDY (19)

HP_DET# (17) CDC_IRQ# (17) EN_ES305_OSC (16) GYRO_INT_R (19)

2M_CAM_CLK#_R (20) 2M_CAM_CLK_R (20)

2M_CAM_DA1#_R (20) 2M_CAM_DA1_R (20)

+AVDD_1V2_DSI_CSI_TEGRA

12

DSI_CSI_RUP DSI_CSI_RDN

12

R1424

49.9_0402_1%

B

RF note

R44

R44 453_0402_1%

453_0402_1%

R45

49.9_0402_1%

C

+AVDD_3V3_USB_TEGRA

130mA +3VS

1

C27

2

12

+T30S_USB1

Vth = 1.5

10MIL 0.1A

Option

1 2

R399 0_0402_5%@R399 0_0402_5%@

4

5 6

FDG6331L_SC70-6

SB00000SM00

1 2

R1432 0_0402_5%@R1432 0_0402_5%@

AO3413_SOT23-3

1 3

D

2

G

+AVDD_1V8_USB_PLL_TEGRA

3 2

1

Q34

Q18

S

12

G

2

R42

1M_0402_1%

EN_T30S_USB1

13

D

Q5

Q5 BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

S

L4

10mA

1 2

MPZ1005S300CT_2P

+USB_CLIENT

0.1U_0402_10V6K

1

D18

C2673

BZT52-B5V6S_SOD323-2

2

2 1

1

C29

2

@

AUDIO_CLK_R (17)

VDD_1V8_GEN

R323

1M_0402_1%

CORE_PWR_REQ(31,7)

CORE_PWR_REQ

SC400003Z00

+AVDD_3V3_USB_TEGRA

USB VBUS overvoltage protection

+VDD_1V8_CAM_TEGRA

VDD_1V8_GEN

1

C34

2

U1G

18/22 CAM

(1.8/2.8 ~ 3.3V)

20mA

(1.8/2.8 ~ 3.3V)

AD9

VDDIO_CAM

1

C35

2

0.1U_0402_10V7K

4.7U_0402_6.3V6M

T30L-P-A3-1.2G_FCBGA728

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

CAM_I2C_SCL CAM_I2C_SDA

CAM_MCLK

GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7

GPIO_PCC1 GPIO_PCC2

U1L

11/22 USB

(3.3V)

U12

AVDD_USB

4.7U_0402_6.3V6M

(1.8V)

U4

AVDD_USB_PLL

0.1U_0402_10V7K

2.2K_0402_1%

AG5 AH7

AD5

AF6 AD6 AG7 AE5 AE6 AE7

AC6 AG6

100K_0402_5%

Compal Secret Data

Deciphered Date

D

+VDD_1V8_CAM_TEGRA

12

R40

Z Z

Z

1 2

R72 0_0402_5%R72 0_0402_5%

Z Z Z Z Z Z

PU PU

R15

R16

@R16

@

100K_0402_5%

1 2

D

ACC1_DETECT

ACC2_DETECT

ACC3_DETECT

R41

2.2K_0402_1%

CAM_I2C_SCL (20) CAM_I2C_SDA (20)

2M_CAM_RST# (20)

2M_CAM_PWDN (20)

@R15

@

+VDD_1V8_CAM_TEGRA

2012/01/092012/05/20

E

W5

W3 W2

1 2

T7

R1422 1K_0402_5%@R1422 1K_0402_5%@

V5

T6 T5

W4

1 2

R5

R1423 0_0402_5%@R1423 0_0402_5%@

V3 V2

V4

Y4

USB_REXT

T30L-P-A3-1.2G_FCBGA728

+T30S_USB1

USB1_DN (21) USB1_DP (21)

+T30S_USB1

USB_HOST_DN (21) USB_HOST_DP (21)

R39

1K_0402_1%

CAM_I2C_SCL CAM_I2C_SDA

C186

USB1_VBUS

USB1_DN USB1_DP

USB2_VBUS

USB2_DN USB2_DP

USB3_VBUS

USB3_DN USB3_DP

USB_REXT

RF note

CAM_MCLK (20)

1

C372

2

2M_CAM_RST# 2M_CAM_PWDN

10P_0402_25V8K

R25

@R25

@

R27

@R27

@

100K_0402_5%

1 2

V10 Add

Compal Electronics, Inc.

Title

T30L-USB/SDIO/UART/AUDIO

Size Document Number Rev

C

Date: Sheet of

Wednesday, June 13, 2012

V0JET(A210)-LA8981P

E

For CLIENT USB

USB1_ID (21)

For HOST USB

12

1

@

2

39P 50V J NPO 0402

1

C187

@

2

39P 50V J NPO 0402

6

35

6

35

6

35

1.0

A

+VDD_1V8_UART_TEGRA

U1R

14/22 UART

20mA

(1.8/3.3V)

VDD_1V8_GEN

AA30

1

C38

2

0.1U_0402_10V6K

VDD_1V8_GEN

NV_THERM_DP

NV_THERM_DN

VDDIO_UART

+VDD_1V8_BB_TEGRA

20mA

W1

1

C43

2

0.1U_0402_10V6K

max current is 350uA VR1 =17mV

R59

100_0402_1%

1 2

1000P_0402_50V7K

R61

100_0402_1%

1 2

PWR_I2C_SCL(16,17,29,31,33,4,7) PWR_I2C_SDA(16,17,29,31,33,4,7)

A

U1S

12/22 BB

VDDIO_BB

(1.8/3.3V)

+3VS

THERMD_F_P

1

C46

2

THERMD_F_N PWR_I2C_SCL PWR_I2C_SDA

1 1

2 2

3 3

4 4

GEN1_I2C_SCL GEN1_I2C_SDA

UART2_TXD UART2_RXD UART2_RTS* UART2_CTS*

UART3_TXD UART3_RXD UART3_RTS* UART3_CTS*

GPIO_PU0 GPIO_PU1 GPIO_PU2 GPIO_PU3 GPIO_PU4 GPIO_PU5 GPIO_PU6

DAP4_DIN

DAP4_DOUT

DAP4_FS

DAP4_SCLK

CLK3_OUT CLK3_REQ

T30L-P-A3-1.2G_FCBGA728

R57

1 2

49.9_0402_1%

2 3

8 7

AB25 V29

W25 AB28 AB26 AA25

AC27 W27 AB29 W29

AA28 V30 AB30 AB27 AC25 W30 AA27

AA29 W28 AA24 AA26

Y27 W24

T30L-P-A3-1.2G_FCBGA728

1

C45

2

U4

D+ D-

ALERT#/ THERM2# SCLK SDATA

NCT72CMNR2G_DFN8_3x3

Open Drain

Z Z

PU PU PU PU

Z Z Z Z Z Z

DEBUG_UART1_RX_R

Z

BT_PD#

R372 100K_0402_5%R372 100K_0402_5%

PD PD PD PD

0 Z

ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7

ULPI_CLK ULPI_DIR

ULPI_NXT

ULPI_STP

DAP3_DIN

DAP3_DOUT

DAP3_FS

DAP3_SCLK

GPIO_PV0 GPIO_PV1

+3VS_TH

0.1U_0402_10V6K

Vcc

THERM#

GND

PU

R3

PU

V1

PU

N1

PU

T3

PU

P4

PU

T4

PU

T1

PU

T2 M2

Z

M4

Z

N2

Z

N4

PD

N3

PD

M3

PD

R4

PD

R6

Z

R1

Z

R2

100K_0402_5%

1 4

6 5

B

2.2K_0402_1%

R77

ON_KEY#

B

+VDD_1V8_SENSOR

12

R46

GPS_UART_TXD (24)

GPS_UART_RXD (24)

GPS_UART_RTS# (24)

GPS_UART_CTS# (24)

BT_UART_TXD (25)

BT_UART_RXD (25)

BT_UART_RTS# (25)

BT_UART_CTS# (25)

BT_RST# (25) GPS_PWRON (24)

GPS_RESET# (24)

1 2

R149

@R149

@

0_0402_5%

12

BT_PCM_IN (25)

BT_PCM_OUT (25) BT_PCM_SYNC (25) BT_PCM_CLK (25)

CLK_12M_ES305 (16)

12

100K_0402_5%

12

@ R1560

@

VDD_1V8_PMU_VRTC

12

R58

12

R47

2.2K_0402_1%

For GPS

For BT

DEBUG_UART1_RX (18,7)

BT_PD# (25)

DEBUG_UART1_TX (18) DEBUG_UART1_RX (18,7)

WAKE_UP_ACIN (27)

AUDIO_UART4_TX (16) AUDIO_UART4_RX (16) EN_VDD_GPS (24) EN_SENSOR_1V8# (23)

+VDD_1V8_BB_TEGRA

100K_0402_5%

12

R379

WF_RST# (25) BT_WAKEUP (25) EN_SENSOR_3V3_2 (23)

12

R164 100K_0402_5%R164 100K_0402_5%

RB751V-40_SOD323-2

12

D20

R1560 100K_0402_5%

100K_0402_5%

+3VS

12

R60

R60 100K_0402_5%

100K_0402_5%

AP_OVERHEAT# (31) TEMP_ALERT# (4)

Thermal

BT_RST# GPS_RESET#

12

R56

100K_0402_5%

GEN1_I2C_SCL (19) GEN1_I2C_SDA (19)

+VDD_1V8_BB_TEGRA

C

For PMU RTC CLOCK

Y1

12

R75

VDD_1V8_GEN

0_0402_5%

12

R65

+VDD_1V8_SYS_TEGRA

0_0402_5%

JTAG_TRST#

JTAG_TDI JTAG_TMS JTAG_TCK JTAG_RTCK JTAG_TDO

HOT_RST#(22)

ONKEY_R#

For JTAG

JTAG_TDI JTAG_TMS JTAG_RTCK JTAG_TCK JTAG_TRST#

1 2

R155

10K_0402_5%

1 2

R159

10K_0402_5%

1 2

R160

10K_0402_5%

R161 100K_0402_5%R161 100K_0402_5% R162 100K_0402_5%@R162 100K_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

32.768KHZ_12.5P_1TJF125DP1A000D

MPZ1005S300CT_2P

L3

1 2

+AVDD_1V1_PLL_TEGRA

54mA

VDD_PMU_LDO7

1

C41

2

VDD_1V8_GEN

ONKEY_R# (22)

@

1

12

2

R1561

3 4 5 6 7 8

9 10 11 12

+VDD_1V8_SYS_TEGRA

12 12

1 2

AVDD_OSC

C39

1

C42

2

0.1U_0402_10V6K

R53

0_0402_5%

1 2

+VDD_1V8_SYS_TEGRA

20mA

C44

JDBUG1

1 2 3 4 5 6 7 8 9 10 GND GND

ACES_87036-1001-CP

@

10mA

1

2

1

2

PMU_OSC32KOUT (31)PMU_OSC32KIN(31)

F30

4.7U_0402_6.3V6M

H13

AA8

AD7

AA22

K29 K30

0.1U_0402_10V6K

U1B

2/22 OSC, PLL & SYS

(1.8V)

AVDD_OSC

Deep Sleep : OFF

(1.1V)

AVDD_PLLA_P_C

(1.1V)

J12

AVDD_PLLX

(1.1V)

J13

AVDD_PLLM

(1.1V)

AVDD_PLLU_D

(1.1V)

AVDD_PLLU_D2

(1.05V)

AVDD_PLLE

(1.8/3.3V)

VDDIO_SYS_1 VDDIO_SYS_2

Compal Secret Data

Deciphered Date

D

+VDD_1V8_SYS_TEGRA

R48

100K_0402_5%

CORE_PWR_REQ CPU_PWR_REQ

Deep Sleep : ON

T30L-P-A3-1.2G_FCBGA728

D

12

2012/01/092012/05/20

12

10K_0402_5%

R1572

1 2

CORE_PWR_REQ

@

R49

100K_0402_5%

XTAL_IN

XTAL_OUT

PWR_I2C_SCL PWR_I2C_SDA

SYS_RESET_N

PWR_INT_N

CPU_PWR_REQ

SYS_CLK_REQ

CLK_32K_IN

CLK_32K_OUT

KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07

KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

JTAG_RTCK

THERM_DN THERM_DP

HDMI_CEC

TEST_MODE_EN

E

T30_XTAL_IN

1

R50

2M_0402_5%

1 2

T30_XTAL_OUT

T30

T30_XTAL_IN

T29

T30_XTAL_OUT

H12

PLL_S_PLL_LF

NC

+VDD_1V8_SYS_TEGRA

1.8K_0402_5%

1.8K_0402_5% R51

R51

Z

M24

Z

N27 N28

M22 N25

R24

Z

T23

SYS_CLK_REQ

R22

0

U27

PU

J30

PU

N26

PU

V25

PU

R26

PU

W26

PU

R30

PU

P27

PU

N29

PD

T26

PD

M23

PD

V27

PD

M28

PD

N24

PD

N30

PD

T24

PD

T25

T10PAD@ T10PAD@

PD

R27

PD

M26

PD

R25

PD

M27

T14PAD@ T14PAD@

PD

1 2

N23

@

PD

V28

R405 0_0402_5%

PD

M25

PD

V26

T27

JTAG_TCK

R29

JTAG_TDI

T28

JTAG_TDO

R23

JTAG_TMS

T22

JTAG_TRST#

V24

JTAG_RTCK

M30

NV_THERM_DN

M29

NV_THERM_DP

N22

OWR

AC18 R28

TEST_MODE_EN

0_0402_5%

R62

1 2

Title

Size Document Number Rev

C

Date: Sheet of

Wednesday, June 13, 2012

2

4

3

12

1.8K_0402_5%

1.8K_0402_5% R52

R52

PMU_RESET_OUT_1V8# (31)

PMU_INT# (31)

CORE_PWR_REQ (31,6) CPU_PWR_REQ (31)

T2PADT2PAD

PMU_CLK_32K (31)

CLK_32K_OUT (25)

SC_LOCK# (22) VOL_UP# (22,4) VOL_DOWN# (22,4)

EN_CAM_2V8 (20) BOARD_ID_WP (4)

WAKEUP_LED (27) EN_CAM_1V8# (23)

UART_SW (18)

SHORT_DET (17) WF_WAKE# (25)

SD_DET# (21,4)

G_ACC_INT (19) BT_IRQ# (25)

T4PAD@ T4PAD@ T5PAD@ T5PAD@ T6PAD@ T6PAD@ T7PAD@ T7PAD@ T8PAD@ T8PAD@ T9PAD@ T9PAD@

Compal Electronics, Inc.

T30L-UART/OSC/PLL

V0JET(A210)-LA8981P

E

4.7P_0402_50V8J

C36

1 2

Y10

Y10 12MHZ_7PF_FL1200105

12MHZ_7PF_FL1200105

4.7P_0402_50V8J

C37

1 2

1

C40

2

@

PWR_I2C_SCL (16,17,29,31,33,4,7) PWR_I2C_SDA (16,17,29,31,33,4,7)

+VDD_1V8_SYS_TEGRA

PCB_ID3

7

0.1U_0402_10V6K

10K_0402_5%

35

R195

1 2

R163

1 2

A210@

@

1.0

A B C D E F G H

T30 Core Power

U1A

1/22 CORE POWER

A2

1

2

3

4

5

GND_001

A29

GND_002

AC11

GND_003

AC14

GND_004

AC17

GND_005

AC2

GND_006

AC20

GND_007

AC23

GND_008

AC26

GND_009

AC29

GND_010

AC5

GND_011

AC8

GND_012

AF11

GND_013

AF14

GND_014

AF17

GND_015

AF2

GND_016

AF20

GND_017

AF23

GND_018

AF26

GND_019

AF29

GND_020

AF5

GND_021

AF8

GND_022

AJ1

GND_023

AJ11

GND_024

AJ14

GND_025

AJ17

GND_026

AJ2

GND_027

AJ20

GND_028

AJ23

GND_029

AJ26

GND_030

AJ29

GND_031

AJ30

GND_032

AJ5

GND_033

AJ8

GND_034

AK2

GND_035

AK29

GND_036

B1

GND_037

B11

GND_038

B14

GND_039

B17

GND_040

B2

GND_041

B20

GND_042

B23

GND_043

B26

GND_044

B29

GND_045

B30

GND_046

B5

GND_047

B8

GND_048

E11

GND_049

E14

GND_050

E17

GND_051

E2

GND_052

E20

GND_053

E23

GND_054

E26

GND_055

E29

GND_056

E5

GND_057

E8

GND_058

H11

GND_059

H14

GND_060

H17

GND_061

H2

GND_062

H20

GND_063

H23

GND_064

H26

GND_065

H29

GND_066

H5

GND_067

H8

GND_068

L2

GND_069

L23

GND_070

L26

GND_071

L29

GND_072

L5

GND_073

L8

GND_074

M12

GND_075

M14

GND_076

M16

GND_077

M18

GND_078

N13

GND_079

N15

GND_080

N17

GND_081

N19

GND_082

P12

GND_083

P18

GND_084

P2

GND_085

P23

GND_086

P26

GND_087

P29

GND_088

P5

GND_089

P8

GND_090

R13

GND_091

R15

GND_092

R16

GND_093

R19

GND_094

T12

GND_095

T15

GND_096

T16

GND_097

T18

GND_098

U13

GND_099

U19

GND_100

U2

GND_101

U23

GND_102

U26

GND_103

U29

GND_104

U5

GND_105

U8

GND_106

V12

GND_107

V14

GND_108

V16

GND_109

V18

GND_110

W12

GND_111

W13

GND_112

W15

GND_113

W17

GND_114

W19

GND_115

Y2

GND_116

Y23

GND_117

Y26

GND_118

Y29

GND_119

Y5

GND_120

Y8

GND_121

(3.3V)

T30L-P-A3-1.2G_FCBGA728

(1.0 ~ 1.2V)

VDD_RTC_0001 VDD_RTC_0002

(0.9 ~ 1.0V)

VDD_CPU_01 VDD_CPU_02 VDD_CPU_03 VDD_CPU_04 VDD_CPU_05 VDD_CPU_06 VDD_CPU_07 VDD_CPU_08 VDD_CPU_09 VDD_CPU_10 VDD_CPU_11 VDD_CPU_12 VDD_CPU_13 VDD_CPU_14 VDD_CPU_15 VDD_CPU_16 VDD_CPU_17 VDD_CPU_18 VDD_CPU_19 VDD_CPU_20 VDD_CPU_21 VDD_CPU_22

(1.0 ~ 1.2V)

VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28

VDD_CPU_SENSE GND_CPU_SENSE

VVDD_CPU_SENSE

VGND_CORE_SENSE

VDD_CORE_SENSE GND_CORE_SENSE

VPP_FUSE

VPP_KFUSE

V22 V23

H10 J10 J8 K8

C2563

K9 M7

0.1U_0402_10V6K

M8 M9 N8 N9 P14 P15 P16 P17 R14 R17 T14 T17 U14 U15 U16 U17

M13 M15 M17 M19 N12 N14 N16 N18 N7 P13 P19 R12 R18 R7 R8 R9 T13 T19 T8 T9 U18 V13 V15 V17 V19 W14 W16 W18

AB12 AB15

AB16

VVDD_CPU_SENSE

AA23

VGND_CORE_SENSE

W23

VDD_CORE_SENSE

W22

GND_CORE_SENSE

AB8 AA4

VPP_KFUSE

R1395

10K_0402_5%

20mA@ 1.2V

10A@ 1.2375V(max)

1

C2564

0.1U_0402_10V6K

2

3A@ 1.3V(max)

1

C2582

C2581

0.1U_0402_10V6K

2

VDD_CPU_SENSE_PAIR

40mA@ 3.3V

1

C2600

0.1U_0402_10V6K

2

1 2

VDD_1V2_RTC_TEGRA

VDD_PMU_LDO4

1

C2562

0.1U_0402_10V6K

2

1

2

1

4.7U_0402_6.3V6M

2

90DIFF_NETCLASS1

90DIFF_NETCLASS1VVDD_CPU_SENSE_PAIR

C2656

1 2

4.7U_0402_6.3V6M

R1396

R1396 1K_0402_5%

1K_0402_5%

1

C2599

4.7U_0402_6.3V6M

2

1

C2655

C2584

4.7U_0402_6.3V6M

2

T22PAD@ T22PAD@ T23PAD@ T23PAD@

C2565

C2566

0.1U_0402_10V6K

2

1

C2583

0.1U_0402_10V6K

2

+VDD_3V3_FUSE_TEGRA

C E

1

C2568

C2567

C2598

4.7U_0402_6.3V6M

2

1

C2585

C2586

4.7U_0402_6.3V6M

2

Layout route as Diff. pair ( Z = 90 ohm )

VDD_CPU_SENSE (33) GND_CPU_SENSE (33)

Layout route as Diff. pair ( Z = 90 ohm )

T24PAD@ T24PAD@

T25PAD@ T25PAD@

T26PAD@ T26PAD@ T27PAD@ T27PAD@

Layout route as Diff. pair ( Z = 90 ohm )

VDD_CORE_SENSE (33) GND_CORE_SENSE (33)

1

C2570

C2569

4.7U_0402_6.3V6M

2

VDD_1V2_CORE_TEGRA

1

C2588

C2587

4.7U_0402_6.3V6M

2

4.7U_0402_6.3V6M

1

2

VDD_1V0_CPU_TEGRA

1

C2571

2

C2589

4.7U_0402_6.3V6M

0_0805_5%

1

VDD_1V0_GEN

J1

2

112

@ JUMP_43X118J1@ JUMP_43X118

1

C2572

2

VDD_1V2_SOC

R1392

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FDBA

For placement question, limint by H=0.5mm

VDD_1V0_CPU_TEGRA

1

C2573

C2576

C2575

C2574

C2574 1U_0402_10V6K

1U_0402_10V6K

2

For placement question, limint by H=0.5mm

VDD_1V2_CORE_TEGRA

1

C2592

C2593

C2591

C2590

1U_0402_10V6K

2

Compal Secret Data

Deciphered Date

1

C2577

C2578

C2579

C2580

C2580 1U_0402_10V6K

1U_0402_10V6K

2

1

C2594

2

2012/01/092012/05/20

1U_0402_10V6K

2

1

C2595

C2596

C2597

C2597 1U_0402_10V6K

1U_0402_10V6K

2

Title

Size Document Number Rev

Custom

Date: Sheet

G

Compal Electronics, Inc.

T30L-Core Power

V0JET(A210)-LA8981P

835Wednesday, June 13, 2012

H

2

3

4

5

1.0

of

5

4

3

2

1

T30 PEX Interface

U1T

20/22 PEX

(1.05V)

AB18

AVDD_PEXA_1

AB19

AVDD_PEXA_2

D D

(1.05V)

AD22

VDD_PEXA

(3.3V)

AB21

HVDD_PEX

(1.05V)

AC22

AE23

AE24

AF24

AVDD_PEXB

(1.05V)

VDD_PEXB

(1.05V)

AVDD_PEX_PLL

(3.3V)

VDDIO_PEX_CTL

5

C C

B B

A A

PEX_L0_TXN PEX_L0_TXP

PEX_L0_RXN PEX_L0_RXP

PEX_L1_TXN PEX_L1_TXP

PEX_L1_RXN PEX_L1_RXP

PEX_L2_TXN PEX_L2_TXP

PEX_L2_RXN PEX_L2_RXP

PEX_L3_TXN PEX_L3_TXP

PEX_L3_RXN PEX_L3_RXP

PEX_L4_TXN PEX_L4_TXP

PEX_L4_RXN PEX_L4_RXP

PEX_L5_TXN PEX_L5_TXP

PEX_L5_RXN PEX_L5_RXP

PEX_CLK1N PEX_CLK1P

PEX_CLK2N PEX_CLK2P

PEX_CLK3N PEX_CLK3P

PEX_REFCLKN PEX_REFCLKP

PEX_L0_CLKREQ*

PEX_L0_PRSNT*

PEX_L0_RST*

PEX_L1_CLKREQ*

PEX_L1_PRSNT*

PEX_L1_RST*

PEX_L2_CLKREQ*

PEX_L2_PRSNT*

PEX_L2_RST*

PEX_WAKE*

PEX_TESTCLKN PEX_TESTCLKP

PEX_TERMP

AG18 AF18

AJ19 AH19

AF19 AG19

AK22 AK21

AJ18 AH18

AK19 AK18

AK24 AK25

AJ21 AH21

AG21 AF21

AJ24 AH24

AJ25 AH25

AG22 AG23

AK28 AK27

AB24 AB23

AH27 AJ27

AJ22 AH22

AG24 AD25 AG26

AD26 AD24 AG27

AC21 AE22 AG25

AF22

AJ28 AH28

AG20

T30L-P-A3-1.2G_FCBGA728

75mA@ 1.05V

18mA@ 1.05V

10mA@ 3.3V

120mA@ 1.05V

4

T30 VI Interface

POR State/ After Wake State/ Wake-Up Events PU: Pull Up PD: Pull Down Z: High Impendance R: Reset H: Hold W: Wake-Up Event

U1F

19/22 VI

(1.2 / 1.8V)

AH30

VDDIO_VI

AVDD_SATA VDD_SATA HVDD_SATA AVDD_SATA_PLL

AE26

PD/H

VI_MCLK

AF25

PD/H

VI_PCLK

AD27

PD/H

VI_HSYNC

AG30

PD/H

VI_VSYNC

AF27

PD/H

VI_D00

AD30

PD/H

VI_D01

AH29

PD/H

VI_D02

AG28

PD/H/W

VI_D03

AE27

PD/H

VI_D04

AE25

PD/H

VI_D05

AG29

PD/H

VI_D06

AD29

PD/H

VI_D07

AE29

PD/H

VI_D08

AD28

PD/H

VI_D09

AE30

PD/H

VI_D10

AE28

PD/H

VI_D11

T30L-P-A3-1.2G_FCBGA728

T30 SATA Interface

U1U

21/22 NC

AC15 AF15 AC16 AG17

3

AVDD_SATA VDD_SATA HVDD_SATA AVDD_SATA_PLL

(1.05V)

(3.3V)

(1.05V)

SATA_TESTCLKN SATA_TESTCLKP

T30L-P-A3-1.2G_FCBGA728

SATA_L0_TXN SATA_L0_TXP

SATA_L0_RXN SATA_L0_RXP

SATA_TERMP

T30 SPARE Pins

U1V

22/22 NC

T30L-P-A3-1.2G_FCBGA728

AD16 AE16

AE19 AD19

AE21 AD21

AD18

2

T30L-P-A3-1.2G_FCBGA728

AB10

NC_37

AB5

NC_38

AC19

NC_39

AC9

NC_40

C25

NC_41

E13

NC_42

H25

NC_43

AB11

NC_1

AB14

NC_2

AB17

NC_3

AB20

NC_4

AB22

NC_5

AB9

NC_6

AE11

NC_7

AE14

NC_8

AE17

NC_9

AE20

NC_10

F11

NC_11

F14

NC_12

F17

NC_13

F20

NC_14

J11

NC_15

J14

NC_16

J17

NC_17

J20

NC_18

J22

NC_19

J9

NC_20

L22

NC_21

L25

NC_22

L6

NC_23

L9

NC_24

P22

NC_25

P25

NC_26

P6

NC_27

P9

NC_28

U22

NC_29

U25

NC_30

U6

NC_31

U9

NC_32

Y22

NC_33

Y25

NC_34

Y6

NC_35

Y9

NC_36

Title

Size Document Number Rev

C

Date: Sheet

T30L-PEX/SATA/VI

V0JET(A210)-LA8981P

1

of

935Wednesday, June 13, 2012

1.0

5

D D

C C

B B

4

3

2

1

A A

Title

<Title>

Size Document Number Rev

V0JET(A210)-LA8981P 1.0

C

V0JET(A210)-LA8981P 1.0

C

V0JET(A210)-LA8981P 1.0

C

Date: Sheet

5

4

3

2

Date: Sheet

1

of

10 35Wednesday, June 13, 2012

of

10 35Wednesday, June 13, 2012

of

10 35Wednesday, June 13, 2012

A B C D E F G

DDR3/DDR3L (page 1/2): 4pcs, 2Gbx4 memory chips: RANK 0: LOW 16 BITS

Note: Layout use the 82 ball biggest packages and co-Layout 78 ball A210 use 78 ball H5TC2G83CFR-H9A

1

U150A

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

M1_ZQ

U150

U151

U152

U153

F4

RAS*

G4

CAS*

H4

WE*

H3

CS*

K4

A[0]

L8

A[1]

L4

A[2]

K3

A[3]

L9

A[4]

L3

A[5]

M9

A[6]

M3

A[7]

N9

A[8]

M4

A[9]

H8

A[10]/AP

M8

A[11]

K8

A[12]/BC*

N4

A[13]

N8

A[14]

J3

BA[0]

K9

BA[1]

J4

BA[2]

G10

CKE

F8

CK

G8

CK*

F2

NC_F2

F10

NC_F10

H2

NC_H2

H10

NC_H10

N3

RESET*

G2

ODT

H9

ZQ

A1

NC_A1

A11

NC_A11

N1

NC_N1

N11

NC_N11

A4

NC_A4

J8

NC_J8

X76-H@

SA000055910

X76-H@

SA000055910

X76-H@

SA000055910

X76-H@

SA000055910

H5TC2G83BFR-PBA_FBGA82X76@

DDR_DQ4 DDR_DQ7 DDR_DQ0 DDR_DQ5 DDR_DQ2 DDR_DQ3 DDR_DQ1 DDR_DQ6

H5TC2G83CFR-H9A

DDR_RAS#(12,5) DDR_CAS#(12,5) DDR_WE#(12,5) DDR_CS0#(12,5) DDR_A[14..0](12,5)

U150

U151

U152

U153

DDR_BA0(12,5) DDR_BA1(12,5) DDR_BA2(12,5)

DDR_CKE0(12,5) DDR_CLKP(12,5) DDR_CLKN(12,5)

DDR_RESET#(12,5) DDR_ODT0(12,5)

DDR_A15(12,5)

K4B2G0846D-HYH9

X76-S@

SA00005KI10

K4B2G0846D-HYH9

X76-S@

SA00005KI10

K4B2G0846D-HYH9

X76-S@

SA00005KI10

K4B2G0846D-HYH9

X76-S@

SA00005KI10

1 2

R1398

R1398 243_0402_1%

243_0402_1%

DDR_A15 DDR_A15

DDR_DQ[31..0](12,5)

DDR_DM0(5) DDR_DQS0P(5) DDR_DQS0N(5)

2

3

4

5

A3

VDD[0]

A10

VDD[1]

D8

VDD[2]

G3

VDD[3]

G9

VDD[4]

K2

VDD[5]

K10

VDD[6]

M2

VDD[7]

M10

VDD[8]

B10

VDDQ[0]

C2

VDDQ[1]

E3

VDDQ[2]

E10

VDDQ[3]

B3

VSSQ[0]

B9

VSSQ[1]

C10

VSSQ[2]

D2

VSSQ[3]

D10

VSSQ[4]

A2

VSS[0]

A9

VSS[1]

B2

VSS[2]

D9

VSS[3]

F3

VSS[4]

F9

VSS[5]

J2

VSS[6]

J10

VSS[7]

L2

VSS[8]

L10

VSS[9]

N2

VSS[10]

N10

VSS[11]

E2

VREFDQ

J9

VREFCA

0.1U_0402_10V6K

1

2

U150B

B4

DQ[0]

C8

DQ[1]

C3

DQ[2]

C9

DQ[3]

E4

DQ[4]

E9

DQ[5]

D3

DQ[6]

E8

DQ[7]

A8

NF/TDQS*

B8

DM/TDQS

C4

DQS

D4

DQS*

H5TC4G83MFR-PBA_FBGA82X76@

700mA@ 1.35V

VDD_1V35_DDR3_MEM

0.1U_0402_10V6K

1

C2602

C2601

2

4.7U_0402_6.3V6M

1

C2611

2

4.7U_0402_6.3V6M

C2617

U156

U155

U160

U159

C2603

2

VDD_1V35_DDR3_MEM VDD_1V35_DDR3_MEM

0.1U_0402_10V6K

1

C2612

2

VDD_0V675_DDR3_VREF

0.1U_0402_10V6K

1

C2618

2

X76-E@

SA000055E10

EDJ2108EDBG-DJ-F

X76-E@

SA000055E10

EDJ2108EDBG-DJ-F

X76-E@

SA000055E10

EDJ2108EDBG-DJ-F

X76-E@

SA000055E10

C E G

0.1U_0402_10V6K

1

C2604

2

0.1U_0402_10V6K

1

C2613

2

VDD_1V35_DDR3_MEM

EDJ2108EDBG-DJ-F

0.1U_0402_10V6K

1

C2605

2

12

R1400

R1400 1K_0402_1%

1K_0402_1%

VDD_0V675_DDR3_VREF

12

R1401

NB DDR3 design

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_RAS# DDR_CAS# DDR_WE# DDR_CS0#

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CKE0 DDR_CLKP DDR_CLKN

DDR_RESET# DDR_ODT0

1 2

R1399

243_0402_1%

DDR_DM2(5) DDR_DQS2P(5) DDR_DQS2N(5)

F4 G4 H4 H3

K4

L8

L4 K3

L9

L3 M9 M3 N9 M4 H8 M8 K8 N4 N8

J3 K9

J4

G10

F8 G8

F2

F10

H2

H10

N3 G2

M4_ZQ

H9 A1

A11

N1

N11

A4

J8

Compal Secret Data

Deciphered Date

U151A

RAS* CAS* WE* CS*

A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]/AP A[11] A[12]/BC* A[13] A[14]

BA[0] BA[1] BA[2]

CKE CK CK*

NC_F2 NC_F10 NC_H2 NC_H10

RESET* ODT ZQ

NC_A1 NC_A11 NC_N1 NC_N11 NC_A4 NC_J8

A3

VDD[0]

A10

VDD[1]

D8

VDD[2]

G3

VDD[3]

G9

VDD[4]

K2

VDD[5]

K10

VDD[6]

M2

VDD[7]

M10

VDD[8]

B10

VDDQ[0]

C2

VDDQ[1]

E3

VDDQ[2]

E10

VDDQ[3]

B3

VSSQ[0]

B9

VSSQ[1]

C10

VSSQ[2]

D2

VSSQ[3]

D10

VSSQ[4]

A2

VSS[0]

A9

VSS[1]

B2

VSS[2]

D9

VSS[3]

F3

VSS[4]

F9

VSS[5]

J2

VSS[6]

J10

VSS[7]

L2

VSS[8]

L10

VSS[9]

N2

VSS[10]

N10

VSS[11]

E2

VREFDQ

J9

VREFCA

0.1U_0402_10V6K

H5TC4G83MFR-PBA _FBGA82X76@

DDR_DQ23 DDR_DQ18 DDR_DQ17 DDR_DQ22 DDR_DQ20 DDR_DQ19 DDR_DQ16 DDR_DQ21

2012/01/092012/05/20

0.1U_0402_10V6K

U151B

B4

DQ[0]

C8

DQ[1]

C3

DQ[2]

C9

DQ[3]

E4

DQ[4]

E9

DQ[5]

D3

DQ[6]

E8

DQ[7]

A8

NF/TDQS*

B8

DM/TDQS

C4

DQS

D4

DQS*

HH5TC4G83MFR-PBA_FBGA82X76@

VDD_1V35_DDR3_MEM

0.1U_0402_10V6K

1

C2606

2

4.7U_0402_6.3V6M

0.1U_0402_10V6K

1

C2614

2

4.7U_0402_6.3V6M

VDD_0V675_DDR3_VREF

0.1U_0402_10V6K

1

C2619

C2620

2

Title

Size Document Number Rev

C

Date: Sheet

FDBA

0.1U_0402_10V6K

1

2

1

2

Compal Electronics, Inc.

1

C2609

C2607

C2615

C2609

C2608

2

0.1U_0402_10V6K

1

C2616

2

DDR3_part1

V0JET(A210)-LA8981P

0.1U_0402_10V6K

1

C2610

2

1.0

of

11 35Wednesday, June 13, 2012