Compal LA-8971P VITU5, IdeaPad U510 Schematic

A

B

C

D

E

Compal Confidential

Model Name : VITU5

1 1

File Name : LA-8971P

Compal Confidential

2 2

VITU5 M/B Schematics Document

Intel Ivy Bridge ULV Processor + Panther Point PCH(HM77)

Nvidia chip:N13M-GS(23x23)

3 3

2012-02-16

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-8971P

E

0.1

1 58Thursday, February 16, 2012

0.1

A

Compal confidential

File Name :LA-8971P

B

C

D

E

Chief River

NV N13M-GS

1 1

23mm *23mm

PCI-E X16

VRAM 128*16

Gen 2

DDR3*4

Intel IVY Bridge ULV (Sandy Bridge)

Processor

BGA1023

DDR3-1333/1600

Dual Channel

DDR3-SO-DIMM X2

SATA3.0 HDD CONN

PCI Express (Full)

FDI *8

Std HDMI

Connector

2 2

LVDS Connector

6*PCI-E x1

Mini VGA Connector

100MHz

2.7GT/s

Intel Panther Point

HM77

FCBGA 989 Balls

25mm*25mm

PCI Express (Half) Mini card Slot 1

3 3

WLAN/WiMAX

PCI-E(WLAN)

SPI ROM

BIOS

4MB*1 2MB*1

ENE KB9012

LPC BUS

EC

DMI2 *4

100MHz 5GT/s

6*SATA

(port0,1 Support SATA3)

4*USB3.0

14*USB2.0

HD Audio

Mini card Slot 2

SSD(SATA3.0)

ODD (SATA2.0)

USB PORT 3.0 x1 (Left)

USB PORT 2.0 x2 (Right)

IO Board

Card Reader RTS 5178 (2in1)

IO Board

CMOS Camera

BlueTooth CONN

LAN(10/100/Giga)

Realtek 8105E-VD (10/100) 8111F-CGT (Giga)

Sub-borad

RJ45 CONN

ODD Board

4 4

POWER BOARD

LED BOARD

IO Board

USB2.0*2,card reader

A

B

Touch Pad

Thermal Sensor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Int.KBD

Compal Secret Data

2011/07/21 2012/12/31

Compal Secret Data

Deciphered Date

Audio Codec

D

RealTek ALC259-VC2-CG

Title

Size Document Number Rev

Custom

Date: Sheet of

2Channel Speaker

Single Digital MIC

Audio Combo Jack (APPLE type)

HeadPhone Output Microphone Input

Compal Electronics, Inc.

MB Block Diagram

LA-8971P

2 58Wednesday, February 15, 2012

E

0.2

A

Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

X

+5VALW

+3VALW

O

X

X X X

+1.5V

EC SM Bus2 address

Device

Thermal Sensor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb

1001 010Xb

AMD-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

SMBUS Control Table

SOURCE

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

4 4

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V

+3VS

A

X

+3VS

X

V

+3VS

X

V

B

+5VS

+3VS

+1.5VS

+V1.05S_VCCP

+VCC_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+1.05VS

O

X X

X

Address

1001_101xb

X

XX

V

+3VS

Thermal Sensor

X

WLAN WWAN

XX

X

V

+3VS

B

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

D

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

E

ONONON ON

ON

OFF

ON

OFF

LOW

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0

PCB Revision

0.1

1 2 3 4

OO

5 6 7

X

USB Port Table

X

USB 3.0

xHCI1 xHCI2 xHCI3 xHCI4

HM70 Disable xHCI3,xHCI4

USB 2.0 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

SATA Port Table

SATA P0

PCH

X

V

+3VS

SATA P1 SATA P2 SATA P3 SATA P4 SATA P5

HM70 Disable P1,P3

X

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

3 External USB Port

0

USB 3.0 Port (Left Side)

1 2 3 4 5 6 7 8

9 10 11 12 13

USB/B (Right Side USB-BD)

X (USB PORT disabled on HM70 )

Camera Blue Tooth Mini Card(WLAN)

USB Port (Right Side CR-BD)

X (USB PORT disabled on HM70 )

HM77

GEN3/2/1

GEN2/1

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V

1.935 V

2.500 V

HM70

GEN3/2/1

DisableGEN3/2/1

GEN2/1

Disable

GEN2/1

SSD

HDD (HM77)

HDD (HM70)

V typ

AD_BID

0.503 V

0.819 V

0 V

V

AD_BID

0.538 V

0.875 V

max

0 V

1.185 V 1.264 V

1.650 V 1.759 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

INTEL UMA only UMA@

XTX@ GPU:Seymour XTX

HDMI HDMI@ HDD1 (HM77 SATA 3.0) HDD1@ HDD2 (HM70 SATA 2.0) HDD2@ Interna-Intel-USB3.0 IU3@ Interna-Intel-USB2.0 IU2@ Blue Tooth BT@ 10/100 LAN 8105E@ GIGA LAN 8111F@ Connector ME@ 45 LEVEL 45@ Unpop

@

PCIe Port Table

HM77

PCIe P1 PCIe P2 PCIe P3 PCIe P4 PCIe P5 PCIe P6 PCIe P7 PCIe P8

Enable

HM70 Disable P5,P6,P7,P8

HM70

Enable

Disable

LAN

WLAN

Porject Phase

G-series

MP

G-series

PVT

G-series

DVT

G-series

EVT

Y-series

EVT

Y-series

DVT

Y-series

PVT

Y-series

MP

X

Security Classification

XX X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-7981P

3 58Wednesday, February 15, 2012

E

0.2

5

4

3

2

1

Hot plug detect for IFP link C

VGA and GDDR3 Voltage Rails (N13x GPIO)

GPIO I/O ACTIVE Function Description

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

OUT GPU VID4-

OUT

I/O

OUT

IN

OUT

IN

OUT

IN

-

GPU VID3OUT

Panel Back-Light brightness(PWM capable)

H

Panel Power Enable

H

Panel Back-Light On/Off (PWM)

H

GPU VID1

-

GPU VID2

-

N/A

Thermal Catastrophic Over Temperature

-

Thermal Alert

-

Memory VREF Control

-

GPU VID0-OUT

AC Power Detect Input

GPU VID5-

N/A

Hot plug detect for IFP link C

N/A

Hot Plug Detect for IFPE

N/A

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

(10K pull low)

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

+1.05VS_VGA

Performance Mode P0 TDP at Tj = 102 C* (GDDR3)

GPU Mem NVCLK

Products

N13P-GL 64bit 1GB GDDR3

Physical Strapping pin

ROM_SCLK

(4) (1,5) (6)

(W) (W) (MHz)

TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

TBD TBD

Power Rail

+3VS_VGA

(V) (A) (W) (A) (W)

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

FBVDD

Logical Strapping Bit2

SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

Device ID

N13P-GL (28nm)

N13M-GE (28nm)

GPU STRAP2 STRAP1 STRAP0

N13P-GL N13M-GE

???

FB Memory (GDDR3)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

K4G10325FG-HC04

H5GQ1H24BFR-T2C

K4G20325FG-HC04

H5GQ2H24MFR-T2CHynix

ROM_SO

32Mx32

32Mx32 PD 15K

PD 10K

64Mx32

FBVDDQ PCI Express I/O and (GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

(1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PCIE_MAX_SPEED DP_PLL_VDD33V

SOR0_EXPOSED

ROM_SCLK ROM_SI

PD 15K

PD 20KPD 10K PU 45K

PU 20K

PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K

PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K64Mx32

X76

I/O and PLLVDD

PD 35K

Other

(3.3V)(1.05V)(1.8V)

PU 45K

1. all power rail ramp up time should be larger than 40us

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

A A

1.all GPU power rails should be turned off within 10ms

5

Tpower-off <10ms

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

VGA Notes List

LA-7981P

4 58Wednesday, February 15, 2012

1

0.2

A

1 1

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16> DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16>

2 2

+1.05VS_VTT

12

R247

24.9_0402_1%

3 3

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms can't be left floating ,even if disable eDP function...

W=12mil L=500mil S=15mil

FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

EDP_COMP

B

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023

C

W=12mil L=500mil S=15mil

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13

PEG_GTX_C_HRX_N8

A11

PEG_GTX_C_HRX_N9

B10

PEG_GTX_C_HRX_N10

G8

PEG_GTX_C_HRX_N11

A8

PEG_GTX_C_HRX_N12

B6

PEG_GTX_C_HRX_N13

H8

PEG_GTX_C_HRX_N14

E5 K7

K22 K19 C21 D19 C19 D16 C13 D12

PEG_GTX_C_HRX_P8

C11

PEG_GTX_C_HRX_P9

C9

PEG_GTX_C_HRX_P10

F8

PEG_GTX_C_HRX_P11

C8

PEG_GTX_C_HRX_P12

C5

PEG_GTX_C_HRX_P13

H6

PEG_GTX_C_HRX_P14

F6 K6

G22 C23 D23 F21 H19 C17 K15 F17

PEG_HTX_GRX_N8

F14

PEG_HTX_GRX_N9

A15

PEG_HTX_GRX_N10

J14

PEG_HTX_GRX_N11

H13

PEG_HTX_GRX_N12

M10

PEG_HTX_GRX_N13

F10

PEG_HTX_GRX_N14

D9 J4

F22 A23 D24 E21 G19 B18 K17 G17

PEG_HTX_GRX_P8

E14

PEG_HTX_GRX_P9

C15

PEG_HTX_GRX_P10

K13

PEG_HTX_GRX_P11

G13

PEG_HTX_GRX_P12

K10

PEG_HTX_GRX_P13

G10

PEG_HTX_GRX_P14

D8 K4

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

eDP

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_COMP

+1.05VS_VTT

12

R249

24.9_0402_1%

C259 0.22U_0402_6.3V6KOPT@C259 0.22U_0402_6.3V6KOPT@

1 2

C276 0.22U_0402_6.3V6KOPT@C276 0.22U_0402_6.3V6KOPT@

1 2

C257 0.22U_0402_6.3V6KOPT@C257 0.22U_0402_6.3V6KOPT@

1 2

C274 0.22U_0402_6.3V6KOPT@C274 0.22U_0402_6.3V6KOPT@

1 2

C254 0.22U_0402_6.3V6KOPT@C254 0.22U_0402_6.3V6KOPT@

1 2

C272 0.22U_0402_6.3V6KOPT@C272 0.22U_0402_6.3V6KOPT@

1 2

C252 0.22U_0402_6.3V6KOPT@C252 0.22U_0402_6.3V6KOPT@

1 2

C270 0.22U_0402_6.3V6KOPT@C270 0.22U_0402_6.3V6KOPT@

1 2

C258 0.22U_0402_6.3V6KOPT@C258 0.22U_0402_6.3V6KOPT@

1 2

C277 0.22U_0402_6.3V6KOPT@C277 0.22U_0402_6.3V6KOPT@

1 2

C256 0.22U_0402_6.3V6KOPT@C256 0.22U_0402_6.3V6KOPT@

1 2

C275 0.22U_0402_6.3V6KOPT@C275 0.22U_0402_6.3V6KOPT@

1 2

C255 0.22U_0402_6.3V6KOPT@C255 0.22U_0402_6.3V6KOPT@

1 2

C273 0.22U_0402_6.3V6KOPT@C273 0.22U_0402_6.3V6KOPT@

1 2

C253 0.22U_0402_6.3V6KOPT@C253 0.22U_0402_6.3V6KOPT@

1 2

C271 0.22U_0402_6.3V6KOPT@C271 0.22U_0402_6.3V6KOPT@

1 2

C562 0.22U_0402_6.3V6KOPT@C562 0.22U_0402_6.3V6KOPT@

1 2

C582 0.22U_0402_6.3V6KOPT@C582 0.22U_0402_6.3V6KOPT@

1 2

C564 0.22U_0402_6.3V6KOPT@C564 0.22U_0402_6.3V6KOPT@

1 2

C584 0.22U_0402_6.3V6KOPT@C584 0.22U_0402_6.3V6KOPT@

1 2

C566 0.22U_0402_6.3V6KOPT@C566 0.22U_0402_6.3V6KOPT@

1 2

C587 0.22U_0402_6.3V6KOPT@C587 0.22U_0402_6.3V6KOPT@

1 2

C568 0.22U_0402_6.3V6KOPT@C568 0.22U_0402_6.3V6KOPT@

1 2

C589 0.22U_0402_6.3V6KOPT@C589 0.22U_0402_6.3V6KOPT@

1 2

C561 0.22U_0402_6.3V6KOPT@C561 0.22U_0402_6.3V6KOPT@

1 2

C583 0.22U_0402_6.3V6KOPT@C583 0.22U_0402_6.3V6KOPT@

1 2

C563 0.22U_0402_6.3V6KOPT@C563 0.22U_0402_6.3V6KOPT@

1 2

C585 0.22U_0402_6.3V6KOPT@C585 0.22U_0402_6.3V6KOPT@

1 2

C565 0.22U_0402_6.3V6KOPT@C565 0.22U_0402_6.3V6KOPT@

1 2

C586 0.22U_0402_6.3V6KOPT@C586 0.22U_0402_6.3V6KOPT@

1 2

C567 0.22U_0402_6.3V6KOPT@C567 0.22U_0402_6.3V6KOPT@

1 2

C588 0.22U_0402_6.3V6KOPT@C588 0.22U_0402_6.3V6KOPT@

1 2

D

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15PEG_GTX_C_HRX_N15

PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15PEG_GTX_C_HRX_P15

PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15PEG_HTX_GRX_N15

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15PEG_HTX_GRX_P15

E

PEG_GTX_HRX_N[8..15] <23> PEG_GTX_HRX_P[8..15] <23>

PEG_HTX_C_GRX_N[8..15] <23> PEG_HTX_C_GRX_P[8..15] <23>

4 4

Security Classification

2011/06/24 2012/07/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-8971P

5 58Wednesday, February 15, 2012

E

0.1

A

B

C

D

E

1 1

PCH->CPU UNCOREPWRGOOD:CORE󰇞󰇞󰇞󰇞OK SM_DRAMPWROK:DRAM power ok RESET#:ok󰒏󰒏󰒏󰒏CPUreset

Follow DG 1.5& Tacoma_Fall2 1.0

reserve

@

C614 0.1U_0402_16V4Z

12

R292

12

10K_0402_5%

2 2

H_CPUPWRGD_R

UNCOREPWRGOOD:CORE󰇞󰇞󰇞󰇞OK

3 3

SYS_PWROK<16>

PM_DRAM_PWRGD<16>

RUN_ON_CPU1.5VS3#<10>

+3VS

SYS_PWROK

SUSP<10,47,52>

R31 10K_0402_5%R31 10K_0402_5%

1 2

R60 10K_0402_5%@R60 10K_0402_5%@

1 2

0.1U_0402_16V4Z

PM_DRAM_PWRGD

RUN_ON_CPU1.5VS3#

C228

PROC_SELECT# PH VCPLL and connect to PCH DF_TVS

R534

4

H_CPUPWRGD<19>

1 2

62_0402_5%

+1.5V_CPU_VDDQ

2

G

12

1

2

+1.05VS_VTT

H_PROCHOT#<42,49>

+3VALW

B

A

R13

R14

5

P

O

G

U22

3

74AHC1G09GW_TSSOP5

@R13

@

1 2

0_0402_5%

@R14

@

1 2

0_0402_5%

XBOX 

12

R238

R238 200_0402_5%

200_0402_5%

PM_SYS_PWRGD_BUF

12

@

R38

R38 39_0402_5%

39_0402_5%

13

D

@

Q4

Q4 2N7002K_SOT23-3

2N7002K_SOT23-3

S

H_SNB_IVB#<18>

R35

@R35

@

12

10K_0402_5%

@

H_CATERR#

T33

T33 PAD

PAD

H_PECI<19,42>

R533

1 2

56_0402_5%

H_THERMTRIP#<19>

H_PM_SYNC<16>

R305

1 2

0_0402_5%

R237

1 2

130_0402_1%

H_PECI

H_PROCHOT#_RH_PROCHOT#

H_THERMTRIP#

H_PM_SYNC

H_CPUPWRGD_RH_CPUPWRGD

VDDPWRGOOD_R

BUF_CPU_RST#

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

0.1U_0402_16V4Z

UCPU1B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

IVY-BRIDGE_BGA1023

1 2

43_0402_5%

12

@

C43

R544

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

Buffered reset to CPU

+1.05VS_VTT

12

R546

R546 75_0402_5%

75_0402_5%

BUFO_CPU_RST#

MISC

4

Y

R9

+3VS

0_0402_5%

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

12

C617

0.1U_0402_16V4Z

U45

5

SN74LVC1G07DCKR_SC70-5

1

P

NC

PCH_PLTRST#

2

A

G

3

@R9

@

12

CLK_CPU_DMI

J3

CLK_CPU_DMI#

H2

CLK_CPU_DPLL

AG3

CLK_CPU_DPLL#

AG1

SM_RCOMP0,SM_RCOMP1 W=20mil L=500mil S=13mil

SM_RCOMP2 W=15mil L=500mil S=13mil

H_DRAMRST#

AT30

SM_RCOMP0

BF44

SM_RCOMP1

BE43

SM_RCOMP2

BG43

R516 1K_0402_5%R516 1K_0402_5% R517 1K_0402_5%R517 1K_0402_5%

R272 140_0402_1%R272 140_0402_1%

1 2

R273 25.5_0402_1%R273 25.5_0402_1%

1 2

R267 200_0402_1%R267 200_0402_1%

1 2

DDR3 Compensation Signals

N53 N55

XDP_TCK

L56

XDP_TMS

L55

XDP_TRST#

J58

XDP_TDI

M60

XDP_TDO

L59

XDP_DBRESET#

K58

G58 E55 E59 G55 G59 H60 J59 J61

PCH_PLTRST# <18>

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

1 2

12

+1.05VS_VTT

100P_0402_50V8J

1

@

C82

2

H_DRAMRST# <7>

ESD C Reserve

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R39 51_0402_5%R39 51_0402_5%

XDP_TDO

R37 51_0402_5%R37 51_0402_5%

XDP_TCK

R40 51_0402_5%R40 51_0402_5%

XDP_TRST#

R28 51_0402_5%R28 51_0402_5%

PU/PD for JTAG signals

XDP_DBRESET#

Tacoma_Fall2 1.0 PH 1K +3VS Check list 1.5 PH 1K +3VS Debug port DG1.1-1.3 50~5K ohm

R312 1K_0402_5%@R312 1K_0402_5%@

+1.05VS_VTT

12 12 12

12 12

+3VS

12

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/7) DDRIII

LA-8971P

E

6 58Wednesday, February 15, 2012

0.1

A

UCPU1C

AP11

AJ10

AR11

AT13 AU13

BA13 BB11

AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

UCPU1C

AG6

SA_DQ[0]

AJ6

SA_DQ[1] SA_DQ[2]

AL6

SA_DQ[3] SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7] SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13] SA_DQ[14] SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17] SA_DQ[18] SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR_A_D[0..63]<12>

1 1

2 2

DDR_A_BS0<12> DDR_A_BS1<12>

3 3

DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE# DDR_A_MA15

B

M_CLK_DDR0

AU36

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_CLK_DDR#0 DDR_CKE0_DIMMA

M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

M_ODT0 M_ODT1

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12> DDR_CS1_DIMMA# <12>

M_ODT0 <12> M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12>

C

UCPU1D

BD13 BF12

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59 AM60

AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17] SB_DQ[18] SB_DQ[19]

BF8

SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

DDR_B_D[0..63]<13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

D

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB

M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

M_ODT2 M_ODT3

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

E

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13> DDR_CS3_DIMMB# <13>

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

DDR_B_MA[0..15] <13>

IVY-BRIDGE_BGA1023

+1.5V

R216

@R216

@

1 2

0_0402_5%

R217

0_0402_5%

D

S

D

S

12

13

Q16

Q16 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

2

1

C190

0.047U_0402_16V7K

2

SM_DRAMRST#_R

CPUDIMMreset

H_DRAMRST#<6>

4 4

DRAMRST_CNTRL_PCH<10,15>

H_DRAMRST#

DRAMRST_CNTRL_PCH

A

4.99K_0402_1%

12

R212

1K_0402_5%

R219

1 2

1K_0402_5%

S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# HIGH Dimm not reset S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm reset

B

SM_DRAMRST# <12,13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

IVY-BRIDGE_BGA1023

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-8971P

E

7 58Wednesday, February 15, 2012

0.1

A

B

C

D

E

CFG Straps for Processor

UCPU1E

@

T32

T32 PAD

PAD

1 1

2 2

3 3

+CPU_CORE

12

+VGFX_CORE

12

R302

49.9_0402_1%

@

R91

R91 100_0402_1%

100_0402_1%

R306

49.9_0402_1%

R310

49.9_0402_1%

@

R95

R95 100_0402_1%

100_0402_1%

R311

49.9_0402_1%

VCC_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

VCC_VAL_SENSE VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

@

T18

T18 PAD

PAD

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RESERVED

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3

These pins are for solder joint

BE3

reliability and non-critical to

BG1 BE1

function. For BGA only.

BD1

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

eDP enable

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

*

CFG5

CFG6

R543

1K_0402_1%

11: (Default) 1x16 PCI Express

*

10: 2x8 PCI Express

12

R296

R296 1K_0402_1%

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

12

UMA,Optimus eDP DISO eDP󰡣󰡣󰡣󰡣

@

R293

R293 1K_0402_1%

1K_0402_1%

1:Disable

0:Enable

12

@

R541

R541 1K_0402_1%

1K_0402_1%

01: Reserved

00: 1x8,2x4 PCI Express

CFG7

12

@

R297

R297 1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion

Tacoma_Fall2 1.0 P.12

0: PEG Wait for BIOS for training

4 4

Security Classification

2011/06/24 2012/07/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-8971P

8 58Wednesday, February 15, 2012

E

0.1

A

1 1

INTEL Recommend VCC 4*470UF,12*22uF(0805) and 35*2.2uF(0402) PD0.8 CAP at Power side

2 2

3 3

4 4

B

UCPU1F

ULV type

UCPU1F

DC 33A

+CPU_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

C

POWER

CORE SUPPLY

8.5A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

PEG IO AND DDR IO

RAILS

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

D

+1.05VS_VTT

For DDR

INTEL Recommend VCCIO 2*330UF,10*10uF(0603) and 26*1uF(0402) PD0.8 CAP at Power side

For PEG

+3VS

12

R521

10K_0402_5%

+1.05VS_VTT

VCCIO_SEL

+1.05VS_VTT

12

C553

C553 1U_0402_6.3V6K

1U_0402_6.3V6K

VCCIO_SENSE VSSIO_SENSE_L

10K_0402_5%

VCCIO_SEL

10K_0402_5%

Place the PU resistors close to VR

R282 0_0402_5%R282 0_0402_5%

1 2

R289 0_0402_5%R289 0_0402_5%

1 2

R513 10_0402_5%R513 10_0402_5%

12

R512

R512 10_0402_5%

10_0402_5%

12

@

R522

12

R531

R531 130_0402_5%

130_0402_5%

12

VCCIO_SEL after Ivy bridge ES2 Voltage support

1/NC : (Default) +1.05VS_VTT

BC22

*

0: +1.0VS_VTT

R528 43_0402_1%

1 2

R527 0_0402_5%

1 2

R530 0_0402_5%

1 2

R79

@R79

@

1 2

100_0402_1%

+1.05VS_VTT

VCCIO_SENSE <54> VSSIO_SENSE_L <54>

Check list 1.5

+CPU_CORE

12

+1.05VS_VTT+1.05VS_VTT

Place the PU resistors close to CPU

R529

R529 75_0402_5%

75_0402_5%

VCCSENSE <56> VSSSENSE <56>

Should change to connect form power cirucit & layout differential with VCCIO_SENSE.

R281

R281 100_0402_1%

100_0402_1%

R288

R288 100_0402_1%

100_0402_1%

12

E

VR_SVID_ALRT# <56> VR_SVID_CLK <56> VR_SVID_DAT <56>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-8971P

E

9 58Wednesday, February 15, 2012

0.1

A

R65 0_0402_5%R65 0_0402_5%

R78

100K_0402_5%

@

Q6

2

G

1 2

+3VALW

12

@

RUN_ON_CPU1.5VS3#

13

D

S

SUSP<6,47,52>

1 1

2N7002K_SOT23-3

R81 0_0402_5%@R81 0_0402_5%@

CPU1.5V_S3_GATE<42,47>

SUSP#<42,47,52,54>

1 2

R82 @ 0_0402_5%R82 @ 0_0402_5%

1 2

2N7002K_SOT23-3

INTEL Recommend VAXG 2*470uF,6*22uF(0805) and 6*10uF(0603) 11*1U(0402) PD0.8

2 2

CR CheckList Rev1.5

1

@

+

C287

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+VGFX_CORE

22U_0805_6.3V6M

12

Place TOP IN BGA

C309

12

Place BOT OUT BGA

C577

12

INTEL Recommend VCCPLL

3 3

4 4

1*330uF,2*1uF(0402) PD0.8

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

B phase Cost down proposal

VCC_AXG_SENSE<56>

VSS_AXG_SENSE<56>

+1.8VS

Place BOT OUT Conn

+VCCSA

330U_2.5V_M

SF000002Z00

1

+

C242

C242 330U_D2_2V_Y

330U_D2_2V_Y

2

INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402) PD0.8

A

C633

1U_0402_6.3V6K

10U_0603_6.3V6M

+VGFX_CORE

12

R308

100_0402_5%

12

R309

100_0402_5%

10U_0603_6.3V6M

+VCCSA

1U_0402_6.3V6K

C302

12

10U_0603_6.3V6M

C560

12

C153

12

C300

12

C555

12

B

+VSB

2

G

RUN_ON_CPU1.5VS3# <6>

@

R87

1 2

100_0402_5%

1U_0402_6.3V6K

C280

C281

1

2

1U_0402_6.3V6K

C301

12

10U_0603_6.3V6M

C579

12

B

+1.5V

12

R85

R85 82K_0402_5%

82K_0402_5%

13

D

Q8

Q8 2N7002K_SOT23-3

2N7002K_SOT23-3

S

DC 29A

1U_0402_6.3V6K

C308

C559

1 2

U11

U11 AO4430L_SO8

AO4430L_SO8

8 7 6 5

RUN_ON_CPU1.5VS3

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59

W50 W51 W52 W53 W55 W56 W61

Y48 Y61

F45 G45

1.2A

BB3

BC1 BC4

6A

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21

W20

+1.5V_CPU_VDDQ

J1 @

PAD-OPEN 4x4m

4

R175

1 2

15K_0402_1%

12

@

R77

R77 330K_0402_5%

330K_0402_5%

UCPU1G

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

VAXG_SENSE VSSAXG_SENSE

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

IVY-BRIDGE_BGA1023

1 2 3

12

POWER

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

12

R80

220_0402_5%

13

D

S

C115

0.047U_0603_25V7K

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18]

DDR3 - 1.5V RAILS

VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

VCCSA VID

lines

VCCSA VID

lines

C

12

@

C116

0.1U_0402_10V6K

RUN_ON_CPU1.5VS3#

2

G

Q7

Q7 2N7002K_SOT23-3

2N7002K_SOT23-3

+V_SM_VREF_CNT +V_SM_VREF

AY43

SA_DIMM_VREFDQ

BE7

SB_DIMM_VREFDQ

BG7

1K_0402_1%

12

@

R519

+1.5V_CPU_VDDQ +1.5V

C150 0.1U_0402_10V7KC150 0.1U_0402_10V7K

C151 0.1U_0402_10V7KC151 0.1U_0402_10V7K

C152 0.1U_0402_10V7KC152 0.1U_0402_10V7K

C157 0.1U_0402_10V7KC157 0.1U_0402_10V7K

+V_SM_VREF_CNT should have 20 mil trace width

C117

0.1U_0402_16V4Z

12

@

R518

1K_0402_1%

12

D

12

+1.5V_CPU_VDDQ +1.5V

12

R113

R113 1K_0402_1%~D

1K_0402_1%~D

12

R124

R124 1K_0402_1%~D

1K_0402_1%~D

R117 0_0402_5%@R117 0_0402_5%@

S

G

12

D

123

@

Q11

Q11 AO3414_SOT23-3

AO3414_SOT23-3

RUN_ON_CPU1.5VS3

5A

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

+1.5V_CPU_VDDQ

AM28 AN26

BC43 BA43

R248

U10

CPU EDS1.3 P.93 VCCSA_VID0 Must PD

H_VCCSA_VID0

D48

H_VCCSA_VID1

D49

C

Place TOP IN BGA

1U_0402_6.3V6K

C351

12

10U_0603_6.3V6M

12

C340

1U_0402_6.3V6K

C348

C328

12

Place BOT OUT BGA

10U_0603_6.3V6M

12

C338

C337

VCCSA_SENSE <53>

H_VCCSA_VID0 <53> H_VCCSA_VID1 <53>

1U_0402_6.3V6K

C321

C329

12

C317

C317 1U_0402_6.3V6K

1U_0402_6.3V6K

@R248

@

1 2

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1U_0402_6.3V6K

C312

12

10U_0603_6.3V6M

12

C296

2011/06/24 2012/07/12

C318

12

10U_0603_6.3V6M

12

C295

1U_0402_6.3V6K

C320

12

10U_0603_6.3V6M

12

C299

Compal Secret Data

1U_0402_6.3V6K

C349

12

10U_0603_6.3V6M

12

C339

VID0

0

1 1

Deciphered Date

D

VID1

12

0

1

0 X1

+1.5V_CPU_VDDQ

C316

1

+

C286

C286 330U_2.5V_M

330U_2.5V_M

SF000002Z00

2

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

C298

VCCSA

Vout

0.9V

0.85V

0.725V

0.675V

HR CR

V V

V

M3 Support

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

R86

@R86

@

1 2

0_0402_5%

D

S

D

S

13

Q9

G

BSS138_NL_SOT23-3

G

2

DRAMRST_CNTRL_PCH

R148

@R148

@

1 2

0_0402_5%

D

S

D

S

13

Q10

G

2

DRAMRST_CNTRL_PCH

12

@

R76

R76 1K_0402_1%~D

1K_0402_1%~D

12

@

R116

R116 1K_0402_1%~D

1K_0402_1%~D

SA_DIMM_VREFDQ SB_DIMM_VREFDQ Check list1.5 P18 M1 default M3 no stuff

INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.8

V

VX

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet of

LA-8971P

E

+V_DDR_REFA

DRAMRST_CNTRL_PCH <7,15>

+V_DDR_REFB

E

0.1

10 58Wednesday, February 15, 2012

0.1

A

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

1 1

2 2

3 3

4 4

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1023

VSS

A

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

B

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023

Security Classification

B

VSS

NCTF

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

M4

VSS[250]

M58

VSS[251]

M6

VSS[252]

N1

VSS[253]

N17

VSS[254]

N21

VSS[255]

N25

VSS[256]

N28

VSS[257]

N33

VSS[258]

N36

VSS[259]

N40

VSS[260]

N43

VSS[261]

N47

VSS[262]

N48

VSS[263]

N51

VSS[264]

N52

VSS[265]

N56

VSS[266]

N61

VSS[267]

P14

VSS[268]

P16

VSS[269]

P18

VSS[270]

P21

VSS[271]

P58

VSS[272]

P59

VSS[273]

P9

VSS[274]

R17

VSS[275]

R20

VSS[276]

R4

VSS[277]

R46

VSS[278]

T1

VSS[279]

T47

VSS[280]

T50

VSS[281]

T51

VSS[282]

T52

VSS[283]

T53

VSS[284]

T55

VSS[285]

T56

VSS[286]

U13

VSS[287]

U8

VSS[288]

V20

VSS[289]

V61

VSS[290]

W13

VSS[291]

W15

VSS[292]

W18

VSS[293]

W21

VSS[294]

W46

VSS[295]

W8

VSS[296]

Y4

VSS[297]

Y47

VSS[298]

Y58

VSS[299]

Y59

VSS[300]

G48

VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

Compal Secret Data

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

LA-8971P

E

0.1

11 58Wednesday, February 15, 2012

E

A

B

C

D

E

+1.5V



12

RD1

RD1 1K_0402_1%

1K_0402_1%

+V_DDR_REFA

1 1

2 2

3 3

4 4

1K_0402_1%

12

1

RD2

2

CD2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

A

1

2

CD1

CD3

0.1U_0402_10V6K

1

2

CD23

2.2U_0603_6.3V4Z

1

2

CD24

0.1U_0402_10V6K

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE#

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

12

RD7

10K_0402_5%



DDR3 SO-DIMM A

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

12

RD8

10K_0402_5%

VTT

205

GND1

207

BOSS1

TYCO_2-2013022-1

CONN@

B

DQS0#

DQS0

RESET#

DQS3#

DQS3

VREF_CA

DQS5#

DQS5

DQS7#

DQS7

EVENT#

GND2

BOSS2

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1 CK1#

VDD

RAS#

VDD

ODT0

VDD ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

VSS DQ62 DQ63

VSS

SDA

SCL

VTT

+1.5V+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_CKE1_DIMMA

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

BA1

S0#

NC

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0DDR_A_CAS#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47DDR_A_D43

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS





SM_DRAMRST# <7,13>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

1

2

CD5

CD6

0.1U_0402_10V6K

PCH_SMBDATA <13,15,40,43> PCH_SMBCLK <13,15,40,43>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

+1.5V

1

+

2

CD4

330U_B2_2.5VM_R15M

+1.5V

12

RD5

RD5 1K_0402_1%

1K_0402_1%

+VREF_CA

12

RD6

RD6 1K_0402_1%

1K_0402_1%

2.2U_0603_6.3V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

Layout Note: Place near JDIMM1

1

2

CD7

10U_0603_6.3V6M

Custom

1

2

CD8

CD9

10U_0603_6.3V6M

Layout Note: Place these 4 Caps near Command and Control signals of JDIMM1

+1.5V

CD20

CD19

Layout Note: Place near JDDRL.203,204

+0.75VS

Title

Size Document Number Rev

Date: Sheet of

0.1U_0402_10V6K

1

2

CD15

CD16

1U_0402_6.3V6K

Compal Electronics, Inc.

DDRIII DIMMB

LA-8971P

1

2

CD10

10U_0603_6.3V6M

CD21

0.1U_0402_10V6K

1

2

CD17

1U_0402_6.3V6K

1

@

2

CD11

CD12

10U_0603_6.3V6M

CD22

0.1U_0402_10V6K

1

2

CD18

1U_0402_6.3V6K

12 58Wednesday, February 15, 2012

E

12 58Wednesday, February 15, 2012

1

@

2

CD13

CD14

10U_0603_6.3V6M

0.1

5

4

3

2

1

+1.5V

12

RD9

1K_0402_1%

D D

C C

B B

A A

RD10

1K_0402_1%

12

+V_DDR_REFB

DDR_B_D0

1

2

CD35

+3VS

1

2

CD27

CD36

0.1U_0402_10V6K

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

1

2

CD47

2.2U_0603_6.3V4Z

5

DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

2.2U_0603_6.3V4Z

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS# M_ODT2

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

RD13

1 2

10K_0402_5%

1

2

CD48

0.1U_0402_10V6K

+1.5V +1.5V





JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

RD14

1 2

10K_0402_5%

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

CONN@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18 20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

SM_DRAMRST#

30 32

DDR_B_D14

34

DDR_B_D15

36 38

DDR_B_D20

40

DDR_B_D21

42 44

DDR_B_DM2

46 48

DDR_B_D22

50

DDR_B_D23

52 54

DDR_B_D28

56

DDR_B_D29

58 60

DDR_B_DQS#3

62

DDR_B_DQS3

64 66

DDR_B_D30

68

DDR_B_D31

70 72

DDR_CKE3_DIMMB

74 76

DDR_B_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

4

DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB#

M_ODT3

+VREF_CB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PCH_SMBDATA PCH_SMBCLK





SM_DRAMRST# <7,12>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

1

2

CD45

CD46

0.1U_0402_10V6K

PCH_SMBDATA <12,15,40,43> PCH_SMBCLK <12,15,40,43>

+0.75VS

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

Layout Note: Place near JDIMM2

+1.5V

1

+

@

2

CD28

CD29

10U_0603_6.3V6M

330U_B2_2.5VM_R15M

Layout Note: Place these 4 Caps near Command and Control signals of JDIMM2

+1.5V

CD37

CD38

+1.5V

12

RD11

RD11 1K_0402_1%

1K_0402_1%

12

RD12

RD12 1K_0402_1%

1K_0402_1%

2.2U_0603_6.3V4Z

+VREF_CB

Layout Note: Place near JDIMM2.203 and 204

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

2

0.1U_0402_10V6K

+0.75VS

1

2

CD41

CD38

1

2

CD42

1U_0402_6.3V6K

1

@

2

CD30

CD25

0.1U_0402_10V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

CD40

CD39

0.1U_0402_10V6K

1

2

CD43

CD44

1U_0402_6.3V6K

Title

Size Document Number Rev

Custom

Date: Sheet of

1

2

CD31

10U_0603_6.3V6M

0.1U_0402_10V6K

Compal Electronics, Inc.

DDRIII DIMMB

LA-8971P

1

2

CD32

CD33

10U_0603_6.3V6M

1

2

CD34

CD26

10U_0603_6.3V6M

1

10U_0603_6.3V6M

0.1

13 58Wednesday, February 15, 2012

0.1

CLRP1/2 close RAM door JDIMM1/2

A

B

+RTCBATT+RTCVCC

C

D

E

W=20mils W=20mils

R59

2

CLRP1

CLRP1 SHORT PADS

C439

1U_0603_10V6K

+RTCVCC

R356

1 2

20K_0402_5%

R357

1 2

20K_0402_5%

C440

1 1

+RTCVCC

R358 1M_0402_5%

R363 330K_0402_5%

*

C440

1U_0603_10V6K

1 2

INTVRMEN

HIntegrated VRM enable

Integrated VRM disable

L



SHORT PADS

1 2

1

PCH_RTCRST#

PCH_SRTCRST#

1

12

CLRP2

CLRP2 SHORT PADS

SHORT PADS

2

SM_INTRUDER# PCH_SPKR

PCH_INTVRMEN

1M_0402_5%

1

C441

C441 1U_0603_10V4Z

1U_0603_10V4Z

2

Prevent back drive issue.

1 2

0_0402_5%

12

R29

(INTVRMEN should always be pull high.)

+3VS

R109 1K_0402_5%@

1 2

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

LOW= Disable (Default internal PD)

*

+3V_PCH

2 2

HDA_SDO

ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when sampled high

*

1.8V when sampled low Needs to be pulled High for Huron River platfrom

3 3

1 2

1K_0402_5%

ME_FLASH<42>

R47 1K_0402_5%

HDA_BITCLK_AUDIO<31>

HDA_SYNC_AUDIO<31>

HDA_RST_AUDIO#<31>

HDA_SDOUT_AUDIO<31>

12

R134

R134 200_0402_5%

200_0402_5%

12

R141

R141 100_0402_1%

100_0402_1%

1 2

0_0402_5%

12

+3V_PCH+3V_PCH +3V_PCH

R46

@ R46

@

R73

12

R143

R143 200_0402_5%

200_0402_5%

12

R140

R140 100_0402_1%

100_0402_1%

R75

1 2

33_0402_5%

R30

1 2

33_0402_5%

R74

1 2

33_0402_5%

R72

1 2

33_0402_5%

PCH_SPKR

HDA_SDOUT_PCH

HDA_SYNC_PCH

HDA_BITCLK_PCH

HDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

R137

R137 200_0402_5%

200_0402_5%

PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS

12

R142

R142 100_0402_1%

100_0402_1%

PCH_SPI_CLK_2

PCH_SPI_CLK_1

PCH_SPI_CS0#_1

PCH_SPI_CS1#_2 PCH_SPI_CS1#

PCH_SPI_MOSI_2

PCH_SPI_MOSI_1

PCH_SPI_MISO_1

PCH_SPI_MISO_2

R433 33_0402_5%WIN8@R433 33_0402_5%WIN8@

R432 33_0402_5%

R127 33_0402_5%

R446 33_0402_5%WIN8@R446 33_0402_5%WIN8@

R123 33_0402_5%WIN8@R123 33_0402_5%WIN8@

R122 33_0402_5%

R437 33_0402_5%

R438 33_0402_5%WIN8@R438 33_0402_5%WIN8@

12

1K_0402_5%

+5VS

G

2

Q3

Q3 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

D

S

D

S

R48

@R48

@

12

+3VS

SPI ROM FOR ME (4MB) Footprint 200mil

+3VS

SPI ROM FOR ME (2MB) Footprint 200mil

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCHHDA_SYNC_PCH_R

PCH_SPKR<31>

HDA_SDIN0<31>

51_0402_5%

R22 3.3K_0402_5%

1 2

R89 3.3K_0402_5%

1 2

R21 3.3K_0402_5%WIN8@R21 3.3K_0402_5%WIN8@

1 2

R88 3.3K_0402_5%WIN8@R88 3.3K_0402_5%WIN8@

1 2

R100

HDA_RST_PCH#

HDA_SDIN0

HDA_SDOUT_PCH

PCH_JTAG_TCK

12

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_MOSI

PCH_SPI_MISO

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

PCH_SPI_CS0#_1 SPI_WP1# SPI_HOLD1#

PCH_SPI_CS1#_2 SPI_WP2# SPI_HOLD2#

U13A

RTCX1

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

COUGARPOINT_FCBGA989

U44

1

CS#

3

WP#

7

HOLD#

4

GND

MX25L3206EM2I-12G_SO8

SA000041P00

U46

WIN8@U46

WIN8@

1

CS#

3

WP#

7

HOLD#

4

GND

MX25L1606EM2I-12G_SO8

SA000041N00

RTCIHDA

JTAG

SPI

VCC

SCLK

SO

VCC

SCLK

SO

LPC

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

8 6 5

SI

2

8 6 5

SI

2

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

+3VS

PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1

+3VS

PCH_SPI_CLK_2 PCH_SPI_MOSI_2 PCH_SPI_MISO_2

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36 K36

SERIRQ

V5

SATA_PRX_DTX_N0

AM3

SATA_PRX_DTX_P0

AM1 AP7 AP5

SATA_PRX_C_DTX_N1_R

AM10

SATA_PRX_C_DTX_P1_R

AM8

SATA_PTX_DRX_N1_R

AP11

SATA_PTX_DRX_P1_R

AP10

SATA_PRX_C_DTX_N2

AD7

SATA_PRX_C_DTX_P2

AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8 AB10 AF3 AF1

SATA_PRX_C_DTX_N4

Y7

SATA_PRX_C_DTX_P4

Y5

SATA_PTX_DRX_N4

AD3

SATA_PTX_DRX_P4

AD1

Y3 Y1 AB3 AB1

Y11

L=500mil S=15mil

SATA_COMP

Y10

AB12

L=500mil S=15mil

SATA3_COMP

AB13

RBIAS_SATA3

AH1

PCH_SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0_R

P1

LPC_AD0 <40,42> LPC_AD1 <40,42> LPC_AD2 <40,42> LPC_AD3 <40,42>

LPC_FRAME# <40,42>

R118

12

10K_0402_5%

+3VS

SERIRQ <42>

C127 0.01U_0402_16V7KC127 0.01U_0402_16V7K C131 0.01U_0402_16V7KC131 0.01U_0402_16V7K

Disable w/ HM70

R121

1 2

37.4_0402_1%

R126

1 2

49.9_0402_1%

R440

1 2

750_0402_1%

R429 10K_0402_5%R429 10K_0402_5%

R136 10K_0402_5%R136 10K_0402_5%

R466 10K_0402_5%R466 10K_0402_5%

@

1 2

C459

10P_0402_50V8J

12 12

SATA_PRX_C_DTX_N1_R <38> SATA_PRX_C_DTX_P1_R <38> SATA_PTX_DRX_N1_R <38> SATA_PTX_DRX_P1_R <38>

SATA_PRX_C_DTX_N2 <38> SATA_PRX_C_DTX_P2 <38> SATA_PTX_DRX_N2 <38> SATA_PTX_DRX_P2 <38>

SATA_PRX_C_DTX_N4 <39> SATA_PRX_C_DTX_P4 <39> SATA_PTX_DRX_N4 <39> SATA_PTX_DRX_P4 <39>

+1.05VS_VTT

12

Reserve for EMI

PCH_SPI_CLK

@

12

R434 33_0402_5%

+3VS

SATA_PRX_DTX_N0 <40>

SATA_PTX_DRX_N0SATA_PTX_C_DRX_N0 SATA_PTX_DRX_P0SATA_PTX_C_DRX_P0

SATA_PRX_DTX_P0 <40> SATA_PTX_DRX_N0 <40> SATA_PTX_DRX_P0 <40>

mSATA

HDD for HM77

HDD for HM70

ODD

Boot BIOS Strap

Boot BIOS

LPC

Reserved

SPI

*

-

GPIO51

0 0 0 1 1 1

GPIO19

1 0

PCH_RTCX1

R406

1 2

10M_0402_5%

4 4

Y2

1 2

32.768KHZ_12.5PF_9H03200019

1

C452

C452 18P_0402_50V8J

18P_0402_50V8J

2

PCH_RTCX2

1

C451

C451 18P_0402_50V8J

18P_0402_50V8J

2

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC, XDP

LA-8971P

E

14 58Wednesday, February 15, 2012

0.1

A

PCIE_DTX_C_PRX_N1<33>

PCIE LAN

WLAN

1 1

2 2

WLAN

PCIE_DTX_C_PRX_P1<33> PCIE_PTX_C_DRX_N1<33> PCIE_PTX_C_DRX_P1<33>

PCIE_PRX_DTX_N2<40>

PCIE_PRX_DTX_P2<40> PCIE_PTX_C_DRX_N2<40> PCIE_PTX_C_DRX_P2<40>

CLK_PCIE_WLAN1#<40> CLK_PCIE_WLAN1<40>

PCIE LAN

3 3

4 4

C480 0.1U_0402_16V7KC480 0.1U_0402_16V7K C478 0.1U_0402_16V7KC478 0.1U_0402_16V7K

C482 0.1U_0402_16V7KC482 0.1U_0402_16V7K C481 0.1U_0402_16V7KC481 0.1U_0402_16V7K

+3V_PCH

1 2 1 2

WLAN_CLKREQ#<40>

+3VS

CLK_PCIE_LAN#<33> CLK_PCIE_LAN<33>

LAN_CLKREQ#<33>

+3V_PCH

1 2 1 2

1 2

10K_0402_5%

R287 0_0402_5%R287 0_0402_5% R291 0_0402_5%R291 0_0402_5%

10K_0402_5%

WLAN_CLKREQ#

R215 10K_0402_5%R215 10K_0402_5%

1 2

R110

1 2

10K_0402_5%

CLK_PCIE_LAN#

LAN_CLKREQ#

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

HM70 not support PCIE port 4-7

R213

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

R214

R53

R50

R54

R32

R51

B

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCH_GPIO73

PCH_GPIO20

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

U13B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

COUGARPOINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / CLKOUT_BCLK1_N

CLKOUT_DP_P / CLKOUT_BCLK1_P

C

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

PCH_GPIO11

E12

PCH_SMBCLK_R

H14

PCH_SMBDATA_R

C9

DRAMRST_CNTRL_PCH

A12

PCH_SML0CLK

C8

PCH_SML0DATA

G12

PCH_HOT#

C13

PCH_SML1CLK

E14

PCH_SML1DATA

M16

M7

T11

P10

PEG_CLKREQ#_R

M10

CLK_PCIE_VGA#

AB37

CLK_PCIE_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLK_BUF_CPU_DMI#

BF18

CLK_BUF_CPU_DMI

BE18

CLKIN_GND1#

BJ30

CLKIN_GND1CLK_PCIE_LAN

BG30

CLK_BUF_DREF_96M#

G24

CLK_BUF_DREF_96M

E24

CLK_BUF_PCIE_SATA#

AK7

CLK_BUF_PCIE_SATA

AK5

CLK_BUF_ICH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

W=12mil S=15mil

XCLK_RCOMP

Y47

K43

F47

CLK_FLEX2

H47

DGPU_PRSNT#

K49

R33 10K_0402_5%R33 10K_0402_5%

12

DRAMRST_CNTRL_PCH <7,10>

PCH_HOT# <42>

CLK_PCIE_VGA# <23> CLK_PCIE_VGA <23>

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

R152 10K_0402_5%

1 2

R147 10K_0402_5%

1 2

R453 10K_0402_5%

1 2

R452 10K_0402_5%

1 2

R99 10K_0402_5%

1 2

R93 10K_0402_5%

1 2

R139 10K_0402_5%

1 2

R138 10K_0402_5%

1 2

R101 10K_0402_5%

1 2

R96

@ R96

@

1 2

33_0402_5%

Reserve for EMI please close to PCH

R120

12

90.9_0402_1%

T26 PAD@ T26 PAD@

R4082.2K_0402_5% R4082.2K_0402_5%

12

R3732.2K_0402_5% R3732.2K_0402_5%

12

CLK_PCI_LPBACK <18>

22P_0402_50V8J

+1.05VS_VTT

+3V_PCH

@

1 2

C29

DGPU_PRSNT#

DIS,Optimus

D

+3V_PCH

UMA

PCH_SMBDATA_R

PCH_SMBCLK_R

PCH_SML1DATA

PCH_SML1CLK

PEG_CLKREQ#_R

+3VS

12

UMA@

R421

R421 10K_0402_5%

10K_0402_5%

12

OPT@

R420

R420 10K_0402_5%

10K_0402_5%

GPIO67

DGPU_PRSNT#

0 1

6 1

DMN66D0LDW-7_SOT363-6

6 1

DMN66D0LDW-7_SOT363-6

+3V_PCH

12

R27

10K_0402_5%

12

@

R23

2.2K_0402_5%

XTAL25_IN

XTAL25_OUT

PCH_SMBCLK_R

PCH_SMBDATA_R

DRAMRST_CNTRL_PCH

PCH_HOT#

PCH_SML1CLK

PCH_SML1DATA

+3VS

2

Q34A

5

3 4

Q34B

+3VS

2

Q33A

10P_0402_50V8J

3 4

2

1 3

D

5

Q33B

OPT@ R8

OPT@

10K_0402_5%

1 2

0.1U_0402_16V4Z

OPT@

G

Q2

Q2 2N7002K_SOT23-3

2N7002K_SOT23-3

S

1

C457

2

E

R405 2.2K_0402_5%R405 2.2K_0402_5%

1 2

R370 2.2K_0402_5%R370 2.2K_0402_5%

1 2

R391 1K_0402_5%R391 1K_0402_5%

1 2

R392 10K_0402_5%R392 10K_0402_5%

1 2

R403 2.2K_0402_5%R403 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

1 2

For DDR

R404

12

4.7K_0402_5%

R371

4.7K_0402_5%

Pull up at EC side. For VGA,EC,Thermal sensor

EC_SMB_DA2

EC_SMB_CK2

R8

12

C123

OPT@C123

OPT@

12

@

R12

2.2K_0402_5%

1 2

1M_0402_5%

Y6

Y6 25MHZ_10PF_7V25000014

25MHZ_10PF_7V25000014

3

GND

+3VS

PCH_SMBDATA <12,13,40,43>

12

+3VS

PCH_SMBCLK <12,13,40,43>

EC_SMB_DA2 <23,42,44>

EC_SMB_CK2 <23,42,44>

DGPU_PWR_EN <18,30,55>

PEG_CLKREQ# <23>

Pull high @ VGA side

R443

1

GND

2

4

+3V_PCH

1

C468

C468 10P_0402_50V8J

10P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-8971P

E

15 58Wednesday, February 15, 2012

0.1

A

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5>

+1.05VS_VTT

DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+3VS

PCH_PWROK

PM_DRAM_PWRGD<6>

EC_RSMRST#

SUSWARN#

PBTN_OUT#

ACIN

1 1

+3V_PCH

R34 10K_0402_5%R34 10K_0402_5%

1 2

R49 10K_0402_5%R49 10K_0402_5%

1 2

R390 10K_0402_5%

1 2

R393 300_0402_5%R393 300_0402_5%

R394 10K_0402_5%R394 10K_0402_5%

2 2

+3V_PCH

200K_0402_5%

AC_PRESENT<42>

3 3

1 2

Follow G

12

not support AMT APWROK can mux with PWROK (check list1.5 P.47)

R26

1 2

R263

PCH_ACIN

@R263

@

1 2

0_0402_5%

SUSWARN#_R

PCH_GPIO72

RI#

PM_DRAM_PWRGD

PCH_RSMRST#

SUSACK#<42>

EC_RSMRST#<42>

SUSWARN#<42>

PBTN_OUT#<42>

ACIN<23,42,50>

No use ,PH 10K +3VALW

Ring Indicator CRB1.0 PH 10K +3VALW

B

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

L=500mil S=15mil

1 2

4mil width and place within 500mil of the PCH

R270 0_0402_5%

R271 0_0402_5%

DMI_IRCOMP

R15649.9_0402_1% R15649.9_0402_1%

DMI2RBIAS

R155750_0402_1% R155750_0402_1%

SUSACK#_R

DSP3@

1 2

SYS_RST#

R415

1 2

10K_0402_5%

PCH_PWROK_R

R107

1 2

0_0402_5%

PM_DRAM_PWRGD

PCH_RSMRST#

R125

1 2

0_0402_5%

SUSWARN#_R

DSP3@

1 2

PBTN_OUT#_R

R129

1 2

0_0402_5%

1 2

D3 RB751V-40_SOD323-2D3 RB751V-40_SOD323-2

PCH_ACIN

PCH_GPIO72

RI#

U13C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

COUGARPOINT_FCBGA989

C

FDI_CTX_PRX_N0

BJ14

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROKSUSACK#

PCH_PCIE_WAKE#

CLKRUN#SYS_PWROK

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

@

R153 100K_0402_5%

1 2

0_0402_5%

R423

8.2K_0402_5%

PCH_RSMRST#

R133

PCH_PCIE_WAKE# <33,40>

12

+3VS

@

T1

T1 PAD

PAD

SUSCLK <42>

PM_SLP_S5# <42>

PM_SLP_S4# <42>

PM_SLP_S3# <42>

@

T4

T4 PAD

PAD

SLP_SUS# <42>

H_PM_SYNC <6>

No use ,PH 10K +3VALW

D

Can be left NC when IAMT is not support on the platfrom

E

DSWODVREN

DSWODVREN - On Die DSW VR Enable

HEnable internal DSW +1.05VS

*

LDisable

R359 330K_0402_5%

R368 330K_0402_5%@R368 330K_0402_5%@

1 2

12

Must always PH at +RTCVCC

PCH_PCIE_WAKE#

PCH_GPIO29

10K_0402_5%

@ R36

@

10K_0402_5%

+RTCVCC

+3V_PCH

R374

12

R36

12

tell PCH all power ok but cpu core

PCH_PWROK<42>

10K_0402_5%

4 4

VGATE<56>

PCH_PWROK

12

R104

VGATE

A

+3VS

U36

5

MC74VHC1G08DFT2G_SC70-5

2

P

B

Y

1

A

G

3

ALL power OK

SYS_PWROK

4

12

R119

R119 100K_0402_5%

100K_0402_5%

B

1

@

C52

0.047U_0402_16V7K

2

SYS_PWROK <6>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM

LA-8971P

E

16 58Wednesday, February 15, 2012

0.1

A

+3VS

R108 2.2K_0402_5%R108 2.2K_0402_5%

1 2

R105 2.2K_0402_5%R105 2.2K_0402_5%

1 2

1 1

2 2

+3VS

3 3

R195 2.2K_0402_5%R195 2.2K_0402_5%

1 2

R196 2.2K_0402_5%R196 2.2K_0402_5%

1 2

12

PCH_CRT_B

PCH_CRT_G

PCH_CRT_R

R192

150_0402_1%

R193

150_0402_1%

R194

150_0402_1%

R190 2.2K_0402_5%R190 2.2K_0402_5%

1 2

R191 2.2K_0402_5%R191 2.2K_0402_5%

1 2

EDID_CLK

EDID_DATA

CTRL_CLK

CTRL_DATA PCH_HDMIDAT

PCH_CRT_CLK

PCH_CRT_DATA

B

PCH_ENBKL<35> PCH_ENVDD<35>

PCH_PWM<35>

EDID_CLK<35> EDID_DATA<35>

R132

2.37K_0402_1%

LVDS_ACLK#<35> LVDS_ACLK<35>

LVDS_A0#<35> LVDS_A1#<35> LVDS_A2#<35>

LVDS_A0<35> LVDS_A1<35> LVDS_A2<35>

LVDS_BCLK#<35> LVDS_BCLK<35>

LVDS_B0#<35> LVDS_B1#<35> LVDS_B2#<35>

LVDS_B0<35> LVDS_B1<35> LVDS_B2<35>

PCH_CRT_B<36> PCH_CRT_G<36> PCH_CRT_R<36>

PCH_CRT_CLK<36>

PCH_CRT_DATA<36>

PCH_CRT_HSYNC<36> PCH_CRT_VSYNC<36>

PCH_ENBKL PCH_ENVDD

PCH_PWM

EDID_CLK EDID_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

12

LVDS_ACLK# LVDS_ACLK

LVDS_A0# LVDS_A1# LVDS_A2#

LVDS_A0 LVDS_A1 LVDS_A2

LVDS_BCLK# LVDS_BCLK

LVDS_B0# LVDS_B1# LVDS_B2#

LVDS_B0 LVDS_B1 LVDS_B2

PCH_CRT_B PCH_CRT_G PCH_CRT_R

PCH_CRT_CLK PCH_CRT_DATA

PCH_CRT_HSYNC PCH_CRT_VSYNC

R114

1K_0402_0.5%

12

CRT_IREF

M45

P45

K47

P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48

AM47

AK47

AJ48

AN47 AM49

AK49

AJ47

AF40 AF39

AH45 AH47

AF49 AF45

AH43 AH49

AF47 AF43

N48 P49

M40

M47 M49

J47

T40

T45

T49

T39

T43 T42

C

U13D

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK L_DDC_DATA

L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

COUGARPOINT_FCBGA989

LVDS

CRT

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

PCH_HDMICLK

P38 M39

AT49 AT47

TMDS_B_HPD#

AT40

TMDS_B_DATA2#_PCH

AV42

TMDS_B_DATA2_PCH

AV40

TMDS_B_DATA1#_PCH

AV45

TMDS_B_DATA1_PCH

AV46

TMDS_B_DATA0#_PCH

AU48

TMDS_B_DATA0_PCH

AU47

TMDS_B_CLK#_PCH

AV47

TMDS_B_CLK_PCH

AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

HDMI@

R144

2.2K_0402_5%

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

D

+3VS

12

HDMI@

R131

2.2K_0402_5%

PCH_HDMICLK <37> PCH_HDMIDAT <37>

TMDS_B_HPD# <37>

C406 0.1U_0402_10V6KHDMI@ C406 0.1U_0402_10V6KHDMI@

1 2

C352 0.1U_0402_10V6KHDMI@ C352 0.1U_0402_10V6KHDMI@

1 2

C539 0.1U_0402_10V6KHDMI@ C539 0.1U_0402_10V6KHDMI@

1 2

C538 0.1U_0402_10V6KHDMI@ C538 0.1U_0402_10V6KHDMI@

1 2

C535 0.1U_0402_10V6KHDMI@ C535 0.1U_0402_10V6KHDMI@

1 2

C534 0.1U_0402_10V6KHDMI@ C534 0.1U_0402_10V6KHDMI@

1 2

C537 0.1U_0402_10V6KHDMI@ C537 0.1U_0402_10V6KHDMI@

1 2

C536 0.1U_0402_10V6KHDMI@ C536 0.1U_0402_10V6KHDMI@

1 2

HDMI_TX2-_CK <37> HDMI_TX2+_CK <37> HDMI_TX1-_CK <37> HDMI_TX1+_CK <37> HDMI_TX0-_CK <37> HDMI_TX0+_CK <37> HDMI_CLK-_CK <37> HDMI_CLK+_CK <37>

E

HDMI D2

HDMI D1

HDMI

HDMI D0

HDMI CLK

Place close to Connector side(0210)

4 4

Security Classification

2011/06/24 2012/07/12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

LA-8971P

17 58Wednesday, February 15, 2012

E

0.1

A

+3VS

1 1

+3VS

2 2

GNT1#/ GPIO51

Internal PH

1K_0402_5%

3 3

PCH_PLTRST#

4 4

DGPU_HOLD_RST#

R90

18 27 36 45

8.2K_1206_8P4R_5%

R409

18 27 36 45

8.2K_1206_8P4R_5%

R395

18 27 36 45

8.2K_1206_8P4R_5%

R401

1 2

8.2K_0402_5%

R410

1 2

8.2K_0402_5%

R66

1 2

8.2K_0402_5%

R41

@ R41

@

12

8.2K_0402_5%

Boot BIOS Strap

GPIO51GPIO19

Bit11

Bit10

0 1

1

0

1 1

00

@

DGPU_PWR_EN2NVDD_PWR_EN

R218

12

0_0402_5%

@

PCH_WL_OFF#

R25

12

OPT@

U29

MC74VHC1G08DFT2G_SC70-5

U29

PCI_PIRQC# PCI_PIRQB# PCI_PIRQA# PCI_PIRQD#

PCH_WL_OFF# PCH_GPIO53 PCH_GPIO4 PCH_GPIO5

PCH_GPIO51 PCH_GPIO2 PCH_ODD_DA#

DGPU_PWR_EN2

DGPU_PWR_EN1

Boot BIOS Destination

Reserved

PCI

SPI

LPC

R10

0_0402_5%

+3VS

5

2

P

B

1

A

G

3

+3VS

5

2

P

B

1

A

G

3

A

DGPU_HOLD_RST#

*

NVDD_PWR_EN<55> DGPU_PWR_EN<15,30,55>

CLK_PCI_LPBACK<15>

CLK_PCI_EC<42>

CLK_PCI_DB<40>

12

4

Y

U25

@U25

@

MC74VHC1G08DFT2G_SC70-5

R6

1 2

4

Y

100_0402_5%

12

OPT@

R3

R3 100K_0402_5%

100K_0402_5%

PCI Interrupt Requests

CLK_PCI_LPBACK CLK_PCI_EC CLK_PCI_DB

10K_0402_5%

0.1U_0402_16V4Z

12

R11

100K_0402_5%

OPT@R6

OPT@

USB3.0

R56 0_0402_5%OPT@R56 0_0402_5%OPT@ R57 0_0402_5%OPT@R57 0_0402_5%OPT@

12

@

R307

@

1

C149

2

PLT_RST# <33,40,42>

DGPU_RST# <23>

PCH_ODD_DA#<39>

B

USB3_RX1_N<45>

USB3_RX1_P<45>

USB3_TX1_N<45>

USB3_TX1_P<45>

DGPU_HOLD_RST#

B

DGPU_PWR_EN1 DGPU_PWR_EN2

12 12

PCH_WL_OFF#<40>

PCI_PME#<42>

PCH_PLTRST#<6>

R417 22_0402_5%

1 2

R84 22_0402_5%

1 2

R162 22_0402_5%@R162 22_0402_5%@

1 2

USB3_RX1_N

USB3_RX1_P

USB3_TX1_N

USB3_TX1_P

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

PCH_GPIO2 PCH_ODD_DA# PCH_GPIO4 PCH_GPIO5

PCI_PME#

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_PCI2

U13E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

COUGARPOINT_FCBGA989

C

AY7

NV_CE#0

AV7

NV_CE#1

AU3

NV_CE#2

BG4

NV_CE#3

AT10

NV_DQS0

BC8

NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

USBRBIAS#

USBRBIAS

C

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5

DF_TVS

AY1

AV10

AT8

AY5 BA2

AT12 BF3

USB20_N0

C24

USB20_P0

A24

USB20_N1

C25

USB20_P1

B25 C26 A26

USB20_N3

K28

USB20_P3

H28 E28 D28 C28 A28 C29

HM70 not support USB port 4,5,6,7,12,13

B29 N28 M28

USB20_N8

L30

USB20_P8

K30

USB20_N9

G30

USB20_P9

E30

USB20_N10

C30

USB20_P10

A30

USB20_N11

L32

USB20_P11

K32 G32 E32 C32 A32

USBRBIAS

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

USB20_N0 <45> USB20_P0 <45> USB20_N1 <46> USB20_P1 <46>

USB20_N3 <46> USB20_P3 <46>

USB20_N8 <35> USB20_P8 <35> USB20_N9 <43> USB20_P9 <43> USB20_N10 <40> USB20_P10 <40> USB20_N11 <46> USB20_P11 <46>

R399

1 2

22.6_0402_1%

USB_OC0# <45,46> USB_OC1# <46>

Compal Secret Data

2011/06/24 2012/07/12

Compal Secret Data

USB3 (Left side)

USB2 (Right side)

CMOS Camera (LVDS)

Bluetooth

Mini Card (WLAN)

Card Reader

L=500mil S=15mil

Deciphered Date

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

RSVD

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

PCI

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

E

DMI,FDI Termination Voltage

DF_TVS

Set to Vcc when HIGH

Set to Vss when LOW

HR CPU NC

CR CPU PD

CR Check list P.89 PH 2.2K series 1K

+1.8VS

12

R145

2.2K_0402_5%

DF_TVS

R146

1K_0402_5%

12

H_SNB_IVB# <6>

CLOSE TO THE BRANCHING POINT

EHCI 1

EHCI 2

+3V_PCH

USB_OC0#

USB_OC7#

USB_OC5#

USB_OC6#

USB_OC1# USB_OC4# USB_OC3# USB_OC2#

Title

PCH (5/9) PCI, USB, NVRAM

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

R24

12

10K_0402_5%

R367

12

10K_0402_5%

R378

12

10K_0402_5%

R377

12

10K_0402_5%

+3V_PCH

RP3

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

Compal Electronics, Inc.

LA-8971P

E

0.1

18 58Wednesday, February 15, 2012

0.1