Compal LA-8952P VIUS3, IdeaPad S300, IdeaPad S400, LA-8952P VIUS4 Schematic

A

B

C

D

E

Compal Confidential

Model Name : VIUS3/S4

le Name : LA-8952PR01

1 1

Fi BOM P/N:43

Compal Confidential

2 2

VIUS3/S4 M/B Schematics Document

Intel Ivy Bridge ULV Processor + Panther Point PCH

AMD Seymour XT

3 3

2013-01-07

REV:0.1

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-8952P

0.1

1 55Thursday, January 10, 2013

E

1 55Thursday, January 10, 2013

0.1

A

Compal confidential

File Name :VIUS3/VIUS4

B

C

D

E

Chief River

AMD Seymour XT

1 1

23mm *23mm

VRAM 128MB*16

gDDR3*4

PCI-E X16

Gen 2

UP TO 1G

IVY Bridge SV/ULV

Intel

(Sandy Bridge)

Processor

BGA1023

R3-SO-DIMM X1

DD

BANK 0, 1

Dua

l Channel

DDR3-1066/1333(1.5V) for Sandy Bridge DDR3-1600(1.5V) for Ivy Bridge

SATA3.0 HDD CONN

FDI *8

Std HDMI

HDMI 1.4a

100MHz

2.7GT/s

Connector

2 2

LVDS Connector

PCI Express (Half) Mini card Slot 1

WLAN/WiMAX

PCI Express (Full) Mi

ni card Slot 2

SSD

PX 5.0

USB(WiMAX)

PCI-E(WLAN)

mSATA(SSD)

Gen 2

6*PCI-E x1

SPI ROM

Intel Pan

ther Point

HM77/HM70

FCBGA 989 Balls

25mm*25mm

LPC BUS

BIOS

3 3

LA

WLAN/WiMAX

N(10/100/Giga)

Realtek 81

05E-VD (10/100)

8111F-VL (Giga)

4MB*1 2MB*1

EC

ENE KB9012

Touch Pad

RJ45 CONN

Su

b-borad

4 4

POWER BOARD

ermal Sensor

Th

EMC1403

DMI2 *4

100MHz 5GT/s

6*SATA

(port0,1 Support SATA3)

4*USB3.0

14*USB2.0

HD Audio

Int.KBD

SATA3.0 HDD (SSD)

USB PORT 3.0 x1 (Left)

US

B PORT 2.0 x2 (Right)

Card Reader RTS 5178 (2in1)

CMO

S Camera

BlueTooth CONN

WLAN/WiMAX

WWAN Touch Screen

Audio Codec

RealTek

C259-VC2

AL

Board

IO

IO Board

2Channel Speaker

Single Digital MIC

Audio Combo Jack (APPLE type)

HeadPhone Output Microphone Input

Board

IO

LED BOARD

oard

IO B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/07/21 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

MB Block Diagram

2 55Thursday, January 10, 2013

E

0.1

A

Voltage Rails

power

State

S0

S3

S5 S4/AC

Device

Smart Battery

plane

Address

0001 011X b

+B

O

X

+5VALW

+3VALW

O

X

X X X

+1.5V

+1.5V_IO

EC SM Bus2 address

Device

Thermal Sen sor F75303M

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

EC SM Bus1 address

PCH SM Bus address

Device Address

DDR DIMM0

3 3

DDR DIMM2

1001 000Xb

1001 010Xb

AMD-GPU SM Bus address

Device Address

Internal thermal sensor

1001 111Xb (0x9E)

SMBUS Control Table

X

X X

V

+3VS

SODIMM

X X

V

+3VS

X

SOURCE

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2

4 4

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

VGA BATT KB9012

X V

+3VALW

X X X

V

+3VS

A

X X X

B

+5VS

+3VS

+1.5VS

+1.05VS_VTT

+CPU_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

O

X X

X

Address

1001_101xb

X XX

V

+3VS

Thermal Sensor

X X X

WLAN WWAN

XX

X

V

+3VS

B

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

D

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

E

ONONON ON

ON

OFF

ON

OFF

LOW

OFF

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0

PCB Revision

0.1

1 2 3 4

OO

5 6 7

X

USB Port Table

X

USB 3.0

xHCI1 xHCI2 xHCI3 xHCI4

HM70 Disable xHCI3,xHCI4

USB 2.0 Port

UHCI0

UHCI1

EHCI1

UHCI2

UHCI3

UHCI4

EHCI2

UHCI5

UHCI6

SATA Port Table

SATA P0 SATA P1

PCH

X

V

+3VS

SATA P2 SATA P3 SATA P4 SATA P5

HM70 Disable P1,P3

X

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

3 External USB Port

0 1 2 3 4 5 6 7 8

9 10 11 12 13

USB 3.0 Port (Left Side) Mini Card(WLAN) Touch Panel

X (USB PORT disabled on HM70 )

USB/B (Right Side USB-BD)

USB Port (Right Side CR-BD)

Camera (LVDS)

X (USB PORT disabled on HM70 )

HM77

GEN3/2/1

GEN2/1

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V

1.935 V

2.500 V

12/12/24

HM70

GEN3/2/1

DisableGEN3/2/1

GEN2/1

Disable

GEN2/1

SSD

HDD (HM77)

HDD (HM70)

V typ

AD_BID

V

AD_BID

max

0 V 0 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.759 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

INTEL UMA only UMA@

PX@ GPU:Seymour XT

HDMI HDMI@ HDD1 (HM77 SATA 3.0) HDD1@ HDD2 (HM70 SATA 2.0) HDD2@ Intel-USB3.0 USB3@

PCH HM77@ PCH HM70@

HM77@

HM70@

10/100 LAN 8105@ GIGA LAN 8111@ AOAC CMOS Deep S3 mSATA SSD

AOAC@

CMOS@

DS3@

mSATA@

Connector ME@ 45 LEVEL 45@ Unpop

@

PCIe Port Table

HM77

PCIe P1 PCIe P2 PCIe P3 PCIe P4 PCIe P5 PCIe P6 PCIe P7 PCIe P8

Enable

HM70 Disable P5,P6,P7,P8

HM70

Enable

Disable

able

Dis

Disable

Porject Phase

G-series

Y-series

LAN

WLAN

MP PVT DVT EVT EVT DVT PVT MP

X

Security Classification

Issued Date

XX X

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-8952P

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

3 55Thursday, January 10, 2013

E

0.1

5

4

3

2

1

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up

D D

sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

VDDR3(3.3VGS)

VDDC.

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)

VDDR1(1.5VGS)

C C

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

Without BACO option :

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

BACO option :

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode) PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

dGPU Power Pins Max current

DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10

PCIE_VDDC

VDDR3 , and A2VDD

BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode) BIF_VDDC=VGA_CORE When GPU enable BIF_VDDC=1.0V When BACO

VDDR1

VDDC/VDDCI

iGPU

PXS_RST#

dGPU

Voltage

1.8V

1.0V

3.3V

Same as VDDC

1.5V

1.12V

PX 3.0

OFF

BACO Mode

ON

ON Same as PCIE_VDDC

OFF

1679mAPCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,

575mA

2A

190mA

70mA

2.8A

12.9A

PERSTb

PXS_PWREN

REFCLK

Straps Reset

+3.3VALW

Straps Valid

B B

Global ASIC Reset

T4+16clock

+1.0V

+1.8V

MOS

Regulator

SI4800

+3.3VGS

1

+1.0VGS

2

+1.8VGS

5

part

CPU

UCPU1

CPU1@

UCPU1

CPU1@

UCPU1

I3_3217 1.8G

SA00005L5D0

UCPU1

CPU7@

UCPU1

CPU7@

I5_2467M 1.6G

SA00004X000

A A

I5_3427 1.8G

SA00005L950

UCPU1

I3_2367M 1.4G

SA000051H70

5

CPU2@

CPU8@

UCPU1

I5_2557 1.4G

SA00004VZ50

UCPU1

I3_2357M 1.3G

SA00004QZ20

CPU3@

CPU9@

UCPU1

977_1.4G

SA00005BJ40

UCPU1

967_1.3G

SA000051J20

UCPU1

CPU4@

CPU10@

UCPU1

SA00005K6E0

UCPU1

SA00004AY20

PCH part

U13

HM70@

U13

HM70@

PCH_HM70

SA00005MQ80

CPU5@

I5_3317U 1.7G

CPU11@

957_1.2G

4

UCPU1

I5_2537 1.4G

SA00004H910

UCPU1

I7-3667U 2G

SA00005LAD0

CPU6@

CPU12@

UCPU1

CPU13@

UCPU1

CPU13@

987 1.4G

SA00005QH30

UCPU1

CPU14@

UCPU1

CPU14@

I3-2377M 1.5G

SA00005MX80

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

UCPU1

CPU15@

UCPU1

CPU15@

I7-3517U

SA00005K5C0

UCPU1

CPU16@

UCPU1

CPU16@

I3-2365M

SA00005UH10

2011/06/15 2012/07/11

3

PCB part

ZZZ5

PCB 0R LA-8951P REV0 M/B

DAZ0S900100

Compal Secret Data

Deciphered Date

2

ZZZ2

Hynix

S512@

X7641338L01

ZZZ1

Hynix

H512@

X7641338L02

ZZZ3

Hynix

S1G@

X7641338L03

Title

Size Document Number Rev

Custom

Date: Sheet of

ZZZ4

Hynix

H1G@

X7641338L04

Compal Electronics, Inc.

VGA Notes List

LA-8952P

4 55Thursday, January 10, 2013

1

0.1

A

1 1

2 2

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms can't be left floating ,even if disable eDP function...

3 3

+1.05VS_ VTT

12

R247

24.9_040 2_1%

B

DMI_CRX_P TX_N0<15> DMI_CRX_P TX_N1<15> DMI_CRX_P TX_N2<15> DMI_CRX_P TX_N3<15>

DMI_CRX_P TX_P0<15> DMI_CRX_P TX_P1<15> DMI_CRX_P TX_P2<15> DMI_CRX_P TX_P3<15>

DMI_CTX_P RX_N0<15> DMI_CTX_P RX_N1<15> DMI_CTX_P RX_N2<15> DMI_CTX_P RX_N3<15>

DMI_CTX_P RX_P0<15> DMI_CTX_P RX_P1<15> DMI_CTX_P RX_P2<15> DMI_CTX_P RX_P3<15>

FDI_CTX_P RX_N0<15> FDI_CTX_P RX_N1<15> FDI_CTX_P RX_N2<15> FDI_CTX_P RX_N3<15> FDI_CTX_P RX_N4<15> FDI_CTX_P RX_N5<15> FDI_CTX_P RX_N6<15> FDI_CTX_P RX_N7<15>

FDI_CTX_P RX_P0<15> FDI_CTX_P RX_P1<15> FDI_CTX_P RX_P2<15> FDI_CTX_P RX_P3<15> FDI_CTX_P RX_P4<15> FDI_CTX_P RX_P5<15> FDI_CTX_P RX_P6<15> FDI_CTX_P RX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

FDI_INT<15>

FDI_LSYNC0<15> FDI_LSYNC1<15>

W=12mil L=500mil S=15mil

EDP_COM P

UCPU1A

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1 023

@

C

W=12mil L=500mil S=15mil

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

G3 G1 G4

H22

PEG_GTX _C_HRX_N0

J21

PEG_GTX _C_HRX_N1

B22

PEG_GTX _C_HRX_N2

D21

PEG_GTX _C_HRX_N3

A19

PEG_GTX _C_HRX_N4

D17

PEG_GTX _C_HRX_N5

B14

PEG_GTX _C_HRX_N6

D13

PEG_GTX _C_HRX_N7

A11

PEG_GTX _C_HRX_N8

B10

PEG_GTX _C_HRX_N9

G8

PEG_GTX _C_HRX_N10

A8

PEG_GTX _C_HRX_N11

B6

PEG_GTX _C_HRX_N12

H8

PEG_GTX _C_HRX_N13

E5

PEG_GTX _C_HRX_N14

K7

PEG_GTX _C_HRX_N15

K22

PEG_GTX _C_HRX_P0

K19

PEG_GTX _C_HRX_P1

C21

PEG_GTX _C_HRX_P2

D19

PEG_GTX _C_HRX_P3

C19

PEG_GTX _C_HRX_P4

D16

PEG_GTX _C_HRX_P5

C13

PEG_GTX _C_HRX_P6

D12

PEG_GTX _C_HRX_P7

C11

PEG_GTX _C_HRX_P8

C9

PEG_GTX _C_HRX_P9

F8

PEG_GTX _C_HRX_P10

C8

PEG_GTX _C_HRX_P11

C5

PEG_GTX _C_HRX_P12

H6

PEG_GTX _C_HRX_P13

F6

PEG_GTX _C_HRX_P14

K6

PEG_GTX _C_HRX_P15

G22

PEG_HTX _GRX_N0

C23

PEG_HTX _GRX_N1

D23

PEG_HTX _GRX_N2

F21

PEG_HTX _GRX_N3

H19

PEG_HTX _GRX_N4

C17

PEG_HTX _GRX_N5

K15

PEG_HTX _GRX_N6

F17

PEG_HTX _GRX_N7

F14

PEG_HTX _GRX_N8

A15

PEG_HTX _GRX_N9

J14

PEG_HTX _GRX_N10

H13

PEG_HTX _GRX_N11

M10

PEG_HTX _GRX_N12

F10

PEG_HTX _GRX_N13

D9

PEG_HTX _GRX_N14

J4

PEG_HTX _GRX_N15

F22

PEG_HTX _GRX_P0

A23

PEG_HTX _GRX_P1

D24

PEG_HTX _GRX_P2

E21

PEG_HTX _GRX_P3

G19

PEG_HTX _GRX_P4

B18

PEG_HTX _GRX_P5

K17

PEG_HTX _GRX_P6

G17

PEG_HTX _GRX_P7

E14

PEG_HTX _GRX_P8

C15

PEG_HTX _GRX_P9

K13

PEG_HTX _GRX_P10

G13

PEG_HTX _GRX_P11

K10

PEG_HTX _GRX_P12

G10

PEG_HTX _GRX_P13

D8

PEG_HTX _GRX_P14

K4

PEG_HTX _GRX_P15

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

eDP

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_COM P

+1.05VS_ VTT

12

R249

24.9_040 2_1%

Layout placement: Place close to U8 (GPU)

1 2

C259 0.1U_040 2_6.3V6KPX@C259 0.1U_040 2_6.3V6KPX@

1 2

C276 0.1U_040 2_6.3V6KPX@C276 0.1U_040 2_6.3V6KPX@

1 2

C257 0.1U_040 2_6.3V6KPX@C257 0.1U_040 2_6.3V6KPX@

1 2

C274 0.1U_040 2_6.3V6KPX@C274 0.1U_040 2_6.3V6KPX@

1 2

C254 0.1U_040 2_6.3V6KPX@C254 0.1U_040 2_6.3V6KPX@

1 2

C272 0.1U_040 2_6.3V6KPX@C272 0.1U_040 2_6.3V6KPX@

1 2

C252 0.1U_040 2_6.3V6KPX@C252 0.1U_040 2_6.3V6KPX@

1 2

C270 0.1U_040 2_6.3V6KPX@C270 0.1U_040 2_6.3V6KPX@

1 2

C250 0.1U_040 2_6.3V6KPX@C250 0.1U_040 2_6.3V6KPX@

1 2

C268 0.1U_040 2_6.3V6KPX@C268 0.1U_040 2_6.3V6KPX@

1 2

C248 0.1U_040 2_6.3V6KPX@C248 0.1U_040 2_6.3V6KPX@

1 2

C267 0.1U_040 2_6.3V6KPX@C267 0.1U_040 2_6.3V6KPX@

1 2

C246 0.1U_040 2_6.3V6KPX@C246 0.1U_040 2_6.3V6KPX@

1 2

C264 0.1U_040 2_6.3V6KPX@C264 0.1U_040 2_6.3V6KPX@

1 2

C244 0.1U_040 2_6.3V6KPX@C244 0.1U_040 2_6.3V6KPX@

1 2

C262 0.1U_040 2_6.3V6KPX@C262 0.1U_040 2_6.3V6KPX@

1 2

C258 0.1U_040 2_6.3V6KPX@C258 0.1U_040 2_6.3V6KPX@

1 2

C277 0.1U_040 2_6.3V6KPX@C277 0.1U_040 2_6.3V6KPX@

1 2

C256 0.1U_040 2_6.3V6KPX@C256 0.1U_040 2_6.3V6KPX@

1 2

C275 0.1U_040 2_6.3V6KPX@C275 0.1U_040 2_6.3V6KPX@

1 2

C255 0.1U_040 2_6.3V6KPX@C255 0.1U_040 2_6.3V6KPX@

1 2

C273 0.1U_040 2_6.3V6KPX@C273 0.1U_040 2_6.3V6KPX@

1 2

C253 0.1U_040 2_6.3V6KPX@C253 0.1U_040 2_6.3V6KPX@

1 2

C271 0.1U_040 2_6.3V6KPX@C271 0.1U_040 2_6.3V6KPX@

1 2

C251 0.1U_040 2_6.3V6KPX@C251 0.1U_040 2_6.3V6KPX@

1 2

C269 0.1U_040 2_6.3V6KPX@C269 0.1U_040 2_6.3V6KPX@

1 2

C249 0.1U_040 2_6.3V6KPX@C249 0.1U_040 2_6.3V6KPX@

1 2

C266 0.1U_040 2_6.3V6KPX@C266 0.1U_040 2_6.3V6KPX@

1 2

C247 0.1U_040 2_6.3V6KPX@C247 0.1U_040 2_6.3V6KPX@

1 2

C265 0.1U_040 2_6.3V6KPX@C265 0.1U_040 2_6.3V6KPX@

1 2

C245 0.1U_040 2_6.3V6KPX@C245 0.1U_040 2_6.3V6KPX@

1 2

C263 0.1U_040 2_6.3V6KPX@C263 0.1U_040 2_6.3V6KPX@

1 2

C562 0.1U_040 2_6.3V6KPX@C562 0.1U_040 2_6.3V6KPX@

1 2

C582 0.1U_040 2_6.3V6KPX@C582 0.1U_040 2_6.3V6KPX@

1 2

C564 0.1U_040 2_6.3V6KPX@C564 0.1U_040 2_6.3V6KPX@

1 2

C584 0.1U_040 2_6.3V6KPX@C584 0.1U_040 2_6.3V6KPX@

1 2

C566 0.1U_040 2_6.3V6KPX@C566 0.1U_040 2_6.3V6KPX@

1 2

C587 0.1U_040 2_6.3V6KPX@C587 0.1U_040 2_6.3V6KPX@

1 2

C568 0.1U_040 2_6.3V6KPX@C568 0.1U_040 2_6.3V6KPX@

1 2

C589 0.1U_040 2_6.3V6KPX@C589 0.1U_040 2_6.3V6KPX@

1 2

C570 0.1U_040 2_6.3V6KPX@C570 0.1U_040 2_6.3V6KPX@

1 2

C591 0.1U_040 2_6.3V6KPX@C591 0.1U_040 2_6.3V6KPX@

1 2

C572 0.1U_040 2_6.3V6KPX@C572 0.1U_040 2_6.3V6KPX@

1 2

C593 0.1U_040 2_6.3V6KPX@C593 0.1U_040 2_6.3V6KPX@

1 2

C574 0.1U_040 2_6.3V6KPX@C574 0.1U_040 2_6.3V6KPX@

1 2

C594 0.1U_040 2_6.3V6KPX@C594 0.1U_040 2_6.3V6KPX@

1 2

C576 0.1U_040 2_6.3V6KPX@C576 0.1U_040 2_6.3V6KPX@

1 2

C597 0.1U_040 2_6.3V6KPX@C597 0.1U_040 2_6.3V6KPX@

1 2

C561 0.1U_040 2_6.3V6KPX@C561 0.1U_040 2_6.3V6KPX@

1 2

C583 0.1U_040 2_6.3V6KPX@C583 0.1U_040 2_6.3V6KPX@

1 2

C563 0.1U_040 2_6.3V6KPX@C563 0.1U_040 2_6.3V6KPX@

1 2

C585 0.1U_040 2_6.3V6KPX@C585 0.1U_040 2_6.3V6KPX@

1 2

C565 0.1U_040 2_6.3V6KPX@C565 0.1U_040 2_6.3V6KPX@

1 2

C586 0.1U_040 2_6.3V6KPX@C586 0.1U_040 2_6.3V6KPX@

1 2

C567 0.1U_040 2_6.3V6KPX@C567 0.1U_040 2_6.3V6KPX@

1 2

C588 0.1U_040 2_6.3V6KPX@C588 0.1U_040 2_6.3V6KPX@

1 2

C569 0.1U_040 2_6.3V6KPX@C569 0.1U_040 2_6.3V6KPX@

1 2

C590 0.1U_040 2_6.3V6KPX@C590 0.1U_040 2_6.3V6KPX@

1 2

C571 0.1U_040 2_6.3V6KPX@C571 0.1U_040 2_6.3V6KPX@

1 2

C592 0.1U_040 2_6.3V6KPX@C592 0.1U_040 2_6.3V6KPX@

1 2

C573 0.1U_040 2_6.3V6KPX@C573 0.1U_040 2_6.3V6KPX@

1 2

C595 0.1U_040 2_6.3V6KPX@C595 0.1U_040 2_6.3V6KPX@

1 2

C575 0.1U_040 2_6.3V6KPX@C575 0.1U_040 2_6.3V6KPX@

1 2

C596 0.1U_040 2_6.3V6KPX@C596 0.1U_040 2_6.3V6KPX@

D

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX _HRX_N0 PEG_GTX _HRX_N1 PEG_GTX _HRX_N2 PEG_GTX _HRX_N3 PEG_GTX _HRX_N4 PEG_GTX _HRX_N5 PEG_GTX _HRX_N6 PEG_GTX _HRX_N7 PEG_GTX _HRX_N8 PEG_GTX _HRX_N9 PEG_GTX _HRX_N10 PEG_GTX _HRX_N11 PEG_GTX _HRX_N12 PEG_GTX _HRX_N13 PEG_GTX _HRX_N14 PEG_GTX _HRX_N15

PEG_GTX _HRX_P0 PEG_GTX _HRX_P1 PEG_GTX _HRX_P2 PEG_GTX _HRX_P3 PEG_GTX _HRX_P4 PEG_GTX _HRX_P5 PEG_GTX _HRX_P6 PEG_GTX _HRX_P7 PEG_GTX _HRX_P8 PEG_GTX _HRX_P9 PEG_GTX _HRX_P10 PEG_GTX _HRX_P11 PEG_GTX _HRX_P12 PEG_GTX _HRX_P13 PEG_GTX _HRX_P14 PEG_GTX _HRX_P15

PEG_HTX _C_GRX_N0 PEG_HTX _C_GRX_N1 PEG_HTX _C_GRX_N2 PEG_HTX _C_GRX_N3 PEG_HTX _C_GRX_N4 PEG_HTX _C_GRX_N5 PEG_HTX _C_GRX_N6 PEG_HTX _C_GRX_N7 PEG_HTX _C_GRX_N8

PEG_HTX _C_GRX_N9 PEG_HTX _C_GRX_N10 PEG_HTX _C_GRX_N11 PEG_HTX _C_GRX_N12 PEG_HTX _C_GRX_N13 PEG_HTX _C_GRX_N14 PEG_HTX _C_GRX_N15

PEG_HTX _C_GRX_P0

PEG_HTX _C_GRX_P1

PEG_HTX _C_GRX_P2

PEG_HTX _C_GRX_P3

PEG_HTX _C_GRX_P4

PEG_HTX _C_GRX_P5

PEG_HTX _C_GRX_P6

PEG_HTX _C_GRX_P7

PEG_HTX _C_GRX_P8

PEG_HTX _C_GRX_P9 PEG_HTX _C_GRX_P10 PEG_HTX _C_GRX_P11 PEG_HTX _C_GRX_P12 PEG_HTX _C_GRX_P13 PEG_HTX _C_GRX_P14 PEG_HTX _C_GRX_P15

E

PEG_GTX _HRX_N[0..15] <22> PEG_GTX _HRX_P[0..15] < 22>

PEG_HTX _C_GRX_N[0..15] <22> PEG_HTX _C_GRX_P[0..15] <22>

4 4

Security Class ification

2011/06/ 24 2012/07/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/ 24 2012/07/ 12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

LA-8952P

5 55Thursday, January 10, 20 13

E

0.1

A

1 1

PCH->CPU UNCOREPWRGOOD: SM_DRAMPWROK:DRAM power ok RESET#:

都都都都ok後後後後後後後後

CPU

非非非非

CORE

做做做做

reset

外外外外外外外外外外外外

OK

Follow DG 1.5& Tacoma_Fall2 1.0

reserve XBOX

@

12

C614 0.1U_ 0402_16V4Z

R292 10K_0402 _5%

2 2

12

H_CPUPW RGD_R

OREPWRGOOD:

UNC

+1.05VS_VTT

H_PROCHOT#<37,42>

非非非非

CORE

SM_DRAMPWROK:DRAM power ok

B

PROC_SELECT# PH VCPLL and connect to PCH DF_TVS

H_SNB_IVB#<17>

偵偵偵偵偵偵偵偵

CPU

有有有有有有有有有有有有有有有有

三三三三三三三三三三三三三三三三

follow Checklist 1.5

R534 62_ 0402_5%

外外外外外外外外外外外外

OK

H_CPUPW RGD<18>

12

H_PECI<18,37>

R305 0_ 0402_5%@R305 0_0402_5%@

T33 PAD@T33 PAD@

R533

56_0402_5 %

1 2

H_THERMT RIP#<18>

H_PM_SYNC<15>

1 2

R237

1 2

130_0402_ 1%

H_CATERR#

H_PECI

H_PROCHOT# _RH_PROCHOT#

H_CPUPW RGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

UCPU1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1023

@

C

J3

BCLK

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

H2

AG3 AG1

AT30

BF44 BE43 BG43

N53 N55

L56

TCK

L55 J58

M60

TDI

L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

D

+1.05VS_VTT

CLK_CPU_D PLL#

CLK_CPU_D PLL

Checklist1.5 P.67 Graphis Disable Guide DIS only SKU eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

CLK_CPU_D PLL CLK_CPU_D PLL#

SM_RCOMP0,SM_RCOMP1 W=20mil L=500mil S=13mil

SM_RCOMP2 W=15mil L=500mil S=13mil

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

R517 1K_0402 _5%R517 1K_0402 _5%

R516 1K_0402 _5%R516 1K_0402 _5%

CLK_CPU_D MI <14> CLK_CPU_D MI# <14>

R272 140_0402_ 1%R272 140_0402_ 1% R273 25.5_0402_1 %R273 25.5_0402_1 % R267 200_0402_ 1%R267 200_0402_ 1%

12

12 12 12

100P_0402_ 50V8J

DDR3 Compensation Signals

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

XDP_DBRESET#

T97T97 T98T98

0301 Add test point

0419 ESD request to reserve

1

@

T49T49 C1278 T90T90 T91T91 T92T92 T93T93 T94T94 T95T95 T96T96

0301 Add test point

@

C1278

1000P_0402 _50V7K

2

1

C82

@ C82

@

2

ESD C

Reserve

PU/PD for JTAG signals

XDP_TMS XDP_TDI XDP_TDO

XDP_TCK XDP_TRST#

XDP_DBRESET#

Tacoma_Fall2 1.0 PH 1K +3VS Check list 1.5 PH 1K +3VS Debug port DG1.1-1.3 50~5K ohm

E

SM_DRAMRST# <7>

R20 51_0402_5 %R20 51_0402_5% R39 51_0402_5 %R39 51_0402_5% R37 51_0402_5 %R37 51_0402_5%

R40 51_0402_5 %R 40 51_0402_5% R28 51_0402_5 %R28 51_0402_5%

R312 1K_0402 _5%

12 12 12

12 12

12

+1.05VS_VTT

+3VS

+3VALW

3 3

SYS_PWROK<15>

4 4

+3VS

R31

10K_0402_5 %

1 2

R35

10K_0402_5 %

1 2

PM_DRAM_PWRGD<15>

A

0.1U_0402_ 16V4Z

@

RUN_ON_CPU1.5VS3#<10>

C228

12

U22

5

1

P

B

O

2

A

G

74AHC1G09GW_TSSOP5

3

RUN_ON_CPU 1.5VS3#

4

PM_SYS_PWRGD_BUF

Q4

2N7002K_SOT 23-3

+1.5V_CPU_VDDQ

12

R238

R238 200_0402_ 5%

200_0402_ 5%

12

R38@

R38@ 39_0402_5 %

39_0402_5 %

13

D

2

G

S

@

B

C43

0.1U_0402_ 16V4Z

@

+1.05VS_VTT

R546

75_0402_5 %

R544

43_0402_5 %

1 2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Buffered reset to CPU

C617

0.1U_0402_ 16V4Z

12

BUFO_CPU_RST#BUF_CPU_RST#

SN74LVC1G07DCKR_SC70-5

+3VS

12

5

U45

1

P

NC

4

Y

2

PCH_PLTRST#

A

G

3

Compal Secret Data

2011/06/24 2012/07/12

Compal Secret Data

PCH_PLTRST# <17>

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-8952P

E

6 5 5Thursday, January 10, 20 13

0.1

A

UCPU1C

DDR_A_D[0..63]<12>

1 1

2 2

3 3

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AL6

AJ8 AL8 AL7

AJ6

UCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

B

AU36

SA_CK[0]

AV36

SA_CK#[0]

AY26

SA_CKE[0]

AT40

SA_CK[1]

AU40

SA_CK#[1]

BB26

SA_CKE[1]

BB40

SA_CS#[0]

BC41

SA_CS#[1]

AY40

SA_ODT[0]

BA41

SA_ODT[1]

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

DDR SYSTEM MEMORY A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

SA_CLK_DDR0 <12 > SA_CLK_DDR#0 <1 2> DDRA_CKE0_DIMMA <12>

SA_CLK_DDR1 <12 > SA_CLK_DDR#1 <1 2> DDRA_CKE1_DIMMA <12>

DDRA_CS0_DIMMA# <12> DDRA_CS1_DIMMA# <12>

SA_ODT0 <12> SA_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12>

C

UCPU1D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

D

SB_CK[0] SB_CK#[0] SB_CKE[0]

SB_CK[1] SB_CK#[1] SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

E

IVY-BRIDGE_BGA1023

@

Follow CRB1.0

R216

0_0402_5%

1 2

@

1 2

@

D

S

D

S

13

G

SB00000QO00

2

1

C190

0.047U_0402_16V7K

2

DIMM_DRAMRST#_RSM_DRAMRST#

Q16

Q16 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

CPU通通DIMM做reset

SM_DRAMRST#<6>

R217

4.99K_0402_1%

4 4

@

1 2

DRAMRST_CNTRL_PC H<14>

DRAMRST_CNTRL<10>

DRAMRST_CNTRL_EC<37>

For DS3

A

R62 0_0402_5%

R64 0_0402_5%@R64 0_0402_5%@

DRAMRST_CNTRL

1 2

+1.5V

12

R212

1K_0402_5%

1 2

R219 1K_0402_5%R219 1K_0402_5%

S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# HIGH Dimm not reset S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm reset

B

DIMM_DRAMRST# <12>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

IVY-BRIDGE_BGA1023

@

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

LA-8952P

E

0.1

7 55Thursday, January 10, 2013

0.1

A

B

C

D

E

CFG Straps for Processor

UCPU1E

T32 PAD @T32 PAD @

1 1

2 2

3 3

+CPU_CO RE

R302

49.9_040 2_1%

1 2

R91

R91 100_040 2_1%

100_040 2_1%

1 2

R306

49.9_040 2_1%

1 2

+VGFX_C ORE

R310

49.9_040 2_1%

1 2

R95

R95 100_040 2_1%

100_040 2_1%

1 2

R311

49.9_040 2_1%

1 2

@

VCC_VAL _SENSE

VSS_VAL _SENSE

VAXG_VA L_SENSE

VSSAXG_ VAL_SENSE

CFG0

CFG2

CFG4 CFG5 CFG6 CFG7

VCC_VAL _SENSE VSS_VAL _SENSE

VAXG_VA L_SENSE VSSAXG_ VAL_SENSE

T18 PAD @T18 PAD @

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1 023

@

BCLK_ITP#

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61

DC_TEST_C61

DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

BCLK_ITP

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61

These pins are for solder joint

BD61

reliability and non-critical to

BE61 BE59

function. For BGA only.

BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

eDP enable

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

CFG2

*

CFG6 CFG5

R543

1K_0402 _1%

11: (Default) 1x16 PCI Express

*

10: 2x8 PCI Express

12

R296

R296 1K_0402 _1%

1K_0402 _1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

12

R293

@ R293

@

1K_0402 _1%

UMA,Optimus eDP DISO eDP

1:Disable

0:Enable

12

R541

1K_0402 _1%

@

1K_0402 _1%

@

01: Reserved

00

: 1x8,2x4 PCI Express

CFG7

12

R297

R297 1K_0402 _1%@

1K_0402 _1%@

關關關關關關關關

啟啟啟啟啟啟啟啟

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion

Tacoma_Fall2 1.0 P.12

0: PEG Wait for BIOS for training

4 4

Security Class ification

2011/06/ 24 2012/07/ 12

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/ 24 2012/07/ 12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-8952P

E

0.1

8 55Thursday, January 10, 20 13

A

1 1

INTEL Recommend VCC 4*470UF,12*22uF(0805) and 35*2.2uF(0402) PD0.8 CAP at Power side

2 2

3 3

4 4

B

UCPU1F

ULV type

UCPU1F

DC 33A

+CPU_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023

@

C

POWER

CORE SUPPLY

8.5A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

VCCSENSE_R VSSSENSE_R

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

PEG IO AND DDR IO

RAILS

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

D

+1.05VS_VTT

For DDR

INTEL Recommend VCCIO 2*330UF,10*10uF(0603) and 26*1uF(0402) PD0.8 CAP at Power side

For PEG

+3VS

12

R521

10K_0402_5%

+1.05VS_VTT

VCCIO_SEL

10K_0402_5%

VCCIO_SEL

+1.05VS_VTT

1 2

C553

C553 1U_0402_6.3V6K

1U_0402_6.3V6K

Place the PU resistors close to VR

1 2

R282 0_0402_5%@R282 0_0402 _5%@ R289 0_0402_5%@R289 0_0402 _5%@

1 2

R513 10_0402_5%R513 10_040 2_5%

1 2

VCCIO_SENSE VSSIO_SENSE_L

12

R512

R512 10_0402_5%

10_0402_5%

Check list 1.5

R522

VCCIO_SENSE <47> VSSIO_SENSE_L <47>

VCCIO_SEL after Ivy bridge ES2 Voltage support

12

@

12

+1.05VS_VTT

BC22

R531

R531 130_0402_5%

130_0402_5%

1 2

R528 43_0402_1%

R528 43_0402_1% R527 0_0402_5%@R527 0_0402_5%@

1 2 1 2

R530 0_0402_5%@R530 0_0402_5%@

R79

1 2

100_0402_1%

@

*

1/NC : (Default) +1.05VS_VTT

0: +1.0VS_VTT

+1.05VS_VTT+ 1.05VS_VTT

+CPU_CORE

12

R281

R281 100_0402_1%

100_0402_1%

R288

R288 100_0402_1%

100_0402_1%

Place the PU

R529

re

75_0402_5%

VCCSENSE <50> VSSSENSE <50 >

Should change to connect form power cirucit & layout differential with VCCIO_SENSE.

E

sistors close to CPU

VR_SVID_ALRT# <50 > VR_SVID_CLK < 50> VR_SVID_DAT <50>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

LA-8952P

E

9 55Thursday, January 10, 2013

0.1

A

1 2

R65

+3VALW

12

RUN_ON_CPU1.5VS3#

13

D

S

@

R65

SUSP<40,45,46>

R78

100K_0402_5% @

12

100K_0402_5% @

Q6

2N7002K_SOT23-3

2

G

1 1

@

R81 0_0402_5%

SUSP#<37,40, 45,46,47,49>

R81 0_0402_5%

1 2

@

R82

0_0402_5% R82

0_0402_5%

CPU1.5V_S3_GATE<37,40>

INTEL Recommend VAXG 2*

470uF,6*22uF(0805) and 6*10uF(0603) 11*1U(0402) PD0.8

2 2

CR CheckList Rev1.5

INTEL Recommend VCCPLL

3 3

4 4

1*330uF,2*1uF(0402) PD0.8

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

B phase Cost down proposal

+1.8VS

+VCCSA

VCC_AXG_SENSE<50>

VSS_AXG_SENSE<50>

Place BOT OUT Conn

1

@

+

C242

C242 330U_D2_2V_Y

330U_D2_2V_Y

2

INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402)

+VGFX_CORE

@

Place TOP IN BGA

C309

1U_0402_6.3V6K

12

@

Place BOT OUT BGA

C577

10U_0603_6.3V6M

@

12

PD0.8

A

22U_0805_6.3V6M@C633

22U_0805_6.3V6M

@

0_0402_5%@

+VCCSA

12

+VGFX_CORE

12

R308

100_0402_5%

12

R309

100_0402_5%

C633

10U_0603_6.3V6M

12

C302

1U_0402_6.3V6K

12

@

C560

10U_0603_6.3V6M

12

B

2

C153

1

12

2

C301

C300

1U_0402_6.3V6K

12

@

C579

C555

10U_0603_6.3V6M

12

B

+1.5V

+VSB

12

R85

R85 82K_0402_5%

82K_0402_5%

RUN_ON_CPU1.5VS3

13

D

G

Q8

G

Q8 2N7002K_SOT23-3

2N7002K_SOT23-3

S

RUN_ON_CPU1.5VS3# <6>

DC 29A

1 2

R87

100_0402_1%

@

1.2A

C280

1U_0402_6.3V6K

C280

1U_0402_6.3V6K

C281

1U_0402_6.3V6K

C281

1U_0402_6.3V6K

1

2

6A

C308

1U_0402_6.3V6K

12

@

C559

10U_0603_6.3V6M

12

J1@

1 2

PAD-OPEN 4x4m

U11 AO4430L_SO8

8 7 6 5

UCPU1G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023

@

SB00000RV00

4

12

R77

R77 330K_0402_5%

330K_0402_5%

@

+1.5V_CPU_VDDQ

1 2 3

R175

R175 15K_0402_1%

15K_0402_1%

1 2

POWER

220_0402_5%

2N7002K_SOT23-3

12

C115

0.047U_0603_25V7K

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

QUIET RAILS

1.8V RAIL

VSS_SENSE_VDDQ

SENSE LINES

SA RAIL

VCCSA VID

lines

VCCSA VID

lines

R80

Q7

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

VDDQ_SENSE

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

C

12

13

D

S

AY43

BE7 BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

C

12

C116@

0.1U_0402_10V6K

2

G

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

5A

+1.5V_CPU_VDDQ

C

PU EDS1.3 P.93

CSA_VID0 Must PD

VC

D

M3 Support

SA_DIMM_VREFDQ

RUN_ON_CPU1.5VS3#

+1.5V_CPU_VDDQ

+V_SM_VREF_CNT should

ve 20 mil trace width

ha

0.1U_0402_16V4Z

12

R518

@R518

R519

1K_0402_1%

@R519

@

1K_0402_1%

@

Place TOP IN BGA

C351

C348

C328

C329

C321

1U_0402_6.3V6K

12

@

C328

1U_0402_6.3V6K

12

@

Place BOT OUT BGA

C340

C338

C337

10U_0603_6.3V6M

@

12

C317

C317 1U_0402_6.3V6K

1U_0402_6.3V6K

R248 0_0402_5%

0_0402_5%

+VCCSA_SENSE <48>

2011/06/24 2012/07/12

12

@ R248

@

H_VCCSA_VID0 H_VCCSA_VID1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

12

R113

R113 1K_0402_1%

1K_0402_1%

12

C117

12

R124

R124 1K_0402_1%

1K_0402_1%

C349

C312

1U_0402_6.3V6K

12

C296

10U_0603_6.3V6M

12

@

12

H_VCCSA_VID0 < 48> H_VCCSA_VID1 < 48>

C349

C318

1U_0402_6.3V6K

12

@

C295

10U_0603_6.3V6M

12

+1.5V_CPU_VDDQ +1.5V

C316

C320

1U_0402_6.3V6K

12

@

C298

C339

C299

Compal Secret Data

10U_0603_6.3V6M

12

C150 0.1U_0402_10V7KC150 0.1U_0402_10V7K

12

C151 0.1U_0402_10V7KC151 0.1U_0402_10V7K

12

C152 0.1U_0402_10V7KC152 0.1U_0402_10V7K

12

C157 0.1U_0402_10V7KC157 0.1U_0402_10V7K

Deciphered Date

D

R117 0_0402_5%@R117 0_0402_5%@

S

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

1

+

C286

C286 330U_D2_2V_Y

330U_D2_2V_Y

2

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

VID0

0

1 1

12

G

VID1

E

1 2

R86 0_0402_5%@R86 0_0402_5%@

D

S

D

S

13

BSS138_NL_SOT23-3

SB00000QO00

G

Q2204

2

DRAMRST_CNTRL_PCH

+1.5V

12

R76@

R76@ 1K_0402_1%

D

123

Q11

Q11 AO3414_SOT23-3

AO3414_SOT23-3

@

+V_SM_VREF+V_SM_VREF_CNT

SA_DIMM_VREFDQ SB_DIMM_VREFDQ Check list1.5 P18 M1 default M3 no stuff

12

1K_0402_1%

R116@

R116@ 1K_0402_1%

1K_0402_1%

INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.8

V

VCCSA

UL

Vout

HR CR

0.9V

0

1

0 X1

V V

0.85V

V

0.775V

0.75V

V

VX

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-8952P

Date: Sheet of

E

+VREF_DQ_DIMMA

DRAMRST_CNTRL <7>

0.1

10 55Thursday, January 10, 2013

0.1

A

UCPU1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

1 1

2 2

3 3

4 4

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]

AA13

VSS[14]

AA50

VSS[15]

AA51

VSS[16]

AA52

VSS[17]

AA53

VSS[18]

AA55

VSS[19]

AA56

VSS[20]

AA8

VSS[21]

AB16

VSS[22]

AB18

VSS[23]

AB21

VSS[24]

AB48

VSS[25]

AB61

VSS[26]

AC10

VSS[27]

AC14

VSS[28]

AC46

VSS[29]

AC6

VSS[30]

AD17

VSS[31]

AD20

VSS[32]

AD4

VSS[33]

AD61

VSS[34]

AE13

VSS[35]

AE8

VSS[36]

AF1

VSS[37]

AF17

VSS[38]

AF21

VSS[39]

AF47

VSS[40]

AF48

VSS[41]

AF50

VSS[42]

AF51

VSS[43]

AF52

VSS[44]

AF53

VSS[45]

AF55

VSS[46]

AF56

VSS[47]

AF58

VSS[48]

AF59

VSS[49]

AG10

VSS[50]

AG14

VSS[51]

AG18

VSS[52]

AG47

VSS[53]

AG52

VSS[54]

AG61

VSS[55]

AG7

VSS[56]

AH4

VSS[57]

AH58

VSS[58]

AJ13

VSS[59]

AJ16

VSS[60]

AJ20

VSS[61]

AJ22

VSS[62]

AJ26

VSS[63]

AJ30

VSS[64]

AJ34

VSS[65]

AJ38

VSS[66]

AJ42

VSS[67]

AJ45

VSS[68]

AJ48

VSS[69]

AJ7

VSS[70]

AK1

VSS[71]

AK52

VSS[72]

AL10

VSS[73]

AL13

VSS[74]

AL17

VSS[75]

AL21

VSS[76]

AL25

VSS[77]

AL28

VSS[78]

AL33

VSS[79]

AL36

VSS[80]

AL40

VSS[81]

AL43

VSS[82]

AL47

VSS[83]

AL61

VSS[84]

AM13

VSS[85]

AM20

VSS[86]

AM22

VSS[87]

AM26

VSS[88]

AM30

VSS[89]

AM34

VSS[90]

IVY-BRIDGE_BGA1023

@

VSS

A

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

B

UCPU1I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023

@

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS

Issued Date

NCTF

C

M4

VSS[250]

M58

VSS[251]

M6

VSS[252]

N1

VSS[253]

N17

VSS[254]

N21

VSS[255]

N25

VSS[256]

N28

VSS[257]

N33

VSS[258]

N36

VSS[259]

N40

VSS[260]

N43

VSS[261]

N47

VSS[262]

N48

VSS[263]

N51

VSS[264]

N52

VSS[265]

N56

VSS[266]

N61

VSS[267]

P14

VSS[268]

P16

VSS[269]

P18

VSS[270]

P21

VSS[271]

P58

VSS[272]

P59

VSS[273]

P9

VSS[274]

R17

VSS[275]

R20

VSS[276]

R4

VSS[277]

R46

VSS[278]

T1

VSS[279]

T47

VSS[280]

T50

VSS[281]

T51

VSS[282]

T52

VSS[283]

T53

VSS[284]

T55

VSS[285]

T56

VSS[286]

U13

VSS[287]

U8

VSS[288]

V20

VSS[289]

V61

VSS[290]

W13

VSS[291]

W15

VSS[292]

W18

VSS[293]

W21

VSS[294]

W46

VSS[295]

W8

VSS[296]

Y4

VSS[297]

Y47

VSS[298]

Y58

VSS[299]

Y59

VSS[300]

G48

VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

Compal Secret Data

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

LA-8952P

E

0.1

11 55Thursday, January 10, 2013

E

A

+1.5V

12

R223

R223 1K_0402_1%

1K_0402_1%

12

All VREF traces should have 10 mil trace width

1 1

DDR_A_DQS#[0..7] <7>

DDR_A_DQS[0..7] <7>

DDR_A_D[0..63] <7>

DDR_A_MA[0..15] <7>

Layout Note: Place near JDIMM1

+1.5V

C294

1U_0402_6.3V6K

C294

1U_0402_6.3V6K

C326

1U_0402_6.3V6K

C326

1U_0402_6.3V6K

1

2

2 2

+1.5V

C287

10U_0603_6.3V6M

C287

10U_0603_6.3V6M

1

2

+1.5V

C303

10U_0603_6.3V6M

C303

10U_0603_6.3V6M

1

2

3 3

+0.75VS

C411

1U_0402_6.3V6K C411

1U_0402_6.3V6K

1

2

Layout Note: Pla

ce near JDIMM1.203,204

4 4

C314

10U_0603_6.3V6M

C314

10U_0603_6.3V6M

C284

10U_0603_6.3V6M

C284

10U_0603_6.3V6M

1

2

C293

10U_0603_6.3V6M

C293

10U_0603_6.3V6M

C343

10U_0603_6.3V6M@C343

10U_0603_6.3V6M

1

@

2

C412

1U_0402_6.3V6K C412

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K C413

1U_0402_6.3V6K

C291

1

2

1

2

C413

1

2

C289

10U_0603_6.3V6M

C289

10U_0603_6.3V6M

C311

220U_B2_2.5VM_R35

C311

220U_B2_2.5VM_R35

+

@

1

2

DDR_A0_DM0 DDR_A0_DM1 DDR_A0_DM2 DDR_A0_DM3 DDR_A0_DM4 DDR_A0_DM5 DDR_A0_DM6 DDR_A0_DM7

A

C310

1U_0402_6.3V6K

C310

1U_0402_6.3V6K

C414

1U_0402_6.3V6K C414

1U_0402_6.3V6K

+0.75VS

R226

R226 1K_0402_1%

1K_0402_1%

DDRA_CKE0_DIMMA< 7>

DDRA_CS1_DIMMA#<7>

+3VS

C222

2.2U_0402_6.3V6M

C222

2.2U_0402_6.3V6M

1

12

2

DDR_A_BS2<7>

SA_CLK_DDR0<7> SA_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

C409

2.2U_0402_6.3V6M

C409

2.2U_0402_6.3V6M

1

12

2

+VREF_DQ_DIMMA

C221

0.1U_0402_16V4Z

C221

0.1U_0402_16V4Z

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

C408

0.1U_0402_16V4Z C408

0.1U_0402_16V4Z

1 2

B

DDR_A_D0 DDR_A_D1

DDR_A0_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A0_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

SA_CLK_DDR0 SA_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A0_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A0_DM7

DDR_A_D58 DDR_A_D59

10K_0402_5%

R336

R331

10K_0402_5%

1 2

B

+1.5V +1.5V+VREF_DQ_DIMMA

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

TYCO_2-2013022-1

ME@

RESET#

VREF_CA

EVENT#

<Address: SA1:SA0=00>

DQS0#

DQS0

DQ12 DQ13

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3

DQ30 DQ31

CKE1

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5

DQ46 DQ47

DQ52 DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7

DQ62 DQ63

GND2

BOSS2

DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS

CK1

VSS

SDA SCL VTT

C

2

VSS

4

DDR_A_D4

6

DDR_A_D5

8 10

DDR_A_DQS#0

12

DDR_A_DQS0

14 16

DDR_A_D6

18

DDR_A_D7

20 22

DDR_A_D12

24

DDR_A_D13

26 28

DDR_A0_DM1

30

DIMM_DRAMRST#

32 34

DDR_A_D14

36

DDR_A_D15

38 40

DDR_A_D20

42

DDR_A_D21

44 46

DDR_A0_DM2

48 50

DDR_A_D22

52

DDR_A_D23

54 56

DDR_A_D28

58

DDR_A_D29

60 62

DDR_A_DQS#3

64

DDR_A_DQS3

66 68

DDR_A_D30

70

DDR_A_D31

72

74

DDRA_CKE1_DIMMA

76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

SA_CLK_DDR1 SA_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDRA_CS0_DIMMA# SA_ODT0

SA_ODT1

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A0_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A0_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

A15 A14

A11

A7

A6 A4

A2 A0

BA1

S0#

NC

DIMM_DRAMRST# <7>

DDRA_CKE1_DIMMA <7>

SA_CLK_DDR1 <7> SA_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_CS0_DIMMA# <7> SA_ODT0 <7>

SA_ODT1 <7>

C353

0.1U_0402_16V4Z C353

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

1

12

2

SMB_DATA_S3 <14,31,3 8> SMB_CLK_S3 <14,3 1,38>

+1.5V

12

R265

R265 1K_0402_1%

1K_0402_1%

12

R269

C354

1K_0402_1%

D

E

Channel A

DIMM_1 Standard H:4.0mm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

LA-8952P

0.1

12 5 5Thursday, January 10, 2013

E

12 5 5Thursday, January 10, 2013

0.1

A

B

C

D

E

RTCRST close to RAM door

12

R501

+RTCBATT

R356 20K_0402_5%

R357 20K_0402_5%

1 1

+RTCBATT

R358 1M_0402_5%

R355 330K_0402_5%

*

C439

1U_0402_6.3V6K

1 2

C440

1U_0402_6.3V6K

1 2

INTVRMEN

H

：：：：

Integrated VRM enable

：：：：

Integrated VRM disable

L

(INTVRMEN should always be pull high.)

+3VS

1 2

R109 1K_0402_5%@

HIGH= Enable ( No Reboot)Disable TCO timer system rebo

LOW= Disable (Default internal PD)

*

2 2

HDA_SDO

ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when sampled high

*

1.8V when sampled low eds to be pulled High for Huron River platfrom

Ne

HDA_BITCLK_AUDIO<36>

3 3

HDA_SDOUT_AUDIO<36>

4 4

+3V_PCH

ME_FLASH<37>

R47 1K_0402_5%

HDA_SYNC_AUDIO<36>

HDA_RST_AUDIO#<36>

12

@

R134

200_0402_5%

12

@

R141

100_0402_1%

1 2

R406 10M_0402_5%R406 10M_0402_5%

Y2

1 2

32.768KHZ_12.5PF_9H03200 019

18P_0402_50V8J

SJ10000BM00

1

C452

2

R501 0_0603_5%@

0_0603_5%@

PCH_RTCRST#

PCH_SRTCRST#

12

R372

R372 0_0603_5%@

0_0603_5%@

SM_INTRUDER# HDA_SPKR

PCH_INTVRMEN

HDA_SPKR

R46

1K_0402_5%

12

HDA_SYNC_PCH

@

PCH_RTCX1

PCH_RTCX2

1

C451

C451 18P_0402_50V8J

18P_0402_50V8J

2

A

HDA_SDOUT_PCH

HDA_BITCLK_PCH

HDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS

12

@

R73

0_0402_5%

@

12

R75

R75 33_0402_5%

33_0402_5%

1 2

R30

R30 33_0402_5%

33_0402_5%

1 2

R74

R74 33_0402_5%

33_0402_5%

1 2

R72

R72 33_0402_5%

33_0402_5%

1 2

+3V_PCH+3V_PCH +3V_PCH

12

@

R143

200_0402_5%

12

R140

R140 100_0402_1%

100_0402_1%

@

R137

200_0402_5%

@

R142

100_0402_1%

ot feature

Prevent back drive issue.

+5VS

G

2

SB00000QO00

S

R48

1 2

12

R29

R29 1M_0402_5%

1M_0402_5%

+3V_PCH

1 2

R266

1 2

R221

1 2

R127

1 2

R171

Q3

Q3 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

D

HDA_SPKR<36>

0_0402_5%@

HDA_SDIN0<36>

1 2

R162 1K_0402_1%@R162 1K_0402_1%@

R341 10K_0402_5%

SPI_WP#1

3.3K_0402_5%

SPI_HOLD#1

3.3K_0402_5%

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

12

R100

@

51_0402_5%

B

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BITCLK_PCH

HDA_SYNC_PCHHDA_SYNC_PCH_R

HDA_RST_PCH#

HDA_SDOUT_PCH

12

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH_R

SPI_SB_CS0#

SPI_SB_CS1#

SPI_SI

SPI_SO_R

SPI_SB_CS1# SPI_SO_R

SPI_SB_CS0#

HDA_SDIN0

PCH_GPIO33

PCH_GPIO13

0_0402_5%

1 2

33_0402_5%

0_0402_5%

1 2

33_0402_5%

U13A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER_FCBGA989

HM77@

JTAG

2MB SPI ROM FOR ME & Non-share ROM.

@

R172

12

CS1# SPI_SO1 SPI_HOLD#1

SPI_WP#1

R188

U6 Rersver 4M+2M Solution

@

R173

12

CS# SPI_SO_LSPI_SO_R

R169

U46

1

CS#

2

SO

3

WP#

4

GND

16M W25Q16BVSSIG SOIC 8P

U44

1

CS#

2

SO

3

SPI_WP# SPI_CLK_PCH

WP#

4

GND

32M W25Q32BVSSIG SOIC 8P

C38

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

SPI

VCC

HOLD#

SCLK

HOLD#

SCLK

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA 6G

SATA

SATAICOMPO

SATA3RCOMPO

SATA3COMPI

SATA0GP / GPIO21

SATA1GP / GPIO19

+3VS+3VS

8 7 6 5

SI

8

VCC

7 6 5

SI

Issued Date

C

SERIRQ

SATA0RXN SATA0RXP

SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP

SATA3TXN SATA3TXP

SATA4RXN SATA4RXP

SATA4TXN SATA4TXP

SATA5RXN SATA5RXP

SATA5TXN SATA5TXP

SATAICOMPI

SATA3RBIAS

SATALED#

SPI_CLK1 SPI_SI1

+3VS

0.1U_0402_16V4Z

SPI_HOLD#

SPI_SI_R

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

V5

SERIRQ

AM3 AM1 AP7

SATA_PTX_DRX_C_N0

AP5

SATA_PTX_DRX_C_P0

AM10

SATA_DTX_C_R_PRX_N1

AM8

SATA_DTX_C_R_PRX_P1

AP11

SATA_PTX_DRX_N1

AP10

SATA_PTX_DRX_P1

AD7

SATA_DTX_C_R_PRX_N2

AD5

SATA_DTX_C_R_PRX_P2

AH5

SATA_PTX_DRX_N2

AH4

AB8 AB10 AF3

Disable w/ HM70

AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

L=500mil S=15mil

Y10

SATA_COMP

AB12

L=500mil S=15mil

AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

BBS_BIT0_R

@

R199

0_0402_5%

1 2

SPI_CLK_PCH_R

1 2

SPI_SI

R196

R196 33_0402_5%

33_0402_5%

C191

1 2

0_0402_5%

0_0402_5% R168

R168

1 2

@

1 2

R170

R170 33_0402_5%

33_0402_5%

2011/06/24 2012/07/12

LPC_AD0 <31,3 7> LPC_AD1 <31,3 7> LPC_AD2 <31,3 7> LPC_AD3 <31,3 7>

LPC_FRAME# <31,37>

SERIRQ <37 >

R148 0_0402_5%HDD1@R148 0_0402_5 %HDD1@ R149 0_0402_5%HDD1@R149 0_0402_5 %HDD1@ R150 0_0402_5%HDD1@R150 0_0402_5 %HDD1@ R151 0_0402_5%HDD1@R151 0_0402_5 %HDD1@

R154 0_0402_5%HDD2@R154 0_0402_5 %HDD2@ R157 0_0402_5%HDD2@R157 0_0402_5 %HDD2@ R160 0_0402_5%HDD2@R160 0_0402_5 %HDD2@ R161 0_0402_5%HDD2@R161 0_0402_5 %HDD2@

1 2

R121 37.4 _0402_1%

1 2

R126 49.9 _0402_1%

1 2

R440 750 _0402_1%

SPI_CLK_PCH_R SPI_SI

Compal Secret Data

12

C1185 0 .01U_0402_16V7KC1185 0 .01U_0402_16V7K

12

C1208 0 .01U_0402_16V7KC1208 0 .01U_0402_16V7K

+1.05VS_VTT

No use PH 10K +3VS

Deciphered Date

12 12 12 12

C459

C459 10P_0402_50V8J

10P_0402_50V8J

1 2

@

D

SATA_PTX_R_DRX_N1_CO SATA_PTX_R_DRX_P1_CO

R434 33_ 0402_5%@

SATA_PRX_DTX_C_N0 <31> SATA_PRX_DTX_C_P0 <31> SATA_PTX_DRX_N0 <31> SATA_PTX_DRX_P0 <31>

SATA_DTX_C_PRX_N1

SATA_DTX_C_PRX_P1 SATA_PTX_R_DRX_N1_CO SATA_PTX_R_DRX_P1_COSATA_PTX_DRX_P2

Reserve for EMI

12

SPI_CLK_PCH_R

SERIRQ

R118 10K_0402_5%

12

SSD

12

C1209 0.01U_0402_16V7KC1209 0.01U_0402_16V7K

12

C1223 0.01 U_0402_16V7KC1223 0.01U_0402_16V7K

SATA_DTX_C_PRX_N1 <35> SATA_DTX_C_PRX_P1 <35> SATA_PTX_R_DRX_N1 <35> SATA_PTX_R_DRX_P1 <35>

HDD0 w/ HM77 Disable w/ HM70

HDD1 w/ HM70

GPIO19 has internal Pull up GPIO21 Debug Port DG 1.2 PH 4.7K +3VS

BBS_BIT0_R

PCH_SATALED#

PCH_GPIO21

R466 10K_0402_5%

R429 10K_0402_5%

R136 10K_0402_5%

Boot BIOS Strap

Boot BIOS

LPC

Reserved

-

SPI

*

Compal Electronics, Inc.

Title

Size Documen t Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC, XDP

LA-8952P

12

GPIO51

0 0 0 1 1 1

GPIO19

E

+3VS

1 0

13 55Thursday, January 10 , 2013

+3VS

0.1

A

PCIE_DTX_C_PRX_N1<32>

PCIE LAN

WLAN

1 1

+3VS

R424 10K_0402_5%

R110 10K_0402_5%

+3V_PCH

R414 10K_0402_5%

R389 10K_0402_5%

R53 10K_0402_5%

R50 10K_0402_5%

R32 10K_0402_5%

R51 10K_0402_5%

R54 10K_0402_5%

PCIE LAN

2 2

No use PH 10K +3VALW

WLAN

No use PH 10K +3VS

PCIE_DTX_C_PRX_P1<32> PCIE_PTX_C_DRX_N1<32> PCIE_PTX_C_DRX_P1<32>

PCIE_PRX_DTX_N2<31>

PCIE_PRX_DTX_P2<31> PCIE_PTX_C_DRX_N2<31> PCIE_PTX_C_DRX_P2<31>

12

CLK_PCIE_LAN#<32> CLK_PCIE_LAN<32>

LAN_CLKREQ#<32>

CLK_PCIE_WLAN1#<31> CLK_PCIE_WLAN1<31>

WLAN_CLKREQ#<31>

WLAN_CLKREQ#_R

PCH_GPIO20

PCH_GPIO25

LAN_CLKREQ#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO45

PCH_GPIO46

PCH_GPIO56

1 2

C480 0.1U_0402_16V7KC480 0.1U _0402_16V7K

1 2

C478 0.1U_0402_16V7KC478 0.1U _0402_16V7K

1 2

C482 0.1U_0402_16V7KC482 0.1U _0402_16V7K

1 2

C481 0.1U_0402_16V7KC481 0.1U _0402_16V7K

HM70 not support PCI

1 2

R153 0_0402_5%@R 153 0_0402_5%@

1 2

R163 0_0402_5%@R 163 0_0402_5%@

1 2

R164 0_0402_5%@R164 0_0402_5%@

1 2

R165 0_0402_5%@R 165 0_0402_5%@

1 2

R166 0_0402_5%@R 166 0_0402_5%@

1 2

R167 0_0402_5%@R 167 0_0402_5%@

use PH 10K +3VS

No

E port 4-7

No use PH 10K +3VALW

3 3

No use PH 10K +3VALW

No

use PH 10K +3VALW

No use PH 10K +3VALW

4 4

B

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

CLK_PCIE_LAN#_R CLK_PCIE_LAN_R

LAN_CLKREQ#_R

CLK_PCIE_WLAN1#_R CLK_PCIE_WLAN1_R

WLAN_CLKREQ#_R

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N PCIE_CLK_8P

U13B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GP IO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GP IO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GP IO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GP IO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GP IO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GP IO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GP IO46

AK14

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

AK13

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

PANTHER_FCBGA989

HM77@

SMBUSController

SML1ALERT# / PC HHOT# / GPIO74

PCI-E*

CLOCKS

CLKOUT_DP_N / C LKOUT_BCLK1_N

CLKOUT_DP_P / C LKOUT_BCLK1_P

C

SMBALERT# / GP IO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO 60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO7 5

CL_CLK1

Link

PEG_A_CLKRQ# / GPIO47

CLKIN_SATA_N / CKS SCD_N

CLKIN_SATA_P / CKS SCD_P

FLEX CLOCKS

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_DMI2_N CLKIN_DMI2_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

E12

PCH_GPIO11

H14

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PC H

C8

PCH_SML0CLK

G12

PCH_SML0DATA

C13

PCH_HOT#

E14

PCH_SML1CLK

M16

PCH_SML1DATA

M7

T11

P10

M10

PEG_CLKREQ#_R

AB37

CLK_PCIE_VGA#_R

AB38

CLK_PCIE_VGA_R

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12 AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_GND1#

BG30

CLKIN_GND1

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

W=12mil S=15mil

Y47

XCLK_RCOMP

K43

F47

H47

LAN_48M

K49

DGPU_PRSNT#

R56 10K_0402_5%

1 2

R207 22_0402_5%@R207 22_0402_5%@

D

No use PH 10K +3VALW

EC LID SW OUT

R,WLAN,XDPSMBUS

DD

PH 2.2K +3VALW

DRAMRST_CNTRL_PC H <7>

S3 reduse

PCH_HOT# <37>

No use PH 10K +3VALW

EC-PCH SMBUS

H

2.2K +3VALW

P

@

12

R9

R9 0_0402_5%

0_0402_5%

PX@

1 2

R58 0_04 02_5%@R58 0_0402_5%@

12

CLK_PCIE_VGA#

12

CLK_PCIE_VGA

R59 0_04 02_5%@R59 0_0402_5%@

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

1 2

R152 10K_0402_5%

1 2

R147 10K_0402_5%

1 2

R453 10K_0402_5%

1 2

R452 10K_0402_5%

1 2

R99 10K_0402_5%

1 2

R93 10K_0402_5%

1 2

R139 10K_0402_5%

1 2

R138 10K_0402_5%

1 2

R101 10K_0402_5%

R96

@R96

@

33_0402_5%

Reserve for EMI please close to PCH

R120

90.9_0402_1%

1 2

PCH_LAN_48M

PEG_CLKREQ# <23>

No use PH 10K +3VALW

12

C29 22P_0402_50V8J@C29 22P_0402_50V8J@

+1.05VS_VTT

DGPU_PRSNT#

DI

CLK_PCIE_VGA# <22> CLK_PCIE_VGA <22>

1 2

UMA@

S,Optimus

UMA

PCH_GPIO11

PCH_SMBCLKPCH_SMBCLK

PCH_SMBDATA

DRAMRST_CNTRL_PC H

PCH_HOT#

PCH_SML1CLK

PCH_SML1DATA

PEG_CLKREQ#_R

6 1

DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

DMN66D0LDW-7_SOT363-6

PCH_SML1DATA

PCH_SML1CLK

Pull down 10K ohm for using internal Clock

+3VS

12

R421

R421 10K_0402_5%

10K_0402_5%

R420

R420 10K_0402_5%PX@

10K_0402_5%PX@

1 2

GPIO67

DGPU_PRSNT#

6 1

DMN66D0LDW-7_SOT363-6

CLK_PCI_LPBACK <17>

0 1

1 2

R33 10K_0402_5%

1 2

R405 2.2K_0402_5%

1 2

R370 2.2K_0402_5%

1 2

R391 1K_0402_5%

1 2

R392 10K_0402_5%

1 2

R403 2.2K_0402_5%R403 2.2K_0402_5%

1 2

R369 2.2K_0402_5%R369 2.2K_0402_5%

UMA@

1 2

R25 10K_0402_5%

+3VS

2

Q34A

3 4

Q34B

+3VS

2

Q33A

3 4

XTAL25_IN

XTAL25_OUT

10P_0402_50V8J

For DDR

R404

2.2K_0402_5%

1 2

SMB_DATA_S3PCH_SMBDATA

R371

2.2K_0402_5%

5

1 2

SMB_CLK_S3

Pull up at EC side. For VGA,EC,Thermal sensor

EC_SMB_DA2

5

EC_SMB_CK2

Q33B

1

25MHZ_10PF_7V25000014

C457

2

E

+3V_PCH

+3VS

SMB_DATA_S3 <12,31,38>

+3VS

SMB_CLK_S3 <12,31,38>

EC_SMB_DA2 <23,34,37>

EC_SMB_CK2 <23,34,37>

+3V_PCH

R551

2.2K_0402_5%

OSC

NC

1 2

4

NC

1

OSC

PCH_SML0CLK

PCH_SML0DATA

1 2

R431 1M_0402_5%

3

2

Y3

SJ10000E500

R545

2.2K_0402_5%

1 2

1

2

C468

10P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-8952P

E

14 5 5Thursday, January 10, 2013

0.1

A

+3V_PCH

R26 200K_0402_ 5%

+3V_PCH

1 1

R34 10K_0402_5 %R34 10K_0402_5 %

R49 10K_0402_5 %R49 10K_0402_5 %

R390 10K_0402_5 %

R393 300_0402_5 %R39 3 300_0402_5 %

R394 10K_0402_5 %

+3VS

not support Deep S4,S5 can be left unconnected. Check list1.5 P.81

2 2

R397

@R397

@

12

200_0402_5 %

Follow G

AC_PRESENT_R

SUSWARN#_R

PCH_GPIO72

RI#

PM_DRAM_PW RGD

PCH_RSMRST#

PM_DRAM_PW RGD

For DS3

SUSACK#<37>

not support AMT APWROK can mux wi

th PWROK (check list1.5 P.47)

R191 0_ 0402_5%@R1 91 0_0402_5%@

AEPWROK can be connect to PWROK if iAMT disable

+3VALW

R195 200K_0402_ 5%R195 200K_0402_ 5%

12

APWROKPCH_PW ROK_R

PCH_APWROK<37>

For DS3

AC_PRESENT_R

PCH_PWROK

PM_DRAM_PW RGD<6>

EC_RSMRST#<37>

SUSWARN#<37>

PBTN_OUT#<37 >

ACIN<23,3 7,43>

No use PH 10K +3VALW

3 3

Ring Indicator CRB1.0 PH 10K +3VALW

B

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5 > DMI_CTX_PRX_P1<5 > DMI_CTX_PRX_P2<5 > DMI_CTX_PRX_P3<5 >

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5 > DMI_CRX_PTX_P1<5 > DMI_CRX_PTX_P2<5 > DMI_CRX_PTX_P3<5 >

+1.05VS_VTT

R156 49.9_0 402_1%

R155 750_0402 _1%

4mil width and place within 500mil of the PCH

R1468

+3VS

R107 0_0402_5%@R10 7 0_0402_5%@

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

L=500mil S=15mil

1 2

R415 10K_0402_ 5%

1 2

R303 0 _0402_5%@R303 0_0402_5 %@

0_0402_5%

1 2

R125

@ R125

@

R1489 0_0402_5 %@R1489 0_0402_5%@

1 2

@ R129

@

D3

1 2

RB751V-40_SOD3 23-2

0_0402_5%

0_0402_5% R129

DMI_IRCOMP

DMI2RBIAS

0_0402_5%@

12

XDP_DBRESET#_R

SYS_PWROK

PCH_PWROK_R

PM_DRAM_PW RGD

PCH_RSMRST#

12

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

SUSACK#_R

APWROK

C

U13C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN# / SUS_PWR_DN_ACK / GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER_FCBGA989

HM77@

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

PCH_PCIE_WAKE #

CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

SLP_A#

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

D

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 < 5> FDI_CTX_PRX_P1 < 5> FDI_CTX_PRX_P2 < 5> FDI_CTX_PRX_P3 < 5> FDI_CTX_PRX_P4 < 5> FDI_CTX_PRX_P5 < 5> FDI_CTX_PRX_P6 < 5> FDI_CTX_PRX_P7 < 5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

@

1 2

R133 0_0402 _5%

PCH_RSMRST#

T1 PAD@T1 PAD@

T4 PAD@T4 PAD@

H_PM_SYNC <6>

DSWODVREN

DSWODVREN - On Die DSW VR Enable

H

：：：：

Enable internal DSW +1.05VS

*

：：：：

Disable

L Must always PH at +RTCVCC

PCH_PCIE_WAKE #

PCH_GPIO29

CLKRUN#

For DS3

PCH_DPWROK

R135 0_0402_ 5%@R135 0_0402_5%@

not support Deep S4,S5 DPWROK mux with RSMRST# check list1.5 P.50

PCH_PCIE_WAKE # <31,32>

12

R375

R375 10K_0402_5 %

10K_0402_5 %

SUSCLK <37>

PM_SLP_S5# <37>

PM_SLP_S4# <37>

PM_SLP_S3# <37>

0111 Add R375 to GND

Can be left NC when IAMT is not support on the platfrom

SLP_SUS# <37, 40>

For DS3

If Intel LAN no use, can let be NC.

E

R350 330K_040 2_5%

R368 330K_040 2_5%@R368 330K_0402_5%@

R374 10K_0402 _5%

R36 10K_0 402_5%@R36 10K_0402_ 5%@

R423 8.2K_040 2_5%

12

1 2

@

1 2

DPWROK_EC <37>

not support Deep S4,S5 can NC PCH EDS1.5 P.75

+RTCBATT

+3V_PCH

+3VS

tell PCH all power ok bu

t cpu core

A

PCH_PWROK

12

R104

R104 10K_0402_5 %

10K_0402_5 %

VGATE<50>

PCH_PWROK<37>

4 4

+3VS

5

U36

2

P

B

1

A

G

MC74VHC1G08DFT2G_ SC70-5

3

Y

4

ALL power OK

SYS_PWROK

B

12

R119

R119 100K_0402_ 5%

100K_0402_ 5%

SYS_PWROK <6>

1

C52

0.047U_0402 _16V7K

2

@

Security Classification

2011/06/24 2012/0 7/12

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/0 7/12

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Do cument Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (3/9) DMI,FDI,PM

LA-8952P

E

of

15 55Thursday, January 1 0, 2013

0.1

A

+3VS

1 1

R108 2.2K_0402_5%R108 2.2K_0402_5%

R105 2.2K_0402_5%R105 2.2K_0402_5%

Change to eDP only

1 2

CTRL_CLK

CTRL_DATA

DIS only can NC

UMA LVDS DDC

1 2

R428 2.2K_0402_5%R428 2.2K_0402_5%

R425 2.2K_0402_5%R425 2.2K_0402_5%

1 2

EDID_CLK

EDID_DATA

Check list1.5 P.60 disable Graphics ALL Can NC but DAC_IREF still need PD

LVDS disable: DATA/Clock/Control an NC VCC_TX_LVDS,VCCA_LVDS PD to GND

2 2

CRT disable: DATA/Clock/Control an NC

UM77 not support

VD

S/CRT

L

VCCADAC connect to +3VS DAC_IREF connect 1K_0402_5%

3 3

B

PCH_ENBKL<29> PCH_ENVDD<29>

PCH_PWM<29>

EDID_CLK<29> EDID_DATA<29>

L=500mil S=20mil

R132

10mil S=30mil

W=

LVDS_ACLK#<29> LVDS_ACLK<29>

LVDS_A0#<29> LVDS_A1#<29> LVDS_A2#<29>

LVDS_A0<29> LVDS_A1<29> LVDS_A2<29>

CRT disable us

2.37K_0402_1%

12

1K_0402_5%

e 1K_0402_5%

PCH_ENBKL

CTRL_CLK CTRL_DATA

LVDS_IBG

LVD_VREF

LVDS_ACLK# LVDS_ACLK

LVDS_A0# LVDS_A1# LVDS_A2#

LVDS_A0 LVDS_A1 LVDS_A2

12

R114

CRT_IREF

U13D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER_FCBGA989

HM77@

C

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39

2.2K_0402_5%

AP40

P38

HDMICLK_NB

M39

HDMIDAT_NB

AT49 AT47 AT40

TMDS_B_HPD#

AV42

TMDS_B_DATA2#_PCH

AV40

TMDS_B_DATA2_PCH

AV45

TMDS_B_DATA1#_PCH

AV46

TMDS_B_DATA1_PCH

AU48

TMDS_B_DATA0#_PCH

AU47

TMDS_B_DATA0_PCH

AV47

TMDS_B_CLK#_PCH

AV49

TMDS_B_CLK_PCH

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

R144

HDMI@

D

+3VS

12

R131

2.2K_0402_5%

HDMI@

HDMICLK_NB <30> HDMIDAT_NB <30>

TMDS_B_HPD# <30>

C406 0.1U_0402_10V6KHDMI@ C406 0.1U_0402_10V6KHDMI@

1 2 1 2

C352 0.1U_0402_10V6KHDMI@ C352 0.1U_0402_10V6KHDMI@

1 2

C539 0.1U_0402_10V6KHDMI@ C539 0.1U_0402_10V6KHDMI@

1 2

C538 0.1U_0402_10V6KHDMI@ C538 0.1U_0402_10V6KHDMI@

1 2

C535 0.1U_0402_10V6KHDMI@ C535 0.1U_0402_10V6KHDMI@ C534 0.1U_0402_10V6KHDMI@ C534 0.1U_0402_10V6KHDMI@

1 2 1 2

C537 0.1U_0402_10V6KHDMI@ C537 0.1U_0402_10V6KHDMI@

1 2

C536 0.1U_0402_10V6KHDMI@ C536 0.1U_0402_10V6KHDMI@

Place close to connector side

E

HDMI_TX2-_CK <30> HDMI_TX2+_CK <30> HDMI_TX1-_CK <30> HDMI_TX1+_CK <30> HDMI_TX0-_CK <30> HDMI_TX0+_CK <30> HDMI_CLK-_CK <30> HDMI_CLK+_CK <30>

HDMI

HDMI D2

HDM

I D1

HDMI D0

HDMI CLK

4 4

Security Classification

2011/06/24 2012/07/12

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (4/9) LVDS,CRT,DP,HDMI

LA-8952P

16 55Thursday, January 10, 2013

E

0.1

of

A

+3VS

R90

18

PCI_PIRQC#

27

PCI_PIRQB#

36

PCI_PIRQA#

45

R409

18 27 36 45

PCI_PIRQD#

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PXS_PWREN_R

PCH_GPIO51

PCH_WL_OFF#

PCH_GPIO53

PCH_GPIO52

PCH_GPIO5

DGPU_HOLD_RST#_R

USB3.0

8.2K_1206_8P4R_5%

1 1

2 2

8.2K_1206_8P4R_5%

1 2

R408 8.2K_0402_5%R408 8.2K_0402_5%

1 2

R418 8.2K_0402_5%R418 8.2K_0402_5%

1 2

R432 8.2K_0402_5%R432 8.2K_0402_5%

1 2

R433 8.2K_0402_5%R433 8.2K_0402_5%

1 2

R401 8.2K_0402_5%R401 8.2K_0402_5%

+3VS

1 2

R66 8.2K_0402_5%R66 8.2K_0402_5%

1 2

R41 8.2K_0402_5%@R41 8.2K_0402_5%@

Boot BIOS Strap

Boot BIOS

GPI

O51GPIO19

GNT1#/ GPIO51

Internal PH

CR Check list 1.5 only use for GPIO

No use PH +3VS

Only GPIO fun

ction

3 3

4 4

PCH_WL_OFF#

R215 1K_0402_5%@R215 1K_0402_5%@

A16 swap overide Strap/Top-Block Swap Override jumper

PCI_GNT3#

Low=A16 swap override/Top-Block Swap Override enabled High=Default

PCH_PLTRST#

DGPU_HOLD_RST#

Bit11

0 1

1

1 1

CR Check list 1.5 only use for GPIO

無無無無無無無無

PH(Internal PH),

1 2

A

Destination

Bit10

Reserved

0

00

如如如如如如如如

GPIO55

*

R10 0_0402_5%@R10 0_0402_5%@

U25

@U25

@ 2

1

MC74VHC1G08DFT2G_SC70-5

U29

PX@U29

PX@ 2

1

MC74VHC1G08DFT2G_SC70-5

PCI

SPI

*

LPC

GPIO PH +3VS

CLK_PCI_LPBACK<14>

12

+3VS

5

P

B

4

Y

A

G

3

+3VS

5

P

B

4

Y

A

G

3

PXS_PWREN<24,49>

CLK_PCI_EC<37>

CLK_PCI_DB<31>

12

R11

100K_0402_5%

DGPU_HOLD_RST#

R6

12

0_0402_5%@R60_0402_5%@

B

USB3_RX2_N<39>

USB3_RX2_P<39>

USB3_TX2_N<39>

USB3_TX2_P<39>

PCI Interrupt Requests

R55 0_0402_5% @R55 0_0402_5% @

R57 0_0402_5% @R57 0_0402_5% @

PCH_WL_OFF#<31>

CLK_PCI_LPBACK

CLK_PCI_EC

R417 22_0402_5%

R417 22_0402_5% R84 22_0402_5%

R84 22_0402_5% R340 22_0402_5%

R340 22_0402_5%

PLT_RST# <31,32,37>

GPU_RST# <22>

B

12

PCI_PME#<37>

PCH_PLTRST#<6>

1 2 1 2

@

USB3_RX2_N

USB3_RX2_P

USB3_TX2_N

USB3_TX2_P

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST#_R

PCH_GPIO52

PXS_PWREN_R

PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

PCI_PME#

PCH_PLTRST#

12

CLK_PCI0 CLK_PCI1 CLK_PCI2CLK_PCI_DB

U13E

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

H3

AH12

AM4 AM5

Y13 K24

L24 AB46 AB45

B21

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

K40 K38 H38 G38

C46 C44 E40

D47 E42 F46

G42 G40 C42 D44

K10

C6

H49 H43 J48 K42 H40

PANTHER_FCBGA989

HM77@

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54

GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55

PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

C

AY7

NV_CE#0

AV7

NV_CE#1

AU3

NV_CE#2

BG4

NV_CE#3

AT10

NV_DQS0

BC8

NV_DQS1

NV_ALE NV_CLE

NV_RCOMP

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC5# / GPIO9

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AY1

DF_TVS

AV10

AT8

AY5 BA2

AT12 BF3

C24 A24 C25

USB20_N1

B25

USB20_P1

C26

USB20_N2

A26

USB20_P2

K28

USB20_N3

H28

USB20_P3

E28 D28 C28 A28 C29

HM70 not support USB port 4,5,6,7,12,13

B29 N28 M28 L30

USB20_N8

K30

USB20_P8

G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32

USB20_N11

K32

USB20_P11

G32 E32 C32 A32

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

USB20_N1 <39> USB20_P1 <39> USB20_N2 <31> USB20_P2 <31> USB20_N3 <29> USB20_P3 <29>

12/12/24 add touch function

USB20_N8 <38> USB20_P8 <38> USB20_N9 <38> USB20_P9 <38> USB20_N10 <38> USB20_P10 <38> USB20_N11 <29> USB20_P11 <29>

0110 modify WLAN USB port to USB8 Port9 is for debug.

1 2

R399 22.6_0402_1%

L=500mil S=15mil

Compal Secret Data

2011/06/24 2012/07/12

Compal Secret Data

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9

NV_DQ10 / NV_IO10

NVRAM

NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

RSVD

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

PCI

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC6# / GPIO10 OC7# / GPIO14

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

USB3 (Left side)

Mini Card (WLAN)

Touch Panel

USB2 (Right side)

Card Reader

CMOS Camera (LVDS)

USB_OC0# <39>

USB_OC4# <38>

Deciphered Date

D

Card reader

EHCI 1

EHCI 2

E

DMI,FDI Termination Voltage

DF_TVS

Set to Vcc when HIGH

Set to Vss when LOW

HR CPU NC

CR CPU PD

CR Check list P.89 PH 2.2K series 1K

+1.8VS

12

R145

2.2K_0402_5%

DF_TVS

R146 1K_0402_5%

CLOSE TO THE BRANCHING POINT

USB_OC0# USB_OC7# USB_OC5# USB_OC6#

USB_OC1# USB_OC4# USB_OC3# USB_OC2#

Title

Size Document Number Rev

Custom

Date: Sheet of

12

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

Compal Electronics, Inc.

PCH (5/9) PCI, USB, NVRAM

LA-8952P

R351

R349

H_SNB_IVB# <6>

+3V_PCH

E

17 55Thursday, January 10, 2013

0.1

A

<37,46>

HDA_SYNC PH(PLL =+1.5VS)

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

H

：：：：

On-Die PLL voltage regulator enable

*

L

：：：：

On-Die PLL Voltage Regulator disable

+3V_PCH

1 1

12

R411

R411 10K_0402_5%

10K_0402_5%

PCH_GPIO28

R413

@

1K_0402_5%

1 2

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

Fan Tachometer Inputs TACH1~7 only on server can insted to GPIO

No use PH 10K +3VS

No use PH 10K +3VALW

Deep S4,S5 wake event signal RTC

alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) Deep S4,S5 wake event signal

+3VALW

R208 10K_04 02_5%

R83 10K_0402_5%@R83 10K_0402_5%@

2 2

For DS3

@

1 2

12

PCH_GPIO27

No use PH +3VALW

No use PH +3VS

VGA_PWRGD<22,49>

No use PH 10K +3VS

No use PD 10K to GND

No use PH 10K +3VALW

No use PH 10K +3VS

+3V_PCH

SATA2GP/GPIO36 & SATA3GP/GPIO37 Sam Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts) NOTE: This signal should NOT be pulled high when strap is sampled

+3VS

3 3

+3V_PCH

4 4

DDR3L_EN#

1 2

R261 1K_040 2_5%@R261 1K_0402_5%@

pled at Rising edge of PWROK.

1 2

R112 10K_04 02_5%R112 10K_04 02_5%

1 2

R402 10K_04 02_5%

1 2

R70 10K_0402_5%

1 2

R115 10K_04 02_5%

1 2

R71 10K_0402_5%

1 2

R419 10K_04 02_5%R419 10K_04 02_5%

1 2

R97 10K_0402_5%R97 10K_04 02_5%

1 2

R416 10K_04 02_5%

1 2

R128 10K_04 02_5%

1 2

R111 10K_04 02_5%

1 2

R376 10K_04 02_5%

1 2

R412 1K_040 2_5%

1 2

R52 10K_0402_5%R52 10K_04 02_5%

1 2

R92 10K_0402_5%R92 10K_04 02_5%

R63 0_0402_5%@R63 0_0402_5%@

1 2

O24 Unmultiplexed

GPI NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. CRB1.0 PH10K to +3VALW

A

EC_SMI#

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

MSATA_DET#

VGA_PWRGD_R

PCH_GPIO39

BT_DISABLE

PCH_BT_ON#

PCH_GPIO48

PCH_GPIO49

PCH_GPIO12

PCH_GPIO15

PCH_GPIO57

PCH_GPIO24

For DDR3L control

PCH_GPIO24

No use can NC

Can't PH

No use PH 10K +3VS

A5GP&TEMP_ALERT# CRB PH 10K +3VS

SAT

No use PH +3VALW

+3VS

UMA@

1 2

R427 10K_04 02_5%

PX@

1 2

R426 10K_04 02_5%

*

Muxless nonMuxless

+3VS +3VS

12

R244

R244 10K_0402_5%

10K_0402_5%

@

PCH_GPIO37 INTE L_BT_OFF#

12

R552

R881

R881 10K_0402_5%

10K_0402_5%

GPIO36/GPIO37 is Strap functionality that requires internal pull down to be sampled at rising PWROK. When uses as SATA2GP/SATA3GP for mechanical presence detect

-use a external pull up 150K-200K ohm to Vcc3_3 When used as GP input

-ensure GPI is not driven high during strap sampling window When Unused as GPIO or SATA*GP

-use 8.2K-10K pull-down check list page 47

R552 10K_0402_5%

10K_0402_5%

B

EC_LID_OUT#<37>

EC_LID_OUT#

Blue Booth

DDR

3No use PH +3VALW

EC_WAKE#<37>

BT ON/OFF

1 2

R243 10K_04 02_5%R243 10K_04 02_5%

INTEL_BT_OFF#<31>

timus(L)/ non optimus(H)

Op

OPTIMUS_EN#

GPIO38

OPTIMUS_EN#

0 1

12

R245

R245 10K_0402_5%

10K_0402_5%

@

12

B

EC_SCI#<37>

EC_SMI#<37>

1 2

R45 0_0402_5%@R45 0_0402_5%@

BT_DISABLE<31>

EC_WAKE#

PCH_BT_ON#<31>

1 2

R60

1 2

@

R61 0_0402_5%

PCH_GPIO0

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

PCH_GPIO12

PCH_GPIO15

0_0402_5%@

mSATA_DET#

VGA_PWRGD_R

BT_DISABLE

PCH_GPIO24

PCH_GPIO27

PCH_GPIO28

PCH_BT_ON#

PCH_GPIO35

INTEL_BT_OFF#

PCH_GPIO37

OPTIMUS_EN#

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

PCH_GPIO57

9/15 Layout request remove Test point They will route by itself

C

PCH_GPIO69

0 1

U13F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER_FCBGA989

HM77@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

GPIO

C

Function

non DS3

DS3

A20GATE

PECI

RCIN#

INIT3_3V#

NC_1

NC_2

NC_3

NC_4

NC_5

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

THRMTRIP#

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

NCTF

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

2011/06/24 2012/07/12

10K_0402_5%

PCH_GPIO69 PCH_GPIO70

10K_0402_5%

PCH_GPIO68

PCH_GPIO69

PCH_GPIO70

PCH_GPIO71

PCH_PECI_R

EC_KBRST#

PCH_THRMTRIP#_R

9/15 Layout request remove Test point They will route by itself

Compal Secret Data

Deciphered Date

D

+3VS +3VS

12

R67

@R 67

@

R42

1 2

@

R1580_0402_5%@R1580_0402_5%

1 2

R159 390_0402_5%

INIT3_3V

Th PU, can't pull low,leave NC

TS_VSS1~4 PD to GND

R69

10K_0402_5%@

200K_0402_5%

1 2

+3VS

1 2

is signal has weak internal

D

R44

R106

R106 10K_0402_5%

10K_0402_5%

H_PECI <37,6>

KBRST# <37>

H_CPUPWRGD <6>

12

1 2

H_THERMTRIP#

Checklist1.5 P.69

E

PCH_GPIO70

0 1

PCH_GPIO71

0 1

GATEA20 <37>

Function

14"

13/

NA

SB3.0

U USB2.0

10K_0402_5%

PCH_GPIO71

200K_0402_5%

PECI CPU-EC

CTRL+ALT+DEL

non CPU power ok

EC_KBRST#

PCH_GPIO68

130c shut down

1 2

R103 10K_04 02_5%

1 2

R400 10K_04 02_5%

H_THERMTRIP# <6>

0419 ESD request to reserve

PCH_THRMTRIP#_R

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (6/9) GPIO, CPU, MISC

LA-8952P

E

1

C1324

1000P_0402_50V7K

2

18 55Thursday, January 10, 2013

R68

USB2@

R43

USB3@

@

+3VS

12

1 2

0.1

A

+1.05VS_VTT

1 1

+1.05VS_VTT

10U_0603_6.3V6M C106

10U_0603_6.3V6M

1

2

C106

C64

1U_0402_6.3V6K

C64

1U_0402_6.3V6K

1

2

Place Near AA23

1

2

1U_0402_6.3V6K

T31PAD @T31PAD @

C67

C75

1U_0402_6.3V6K

C75

1U_0402_6.3V6K

1

2

+VCCAPLLEXP

On-Die PLL Voltage Regulator

：：：：

On-Die PLL voltage regulator

H enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VC

CAPLLSATA

2 2

3 3

On-Die PLL Voltage Regulator

H enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,V

4 4

+1.05VS_VTT

C80

10U_0603_6.3V6M C80

10U_0603_6.3V6M

1

2

Pla

+3VS

Place Near BH29

：：：：

On-Die PLL voltage regulator

CCAPLLSATA

C88

1U_0402_6.3V6K C88

1U_0402_6.3V6K

C87

1U_0402_6.3V6K C87

1U_0402_6.3V6K

1

2

ce Near AN16,AN21,AN33

1

2

1U_0402_6.3V6K C90

1U_0402_6.3V6K

1

2

C107

0.1U_0402_16V7K

PAD @

T17

C90

+1.05VS_VCCAPLL_FDI

+1.05VS_VTT

C86

1U_0402_6.3V6K C86

1U_0402_6.3V6K

1

2

Trace 20mil

+1.5VS

1

C98

C98 1U_0402_6.3V6K

1U_0402_6.3V6K

2

Near AU

20

U13G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VCCFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER_FCBGA989

HM77@

2925mA

B

POWER

VCC CORE

60mA

VCCIO

FDI

1

mA

CRTLVDS

mA

1

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

266mA

20mA

DMI

190mA

VCCPNAND[1]

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

NAND / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCIO[1]

VCCSPI

C

Thermal Senser share with VCCADAC power rail so

can't remove this power

+VCCADAC

+VCCA_LVDS

+1.05VS_VTT

+1.8VS

+3VS

1

2

Place Near U48

1

0.01U_0402_16V7K

2

Place Near AM37

1

2

+3VS

0.01U_0402_16V7K

Place Near V33

1

C61

0.1U_0402_16V7K

2

1

C96

C96 1U_0402_6.3V6K

1U_0402_6.3V6K

2

place

ar AT20

ne

1

C81

0.1U_0402_16V7K

2

place near AG16

C60

C60 1U_0402_6.3V6K

1U_0402_6.3V6K

C53

C91

1

C54

0.1U_0402_16V7K

2

1

C92

0.01U_0402_16V7K

2

+1.5VS

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

MBK1608221YZF_2P

1

C40

C40 10U_0603_6.3V6M

10U_0603_6.3V6M

2

12

C108

C108 22U_0603_6.3V6K

22U_0603_6.3V6K

L16

R442

1 2

0_0603_5%

12

+VCCTX_LVDS

+3VS

0.1UH_MLF1608DR10KT_10%_1608

I/O Buffer Voltage

Internal PLL and VRM(+1.5VS)

DMI buffer logic

Core Well I/O Buffer

VccDFTERM should PH +1.8VS or +3VS

For

SPI control logi

D

L27

+1.8VS

12

0.1uH inductor, 200mA

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

VccIO 2.925

VccASW 1.01

VccSPI 0.02

VccDSW 0.003

Voltage

1.05

5

3.3

1.05

1.0

1.05

3.3

1.8 0.19VccpNAND

VccRTC 6 uA

VccSus3_3

3.3

3.3 / 1.5VccSusHDA

VccVRM 1.8 / 1.5 0.16

VccCLKDMI

VccSSC 0.095

VccDIFFCLKN 0.055

VccALVDS

VccTX_LVDS 0.06

1.05

3.3

1.8

5

S0 Iccmax Current(A)

0.001

0.266

0.001

0.08

1.3

0.042

0.266

0.01

0.02

0.001

E

Processor I/F

PCH Core Well Reference Voltage

Suspend Well Reference Voltag

I/O Buffer Voltage

Display DAC Analog Power. This power is supplied by the core well.

Display PLL A power

Display PLL B power

Internal Logic Voltage

DMI Buffer Voltage

Core Well I/O buffers

1.05 V Supply for Intel R Management Engine and Integrated LAN

3.3 V Supply for SPI Controller Logic

3.3v supply for Deep S4/S5 well

1.8V power supply for DF_TVS

Battery Voltage

Suspend Well I/O Buffer Voltage

High Definition Audio Controller Suspend Voltage

1.8 V Internal PLL and VRMs (1.8 V for Desktop)

DMI Clock Buffer Voltage

Spread Modulators Power Supply

Differential Clock Buffers Power Supply

Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (7/9) PWR

LA-8952P

0.1

19 55Thursday, January 10, 2013

E

19 55Thursday, January 10, 2013

0.1

A

+3VS

L23

10UH_LB20 12T100MR_20%

1 2

10U_0603_ 6.3V6M

1 1

C71

+3VS_VCC_CLKF3 3

1

2

Near T38

GPIO28

O

Die PLL Voltage Regulator

n-

H

：：：：

On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

+1.05VS_VTT

2 2

L25

10UH_LB20 12T100MR_20%

1 2

L26

10UH_LB20 12T100MR_20%

@

+1.05VS_VCCA_A_DPL

C118

220U_B2_2.5VM_R35+C118

220U_B2_2.5VM_R35

1

+

2

+1.05VS_VCCA_B_DP L

@

C112

220U_B2_2.5VM_R35

C112

220U_B2_2.5VM_R35

1

+

2

C103

1U_0402_6.3V6K

C103

1U_0402_6.3V6K

1

2

C104

1U_0402_6.3V6K

C104

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K C55

1U_0402_6.3V6K

1

2

Near BD47

+1.05V analog internal clock PLL Can NC

C55

+3VALW

12

C187

22U_0805_6.3V6M

C187

22U_0805_6.3V6M

1

2

Not support Deep S4,S5 connect to +3VALW

suppied by internal

1.05V VR must NC

12

R4070_0603_5%@R4070_0603_5%

@

R301

R301 0_0603_5%

0_0603_5%

Near BF47

+1.05VS_VTT

+VCCDSW3 _3

Near M6

3 3

Place

r AF33,

nea AF34,AG34

Place near AG33

+1.05VS_VTT

1

2

C74

C74 1U_0402_6 .3V6K

1U_0402_6 .3V6K

+1.05VS_VTT

Place near BJ8

4.7U_0603_6.3V6K C114

4.7U_0603_6.3V6K

1

2

+1.05VS_VTT

Place near AG33

+1.05VS_VTT

C72

1

1U_0402_6 .3V6K

2

C79

C77

1

1U_0402_6 .3V6K

Place

2

ar AF17

ne

isolation between SSC (AG33) and DIFFCLKN(AF33,AF34,AG34)

4 4

18mil width(DIFFCLKN) 10mil (SSC)

C79

1

1U_0402_6 .3V6K

2

suppied by internal

1.05V VR Must NC

A

B

R430

@R430

@

0_0603_5%

12

1

2

T14PAD @T14PAD @

T30PAD @T30PAD @

+1.05VS_VTT

C113

22U_0603_6.3V6K

C113

22U_0603_6.3V6K

12

C56

1U_0402_6.3V6K C56

1U_0402_6.3V6K

C73

1U_0402_6.3V6K C73

1U_0402_6.3V6K

1

2

Near AA19

12

C39 0.1U_040 2_16V7KC39 0.1U_0402_16 V7K

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DP L

Near V16

T13PAD @T13PAD @

C109

0.1U_0402_16V7K C109

0.1U_0402_16V7K

C111

0.1U_0402_16V7K C111

0.1U_0402_16V7K

C114

1

+RTCBATT

2

B

+VCCACLK

+VCCDSW3 _3

C47

0.1U_0402_ 16V7K

Near T16

+PCH_VCCDSW

+3VS_VCC_CLKF3 3

+VCCAPLL_CPY_PCH

+VCCSUS1

T15PAD @T15PAD @

C110

22U_0603_6.3V6K

C110

22U_0603_6.3V6K

12

C66

1U_0402_6.3V6K C66

1U_0402_6.3V6K

1

2

+VCCRTCEXT

+1.5VS

12

+VCCSST

C57 0.1U_0 402_16V7K

+1.05VM_VCCSUS

C450

0.1U_0402_16V7K C450

0.1U_0402_16V7K

C445

1U_0402_6.3V6K C445

1U_0402_6.3V6K

1

2

Near A22

1

2

AD49

T16

V12

T38

BH23

AL29

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17 AF33 AF34 AG34

AG33

V16

T17

V19

BJ8

A22

C453

0.1U_0402_16V7K C453

0.1U_0402_16V7K

U13J

VCCACLK

VCCDSW3_3

3mA

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2

VCCIO[14]

DCPSUS[3]

VCCASW[1]

1010mA

VCCASW[2]

VCCASW[3]

VCCASW[4]

VCCASW[5]

VCCASW[6]

VCCASW[7]

VCCASW[8]

VCCASW[9]

VCCASW[10]

VCCASW[11]

VCCASW[12]

VCCASW[13]

VCCASW[14]

VCCASW[15]

VCCASW[16]

VCCASW[17]

VCCASW[18]

VCCASW[19]

VCCASW[20]

DCPRTC

VCCVRM[4]

80mA

VCCADPLLA

80mA

VCCADPLLB

VCCIO[7] VCCIO[8]

55mA

VCCIO[9] VCCIO[11]

VCCIO[10]

95mA

DCPSST

DCPSUS[1] DCPSUS[2]

1mA

V_PROC_IO

VCCRTC

PANTHER_FCBGA98 9

HM77@

POWER

119mA

Clock and Miscellaneous

CPURTC

1mA

PCI/GPIO/LPCMISC

SATA USB

10mA

HDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

C

D

VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec

+1.05VS_VTT

V5REF

C

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

+1.05VS_VTT

T21

V21

T19

P32

1

C51

C51 1U_0402_6 .3V6K

1U_0402_6 .3V6K

2

Near N26

1

C46

0.1U_0402_ 16V7K

2

+1.05VS_VTT

+PCH_V5REF_SU S

+VCCA_USBSUS

+PCH_V5REF_R UN

+VCCSATAPLL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T16

@ T16

@

PAD

+3V_PCH

1

C38

C38 1U_0402_6 .3V6K

1U_0402_6 .3V6K

2

Near N20

1

C471

0.1U_0402_ 16V7K

Place near

2

AJ2

+1.05VS_VTT

Near AH13,AH14,AF13

1

C76

C76 1U_0402_6 .3V6K

1U_0402_6 .3V6K

2

T29 PAD@ T29 PAD@

+1.05VS_VTT

Near AC16

1

C68

C68 1U_0402_6 .3V6K

1U_0402_6 .3V6K

2

+3V_PCH

1

C41

0.1U_0402_ 16V4Z

2

Ne

ar P32

+3V_PCH

1

C45

0.1U_0402_ 16V7K

Near T24Near T23

2

RB751V-40_SOD 323-2

Near M26

1 2

C37

0.1U_0402_ 16V7K

suppied by internal

5V VR Must NC

1.0

+3V_PCH

1

C62

0.1U_0402_ 16V7K

Place near

2

AA16,W16

+3V_PCH +5V_P CH

D23

1 2

RB751V-40_SOD 323-2

+3VS

1

C49

0.1U_0402_ 16V7K

Place near

2

T34

12

100_0402_ 5%

Near P34

R348

D29

GPIO28

+1.5VS

On-Die PLL Voltage Regulator

H

：：：：

On-Die PLL voltage regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

Need +3VALW and 0.1U close PCH

Compal Secret Data

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

D

+3VS +5VS

1 2

12

C42

C42 1U_0402_6 .3V6K

1U_0402_6 .3V6K

12

R130

R130 100_0402_ 5%

100_0402_ 5%

E

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (8/9) PWR

LA-8952P

20 55Thur sday, January 10, 2013

E

20 55Thur sday, January 10, 2013

0.1

A

1 1

2 2

3 3

4 4

U13H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER_FCBGA989

HM77@

B

U13I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER_FCBGA989

HM77@

C

H46

VSS[259]

K18

VSS[260]

K26

VSS[261]

K39

VSS[262]

K46

VSS[263]

K7

VSS[264]

L18

VSS[265]

L2

VSS[266]

L20

VSS[267]

L26

VSS[268]

L28

VSS[269]

L36

VSS[270]

L48

VSS[271]

M12

VSS[272]

P16

VSS[273]

M18

VSS[274]

M22

VSS[275]

M24

VSS[276]

M30

VSS[277]

M32

VSS[278]

M34

VSS[279]

M38

VSS[280]

M4

VSS[281]

M42

VSS[282]

M46

VSS[283]

M8

VSS[284]

N18

VSS[285]

P30

VSS[286]

N47

VSS[287]

P11

VSS[288]

P18

VSS[289]

T33

VSS[290]

P40

VSS[291]

P43

VSS[292]

P47

VSS[293]

P7

VSS[294]

R2

VSS[295]

R48

VSS[296]

T12

VSS[297]

T31

VSS[298]

T37

VSS[299]

T4

VSS[300]

W34

VSS[301]

T46

VSS[302]

T47

VSS[303]

T8

VSS[304]

V11

VSS[305]

V17

VSS[306]

V26

VSS[307]

V27

VSS[308]

V29

VSS[309]

V31

VSS[310]

V36

VSS[311]

V39

VSS[312]

V43

VSS[313]

V7

VSS[314]

W17

VSS[315]

W19

VSS[316]

W2

VSS[317]

W27

VSS[318]

W48

VSS[319]

Y12

VSS[320]

Y38

VSS[321]

Y4

VSS[322]

Y42

VSS[323]

Y46

VSS[324]

Y8

VSS[325]

BG29

VSS[328]

N24

VSS[329]

AJ3

VSS[330]

AD47

VSS[331]

B43

VSS[333]

BE10

VSS[334]

BG41

VSS[335]

G14

VSS[337]

H16

VSS[338]

T36

VSS[340]

BG22

VSS[342]

BG24

VSS[343]

C22

VSS[344]

AP13

VSS[345]

M14

VSS[346]

AP3

VSS[347]

AP1

VSS[348]

BE16

VSS[349]

BC16

VSS[350]

BG28

VSS[351]

BJ28

VSS[352]

D

E

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/24 2012/07/12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PCH (9/9) VSS

LA-8952P

0.1

21 55Thursday, January 10, 2013

E

21 55Thursday, January 10, 2013

0.1

5

PEG_HTX_C_GRX_P[15..0]<5>

PEG_HTX_C_GRX_N[15..0]<5>

D D

C C

B B

PEG_HTX_GRX_P[15..0]

PEG_HTX_GRX_N[15..0]

PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_N14

PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13

PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12

PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11

PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10

PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9

PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2

PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

AF30

AE31

AE29 AD28

AD30 AC31

AC29 AB28

AB30 AA31

AA29

Y28

Y30

W31

W29

V28

V30 U31

U29

T28

T30

R31

R29 P28

P30 N31

N29

M28

M30

L31

L29

K30

U8A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

4

PEG_GTX_HRX_P[0..15]

PEG_GTX_HRX_N[0..15]

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCI EXPRESS INTERFACE

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8P

PCIE_TX8N

PCIE_TX9P

PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

PEG_GTX_HRX_P[0..15] <5>

PEG_GTX_HRX_N[0..15] <5>

PEG_GTX_HRX_P15

PEG_GTX_HRX_N15

PEG_GTX_HRX_P14

PEG_GTX_HRX_N14

PEG_GTX_HRX_P13

PEG_GTX_HRX_N13

PEG_GTX_HRX_P12

PEG_GTX_HRX_N12

PEG_GTX_HRX_P11

PEG_GTX_HRX_N11

PEG_GTX_HRX_P10

PEG_GTX_HRX_N10

PEG_GTX_HRX_P9 PEG_GTX_HRX_N9

PEG_GTX_HRX_P8 PEG_GTX_HRX_N8

PEG_GTX_HRX_P7 PEG_GTX_HRX_N7

PEG_GTX_HRX_P6 PEG_GTX_HRX_N6

PEG_GTX_HRX_P5 PEG_GTX_HRX_N5

PEG_GTX_HRX_P4 PEG_GTX_HRX_N4

PEG_GTX_HRX_P3 PEG_GTX_HRX_N3

PEG_GTX_HRX_P2 PEG_GTX_HRX_N2

PEG_GTX_HRX_P1 PEG_GTX_HRX_N1

PEG_GTX_HRX_P0 PEG_GTX_HRX_N0

3

2

U8F

LVDS CONTROL

LVTMDP

216-0774207-A11ROB_F CBGA631

PX@

VARY_BL

DIGON

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P

TXOUT_U0N_D PF2N

TXOUT_U1P_DPF1P

TXOUT_U1N_D PF1N

TXOUT_U2P_DPF0P

TXOUT_U2N_D PF0N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

AB11 AB12

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

1

LVDS

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

CALIBRATION

12

N10

PWRGOOD

AL27

PERSTB

216-0774207-A11ROB_F CBGA631

PX@

PCIE LANE

CALIBRATION

PCIE_CALRP

PCIE_CALRN

4

PX@

Y22

AA22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PX@

1 2

R2981.27 K_0402_1%

R3002K_0402_1% PX@ R3002K_0402_1% PX@

+1.0VGS

Compal Secret Data

2010/07/12 2012/07/11

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

B

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

SeymourXT-S3 PCIE/LVDS

22 55Thursday, January 10, 2013

of

22 55Thursday, January 10, 2013

of

22 55Thursday, January 10, 2013

1

0.1

5

R299 10K_0402_5%

10K_0402_5%

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 0_04 02_5%

@

12

PX@R299

PX@

GPU_RST#

CLK_PCIE_VGA<14> CLK_PCIE_VGA#<14>

VGA_PWRGD<18,49>

A A

GPU_RST#<17>

5

+1.8VGS

L8

@ L8

@

D D

+1.0VGS

C C

+1.8VGS +DPLL_PVDD

B B

A A

12

0_0402_5%

@

L9

@ L9

@

0_0402_5%

@

+3VGS

L14

BLM15BD121SN1D_0402

+1.8VGS

12

PX@

L49

BLM15BD121SN1D_0402

BLM18AG121SN1D_0603

12

PX@

L17

12

PX@

4

1

XTALIN

27MHZ 16PF +-30PPM X3G027000FG1H-HX

2

PX@

C341

C341 10P_0402_50V8J

10P_0402_50V8J

1

C304

2

10U_0603_6.3V6M

12

1

C307

2

10U_0603_6.3V6M

1 2

R321 10K_0402_5%PX@ R321 10K_0402_5%PX@

1 2

R322 10K_0402_5%PX@ R322 10K_0402_5%PX@

1 2

R323 10K_0402_5%PX@ R323 10K_0402_5%PX@

1 2

R324 10K_0402_5%PX@ R324 10K_0402_5%PX@

1

C323

2

10U_0603_6.3V6M

1

C330

PX@

2

1

C334

2

1 2

R337 10M_0402_5%

PX@

Y6

NC

OSC

PX@

SJ1

@

PX@

10U_0603_6.3V6M

OSC

00009700

+DPC_VDD18

1

C305

2

1U_0402_6.3V4Z

+DPC_VDD10

1

C346

2

1U_0402_6.3V4Z

+DPLL_PVDD

1

C324

2

1U_0402_6.3V4Z

+DPLL_VDDC

1

C331

2

+TSVDD

1

C335

2

3

2

NC

5

@

PX@

1U_0402_6.3V4Z

PX@

1U_0402_6.3V4Z

PX@

1

C306

2

1

C347

2

1

C325

2

XTALOUT

+DPC_VDD18

0.1U_0402_10V6K

+DPC_VDD10

0.1U_0402_10V6K

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS GPIO26_TCK

0.1U_0402_10V6K

+DPLL_VDDC+1.0VGS

1

C332

2

0.1U_0402_10V6K

+TSVDD

1

C336

PX@

2

0.1U_0402_16V4Z

2

PX@

C350

C350 10P_0402_50V8J

10P_0402_50V8J

1

ACIN<15,37,43>

VRAM_ID2<27> VRAM_ID1<27> VRAM_ID0<27>

+DPC_VDD18

+DPC_VDD10

D4

CH751H-40PT_SOD323-2 @

+1.8VGS

D4

GPU_VID0<49>

GPU_VID1<49>

PEG_CLKREQ#<14>

1 2

R326

1 2

4.7K_0402_5%

@

PX@

12

R329 499_0402_1%

12

R332 249_0402_1%

PX@

12

C322 0.1U_0402_10V6K

PX@

+DPLL_PVDD

+DPLL_VDDC

R335 0_0402_5% @R335 0_0402_5% @ R333 0_0402_5% @R333 0_0402_5% @

R334 2.61K_0402_5%

+3VGS

+TSVDD

+DPC_VDD18

+DPC_VDD10

21

R319 10K_0402_5%

PEG_CLKREQ#

T64T64

5.11K_0402_1%PX@

R613

PX@

1 2

VRAM_ID2 VRAM_ID1 VRAM_ID0

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R GPU_GPIO5

GPU_GPIO8 GPU_GPIO9

GPU_GPIO11 GPU_GPIO12 GPU_GPIO13

GPU_VID0

T63T63

PX@

1 2

GPU_VID1

T70T70

GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO

TEST_EN

+VREFG_GPU

+DPLL_PVDD

+DPLL_VDDC

XTALIN XTALOUT

12 12

4

U8B

Y11

DVCLK

AE9

DVCNTL_0

L9

DVCNTL_1

N9

DVCNTL_2

AE8

DVDATA_12

AD9

DVDATA_11

AC10

DVDATA_10

AD7

DVDATA_9

AC8

DVDATA_8

AC7

DVDATA_7

AB9

DVDATA_6

AB8

DVDATA_5

AB7

DVDATA_4

AB4

DVDATA_3

AB2

DVDATA_2

Y8

DVDATA_1

Y7

DVDATA_0

W6

DPC_PVDD

V6

DPC_PVSS

AC6

DPC_VDD18#1

AC5

DPC_VDD18#2

AA5

DPC_VDD10#1

AA6

DPC_VDD10#2

U1

DPC_VSSR#1

W1

DPC_VSSR#2

U3

DPC_VSSR#3

Y6

DPC_VSSR#4

AA1

DPC_VSSR#5

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U10

GPIO_1

T10

GPIO_2

U8

GPIO_3_SMBDATA

U7

GPIO_4_SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6

T7

GPIO_7_BLON

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

GPIO_11

N5

GPIO_12

N3

GPIO_13

Y9

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16_SSIN

R6

GPIO_17_THERMAL_INT

W10

GPIO_18_HPD3

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21_BB_EN

N8

GPIO_22_ROMCSB

N7

GPIO_23_CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

TESTEN_LEGACY

T65T65

AB13

GENERICA

W8

GENERICB

W9

GENERICC

W7

GENERICD

AD10

GENERICE_HPD4

AC14

HPD1

AB16

PX_EN

AC16

VREFG

AF14

DPLL_PVDD

AE14

DPLL_PVSS

AD14

DPLL_VDDC

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

TS_FDO

AD17

TSVDD

AC17

TSVSS

216-0774207-A11ROB_FCBGA631

PX@

4

PLL/CLOCK

THERMAL

3

AF2

TXCAP_DPA3P

TX0P_DPA2P

TX0M_DPA2N

TX1P_DPA1P

TX1M_DPA1N

TX2P_DPA0P

TX2M_DPA0N

TXCBP_DPB3P

TX3P_DPB2P

TX3M_DPB2N

TX4P_DPB1P

TX4M_DPB1N

TX5P_DPB0P

TX5M_DPB0N

TX0P_DPC2P

TX0M_DPC2N

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

DPC_CALR

HSYNC

VSYNC

RSET

AVDD

AVSSQ

VDD1DI VSS1DI

COMP

H2SYNC

V2SYNC

VDD2DI VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDC6CLK

DDC6DATA

AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

W3 V2

Y4 W5

AA3 Y2

1 2

J8

R307

150_0402_1%

PX@

AM26

T55T55

R

AK26

RB

AL25

T56T56

G

AJ25

GB

AH24

T57T57

B

AG25

BB

AH26

VGA_HSYNC

AJ27

VGA_VSYNC

PX@

1 2

AD22

R318

R318 499_0402_1%

499_0402_1%

AG24

+AVDD

AE22

AE23

+VDD1DI

AD23

AM12

R2

AK12

R2B

AL11

G2

AJ11

G2B

AK10

B2

AL9

B2B

AH12

C

AM10

Y

AJ9

AL13

T53T53

AJ13

T54T54

AD19 AC19

AE20

AE17

AE19

1 2

AG13

R330

R330 715_0402_1%

715_0402_1%

@

AE6 AE5

AD2 AD4

AC11 AC13

AD13 AD11

AD20 AC20

AE16 AD16

AC1

T58T58

AC3

T59T59

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

+AVDD

1

C397

PX@

2

0.1U_0402_10V6K

+VDD1DI

1

C313

PX@

2

0.1U_0402_10V6K

Compal Secret Data

2010/07/12 2012/07/11

Compal Secret Data

TXCAM_DPA3N

DPA

DVO

DPA

DVO

TXCBM_DPB3N

DPB

DPC

TXCCP_DPC3P TXCCM_DPC3N

DAC1

DAC2

DDC/AUX

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX5P

DDCDATA_AUX5N

1

C400

PX@

2

1U_0402_6.3V4Z

1

C396

PX@

2

1U_0402_6.3V4Z

Deciphered Date

C401

C315

1

2

10U_0603_6.3V6M

1

PX@

2

10U_0603_6.3V6M

2

L10

1 2

0_0402_5%

@

L11

1 2

0_0402_5%

@

2

+1.8VGS

10K_0402_5%

VGA_SMB_CK2_R

VGA_SMB_DA2_R

1

0117 AMD reque st to stuff R3 20

GPU_GPIO0

R339 10K_0402_5%@R339 10K_0402_5%@

GPU_GPIO1

R338 10K_0402_5%PX@R338 10K_0402_5%PX@

GPU_GPIO2

R325 10K_0402_5%PX@R325 10K_0402_5%PX@

GPU_GPIO5

R320 10K_0402_5%PX@R320 10K_0402_5%PX@

GPU_GPIO8

R313 10K_0402_5%@R313 10K_0402_5%@

GPU_GPIO9

R314 10K_0402_5%@R314 10K_0402_5%@

GPU_GPIO11

R315 10K_0402_5%PX@R315 10K_0402_5%PX@

GPU_GPIO12

R316 10K_0402_5%@R316 10K_0402_5%@

GPU_GPIO13

R317 10K_0402_5%@R317 10K_0402_5%@

R548 10K_0402_5%@R548 10K_0402_5%@ R549 10K_0402_5%@R549 10K_0402_5%@

+3VGS

12

R328

R328 10K_0402_5%

10K_0402_5%

2

PX@

Q64A

PX@

Title

SeymourXT-S3 Main Generic/MSIC

Size Document Number Rev

C

Date: Sheet

+3VGS

12

R327

PX@

VGA_HSYNC VGA_VSYNC

2N7002DW-T/R7_SOT363-6

12 12 12 12

12 12

12 12 12

1 2 1 2

61

5

3

4

Q64B

2N7002DW-T/R7_SOT363-6

PX@

Compal Electronics, Inc.

1

+3VGS

EC_SMB_CK2 <14,34,37>

EC_SMB_DA2 <14,34,37>

23 55Thursday, January 10, 2013

of

0.1

5

4

3

2

1

1 2

R283

@ R283

@

0_0402_5%

12

55mA@1.0V, in BACO mode

+BIF_VDDC

@

R398

1 2

0_0805_5%

12

C342

@C342

@

22U_0603_6.3V6K

12

R284

@R284

PX@C345

PX@

2

G

@

470_0603_5%

Q35

@

Q35

@

13

D

S

2N7002K_SOT23-3

C345 1U_0402_6.3V6K

1U_0402_6.3V6K

+VGA_CORE

+3VALW

12

R263

PX@R263

100K_0402_5%

DTC124EKAT146_SC59-3

PXS_PWREN<17,49>

PXS_PWREN

PX@

PXS_PWREN#

Q26

1

OUT

2

IN

GND

PX@

3

D D

PX@

C1139

2

G

+3VS TO +3VGS

+3VS +3VGS

1

2

1 2

R271

PX@R271

PX@

100K_0402_5%

13

D

Q30

PX@

Q30

PX@

2N7002K_SOT23-3

S

J2

@J2

@

2 1

2MM

3 1

Q27

AP2301GN-HF_SOT23-3

2

1

C1143

0.1U_0402_16V4Z

2

1

PX@

C344

C344 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PX@Q27

PX@

PXS_PWREN#

PX@C1143

PX@

+1.8VS TO +1.8VGS

+1.8VS +1.8VGS

PX@

1

C375

SE107475K80

4.7U_0603_6.3V6M

C C

B B

4.7U_0603_6.3V6M

2

+VSB

R279

1 2

330K_0402_5%

PX@

PXS_PWREN#

+1.5V TO +1.5VGS

2

G

1 2

R1451

10K_0402_5%

13

D

Q32

2N7002K_SOT23-3

S

PXS_PWREN#

2 1

2MM

U15

PX@

U15

PX@

AO4430L_SO8

8 7 6 5

PX@R1451

PX@

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M C1145

C1145

PX@

SE107475K80

2

G

J4

@J4

@

4

SB00000RV00

12

C1142

0.1U_0402_25V6

1

2

+VSB

PX@

R275

R275 220K_0402_5%

220K_0402_5%

13

D

2N7002K_SOT23-3

S

1 2 3

PX@C1142

PX@

+1.5V_IO

R278

1 2

62K_0402_5%

PX@

Q37

PX@

Q37

PX@

PXS_PWREN#

U12

U12 AO4430L_SO8

AO4430L_SO8

8 7 6 5

SB00000RV00

1

PX@

C1140

C1140 10U_0603_6.3V6M

10U_0603_6.3V6M

2

J9

2 1

2MM

PX@

4

1 2

R287

@ R287

@

0_0402_5%

@J9

@

R280

R280 0_0402_5%

0_0402_5%

@

1 2 3

12

C1141 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.5VGS

1

PX@

C1146

C1146 10U_0603_6.3V6M

10U_0603_6.3V6M

2

PXS_PWREN#

12

C1149

0.047U_0402_25V6

PX@C1141

PX@

2

G

PX@C1149

PX@

12

R290

@R290

@

470_0603_5%

Q36

@

Q36

@

13

D

S

2N7002K_SOT23-3

12

C1147 1U_0402_6.3V6K

1U_0402_6.3V6K

R285

@R285

@

1 2

0_0402_5%

2N7002K_SOT23-3

SE107475K80

4.7U_0603_6.3V6M

+5VALW

R270

1 2

51K_0402_5%

PX@

PXS_PWREN

12

@

PX@C1147

PX@

R274

R274 470_0603_5%

470_0603_5%

13

D

2

G

Q31

@

Q31

@

S

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/10/12 2013/10/12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

SeymourXT_S3_BACO POWER

LA-8952P

1

24 55Thursday, January 10, 2013

of

0.1

5

4

3

2

1

+1.8VGS

D D

Change to 0 ohm P/N

+1.0VGS

@

Change to 0 ohm

@

P/N

C C

B B

total:440mA@LVDS total:300mA@DP

12

L180_0603_5%

@

total:240mA@LVDS total:220mA@DP

12

L200_0603_5%

@

1

C367

2

10U_0603_6.3V6M

1

C356

2

10U_0603_6.3V6M

1

C368

@

2

1

C360

@

2

+DPEF_VDD18

total:300mA

1

C355

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+DPEF_VDD10

1

C361

@

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

+DPEF_VDD18

+DPEF_VDD10

R463

PX@R463

PX@

12

150_0402_1%

+DPEF_VDD18

AG15 AG16

AG20 AG21

AG14

AH14 AM14 AM16 AM18

AF16

AG17

AF22

AG22

AF23 AG23 AM20 AM22 AM24

AF17

20mA

AG18

AF19

AG19

AF20

U8G

DPE_VDD18#1 DPE_VDD18#2

DPE_VDD10#1 DPE_VDD10#2

DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5

DPF_VDD18#1 DPF_VDD18#2

DPF_VDD10#1 DPF_VDD10#2

DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5

DPEF_CALR

DPE_PVDD DPE_PVSS

DPF_PVDD DPF_PVSS

DP A/B POWERDP E/F POWER

DP PLL POWER

DPA_VDD18#1 DPA_VDD18#2

DPA_VDD10#1 DPA_VDD10#2

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

DPB_VDD18#1 DPB_VDD18#2

DPB_VDD10#1 DPB_VDD10#2

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPAB_CALR

DPA_PVDD DPA_PVSS

DPB_PVDD DPB_PVSS

130mA

AE11 AF11

110mA

AF6 AF7

AE1 AE3 AG1 AG6 AH5

130mA

AE13 AF13

110mA

AF8 AF9

AF10 AG9 AH8 AM6 AM8

AE10

20mA

AG8 AG7

20mA20mA

AG10 AG11

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

+DPAB_VDD10

1 2

R464

150_0402_1%

PX@

C357

@

total:220mA

C362

@

+DPAB_VDD18+DPEF_VDD18

+DPAB_VDD18

1

2

1

2

+DPAB_VDD18

+DPAB_VDD10

+DPAB_VDD18

1

C359

C358

@

2

0.1U_0402_10V6K

1

C363

@

2

0.1U_0402_10V6K

Change to 0 ohm

2

P/N

1U_0402_6.3V4Z

10U_0603_6.3V6M

1 2

1

C364

@

Change to 0 ohm

2

P/N

1U_0402_6.3V4Z

10U_0603_6.3V6M

L21

+1.8VGS+DPAB_VDD18

@

12

L190_0603_5%@L190_0603_5%

+1.0VGS

0_0603_5%@

216-0774207-A11ROB_F CBGA631

PX@

A A

Security Classification

2010/07/12 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/07/12 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

B

Date: Sheet of

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SeymourXT-S3 DP PWR

25 55Thursday, January 10, 2013

1

0.1

of

5

+1.5VGS

4

3

2

1

2.3A(RMS)/2.8A(Peak)

1

C366

C365

2

10U_0603_6.3V6M

PX@

@

L46

0_0402_5%

L47

L48

PX@

110mA

1

C404

2

PX@

1

C429

PX@

2

1

C446

2

PX@

1

C462

2

PX@

D D

+1.8VGS +VDDC_CT

1 2

Change to 0 ohm P/N

@

1 2

L24

0_0402_5%

C C

B B

0_0402_5%

Change to 0 ohm P/N

1 2

BLM15BD121SN1D_0402

PX@

1 2

BLM15BD121SN1D_0402

PX@

1

C369

2

10U_0603_6.3V6M

1

C405

2

10U_0603_6.3V6M

PX@

1

C430

PX@

2

1U_0402_6.3V4Z

1

C370

C371

2

1U_0402_6.3V4Z

PX@

1

C422

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

0.1U_0402_10V6K

0120 change power rail to +PC IE_VDDR

1

C447

C449

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

10U_0603_6.3V6M

PX@

1

C463

C454

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

PX@

+1.0VGS

2

0.1U_0402_10V6K

PX@

1

C372

C373

C374

2

1U_0402_6.3V4Z

PX@

+3VGS

1

C427

2

PX@

L28

1 2

BLM15BD121SN1D_0402

PX@

1

C390

C389

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C428

C410

2

1U_0402_6.3V4Z

10U_0603_6.3V6M

PX@

For Seymour, PCIE_PVDD is PCIE_VDDR.

1

C456

C464

2

10U_0603_6.3V6M

PX@

1

C392

C381

C391

2

0.1U_0402_10V6K

PX@

@

17mA

60mA

170mA

+PCIE_VDDR

+MPV18

+SPV18

+SPV10

1

C458

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

U8D

H13

VDDR1#1

H16

VDDR1#2

H19

VDDR1#3

J10

VDDR1#4

J23

VDDR1#5

J24

VDDR1#6

J9

VDDR1#7

K10

VDDR1#8

K23

VDDR1#9

K24

VDDR1#10

K9

VDDR1#11

L11

VDDR1#12

L12

VDDR1#13

L13

VDDR1#14

L20

VDDR1#15

L21

VDDR1#16

L22

VDDR1#17

LEVEL

LEVEL TRANSLATION

TRANSLATION

AA20

VDD_CT#1

AA21

VDD_CT#2

AB20

VDD_CT#3

AB21

VDD_CT#4

AA17

VDDR3#1

AA18

VDDR3#2

AB17

VDDR3#3

AB18

VDDR3#4

V12

VDDR4#1

Y12

VDDR4#2

U12

VDDR4#3

AA11

NC#1

AA12

NC#2

V11

NC#3

U11

NC#4

MEM CLK

L17

NC_VDDRHA

L16

NC_VSSRHA

PLL

AM30

PCIE_PVDD

L8

75mA

NC_MPV18

H7

75mA

SPV18

H8

120mA

SPV10

J7

SPVSS

216-0774207-A11ROB_FCBGA631

PX@

MEM I/O

I/O

PCIE

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8

PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

CORE

POWER

ISOLATED

ISOLATED CORE I/O

CORE I/O

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8

VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23

BIF_VDDC#1 BIF_VDDC#2

VDDCI#1

VDDCI#2

VDDCI#3

VDDCI#4

VDDCI#5

VDDCI#6

VDDCI#7

VDDCI#8

+PCIE_VDDR

1

C387

C385

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 M11 M12

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

2

1U_0402_6.3V4Z

0.1U_0402_10V6K

PX@

1

C398

C399

2

1U_0402_6.3V4Z

PX@

11.8A(RMS)/12.9A(Peak)

1

C432

C431

2

1U_0402_6.3V4Z

PX@

1

C470

2

1U_0402_6.3V4Z

PX@

+VDDCI

1

C465

C460

2

1U_0402_6.3V4Z

PX@

504mA

1

C388

2

1U_0402_6.3V4Z

PX@

1920mA

1

C383

2

1U_0402_6.3V4Z

PX@

1

C415

2

1U_0402_6.3V4Z

PX@

1

C516

2

1U_0402_6.3V4Z

PX@

1

C461

2

1U_0402_6.3V4Z

PX@

1

C380

2

10U_0603_6.3V6M

1

C403

2

1U_0402_6.3V4Z

1

C416

2

1U_0402_6.3V4Z

7/22 modify

+BIF_VDDC

1

C466

2

10U_0603_6.3V6M

+1.8VGS

@

L22

12

0_0603_5%

Change to 0 ohm P/N

+1.0VGS

1

C384

2

10U_0603_6.3V6M

PX@

1

C419

C418

C417

2

1U_0402_6.3V4Z

PX@

1

C420

2

1U_0402_6.3V4Z

PX@

R745

1 2

9/28 Reserved for VGA_CORE 10/8 change to B2 size

1

@

0_0603_5%

PX@

+VGA_CORE

1

C423

2

10U_0603_6.3V6M

C426

C424

C425

2

10U_0603_6.3V6M

PX@

U8E

AA27

PCIE_VSS#1

AB24

PCIE_VSS#2

AB32

PCIE_VSS#3

AC24

PCIE_VSS#4

AC26

PCIE_VSS#5

AC27

PCIE_VSS#6

AD25

PCIE_VSS#7

AD32

PCIE_VSS#8

AE27

PCIE_VSS#9

AF32

PCIE_VSS#10

AG27

PCIE_VSS#11

AH32

PCIE_VSS#12

K28

PCIE_VSS#13

K32

PCIE_VSS#14

L27

PCIE_VSS#15

M32

PCIE_VSS#16

N25

PCIE_VSS#17

N27

PCIE_VSS#18

P25

PCIE_VSS#19

P32

PCIE_VSS#20

R27

+VGA_CORE

1

2

10U_0603_6.3V6M

PCIE_VSS#21

T25

PCIE_VSS#22

T32

PCIE_VSS#23

U25

PCIE_VSS#24

U27

PCIE_VSS#25

V32

PCIE_VSS#26

W25

PCIE_VSS#27

W26

PCIE_VSS#28

W27

PCIE_VSS#29

Y25

PCIE_VSS#30

Y32

PCIE_VSS#31

M6

GND#56

N11

GND#57

N12

GND#58

N13

GND#59

N16

GND#60

N18

GND#61

N21

GND#62

P6

GND#63

P9

GND#64

R12

GND#65

R15

GND#66

R17

GND#67

R20

GND#68

T13

GND#69

T16

GND#70

T18

GND#71

T21

GND#72

T6

GND#73

U15

GND#74

U17

GND#75

U20

GND#76

U9

GND#77

V13

GND#78

V16

GND#79

V18

GND#80

Y10

GND#81

Y15

GND#82

Y17

GND#83

Y20

GND#84

R11

GND#85

T11

GND#86

216-0774207-A11ROB_FCBGA631

PX@

GND

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8

GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/07/12 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Compal Electronics, Inc.

SeymourXT-S3 PWR/GND

26 55Thursday, January 10, 2013

1

26 55Thursday, January 10, 2013

of

0.1

5

M_DA[63..0]<28>

M_MA[13..0]<28>

M_DQM[7..0]<28>

M_DQS[7..0]<28>

D D

M_DQS#[7..0]<28>

M_DA[63..0]

M_MA[13..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

PARK SCL has different recommand

DRAM_RST#<28>

120P_0402_50V8J

C C

B B

A A

+1.5VGS

R363

40.2_0402_1%

R364

100_0402_1%

PX@

12

1

C467

0.1U_0402_16V4Z

2

PX@

9/28 change P/N to SD034100A80

1 2

R366

51.1_0402_1%

PX@

C469

40.2_0402_1%

100_0402_1%

PX@

1

2

+1.5VGS

R365

R457

10_0402_1%

R456

PX@

12

PX@

12

PX@

1 2

R460 51.1_0402_1%@R460 51.1_0402_1%@

1 2

R373 51.1_0402_1%@R373 51.1_0402_1%@

R455

12

DRAM_RST

12

4.99K_0402_1%

PX@

+MVREFSA+MVREFDA

1

C514

0.1U_0402_16V4Z

2

+1.5VGS

1 2

C515 0.1U_0402_16V4Z@C515 0.1U_0402_16V4Z@

1 2

C517 0.1U_0402_16V4Z@C517 0.1U_0402_16V4Z@

Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not

need, DNI.

5

4

M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

+MVREFDA +MVREFSA

1 2

R458 240_0402_1%PX@R458 240 _0402_1%PX@

1 2

R459 240_0402_1%PX@R459 240 _0402_1%PX@

4

3

U8C

GDDR5/DDR3

K27

DQA0_0/DQA_0

J29

DQA0_1/DQA_1

H30

DQA0_2/DQA_2

H32

DQA0_3/DQA_3

G29

DQA0_4/DQA_4

F28

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

F30

DQA0_7/DQA_7

C30

DQA0_8/DQA_8

F27

DQA0_9/DQA_9

A28

DQA0_10/DQA_10

C28

DQA0_11/DQA_11

E27

DQA0_12/DQA_12

G26

DQA0_13/DQA_13

D26

DQA0_14/DQA_14

F25

DQA0_15/DQA_15

A25

DQA0_16/DQA_16

C25

DQA0_17/DQA_17

E25

DQA0_18/DQA_18

D24

DQA0_19/DQA_19

E23

DQA0_20/DQA_20

F23

DQA0_21/DQA_21

D22

DQA0_22/DQA_22

F21

DQA0_23/DQA_23

E21

DQA0_24/DQA_24

D20

DQA0_25/DQA_25

F19

DQA0_26/DQA_26

A19

DQA0_27/DQA_27

D18

DQA0_28/DQA_28

F17

DQA0_29/DQA_29

A17

DQA0_30/DQA_30

C17

DQA0_31/DQA_31

E17

DQA1_0/DQA_32

D16

DQA1_1/DQA_33

F15

DQA1_2/DQA_34

A15

DQA1_3/DQA_35

D14

DQA1_4/DQA_36

F13

DQA1_5/DQA_37

A13

DQA1_6/DQA_38

C13

DQA1_7/DQA_39

E11

DQA1_8/DQA_40

A11

DQA1_9/DQA_41

C11

DQA1_10/DQA_42

F11

DQA1_11/DQA_43

A9

DQA1_12/DQA_44

C9

DQA1_13/DQA_45

F9

DQA1_14/DQA_46

D8

DQA1_15/DQA_47

E7

DQA1_16/DQA_48

A7

DQA1_17/DQA_49

C7

DQA1_18/DQA_50

F7

DQA1_19/DQA_51

A5

DQA1_20/DQA_52

E5

DQA1_21/DQA_53

C3

DQA1_22/DQA_54

E1

DQA1_23/DQA_55

G7

DQA1_24/DQA_56

G6

DQA1_25/DQA_57

G1

DQA1_26/DQA_58

G3

DQA1_27/DQA_59

J6

DQA1_28/DQA_60

J1

DQA1_29/DQA_61

J3

DQA1_30/DQA_62

J5

DQA1_31/DQA_63

K26

MVREFDA

J26

MVREFSA

J25

MEM_CALRN0

K25

MEM_CALRP0

DRAM_RST

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

216-0774207-A11ROB_F CBGA631

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GDDR5/DDR3

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4

MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7

MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_13/BA2 MAA1_6/MAA_14/BA0 MAA1_7/MAA_15/BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

MEMORY INTERFACE

EDCA0_0/RDQSA_0 EDCA0_1/RDQSA_1 EDCA0_2/RDQSA_2 EDCA0_3/RDQSA_3 EDCA1_0/RDQSA_4 EDCA1_1/RDQSA_5 EDCA1_2/RDQSA_6 EDCA1_3/RDQSA_7

DDBIA0_0/WDQSA_0 DDBIA0_1/WDQSA_1 DDBIA0_2/WDQSA_2 DDBIA0_3/WDQSA_3 DDBIA1_0/WDQSA_4 DDBIA1_1/WDQSA_5 DDBIA1_2/WDQSA_6 DDBIA1_3/WDQSA_7

ADBIA0/ODTA0 ADBIA1/ODTA1

GDDR5

2010/07/12 2012/07/11

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA1_8 MAA0_8

3

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

E32 E30 A21 C21 E13 D12 E3 F4

H28 C27 A23 E19 E15 D10 D6 G5

H27 A27 C23 C19 C15 E9 C5 H4

L18 K16

H26 H25

G9 H9

G22 G17

G19 G16

H22 J22

G13 K13

K20 J17

G25 H10

G14 G20

M_MA13

Compal Secret Data

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1

M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7

VRAM_ODT0 VRAM_ODT1

M_CLK0 M_CLK#0

M_CLK1 M_CLK#1

M_RAS#0 M_RAS#1

M_CAS#0 M_CAS#1

M_CS#0

M_CS#1

M_CKE0 M_CKE1

M_WE#0 M_WE#1

Deciphered Date

64MX16 (512MB)

M_BA2 <28> M_BA0 <28> M_BA1 <28>

128M16 (1GB)

VRAM_ODT0 <28> VRAM_ODT1 <28>

M_CLK0 < 28> M_CLK#0 <28>

M_CLK1 < 28> M_CLK#1 <28>

M_RAS#0 <28> M_RAS#1 <28>

M_CAS#0 <28> M_CAS#1 <28>

M_CS#0 < 28>

M_CS#1 < 28>

M_CKE0 <28> M_CKE1 <28>

M_WE#0 < 28> M_WE#1 < 28>

2

+1.8VGS

1 2

R461 10K_0402_ 5%X76@R461 10K_0402_5%X76@

1 2

R462 10K_0402_ 5%X76@R462 10K_0402_5%X76@

1 2

R359 10K_0402_ 5%X76@R359 10K_0402_5%X76@

1 2

R360 10K_0402_ 5%X76@R360 10K_0402_5%X76@

1 2

R361 10K_0402_ 5%X76@R361 10K_0402_5%X76@

1 2

R362 10K_0402_ 5%X76@R362 10K_0402_5%X76@

K4W1G1646G-BC11

Samsung 128MB PN:SA00004GS00

H5TQ1G63DFR-11C

Hynix 128MB PN:SA000041S20

K4W2G1646C-HC11

Samsung 256MB PN:SA000047Q00

H5TQ2G63BFR-11C/H5TQ2G63DFR-11C

Hynix 256MB PN:SA00003YO10/ SA00003YOA0

S IC D3 128MX16 K4W2G1646E-BC11

Samsung 256MB

Title

Size Doc ument Number Rev

B

Date: Sheet of

Date: Sheet

2

Date: Sheet

1

VRAM_ID0

VRAM_ID1

VRAM_ID2

VRAM_ID1VRAM_ID0Vendor

R461

R462

R461

R462

R461

1

ZZZ

Hynix

H1G@

X7639238L02

Compal Electronics, Inc.

SeymourXT-S3 MEM Interface

1

0

R360

R359

R360

R359

R359 R361

1 1

1

0

1

0

VRAM_ID0 < 23>

VRAM_ID1 < 23>

VRAM_ID2 < 23>

VRAM_ID2

27 55Thursday, January 10, 2013

of

27 55Thursday, January 10, 2013

of

27 55Thursday, January 10, 2013

R362

0

R362

00

R361

11

R361

11

0.1

5

M_DA[63..0]<27>

M_MA[13..0]<27>

M_DQM[7..0]<27>

M_DQS[7..0]<27>

M_DQS#[7..0]<27>

D D

C C

M_DA[63..0]

M_MA[13..0]

M_DQM[7..0]

M_DQS[7..0]

M_DQS#[7..0]

VRAM_ODT0<27>

DRAM_RST#<27>

M_BA0<27> M_BA1<27> M_BA2<27>

M_CLK0<27> M_CLK#0<27> M_CKE0<27>

M_CS#0<27> M_RAS#0<27> M_CAS#0<27> M_WE#0<27>

R454

243_0402_1%

PX@

+VREFC_A1 +VREFD_Q1

M_DQS2 M_DQS0

M_DQM2 M_DQM0

M_DQS#2 M_DQS#0

12

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M_BA0 M_BA1 M_BA2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

U19

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

4

U20

E3

M_DA22

F7

M_DA20

F2

M_DA19

F8

M_DA18

H3

M_DA21

H8

M_DA17

G2

M_DA23

H7

M_DA16

D7

M_DA3

C3

M_DA1

C8

M_DA0

C2

M_DA5

A7

M_DA6

A2

M_DA7

B8

M_DA2

A3

M_DA4

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R451

243_0402_1%

PX@

+VREFC_A2 +VREFD_Q2

M_CLK0 M_CLK#0 M_CKE0

VRAM_ODT0 M_CS#0 M_RAS#0 M_CAS#0 M_WE#0

M_DQS3 M_DQS1

M_DQM3 M_DQM1

M_DQS#3 M_DQS#1

DRAM_RST#

12

M_BA0 M_BA1 M_BA2

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

3

U18

E3

M_DA25

F7

M_DA28

F2

M_DA27

F8

M_DA31

H3

M_DA24

H8

M_DA29

G2

M_DA26

H7

M_DA30

D7

M_DA14

C3

M_DA10

C8

M_DA15

C2

M_DA11

A7

M_DA12

A2

M_DA8

B8

M_DA13

A3

M_DA9

+1.5VGS

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

X76@

M_CLK1<27> M_CLK#1<27> M_CKE1<27>

VRAM_ODT1<27>

M_CS#1<27> M_RAS#1<27> M_CAS#1<27> M_WE#1<27>

243_0402_1%

+VREFC_A3 +VREFD_Q3

12

R410

PX@

U18

M8

VREFCA

H1

VREFDQ

N3

M_MA0

A0

P7

M_MA1

A1

P3

M_MA2

A2

N2

M_MA3

A3

P8

M_MA4

A4

P2

M_MA5

A5

R8

M_MA6

A6

R2

M_MA7

A7

T8

M_MA8

A8

R3

M_MA9

A9

L7

M_MA10

A10/AP

R7

M_MA11

A11

N7

M_MA12

A12

T3

M_MA13

A13

T7

A14

M7

A15/BA3

M2

M_BA0

BA0

N8

M_BA1

BA1

M3

M_BA2

BA2

J7

M_CLK1

CK

K7

M_CLK#1

CK

K9

M_CKE1

CKE/CKE0

K1

VRAM_ODT1

ODT/ODT0

L2

M_CS#1

CS/CS0

J3

M_RAS#1

RAS

K3

M_CAS#1

CAS

L3

M_WE#1

WE

F3

M_DQS4 M_DQS5

M_DQM4 M_DQM5

M_DQS#4 M_DQS#5

DRAM_RST# DRAM_RST#

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

H5TQ1G63DFR-11C

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

2

U21

E3

M_DA35

F7

M_DA34

F2

M_DA36

F8

M_DA37

H3

M_DA32

H8

M_DA38

G2

M_DA33

H7

M_DA39

D7

M_DA47

C3

M_DA42

C8

M_DA45

C2

M_DA40

A7

M_DA44

A2

M_DA43

B8

M_DA46

A3

M_DA41

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R444

243_0402_1%

PX@

+VREFC_A4 +VREFD_Q4

M_BA0 M_BA1 M_BA2

M_CLK1 M_CLK#1 M_CKE1

VRAM_ODT1 M_CS#1 M_RAS#1 M_CAS#1 M_WE#1

M_DQS6 M_DQS7

M_DQM6 M_DQM7

M_DQS#6 M_DQS#7

12

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

H5TQ1G63DFR-11C

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

X76@

1

E3

M_DA52

F7

M_DA48

F2

M_DA54

F8

M_DA50

H3

M_DA53

H8

M_DA49

G2

M_DA55

H7

M_DA51

D7

M_DA60

C3

M_DA58

C8

M_DA56

C2

M_DA61

A7

M_DA63

A2

M_DA62

B8

M_DA57

A3

M_DA59

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

B B

1 2

M_CLK0

R443 56_0402_1%

PX@

1 2

M_CLK#0

R396 56_0402_1%

PX@

1 2

M_CLK1

R422 56_0402_1%

A A

ref 139-02 recommand add off page Park SCL recommand pu 60.4 ohm

to 1.5VGS

0619 update

R422 56_0402_1%

M_CLK#1

R436 56_0402_1%

PX@

1 2

PX@

5

1

C506

0.01U_0402_16V7K

2

PX@

1

C507

0.01U_0402_16V7K

2

PX@

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

4.99K_0402_1%

C499

1U_0402_6.3V4Z

PX@

R447

PX@

+1.5VGS

1U_0402_6.3V4Z

@

C500

1

2

PX@

2

12

R383

4.99K_0402_1%

12

1U_0402_6.3V4Z

C501

1

2

1U_0402_6.3V4Z

PX@

1

2

1

C477

2

PX@

C484

0.1U_0402_10V6K

1U_0402_6.3V4Z

@

C508

1

2

1U_0402_6.3V4Z

PX@

C509

1

2

PX@

12

R384

4.99K_0402_1%

PX@

12

R446

4.99K_0402_1%

PX@

1U_0402_6.3V4Z

C503

C504

C505

C502

1U_0402_6.3V4Z

PX@

C505

C487

1

2

1U_0402_6.3V4Z

C487

1

2

@

PX@

Title

SeymourXT-S3 VRAM

Size Document Number Rev

C

Date: Sheet

Date: Sheet of

12

R450

4.99K_0402_1%

+VREFD_Q1

PX@

12

0.1U_0402_10V6K

R386

4.99K_0402_1%

1

C472

2

PX@

VRAM P/N :

Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )

Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )

R379

4.99K_0402_1%

R387

4.99K_0402_1%

12

+VREFC_A1

PX@

12

0.1U_0402_10V6K

1

C473

2

PX@

10U_0603_6.3V6M

+1.5VGS

C488

@

1

2

10U_0603_6.3V6M

update VRAM PN 0619 update

4

C489

4.99K_0402_1%

10U_0603_6.3V6M

1

C490

@

2

12

R380

PX@

12

R388

PX@

1

C512

2

10U_0603_6.3V6M

PX@

12

R381

4.99K_0402_1%

+VREFC_A2 +VREFD_Q2 +VREFD_Q3+VREFC_A3 +VREFC_A4 +VREFD_Q4

0.1U_0402_10V6K

1

C474

2

PX@

10U_0603_6.3V6M

1

C491

2

10U_0603_6.3V6M

PX@

PX@ PX@

PX@

4.99K_0402_1%

1

C511

2

PX@

12

0.1U_0402_10V6K

R449

1

2

PX@

1

C475

2

PX@

+1.5VGS

1U_0402_6.3V4Z

C492

1

2

1U_0402_6.3V4Z

PX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

1U_0402_6.3V4Z

C483

C510

C493

1

2

1U_0402_6.3V4Z

PX@

12

R382

4.99K_0402_1%

PX@

12

0.1U_0402_10V6K

PX@

1U_0402_6.3V4Z

C497

C496

1

@

2

1U_0402_6.3V4Z

PX@

1

C476

2

PX@

1U_0402_6.3V4Z

C498

1

2

PX@

Compal Secret Data

Deciphered Date

R448

4.99K_0402_1%

C494

C495

1

@

2

1U_0402_6.3V4Z

PX@

2010/07/12 2012/07/11

12

R385

4.99K_0402_1%

PX@

R445

4.99K_0402_1%

1

PX@

12

1

C479

2

PX@

28 55Thursday, January 10, 2013

0.1U_0402_10V6K

1

C513

2

Compal Electronics, Inc.

0.1U_0402_10V6K

0.1

of

5

LCD POWER CIRCUIT

+5VALW

12

R1455

R1454

R1454 150_0603_5%

D

Q71

S

@ R1459

@

100K_0402_5%

12

@

150_0603_5%

13

2

G

12

R1459

R1464

R1464 10K_0402_5%

10K_0402_5%

12

100K_0402_1%

D D

2N7002_SOT23

PCH_ENVDD<16>

C C

BKOFF#<37 >

B B

R1466 0_0402_5%

PCH_ENBKL<16>

A A

R1466 0_0402_5%

R1455 100K_0402_5%

100K_0402_5%

1

OUT

2

IN

GND

DTC124EKAT146_SC59-3

3

R1462

0_0402_5%

@

12

21

D30

@D30

@

CH751H-40PT_SOD323-2

R1467

1 2

R1457

220K_0402_5%

1 2

0.1U_0402_16V4Z

DTC124EK

Q73

+3VS

12

R1461

4.7K_0402_5%

2

1

C1154

2

FBMA-L11-201209-221LMA30T_0805

@R14 61

@

DISPOFF#BKOFF#

ENBKL <37>

+3VS+LCDVDD

G

1 3

4

W=60mils

1

C1150

4.7U_0603_6.3V6K

2

S

Q72

Q72 PMV65XP_SOT23-3~D

PMV65XP_SOT23-3~D

D

+LCDVDD

1 2

4.7U_0603_6.3V6K

PCH_PWM<16>

EC_INVT_PWM<37>

L29

W=60mils

+LCDVDD_CONN

1

C1156

2

R1463 0_0402_5%

R1465 0_0402_5%R1465 0_0402_5%

3

R1458

CMOS@R1458

CMOS@

150K_0402_5%

C1160

+3VS

CMOS

@C 1160

@

150K_0402_5%

R1479 0_0402_5%@R1479 0_0402_5%@

LVDS_ACLK<16,29> LVDS_ACLK#<16,29>

LVDS_A2<16,29> LVDS_A2#<16,29> LVDS_A1<16,29> LVDS_A1#<16,29> LVDS_A0<16,29> LVDS_A0#<16,29>

EDID_DATA<16,29> EDID_CLK<16,29>

1

+LCDVDD_CONN

2

+3VS_CMOS USB20_P11<17> USB20_N11<17>

1

C1155

0.1U_0402_16V4Z

2

12

+3VS

CMOS_ON#<37>

C1157

0.1U_0402_16V4Z

0314 For EC control 0418 Add to protect DISPOFF# damage

@

1 2

680P_0402_50V7K

CMOS Camera

+3VS

(20 MIL)

CMOS@

Q70

Q70 PMV65XP_SOT23-3~D

CMOS@C 1155

CMOS@

PMV65XP_SOT23-3~D

D

S

D

S

13

G

2

0_0603_5%

(20 MIL)

CMOS@ R1456

CMOS@

1

CMOS@

C1152

0.1U_0402_16V4Z

2

R296 for CMOS shake issue reserve

VGA LCD/PANEL BD. Conn.

@

R1460

1 2

1

C1158

(60

MIL)

USB20_P11

USB20_N11

680P_0402_50V7K

N98117648 DISPOFF# INVT_PWM

C1158

@

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

STARC_107K30-000001-G2

SP010011S00

2

ME@

GND1 GND2 GND3 GND4 GND5 GND6

0_0805_5%

C1159

4.7U_0805_25V6-K

31 32 33 34 35 36

2

+3VS_CMOS

12

R1456

R02

10U

1

C1153 10U_0603_6.3V6M

10U_0603_6.3V6M

2

B++LEDVDD

EC_TS_RST#< 37>

@C11 53

@

+3VS

CMOS

TOU

CH

R721 0_0402_5%R721 0_0402_5%

LVDS_ACLK<16,29> LVDS_ACLK#<16,29>

EDID_DATA<16,29> EDID_CLK<16,29>

+LCDVDD_CONN

USB20_P3<17> USB20_N3<17>

1 2

LVDS_A2<16,29> LVDS_A2#<16,29> LVDS_A1<16,29> LVDS_A1#<16,29> LVDS_A0<16,29> LVDS_A0#<16,29>

+3VS

+3VS_CMOS

USB20_P11<17> USB20_N11<17>

+3VS

+LEDVDD

USB20_P3 USB20_N3

TS_RST#

N98117648 DISPOFF# INVT_PWM

(60 MIL)

1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

JLVDS2 ME@

1

41

2

G1

42

3

G2

43

4

G3

44

5

G4

45

6

G5

46

7

G6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

STARC_107K40-000001-G2

SP01000XE00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LVDS/CAMERA

LA-8952P

1

29 5 5Thursday, January 10, 2013

0.1

5

4

3

2

1

+5VS

R1472

R1472 20K_0402_5%

20K_0402_5%

HDMI@

1 2

+5VS

3

1

2

D32

@D32

@

BAT54S-7-F_SOT23-3

HDMI_CLK-_CK

HDMI_CLK+_CK HDMI_TX0-_CK

HDMI_TX0+_CK HDMI_TX1-_CK

HDMI_TX1+_CK HDMI_TX2-_CK

HDMI_TX2+_CK

R1473 0_0402_5%@R1473 0_0402_5%@

R1474 0_0402_5%@R1474 0_0402_5%@ R1475 0_0402_5%@R1475 0_0402_5%@

R1476 0_0402_5%@R1476 0_0402_5%@ R1477 0_0402_5%@R1477 0_0402_5%@

R1478 0_0402_5%@R1478 0_0402_5%@ R1480 0_0402_5%@R1480 0_0402_5%@

R1481 0_0402_5%@R1481 0_0402_5%@

0308 Add for ESD request

+3VS

D D

TMDS_B_HPD#<16>

C C

+3VS

R1469

1M_0402_5%

HDMI@

TMDS_B_HPD#

1 2

Q74

HDMI@

G

2

2N7002H_SOT23-3

D

S

D

S

13

1

C1224

C1224 1000P_0402_50V7K

1000P_0402_50V7K

2

HDMI_CLK-_CK<16>

HDMI_CLK+_CK<16> HDMI_TX0-_CK<16>

HDMI_TX0+_CK<16 > HDMI_TX1-_CK<16>

HDMI_TX1+_CK<16 > HDMI_TX2-_CK<16>

HDMI_TX2+_CK<16 >

1 2

1 2 1 2

1 2

RB491D_SC59-3

RB491D_SC59-3 D31

HDMI@D31

HDMI@

2 1

R1470

HDMI@ R1470

HDMI@

2.2K_0402_5%

+HDMI_5V

1 2

Pull up R for PCH OR VGA SIDE

Q75A

HDMI@

2

2N7002DW-T /R7_SOT363-6

61

HDMICLK_NB<16>

B B

A A

HDMIDAT_NB<16>

5

4

3

Q75B

HDMI@

2N7002DW-T /R7_SOT363-6

HDMIDAT_R

HDMICLK_R

2

3

D33 PJDLC05_SOT23-3

PJDLC05_SOT23-3

1

HDMICLK_R

HDMIDAT_R

@D33

@

HDMI_CLK+_CK

HDMI_CLK-_CK

HDMI_TX0+_CK

HDMI_TX0-_CK

HDMI_TX1+_CK

HDMI_TX1-_CK

HDMI_TX2+_CK

HDMI_TX2-_CK

L30

1

4

WCM-2012HS-900T

L31

1

4

WCM-2012HS-900T

L32

1

4

WCM-2012HS-900T

L33

1

4

WCM-2012HS-900T

HDMI@L30

HDMI@

HDMI@L31

HDMI@

HDMI@L32

HDMI@

HDMI@L33

HDMI@

2

3

2

3

2

3

2

3

HDMI_CLK+_CONNHDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN

HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

Change Symbol to main source 02/24

680 +-5% 8P4R

45 36 27 18

RP1

HDMI@RP1

HDMI@

680 +-5% 8P4R

45 36 27 18

RP2

HDMI@RP2

HDMI@

W=40mils

F1

1.1A_6VDC_FUSE

R1471

HDMI@R1471

HDMI@

2.2K_0402_5%

1 2

HDMI_DET

+5VS_HDMI

HDMIDAT_R HDMICLK_R

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

13

D

S

HDMI@F1

HDMI@

2

G

Q76

HDMI@

2N7002H_SOT23-3

+5VS_HDMI

21

+5VS_HDMI

0.1U_0402_16V4Z

SD309680080 S R

OW RES 1/16W 680 +-5% 8P4R

+3VS

1

C1161

HDMI@

2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

CONCR_099ATAC19 NBLCNF

DC232001K00

ME@

GND GND GND GND

20 21 22 23

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics,Ltd.

Title

Size Doc ument Number Rev

B

Date: Sheet of

2

Date: Sheet of

HDMI CONN

LA-8952P

0.1

30 55Thursday, January 10, 2013

1

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half) Mini-Express Card for SSD(Full)

Mini-Express Card(WLAN/WiMAX)

9/18 JP1 Pin2,24,52 contact t o +3VS_WLAN for AOAC function

@

1 2

R1505 0_0402_5%

1 1

EC_WL_WAKE#<37>

PCH_BT_ON#<18>

BT_DISABLE<18>

INTEL_BT_OFF#<18>

R1505 0_0402_5%

@

1 2

R1490 0_0402_5%

1 2

R1491 0_0402_5%@R1491 0_0402_5%@

1 2

R1522 0_0402_5%@R1522 0_0402_5%@

1 2

R1523 1K_0402_5%R1523 1K_0402_5%

EC_WL_WAKE#_R

WLAN_CLKREQ#<14>

0524 For Intel 2230 combo car d only

EC_TX<37> EC_RX<37>

Note: The real behavior of BT_ DISABLE are

_DISABLE=LOW, BT=OFF

BT BT_DISABLE=HIGH, BT=ON

2 2

Mini-Express Card(SSD)

0.1U_0402_16V4Z

1

C1176

2

0.01U_0402_16V7K

3 3

SATA_PRX_DTX_C_P0<13>

SATA_PRX_DTX_C_N0<13>

SATA_PTX_DRX_N0<13> SATA_PTX_DRX_P0<13>

+3VS_SSD

1

C1177

2

10U_0603_6.3V6M

SATA_PRX_DTX_C_P0 SATA_DTX_IRX_P0 SATA_PRX_DTX_C_N0

SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

10U_0603_6.3V6M

1

C1178

2

11/07 Change type to 0603

+3VS_SSD

1 2

R1520 0_0402_5%@R1520 0_0402_5%@

BT_DISABLE_R WLAN_CLKREQ#

CLK_PCIE_WLAN1#<14>

CLK_PCIE_WLAN1<14>

PCIE_PRX_DTX_N2<14> PCIE_PRX_DTX_P2< 14>

PCIE_PTX_C_DRX_N2<14> PCIE_PTX_C_DRX_P2<14>

EC_TX EC_RX INT EL_BT_OFF#_R

For EC to detect de

bug card insert.

1

@

C1179

2

C11810.01U_0402_16V7K C11810.01U_0402_16V7K

12 12

SATA_DTX_IRX_N0

C11800.01U_0402_16V7K C11800.01U_0402_16V7K

PCI_RST#_R CLK_PCI_DB

100_0402_1%

R1498

1 2 1 2

R1499

100_0402_1%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

+3VS_WLAN

JSSD1

WAKE# NC NC CLKREQ# GND REFCLKREFCLK+ GND NC NC GND PERn0 PERp0 GND GND PETn0 PETp0 GND NC NC NC NC NC NC NC NC

GND

BELLW_80019-1021

DC040004X00

PCH_PCIE_WAKE# <15,32>

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

R1501

R1501 100K_0402_5%

100K_0402_5%

1 2

SSD Active:4.5W(1.5A)

+3VS

J14

2

112

JUMP_43X79

@

ME@

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

+3.3V

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22 24 26

GND

28 30 32 34

GND

36 38 40

GND

42 44 46 48 50

GND

52

54

GND

JWLAN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND REFCLKREFCLK+ GND NC NC GND PERn0 PERp0 GND GND PETn0 PETp0 GND NC NC NC NC NC NC NC NC

GND

BELLW_80019-1021

DC040004X00

+3VS_SSD

ME@

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

+3.3V

+3VS_WLAN

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22 24 26

GND

28 30 32 34

GND

36 38 40

GND

42 44 46 48 50

GND

52

54

GND

+1.5VS

12

R1488

R1488 0_0603_5%

0_0603_5%

@

+1.5VS_WLAN

R1492 0_0402_5%@R1492 0_0402_5%@

R1494 0_0402_5%@R1494 0_0402_5%@ R1495 0_0402_5%@R1495 0_0402_5%@

R1496 0_0402_5% @R1496 0_0402_5% @ R1497 0_0402_5% @R1497 0_0402_5% @

USB20_N2_WLAN USB20_P2_WLAN

1 2

1 2 1 2

+3VS

AOAC_ON#<37>

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

WL_RST#

+1.5VS_WLAN

1

C1172

0.1U_0402_16V4Z

2

R1518

0_0805_5%@

+3VALW +3VS_WLAN

12

C1170

0.1U_0402_16V4Z

R1502

R1502 150K_0402_5%

150K_0402_5%

AOAC@

PCH_WL_OFF# <17>

R1493 0_0402_5%@R1493 0_0402_5%@

SMB_CLK_S3 SMB_DATA_S3

+3VS_WLAN

1

2

+3VALW

1

AOAC@

C1175

0.1U_0402_16V4Z

2

12

SMB_CLK_S3 <12,14,38> SMB_DATA_S3 <12,14,38>

@

1

C1171

0.1U_0402_16V4Z

2

Q77 AO3413_SOT23-3

D

S

D

S

13

AOAC@

G

2

9/18 Increase for Intel AOAC f unction

Reserve for SW mini-pcie debug card.

ries resistors closed to KBC side.

Se

PLT_RST#INTEL_BT_OFF#_R

R1500

0_0805_5%

1

C1173

0.1U_0402_16V4Z

2

12

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

+3VS_WLAN_AOAC

R1482 0_0402_5%@R1482 0_0402_5%@ R1483 0_0402_5%@R1483 0_0402_5%@ R1484 0_0402_5%@R1484 0_0402_5%@ R1485 0_0402_5%@R1485 0_0402_5%@ R1486 0_0402_5%@R1486 0_0402_5%@ R1487 0_0402_5%@R1487 0_0402_5%@

PLT_RST# <17,32,37>

R1500 BOM structure: For test

1

AOAC@

C1174

0.1U_0402_16V4Z

2

1 2 1 2 1 2 1 2 1 2 1 2

USB20_N2_WLAN

USB20_P2_WLAN

USB20_N2_WLAN

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST#

R1503

@R1503

@

0_0402_5%

1 2

R1504 0_0402_5%@R1504 0_0402_5%@

+3VALW

7

5

4

TS3USB31RSER_QFN8_1P5X1P5

NC

D-

D+3HSD+

GND

U1

@

HSD-

8

VCC

6

2

1

OE#

LPC_FRAME# <13,37> LPC_AD3 <13,37> LPC_AD2 <13,37> LPC_AD1 <13,37> LPC_AD0 <13,37>

CLK_PCI_DB <17>

USB20_N2

USB20_P2

C1273

1 2

0.1U_0402_16V4Z

USB20_N2

USB20_P2USB20_P2_WLAN

12

@

R1519 0_0402_5%

0_0402_5%

@R1519

@

USB20_N2 <17>

USB20_P2 <17>

WLAN_USB_ON# <37>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/07/21 2012/12/31

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Mini-Card

LA-8952P

E

of

31 55Thursday, January 10, 2013

of

31 55Thursday, January 10, 2013

of

31 55Thursday, January 10, 2013

0.1

5

D D

1 2

PCIE_DTX_C_PRX_P1<14>

PCIE_DTX_C_PRX_N1<14>

PCIE_PTX_C_DRX_P1<14>

PCIE_PTX_C_DRX_N1<14>

LAN_CLKREQ#<14>

PLT_RST#<17,31,37>

CLK_PCIE_LAN<14>

C C

CLK_PCIE_LAN#<14>

Pin 16 and Pin 28 are OD pins

LAN_WAKE#<37>

PCH_PCIE_WAKE#<15,31>

+3V_LAN

12

R1512

R1512 10K_0402_5%

10K_0402_5%

@

LAN_CLKREQ#

B B

C1183 0.1U_0402_16V7KC1183 0.1U_0402_16V7K

1 2

C1186 0.1U_0402_16V7KC1186 0.1U_0402_16V7K

@

1 2

R1508 0_0402_5%

1 2

R1509@0_0402_5%R1509@0_0402_5%

+3V_LAN

R1510 10K_0402_5%@ R1510 10K_04 02_5%@

1 2

R1511 1K_0402_5%@ R1511 1K_0402_5%@

+LAN_VDDREG

PCIE_DTX_PRX_P1

PCIE_DTX_PRX_N1

LAN_XTALI

LAN_XTALO

PCIE_WAKE#_R

12

ENSWREG

1 2

R1513 2.49K _0402_1%R1513 2.49K_0402_1%

22

23

17 18

16

25

19 20

43

44

28

26

ISOLATEB

14 15 38

33

34 35

46

24 49

25MHZ_20PF_FSX3M-25.M20FDO

1

C1204

2

15P_0402_50V8J

4

U47

8105@

U47

8105@

RTL8105E-VL-CGT

U47

RTL8111F-CGT_QFN48_6x6

8111@

SA00003PO40

HSOP

HSON

HSIP HSIN

CLKREQB

PERSTB

REFCLK_P REFCLK_N

CKXTAL1

CKXTAL2

LANWAK EB

ISOLATEB

NC/SMBCLK NC/SMBDATA GPO/SMBALERT

ENSWR EG

VDDREG VDDREG

RSET

GND PGND

LED3/EEDO

LED1/EESK

SA00004Y700

Y4

4

1

SJ10000E500

NC

OSC

3

2

NC

LED0

EECS

EEDI

MDIP0 MDIN0 MDIP1

MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10

AVDD10 AVDD10 AVDD10 AVDD10

REGOUT

C1205

31 37 40

30

R1506 10K_0402_5%

32

R1507 10K_0402_5%

1

MDI0+

2

MDI0-

4

MDI1+

5

MDI1-

7

MDI2+

8

MDI2-

10

MDI3+

11

MDI3-

13 29 41

27 39

12 42 47 48

21

3 6 9 45

36

+LAN_REGOUT

LAN_XTALI

LAN_XTALO

1

2

15P_0402_50V8J

@

+LAN_VDD10

+3V_LAN

+LAN_EVDD10

+LAN_VDD10

12 12

MDI0+ <33> MDI0- <33> MDI1+ <33> MDI1- <33> MDI2+ <33> MDI2- <33> MDI3+ <33> MDI3- <33>

3

+LAN_REGOUT

Layout Note: L39 must be wi

thin 200mil to Pin36, C700,C738 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

+LAN_VDD10

1K_0402_5%

15K_0402_5%

L34

1 2

2.2UH +-5% NLC252018T-2R2J-N

4.7U_0603_6.3V6K

12

L350_0603_5% L350_0603_5%

1U_0402_6.3V4Z

Close to Pin 21

12

L360_0603_5% L360_0603_5%

4.7U_0603_6.3V6K

X5R

+3VS

12

R1514

ISOLATEB

R1516

+LAN_VDD10

12

C1184

X5R

12

C1187

12

C1195

H: Enable internal Regular L:

+LAN_EVDD10

C1188

0.1U_0402_16V4Z

1 2

+LAN_VDDREG+ 3V_LAN

0.1U_0402_16V4Z

1 2

ENSWREG

Disable

C1182

0.1U_0402_16V4Z

1 2

C1196

+3V_LAN

12

2

R1515

R1515 0_0402_5%

0_0402_5%

@

R1517

R1517 0_0402_5%

0_0402_5%

@

1

L

ayout Notice : Place as close

p as possible.

chi

J15

112

JUMP_43X79

@

+3V_LAN

2

Layout Notice : Place as close chip as possible.

+3VALW

Rising time (10%~90%)1mS <Rising time <100mS

Close to Pin 12,27,39,42,47,48

+3V_LAN

1 2

C11890.1U_0402_16V4Z C11890.1U_0402_16V4Z

1 2

C11900.1U_0402_16V4Z C11900.1U_ 0402_16V4Z

1 2

C11910.1U_0402_16V4Z C11910.1U_ 0402_16V4Z

1 2

C11920.1U_0402_16V4Z8111@ C11920.1U_0402_16V4Z8111@

1 2

C11930.1U_0402_16V4Z8111@ C11930.1U_0402_16V4Z8111@

1 2

C11940.1U_0402_16V4Z8111@ C11940.1U_0402_16V4Z8111@

Clo

se to Pin 3,6,9,13,29,41,45

1 2

+LAN_VDD10

C11970.1U_0402_16V4Z C11970.1U_040 2_16V4Z

C11980.1U_0402_16V4Z C11980.1U_040 2_16V4Z

C11990.1U_0402_16V4Z C11990.1U_040 2_16V4Z

C12000.1U_0402_16V4Z8111@ C12000.1U_0402_16V4Z8111@

C12010.1U_0402_16V4Z8111@ C12010.1U_0402_16V4Z8111@

C12020.1U_0402_16V4Z8111@ C12020.1U_0402_16V4Z8111@

C12030.1U_0402_16V4Z8111@ C12030.1U_0402_16V4Z8111@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN-RTL8111F/8105E

LA-8952P

Thursday, January 10, 2013

LA-8952P

1

32 5 5

0.1

5

4

3

2

1

Reserve gas tube for EMI go rural solution

SP0

50007J00

T71

MDI0+ MDI0-

MDI1+ MDI1-

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

BOTHHAND_NS0013L F

8111@

T72

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

BOTHHAND_NS0013L F

SP050007J00

MDI3+<32>

@

D D

MDI2+ MDI3+

MDI3- MDI2-

AZC099-04S.R7G_SOT23- 6

Pl

C C

MDI1+ MDI0+

@

D34

1

I/O1

2

GND

3

I/O2

I/O3

VDD

I/O4

ace Close to T71

@

D35

AZC099-04S.R7G_SOT23- 6

1

I/O1

2

GND

I/O3

VDD

4

5

6

1

C1207

0.01U_0402_16V7K

4

5

2

MDI3-<32>

MDI2+<32> MDI2-<32>

MDI3+ MDI3-

MDI2+ MDI2-

MDI0+<32> MDI0-<32>

MDI1+<32> MDI1-<32>

R02

TX+

RX+

TX+

RX+

16

MDO3+

15

MDO3-

TX-

14

MCT3

CT

13

NC

12

NC

11

MCT2

CT

10

MDO2+

9

MDO2-

Place Close to T1,T2

16

MDO0+

15

TX-

CT NC NC

CT

MDO0-

14

MCT0

13 12 11

MCT1

10

MDO1+

9

MDO1-

0320 EMI request to stuff

R1521

1 2

75_0805_5%

DL2

DL2 BS4200N-C-LV_SMB-F2

BS4200N-C-LV_SMB-F2

GAS@

00001D00

SCV

1 2

C1206

10P_0603_50V8-J

12

CHASSIS1_GND

MDI0- MDI1-

3

I/O2

Place Close to T72

4/D35

D3

'S

PN:SC300001G00

B B

1 2'S PN:SC300002E00

I/O4

6

JRJ1

ME@

JRJ1

ME@

12

GND

11

GND

10

MDO0+

MDO0-

MDO1+

MDO2+

MDO2-

MDO1-

MDO3+

MDO3-

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

SANTA_130460-3

DC231112261

GND

9

CHASSIS1_GND

Reserve for EMI go rural solution

A A

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

LAN_Transformer

LA-8952P

33 55Thursday, January 10, 2013

1

0.1

5

4

3

2

1

SMSC thermal sensor

aced near by VRAM

Close U27

REMOTE1+

D D

2200P_0402_50V7K

C1213

2200P_0402_50V7K

C1211

@C1213

@

1

2

1

2

REMOTE1-

REMOTE2+

REMOTE2-

C1212

0.1U_0402_16V4Z

+3VS

REMOTE1+

2

REMOTE1-

REMOTE2+

1

REMOTE2-

pl

U49

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403-2-AIZL-TR_MSOP10

SMCLK

SMDATA

ALERT#

THERM#

GND

+3VS

12

R1524

R1524 10K_0402_5%

10K_0402_5%

@

10

9

8

7

6

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2 <14,23,37>

EC_SMB_DA2 <14,23,37>

Address 1001_101xb

C C

+5VS

@

0_0603_5%

R1525

1 2

2

C1215

C1215 10U_0603_6.3V6M

10U_0603_6.3V6M

1

10U

EC_FAN_PWM<37>

+5VS_FAN

EC_TACH<37>

FAN1 Conn

JFAN1

ME@

JFAN1

ME@

1

2

3

4

5

G1

6

G2

ACES_85204-04001

SP02000CW00

H25

H25 HOLEA

HOLEA

1

H_2P5X3P1N

R

H17

H17 HOLEA

HOLEA

1

H_2P5X3P1N

FD1FD1

REMOTE1+

C1210

@ C1210

@

100P_0402_50V8J

REMOTE1-

REMOTE2+

C1214

@ C1214

@

100P_0402_50V8J

REMOTE2-

REMOTE1,2+/-: Tra

ce width/space:10/10 mil

Trace length:<8"

FD3FD3

FD2FD2

Close to DDR

1

C

2

B

2

E

3 1

1

C

2

B

2

E

3 1

FD4FD4

Q79

MMST3904-7-F_SOT323-3

Under mSSD

Q80

MMST3904-7-F_SOT323-3

B B

H8

H7

H7 HOLEA

HOLEA

1

H_2P5

H8 HOLEA

HOLEA

1

H_2P5

H13

H13 HOLEA

HOLEA

1

H_2P5

H15

H15 HOLEA

HOLEA

1

H_2P5N

H29

H29 HOLEA

HOLEA

1

H_4P0

H_2P5

H9

H9 HOLEA

HOLEA

1

CHASSIS1_GND

H6

H6 HOLEA

HOLEA

H_3P0

H10

H11

HOLEA

1

H_2P5

1

H_2P5

1

0418 Add for LAN screw hole

H26

H27

HOLEA

1

H_1P5N

E

H14

H14 HOLEA

HOLEA

1

H_5P4X2P5

R

H16

H16 HOLEA

HOLEA

1

H_5P9X3P0

H12

H12 HOLEA

HOLEA

1

H_5P4X2P5

1

M/B

橢橢橢

1

B KB

M/

橢橢橢

A

2P5 * 9 pcd

H22

H20

H18

H18 HOLEA

A A

HOLEA

1

H_4P0

CPU

B

H19

H19 HOLEA

HOLEA

1

H_4P0

5

H20 HOLEA

HOLEA

1

H_4P0

H21

H21 HOLEA

HOLEA

1

H_3P3

C

GPU

H22 HOLEA

HOLEA

1

H_3P3

H23

H23 HOLEA

HOLEA

1

CHASSIS1_GND

H_3P3

D

LAN

H24

H24 HOLEA

HOLEA

1

H_3P3

4

Security Classification

2011/06/15 2012/07/11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

2

F

Compal Electronics,Ltd.

Title

Fintek-Thermal IC/FAN/screw

Size Doc ument Number Rev

B

Date: Sheet of

LA-8952P

G

0.1

34 55Thursday, January 10, 2013

1

A

1 1

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

ME@

JHDD1

ME@

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RSVD

19

GND

20

V12

21

V12

22

V12

SANTA_192701-1

DC010006J00

@

C1222

0.1U_0402_16V4Z

1 2

1

C1221

C1221 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SATA_PTX_R_DRX_P1 SATA_PTX_R_DRX_N1

SATA_DTX_PRX_N1SATA_DTX_C_PRX_N1 SATA_DTX_PRX_P1

+3VS

12

+5VS_HDD

SATA_PTX_R_DRX_P1<13> SATA_PTX_R_DRX_N1<13>

1 2

SATA_DTX_C_PRX_N1<13>

SATA_DTX_C_PRX_P1<13>

2 2

+5VS_HDD

R02

1

C1218

C1218 1000P_0402_50V7K

1000P_0402_50V7K

2

SATA_DTX_C_PRX_P1

1

C1219

0.1U_0402_16V4Z

2

12

C1217 0.01U_0402_16V7KC1217 0.01U_0402_16V7K

1 2

C1216 0.01U_0402_16V7KC1216 0.01U_0402_16V7K

C1220 1U_0402_6.3V6K

1U_0402_6.3V6K

R02

@C1220

@

+5VS

R1526 0_0805_5%@R1526 0_0805_5%@

10U

PTH PTH

NPTH NPTH

23 24

25 26

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

D

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HDD/ODD/BT Connector

LA-8952P

G

35 55Thursday, January 10, 2013

H

0.1

5

D D

wer down (PD#) power stage for save power

Po

V:

Power down power stage

0

3.3V: Power up power stage

EC_MUTE#<37>

+3VS

R1535

4.7K_0402_5%

@

HDA_RST_AUDIO#<13>

C C

B B

wide 25MIL

SPK_R2+ SPK_R1SPK_L2+ SPK_L1-

A A

1 2

R1553 0_0603_5%R1553 0_0603_5%

1 2

R1555 0_0603_5%R1555 0_0603_5%

1 2

R1554 0_0603_5%R1554 0_0603_5%

1 2

R1556 0_0603_5%R1556 0_0603_5%

1 2

MIC Sense R939 place near pin13

Capless HP Sense R9

HDA_SDOUT_AUDIO<13>

HDA_BITCLK_AUDIO<13>

HDA_SDIN0<13>

HDA_SYNC_AUDIO<13>

PLUG_IN#<38>

40 place near pin34

+MIC1_VREFO_L

SPK_R2+_CONN SPK_R1-_CONN SPK_L2+_CONN

SPK_L1-_CONN

1

C1248

C1249

2

1000P_0402_50V7K

SPK_R2+_CONN

SPK_R1-_CONN

2

3

@

D38

PACDN042Y3R_SOT23-3

1

2

Reserve for ESD request.

5

4

600ohms @100MHz 1A P/N: SM01000BU00

600ohms @100MHz 2A

: SM01000EE00

P/N

@

R1531

1 2

+5VS

0_0805_5%

1 2

R1533 0_0402_5%@R1533 0_0402_5%@

1 2

EC_MUTE#

R1538 0_0402_5%@R1538 0_0402_5%@

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_SDIN0 SDATA_IN

HDA_RST_AUDIO#

PC_BEEP

C1239 2.2U_0402_6.3V6MC1239 2.2U_0402_6.3V6M

C1240 2.2U_0402_6.3V6MC1240 2.2U_0402_6.3V6M

C1241 4.7U_0603_6.3V6KC 1241 4.7U_0603_6.3V6K

1

C1250

C1251

SE074102K80

2

1000P_0402_50V7K

SPK_L1-_CONN

SPK_L2+_CONN

2

3

@

D39

PACDN042Y3R_SOT23-3

1

4

1000P_0402_50V7K

+5VDDA_CODEC+5VS

L37

1 2

FBMA-L11160808601LMA10T_2P

Place near Pin25

1

2

C1235

C1236

2

1

C1234

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

COMBOJACKMIC_JD

EC_MUTE#_R

12

R153622_0402_5% R153622_0402_5%

12

JDREF

R154120K_0402_1% R154120K_0402_1%

12

SENSEA

R154339.2K_0402_1% R154339.2K_0402_1%

CBN

12

CBP

12

Pin Assignment Location Function

SPK-OUT (Pin40/41/44/45)

Capless HP-OUT (Pin32/33)

MIC1(Pin21/22) Ex

JSPK1

4

6

4

G2

3

5

3

G1

2

1

ACES_88266-04001

SP0

2000K200

ME@

4.7U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

1

2

C1230

+5VS_PVDD

47

DAPD/COMB_JACK

4

PD#

5

SDATA-OUT

6

BIT-CLK

8

SDATA-IN

10

SYNC

11

RESET#

12

PCBEEP

19

JDREF

20

MONO-OUT(PORT-H)

13

Sense A

18

Sense-B

35

CBN

36

CBP

34

CPVEE

28

LDO-CAP

29

MIC2-VREFO

30

MIC1-VREFO-R

31

MIC1-VREFO-L

42

PVSS1

43

PVSS2

7

DVSS

3

+5VDDA_CODEC

1

C1231

2

0.1U_0402_16V4Z

U50

39

25

46

PVDD1

PVDD2

38

AVDD1

AVDD2

1

DVDD1

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-R(PORT-E-R)

LINE2-L(PORT-E-L)

HPOUT-R(PORT-A-R)

HPOUT-L(PORT-A-L)

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

ALC259Q-VC2-GR_QFN48_6X6

Internal

Ext

ernal

9

DVDD-IO

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

SPDIF-OUT

VREF

AVSS1

AVSS2

Thermal PAD

Int Speaker

Headphone out

1

2

C1232

2

1

C1233

0.1U_0402_16V4Z

C1233

4.7U_0603_6.3V6K

Place near Pin38

24

23

22

MIC_EXTR_C EXT_MIC

21

MIC_EXTL_C

17

16

15

14

40

41

44

45

33

HPOUT_R

32

HPOUT_L

48

3

DMIC_CLK_R

2

DMIC_DATA_R

27

26

37

49

ternal Mic in

Combo Jack detect (normal open)

R1123 47K_0402_5%R1123 47K_0402_5%

2

1

C1134

Issued Date

1 2

4.7U_0603_6.3V6K

2011/07/21 2012/12/31

MIC_JD

Security Classification

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

1 2

+3VDD_CODEC

+IOVDD_CODEC

Vendor recommend. 2.2u

1 2

C1237 2.2U_0402_6.3V6MC1237 2.2U_0402_6.3V6M

1 2

C1238 2.2U_0402_6.3V6MC1238 2.2U_0402_6.3V6M

SM01000CY00

EXT_MIC

Compal Secret Data

2

R1529

1

0_0603_5%

Place near Pin1 Place near Pin9

SPK_L2+

SPK_L1-

SPK_R1-

SPK_R2+

12

R154475_0402_5% R154475_0402_5%

12

R154575_0402_5% R154575_0402_5%

0425 EMI request to add these two bead.

12

R9370_0402_5%

12

R15480_0402_5%

12

C1226

C1227

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

2.2K_0402_5%

12

R1534 1K_0402_5%R1534 1K_0402_5%

0110 delete R1539

HP_OUTR <38>

HP_OUTL < 38>

DMIC_CLK <38>

DMIC_DATA <38>

C1228

@

+MIC1_VREFO_L

R1537

Internal Speaker

Hea

1

2

0.1U_0402_16V4Z

1 2

dphone

1 2

1

C1229

@

2

10U_0603_6.3V6M

Place next to pin 27

1

12

C1243

C1242

C1243

2

1U_0402_6.3V6K

0.1U_0402_16V4Z

R1549

@R1549

@

1 2

0_0402_5%

R1550

@R1550

@

1 2

0_0402_5%

R1551

1 2

0_0402_5%@

C1244

@

22P_0402_50V8J

GNDAGND

22P_0402_50V8J

PC Beep

EC Beep

PCH Beep

Deciphered Date

2

BEEP#<37>

HDA_SPKR<13>

1 2

C1252 0.1U_0402_16V4ZC1252 0.1U_0402_16V4Z

1 2

C1253 0.1U_0402_16V4ZC1253 0.1U_0402_16V4Z

1

+3VDD_CODEC+3VS +3VDD_CODEC +IOVDD_CODEC

R1530

SUPPRE_ KC FBMA-10-100505-101T 0402

Vendor recommend. 2.2K

EXT_MIC <38>

1

2

@

22P_0402_50V8J

PC_BEEP1 PC_BEEP

Title

Size Document Number Rev

C

Date: Sheet

external MIC

0522 EMI request to add C83 and C84

DMIC_CLK

DMIC_DATA

1

C83

100P_0402_50V8J

HDA_RST_AUDIO#

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

1

@

2

C1246

C1245

@

22P_0402_50V8J

12

@

R1558

R1558 10K_0402_5%

10K_0402_5%

Compal Electronics,Ltd.

HD Audio Codec_ALC259Q-VC

2

1 2

R1552 27_0402_5%@R1552 27_0402_5%@

1

C1247

C1247 33P_0402_50V8J

33P_0402_50V8J

2

R1557

1 2

33_0402_5%

C84

100P_0402_50V8J

2

HDA_BITCLK_AUDIO

1 2

LA-8952P

1

EMI

C44

0.1U_0402_16V7K

36 55Thursday, January 10, 2013

of

0.1

L38

FBM-11-160 808-601-T_0603

1 2

R1563 47K_0402 _5%R1563 47K_0402_ 5%

KSO[0..15]< 38>

KSI[0..7]<38>

R1568 4 7K_0402_5%@R1568 47K_0402_5%@1 2

R1570 4 7K_0402_5%@R1570 47K_0402_5%@1 2

+3VS

1 2

R1581 10K_0402 _5%R1581 10K_0402_ 5%

1 2

C1262

0.1U_0402_1 6V4Z

1 2

L39

FBM-11-160 808-601-T_0603

12

C1263 22P_0402_50V8J@ C1263 22P_0402_50V8J@

C1264

0.1U_0402_1 6V4Z

KSO[0..15]

KSI[0..7]

+3VALW

R1576

2.2K_0402_5%

EC_SMB_CK2 EC_SMB_DA2

1

@

C1268

C1268 100P_0402_5 0V8J

100P_0402_5 0V8J

2

EC_TACH

PCH_PWROK<15>

1

2

ECAGND

R1560 10_0402 _5%@ R1560 10_0402_5 %@

2

1

KSO1

KSO2

1 2

For DS3

DRAMRST_CNTRL_EC<7>

12

R1582

@ R1582

@

10K_0402_5%

1

2

12

PLT_RST#

1000P_0402_ 50V7K

R1574

R1577

C1260

1000P_0402_ 50V7K

2.2K_0402_5%

SUSCLK<15>

+3VALW +EC_VCCA

+3VALW

+3VS

R1575

2.2K_0402_5%

1

@

C1267

C1267 100P_0402_5 0V8J

100P_0402_5 0V8J

2

C1255

0.1U_0402_16V4Z

C1255

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

C1256

0.1U_0402_16V4Z

C1257

0.1U_0402_16V4Z

C1257

KBRST#<18>

SERIRQ<13>

LPC_AD3< 13,31> LPC_AD2< 13,31> LPC_AD1< 13,31> LPC_AD0< 13,31>

R1590 0_0402_5 %@ R1590 0_0402_5%@

NUM_LED#: NC

@

12

100K_0402_5 %

0.1U_0402_16V4Z

1

2

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMI#

EC_INVT_PWM EC_TACH EC_PME# EC_TX EC_RX PCH_PWROK EC_FAN_PWM

SUSCLK_R

R1587

1

2

GATEA20<18>

LPC_FRAME#< 13,31>

CLK_PCI_EC<17>

PLT_RST#<17,31,32 >

EC_SCI#<18>

0419 ESD request to reserve

C1330

@C13 30

@

EC_SMB_CK1

EC_SMB_DA1

BATT_LEN#<42>

1

2

EC_SMB_CK1<42,4 3> EC_SMB_DA1<42,4 3> EC_SMB_CK2<14,23,34 > EC_SMB_DA2<14,23,34 >

PM_SLP_S3#<15> PM_SLP_S5#<15> EC_SMI#<18> CMOS_ON#<29>

SLP_SUS#<15,40>

EC_INVT_PWM<29>

EC_TACH<34>

EC_TX<31> EC_RX<31>

EC_FAN_PWM<34>

0_0402_5%

0_0402_5% R1586

R1586

+3VLP

1

C1254

+3VALW

C1258

0.1U_0402_16V4Z

C1258

0.1U_0402_16V4Z

C1261

1000P_0402_50V7K

C1261

1000P_0402_50V7K

C1259

1000P_0402_50V7K

C1259

1

2

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

1000P_0402_50V7K

1

2

LPC & MISC

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

1

2

LPC_AD3 LPC_AD2 LPC_AD1 BATT_TEMP LPC_AD0

EC_RST# EC_SCI# BATT_LEN#

12

EC_RTCX1

12

C1271

C1271 20P_0402_50 V8

20P_0402_50 V8

2

+3VALW

+EC_VCCA

9

22

33

96

125

111

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

GND/GND

GND0

11

24

35

94

113

C1254 100P_0402_5 0V8J

100P_0402_5 0V8J

67

GPIO0F

BEEP#/GPIO10

EC_VDD/AVCC

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C

SPICLK/GPIO58

SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

PECI_KB9012/GPXIOD07

AGND/AGND

69

ECAGND

V18R

KB9012QF A3 L QFP 128P_14X14

U51

21

DDR3L_EN#_R

23

BEEP#

26

NOVO#

27

ACOFF

63 64 65 66

BATT_OUT_R

75

BRDID BRDID

76

68

EC_WL_W AKE#

70

WLAN_USB_O N#_R

71 72

83 84

USB_ON#

85 86 87

TP_CLK

88

TP_DATA

97

CPU1.5V_S3_GATE

98 99 109

NTC_V_R

119

PCH_PWR_EN

120

VSB_PWR_EN

126

AOAC_ON#

128

73 74 89 90

BATT_CHG_LED#

91

CAPS_LED#

92 93

BATT_LOW_LED #

95

SYSON

121 127

100 101

EC_LID_OUT#

102

Turbo_V

103

H_PROCHOT#_EC

104

MAINPWON_ R

105

BKOFF#

106

PBTN_OUT#

107 108

110

ACIN

112

EC_ON

114 115

LID_SW#

116

SUSP#

117

PCH_HOT#_R

118

PECI_KB9012

124

+V18R

1

2

PN : SA00004OB20 S IC KB9012QF A3 LQFP 128P KB CONTROLLER

R1599

R1598 0 _0402_5%@R1598 0_0402_5%@

R1595

0_0402_5%

R1571 0_0 402_5%@R1 571 0_0402_5%@

R1583 0 _0402_5%@R1583 0_04 02_5%@ 12

1 2

C1270

4.7U_0603_6 .3V6K

12

0_0402_5%@

BEEP# <36> NOVO# <38> ACOFF <43>

ADP_I <42,4 3>

12

For DS3

12

@R1595

@

EC_MUTE#

12

CAPS_LED# <38> PWR_LED# <38 > BATT_LOW_LED # <38>

SYSON <40,45,46 > VR_ON < 50>

PM_SLP_S4# <15 >

EC_RSMRST# <15> EC_LID_OUT# <18>

R1591 0_0 402_5%@R159 1 0_0402_5%@ 12

BKOFF# < 29>

PBTN_OUT# <15 >

PCH_APWROK <15> SA_PGOOD <48>

R1584 43_0402_ 1%R1584 43 _0402_1%

DDR3L_EN# <18,46>

BATT_TEMP <42>

BATT_OUT <42,43>

EC_FAN_PWM

EC_WL_W AKE# < 31>

WLAN_USB_O N# <31>

DPWROK_EC <15>

SUSWARN# < 15>

R1565 10K_ 0402_5%R1565 10K_0402_5%1 2

EC_MUTE# <36> USB_ON# <38,39>

EC_WAKE# <18>

TP_CLK <38>

TP_DATA <38>

R1580 0_04 02_5%@R1580 0_0 402_5%@

3.3V +/- 5%

Vcc

100K +/- 5%

R694

Board ID

0 1 2 3

+3VS +3VALW

12

R1561

R1561 10K_0402_5%

10K_0402_5%

@

For WLAN USB switch control

+3VALW

For DS3

CPU1.5V_S3_GATE <10,40>

ME_FLASH <13>

NTC_V <42>

PCH_PWR_EN <40 ,42> VSB_PWR_EN <42>

AOAC_ON# <31>

SUSACK# <15>

ENBKL <29> EC_TS_RST# <29>

BATT_CHG_LED# < 38>

12

ACIN < 15,23,43> EC_ON < 44>

ON/OFF <38>

LID_SW# <38> SUSP# <10,4 0,45,46,47,49> PCH_HOT# <14>

H_PECI <18,6>

EMC Request

0

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

For DS3

+3VLP

@

12

KB9012A2 work around

R1578

R1578 47K_0402_5%

47K_0402_5%

MAINPWON_ R

1000P_0402_ 50V7K

SYSON

C1272

1

@

2

0.1U_0402_10V6K

USB_ON#

+3VALW

EC_WL_W AKE#

Turbo_V <42>

PROCHOT <42> MAINPWON <42 ,44>

C1277

@C 1277

@

EC_PME#

min

VR695

AD_BID

0 V

0.436 V

0.712 V

R1566

1 2

10K_0402_5%

12

@

R5118

R5118 10K_0402_5%

10K_0402_5%

100K_0402_5 %

1

2

V

AD_BID

0.503 V

0.819 V

+5VALW

+3VALW

12

R1572

R1572 100K_0402_1 %

100K_0402_1 %

@

12

R1634

100K_0402_5 %

WLAN_USB_O N#_R

H_PROCHOT#_EC

+3VALW

R1585

10K_0402_5%

1 2

Q83

2N7002_SOT23

VR_HOT#

0_0402_5% @

VR_HOT#<50>

0419 ESD request to reserve

typ

+3VALW

@

R1641

1 2

R1579 0 _0402_5%@R1579 0_0402_5%@

2N7002H_SOT23 -3

R1588

@R 1588

@

0_0402_5%

R1589

1 3

D

@

G

2

V

max

0.289 V0.250 V0.216 V

0.538 V

0.875 V

12

AD_BID

0 V0 V

R1562

R1562 100K_0402_1 %

100K_0402_1 %

1 2

R1564

R1564 18K_0402_5%

18K_0402_5%

1 2

TP_CLK

TP_DATA

MP PVT DVT EVT

R02

R1567 2.2 K_0402_5%R1567 2.2K_04 02_5%1 2

R1569 2.2 K_0402_5%R1569 2.2K_04 02_5%1 2

@

@1 2

NTC_V_R

C1319 100P_0 402_50V8J

BATT_TEMP

C1265 100P_040 2_50V8JC1265 100P_ 0402_50V8J

ACINPCH_PWR_EN

C1266 100P_040 2_50V8JC1266 100P_ 0402_50V8J

1 2

R1573 4.7K_040 2_5%@R15 73 4.7 K_0402_5%@

1 2

0419 ESD request to reserve

13

D

12

S

Q82

12

+3VALW

2

G

S

1

2

LAN_WAKE# <32>

PCI_PME# <1 7>

C1269

C1269 47P_0402_50 V8J

47P_0402_50 V8J

VSB_PWR_EN

+3VS

100K_0402_5 %

LID_SW#

1000P_0402_ 50V7K

H_PROCHOT# <42,6>

+3VALW

R1642

100K_0402_5 %

R1640

C1274

@C 1274

@

12

R1597

R1597 100K_0402_1 %

100K_0402_1 %

@

12

+3VALW

12

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BIOS & EC I/O Port

LA-8952P

37 55Thursday, January 10, 2013

0.1

TP_CLK<37> TP_DATA<37>

C1302

@C1302

@

100P_0402_50V8J

Power Board

NOVO#<37>

ON/OFF<37>

1

C1303 100P_0402_50V8J

100P_0402_50V8J

2

PSOT24C_SOT23-3

PWR_LED#<37>

LID_SW#< 37>

3

1

NOVO#

ON/OFF

ON/OFFBTN#

J16

1 2

SHORT PADS

@C1303

@

3

D42

@D42

@

1

NOVO_BTN# PWR_LED# LID_SW# ON/OFFBTN#

NOVO_BTN# ON/OFFBTN#

2

D43

@D43

@

PJSOT24C 3P C/A SOT-23

KSI[0..7]

+3VALW

R1592

R1592 100K_0402_5%

100K_0402_5%

1 2

D40

2

1

R1593

R1593 100K_0402_5%

100K_0402_5%

1 2

NOVO_BTN#

ON/OFF

0_0402_5%@

R1600

R1601 0_0402_5%

@

12 12

SMB_DATA_TP

TP_CLK TP_DATA

SMB_CLK_TP

JTP1

ME@

JTP1

ME@

8

GND

7

GND

6

5

4

3

2

1

ACES_88514-00601-071

SP010014M00

1

C1305

C1304

@

2

0.1U_0402_10V6K

3

DAN202UT106_SC70-3

+3VLP

@

R1596

12

0_0402_5%

+3VS

C1301

0.1U_0402_16V4Z

SMB_CLK_S3<12,14,31> SMB_DATA_S3<12,14,31>

2

KSO[0..15]

KSO2 KSO1

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

LED Board

+3VALW

+5VALW

JPWR1

ME@

JPWR1

ME@

8

7

10

7

G2

6

9

6

G1

5

4

3

2

1

ACES_51524-0080N-001

SP01001A900

BATT_LOW_LED#<37> BATT_CHG_LED#<37>

+5VALW

PWR_LED# BATT_LOW_LED# BATT_CHG_LED#

JLED1

ME@

JLED1

ME@

6

8

6

G2

5

7

5

G1

4

3

2

1

ACES_51524-0060N-001

SP010014M10

1 2

C1275 100P_0402_50V8J@C1275 100P_0402_50V8J@

1 2

C1280 100P_0402_50V8J@C1280 100P_0402_50V8J@

1 2

C1281 100P_0402_50V8J@C1281 100P_0402_50V8J@

1 2

C1283 100P_0402_50V8J@C1283 100P_0402_50V8J@

1 2

C1285 100P_0402_50V8J@C1285 100P_0402_50V8J@

1 2

C1287 100P_0402_50V8J@C1287 100P_0402_50V8J@

1 2

C1289 100P_0402_50V8J@C1289 100P_0402_50V8J@

1 2

C1291 100P_0402_50V8J@C1291 100P_0402_50V8J@

1 2

C1293 100P_0402_50V8J@C1293 100P_0402_50V8J@

1 2

C1295 100P_0402_50V8J@C1295 100P_0402_50V8J@

1 2

C1297 100P_0402_50V8J@C1297 100P_0402_50V8J@

1 2

C1299 100P_0402_50V8J@C1299 100P_0402_50V8J@

USB20_P8<17>

USB20_N8<17>

USB20_P9<17>

USB20_N9<17>

KSI[0..7] <37>

KSO[0..15] <37>

R1614

WCM-2012-900T_4P

3

USB20_P8 USB20_P8_R

3

SM070000K00

2

USB20_N8 USB20_N8_R

2

L50

R1615 0_0402_5%@R1615 0_0402_5%@

R1619

1 2

WCM-2012-900T_4P

3

USB20_P9 USB20_P9_R

3

SM070000K00

2

USB20_N9 USB20_N9_R

2

L51

1 2

R1624 0_0402_5%@R1624 0_0402_5%@

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

1 2

@

0_0402_5%

1 2

@

0_0402_5%

1 2

C1279 100P_0402_50V8J@C1279 100P_0402_50V8J@

1 2

C1276 100P_0402_50V8J@C1276 100P_0402_50V8J@

1 2

C1282 100P_0402_50V8J@C1282 100P_0402_50V8J@

1 2

C1284 100P_0402_50V8J@C1284 100P_0402_50V8J@

1 2

C1286 100P_0402_50V8J@C1286 100P_0402_50V8J@

1 2

C1288 100P_0402_50V8J@C1288 100P_0402_50V8J@

1 2

C1290 100P_0402_50V8J@C1290 100P_0402_50V8J@

1 2

C1292 100P_0402_50V8J@C1292 100P_0402_50V8J@

1 2

C1294 100P_0402_50V8J@C1294 100P_0402_50V8J@

1 2

C1296 100P_0402_50V8J@C1296 100P_0402_50V8J@

1 2

C1298 100P_0402_50V8J@C1298 100P_0402_50V8J@

1 2

C1300 100P_0402_50V8J@C1300 100P_0402_50V8J@

C1320

0.1U_0402_16V7K

1 2

0424 EMI reque st to add them

4

1

USB20_P10<17>

USB20_N10<17>

4

1

+USB2_VCCA +3VS

IO Board

DMIC_CLK<36> DMIC_DATA<36>

PLUG_IN#<36> HP_OUTL<36> HP_OUTR<36>

EXT_MIC<36>

1 2

R94 300_0402_5%R94 300_0402_5%

+5VS

CAPS_LED#<37>

2A/Active Low

U55

1 2

4

G547I2P81U_MSOP8

USB20_N10 USB20_N10_R

1

C1307

C1306

@

2

0.1U_0402_10V6K

USB20_P8_R USB20_N8_R

USB20_P9_R USB20_N9_R

USB20_P10_R USB20_N10_R

DMIC_CLK DMIC_DATA

PLUG_IN# HP_OUTL HP_OUTR

EXT_MIC

GND

VOUT

VOUT7VIN VIN3VOUT EN

SM070000K00

R02

FLG

R1625

3

2

R1632 0_0402_5%@R1632 0_0402_5%@

+USB2_VCCA+5VALW

8

6 5

1 2

WCM-2012-900T_4P

3

2

L52

1 2

CAPS_LED#

1

2

@

0_0402_5%

+3VS

+5VS_CAPLED

W=

80mils

C1321

470P_0402_50V7K

4

USB20_P10_RUSB20_P10

4

1

+USB2_VCCA

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6

KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

28

GND1

27

GND2

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JKB1

ACES_88514-02601-071

ME@

USB_OC4# <17>USB_ON#<37,39>

JCR1

ME@

JCR1

ME@

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

GND1 GND2

ACES_88514-02401-071

SP010015W00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

ROM/KBD/PWR/CR/LED/TP Conn.

LA-8952P

38 55Thursday, January 10, 2013

of

0.1

5

D D

4

3

2

1

0424 EMI request to add them

R1605

@R1605

In

tel_PCH_USB2.0

USB20_P 1<17>

C C

B B

23 ESD request t o reserve

04

1000P_0 402_50V7 K

USB_ON#<37,38> USB_OC0# <17>

C1331

@C1331

@

C1308

0.1U_040 2_16V7K

1 2

+5VALW

2A

12

/Active Low

U52

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

FLG

EN

G547I2P 81U_MSOP8

R02

8

6 5

220U_6.3 V_M

+USB3_VCC A

C1311

W=80mils

1

+

2

C1312

1

470P_04 02_50V7K

2

USB20_N1<17>

el_PCH_USB3.0

Int

USB3_RX2 _N<17>

USB3_RX2 _P<17>

USB3_TX2_ N<17 >

USB3_TX2_ P<17>

Place TX AC coup ling Cap (C843~ C850). Close to connector

D44

@

9

U3RXDN2 U3RXDN2

10

8

9

7

U3TXDN2

7

6

U3TXDP2

6 5

YSCLAMP05 24P_SLP2 510P8-10-9

For EMI request

1

2

4

3

8

1

2

U3RXDP2U3RXDP2

4

U3TXDN2

5

U3TXDP2

3

1 2

SM07000 0K00

SM0

70001S0 0

C1309

0.1U_040 2_16V7K

U3TXDN2_L

SM07000 1S00

U3TXDP2_L

C1310

0.1U_040 2_16V7K

U2DP2

@

1 2

0_0402_ 5%

WCM-201 2-900T_4P

1

4

L43

@

1 2

R1608 0 _0402_5%

R1609

1 2

@

0_0402_ 5%

WCM-201 2-900T_4P

1

4

USB3@

L44

1 2

R1612 0_040 2_5% @R1612 0_04 02_5% @

1 2

R1613

0_0402_ 5%

WCM-201 2-900T_4P

1

4

L45

USB3@

1 2

R1616 0_040 2_5% @R1616 0_04 02_5% @

D45

@

3

I/O2

2

GND

1

I/O1

AZC099-04 S.R7G_SOT23 -6

2

3

2

3

2

3

2

U2DP2

3

U2DN2

2

U3RXDN2

3

U3RXDP2

1000P_0 402_50V7 K

@R1 613

@

2

U3TXDN2

0308 Add for ESD request

3

U3TXDP2

6

U2DN2

I/O4

+USB3_VCC A

5

VDD

4

I/O3

+USB3_VCC A

C1225

U3TXDP2

U3TXDN2 U2DP2

1

U2DN2 U3RXDP2

2

U3RXDN2

0113 EMI request

W=80mils

LP2

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND D-2GND

6

GND

SSRX+

4

GND

5

GND

SSRX-

TAITW_PUB AU1-09FNLSCNN 4H0

ME@

10 11 12 13

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

2

Title

USB3.0/Left USB Ports

Size Docum ent Number R ev

Custom

Date: Sheet of

Compal Electronics, Inc.

39 55Thursday, Janu ary 10, 2013

1

39 55Thursday, Janu ary 10, 2013

0.1

A

B

C

D

E

+5VALW TO +5VS

+5VALW

U53

DMN3030LSS-13_SOP8L-8

8 7

SE107475K80

1 1

12

2 2

R1626

R1626 470_0603_5%

470_0603_5%

@

13

D

2

G

Q92

S

2N7002_SOT23

@

SUSP<10,45,46>

3 3

SUSP#<10,37,45,46 ,47,49>

4.7U_0603_6.3V6M

SUSP

+1.5V_IO+1.8VS +0.75VS+1.05VS_VTT

12

13

D

S

R1636

220K_0402_5%

SUSP SYSON#

DTC124EKAT146_SC59-3

12

1

C1313

2

G

+VSB

12

13

D

S

2

R1620

R1620 150K_0402_5%

150K_0402_5%

5VS_GATE

Q88

Q88 2N7002_SOT23

2N7002_SOT23

5

R1622

82K_0402_5%

12

R1628

@

R1637

R1637 100K_0402_5%

100K_0402_5%

OUT

GND

R1628 470_0603_5%

470_0603_5%

@

13

D

S

2

G

Q94

Q94 2N7002_SOT23

2N7002_SOT23

@

SYSON< 37,45,46>

R1627

R1627 470_0603_5%

470_0603_5%

@

2

SYSON# SUSPSUSP

G

Q93

Q93 2N7002_SOT23

2N7002_SOT23

@

+5VALW+RTCBATT +5VALW

12

1 2

Q99

1

2

IN

R1639 100K_0402_5%

100K_0402_5%

3

@R1639

@

+5VS

1 2

4

5VS_GATE_R

36

12

C1322

0.01U_0402_25V7K

1

C1314

C1314 10U_0603_6.3V6M

10U_0603_6.3V6M

2

12

C1315

C1315 1U_0402_6.3V6K

10U

1U_0402_6.3V6K

12

R1629

R1629 22_0603_5%

22_0603_5%

13

D

SUSP

S

2

G

Q95

Q95 2N7002_SOT23

2N7002_SOT23

For Intel S3 Power Reduction.

12

@

R1638

100K_0402_5%

1

Q100

@Q1 00

SYSON

12

@

2

IN

R1594

R1594 10K_0402_5%

10K_0402_5%

0131 Add PD 10K

OUT

GND

3

DTC124EKAT146_SC59-3

12

R1617

R1617 470_0603_5%

470_0603_5%

@

13

D

2

SUSP

G

Q85

S

2N7002_SOT23

@

12

R1630 0_ 0402_5%@ R1630 0_ 0402_5%@

CPU1.5V_S3_GATE <1 0,37>

SE107475K80

4.7U_0603_6.3V6M

SUSP

SUSP#

2N7002_SOT23

C1316

Q98

2

G

1

2

+VSB

12

13

D

2

G

S

+1.5V_IO

1

C1325

4.7U_0603_6.3V6M

2

SE107475K80

+3VALW

12

100K_0402_5%

100K_0402_5% R1633

R1633

13

D

S

+3VALW

R1621

R1621 470K_0402_1%

470K_0402_1%

@

+3VALW TO +3VS

U54

DMN3030LSS-13_SOP8L-8

8 7

5

4

R1623

1 2

R1623 0_0402_5%

0_0402_5%

@

Q89

Q89 2N7002_SOT23

2N7002_SOT23

+1.5V_IO to +1.5VS

Q91

PMV65XP_SOT23-3~D

D

S

D

S

13

G

2

R1635

12

0_0402_5%

1.5VS_GATE

1

2

0.1U_0402_16V4Z

C1328

+3VS

1 2 36

12

C1323

0.01U_0402_25V7K

+1.5VS

1

C1329

0.1U_0402_16V4Z

2

1

C1317

C1317 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C1326

C1326 10U_0603_6.3V6M

10U_0603_6.3V6M

2

10U

12

C1318

C1318 1U_0402_6.3V6K

1U_0402_6.3V6K

12

C1327

C1327 1U_0402_6.3V6K

1U_0402_6.3V6K

12

R1618

R1618 470_0603_5%

470_0603_5%

@

13

D

S

12

R1631

R1631 470_0603_5%

470_0603_5%

@

13

D

Q96

S

2N7002_SOT23

@

2

SUSP

G

Q86

Q86 2N7002_SOT23

2N7002_SOT23

@

2

SUSP

G

PCH_PWR_EN<37 ,42>

SLP_SUS#<15,3 7>

PCH_PWR_EN#

For Deep S3

DS3@

R5534

1 2

0_0402_5%

1 2

0_0402_5%

R5537

@ R5537

@

+3VALW

DS3@

+5VALW

12

1

2

C5529

R5533 47K_0402_5%

100K_0402_5% DS3@

PCH_PWR_EN#

12

@

R5529

100K_0402_5%

DS3@

0.1U_0402_25V6

1 2

R437 0_0805_5%R437 0_0805_5%

DS3@

S

PCH_PWR_EN#

+5VALW

R5545

1 2

13

D

2

G

SB00000EN00

S

2N7002E-T1-E3_SOT23-3

1 2

R435 0_0805_5%R435 0_0805_5%

DS3@

Q5510

Q5510 AO3413_SOT23

AO3413_SOT23

D

S

D

S

13

G

2

DS3@

QH6

AO3413_SOT23

D

13

G

2

DS3@

Q5527

1

2

1

2

DS3@

+3V_PCH

12

@

R5510

C5528

0.1U_0402_10V7K~D

+5V_PCH

20K_0402_5%~D

12

@

RH228

CH57

20K_0402_5%~D

0.1U_0402_10V7K~D

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DC Interface

LA-8952P

E

40 5 5Thursday, January 10, 2013

0.1

5

4

3

2

1

VIN

PL101

JDCIN1

ACES_87302-0401-003

D D

C C

GND

1

2

3

4

5

6

PF101

7A_24VDC_429007.WRML

21

APDIN1APDIN

12

PC101

SMB3025500YA_2P

12

1000P_0402_50V7K

PL101

1 2

100P_0402_50V8J

PC102

12

100P_0402_50V8J

PC103

PC104

1000P_0402_50V7K

+3VLP

JRTC2

- +

MAXEL_ML1220T10@

+CHGRTC

PR132

PR131

560_0603_5%

12

1 2

PR132

560_0603_5%

1 2

PD109

RB751V-40_SOD323-2

12

1 2

PD108

RB751V-40_SOD323-2

+RTCBATT

12

PR127

PR127 0_0402_5%

0_0402_5%

@

RTCVREF

RTC Battery

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR DCIN

Size Document Number Rev

Custom

C38-G series Chief River Schematic

Date: Sheet of

2

Date: Sheet

1

41 55Thursday, January 10, 2013

0.1

of

5

4

3

2

1

JBATT1

VMB2

JBATT1

1

2

3

3 4

D D

C C

5 6

7 GND GND

@

SUYIN_200082GR007G201ZR

JBATT2

1

2

3

4

5

6

7 GND GND

@

SUYIN_200082GR007G201ZR

EC_SMCA

4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

EC_SMDA

12

PR201

100_0402_1%

PR201

100_0402_1%

PR202

100_0402_1%

PR202

100_0402_1%

1 2

PR203

6.49K_0402_1%

1 2

PR204

PR204 10K_0402_5%

10K_0402_5%

PF201

PF201 12A_65V_451012MRL

12A_65V_451012MRL

21

VMB

SMB3025500YA_2P

1 2

12

PC201

PC201 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <37,43>

EC_SMB_DA1 <37,43>

+3VALW

BATT_TEMP <37>

PL201

A/D

BATT+

12

PC202

0.01U_0402_25V7K

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

VL

12

PC203

+3VS

@

PR208

1 2

PQ201

13

D

2

ADP_OCP_1

G

SSM3K7002FU_SC70-3

S

PR212

@PR212

@

1 2

0_0402_5%

PU201

1

VCC

2

GND

3

OT1

4

OTP_N_003

@

PR213 0_0402_5%

OT2

G718TM1U_SOT23-8@

100K_0402_1%

H_PROCHOT#<37,6>

PROCHOT<37>

0.1U_0603_16V7K

TMSNS1

RHYST1

TMSNS2

RHYST2

12

8

7

OTP_N_002

6

5

ADP_OCP_2

5.11K_0402_1%

MAINPWON <37,44>

65W(UMA) : PR205=1.65K(SD034165180)

For KB930 --> Keep PU201 circuit (Vth = 1.25V)

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212

NTC_V_2

12

@

PR231

0_0402_5%

@PR230

@

47K_0402_1%

@PR233

@

47K_0402_1%

+EC_VCCA

12

PR206

12.7K_0402_1%

+3VLP

PR230

12

PR233

12

PR209

@PR209

@

10K_0402_1%

12

PH201

@PR235

@

1 2

@

PR234

PR234 0_0402_5%

0_0402_5%

1 2

100K_0402_1%_NCP15WF104F03RC

+3VALW

12

@

12

PR235 0_0402_5%

0_0402_5%

ADP_I<37,43>

PR210

@PR210

@

1 2

PR205

1.65K_0402_1%

Turbo_V_2

PR227

@PR227

@

0_0402_5%

PR232

@

0_0402_5%

1 2

12

Turbo_V

PR211

1 2

10K_0402_1%

<37>

PR207

21.5K_0402_1%

ECAGND

<37>

B B

VMB2

PR217

PR217 887K_0402_1%

887K_0402_1%

PR219

10K_0402_1%

1 2

PR221

PR221 180K_0402_1%

180K_0402_1%

1 2

A A

5

12

3

2

P2

PC204

0.01U_0402_25V7K

8

P

+

-

G

4

PR223

PR223 10K_0402_1%

10K_0402_1%

PR225

PR225 10K_0402_1%

10K_0402_1%

@

PR218

10M_0402_5%

1 2

1

O

PU202A

LM393DG_SO8

12

2VREF_8205

12

RTCVREF

BATT_LEN#<37>

PR214

PR214 100K_0402_1%

100K_0402_1%

1 2

PR226

100K_0402_1%

+3VLP

1 2

+3VALW+3VLP

1 2

13

2

G

2

G

PR215

PR215 100K_0402_1%

100K_0402_1%

PQ202

D

2N7002KW_SOT323-3

S

PQ203

13

D

2N7002KW_SOT323-3

S

4

PCH_PWR_EN<37,40>

VSB_PWR_EN<37>

BATT_OUT <37,43>

SPOK<44>

PQ205

TP0610K-T1-E3_SOT23-3

B+

VL

PR222

@PR222

@

100K_0402_1%

PR229

@PR229

@

0_0402_5%

@PR228

@

0_0402_5%

1 2

PR236 0_0402_5%@PR236 0_0402_5%@

PR228

PR224

1 2

1K_0402_5%

1 2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

22K_0402_1%

13

D

2

G

2N7002W-T/R7_SOT323-3

G

2N7002W-T/R7_SOT323-3

S

PC207

1U_0402_6.3V6K

2010/01/25 2012/07/11

PR220

1 2

PQ204

12

PC205

PR216

100K_0402_1%

0.22U_0603_25V7K

Compal Secret Data

Deciphered Date

13

12

2

+VSBP

PC206

0.1U_0603_25V7K

+VSBP

NTC_V

PJ201

PJ201 JUMP_43X39@

JUMP_43X39@

2

112

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

C38-G series Chief River Schematic

Date: Sheet of

+VSB

42 55Thursday, January 10, 2013

1

42 55Thursday, January 10, 2013

0.1

5

1 2 36

13

P2

12

PC301

0.1U_0603_25V7K

PQ307B

5

ACPRN <43>

12

PR303

200K_0402_1%

P2-1

12

PR308

150K_0402_1%

P2-2

34

2N7002KDW-2N_SOT363-6

PR335

47K_0402_1%

PQ302

AO4423_SO8

1 2 3 6

4

5600P_0402_25V7K

12

PR307

PR307 20K_0402_1%

20K_0402_1%

PQ308

13

D

2N7002KW_S OT323-3

2

G

S

PR314

PR317

1 2

60.4K_0603_1%

EC_SMB_DA1<37,42>

EC_SMB_CK1<37,42>

BQ24727VDD

12

PQ316

2

G

1 2

12

13

PQ301

PQ301 AO4407A_SO8

AO4407A_SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ307A

PACIN

PQ311

DTC115EUA_SC70-3

PR321

1 2

10K_0402_5%

PR325

@PR3 25

@

0_0402_5%

CHGVADJ

0V

1.882V

3.2935V

8 7

5

PQ304

2

1 3

PQ305

DTC115EUA_SC70-3

PR318

47K_0402_1%

1 2

2

ACOFF-1

12

PQ313

13

D

2

G

S

4

2N7002KW_SOT323-3

VIN

D D

C C

B B

12

PR301

61

2

2N7002KDW -2N_SOT363-6

PACIN

ACON

ACOFF<37>

BATT_OUT

CH

GVADJ=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

A A

8 7

5

PC304

BATT_OUT <37,42,43>

VIN

PR315

390K_0603_1%

PC370

0.1U_0603_25V7K

+3VALW

PR336

PR336 10K_0402_1%

10K_0402_1%

D

S

2N7002KW_SOT323-3

4

P3

2.2K_0402_5%

@

+3VALW

PR316

1 2

2.2K_0402_5%

@

1 2

316K_0402_1%

PR337

10K_0402_1%

1 2

PACIN

12

PR339

12K_0402_1%

1 2

ADP_I<37,42>

100P_0603_50V8

PR323

PC312

1 2

ACPRN<43>

39.2K_0402_1%

10

12

PR302

0.01_1206_1%

1

2

ACP

PR309

@

PR312

@PR3 12

@

6

7

8

9

PR326

PR326 100K_0402_1%

100K_0402_1%

1 2 1 2

12

4.7M_0603_1%

5

ACOK

ACDET

IOUT

SDA

BQ24727RGRR_VQFN20_ 3P5X3P5

SA000051W00

SCL

ILIM

11

6.8_0603_5%

0.1U_0603_25V7K

ACIN <15,23,37>

B+

4

3

+3VALW

PR310

100K_0402_1%

PR313

4

CMPIN

PU301

SRN12BM

12

PR327

PC373

12

PC374

0.1U_0603_25V7K

ACN

PC308

1 2

12

0.1U_0603_25V7K

10K_0603_1%

@

3

CMPOUT

SRP

12 13

PR328

10_0603_5%

12

PC310

2

14

ACP

GND

3

SH00000Q100

1 2

PL301

1 2

PC302

10U_0805_25V6K@

PC309

12

0.1U_0603_25V7K

21

TP

20

VCC

19

18

17

BTST

16

REGN

12

@

PC375

0.1U_0603_25V7K

PL301

BST_CHG

PD303

RB751V-40_SOD323-2

12

PC376

PC376 1U_0603_25V6K

1U_0603_25V6K

1UH_MNR-4018-1R0N -F_3A_30%

0.1U_0603_25V7K

12

1

ACN

PHASE

HIDRV

LODRV

15

1 2

P2

PR319

10_1206_5%

BQ24727VCC

DH_CHG

12

DL_CHG

PC315

10U_0805_25V6K@

1 2

PC313

1 2

1U_0603_25V6K

2.2_0603_5%

1 2

PR324

1 2

PC303

LX_CHG

0.047U_0603_16V7M

BQ24727VDD

4.7U_0805_25V6-K

PC314

2

CHG_B+

PQ303

AO4407A_SO8

1 2 3 6

PL302

PD301

ACOFF-1

1 2

1SS355_SOD323-2

1 2

CHGCHG

4

PD302

PD302 1SS355_SOD323-2

1SS355_SOD323-2

0.01_1206_1%

1

2

SRP

DISCHG_G

PC307

1 2

PC305

4.7U_0805_25V6-K

12

PC307

1 2

PC306

2200P_0402_50V7K

4.7U_0805_25V6-K

6

578

4

123

6

578

4

123

PR304

200K_0402_1%

1 2

PR305

PR305 47K_0402_1%

47K_0402_1%

1 2

DISCHG_G-1

PQ306

13

DTC115EUA_SC70-3

2

PQ310

AO4466L_SO8

10UH_PCMB063T-100MS _4A_20%

1 2

12

PQ312

PR322

4.7_1206_5%

AO4466L_SO8

4.7_1206_5%

6251_SN

12

PC377

680P_0603_50V7K

PC311

PR320

1 2

12

0.1U_0603_25V7K

1

8 7

5

PR306

PR306 200K_0402_1%

200K_0402_1%

PQ309

2N7002W- T/R7_SOT323-3

13

D

2

G

S

4

3

SRN

VIN

PACIN

PC371

BATT+

12

PC372

10U_0805_25V6K

For disable pre- charge circuit.

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2012/07/112010/01/13

2

Title

Size D ocument Number Rev

Date: Sheet of

Compal Electronics, Inc.

CHARGER

C38-G series Chief River Schematic

43 55Thurs day, January 10, 2013

1

0.1

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALW P +3VALW

D D

PR401

13K_040 2_1%

1 2

PR403

RT8205_B+

PJ401

B+

PC405

C C

B B

A A

PJ401

2

112

JUMP_43 X118@

12

PC402

0.1U_0603_25V7K

PC402

PC403

PC404

0.1U_0603_25V7K

PC404

4.7U_0805_25V6-K

+3VALWP

EC_ON<37>

MAINPWON<37,42>

PR418

2.2K_040 2_5%

PR413

1 2

0_0402_ 5%

@

5

12

PC406

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

1

+

PC415

PC415 150U_B2 _6.3VM_R45M

150U_B2 _6.3VM_R45M

2

2N7002K DW-2N_SOT3 63-6

VL

AO4466L _SO8

PL401

1 2

PQ405A

12

@

PQ401

PR409

4.7_1206_5%

PC418

680P_0603_50V7K

61

100K_04 02_1%

PR417

40.2K_0402_1%

6

578

4

123

PR414

PC423

578

PQ403

PQ403 AO4712_ SO8

AO4712_ SO8

3 6

241

12

13

2

4.7U_0603_6.3V6M

4

12

2

12

Typ: 175mA

PC411

34

PQ405B

PQ405B 2N7002K DW-2N_SOT3 63-6

2N7002K DW-2N_SOT3 63-6

5

PQ406

PQ406 DTC115E UA_SC70-3

DTC115E UA_SC70-3

+3VLP

12

4.7U_0805_10V6K

PR407

1 2

2.2_0603 _5%

PC412

0.1U_060 3_25V7K

PR411

499K_04 02_1%

1 2

B+

ENTRIP2ENTRIP1

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR412

100K_0402_1%

Issued Date

12

PR403

20K_040 2_1%

1 2

PR405

130K_04 02_1%

1 2

25

7

8

9

BST_3V

10

UG_3V

11

LX_3V

12

LG_3V

12

PC420

1U_0603_10V6K

2VREF_8205

PU401

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

3

12

PC401

1U_0603_10V6K

PR402

30K_040 2_1%

1 2

PR404

19.6K_04 02_1%

1 2

PR406

66.5K_04 02_1%

ENTRIP2

6

3

4

5

FB2

TONSEL

ENTRIP2

VFB=2.0V

SKIPSEL

EN

14

15

13

RT8205_ B+

2010/01/ 25 2012/07/ 11

12

1 2

ENTRIP1

1

2

FB1

REF

ENTRIP1

24

VO1

23

PGOOD

22

BOOT1

21

UGATE1

20

PHASE1

19

LGATE1

RT8205E GQW_W QFN24_4X4

NC18VREG5

VIN16GND

17

12

PC422

0.1U_0603_25V7K

Compal Secret Data

VL

Typ: 175mA

PC421

4.7U_0805_10V6K

Deciphered Date

BST_5V

UG_5V

LX_5V

LG_5V

PC407

4.7U_0805_25V6-K

PR408

2.2_0603 _5%

1 2

RT8205_ B+

12

PC408

4.7U_0805_25V6-K

SPOK <42>

PC413

0.1U_060 3_25V7K

1 2

2

+5VALW P +5VALW

12

PC410

PC409

0.1U_0603_25V7K

2200P_0402_50V7K

Title

Size Do cument Number Rev

Custom

Date: Sheet of

678

PQ402

35241

5

PQ404MDS1521URH_SO8 PQ404MDS1521URH_SO8

4

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

Compal Electronics, Inc.

3VALWP/5VALWP

C38-G series Chief River Schematic

PJ402

2

112

JUMP_43 X118@

PJ403

2

112

JUMP_43 X118

@

MDS1525URH_SO8

PL402

12

PR410

12

PC419

PL402

1 2

4.7_1206_5%

680P_0603_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

786

123

+5VALWP

1

+

PC417

PC417 150U_B2 _6.3VM_R45M

150U_B2 _6.3VM_R45M

2

0.1

44 55Thursd ay, January 10, 2013

1

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

S4/S5

1 1

HiLo

Lo Lo

Note: S3 - sleep ; S5 - power off

On

Off

On

Off (Hi-Z)

Off Off

+0.75VSP

12

PC506

PC504

10U_0805_25V6K

+VTT_REFP

+1.5VP

12

PC507

0.033U_0402_16V7K

PQ501

@

2

G

0.033U_0402_16V7K

PR504

1 2

0.1U_0402_16V7K

13

D

S

2 2

PR503

49.9K_0402_5%

SUSP#

1 2

SYSON<37,40,46>

12

PC512

0.1U_0402_16V6K

2N7002KW_S OT323-3

SUSP<10,40,46>

21

1

2

3

4

5

0_0402_5%@

PC508

@PC5 08

@

5.76K_0402_1%

PU501

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

12

PR508

B

+1.5VP

PJ5025

@PJ5025

@

1

JUMP_43X39

1

2

BST_1.5V BST_1.5V-1

18

19

VLDOIN

S3

7

S3_1.5V

17

BOOT

UGATE

S5

TON

8

9

S5_1.5V

PR510

5.9K_0402_1%

20

VTT

RT8207MZQW _WQFN20_3X3

FB

6

FB=0.75V

12

To GND = 1.5V To VDD = 1.8V

PR507

2.2_0603_5%

1 2

16

PHASE LGATE

PGND

CS

VDDP

VDD

PGOOD

10

PR501

887K_0402_1%

12

UG_1.5V

LX_1.5V

15

14

8.66K_0402_1%

13

12

11

+3VALW

12

@

12

1.05VS_B+

PR505

PC503

PR509

PGOOD_1.5V

10K_0402_5%

0.1U_0603_25V7K

LG_1.5V

12

1U_0603_10V6K

PC502

1 2

12

1U_0603_10V6K

PR502

5.1_0603_5%

PC511

4

12

5

PQ503

TPCA8065-H_PPAK56-8 -5

123

5

PQ502

123

+5VALW

C

1UH_PCMC063T-1R0M N_11A_20%

12

PR506

@PR506

@

4.7_1206_5%

12

PC510

@PC510

@

680P_0402_50V7K

TPCA8057-H_PPAK56-8-5

12

PC509

1 2

4.7U_0805_25V6-K

1.05VS_B+

12

PC501

PL502

1.05VS_B+

4.7U_0805_25V6-K

JUMP_43X118

+1.5VP

@PJ501

@

112

PJ501

2

1

+

2

PC505

PC505 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

PJ505

2

JUMP_43X118@

PJ506

JUMP_43X118@

B+

112

D

+1.5VP

112

+1.5V_IO

+1.5V

3 3

PJ507

2

112

JUMP_43X39

PU502 SY 8033BDBC_DFN10_3X3PU502 SY8033BDBC_DFN10_3X3

PJ504

+3VALW

2

112

JUMP_43X118@

SUSP#<10,37,40,45,46,47,49>

4 4

A

1.8VSP_VIN

12

PC513

PC513 22U_0805_6.3VAM

22U_0805_6.3VAM

1 2

PR513

0_0402_5%

@

EN_1.8VSP

PR514

PR514 1M_0402_5%

1M_0402_5%

@PC518

@

12

PC518

1 2

4

10

PVIN

9

PVIN

8

SVIN

5

EN

0.1U_0402_10V7K

2

1.8VSP_LX

LX

PG

3

LX

6

FB

FB=0.6Volt

TP

NC

7

1

11

12

PC532

@ PC532

@

0.1U_0402_10V7K

Security Classifi cation

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

PL501

1UH_PH041H-1R0MS_3. 8A_20%

1 2

12

PR512

20K_0402_1%

PR511

4.7_1206_5%

12

PC515

680P_0603_50V7K

1.8VSP_FB

PR515

10K_0402_1%

Issued Date

PC517

22U_0805_6.3VAM

Deciphered Date

C

+1.8VSP

12

PC514

68P_0402_50V8J

12

2010/01/25 2012/07/11

12

PC516

22U_0805_6.3VAM

Compal Secret Data

JUMP_43X39

@

1.8VSP max current=4A

Compal Electronics, Inc.

Title

PWR-+1.5VP/+1.8VSP

Size D ocument Number Rev

Custom

C38-G series Chief River Schematic

Date: Sheet of

+0.75VS+0.75VSP

PJ503

2

112

JUMP_43X118@

D

+1.8VS+1.8VSP

0.1

45 55Thursday, January 10, 2013

0.1

A

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

Hi Hi

S3

S4/S5

1 1

HiLo

Lo Lo

Note: S3 - sleep ; S5 - power off

On

Off

On

Off (Hi-Z)

Off Off

+0.75VSP_DDR3L

12

PC522

PC523

10U_0805_25V6K

@

+VTT_REFP_DDR3L

12

+1.5VP_DDR3L

PC526

0.033U_0402_16V7K

2 2

PR521

49.9K_0402_5%@

SUSP#

1 2

SYSON<37,40,45>

12

PC529

1U_0402_16V6K

2N7002KW_S OT323-3

@

SUSP<10,40,45>

3 3

DDR3L_EN#<18,37>

0.033U_0402_16V7K

@

@PR5 22

@

0_0402_5%

1 2

0.1U_0402_16V7K

13

D

S

1 2

0_0402_5%

PR527

@

0.1U_0402_16V7K

2N7002KW_S OT323-3

PQ506

2

G

@

DDR3L_EN#=high => 1.5V DDR3L_EN#=low => 1.35V

PR522

49.9K_0402_1%

PC531

PC530

@

21

1

2

3

4

5

PQ507

12

PU503

PAD

VTTGND

VTTSNS

GND

VTTREF

VDDQ

@

12

@

PR525

2

G

@

B

+1.5VP_DDR3L

PJ508

@ PJ508

@

1

JUMP_43X39

1

2

BST_1.5V_DDR3L BST_1.5V-1_DDR 3L

18

20

19

VTT

BOOT

VLDOIN

RT8207MZQW _WQFN20_3X3

FB

S5

S3

6

8

7

S3_1.5V_DDR3L

S5_1.5V_DDR3L

PR524

10K_0402_1%

@

12

PR526

12.7K_0402_1%

@

13

D

S

LX_1.5V_DDR3L

PR516

2.2_0603_5%

1 2

@

16

17

PHASE

UGATE

LGATE

PGND

CS

VDDP

VDD

PGOOD

TON

9

10

PR523

887K_0402_1%

12

@

FB=0.75V To GND = 1.5V To VDD = 1.8V

UG_1.5V_DDR3L

15

14

PR518

11K_0402_1%

13

12

11

+3VALW

12

PR520

@

12

1.5V_B+_DDR3L

PC521

0.1U_0603_25V7K

1 2

LG_1.5V_DDR3L

12

@

12

PC527

1U_0603_10V6K

PGOOD_1.5V_DDR3L

@

10K_0402_5%

@

1U_0603_10V6K

PR519

5.1_0603_5%

@

PC528

5

4

5

4

@

12

C

PQ504

TPCA8065-H_PPAK56-8 -5

123

PQ505

123

TPCA8057-H_PPAK56-8-5

+5VALW

12

PR517

4.7_1206_5%

12

@

PC525

680P_0402_50V7K

@

1.5V_B+_DDR3L

12

PC519

PC520

4.7U_0805_25V6-K

@

PL1

1UH_PCMC063T-1R0M N_11A_20%

PL1

1 2

+1.5VP_DDR3L

PJ509

@ PJ509

@

112

JUMP_43X118

2

1

+

2

@

2

B+

PC524

PC524 330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

PJ510

112

JUMP_43X118@

PJ511

112

JUMP_43X118@

PJ512

2

112

JUMP_43X39

@

D

+1.5VP_DDR3L

+1.5V

+0.75VS+0.75VSP_DDR3L

4 4

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

PWR-+1.5VP/+1.8VSP

Size D ocument Number Rev

Custom

C38-G series Chief River Schematic

Date: Sheet of

D

46 55Thursday, January 10, 2013

0.1

5

D D

PR709

60.4K_04 02_1%

+V1.05S_ VCCP_PWRG OOD<48>

PC716

0.1U_0402_25V6

60.4K_04 02_1%

1 2

10.7K_0402_1%

12

PR720

1 2

10_0402 _1%

12

PR710

10K_0402_1%@

1 2

PR715

1 2

PC717

1 2

12K_0402_1%

1 2

PC717

0.01UF_0 402_25V7K

PR719

@

1 2

10_0402 _5%

PC722

PC722 1000P_0 402_50V7K

1000P_0 402_50V7K

PR716

SUSP#<10,37,40,45,46,49>

C C

VSSIO_SEN SE_L<9>

B B

PR718

@

1 2

0_0402_ 5%

VCCIO_SEN SE<9 >

PC710

.1U_0402_16V7K

PR713

1 2

0_0402_ 5%

@

0.01UF_0 402_25V7K

PC723

PC723 1000P_0 402_50V7K

1000P_0 402_50V7K

1 2

4

+3VS

17

PU702

1

VREF

2

REFIN

TPS5121 9RTER_QFN16_ 3X3

3

GSNS

4

VSNS

PC720

1 2

PR722

1 2

10_0402 _1%

PR711

100K_0402_1%

PR712

1 2

16

15

PAD

COMP5TRIP6GND

MODE

PGOOD

12

75K_0402_1%

PR721

100K_0402_1%

14

EN

7

BST_1.05 VS_VCCP

13

BST

12

SW

11

DH

10

DL

9

V5

PGND

8

PR714

2.2_0603 _5%

1 2

3

0.1U_060 3_25V7K

LX_1.05V S_VCCP

DH_1.05V S_VCCP

DL_1.05V S_VCCP

PC713

1 2

12

+5VALW

PC721

1U_0603 _10V6K

PQ703

TPCA8065-H_PPAK56-8-5

PQ704

2

1

+1.05VS_VCCPP OCP(min)=20.75A

1.05VS_B +

PC714

12

5

4

123

5

4

TPCA8057-H_PPAK56-8-5

12

123

12

PC714

PC711

0.1U_0402_25V6

2200P_0402_50V7K

PL2

1UH_PCM C063T-1R0MN_1 1A_20%

PR717

4.7_1206_5%

PC719

1000P_0603_50V7K

PL2

1 2

12

PC712

PC715

4.7U_0805_25V6-K

PC718

330U_X_2VM_R9M

PJ705

2

112

JUMP_43 X118@

JUMP_43 X118@ PJ706

PJ706

2

112

JUMP_43 X118@

1

+

2

1.05VS_B+

+1.05VS_VTTP

+1.05VS_ VTT+1.05VS_ VTTP

A A

Security Class ification

2010/01/ 25 2012/07/ 11

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/01/ 25 2012/07/ 11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR +1.05VS_VCCPP/

Size Do cument Number Rev

Custom

C38-G series Chief River Schematic

Date: Sheet of

2

Date: Sheet of

47 55Thursd ay, January 10, 2013

1

0.1

5

VID [0] VID[1] VCCSA Vout 0 0 0.9V 0 1 0.85V 1 0 0.775V 1 1 0.75V

output voltage adjustable network

D D

2

1

PC614

PC613

1 2

2

2200P_0402_50V7K

0.1U_0603_25V7K

0.1U_0603_25V7K 10U_0805_6.3V6M

PJ601

+3VALW

C C

2

112

JUMP_43X118@

+VCCSA_PWR_SRC

10U_0805_6.3V6M

2

PC615

PC616

1

10U_0805_6.3V6M

2.2U_0603_10V7K

+VCCSA_PWR_SRC

4

PC602

1 2

PC617

0.22U_0402_10V6K

SA_PGOOD<37>

+5VALW

12

3300P_0402_50V7K

PR604

10_0402_1%

19

20

21

22

23

24

PC618

PU601

12

PGND

VIN

12

18

1

5.1K_0402_1%

+3VS

12

PR602

100K_0402_5%

+VCCSA_PWRGD

PC601

1 2

1U_0603_10V6K

16

17

V5FILT

V5DRV

PGOOD

TPS51463RGER_QFN24_4X4

COMP

GND

VREF

3

2

12

PR610

PC619

0.01U_0402_25V7K

3

PR601

1K_0402_5%

12

H_VCCSA_VID1 <10>

PR603

1K_0402_5%

12

+VCCSA_VID0

+VCCSA_VID1

15

VID1

SLEW

4

1 2

+VCCSA_EN

13

14

EN

VID0

12

BST

11

SW

10

SW

9

SW

8

SW

7

SW

25

TP

VOUT

MODE

5

6

+VCCSA_BT

+VCCSA_PHASE

PR608

@ PR608

@

33K_0402_5%

1 2

12

1

2

PR605

1 2

0_0402_5%

@

PR606

PR606 0_0603_5%

0_0603_5%

H_VCCSA_VID0 <10>

PC620

@

0.033U_0402_16V7K

+VCCSA_BT_1

12

PR607

4.7_1206_5%

12

PC604

1000P_0603_50V7K

+V1.05S_VCCP_PWRGOOD <47>

PC603

0.22U_0603_16V7K

1 2

12

PR612

0_0402_5%@

+VCC_SAP TD Peak Current 6A OCP current 7.2A

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

PL601

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

C 4.2A

PC605

2

+VCCSAP

2

PJ602

JUMP_43X118@

1

112

+VCCSA

+VCCSAP

@

12

PC606

1 2

PC607

0.1U_0402_10V7K

22U_0805_6.3V6M

0.1U_0402_10V7K

PR609

100_0402_5%

PR611

1 2

0_0402_5%

@

22U_0805_6.3V6M

PC609

PC608

1 2

22U_0805_6.3V6M

12

1 2

22U_0805_6.3V6M

@

12

PC610

2200P_0402_50V7K

+VCCSA_SENSE <10>

@

PC612

PC611

1 2

22U_0805_6.3V6M

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

2010/01/25 2012/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PWR +VCCSAP

Size Document Number Rev

C

C38-G series Chief River Schematic

Date: Sheet

1

48 55Thursday, January 10, 2013

of

0.1

A

+VGA_COREP

1 1

PR802

PR802 0_0402_5%

0_0402_5%

@

1 2

PC806

12

10P_0402_25V8J

1 2

10P_0402_25V8J

1 2

10.7K_0402_1%

PR807

10.7K_0402_1%

1 2

1 2 12

6.04K_0402_1%

PR810

93.1K_0402_1%

+3VS

12

PR811

PC818

0.1U_0402_16V7K

10P_0402_25V8J

PC801

10K_0402_1%

VRON_VGA

21

PU801

1

GSNS

2

V3

3

V2

4

V1

5

V0

PR824

PR825

0_0402_5%

@

PAD

TPS51518RUKR_QFN20_3X3

VREF

6

12

0_0402_5%@

PR801

1 2

PR804

12

100K_0402_1%

PR805

PR809

PR812

0_0402_5%

12

PR822

PR822 10K_0402_5%

10K_0402_5%

1 2

PR823

PR823 10K_0402_5%

10K_0402_5%

1 2

PR809

12

GPU_VID0

GPU_VID1

1 2

2 2

@

PR814

PR814 0_0402_5%@

0_0402_5%@

1 2

GPU_VID0

GPU_VID1

@

GPU_VID0<23>

GPU_VID1<23>

PR815

0_0402_5%

@

VGA_PWRGD<18,22>

3 3

+3VS

SUSP#<10,37,40,45,46,47>

@

@ PR820

@

PR820 10k_0402_5%

10k_0402_5%

1 2

PR821

PR821 10k_0402_5%

10k_0402_5%

1 2

PXS_PWREN

PXS_PWREN<17,24,49>

PR803

73.2K_0402_1%

1 2

PC807

19

20

4700P_0402_25V7K

VSNS

SLEW

VID08PGOOD

7

PC817

0.1U_0402_10V7K

12

PXS_PWREN<17,24,49>

18

TRIP

VID19EN

17

GND

10

PXS_PWREN

DRVL

DRVH

16

MODE

15

V5IN

14

13

12

SW

11

BST

B

PR808

2.2_0603_5%

GPU_VID1

1

0

PD801

@ PD801

@

RB751V-40_SOD323-2

1 2

PR816

40.2K_0402_1%

12

PC808

1U_0603_10V6K

12

GPU_VID0

1

0

1

0

@

+5VALW

UGATE2_VGA

0.1U_0603_25V7K

1 2

BOOT2_2_VGABOOT2_VGA

LGATE2_VGA

Core Voltage Level

12

PR818

PC822

20K_0402_1%

0.1U_0603_25V7K

Sey

0.9V

1.0V

1.1V

1.15V

PC816

mour XT

12

PU802

7

POK

8

EN

+5VALW

PC819

PC819 1U_0402_6.3V6K

1U_0402_6.3V6K

6

VOUT

VCNTL

VOUT

GND

APL5912-KAC-TRL_SO8

1

C

PJ801

@ PJ801

@

VGA_CORE_B+

12

PC803

5

4

PQ801

123

TPCA8065-H_SOP-ADV8-5

4

PQ802

123 5

TPCA8057-H 1N PPAK56-8

PC803

PC802

0.1U_0402_25V6

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

4.7_1206_5%

12

680P_0603_50V7K

2200P_0402_50V7K

PL801

1 2

PR806

PC815

PC804

4.7U_0805_25V6-K

+VGA_COREP +VGA_CORE

+1.5V_IO

@

1

PJ804

1

JUMP_43X79

2

12

PC820

4.7U_0805_6.3V6K

5

VIN

4

3

2

FB

9

VIN

4.7U_0805_6.3V6K

PR817

1.15K_0402_1%

PR819

4.53K_0402_1%

12

0.01U_0402_25V7K

+VGA_PCIEP +1.0VGS

+VGA_PCIEP

12

PC823

22U_0603_6.3V6K

PC821

2

JUMP_43X118

PC805

4.7U_0805_25V6-K

1

+

2

+

PC809

2

330U_D2_2.5VM_R9M

+VGA_COREP Iocp=32.5A

2

1

+

PC810

2

330U_D2_2.5VM_R9M

@

PJ802

2

JUMP_43X118@

PJ803

2

JUMP_43X118@

PJ805

JUMP_43X79

@

PR819 4.53K

112

PC811

330U_D2_2.5VM_R9M

112

1.0VVGA_PCIE

B+

1

PC812

2

10U_0603_6.3V6M

1.1 V

1

PC814

PC813

2

10U_0603_6.3V6M

3K

D

+VGA_COREP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/10/12 2013/10/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR-VGA_CORE/VGA_PCIE

Size Document Number Rev

Date: Sheet

Date: Sheet of

D

of

49 55Thursday, January 10, 2013

0.1

5

4

3

2

B+

PL901

HCB4532KF-800T90_1812

1 2

1

CPU_B+

12

PR911 1.91K_0402_1% PR911 1.91K_0402_1%

PWMG2

37

36

35

COMPG

PGOODG

15

12

68P_0402_50V8J

137K_0402_1%

PR905

12

PR910

154K_0402_1%

330P_0402_50V7K

PR912

@PR912

@

0_0402_5%

1 2

34

31

33

32

PWM2G

BOOT1G

LGATE1G

PHASE1G

UGATE1G

BOOT2 UGATE2 PHASE2

LGATE2

VCCP

VDD

PWM3

LGATE1 PHASE1 UGATE1

COMP

PGOOD19ISUMN

RTN16ISEN1

BOOT1

ISL95836HRTZ-T_TQFN40_5X5~D

18

20

PR933 1.91K_0402_1%

PC907

12

PC909

150P_0402_50V8J

12

PR907

2K_0402_1%

PC914

+5VS

LGATE1G

PHASE1G

UGATE1G

BOOT1G

30 29 28 27 26 25 24 23 22 21

12

PR939

475_0402_1%

1 2

1000P_0402_50V7K

0.01UF_0402_25V7K

470P_0402_50V7K

12

2.74K_0402_1%

12

Shortpad

+3VS

12

PC934

+VGFX_CORE

PR902

@

475_0402_1%

1 2

PC913

0.047U_0402_16V8J

ISEN2G

NTCG SCLK

ALERT#

SDA

12

PR930

27.4K_0402_1%

+5VS

12

PR931

470K_0402_5%_ TSM0B474J470 2RE

3.83K_0402_1%

PC930

@PC930

@

10P_0402_50V8J

PC939

@PC939

@

330P_0402_50V7K

12

PC940

0.01UF_0402_25V7K

@

10_0402_1%

PR904

1 2 3 4 5 6 7 8 9

10

41

1 2

D D

PH901

10K_0402_1%_ERTJ0EG103FA

VSUMG-

12

1 2

PC910

PR908

0.1U_0402_16V7K

2.61K_0402_1%

VSUMG+

C C

PR917

27.4K_0402_1%

PR920

3.83K_0402_1%

1 2

VR_SVID_CLK<9>

VR_SVID_ALRT#<9>

VR_SVID_DAT<9>

VR_HOT#<37>

VR_ON<37>

PC923

@PC923

@

47P_0402_50V8J

+1.05VS_VTT

B B

A A

470P_0402_50V7K

12

1 2

PR922 0_0402_5%@ PR922 0_0402_5%@

1 2

PR924 0_0402_5%@ PR924 0_0402_5%@

PR934

2K_0402_1%

499_0402_1%

PR942

PR941

12

+5VS

12

PH902470K_0402_5%_ TSM0B474J4702RE

1 2

PR923 0_0402_5%@ PR923 0_0402_5%@

1 2

PR925 0_0402_5%@ PR925 0_0402_5%@

12

PC929

12

PC933

470P_0402_50V7K

12

1.91K_0402_1%

+CPU_CORE

VCCSENSE<9>

VSSSENSE<9>

PR926

PR927

@

0_0402_5%

1 2

12

PC924

@PC924

@

0.1U_0402_16V7K

PR943

137K_0402_1%

PR946

@PR946

@

10_0402_1%

PR947

@PR947

@

10_0402_1%

PR909

1 2

11K_0402_1%

1 2

0_0402_5%@

PR921

1 2

PR928

@

1 2

75_0402_5%

130_0402_1%

PR935

42.2K_0402_1%

PC935

68P_0402_50V8J

12

PC937

150P_0402_50V8J

12

PC912

PC918

1 2

@

0.1U_0603_25V7K

0.022U_0402_16V7K

PR929

12

54.9_0402_1%

PH903

12

VCC_AXG_SENSE<10> VSS_AXG_SENSE<10>

PU901

ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC

TP

PR932 0_0402_5%@ PR932 0_0402_5%@

12

PR901 10_0402_1%@PR901 10_0402_1%@

12

+3VS

39

38

40

FBG

RTNG

ISUMNG

ISEN212FB17ISUMP14ISEN3/FB2

11

13

PC902

@PC902

@

PC906

PC908

12

PR906

@PR918

@

0_0603_5%

LGATE1

PHASE1

UGATE1

BOOT1

VGATE <15>

PC932

0.1U_0603_16V7K

0.047U_0402_16V8J

PR903

499_0402_1%

12

+5VS

PR918

1 2

12

1 2

12

PHASE1G

12

PR919

1_0603_5%

12

PC922

1U_0603_10V6K

VSUM+

12

PR936

12

2.61K_0402_1%

PH904

PR940 11K_0402_1% PR940 11K_0402_1%

10K_0402_1%_ERTJ0EG103FA

VSUM-

Close Phase 1 choke

12

PC938

0.1U_0402_16V7K

BOOT1G

12

UGATE1G

PC921

1U_0603_10V6K

PC919

0.22U_0603_16V7K

1 2 12

PR916

2.2_0603_5%

UGATE1

PHASE1

BOOT1

PQ901

LGATE1G

PR937

2.2_0603_5%

5

4

5

PQ902

4

PQ903

12

1 2

PC931

0.22U_0603_16V7K

Rds(on) typ=2.6m Ω max=3.2m Ω

123

@

4

CPU_B+

MDU1516URH_POWERDFN56-8-5

Rds(on) typ=2.6m Ω max=3.2m Ω

MDU1511RH_POWERDFN56-8-5

CPU_B+

5

123

PQ906

4

LGATE1

1

+

PC904

PC903

2

15U_D2_25VM_R90

33U_D2_25VM_R60

+VGFX_CORE:

12

PC911

PC915

@

10U_0805_25V6K

12

PC917

PC916

@

10U_0805_25V6K

PC920

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

12

680P_0402_50V7K

2

PR913

4.7_1206_5%

PR914

1 2

3.65K_0603_1%

VSUMG+

VID1=1.23V IccMax=33A Icc_TDC=21.5A Icc_Dyn=20.2A OCP~40A

PL902

4

3

For ULV 17W 1+1 CP

U_CORE LL= -2.9mΩ, GFX_CORE LL= -3.9mΩ, L DCR=1.1mΩ

5

PQ904

4

MDU1516URH_POWERDFN56-8-5

5

MDU1516URH_POWERDFN56-8-5

123

5

PQ905

4

123

MDU1511RH_POWERDFN56-8-5

LGATE1

12

PC925

10U_0805_25V6K

123

MDU1511RH_POWERDFN56-8-5

12

PC926

10U_0805_25V6K

PC936

680P_0402_50V7K

PC928

PC927

10U_0805_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

12

PR938

4.7_1206_5%

12

PR944

3.65K_0603_1%

1 2

VSUM+

PU_CORE:

+C

VID1=0.9V IccMax=33A Icc_TDC=25A Icc_Dyn=28A OCP~40A

10U_0805_25V6K

PL903

1

+

PC905

PC901

2

15U_D2_25VM_R90

33U_D2_25VM_R60

@

+VGFX_CORE

12

PR915

1_0402_5%

VSUMG-

12

4

+CPU_CORE

3

12

PR945

PR945 1_0402_5%

1_0402_5%

VSUM-

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/12/01 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

2

Date: Sheet

PWR-CPU_CORE

C38-G series Chief River Schematic

1

0.1

of

50 55Thursday, January 10, 2013

5

+VGFX_CORE

12

D D

1

+

PC255

C C

2

PC230

PC231

1U_0402_6.3V6K

12

PC242

PC247

10U_0603_6.3V6M

1

+

PC256

2

330U_D2_2V_Y

12

PC233

PC232

1U_0402_6.3V6K

12

PC243

1U_0402_6.3V6K

12

PC244

10U_0603_6.3V6M

1

PC241

2

22U_0805_6.3V6M

4

12

PC235

PC234

1U_0402_6.3V6K

12

PC245

PC246

10U_0603_6.3V6M

1

PC261

PC259

2

22U_0805_6.3V6M

PC261

PC260

2

22U_0805_6.3V6M

12

PC363

PC364

PC365

PC366

1U_0402_6.3V6K

1

PC358

PC262

2

22U_0805_6.3V6M

PC366

1U_0402_6.3V6K

3

+CPU_CORE

PC225

2.2U_0402_6.3V6M

PC225

2.2U_0402_6.3V6M

12

2

2.2U_0402_6.3V6M

PC229

2.2U_0402_6.3V6M

PC229

PC227

2.2U_0402_6.3V6M

PC227

2.2U_0402_6.3V6M

PC226

2.2U_0402_6.3V6M

PC226

2.2U_0402_6.3V6M

12

2.2U_0402_6.3V6M

PC228

2.2U_0402_6.3V6M

PC228

2.2U_0402_6.3V6M

12

2.2U_0402_6.3V6M

PC275

2.2U_0402_6.3V6M

PC275

2.2U_0402_6.3V6M

12

1

PC317

PC319

2.2U_0402_6.3V6M

PC319

2.2U_0402_6.3V6M

12

PC320

For BOT side

PC367

1U_0402_6.3V6K

+CPU_CORE

PC236

2.2U_0402_6.3V6M

PC236

2.2U_0402_6.3V6M

12

PC249

22U_0805_6.3V6M

PC249

22U_0805_6.3V6M

1

2

PC237

2.2U_0402_6.3V6M

PC237

2.2U_0402_6.3V6M

12

PC250

22U_0805_6.3V6M

PC250

22U_0805_6.3V6M

1

2

PC238

2.2U_0402_6.3V6M

PC238

2.2U_0402_6.3V6M

12

22U_0805_6.3V6M

PC251

22U_0805_6.3V6M

PC251

22U_0805_6.3V6M

1

2

2.2U_0402_6.3V6M

PC239

2.2U_0402_6.3V6M

PC239

2.2U_0402_6.3V6M

12

PC252

PC253

22U_0805_6.3V6M

PC253

22U_0805_6.3V6M

1

2

PC316

2.2U_0402_6.3V6M

PC316

2.2U_0402_6.3V6M

PC240

12

PC254

22U_0805_6.3V6M

PC254

22U_0805_6.3V6M

1

2

2.2U_0402_6.3V6M

PC318

2.2U_0402_6.3V6M

PC318

2.2U_0402_6.3V6M

12

@

PC258

22U_0805_6.3V6M@PC258

22U_0805_6.3V6M

For TOP side

22U_0805_6.3V6M

PC265

22U_0805_6.3V6M

PC265

22U_0805_6.3V6M

1

2

1

2

22U_0805_6.3V6M

1

2

PC269

22U_0805_6.3V6M

PC269

22U_0805_6.3V6M

PC268

1

2

PC267

22U_0805_6.3V6M

PC267

22U_0805_6.3V6M

PC266

22U_0805_6.3V6M

PC266

@

PC270

22U_0805_6.3V6M

PC270

22U_0805_6.3V6M

PC264

22U_0805_6.3V6M@PC264

22U_0805_6.3V6M

1

2

+1.05VS_VTT

12

PC353

PC352

1U_0402_6.3V6K

12

B B

A A

12

PC324

PC326

1U_0402_6.3V6K

12

PC334

PC351

1U_0402_6.3V6K

12

PC323

PC322

1U_0402_6.3V6K

5

12

PC333

PC332

1U_0402_6.3V6K

12

1U_0402_6.3V6K

PC332

1U_0402_6.3V6K

12

PC289

PC321

1U_0402_6.3V6K

12

PC330

PC331

1U_0402_6.3V6K

12

PC288

PC287

1U_0402_6.3V6K

12

PC248

PC263

10U_0603_6.3V6M

12

PC328

PC329

1U_0402_6.3V6K

12

PC286

PC285

1U_0402_6.3V6K

12

PC283

PC279

10U_0603_6.3V6M

12

PC276

PC277

10U_0603_6.3V6M

4

12

PC327

PC354

PC356

1U_0402_6.3V6K

12

PC284

1U_0402_6.3V6K

12

PC282

10U_0603_6.3V6M

12

1

+

PC278

2

10U_0603_6.3V6M

PC356

1U_0402_6.3V6K

12

PC355

PC357

1U_0402_6.3V6K

12

PC281

PC280

10U_0603_6.3V6M

PC291

330U_D2_2V_Y

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/24 2012/07/12

3

+CPU_CORE

1

+

PC271

PC271 330U_D2_2V_Y

330U_D2_2V_Y

2

Compal Secret Data

Deciphered Date

1

+

PC272

PC272 330U_D2_2V_Y

330U_D2_2V_Y

2

1

+

PC273

PC273 330U_D2_2V_Y

330U_D2_2V_Y

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU_CORE_CAP

51 55Thursday, January 10, 2013

1

0.1

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for changePG#Modify List Date PhaseItem

1

Reserve support DDR3L circuit P46 For Coustom request 2012.1.19 EVT

2

D D

co-lay 1.8VSP for SY8033 and SY8035 P45 2012.2.24 DVT

3

Remove PX_mode signal P49 For HW request 2012.3.12 DVT

Change PR503 form 0ohm to 49.9Kohm.

4

Change PC512 from 1U to 0.1U.

P45 For S3 resum will shutdown issue. 2012.3.12 DVT

Change PR805 form 11.8Kohm to 10.7Kohm. Change PR807 from 5.11K to 10.7K.

5

Change PR809 from 7.68K to 6.04K.

P49 For AMD request to adjust VGA_CORE voltage. 2012.3.12 DVT

Change PR810 from 97.6K to 93.1K.

6

Add Batt_out to KB9012 pin66 For Battery learning reserve.P43 2012.3.12 DVT

7

Remove DDR3L circurt. P46 For reserve circuit. 2012.5.28 SVT

C C

9

10

11

12

13

14

B B

15

16

17

A A

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

2009/01/06 2012/07/11

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

52 55Thursday, January 10, 2013

1

0.1

5

4

COMPAL CONFIDENTIAL

3

2

1

MODEL NAME: PCB NAME:

D D

REVISION: DATE:

AC MOD

BATT MOD

C C

A1

VIN

E

BATT

B1

V

PU301

V

Power Sequence Block Diagram LA-7981P

2011/07/13

A2

PU401

V

B+

B2

B+

V

B

4

A3

B5

+3VALW

+5VALW

A5

V

B7 3

V

PQ2

EC

VV

A5

ON/

B7

A4

B6

V

OFF

B3

51ON#

EC_ON

10

PCH_PWROK

+3V_PCH

3

V

PCH_RSMRST#_R

PBTN_OUT#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_SUS#

V

SYSON

SUSP#,SUSP

+5V_PCH

4

5

6

7 SYSON#

8

V V

+1.5V

V

PU501

3

V

PCH

10

PCH_PWROK

V

PM_

DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

SYS_PWROK

11

12

16

DGPU_PWR_EN

15

V

CP

V

DGPU_PWROK

14

VGATE

D

13

U

SVI

PU601

B B

V

+VCC_SA

PU702

V

+V1.05S

PU602

V

+V1.05S_VCCP

U38

V

+5VS

U39

V

+3VS

Q8

VV

+1.5VS

IS)

(D

8a

(DIS)

8b

V

DGPU

PU701 +0.75VS

13 SVID

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Power sequence

LA-8951P

1.0

53 55Thursday, January 10, 2013

1

53 55Thursday, January 10, 2013

1.0

PU901 +VCC_CORE

V

3

8a

2011/06/15 2012/07/11

SA_PGOOD

14

VGATE

9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

VR_ON

A A

5

4

5

4

3

2

Version change list (P.I.R. List) Page 1 for HW PIR

Reason for change PG# Modify List Date PhaseItem

1

Initial：co-lay JLVDS2 (40pin) from LA-8951PR30

D D

1

For touch screen function

2

3

For touch screen function

P.29 adding JLVDS2、R721 2013/01/07

P.17 P.29

adding nets EC_TS_RST#、TS_RST#、USB20_P3、USB20_N3

2013/01/07

EVT

P.37

4

5

6

7

8

C C

9

10

11

12

13

14

15

B B

16

17

18

19

20

21

22

23

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW-PIR1

LA-8952P

1

54 55Thursday, January 10, 2013

0.1

Compal LA-8952P VIUS3, IdeaPad S300, IdeaPad S400, LA-8952P VIUS4 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual