Compal LA-8712P QCL51 AMD, ENVY M6 Schematic
A
1 1
B
C
D
E
Compal Confidential
2 2
QCL51 Schematics Document
AMD Comal Platform
AMD Trinity APU / Hudson FCH / ATI Chelsea Pro M2
Muxless/UMA / PX 4.0 / PX 5.0
3 3
2011-10-26
LA-8712P REV: 0.1
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
0.1
0.1
1 56Monday, November 28, 2011
1 56Monday, November 28, 2011
1 56Monday, November 28, 2011
0.1
A
B
C
D
E
Compal Confidential
Model Name : QCL51 AMD
Board Name : LA-8712P
1 1
Thermal Sensor
ADM1032
page 14
HDMI Conn.
LVDS Conn.
2 2
CRT Conn.
USB 2.0 Port 8
MINI Card 1
(Wireless LAN with BT)
3 3
LED
page 39
ATI Chelsea Pro M2
uFCBGA-962
page 23
page 22
page 24
64M x16
128M x 16
VRAM DDR3
1 CH
page 32
SD slot
page 19, 20
DDR3
Page 13~18
1 CH
LVDS
Translator
ANX3112
page 21
GPP0GPP1
Card Reader/Gbe Lan
Realtek RTL8411
page 31
Transformer / RJ45
APU HDMI
(UMA / Muxless)
page 31
page 31
AMD Comal
Gen2GFX x 16
DP2
DP0
P_GPP x 3
GEN1
ENE
KBC932
AMD FS1R2 APU
Trinity
uPGA-722 Package
DP1
DP x 4
(DP1 TXP/N 0~4)
ML for FCH VGA
Page 6~10
FCH
Hudson-M3
uFCBGA-656
Page 25~29
LPC BUS
HD Audio
page 37
UMI
HDA Codec
IDT 92HD91
Memory BUS(DDR3/DDR3L)
Dual Channel
1.5V DDRIII 1333/1600MHz
Daughter board
USB
SATA
SATA HDD
page 30
page 33
USB20
Sub/B*1
USB Charger
page 40 page 22
Port 0
port 0
SATA ODD
Daughter board
USB30
Sub*1
Repeater
page 40
Gen2 3Gb/sGen3 6Gb/s
port 1
page 30
USB 3.0 Port 2
USB 2.0 Port 12
SPK
page 36
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
CMOS
Camera
Port 5
page 39
Page 11,12
USB30
M/B*2
page 41
USB 3.0 Port 0,1
USB 2.0 Port 10,11
Port 1
FP
RTC CKT.
page 25
Power On/Off CKT.
page 38
Fan Control
4 4
page 30
Daughter board
Power/B with LED
page 38
Touch Pad Int.KBD
Daughter board
FAN/LED
page 39
page 38page 39
HP Amp
Combo
page 36
jack
Sub Woofer
page 34page 35
Amp
Sub Woofer
page 34
BIOS ROM
SYS BIOS (4M)
EC BIOS (256K)
page 26
page 38
DC/DC
Interface CKT.
Power Circuit
page 42
page 44~56
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
0.1
0.1
2 56Monday, November 28, 2011
2 56Monday, November 28, 2011
2 56Monday, November 28, 2011
E
0.1
5
4
3
2
1
CLOCK DISTRIBUTION
D D
B_SODIMM
A_SODIMM
DISPLAY OUTPUT
AMD
DDRA_CLK1P/N
DDRB_CLK0P/N
DDRB_CLK1P/N
1066~1866MHz
C C
AMD
CPU FS1 SOCKET
DDRA_CLK0P/N
1066~1866MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
100MHz
DP0_AUX
LVDS Transtator
ATI VGA
Chelsea Pro
AMD
FCH
Hudson-M2/M3
Internal CLK GEN
32.768KHz 25MHz
X1X5
CLK_PEG_VGAP/N
100MHz
GPP_CLK
100MHz
LVDS CONN
APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_LVDS_CLK/DATA
LVDS_OUT
RTD2132
DP_IN
C
DP0_TXP/N0
DP0_AUXP/N
B B
WLAN
Mini PCI Socket
GPP2 GPP3
GbE LAN/
Card reader
APU
DP1 DPA
DP0
PCIE_GFX[0:15]
DP2
C
DPFDPE
VGA
PCIE_GFX[0:15]
DAC1
25MHz
YL1
FCH
CRT CONN
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
3
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
HDMI CONN
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
CLOCK / DISPLAY DISTRIBUTION
CLOCK / DISPLAY DISTRIBUTION
CLOCK / DISPLAY DISTRIBUTION
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
3 56Monday, November 28, 2011
3 56Monday, November 28, 2011
3 56Monday, November 28, 2011
0.1
0.1
0.1
A
B
C
D
ZZZ1
ZZZ1
E
Voltage Rails
Power Plane Description
VIN
B+
+APU_CORE
+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
1 1
+VGA_CORE OFFOFFON0.95-1.2V switched power rail
+VDDCI OFF0.95-1.2V switched power rail ON OFF
+0.75VS ONON OFF0.75V switched power rail for DDR terminator
+0.935VGS ON OFF OFF0.935V switched power rail for VGA
+1.1ALW 1.1V switched power rail for FCH ON ON*ON
+1.1VS
+1.2VS ON OFF OFF
+1.5V ON
+1.5V_PCIE
+1.8VGS OFFON OFF1.8V switched power rail
+2.5VS
+3VALW
+LAN_VDD_3V3 ON ON ON
+3VS
+5VALW
+5VS
2 2
+VSB ON ON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for APU
1.5V power rail for CPU VDDIO and DDR
1.5V switched power rail
2.5V for CPU_VDDA
3.3V always on power rail
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF OFF1.1V switched power rail for FCH
ON OFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
ON
ON*
OFF
OFFON
ONON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
LOW
LOW LOW
LOW
100K +/- 5%Ra/Rb
Ra / Rb V min
AD_BID
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
BOM Option Table
BOM
Structure
PX@ PX function
Description
0 V
HIGH
LOW
ON
ON
ON
HIGHHIGHHIGH
HIGH
HIGH
LOW
V typ
AD_BID
ON
ON
ON
ON
OFF
ON
OFF
V
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
BOM Config
UMA PX
V
ON ON
ON
OFF
OFF
OFF
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
max
PCB
PCB
Part Number = DA80000SH00
Part Number = DA80000SH00
PCB 0OH LA-8712P REV0 M/B
PCB 0OH LA-8712P REV0 M/B
LOW
OFF
OFF
OFF
BOARD ID Table
Board ID
0
DB
1
2
3
4
5
6
7
PCB Revision
x = 1 is read cmd, x= 0 is writee cmd.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
3 3
EC SM Bus1 address EC SM Bus2 address
Device Address HEX
Smart Battery
0001 011X b
FCH (S0)
SM Bus 0 address
4 4
Device Address Device Address
DDR DIMM1
DDR DIMM2
Amplifier
1010 000X b
1010 001X b
A
Device Address HEX
16H
ADI ADM1032 (GPU)
SB-TSI (APU)
LVDS TR
VGA Internal Thermal
1001 101X b
1001 100X b
1010 100X b
1000 001X b
FCH (S0~S5)
SM Bus 1 address
HEX
Touch pad
A0
A2
9AH
98H
A8H
82H
HEX
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
0.1
0.1
4 56Monday, November 28, 2011
4 56Monday, November 28, 2011
4 56Monday, November 28, 2011
0.1
5
4
3
2
1
BATTERY
12.6V
AC ADAPTOR
D D
19V 90W
C C
BATT+
V
IN
PU101
CHARGER
BQ24738ARGRR
PU2000
ISL6277HRTZ-T
PU501
RT8207MZQW
PU701
B+
RT8237EZQW
PU900
ADP3211MNR2G
PU801
SY8809DFC
PU301
RT8205LZQW
+3VS
+INVPWR_B+
LCD panel
15.6"
B+ 300mA
+3.3 350mA
B B
FAN Control
APL5607
+5VS
+5VS 500mA
U54
+USB3_VCCA
USB3.0 X2
+5V
Dual+1
2.5A
A A
AP2301MPG
+USB_BS
USB3.0 X1
USB2.0 X1
+5V
Dual+1
2.5A
U61
TPS2540RTER
SATA
HDD*1
ODD*1
+5V 3A
Audio Codec
IDT 92HD91
+5V 45mA
+3.3VS 25mA
+APU_CORE
+APU_CORE_NB
+1.5V
+0.75VS
+1.2VS
+VGA_CORE
+1.1VALW
+3VALW
+5VALW
U38
SI4800
EC
ENE KB932
+3.3VALW 30mA
+3.3VS 3mA
PU1000
SY8033BDBC
+5VS
+5VALW
+3VS
+3VALW
LAN /Card reader
RTL8411
+3.3VALW 201mA
PU1501
SY8036DBC
+VDDCI
+1.5V_PCIE
+1.5VS_WLAN
Mini Card
WLAN
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
RM13
PU702
APL5508
U40
SI4800
+3VS
+2.5VS
PU935
SY8809DFC
UV19
AO4430L
PU401
SY8033BDBC
QV16
AP2301GN
JUMP @
U39
AO4430L
+0.935VGS
+1.5VGS
+1.8VGS
+3VSG
+1.1VS
RTC
Bettary
+APU_CORE
+APU_CORE_NB
+2.5VS
+1.5V
+1.2VS
+1.5V
+0.75VS
+VGA_CORE
+VDDCI
+0.935VGS
+1.5VGS
+1.8VGS
+3VSG
+1.1VS
+1.1VALW
+3VS
+3VALW
AMD APU FS1R2
0.7~1.475V
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
VDD CORE 60A
VDDNB 44A
VDDA 0.5A
VDDIO 3.2A
VDDR 8.5A
RAM DDRIII SODIMMX2
VGA ATI
Chelsea Pro
VDD_MEM 4A
VTT_MEM 0.5A
VDDC 28A
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 100 mA
PCIE_VDDC: 1100 mA
DP[A:E]_VDD10: 880 mA
VDDR1: 1200 mA
PLL_PVDD: 75 mA
TSVDD: 5 mA
AVDD: 70 mA
VDD1DI: 45 mA
VDD_CT: 17mA
PCIE_VDDR: 440 mA
DP[A:F]_VDD18: 990 mA
SPV18: 50mA
MPV18: 150mA
VDDR3: 60 mA
+1.5V
+0.75VS
0.85~1.1V
0.9~1.0V
+0.935VGS
+1.5VGS
+1.8VGS
+3VGS
FCH AMD Hudson M3
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
+1.1VS
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 42 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
+1.1VALW
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
VDDCR_11_GBE_S:63mA
VDDIO_33_PCIGP: 102 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 12 mA
VDDAN_33_DAC: 30 mA
+3VS
VDDPL_33_PCIE: 11 mA
VDDPL_33_SATA: 12 mA
VDDPL_33_USB_S: 14 mA
VDDPL_33_SSUSB_S: 11 mA
VDDIO_AZ_S: 26 mA
VDDAN_33_USB_S: 470 mA
VDDIO_33_S: 59 mA
+3VALW
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_GEB_S: 145mA
VDDIO_33_GBE_S: 2mA
VDDIO_33_GBE_S
GND
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDBT_RTC_GRTC BAT
VRAM 512/1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VGS 2.4 A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
POWER DELIVERY CHART
POWER DELIVERY CHART
POWER DELIVERY CHART
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
5 56Monday, November 28, 2011
5 56Monday, November 28, 2011
5 56Monday, November 28, 2011
0.1
0.1
0.1
A
PCIE_GTX_C_FRX_P[0..15]13 PCIE_FTX_C_GRX_P[0..15] 13
PCIE_GTX_C_FRX_N[0..15]13
1 1
GPU
2 2
GLAN/Card reader
WLAN
UMI
3 3
PCIE_DTX_C_FRX_P031
PCIE_DTX_C_FRX_N031
PCIE_DTX_C_FRX_P132
PCIE_DTX_C_FRX_N132
UMI_MTX_C_FRX_P025
UMI_MTX_C_FRX_N025
UMI_MTX_C_FRX_P125
UMI_MTX_C_FRX_N125
UMI_MTX_C_FRX_P225
UMI_MTX_C_FRX_N225
UMI_MTX_C_FRX_P325
UMI_MTX_C_FRX_N325
+1.2VS
P_ZVDDP W/S=8/12 mil, <3000mil
L
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
PCIE_GTX_C_FRX_P8
PCIE_GTX_C_FRX_N8
PCIE_GTX_C_FRX_P9
PCIE_GTX_C_FRX_N9
PCIE_GTX_C_FRX_P10
PCIE_GTX_C_FRX_N10
PCIE_GTX_C_FRX_P11
PCIE_GTX_C_FRX_N11
PCIE_GTX_C_FRX_P12
PCIE_GTX_C_FRX_N12
PCIE_GTX_C_FRX_P13
PCIE_GTX_C_FRX_N13
PCIE_GTX_C_FRX_P14
PCIE_GTX_C_FRX_N14
PCIE_GTX_C_FRX_P15
PCIE_GTX_C_FRX_N15
1 2
R539 196_0402_1%R539 196_0402_1%
B
P_ZVDDP
JCPU1A
JCPU1A
AB8
P_GFX_RXP0
AB7
P_GFX_RXN0
AA9
P_GFX_RXP1
AA8
P_GFX_RXN1
AA5
P_GFX_RXP2
AA6
P_GFX_RXN2
Y8
P_GFX_RXP3
Y7
P_GFX_RXN3
W9
P_GFX_RXP4
W8
P_GFX_RXN4
W5
P_GFX_RXP5
W6
P_GFX_RXN5
V8
P_GFX_RXP6
V7
P_GFX_RXN6
U9
P_GFX_RXP7
U8
P_GFX_RXN7
U5
P_GFX_RXP8
U6
P_GFX_RXN8
T8
P_GFX_RXP9
T7
P_GFX_RXN9
R9
P_GFX_RXP10
R8
P_GFX_RXN10
R5
P_GFX_RXP11
R6
P_GFX_RXN11
P8
P_GFX_RXP12
P7
P_GFX_RXN12
N9
P_GFX_RXP13
N8
P_GFX_RXN13
N5
P_GFX_RXP14
N6
P_GFX_RXN14
M8
P_GFX_RXP15
M7
P_GFX_RXN15
AE5
P_GPP_RXP0
AE6
P_GPP_RXN0
AD8
P_GPP_RXP1
AD7
P_GPP_RXN1
AC9
P_GPP_RXP2
AC8
P_GPP_RXN2
AC5
P_GPP_RXP3
AC6
P_GPP_RXN3
AG8
P_UMI_RXP0
AG9
P_UMI_RXN0
AG6
P_UMI_RXP1
AG5
P_UMI_RXN1
AF7
P_UMI_RXP2
AF8
P_UMI_RXN2
AE8
P_UMI_RXP3
AE9
P_UMI_RXN3
AG11
P_ZVDDP
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
PCI EXPRESS
PCI EXPRESS
GRAPHICS
GRAPHICS
GPPUMI
GPPUMI
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
C
AB2
PCIE_FTX_GRX_P0 PCIE_FTX_C_GRX_P0
AB1
PCIE_FTX_GRX_N0 PCIE_FTX_C_GRX_N0
AA3
PCIE_FTX_GRX_P1 PCIE_FTX_C_GRX_P1
AA2
PCIE_FTX_GRX_N1 PCIE_FTX_C_GRX_N1
Y5
PCIE_FTX_GRX_P2
Y4
PCIE_FTX_GRX_N2 PCIE_FTX_C_GRX_N2
Y2
PCIE_FTX_GRX_P3
Y1
PCIE_FTX_GRX_N3 PCIE_FTX_C_GRX_N3
W3
PCIE_FTX_GRX_P4 PCIE_FTX_C_GRX_P4
W2
PCIE_FTX_GRX_N4 PCIE_FTX_C_GRX_N4
V5
PCIE_FTX_GRX_P5 PCIE_FTX_C_GRX_P5
V4
PCIE_FTX_GRX_N5 PCIE_FTX_C_GRX_N5
V2
PCIE_FTX_GRX_P6 PCIE_FTX_C_GRX_P6
V1
PCIE_FTX_GRX_N6 PCIE_FTX_C_GRX_N6
U3
PCIE_FTX_GRX_P7 PCIE_FTX_C_GRX_P7
U2
PCIE_FTX_GRX_N7 PCIE_FTX_C_GRX_N7
T5
PCIE_FTX_GRX_P8 PCIE_FTX_C_GRX_P8
T4
PCIE_FTX_GRX_N8 PCIE_FTX_C_GRX_N8
T2
PCIE_FTX_GRX_P9 PCIE_FTX_C_GRX_P9
T1
PCIE_FTX_GRX_N9 PCIE_FTX_C_GRX_N9
R3
PCIE_FTX_GRX_P10 PCIE_FTX_C_GRX_P10
R2
PCIE_FTX_GRX_N10 PCIE_FTX_C_GRX_N10
P5
PCIE_FTX_GRX_P11 PCIE_FTX_C_GRX_P11
P4
PCIE_FTX_GRX_N11 PCIE_FTX_C_GRX_N11
P2
PCIE_FTX_GRX_P12 PCIE_FTX_C_GRX_P12
P1
PCIE_FTX_GRX_N12 PCIE_FTX_C_GRX_N12
N3
PCIE_FTX_GRX_P13 PCIE_FTX_C_GRX_P13
N2
PCIE_FTX_GRX_N13 PCIE_FTX_C_GRX_N13
M5
PCIE_FTX_GRX_P14 PCIE_FTX_C_GRX_P14
M4
PCIE_FTX_GRX_N14 PCIE_FTX_C_GRX_N14
M2
PCIE_FTX_GRX_P15 PCIE_FTX_C_GRX_P15
M1
PCIE_FTX_GRX_N15 PCIE_FTX_C_GRX_N15
AD5
PCIE_FTX_DRX_P0
AD4
PCIE_FTX_DRX_N0
AD2
PCIE_FTX_DRX_P1
AD1
PCIE_FTX_DRX_N1
AC3
AC2
AB5
AB4
AG2
UMI_FTX_MRX_P0
AG3
UMI_FTX_MRX_N0
AF4
UMI_FTX_MRX_P1
AF5
UMI_FTX_MRX_N1
AF1
UMI_FTX_MRX_P2
AF2
UMI_FTX_MRX_N2
AE2
UMI_FTX_MRX_P3
AE3
UMI_FTX_MRX_N3
AH11
P_ZVSS
R540 196_0402_1%R540 196_0402_1%
L
C917 .1U_0402_16V7KPX@C917 .1U_0402_16V7KPX@
C918 .1U_0402_16V7KPX@C918 .1U_0402_16V7KPX@
C919 .1U_0402_16V7KPX@C919 .1U_0402_16V7KPX@
C920 .1U_0402_16V7KPX@C920 .1U_0402_16V7KPX@
C921 .1U_0402_16V7KPX@C921 .1U_0402_16V7KPX@
C922 .1U_0402_16V7KPX@C922 .1U_0402_16V7KPX@
C923 .1U_0402_16V7KPX@C923 .1U_0402_16V7KPX@
C924 .1U_0402_16V7KPX@C924 .1U_0402_16V7KPX@
C925 .1U_0402_16V7KPX@C925 .1U_0402_16V7KPX@
C926 .1U_0402_16V7KPX@C926 .1U_0402_16V7KPX@
C927 .1U_0402_16V7KPX@C927 .1U_0402_16V7KPX@
C928 .1U_0402_16V7KPX@C928 .1U_0402_16V7KPX@
C929 .1U_0402_16V7KPX@C929 .1U_0402_16V7KPX@
C930 .1U_0402_16V7KPX@C930 .1U_0402_16V7KPX@
C931 .1U_0402_16V7KPX@C931 .1U_0402_16V7KPX@
C932 .1U_0402_16V7KPX@C932 .1U_0402_16V7KPX@
C933 .1U_0402_16V7KPX@C933 .1U_0402_16V7KPX@
C934 .1U_0402_16V7KPX@C934 .1U_0402_16V7KPX@
C936 .1U_0402_16V7KPX@C936 .1U_0402_16V7KPX@
C937 .1U_0402_16V7KPX@C937 .1U_0402_16V7KPX@
C938 .1U_0402_16V7KPX@C938 .1U_0402_16V7KPX@
C939 .1U_0402_16V7KPX@C939 .1U_0402_16V7KPX@
C940 .1U_0402_16V7KPX@C940 .1U_0402_16V7KPX@
C941 .1U_0402_16V7KPX@C941 .1U_0402_16V7KPX@
C942 .1U_0402_16V7KPX@C942 .1U_0402_16V7KPX@
C943 .1U_0402_16V7KPX@C943 .1U_0402_16V7KPX@
C944 .1U_0402_16V7KPX@C944 .1U_0402_16V7KPX@
C945 .1U_0402_16V7KPX@C945 .1U_0402_16V7KPX@
C946 .1U_0402_16V7KPX@C946 .1U_0402_16V7KPX@
C947 .1U_0402_16V7KPX@C947 .1U_0402_16V7KPX@
C948 .1U_0402_16V7KPX@C948 .1U_0402_16V7KPX@
C949 .1U_0402_16V7KPX@C949 .1U_0402_16V7KPX@
1 2
P_ZVSS W/S=8/12 mil, <3000mil
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C950 .1U_0402_16V7KC950 .1U _0402_16V7K
1 2
C951 .1U_0402_16V7KC951 .1U _0402_16V7K
1 2
C952 .1U_0402_16V7KC952 .1U _0402_16V7K
1 2
C953 .1U_0402_16V7KC953 .1U _0402_16V7K
1 2
C956 .1U_0402_16V7KC956 .1U _0402_16V7K
1 2
C957 .1U_0402_16V7KC957 .1U _0402_16V7K
1 2
C958 .1U_0402_16V7KC958 .1U _0402_16V7K
1 2
C959 .1U_0402_16V7KC959 .1U _0402_16V7K
1 2
C960 .1U_0402_16V7KC960 .1U _0402_16V7K
1 2
C961 .1U_0402_16V7KC961 .1U _0402_16V7K
1 2
C962 .1U_0402_16V7KC962 .1U _0402_16V7K
1 2
C963 .1U_0402_16V7KC963 .1U _0402_16V7K
D
PCIE_FTX_C_GRX_N[0..15] 1 3
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_DRX_P0 31
PCIE_FTX_C_DRX_N0 31
PCIE_FTX_C_DRX_P1 32
PCIE_FTX_C_DRX_N1 32
UMI_FTX_C_MRX_P0 25
UMI_FTX_C_MRX_N0 25
UMI_FTX_C_MRX_P1 25
UMI_FTX_C_MRX_N1 25
UMI_FTX_C_MRX_P2 25
UMI_FTX_C_MRX_N2 25
UMI_FTX_C_MRX_P3 25
UMI_FTX_C_MRX_N3 25
E
GPU
GLAN/Card reader
WLAN
UMI
4 4
Security Classification
Security Classification
Security Classification
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/07/08 2015/07/08
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AMD FS1R2 PCIE / GFX / UMI
AMD FS1R2 PCIE / GFX / UMI
AMD FS1R2 PCIE / GFX / UMI
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
0.1
0.1
0.1
6 56Monday, November 28, 2011
6 56Monday, November 28, 2011
6 56Monday, November 28, 2011
E
A
1 1
JCPU1B
JCPU1B
MEMORY CHANNEL A
DDRA_SMA[15..0]11
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11
DDRA_SDM[7..0]11
2 2
DDRA_SDQS011
DDRA_SDQS0#11
DDRA_SDQS111
DDRA_SDQS1#11
DDRA_SDQS211
DDRA_SDQS2#11
DDRA_SDQS311
DDRA_SDQS3#11
DDRA_SDQS411
DDRA_SDQS4#11
DDRA_SDQS511
DDRA_SDQS5#11
DDRA_SDQS611
DDRA_SDQS6#11
DDRA_SDQS711
DDRA_SDQS7#11
DDRA_CLK011
DDRA_CLK0#11
DDRA_CLK111
DDRA_CLK1#11
DDRA_CKE011
DDRA_CKE111
DDRA_ODT011
DDRA_ODT111
3 3
DDRA_SCS0#11
DDRA_SCS1#11
DDRA_SRAS#11
DDRA_SCAS#11
DDRA_SWE#11
MEM_MA_RST#11
MEM_MA_EVENT#11
+MEM_VREF
+1.5V
M_ZVDDIO W/S=8/12 mil, <1000mil
L
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE0
DDRA_CKE1
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
MEM_MA_RST#
MEM_MA_EVENT#
1 2
R541 39.2_0402_1%R541 39.2_0402_1%
M_ZVDDIO
AA25
AD27
AC23
AD19
AC15
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15
AA27
AA26
W24
W23
W20
W21
U20
R20
R21
P22
P21
N24
N23
N20
N21
M21
U23
M22
U24
U21
E14
E21
F25
G14
H14
G18
H18
H21
E27
E26
T21
T22
R23
R24
H28
H27
Y25
V22
V21
H25
T24
L24
L21
L20
L23
J17
J21
MEMORY CHANNEL A
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CKE0
MA_CKE1
MA_ODT0
MA_ODT1
MA_CS_L0
MA_CS_L1
MA_RAS_L
MA_CAS_L
MA_WE_L
MA_RESET_L
MA_EVENT_L
M_VREF
M_ZVDDIO
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
EVENT# pull high
+1.5V
1 2
4 4
R544 1K_0402_5%R544 1K_0402_5%
1 2
R545 1K_0402_5%R545 1K_0402_5%
MEM_MA_EVENT#
MEM_MB_EVENT#
B
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
0.75V reference voltage
+1.5V
R542
R542
1K_0402_1%
1K_0402_1%
1 2
R543
R543
1K_0402_1%
1K_0402_1%
1 2
DDRA_SDQ[63..0] 11
1
C964
C964
1000P_0402_50V7K
1000P_0402_50V7K
2
C
+MEM_VREF 15mil
L
Close to JCPU1
+MEM_VREF
2
C965
C965
.1U_0402_16V7K
.1U_0402_16V7K
1
D
JCPU1C
JCPU1C
MEMORY CHANNEL B
DDRB_SMA[15..0]12
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SBS2#12
DDRB_SDM[7..0]12
DDRB_SDQS012
DDRB_SDQS0#12
DDRB_SDQS112
DDRB_SDQS1#12
DDRB_SDQS212
DDRB_SDQS2#12
DDRB_SDQS312
DDRB_SDQS3#12
DDRB_SDQS412
DDRB_SDQS4#12
DDRB_SDQS512
DDRB_SDQS5#12
DDRB_SDQS612
DDRB_SDQS6#12
DDRB_SDQS712
DDRB_SDQS7#12
DDRB_CLK012
DDRB_CLK0#12
DDRB_CLK112
DDRB_CLK1#12
DDRB_CKE012
DDRB_CKE112
DDRB_ODT012
DDRB_ODT112
DDRB_SCS0#12
DDRB_SCS1#12
DDRB_SRAS#12
DDRB_SCAS#12
DDRB_SWE#12
MEM_MB_RST#12
MEM_MB_EVENT#12
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE0
DDRB_CKE1
DDRB_ODT0
DDRB_ODT1
DDRB_SCS0#
DDRB_SCS1#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
MEM_MB_RST#
MEM_MB_EVENT#
M28
M27
M24
M25
U26
W26
U27
D14
C25
AF25
AG22
AH18
AD14
C15
D18
D22
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
R26
R27
W27
T27
P24
P25
N27
N26
L26
L27
K27
K25
K24
T28
K28
A18
A22
B15
E18
E22
B26
A26
P27
P28
J26
J27
Y28
V25
Y27
V24
V27
V28
J25
T25
MEMORY CHANNEL B
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
E
DDRB_SDQ[63..0] 12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD FS1 DDRIII I/F
AMD FS1 DDRIII I/F
AMD FS1 DDRIII I/F
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
0.1
0.1
7 56Monday, November 28, 2011
7 56Monday, November 28, 2011
7 56Monday, November 28, 2011
E
0.1
A
DP0_TXP0_C21
To LVDS
Translator
1 1
+1.5V
1 2
R579 1K_0402_5%R579 1K_0402_5%
R581 1K_0402_5%R581 1K_0402_5%
1 2
R791 1K_0402_5%R791 1K_0402_5%
1 2
R604 1K_0402_5%R604 1K_0402_5%
R577 1K_0402_5%
R577 1K_0402_5%
1 2
@
@
R613 0_0402_5%
R613 0_0402_5%
1 2
R616 0_0402_5%R616 0_0402_5%
2 2
R578 300_0402_5%R578 300_0402_5%
R580 300_0402_5%R580 300_0402_5%
R575 1K_0402_5%@R575 1K_0402_5%@
R576 1K_0402_5%@R576 1K_0402_5%@
R92 1K_0402_5%@R92 1K_0402_5%@
12
12
@
@
Allow_STOP leakage issue
+1.5V_PCIE +1.5V
12
12
1 2
1 2
1 2
APU_SIC
APU_SID
ALERT_L
ALLOW_STOP
11/14 Reserve
APU_RST#
APU_PWRGD
APU_SVC
APU_SVD
APU_SVT
To FCH
VGA ML
To HDMI
100MHz
100MHz
NSS
SVI 2.0
(0 ohm
at Power Side)
For ESD request close APU side
12
12
C4702 22P_0402_50V8JC4702 22P_0402_50V8J
C4703 22P_0402_50V8JC4703 22P_0402_50V8J
12
12
C4704 22P_0402_50V8JC4704 22P_0402_50V8J
C4705 22P_0402_50V8JC4705 22P_0402_50V8J
11/15 RF
12
12
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
C40 33P_0402_50V8JC40 33P_0402_50V8J
C38 33P_0402_50V8JC38 33P_0402_50V8J
C36 22P_0402_50V8JC36 22P_0402_50V8J
C35 22P_0402_50V8JC35 22P_0402_50V8J
3 3
DP0_TXN0_C21
ML_VGA_TXP026
ML_VGA_TXN026
ML_VGA_TXP126
ML_VGA_TXN126
ML_VGA_TXP226
ML_VGA_TXN226
ML_VGA_TXP326
ML_VGA_TXN326
APU_HDMI_TXD2+23
APU_HDMI_TXD2-23
APU_HDMI_TXD1+23
APU_HDMI_TXD1-23
APU_HDMI_TXD0+23
APU_HDMI_TXD0-23
APU_HDMI_TXC+23
APU_HDMI_TXC-23
APU_CLKP25
APU_CLKN25
APU_DISP_CLKP25
APU_DISP_CLKN25
APU_SVC54
APU_SVD54
APU_SVT54
APU_RST#25
APU_PWRGD25,54
ALLOW_STOP25
H_PROCHOT#45
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
Internal PU when no use HDT
CPU TSI interface level shift
BSH111, the Vgs is:
min = 0.4V
1 2
C935 0.1U_0402_16V4ZC935 0.1U_0402_16V4Z
1 2
+3VS
31.6K_0402_1%
31.6K_0402_1%
APU_SID
BSH111_SOT23-3
BSH111_SOT23-3
APU_SIC
BSH111_SOT23-3
4 4
BSH111_SOT23-3
R535
R535
S
S
S
S
G
G
2
G
G
2
1 2
R536
R536
30K_0402_1%
30K_0402_1%
Q9
Q9
13
D
D
Q10
Q10
13
D
D
Vg = 1.607 V
EC_SMB_DA2
EC_SMB_CK2
When APU High -> MOS OFF (Vgs < 0.4V )
APU Low -> MOS ON (Vgs > 1.3V)
Max = 1.3V
EC_SMB_DA2 14,21,37
EC_SMB_CK2 14,21,37
B
Close to APU (JCPU1)
L
1 2
C971 .1U_0402_16V7KC971 .1U_0402_16V7K
C973 .1U_0402_16V7KC973 .1U_0402_16V7K
1 2
DP0_TXP0
DP0_TXN0
Del DP0_TXP1/N1
1 2
C977 .1U_0402_16V7KC977 .1U_0402_16V7K
C968 .1U_0402_16V7KC968 .1U_0402_16V7K
1 2
1 2
C969 .1U_0402_16V7KC969 .1U_0402_16V7K
C970 .1U_0402_16V7KC970 .1U_0402_16V7K
1 2
C978 .1U_0402_16V7KC978 .1U_0402_16V7K
1 2
1 2
C979 .1U_0402_16V7KC979 .1U_0402_16V7K
C980 .1U_0402_16V7KC980 .1U_0402_16V7K
1 2
1 2
C981 .1U_0402_16V7KC981 .1U_0402_16V7K
APU_SVC
APU_SVD
APU_SVT
SB-TSI (S5 Domain)
1 2
R598 0_0402_5%R598 0_0402_5%
R615 0_0402_5%R615 0_0402_5%
R623 0_0402_5%@R623 0_0402_5%@
APU_VDD_RUN_FB_L54
APU_VDDNB_SEN54
1 2
1 2
APU_VDD_SEN54
T18T18
T17T17
T21T21
APU_PWRGD APU_PWRGD_APU
ALLOW_STOP
Route as differential with APU _VDD_RUN_FB_L
Asserted as an input to
force processor into
HTC-active state
APU_PROCHOT#
THERMTRIP shutdown
temperature: 115 degree
APU_THERMTRIP#
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SIC
APU_SID
APU_RST#_APUAPU_RST#
APU_PROCHOT#
APU_THERMTRIP#
ALERT_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_VDDNB_SEN
APU_VDD_SEN
1 2
+1.5V
R610
R610
1K_0402_5%
1K_0402_5%
1 2
MMBT3904_SOT23-3
MMBT3904_SOT23-3
C
JCPU1D
JCPU1D
ANALOG/DISPLAY/MIS C
ANALOG/DISPLAY/MIS C
L3
DP0_TXP0
L2
DP0_TXN0
K5
DP0_TXP1
K4
DP0_TXN1
K2
DP0_TXP2
K1
DP0_TXN2
J3
DP0_TXP3
J2
DP0_TXN3
H5
DP1_TXP0
H4
DP1_TXN0
H2
DP1_TXP1
H1
DP1_TXN1
G3
DP1_TXP2
G2
DP1_TXN2
F2
DP1_TXP3
F1
DP1_TXN3
L9
DP2_TXP0
L8
DP2_TXN0
L5
DP2_TXP1
L6
DP2_TXN1
K8
DP2_TXP2
K7
DP2_TXN2
J6
DP2_TXP3
J5
DP2_TXN3
AE11
CLKIN_H
AD11
CLKIN_L
AB11
DISP_CLKIN_H
AA11
DISP_CLKIN_L
B3
SVC
A3
SVD
C3
SVT
AG12
SIC
AH12
SID
AF10
RESET_L
AB12
PWROK
AC12
DMAACTIVE_L
AC10
PROCHOT_L
AE12
THERMTRIP_L
AF12
ALERT_L
H10
TDI
J10
TDO
F10
TCK
G10
TMS
F9
TRST_L
G9
DBRDY
H9
DBREQ_L
B4
VSS_SENSE
C5
VDDP_SENSE
A4
VDDNB_SENSE
A5
VDDIO_SENSE
C4
VDD_SENSE
B5
VDDR_SENSE
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
R586
R586
1K_0402_5%
1K_0402_5%
R591
R591
1 2
0_0402_5%
0_0402_5%
Indicates to the FCH that a th ermal trip
has occurred. Its assertion wi ll cause the FCH
12
to transition the system to S5 immediately
R609
R609
10K_0402_5%
10K_0402_5%
B
B
2
Q12
Q12
E
E
3 1
C
C
DISPLAY PORT
DISPLAY PORT
DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE
DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE
+3VS+1.5V
R587
R587
10K_0402_5%
10K_0402_5%
Q11
Q11
C
C
MMBT3904_SOT23-3
MMBT3904_SOT23-3
1 2
R611 0_0402_5%R611 0_0402_5%
1 2
R612 0_0402_5%@R612 0_0402_5%@
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
0
0
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DISPLAY PORT
MISC.
DISPLAY PORT
MISC.
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST6
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST32_H
TEST32_L
TEST4
TEST5
TEST9
TEST10
TEST14
TEST15
TEST16
TESTRSVD
TESTRSVD
TEST17
TEST18
TEST19
TEST20
TEST24
TEST35
TEST25_H
TEST25_L
TEST31
FS1R2
RSVD1
RSVD2
RSVD3
RSVD4
12
12
R588
R588
10K_0402_5%
10K_0402_5%
2
B
B
E
E
31
H_THERMTRIP# 27
MAINPWON 45,46
D1
DP0_AUXP
D2
DP0_AUXN
E1
ML_VGA_AUXP
E2
ML_VGA_AUXN
D5
APU_HDMI_CLK
D6
APU_HDMI_DATA
E5
E6
F5
F6
G5
G6
D3
DP0_HPD
E3
DP1_HPD
D7
DP2_HPD
E7
F7
G7
C6
DP_ENBKL
B6
A6
DP_INT_PWM
C1
DP_AUX_ZVSS
AD12
L10
M10
P19
R19
T19
N19
P18
R18
M18
N18
F11
G11
H11
J11
F12
APU_TEST18
G12
APU_TEST19
J12
APU_TEST20
H12
APU_TEST24
AA12
TEST35
AE10
TEST25_H
AD10
TEST25_L
K22
M_TEST
W10
FS1R2
Y10
AA10
Y12
K21
EC_THERM# 25,37,45,54
Place near APU
1 2
C972 .1U_0402_16V7KC972 .1U_0402_16V7K
C974 .1U_0402_16V7KC974 .1U_0402_16V7K
1 2
C975 .1U_0402_16V7KC975 .1U_0402_16V7K
1 2
1 2
C976 .1U_0402_16V7KC976 .1U_0402_16V7K
Del DP_ENVDD
1 2
R569 150_0402_1%R569 150_0402_1%
T16T16
T15T15
T6T6
T7T7
T8T8
T9T9
T10T10
T11T11
T12T12
T13T13
R582 1K_0402_5%R582 1K_0402_5%
1 2
1 2
R583 1K_0402_5%R583 1K_0402_5%
1 2
R584 1K_0402_5%R584 1K_0402_5%
R574 1K_0402_5%R574 1K_0402_5%
1 2
R558 300_0402_5%R558 300_0402_5%
1 2
1 2
R559 300_0402_5%@R559 300_0402_5%@
1 2
R557 510_0402_1%R557 510_0402_1%
R548 510_0402_1%R548 510_0402_1%
1 2
R564 39.2_0402_1%@R564 39.2_0402_1%@
1 2
1 2
R567 39.2_0402_1%R567 39.2_0402_1%
R571 10K_0402_5%R571 10K_0402_5%
1 2
HDT Debug conn
D
DP0_AUXP_C 21
DP0_AUXN_C 21
ML_VGA_AUXP_C 26
ML_VGA_AUXN_C 26
APU_HDMI_CLK 23
APU_HDMI_DATA 23
DP0_HPD 10
DP1_HPD 10
DP2_HPD 23
To LVDS Translator
To FCH
To HDMI
LVDS/eDP
CRT
HDMI
LA-8124 no use this DP_ENBKL.
DP_ENBKL 10
DP_INT_PWM 10
DP_AUX_ZVSS W/S=8/12 mil, <3000mil
L
TEST35 change to PU for
HDMI can not output
+1.5V
20110126
+1.2VS
+1.5V
+3VALW
VDDIO level
Need Level shift
11/14 Change net name
11/10 del debug connector
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
+1.5V
Close to Header
R592 1K_0402_5%R592 1K_0402_5%
1 2
R593 1K_0402_5%R593 1K_0402_5%
1 2
1 2
R594 1K_0402_5%R594 1K_0402_5%
1 2
R595 1K_0402_5%R595 1K_0402_5%
1 2
R596 1K_0402_5%R596 1K_0402_5%
10/27 300 ohm??
E
R554 1.8K_0402_5%R554 1.8K_0402_5%
R555 1.8K_0402_5%R555 1.8K_0402_5%
R547 1.8K_0402_5%R547 1.8K_0402_5%
R556 1.8K_0402_5%R556 1.8K_0402_5%
12
12
12
12
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD FS1 Display / MISC / HDT
AMD FS1 Display / MISC / HDT
AMD FS1 Display / MISC / HDT
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
8 56Monday, November 28, 2011
8 56Monday, November 28, 2011
8 56Monday, November 28, 2011
0.1
0.1
0.1
A
Power Name
VDD
+CPU_CORE
VDDNB
+CPU_CORE_NB
VDDIO
+1.5V
VDDP / VDDR
+1.2VS
VDDA
1 1
+2.5VS
Consumption
60A
37A
3.2A
5A / 3.5A
0.75A
+CPU_CORE-->+APU_CORE
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDR_1
VDDR_2
VDDR_3
VDDR_4
+APU_CORE
R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11
C11
+APU_CORE_NB
C12
D9
D8
D12
+CPU_CORE_NB-->+APU_CORE_NB
D11
B11
A12
B10
E12
B9
K13
VDDNB_CAP
K12
T23
T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28
AG10
AH8
AH9
AH10
C1003 22U_0805_6.3V6MC1003 22U_0805_6.3V6M
C1026 180P_0402_50V 8JC1026 180P_0402_50V 8J
C1002 22U_0805_6.3V6MC1002 22U_0805_6.3V6M
1
1
1
2
2
2
Northbridge Powe r Pins
for Remote Decou pling
+1.5V
VDDIO: 3200mA
+1.2VS
VDDR: 3500mA
+APU_CORE
2 2
+APU_CORE_NB
3 3
+1.5V
+1.2VS
VDDP: 5000mA
+APU_VDDA
VDDA: 750mA
4 4
JCPU1E
JCPU1E
F8
VDD_1
H6
VDD_2
J1
VDD_3
J14
VDD_4
P6
VDD_5
P10
VDD_6
J16
VDD_7
J18
VDD_8
J9
VDD_9
K19
VDD_10
K3
VDD_11
K17
VDD_12
M3
VDD_13
K6
VDD_14
V10
VDD_15
V18
VDD_16
V3
VDD_17
F3
VDD_18
L18
VDD_19
V6
VDD_20
W1
VDD_21
T18
VDD_22
Y14
VDD_23
AA1
VDD_24
AB6
VDD_25
AC1
VDD_26
R1
VDD_27
P3
VDD_28
K10
VDD_29
H3
VDD_30
M19
VDD_31
C8
VDDNB_1
D10
VDDNB_2
B8
VDDNB_3
B12
VDDNB_4
C9
VDDNB_5
A9
VDDNB_6
A10
VDDNB_7
A8
VDDNB_8
A11
VDDNB_9
E10
VDDNB_10
E11
VDDNB_11
C10
VDDNB_12
H26
VDDIO_1
K20
VDDIO_2
J28
VDDIO_3
K23
VDDIO_4
K26
VDDIO_5
L22
VDDIO_6
L25
VDDIO_7
L28
VDDIO_8
M20
VDDIO_9
M23
VDDIO_10
M26
VDDIO_11
N22
VDDIO_12
N25
VDDIO_13
N28
VDDIO_14
P20
VDDIO_15
P23
VDDIO_16
P26
VDDIO_17
AA28
VDDIO_18
AH6
VDDP_1
AH5
VDDP_2
AH4
VDDP_3
AH3
VDDP_4
AH7
VDDP_5
AB10
VDDA
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
POWER
POWER
VDDNB_CAP_1
VDDNB_CAP_2
Decoupling Caps.
Pop / @
Pumori 2.0
Comal
P5WS5
330uF 220uF 47uF 22uF 10uF 4.7uF 0.22uF 0.01uF 3300pF 180pF1nF
0
19/11 7 35 17 1 1 / 1 13/3
7 / 2
7 / 21111
A
19/11 7 4 17 3
13 3 8 19 3 1 4 16
B
+1.5V
C1012 22U_0805_6.3V6MC1012 22U_0805_6.3V6M
C1013 22U_0805_6.3V6MC1013 22U_0805_6.3V6M
1
2
+1.2VS
+1.2VS
+2.5VS
C53 10U_0603_6.3V6MC53 10U_0603_6.3V6M
C54 10U_0603_6.3V6MC54 10U_0603_6.3V6M
1
2
C51 22U_0805_6.3V6MC51 22U_0805_6.3V6M
1
2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1 1 / 1 14/2
B
On power team page
C56 22U_0805_6.3V6MC56 22U_0805_6.3V6M
C55 22U_0805_6.3V6MC55 22U_0805_6.3V6M
1
1
1
2
2
2
C1052 0.22U_04 02_10V4ZC1052 0.22U_0402_10V 4Z
C52 10U_0603_6.3V6MC52 10U_0603_6.3V6M
1
1
2
2
C6 10U_0603_6.3V6MC6 10U_0603_6.3V6M
C7 10U_0603_6.3V6MC7 10U_0603_6.3V6M
C8 10U_0603_6.3V6MC8 10U_0603_6.3V6M
1
1
1
2
2
2
L1
L1
12
C18 47U_0805_4V6C18 47U_0805_4V6
C
On power team page
+CPU_CORE_NB Decoupling
330uF x2
22uF x2 @ x2
10uF x1
0.22uF x2
180pF x3
C16 4.7U_0603_6.3V6KC16 4.7U_0603_6.3V6K
C15 4.7U_0603_6.3V6KC15 4.7U_0603_6.3V6K
C17 4.7U_0603_6.3V6KC17 4.7U_0603_6.3V6K
C14 4.7U_0603_6.3V6KC14 4.7U_0603_6.3V6K
1
1
1
1
2
2
2
2
C1053 0.22U_04 02_10V4ZC1053 0.22U_0402_10V 4Z
C1048 1000P _0402_50V7KC1048 1000P _0402_50V7K
1
1
1
2
2
2
@
C50 1000P_0402_50V7K@C50 1000P_0402_50V7K
C1036 0.22U_0402_10V4 ZC1036 0.22U_0402_10V4Z
C1037 0.22U_0402_10V4 ZC1037 0.22U_0402_10V4Z
1
1
2
2
C1020 0.22U_0402_10V4 ZC1020 0.22U_0402_10V4Z
C1019 0.22U_0402_10V4 ZC1019 0.22U_0402_10V4Z
C1022 0.22U_0402_10V4 ZC1022 0.22U_0402_10V4Z
C1021 0.22U_0402_10V4 ZC1021 0.22U_0402_10V4Z
C1018 0.22U_0402_10V4 ZC1018 0.22U_0402_10V4Z
1
1
2
2
C1044 180P _0402_50V8JC1044 180P _0402_50V8J
C1045 180P _0402_50V8JC1045 180P _0402_50V8J
1
1
2
2
C1034 180P_0402_50V 8JC1034 180P_0402_50V 8J
C1035 180P_0402_50V 8JC1035 180P_0402_50V 8J
1
1
2
2
C1023 0.22U_0402_10V4 ZC1023 0.22U_0402_10V4Z
1
1
1
1
2
2
2
2
VDDR Decoupling
Close JCPU1.AG10,AH8,AH9,AH10
10uF x3
0.22uF x2
1000pF x1
180pF x2
VDDP Decoupling
Close JCPU1.AH3~7
1
22uF x1
2
10uF x3
0.22uF x2
1000pF @x1
180pF x2
C5 330U_D2_2V_Y+C5 330U_D2_2V_Y
C1024 180P_0402_50V 8JC1024 180P_0402_50V 8J
C1025 180P_0402_50V 8JC1025 180P_0402_50V 8J
1
1
2
2
+1.5V / VDDIO Decoupling
1
+
330uF x1
22uF x4
2
4.7uF x4
0.22uF x6
180pF x1 @x1
+1.2VS
1
C1038220U_6.3V_M+C1038220U_6.3V_M
+
2
220uF x1
C1043 180P_0402_50V 8JC1043 180P_0402_50V 8J
1
2
+APU_VDDA
VDDA Decoupling
47uF x1
0.22uF x1
3300pF x1
180pF x1
C1040 3300P_0402_50V 7-KC1040 3300P_0402_50V7-K
C1041 0.22U_0402_10V4 ZC1041 0.22U_0402_10V4Z
1
2
1
1
2
2
D
+CPU_CORE Decoupling
330uF x 4 @ x1
22uF x 10
0.22uF x2
0.01uF x3
180pF x2 @ x1
Decoupling betwe en CPU and DIMMs
across VDDIO and VSS split
+1.5V
C1027 0.22U_0402_10V4 ZC1027 0.22U_0402_10V4Z
C1028 0.22U_0402_10V4 ZC1028 0.22U_0402_10V4Z
C1029 180P_0402_50V 8JC1029 180P_0402_50V 8J
C1030 180P_0402_50V 8JC1030 180P_0402_50V 8J
1
1
1
1
2
2
2
2
Power Sequence of APU
+1.5V
+2.5VS
E
JCPU1F
JCPU1F
J20
VSS_1
L4
VSS_2
R7
VSS_3
W18
VSS_4
A15
VSS_5
AB17
VSS_6
AC22
VSS_7
AE21
VSS_8
AF24
VSS_9
AH23
VSS_10
AH25
VSS_11
B7
VSS_12
C14
VSS_13
C16
VSS_14
C2
VSS_15
C20
VSS_16
C22
VSS_17
C24
VSS_18
C26
VSS_19
C28
VSS_20
D13
VSS_21
D15
VSS_22
D17
VSS_23
D19
VSS_24
D23
VSS_25
D25
VSS_26
D27
VSS_27
E4
VSS_28
E9
VSS_29
F14
VSS_30
F16
VSS_31
F18
VSS_32
F20
VSS_33
F22
VSS_34
F26
VSS_35
F28
VSS_36
G13
VSS_37
G15
VSS_38
G17
VSS_39
G19
VSS_40
GND
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
GND
G21
G23
G25
G4
J22
J24
J4
J7
K11
K14
K9
AC11
L19
L7
M11
AF11
V19
V9
W16
W4
W7
Y11
Y20
Y22
Y9
A17
A13
K16
F24
G8
H7
J8
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12
Group A
+1.5VS
+CPU_CORE
+CPU_CORE_NB
Group B
+1.2VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
AMD FS1R2 PWR / GND
AMD FS1R2 PWR / GND
AMD FS1R2 PWR / GND
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
0.1
0.1
9 56Monday, November 28, 2011
9 56Monday, November 28, 2011
9 56Monday, November 28, 2011
0.1
5
4
3
2
1
Panel ENBKL
HPD
HPD
HPDHPD
Del reserved NMOS
D D
Translator and eDP HPD
From Translator or Conn.
LVDS_HPD21
LVDS_HPD
1 2
R86 0_0402_5%R86 0_0402_5%
Del reserved NMOS
C C
CRT HPD
From FCH
FCH_CRT_HPD26
FCH_CRT_HPD
DP0_HPD
DP0_HPD 8
DP1_HPD 8
DP_ENBKL8
Del VGA_ENBKL
eDP Panel ENVDD
LA-8124 no use this DP_ENBKL.
+3VS
12
R614
R614
4.7K_0402_5%
R617
R617
100K_0402_5%
100K_0402_5%
1 2
C
C
Q15
1 2
Q15
2
B
B
E
E
3 1
MMBT3904_SOT23-3
MMBT3904_SOT23-3
1 2
R619 2.2K_0402_5%R619 2.2K_0402_5%
R620
R620
100K_0402_5%
100K_0402_5%
1 2
DP_ENBKL ENBKL
R624 0_0402_5%@R624 0_0402_5%@
Reserved R624
4.7K_0402_5%
13
D
D
2
G
Q14
G
Q14
2N7002K_SOT23-3
2N7002K_SOT23-3
S
S
D16
@D16
@
2 1
RB751V-40_SOD323-2
RB751V-40_SOD323-2
APU_PCIE_RST# 13,21,25,31,32
ENBKL 21,37
Del eDP panel control
1 2
R88 0_0402_5%R88 0_0402_5%
B B
Panel PWM
R637
R637
2.2K_0402_5%
2.2K_0402_5%
DP_INT_PWM8
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
1 2
12
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
R638
R638
4.7K_0402_5%
4.7K_0402_5%
MMBT3904_SOT23-3
MMBT3904_SOT23-3
Compal Secret Data
Compal Secret Data
Compal Secret Data
R635
R635
47K_0402_5%
47K_0402_5%
2
B
B
Deciphered Date
Deciphered Date
Deciphered Date
+3VS
E
E
12
C
C
Q21
Q21
3 1
12
R636
R636
4.7K_0402_5%
4.7K_0402_5%
13
D
D
2
G
G
Q20
Q20
2N7002K_SOT23-3
2N7002K_SOT23-3
S
S
2
APU_INVT_PWM 21
Title
Title
Title
AMD FS1R2 Singal Level Shifter
AMD FS1R2 Singal Level Shifter
AMD FS1R2 Singal Level Shifter
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
0.1
0.1
10 56Monday, November 28, 2011
10 56Monday, November 28, 2011
10 56Monday, November 28, 2011
0.1
A
+1.5V +1.5V+VREF_DQA
JDIMM1
+VREF_DQ 15mil
L
1 1
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_CKE07
2 2
3 3
4 4
C1080
C1080
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
DDRA_SBS2#7
DDRA_CLK07
DDRA_CLK0#7
DDRA_SBS0#7
DDRA_SWE#7
DDRA_SCAS#7 DDRA_ODT0 7
DDRA_SCS1#7
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
+3VS
1
1
2
C1081
C1081
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS# DDRA_ODT0
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643 10K_0402_5%R643 10K_0402_5%
+3VS
1 2
12
R645
R645
10K_0402_5%
10K_0402_5%
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
B
2
4
DDRA_SDQ4
6
DDRA_SDQ5
8
10
DDRA_SDQS0#
12
DDRA_SDQS0
14
16
DDRA_SDQ6
18
DDRA_SDQ7
20
22
DDRA_SDQ12
24
DDRA_SDQ13
26
28
DDRA_SDM1
30
MEM_MA_RST#
32
34
DDRA_SDQ14
36
DDRA_SDQ15
38
40
DDRA_SDQ20
42
DDRA_SDQ21
44
46
DDRA_SDM2
48
50
DDRA_SDQ22
52
DDRA_SDQ23
54
56
DDRA_SDQ28
58
DDRA_SDQ29
60
62
DDRA_SDQS3#
64
DDRA_SDQS3
66
68
DDRA_SDQ30
70
DDRA_SDQ31
72
74
DDRA_CKE1
76
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDRA_SMA15
80
DDRA_SMA14
82
84
DDRA_SMA11
86
DDRA_SMA7
88
90
DDRA_SMA6
92
DDRA_SMA4
94
96
DDRA_SMA2
98
DDRA_SMA0
100
102
DDRA_CLK1
104
DDRA_CLK1#
106
108
DDRA_SBS1#
110
DDRA_SRAS#
112
114
DDRA_SCS0#
116
118
120
DDRA_ODT1
122
124
126
128
130
DDRA_SDQ36
132
DDRA_SDQ37
134
136
DDRA_SDM4
138
140
DDRA_SDQ38
142
DDRA_SDQ39
144
146
DDRA_SDQ44
148
DDRA_SDQ45
150
152
DDRA_SDQS5#
154
DDRA_SDQS5
156
158
DDRA_SDQ46
160
DDRA_SDQ47
162
164
DDRA_SDQ52
166
DDRA_SDQ53
168
170
DDRA_SDM6
172
174
DDRA_SDQ54
176
DDRA_SDQ55
178
180
DDRA_SDQ60
182
DDRA_SDQ61
184
186
DDRA_SDQS7#
188
DDRA_SDQS7
190
192
DDRA_SDQ62
194
DDRA_SDQ63
196
198
MEM_MA_EVENT#
200
202
204
206
+0.75VS
DDRA_SDQS0# 7
DDRA_SDQS0 7
MEM_MA_RST# 7
DDRA_SDQS3# 7
DDRA_SDQS3 7
DDRA_CKE1 7
DDRA_CLK1 7
DDRA_CLK1# 7
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
DDRA_ODT1 7
+VREF_CA
L
1
C1066
C1066
1000P_0402_50V7K
1000P_0402_50V7K
2
DDRA_SDQS5# 7
DDRA_SDQS5 7
DDRA_SDQS7# 7
DDRA_SDQS7 7
MEM_MA_EVENT# 7
FCH_SDATA0 12,27,32,35
FCH_SCLK0 12,27,32,35
+VREF_CA 15mil
C
Place near DIMM1
11/14 Change net name
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+1.5V
2
C1067
C1067
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1077
C1077
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
L
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
@
@
C1060
C1060
2
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1068
C1068
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1078
C1078
1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+VREF_DQ 15mil
+VREF_DQA
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
C1062
C1062
C1061
C1061
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C1069
C1069
1
1
C1106 0.1U_0402_16V4ZC1106 0.1U_0402_16V4Z
1
C1079
C1079
2
+1.5V+VREF_DQA
R639
R639
1K_0402_1%
1K_0402_1%
1 2
R641
R641
1K_0402_1%
1K_0402_1%
1 2
D
C1070
C1070
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1071
C1071
1
+1.5V+0.75VS
2
C1072
C1072
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15mil
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
@
@
2
2
C1073
C1073
1
+VREF_CA 15mil
L
+VREF_CA
1
C1063
C1063
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1074
C1074
1
1
C1064
C1064
2
1000P_0402_50V7K
1000P_0402_50V7K
2
C1075
C1075
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V+VREF_CA
1 2
C1065
C1065
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1076
C1076
1
R640
R640
1K_0402_1%
1K_0402_1%
R642
R642
1K_0402_1%
1K_0402_1%
E
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_A REV H:4mm
<Address: 00>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
0.1
0.1
11 56Monday, November 28, 2011
11 56Monday, November 28, 2011
11 56Monday, November 28, 2011
0.1
A
B
C
D
E
DQ4
DQ5
DQ6
DQ7
DM1
DM2
CK1
BA1
NC2
DM4
DM6
SDA
SCL
+1.5V+1.5V
2
4
DDRB_SDQ4
6
DDRB_SDQ5
8
10
DDRB_SDQS0#
12
DDRB_SDQS0
14
16
DDRB_SDQ6
18
DDRB_SDQ7
20
22
DDRB_SDQ12
24
DDRB_SDQ13
26
28
DDRB_SDM1
30
MEM_MB_RST#
32
34
DDRB_SDQ14
36
DDRB_SDQ15
38
40
DDRB_SDQ20
42
DDRB_SDQ21
44
46
DDRB_SDM2
48
50
DDRB_SDQ22
52
DDRB_SDQ23
54
56
DDRB_SDQ28
58
DDRB_SDQ29
60
62
DDRB_SDQS3#
64
DDRB_SDQS3
66
68
DDRB_SDQ30
70
DDRB_SDQ31
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
DDRB_CKE1
DDRB_SMA15
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0DDRB_SCAS#
DDRB_ODT1
15mil
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
DDRB_SDQ62
DDRB_SDQ63
MEM_MB_EVENT#
+0.75VS
DDRB_SDQS0# 7
DDRB_SDQS0 7
MEM_MB_RST# 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_CKE1 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
+VREF_CB
1
C1088
C1088
1000P_0402_50V7K
1000P_0402_50V7K
2
DDRB_SDQS5# 7
DDRB_SDQS5 7
DDRB_SDQS7# 7
DDRB_SDQS7 7
MEM_MB_EVENT# 7
FCH_SDATA0 11,27,32,35
FCH_SCLK0 11,27,32,35
+VREF_CA 15mil
L
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
Place near DIMM2
+1.5V
2
C1089
C1089
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.75VS
2
C1099
C1099
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1090
C1090
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
2
C1091
C1091
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1101
C1101
C1100
C1100
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
C1092
C1092
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
C1107 0.1U_0402_16V4ZC1107 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1093
C1093
11/14 Change net name11/14 Change net name
R649
C1084
C1084
R649
1K_0402_1%
1K_0402_1%
1 2
R650
R650
1K_0402_1%
1K_0402_1%
1 2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+VREF_DQB +VREF_CB
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
+VREF_DQ 15mil
L
+VREF_DQB +VREF_CB
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C1083
C1083
C1082
C1082
2
2
1000P_0402_50V7K
1000P_0402_50V7K
1
2
2
1
L
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1085
C1085
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1094
C1094
C1095
C1095
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V+1.5V
1
+
+
@
@
C9
C9
330U_D2_2V_Y
330U_D2_2V_Y
2
Change To D2 Typ e 20110905
+VREF_CA 15mil
1
1
2
C1086
C1086
C1087
C1087
2
1000P_0402_50V7K
1000P_0402_50V7K
2
C1096
C1096
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V+1.5V
2
1
R647
R647
1K_0402_1%
1K_0402_1%
1 2
R644
R644
1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1097
C1097
2
C1098
C1098
1
+VREF_DQB
+VREF_DQ 15mil
L
1 1
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQS2#7
DDRB_SDQS27
DDRB_CKE07
2 2
3 3
4 4
DDRB_SBS2#7
DDRB_CLK07
DDRB_CLK0#7
DDRB_SBS0#7
DDRB_SWE#7
DDRB_SCAS#7
DDRB_SCS1#7
DDRB_SDQS4#7
DDRB_SDQS47
DDRB_SDQS6#7
DDRB_SDQS67
+3VS
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646 10K_0402_5%R646 10K_0402_5%
1 2
12
R648
R648
10K_0402_5%
10K_0402_5%
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4406-0102
LCN_DAN06-K4406-0102
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_B REV H:8mm
<Address: 01>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
C
2011/07/08 2015/07/08
2011/07/08 2015/07/08
2011/07/08 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
E
0.1
0.1
0.1
of
12 56Monday, November 28, 2011
12 56Monday, November 28, 2011
12 56Monday, November 28, 2011
5
4
3
2
1
LVDS Interface
UVG1G
UVG1G
PART 7 0F 9
H7
H8
AN9
1M_0402_5%
1M_0402_5%
2 1
LVTMDP
LVTMDP
DPLL_PVDD
DPLL_VDDC
DPLL_PVSS
MPLL_PVDD
MPLL_PVDD
SPLL_PVDD
SPLL_VDDC
SPLL_PVSS
NC_XTAL_PVDD
NC_XTAL_PVSS
RV28
RV28
PX@
PX@
YV2
PX@YV2
PX@
PART 7 0F 9
LVDS CONTROL
LVDS CONTROL
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
UVG1I
UVG1I
PART 9 0F 9
PART 9 0F 9
PLLS/XTAL
PLLS/XTAL
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
CV50
PX@CV50
PX@
18P_0402_50V8J
18P_0402_50V8J
AK27
VARY_BL
AJ27
DIGON
AK35
TXCLK_UP_DPF3P
AL36
TXCLK_UN_DPF3N
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
TXOUT_U3P
AG36
TXOUT_U3N
AP34
TXCLK_LP_DPE3P
AR34
TXCLK_LN_DPE3N
AW37
AU35
AR37
AU39
AP35
AR35
AN36
TXOUT_L3P
AP37
TXOUT_L3N
AV33
XTALIN
XTALIN
AU34
XTALOUT
XTALOUT
RV146
@RV146
@
0_0402_5%
0_0402_5%
@RV147
@
0_0402_5%
0_0402_5%
51.1_0402_1%
51.1_0402_1%
RV147
CV170
CV170
RV69
RV69
@
@
@
@
12
12
12
12
12
@
@
CV171
CV171
0.1U_0402_16V7K
0.1U_0402_16V7K
12
@
@
RV70
RV70
51.1_0402_1%
51.1_0402_1%
AW34
XO_IN
AW35
XO_IN2
AK10
CLKTESTA
AL10
CLKTESTB
0.1U_0402_16V7K
0.1U_0402_16V7K
route 50ohms single-ended/100o hms diff
and keep short
Debug only, for clock observat ion, if not needed, DNI
5mil 5mil
PCIE_FTX_C_GRX_P[15..0]6
PCIE_FTX_C_GRX_N[15..0]6
D D
C C
CLK_PEG_VGA25
CLK_PEG_VGA#25
B B
PCIE_FTX_C_GRX_P[15..0]
PCIE_FTX_C_GRX_N[15..0]
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_C_GRX_P8
PCIE_FTX_C_GRX_N8
PCIE_FTX_C_GRX_P9
PCIE_FTX_C_GRX_N9
PCIE_FTX_C_GRX_P10
PCIE_FTX_C_GRX_N10
PCIE_FTX_C_GRX_P11
PCIE_FTX_C_GRX_N11
PCIE_FTX_C_GRX_P12
PCIE_FTX_C_GRX_N12
PCIE_FTX_C_GRX_P13
PCIE_FTX_C_GRX_N13
PCIE_FTX_C_GRX_P14
PCIE_FTX_C_GRX_N14
PCIE_FTX_C_GRX_P15
PCIE_FTX_C_GRX_N15
PX@
PX@
RV4
RV4
1K_0402_5%
1K_0402_5%
GPU_RST#
AA38
W36
W38
M37
M35
G36
G38
AB35
AA36
AH16
12
AA30
12
PX@
PX@
RV6
RV6
100K_0402_5%
100K_0402_5%
UVG1A
UVG1A
PART 1 0F 9
PART 1 0F 9
PCIE_RX0P
Y37
PCIE_RX0N
Y35
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
V37
PCIE_RX2N
V35
PCIE_RX3P
U36
PCIE_RX3N
U38
PCIE_RX4P
T37
PCIE_RX4N
T35
PCIE_RX5P
R36
PCIE_RX5N
R38
PCIE_RX6P
P37
PCIE_RX6N
P35
PCIE_RX7P
N36
PCIE_RX7N
N38
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
L36
PCIE_RX9N
L38
PCIE_RX10P
K37
PCIE_RX10N
K35
PCIE_RX11P
J36
PCIE_RX11N
J38
PCIE_RX12P
H37
PCIE_RX12N
H35
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
F37
PCIE_RX14N
F35
PCIE_RX15P
E37
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
TEST_PG
PERSTB
CLOCK
CLOCK
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALR_TX
PCIE_CALR_RX
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
RV1 0_0402_5%@RV1 0_0402_5%@
+3VGS
5
UV1
UV1
2
PX_GPU_RST#25,27
APU_PCIE_RST#10,21,25,31,32
A A
P
B
Y
1
A
G
PX@
PX@
3
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
12
4
PCIE_GTX_C_FRX_P[0..15]
PCIE_GTX_C_FRX_N[0..15]
Y33
PCIE_GTX_FRX_P0
Y32
PCIE_GTX_FRX_N0
W33
PCIE_GTX_FRX_P1
W32
PCIE_GTX_FRX_N1
U33
PCIE_GTX_FRX_P2
U32
PCIE_GTX_FRX_N2
U30
PCIE_GTX_FRX_P3
U29
PCIE_GTX_FRX_N3
T33
PCIE_GTX_FRX_P4
T32
PCIE_GTX_FRX_N4
T30
PCIE_GTX_FRX_P5
T29
PCIE_GTX_FRX_N5
P33
PCIE_GTX_FRX_P6
P32
PCIE_GTX_FRX_N6
P30
PCIE_GTX_FRX_P7
P29
PCIE_GTX_FRX_N7
N33
PCIE_GTX_FRX_P8
N32
PCIE_GTX_FRX_N8
N30
PCIE_GTX_FRX_P9
N29
PCIE_GTX_FRX_N9
L33
PCIE_GTX_FRX_P10
L32
PCIE_GTX_FRX_N10
L30
PCIE_GTX_FRX_P11
L29
PCIE_GTX_FRX_N11
K33
PCIE_GTX_FRX_P12
K32
PCIE_GTX_FRX_N12
J33
PCIE_GTX_FRX_P13
J32
PCIE_GTX_FRX_N13
K30
PCIE_GTX_FRX_P14
K29
PCIE_GTX_FRX_N14
H33
PCIE_GTX_FRX_P15
H32
PCIE_GTX_FRX_N15
Y30
Y29
GPU_RST#
1 2
1 2
1 2
PCIE_GTX_C_FRX_P[0..15] 6
PCIE_GTX_C_FRX_N[0..15] 6
12
CV1.1U_0402_16V7K PX@CV1.1U_0402_16V7K PX@
12
CV2.1U_0402_16V7K PX@CV2.1U_0402_16V7K PX@
12
CV3.1U_0402_16V7K PX@CV3.1U_0402_16V7K PX@
12
CV4.1U_0402_16V7K PX@CV4.1U_0402_16V7K PX@
12
CV5.1U_0402_16V7K PX@CV5.1U_0402_16V7K PX@
12
CV6.1U_0402_16V7K PX@CV6.1U_0402_16V7K PX@
12
CV7.1U_0402_16V7K PX@CV7.1U_0402_16V7K PX@
12
CV8.1U_0402_16V7K PX@CV8.1U_0402_16V7K PX@
12
CV9.1U_0402_16V7K PX@CV9.1U_0402_16V7K PX@
12
CV10.1U_0402_16V7K PX@CV10.1U_0402_16V7K PX@
12
CV11.1U_0402_16V7K PX@CV11.1U_0402_16V7K PX@
12
CV12.1U_0402_16V7K PX@CV12.1U_0402_16V7K PX@
12
CV13.1U_0402_16V7K PX@CV13.1U_0402_16V7K PX@
12
CV14.1U_0402_16V7K PX@CV14.1U_0402_16V7K PX@
12
CV15.1U_0402_16V7K PX@CV15.1U_0402_16V7K PX@
12
CV16.1U_0402_16V7K PX@CV16.1U_0402_16V7K PX@
12
CV17.1U_0402_16V7K PX@CV17.1U_0402_16V7K PX@
12
CV18.1U_0402_16V7K PX@CV18.1U_0402_16V7K PX@
12
CV19.1U_0402_16V7K PX@CV19.1U_0402_16V7K PX@
12
CV20.1U_0402_16V7K PX@CV20.1U_0402_16V7K PX@
12
CV21.1U_0402_16V7K PX@CV21.1U_0402_16V7K PX@
12
CV22.1U_0402_16V7K PX@CV22.1U_0402_16V7K PX@
12
CV23.1U_0402_16V7K PX@CV23.1U_0402_16V7K PX@
12
CV24.1U_0402_16V7K PX@CV24.1U_0402_16V7K PX@
12
CV25.1U_0402_16V7K PX@CV25.1U_0402_16V7K PX@
12
CV26.1U_0402_16V7K PX@CV26.1U_0402_16V7K PX@
12
CV27.1U_0402_16V7K PX@CV27.1U_0402_16V7K PX@
12
CV28.1U_0402_16V7K PX@CV28.1U_0402_16V7K PX@
12
CV29.1U_0402_16V7K PX@CV29.1U_0402_16V7K PX@
12
CV30.1U_0402_16V7K PX@CV30.1U_0402_16V7K PX@
12
CV31.1U_0402_16V7K PX@CV31.1U_0402_16V7K PX@
12
CV32.1U_0402_16V7K PX@CV32.1U_0402_16V7K PX@
PX@
PX@
RV291.69K_0402_1%
RV291.69K_0402_1%
RV31.27K_0402_1% @ RV31.27K_0402_1% @
RV51K_0402_5% PX@RV51K_0402_5% PX@
+0.935VGS
+0.935VGS
For Chelsea only
For Chelsea non staff
+1.0VGS-->+0.935VGS
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
PCIE_GTX_C_FRX_P8
PCIE_GTX_C_FRX_N8
PCIE_GTX_C_FRX_P9
PCIE_GTX_C_FRX_N9
PCIE_GTX_C_FRX_P10
PCIE_GTX_C_FRX_N10
PCIE_GTX_C_FRX_P11
PCIE_GTX_C_FRX_N11
PCIE_GTX_C_FRX_P12
PCIE_GTX_C_FRX_N12
PCIE_GTX_C_FRX_P13
PCIE_GTX_C_FRX_N13
PCIE_GTX_C_FRX_P14
PCIE_GTX_C_FRX_N14
PCIE_GTX_C_FRX_P15
PCIE_GTX_C_FRX_N15
+1.8VGS
+0.935VGS
+1.8VGS
MCK1608471YZF 0603
MCK1608471YZF 0603
+1.8VGS
+0.935VGS
MCK1608471YZF 0603
MCK1608471YZF 0603
RV143
RV143
1 2
0_0402_5%
0_0402_5%
RV144
RV144
1 2
0_0402_5%
0_0402_5%
LV9
PX@LV9
PX@
1 2
LV10
PX@LV10
PX@
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
LV11
PX@LV11
PX@
1 2
75mA
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV40
2
PX@ CV40
PX@
CV43
PX@ CV43
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
125mA
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+DPLL_PVDD
1
1
CV42
CV41
2
2
PX@ CV42
PX@
PX@ CV41
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
+DPLL_VDDC
1
1
CV44
CV45
2
2
PX@ CV44
PX@
PX@ CV45
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
+MPV18
1
1
1
CV149
CV151
CV150
2
2
2
PX@ CV150
PX@
PX@ CV149
PX@
PX@ CV151
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
+DPLL_PVDD
+DPLL_PVDD
+DPLL_VDDC
+MPV18
+SPV18
+SPV10
RV141 0_0402_5%@ RV141 0_0402_5%@
RV148 0_0402_5%@ RV148 0_0402_5%@
AM32
AN31
AN32
AM10
AN10
12
AF30
12
AF31
+SPV18
1
1
1
CV153
CV152
CV154
2
2
2
PX@ CV153
PX@
PX@ CV152
PX@
PX@ CV154
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
+SPV10
1
1
1
CV166
CV168
CV169
2
2
2
PX@ CV168
PX@
PX@ CV166
PX@
PX@ CV169
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
XTALOUT XTALIN
27MHZ_16PF_X5H027000FG1H
27MHZ_16PF_X5H027000FG1H
CV49
PX@ CV49
PX@
18P_0402_50V8J
18P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ATI_SeymourXT_M2_PCIE/LVDS
ATI_SeymourXT_M2_PCIE/LVDS
ATI_SeymourXT_M2_PCIE/LVDS
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
13 56Monday, November 28, 2011
13 56Monday, November 28, 2011
13 56Monday, November 28, 2011
0.1
0.1
0.1
5
T53T53
T54T54
D D
VRAM_ID016
VRAM ID
C C
VRAM_ID116
VRAM_ID216
11/15 AMD suggest
RB751V_SOD323
RB751V_SOD323
DV1
@DV1
ACIN37,42,47
RV132 10K_0402_5%@R V132 10K_0402_5%@
11/16 add
Base on AMD Check list
GPIO_23_CLKREQB should be reserve
+3VGS
12
RV131
@ RV131
@
10K_0402_5%
10K_0402_5%
PEG_CLKREQ#
B B
+1.8VGS
+3VGS
A A
PX@
PX@
LV5
LV5
+1.8VGS
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
5
1
CV46
2
10U_0603_6.3V6M
10U_0603_6.3V6M
PX@ CV46
PX@
+TSVDD
1
1
CV48
CV47
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PX@ CV48
PX@
PX@ CV47
PX@
@
VDDCI_VID53
1 2
GPU_GPIO11
T60T60
1 2
12
12
1 2
1 2
RV66 1K_0402_5%PX@ RV66 1K_0402_5%PX@
GPU_VID1
GPU_GPIO13
GPU_VID3
GPU_VID2
GPIO22_ROMCSB
@
@
GPU_VID156
GPU_VID356
GPU_VID256
RV17 10K_0402_5%@RV17 10K_0402_5%@
GPU_VID456
PX@
PX@
RV25 499_0402_1%
RV25 499_0402_1%
PX@
PX@
RV26 249_0402_1%
RV26 249_0402_1%
12
CV39 0.1U_0402_16V7K
CV39 0.1U_0402_16V7K
PX@
PX@
RV149 5.11K_0402_5%
RV149 5.11K_0402_5%
T52T52
+3VGS
PX@ RV30
PX@
1 2
10K_0402_5%
10K_0402_5%
RV30
(1.8V@20mA TSVDD)
GENLK_CLK
GENLK_VSYNC
VGA_SMB_CK2
VGA_SMB_DA2
T66T66
T67T67
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
21
GPU_GPIO5
VDDCI_VID
GPU_GPIO8
GPU_GPIO9
GPIO_19_CTF
GPU_VID4
GPIO21_BBEN
PEG_CLKREQ#
+VREFG_GPU+VREFG_GPU
TESTEN
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
THERM_D+
THERM_D-
GPIO_28_FDO
4
4
AD29
AC29
AK21
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
AH23
AK26
AH20
AH18
AN16
AH17
AK17
AH15
AK16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AK13
AN13
AG32
AG33
AK19
AK20
AH26
AH24
AC30
AK24
AH13
AD28
AM23
AN23
AK23
AM24
AF29
AG29
AJ21
AW8
AW3
AW5
AW6
AJ23
AJ26
AJ17
AJ13
AJ16
AL16
AL13
AJ14
AJ19
AJ20
AJ24
AL21
AL24
AK32
AL31
AJ32
AJ33
AR8
AU8
AP8
AR3
AR1
AU1
AU3
AP6
AU5
AR6
AU6
AT7
AV7
AN7
AV9
AT9
MUTI GFX
MUTI GFX
GENLK_CLK
GENLK_VSYNC
SWAPLOCKA
SWAPLOCKB
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
SMBCLK
SMBus
SMBus
SMBDATA
SCL
I2C
I2C
SDA
GENERAL PURPOSE I/O
GENERAL PURPOSE I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21
GPIO_22_ROMCSB
CLKREQB
GPIO_29
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
CEC_1
HPD1
VREFG
BACO
BACO
PX_EN
DEBUG
DEBUG
TESTEN
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
THERMAL
THERMAL
DPLUS
DMINUS
GPIO_28_FDO
TS_A
TSVDD
TSVSS
UVG1B
UVG1B
PART 2 0F 9
PART 2 0F 9
DPA
DPA
DPB
DPB
DPC
DPC
DPD
DPD
DAC1
DAC1
MLPS
MLPS
DDC/AUX
DDC/AUX
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
TX4P_DPD1P
TX4M_DPD1N
TX5P_DPD0P
TX5M_DPD0N
AVSSN#1
AVSSN#2
AVSSN#3
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
NC_TSVSSQ
DDC1CLK
DDC1DATA
AUX1P
AUX1N
DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
DDCCLK_AUX6P
DDCDATA_AUX6N
DDCVGACLK
DDCVGADATA
3
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1
CV38
2
PX@ CV38
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
STRAPS
1 2
1 2
1 2
R1.0
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
(
1.8V@65mA AVDD)
1 2
LV2
PX@LV2
PX@
RV710K_0402_5% @ RV710K_0402_5% @
RV810K_0402_5% PX@ RV810K_0402_5% PX@
RV910K_0402_5% @ RV910K_0402_5% @
RV10100K_0402_5% @ RV10100K_0402_5% @
RV3110K_0402_5% @ RV3110K_0402_5% @
RV3210K_0402_5% @ RV3210K_0402_5% @
RV1110K_0402_5% @ RV1110K_0402_5% @
RV1210K_0402_5% @ RV1210K_0402_5% @
RV1310K_0402_5% PX@ RV1310K_0402_5% PX@
RV1510K_0402_5% @ RV1510K_0402_5% @
RV1610K_0402_5% @ RV1610K_0402_5% @
RV1810K_0402_5% @ RV1810K_0402_5% @
RV1910K_0402_5% @ RV1910K_0402_5% @
RV2010K_0402_5% @ RV2010K_0402_5% @
RV2110K_0402_5% @ RV2110K_0402_5% @
+1.8VGS
GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
RV9 SMT-->@
GPU_GPIO5
GPIO21_BBEN
GPIO22_ROMCSB
GPU_GPIO8
GPU_GPIO9
GPU_GPIO11
GPU_VID1
GPU_GPIO13
Update net name
GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS
GPIO26_TCK
1
CV33
2
PX@ CV33
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
1
CV34
2
PX@ CV34
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
AU24
AV23
AT25
AR24
AU26
AV25
AT27
AR26
AR30
AT29
AV31
AU30
AR32
AT31
AT33
AU32
AU14
AV13
AT15
AR14
AU16
AV15
AT17
AR16
AU20
AT19
AT21
AR20
AU22
AV21
AT23
AR22
AD39
AD37
AE36
AD35
AF37
AE38
AC36
AC38
AB34
AD34
AE34
AC33
AC34
V13
U13
AC31
AD30
AC32
AD32
AF32
AA29
AG21
RV14 499_0402_1%PX@RV14 499_0402_1%PX@
+VDD1DI
T61T61
T62T62
T63T63
T64T64
T65T65
1 2
+AVDD
R
G
B
NC#1
NC#2
NC#3
NC#4
NC#5
NC#6
NC#7
NC#8
NC#9
AF33
AM34
PS_0
AD31
PS_1
AG31
PS_2
AD33
PS_3
+3VGS
+3VGS
(1.8V@100mA VDD1DI)
1
1
CV36
CV37
2
2
PX@ CV36
PX@
PX@ CV37
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
RV142
@RV142
@
1 2
0_0402_5%
0_0402_5%
RV140
@RV140
@
12
0_0402_5%
0_0402_5%
For Chelsea non staff
2
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET
STRAPS
GPIO0TX_PWRS_ENB
DESCRIPTION OF DEFAULT SETT INGS <all internal PD>PIN
PCIE TRANSMITTER Power Saving Enable
GPIO1TX_DEEMPH_EN PCIE T RANSMITTER DE-EMPHASIS
RSVD
RSVD
RSVD
RSVD
BIOS_ROM_EN
GPIO2
GPIO8
H2SYNC
GPIO21
GPIO_22_ROMCSB
GPIO[13:11]ROMIDCFG(2:0)
Advertises PCIE speed when compliance test
Internal use only.This Pad has an internal PD and Must be 0V at reset.
The pad may be left unconnected.
ENABLE EXTERNAL BIOS ROM
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
GPIO13,12,11(config 2,1,0): internal PD.
a)If BIOS_ROM_EN=1,the config[2:0] defines the ROM type.
b)If BIOS_ROM_EN=0,the config[2:0] defines the primary aperture size.
VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS
GPIO9 VGA ENABLEDBIF_VGA DIS
RSVD
AMD RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET
GPIO21 GPIO2
GENERICC
HSYNCAUD[1]
VSYNCAUD[0]
H2SYNC GENERICC
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI
TX_PWRS_ENB GPIO0
+1.8VGS
1 2
LV1
PX@LV1
PX@
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1
CV35
2
PX@ CV35
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
PX@RV22
PX@
100K_0402_5%
100K_0402_5%
VGA_SMB_CK2
VGA_SMB_DA2
+3VGS
RV22
1 2
Internal VGA Thermal Sensor
RV23
PX@RV23
PX@
100K_0402_5%
100K_0402_5%
1 2
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
RECOMMEN DED SETTINGS
0= DO N OT INSTALL RESISTOR
1 = I NSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
0: 50% swing
1: Full swing
0: disable
1: enable
0: 2.5GT/s
1: 5GT/s
0: disable
1: enable
GPIO8
Transmitter Power Saving Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
PCI Express Transmitter De-emphasis Enable
GPIO1TX_DEEMPH_EN
0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)
+3VGS
2
61
5
QV1A
PX@QV1A
PX@
4
QV1B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1 2
RV24 0_0402_5%@ RV24 0_0402_5%@
1 2
RV27 0_0402_5%@ RV27 0_0402_5%@
3
PX@QV1B
PX@
EC_SMB_CK2 21,37,8
EC_SMB_DA2 21,37,8
RECOMMENDED
SETTINGS
X
X
0
0
0
0
X
XXX
Memory apertures
config[3:0]
128MB 000
256MB 001
64MB 010
0
0
0
11
Use Internal Thermal Sensor
AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
AM29
AN21
AM21
AK30
AK29
AJ30
AJ31
T69T69
T70T70
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
External VGA Thermal Sensor: No stuff
@
@
CV271 0.1U_0402_16V4Z
CV271 0.1U_0402_16V4Z
CV272
CV272
1 2
2200P_0402_50V7K
2200P_0402_50V7K
RV133 2.2K_0402_5%@ RV133 2.2K_0402_5%@
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Issued Date
Issued Date
Issued Date
THERM_D+
THERM_D-
+3VGS
+3VGS
12
@
@
12
Compal Secret Data
Compal Secret Data
Compal Secret Data
UV13
UV13
1
VDD
SCLK
2
D+
SDATA
3
ALERT#
D-
THERM#4GND
ADM1032ARMZ-2REEL_MSOP8
ADM1032ARMZ-2REEL_MSOP8
@
@
Deciphered Date
Deciphered Date
Deciphered Date
2
8
7
6
5
VGA_SMB_CK2
VGA_SMB_DA2
12
RV134 2.2K_0402_5%@ RV134 2.2K_0402_5%@
+3VGS
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ATI_SeymourXT_M2_Main_MSIC
ATI_SeymourXT_M2_Main_MSIC
ATI_SeymourXT_M2_Main_MSIC
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
14 56Monday, November 28, 2011
14 56Monday, November 28, 2011
14 56Monday, November 28, 2011
0.1
0.1
0.1
5
D D
G
PU_Reset
PWREN
1 2
RV145 0_0402_5%
PXS_PWREN25,27,48,52,53,56
RV145 0_0402_5%
PX@
PX@
PXS_PWREN=FCH GPIO192=PE_GPIO1
C C
4
3
2
1
11/10 follow Lotus
+3VALW
12
PX@
PX@
RV35
RV35
100K_0402_5%
100K_0402_5%
PXS_PWREN#_R
13
D
D
PXS_PWREN_RPXS_PWREN
2
G
G
QV8
QV8
2N7002K_SOT23-3
2N7002K_SOT23-3
PX@
PX@
S
S
+3.3VS TO +3.3VGS
+5VALW
PX@
PX@
RV36
RV36
20K_0402_5%
20K_0402_5%
PXS_PWREN_R
+3VS +3VGS
PX@
PX@
RV37
RV37
20K_0402_5%
20K_0402_5%
34
PX@
PX@
5
QV2B
QV2B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
J2
@J2
@
2 1
2MM
2MM
3 1
QV16
AP2301GN-HF_SOT23-3
AP2301GN-HF_SOT23-3
2
PX@
PX@
1
CV58
CV58
0.1U_0603_25V7K
0.1U_0603_25V7K
2
PX@QV16
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV56
CV56
PX@
PX@
2
PXS_PWREN#_R
1U_0603_10V6K
1U_0603_10V6K
1
CV57
CV57
PX@
PX@
2
@
@
QV7B
QV7B
1 2
12
RV34
470_0603_5%
470_0603_5%
34
5
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
0_0402_5%
0_0402_5%
RV38
@RV38
@
@RV34
@
dd +1.5VGS DC DC
10U_0603_6.3V6M
10U_0603_6.3V6M
CV59
CV59
PX@
PX@
+VSB
RV40
20K_0402_5%
20K_0402_5%
RV41
RV41
6
PX@
PX@
2
QV2A
QV2A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
A
+1.5V_PCIE
2 1
UV19
AO4430L_SO8
AO4430L_SO8
8
7
1
6
5
2
PX@RV40
PX@
1 2
PX@
PX@
200K_0402_1%
200K_0402_1%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2MM
2MM
PX@UV19
PX@
1 2
J9
@J9
@
4
RV43
RV43
0_0402_5%
0_0402_5%
@
@
2
+1.5VGS
1
2
3
1
CV62
0.1U_0603_25V7K
0.1U_0603_25V7K
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV60
CV60
PX@
PX@
2
PX@CV62
PX@
1
CV61
1U_0603_10V6K
1U_0603_10V6K
2
PXS_PWREN_R
12
PX@CV61
PX@
RV39
@RV39
@
470_0603_5%
470_0603_5%
6
@
@
2
QV7A
QV7A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
1 2
RV44 0_0402_5%@RV44 0_0402_5%@
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ATI_SeymourXT_M2_BACO POWER
ATI_SeymourXT_M2_BACO POWER
ATI_SeymourXT_M2_BACO POWER
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
15 56Monday, November 28, 2011
15 56Monday, November 28, 2011
15 56Monday, November 28, 2011
0.1
0.1
0.1
+1.5V_PCIE TO +1.5VGS
Del +1.8VGS DC DC
B B
PXS_PWREN#_R
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
5
UVG1C
UVG1C
PART 3 0F 9
PART 3 0F 9
GDDR5/DDR3
DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MVREFDA
MVREFSA
NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2
NC_MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
GDDR5/DDR3
MEMORY INTERFACE A
MEMORY INTERFACE A
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_BA2
MAA1_6/MAA_BA0
MAA1_7/MAA_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
EDCA0_0/QSA_0
EDCA0_1/QSA_1
EDCA0_2/QSA_2
EDCA0_3/QSA_3
EDCA1_0/QSA_4
EDCA1_1/QSA_5
EDCA1_2/QSA_6
EDCA1_3/QSA_7
DDBIA0_0/QSA_0B
DDBIA0_1/QSA_1B
DDBIA0_2/QSA_2B
DDBIA0_3/QSA_3B
DDBIA1_0/QSA_4B
DDBIA1_1/QSA_5B
DDBIA1_2/QSA_6B
DDBIA1_3/QSA_7B
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
CKEA0
CKEA1
WEA0B
WEA1B
MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15
MAA1_9/RSVD
G24
MAA0
J23
MAA1
H24
MAA2
J24
MAA3
H26
MAA4
J26
MAA5
H21
MAA6
G21
MAA7
H19
MAA8
H20
MAA9
L13
MAA10
G16
MAA11
J16
MAA12
H16
A_BA2
J17
A_BA0
H17
A_BA1
A32
DQMA#0
C32
DQMA#1
D23
DQMA#2
E22
DQMA#3
C14
DQMA#4
A14
DQMA#5
E10
DQMA#6
D9
DQMA#7
C34
QSA0
D29
QSA1
D25
QSA2
E20
QSA3
E16
QSA4
E12
QSA5
J10
QSA6
D7
QSA7
A34
QSA#0
E30
QSA#1
E26
QSA#2
C20
QSA#3
C16
QSA#4
C12
QSA#5
J11
QSA#6
F8
QSA#7
J21
ODTA0
G19
ODTA1
H27
CLKA0
G27
CLKA0#
J14
CLKA1
H14
CLKA1#
K23
RASA0#
K19
RASA1#
K20
CASA0#
K17
CASA1#
K24
CSA0#_0
K27
M13
CSA1#_0
K16
K21
CKEA0
J20
CKEA1
K26
WEA0#
L15
WEA1#
H23
MAA13
J19
M21
M20
C37
MDA0
C35
MDA1
A35
MDA2
E34
MDA3
G32
MDA4
D33
MDA5
F32
MDA6
E32
MDA7
D31
MDA8
F30
MDA9
C30
MDA10
A30
D D
C C
+1.5VGS
1 2
RV62 240_0402_1%@ RV62 240_0402_1%@
1 2
RV63 240_0402_1%@ RV63 240_0402_1%@
1 2
RV64 240_0402_1%@ RV64 240_0402_1%@
1 2
RV65 240_0402_1%@ RV65 240_0402_1%@
1 2
RV67 120_0402_5%RV67 120_0402_5%
1 2
RV68 120_0402_5%RV68 120_0402_5%
For Chelsea
RV60,RV61,RV62,RV63 non staff
RV65,RV66 from 240ohm
change to 120ohm
B B
MDA11
F28
MDA12
C28
MDA13
A28
MDA14
E28
MDA15
D27
MDA16
F26
MDA17
C26
MDA18
A26
MDA19
F24
MDA20
C24
MDA21
A24
MDA22
E24
MDA23
C22
MDA24
A22
MDA25
F22
MDA26
D21
MDA27
A20
MDA28
F20
MDA29
D19
MDA30
E18
MDA31
C18
MDA32
A18
MDA33
F18
MDA34
D17
MDA35
A16
MDA36
F16
MDA37
D15
MDA38
E14
MDA39
F14
MDA40
D13
MDA41
F12
MDA42
A12
MDA43
D11
MDA44
F10
MDA45
A10
MDA46
C10
MDA47
G13
MDA48
H13
MDA49
J13
MDA50
H11
MDA51
G10
MDA52
G8
MDA53
K9
MDA54
K10
MDA55
G9
MDA56
A8
MDA57
C8
MDA58
E8
MDA59
A6
MDA60
C6
MDA61
E6
MDA62
A5
MDA63
+VDD_MEM15_REFDA
+VDD_MEM15_REFSA
L18
L20
L27
N12
AG12
M12
M27
AH12
This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2
4
MAA[12..0]
A_BA[2..0]
MDA[0..63]
MAA[12..0] 19
A_BA[2..0] 19
MDA[0..63]19 MDB[0..63]20
+1.8VGS
1 2
RV56 10K_0402_5%X76@RV56 10K_0402_5%X76@
1 2
RV59 10K_0402_5%X76@RV59 10K_0402_5%X76@
1 2
RV57 10K_0402_5%X76@RV57 10K_0402_5%X76@
1 2
RV58 10K_0402_5%X76@RV58 10K_0402_5%X76@
1 2
RV60 10K_0402_5%X76@RV60 10K_0402_5%X76@
RV61 10K_0402_5%X76@RV61 10K_0402_5%X76@
128M16 (2G)
128M16 (2G)
64M16 (1G)
64M16 (1G)
1 2
Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
H5TQ2G63DFR-11C
Hynix 2GB
PN:SA00003YO70
K4W2G1646C-HC11
Samsung 2GB
PN:SA000047Q00
H5TQ1G63DFR-11C
Hynix 1GB
PN:SA000041S20
K4W1G1646G-BC11
Samsung 1GB
PN:SA00004GS20
ODTA0 19
ODTA1 19
CLKA0 19
CLKA0# 19
CLKA1 19
CLKA1# 19
RASA0# 19
RASA1# 19
CASA0# 19
CASA1# 19
CSA0#_0 19
DQMA#[7..0] 19
QSA[7..0] 19
QSA#[7..0] 19
CSA1#_0 19
CKEA0 19
CKEA1 19
WEA0# 19
WEA1# 19
MAA13 19
3
MDB[0..63]
MAB[12..0]
B_BA[2..0]
VRAM_ID0
VRAM_ID1
VRAM_ID2
RV56
RV58
1 0
RV57
RV56
0 0
RV59 RV58
RV59
1
0
1 1
RV57 RV60
0
1 1
MAB[12..0] 20
B_BA[2..0] 20
VRAM_ID0 14
VRAM_ID1 14
VRAM_ID2 14
RV61
0
RV61
RV60
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
+VDD_MEM15_REFDB
+VDD_MEM15_REFSB
AA12
2
UVG1D
UVG1D
PART 4 0F 9
PART 4 0F 9
GDDR5/DDR3
DQB0_0
DQB0_1
DQB0_2
DQB0_3
DQB0_4
DQB0_5
DQB0_6
DQB0_7
DQB0_8
DQB0_9
DQB0_10
DQB0_11
DQB0_12
DQB0_13
DQB0_14
DQB0_15
DQB0_16
DQB0_17
DQB0_18
DQB0_19
DQB0_20
DQB0_21
DQB0_22
DQB0_23
DQB0_24
DQB0_25
DQB0_26
DQB0_27
DQB0_28
DQB0_29
DQB0_30
DQB0_31
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MVREFDB
MVREFSB
GDDR5/DDR3
MEMORY INTERFACE B
MEMORY INTERFACE B
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
EDCB0_0/QSB_0
EDCB0_1/QSB_1
EDCB0_2/QSB_2
EDCB0_3/QSB_3
EDCB1_0/QSB_4
EDCB1_1/QSB_5
EDCB1_2/QSB_6
EDCB1_3/QSB_7
DDBIB0_0/QSB_0B
DDBIB0_1/QSB_1B
DDBIB0_2/QSB_2B
DDBIB0_3/QSB_3B
DDBIB1_0/QSB_4B
DDBIB1_1/QSB_5B
DDBIB1_2/QSB_6B
DDBIB1_3/QSB_7B
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
WEB0B
WEB1B
MAB0_8/MAB_13
MAB1_8/MAB_14
MAB0_9/MAB_15
MAB1_9/RSVD
DRAM_RST
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
H3
H1
T3
T5
AE4
AF5
AK6
AK5
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
T7
W7
L9
L8
AD8
AD7
T10
Y10
W10
AA10
P10
L10
AD10
AC10
U10
AA11
N10
AB11
T8
W8
U12
V12
AH11
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
ODTB0
ODTB1
CLKB0
CLKB0#
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0#_0
CSB1#_0
CKEB0
CKEB1
WEB0#
WEB1#
MAB13
DRAM_RST#_R
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
ODTB0 20
ODTB1 20
CLKB0 20
CLKB0# 20
CLKB1 20
CLKB1# 20
RASB0# 20
RASB1# 20
CASB0# 20
CASB1# 20
CSB0#_0 20
CSB1#_0 20
CKEB0 20
CKEB1 20
WEB0# 20
WEB1# 20
MAB13 20
1
DQMB#[7..0] 20
QSB[7..0] 20
QSB#[7..0] 20
+1.5VGS
+1.5VGS +1.5VGS
12
RV72
RV72
40.2_0402_1%
40.2_0402_1%
PX@
PX@
+VDD_MEM15_REFDA
12
12
CV172
CV172
0.1U_0402_16V7K
RV78
RV78
100_0402_1%
100_0402_1%
PX@
PX@
A A
0.1U_0402_16V7K
PX@
PX@
RV73
RV73
40.2_0402_1%
40.2_0402_1%
PX@
PX@
RV79
RV79
100_0402_1%
100_0402_1%
PX@
PX@
12
12
+VDD_MEM15_REFSA
12
CV173
CV173
0.1U_0402_16V7K
0.1U_0402_16V7K
PX@
PX@
DRAM_RST#19,20
4.7K_0402_5%
4.7K_0402_5%
1 2
RV76
RV76
51.1_0402_1%
51.1_0402_1%
PX@
PX@
RV71
RV71
@
@
120P_0402_50V9
120P_0402_50V9
12
+1.5VGS +1.5VGS
RV75
RV75
40.2_0402_1%
40.2_0402_1%
PX@
PX@
RV82
RV82
100_0402_1%
100_0402_1%
PX@
PX@
12
12
+VDD_MEM15_REFSB
12
CV176
CV176
0.1U_0402_16V7K
0.1U_0402_16V7K
PX@
PX@
PX@
PX@
CV174
CV174
12
1 2
RV77
RV77
10_0402_5%
10_0402_5%
PX@
PX@
DRAM_RST#_R
PX@
PX@
RV80
RV80
4.99K_0402_1%
4.99K_0402_1%
1 2
RV74
RV74
40.2_0402_1%
40.2_0402_1%
PX@
PX@
RV81
RV81
100_0402_1%
100_0402_1%
PX@
PX@
12
12
+VDD_MEM15_REFDB
12
CV175
CV175
0.1U_0402_16V7K
0.1U_0402_16V7K
PX@
PX@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ATI_SeymourXT_M2_MEM IF
ATI_SeymourXT_M2_MEM IF
ATI_SeymourXT_M2_MEM IF
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
16 56Monday, November 28, 2011
16 56Monday, November 28, 2011
16 56Monday, November 28, 2011
0.1
0.1
0.1
5
4
3
2
1
UVG1E
+1.5VGS
D D
VDDR1 CRB Design
0.1u 6 6
1u 10 5
10u 6 5
VDD_CT CRB Design
0.1u 1 1
1u 3 3
10u 1 1
VDDR3 CRB Design
C C
1u 3 3
10u 1 1
VDDR4 CRB Design
0.1u 1 1
1u 1 1
MPV18 CRB Design
0.1u 2 1
1u 2 1
10u 1 1
SPV18 CRB Design
0.1u 1 1
1u 1 1
10u 1 1
SPV10 CRB Design
0.1u 1 1
1u 1 1
10u 1 1
B B
1
CV87
CV87
+
+
@
@
2
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
1
1
CV93
CV82
2
2
PX@ CV93
PX@
PX@ CV82
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
For DDR3/GDDR5, MVDDQ = 1.5V
1
1
1
CV94
CV83
CV95
2
2
2
PX@ CV94
PX@
PX@ CV83
PX@
PX@ CV95
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.8VGS +VDDC_CT
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
+3VGS
1
1
1
CV141
CV140
CV139
2
2
2
PX@ CV141
PX@
PX@ CV140
PX@
PX@ CV139
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV96
CV84
2
PX@ CV96
PX@
PX@ CV84
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
PX@ LV7
PX@
1 2
1
CV142
2
PX@ CV142
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.8VGS
1
1
CV85
CV97
2
2
PX@ CV85
PX@
PX@ CV97
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
LV7
(1.8V@110mA VDD_CT)
CV122
PX@ CV122
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
PX@ LV8
PX@
1 2
BLM15BD121SN1D_0402
BLM15BD121SN1D_0402
1
1
CV86
2
2
PX@ CV86
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV123
2
2
PX@ CV123
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
LV8
CV98
2
2
PX@ CV99
PX@
PX@ CV98
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
CV125
CV124
2
2
PX@ CV125
PX@
PX@ CV124
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
CV102
CV101
CV100
2
2
2
PX@ CV102
PX@
PX@ CV101
PX@
PX@ CV100
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
CV126
2
PX@ CV126
PX@
1
1
1
1
1
CV99
+VDDR4
1
1
CV143
2
PX@ CV143
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV144
CV145
2
2
PX@ CV144
PX@
PX@ CV145
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
11/16 add
VCC_GPU_SENSE56
VDDCI_SEN53
VSS_GPU_SENSE56
VCC_GPU_SENSE & VSS_GPU_SENSE
needs to be routed as differential pair
A A
AD11
AG10
AF26
AF27
AG26
AG27
AF23
AF24
AG23
AG24
AD12
AF11
AF12
AF13
AF15
AG11
AG13
AG15
AF28
AG28
AH29
AC7
AF7
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
K11
K13
L12
L16
L21
L23
L26
M11
N11
R11
U11
Y11
J7
J9
K8
L7
P7
U7
Y7
MEM I/O
MEM I/O
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
LEVEL
LEVEL
TRANSLATION
TRANSLATION
VDD_CT
VDD_CT
VDD_CT
VDD_CT
I/O
I/O
VDDR3
VDDR3
VDDR3
VDDR3
DVP
DVP
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VOLTAGE
VOLTAGE
SENESE
SENESE
FB_VDDC
FB_VDDCI
FB_GND
UVG1E
PART 5 0F 9
PART 5 0F 9
PCIE
PCIE
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
AA31
NC_PCIE_VDDR
AA32
NC_PCIE_VDDR
AA33
NC_PCIE_VDDR
AA34
NC_PCIE_VDDR
W30
NC_PCIE_VDDR
Y31
NC_PCIE_VDDR
V28
NC_BIF_VDDC
W29
NC_BIF_VDDC
AB37
PCIE_PVDD
G30
PCIE_VDDC
G31
PCIE_VDDC
H29
PCIE_VDDC
H30
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
BIF_VDDC
BACO
BACO
BIF_VDDC
VDDC
CORE
CORE
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
ISOLATED
ISOLATED
VDDCI
CORE I/O
CORE I/O
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
J29
J30
L28
M28
N28
R28
T28
U28
N27
T27
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
1
CV89
2
PX@ CV89
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
11/16 add
(1.8V@504mA PCIE_VDDR)
(1.0V@1920mA PCIE_VDDC)
1
1
1
CV90
CV104
CV103
2
2
2
PX@ CV104
PX@
PX@ CV103
PX@
PX@ CV90
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+PCIE_VDDR
1
1
CV88
CV81
2
2
PX@ CV88
PX@
PX@ CV81
PX@
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
+0.935VGS
1
1
1
CV107
CV105
CV106
2
2
2
@ CV107
@
PX@ CV105
PX@
PX@ CV106
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
MBK1608121YZF_0603
MBK1608121YZF_0603
1
1
CV91
CV92
2
2
PX@ CV91
PX@
PX@ CV92
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.0VGS-->+0.935VGS
1
CV108
2
PX@ CV108
PX@
11/09 On power team page
(GDDR3/DDR3 1.12V@4A VDDCI)
(GDDR5 1.12V@16A VDDCI)
On power team page
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator
+1.8VGS
LV6
PX@ LV6
PX@
12
Change power rail same as PCIE_VDDC
Must be connected to PCIE_VDDC (0.935 V) on
"Heathrow"/"Chelsea" for both BACO and non-BACO designs
+0.935VGS
1
1
1
CV148
CV147
CV155
2
2
2
PX@ CV148
PX@
PX@ CV147
PX@
PX@ CV155
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
+VGA_CORE
+VDDCI
For Chelsea, Delete 2*1U
PCIE_VDDR CRB Design
0.1u 2 2
1u 1 1
10u 1 1
PCIE_VDDC CRB Design
1u 7 5 (1@)
10u 1 1
VDDC CRB Design
1u 30 25
10u 10 1
22u 0 1
VDDCI CR B Design
1u 10 9
10u 3 2
22u 0 1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ATI_SeymourXT_M2_Power
ATI_SeymourXT_M2_Power
ATI_SeymourXT_M2_Power
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
17 56Monday, November 28, 2011
17 56Monday, November 28, 2011
17 56Monday, November 28, 2011
0.1
0.1
0.1
5
D D
+1.8VGS
1 2
RV47
RV47
0_0603_5%
0_0603_5%
PX@
PX@
11/14 1% to 5%
C C
B B
A A
CV66
CV66
PX@
PX@
+DP_VDDR18
1
CV67
CV67
PX@
PX@
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PX@
PX@
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV68
CV68
CV75
PX@ CV75
PX@
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1
1
CV77
CV76
PX@ CV77
PX@
PX@ CV76
PX@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
CV65
CV65
PX@
PX@
10U_0603_6.3V6M
10U_0603_6.3V6M
CV63
CV63
CV64
CV64
2
2
PX@
PX@
PX@
PX@
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
RV51
PX@RV51
PX@
12
150_0402_1%
150_0402_1%
RV50
PX@RV50
PX@
12
150_0402_1%
150_0402_1%
RV55
PX@RV55
PX@
12
150_0402_1%
150_0402_1%
4
DP_VDDR DP_VDDC
DP_VDDR DP_VDDC
AN24
DP_VDDR
AP24
DP_VDDR
AP25
DP_VDDR
AP26
DP_VDDR
AU28
DP_VDDR
AV29
DP_VDDR
AP20
DP_VDDR
AP21
DP_VDDR
AP22
DP_VDDR
AP23
DP_VDDR
AU18
DP_VDDR
AV19
DP_VDDR
AH34
DP_VDDR
AJ34
DP_VDDR
AF34
DP_VDDR
AG34
DP_VDDR
AM37
DP_VDDR
AL38
DP_VDDR
CALIBRATION
CALIBRATION
AW28
DPAB_CALR
AW18
DPCD_CALR
AM39
DPEF_CALR
UVG1H
UVG1H
PART 8 0F 9
PART 8 0F 9
DP GND
DP GND
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
AP31
AP32
AN33
AP33
AP13
AT13
AP14
AP15
AL33
AM33
AK33
AK34
AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
+DP_VDDC
3
+0.935VGS
1 2
RV48
RV48
0_0603_5%
1
1
CV70
CV69
PX@ CV70
PX@
PX@ CV69
PX@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
CV74
PX@ CV74
PX@
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
CV80
PX@ CV80
PX@
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0_0603_5%
1
CV71
PX@
PX@
PX@ CV71
PX@
2
11/14 1% to 5%
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV72
CV73
PX@ CV72
PX@
PX@ CV73
PX@
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV78
CV79
PX@ CV78
PX@
PX@ CV79
PX@
2
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
2
AB39
1
UVG1F
UVG1F
PART 6 0F 9
PART 6 0F 9
PCIE_VSS
E39
PCIE_VSS
F34
PCIE_VSS
F39
PCIE_VSS
G33
PCIE_VSS
G34
PCIE_VSS
H31
PCIE_VSS
H34
PCIE_VSS
H39
PCIE_VSS
J31
PCIE_VSS
J34
PCIE_VSS
K31
PCIE_VSS
K34
PCIE_VSS
K39
PCIE_VSS
L31
PCIE_VSS
L34
PCIE_VSS
M34
PCIE_VSS
M39
PCIE_VSS
N31
PCIE_VSS
N34
PCIE_VSS
P31
PCIE_VSS
P34
PCIE_VSS
P39
PCIE_VSS
R34
PCIE_VSS
T31
PCIE_VSS
T34
PCIE_VSS
T39
PCIE_VSS
U31
PCIE_VSS
U34
PCIE_VSS
V34
PCIE_VSS
V39
PCIE_VSS
W31
PCIE_VSS
W34
PCIE_VSS
Y34
PCIE_VSS
Y39
PCIE_VSS
GND
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2160834000A10CHELSE_FCBGA962
2160834000A10CHELSE_FCBGA962
VSS_MECH
VSS_MECH
VSS_MECH
A3
GND
A37
GND
AA16
GND
AA18
GND
AA2
GND
AA21
GND
AA23
GND
AA26
GND
AA28
GND
AA6
GND
AB12
GND
AB15
GND
AB17
GND
AB20
GND
AB22
GND
AB24
GND
AB27
GND
AC11
GND
AC13
GND
AC16
GND
AC18
GND
AC2
GND
AC21
GND
AC23
GND
AC26
GND
AC28
GND
AC6
GND
AD15
GND
AD17
GND
AD20
GND
AD22
GND
AD24
GND
AD27
GND
AD9
GND
AE2
GND
AE6
GND
AF10
GND
AF16
GND
AF18
GND
AF21
GND
AG17
GND
AG2
GND
AG20
GND
AG22
GND
AG6
GND
AG9
GND
AH21
GND
AJ10
GND
AJ11
GND
AJ2
GND
AJ28
GND
AJ6
GND
AK11
GND
AK31
GND
AK7
GND
AL11
GND
AL14
GND
AL17
GND
AL2
GND
AL20
GND
AL23
GND
AL26
GND
AL32
GND
AL6
GND
AL8
GND
AM11
GND
AM31
GND
AM9
GND
AN11
GND
AN2
GND
AN30
GND
AN6
GND
AN8
GND
AP11
GND
AP7
GND
AP9
GND
AR5
GND
B11
GND
B13
GND
B15
GND
B17
GND
B19
GND
B21
GND
B23
GND
B25
GND
B27
GND
B29
GND
B31
GND
B33
GND
B7
GND
B9
GND
C1
GND
C39
GND
E35
GND
E5
GND
F11
GND
F13
GND
A39
AW1
AW39
MECH#1
MECH#2
MECH#3
T55 PADT55 PAD
T56 PADT56 PAD
T57 PADT57 PAD
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2013/06/30
2011/06/30 2013/06/30
2011/06/30 2013/06/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
ATI_SetmourXT_M2_PWR_GND
ATI_SetmourXT_M2_PWR_GND
ATI_SetmourXT_M2_PWR_GND
QCL51 LA-8712P
QCL51 LA-8712P
QCL51 LA-8712P
1
of
18 56Monday, November 28, 2011
18 56Monday, November 28, 2011
18 56Monday, November 28, 2011
0.1
0.1
0.1
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